Re: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table
Hi Prabin, Thank you for this patch. Please see my response inline marked [SAMI]. With that fixed, Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 4/3/24 18:33, Prabin CA wrote: The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU. Use the size specified by this PCD in the PPTT table of the RD-N2 platform. The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of the CPU's L2 cache and this allows changing the value of the L2 cache size depending the variant of the RD-N2 platform being build. RD-V2 platform is an example of such a variant. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 4 +++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc index 49a317a930e0..634edc2416c4 100644 --- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc +++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc @@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmPlatformTokenSpaceGuid.PcdClusterCount|16 +!ifdef $(PLAT_L2_CACHE_SIZE) + gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE) [SAMI] I think there is no need for PLAT_L2_CACHE_SIZE. The pcd can be set from the build command line using the something like '--pcd PcdL2CacheSize=0x1'. Can you check, please? Also update the commit message to document that the Pcd can be configured from the build command line and provide an example. [/SAMI] +!endif + # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index afc38385c051..fb5e6e72c9e8 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -64,6 +64,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdL2CacheSize gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc index b8cb04459be2..c37f04582f9c 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -21,6 +21,8 @@ #include "SgiAcpiHeader.h" #include "SgiPlatform.h" +#define L2_CACHE_SIZE FixedPcdGet32 (PcdL2CacheSize) + /** Define helper macro for populating processor core information. @param [in] PackageId Package instance number. @@ -81,7 +83,7 @@ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ 0,/* Next level of cache */ \ - SIZE_1MB, /* Size */ \ + L2_CACHE_SIZE,/* Size */ \ [SAMI] I think you can use FixedPcdGet32 (PcdL2CacheSize) in the above macro directly. [/SAMI] 2048, /* Num of sets */ \ 8,/* Associativity */ \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#119476): https://edk2.groups.io/g/devel/message/119476 Mute This Topic: https://groups.io/mt/105313652/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table
Reviewed-by: levi.yun From: devel@edk2.groups.io on behalf of Prabin CA via groups.io Sent: 03 April 2024 18:33 To: devel@edk2.groups.io Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham Subject: [edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU. Use the size specified by this PCD in the PPTT table of the RD-N2 platform. The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of the CPU's L2 cache and this allows changing the value of the L2 cache size depending the variant of the RD-N2 platform being build. RD-V2 platform is an example of such a variant. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 4 +++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc index 49a317a930e0..634edc2416c4 100644 --- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc +++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc @@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmPlatformTokenSpaceGuid.PcdClusterCount|16 +!ifdef $(PLAT_L2_CACHE_SIZE) + gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE) +!endif + # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index afc38385c051..fb5e6e72c9e8 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -64,6 +64,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdL2CacheSize gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc index b8cb04459be2..c37f04582f9c 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -21,6 +21,8 @@ #include "SgiAcpiHeader.h" #include "SgiPlatform.h" +#define L2_CACHE_SIZE FixedPcdGet32 (PcdL2CacheSize) + /** Define helper macro for populating processor core information. @param [in] PackageId Package instance number. @@ -81,7 +83,7 @@ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ 0,/* Next level of cache */ \ - SIZE_1MB, /* Size */ \ + L2_CACHE_SIZE,/* Size */ \ 2048, /* Num of sets */ \ 8,/* Associativity */ \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ -- 2.34.1 -=-=-=-=-=-= Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117380): https://edk2.groups.io/g/devel/message/117380 Mute This Topic: https://groups.io/mt/105313652/7717249 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [yeoreum@arm.com] -=-=-=-=-=-= IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117402): https://edk2.groups.io/g/devel/message/117402 Mute This Topic: https://groups.io/mt/105313652/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Use PCD value for L2 cache size in PPTT table
The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU. Use the size specified by this PCD in the PPTT table of the RD-N2 platform. The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of the CPU's L2 cache and this allows changing the value of the L2 cache size depending the variant of the RD-N2 platform being build. RD-V2 platform is an example of such a variant. Signed-off-by: Prabin CA --- Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 4 +++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc index 49a317a930e0..634edc2416c4 100644 --- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc +++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc @@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmPlatformTokenSpaceGuid.PcdClusterCount|16 +!ifdef $(PLAT_L2_CACHE_SIZE) + gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE) +!endif + # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index afc38385c051..fb5e6e72c9e8 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -64,6 +64,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdL2CacheSize gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc index b8cb04459be2..c37f04582f9c 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -21,6 +21,8 @@ #include "SgiAcpiHeader.h" #include "SgiPlatform.h" +#define L2_CACHE_SIZE FixedPcdGet32 (PcdL2CacheSize) + /** Define helper macro for populating processor core information. @param [in] PackageId Package instance number. @@ -81,7 +83,7 @@ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ 0,/* Next level of cache */ \ - SIZE_1MB, /* Size */ \ + L2_CACHE_SIZE,/* Size */ \ 2048, /* Num of sets */ \ 8,/* Associativity */ \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117380): https://edk2.groups.io/g/devel/message/117380 Mute This Topic: https://groups.io/mt/105313652/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
