Re: [edk2-devel] [PATCH v1 5/7] IntelFsp2WrapperPkg.dec: Remove duplicate LibraryClasses entry
Looks good to me! Thanks Michael! > -Original Message- > From: Michael Kubacki > Sent: Tuesday, September 6, 2022 9:35 PM > To: Chiu, Chasel ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Zeng, Star > > Subject: Re: [edk2-devel] [PATCH v1 5/7] IntelFsp2WrapperPkg.dec: Remove > duplicate LibraryClasses entry > > If that's your intention, yes the CI can allow that. I've pushed a v2 > candidate > branch of this series here with your review tags provided so far. > > https://github.com/makubacki/edk2/tree/add_missing_ci_yaml_intel_fsp_pkgs_ > v2 > > This patch (v1 5/7) is removed from that branch and the change to explicitly > allow this is in the following commit on that branch: > > https://github.com/makubacki/edk2/commit/b11dd1a4f59a62b90ed401b6b7ca > d889dd1e013f#diff- > ba7b110a0ec2f7f8fabc973b327ddb98a7d65b6a00b544a609a56593e6b87be3R8 > 0-R86 > > If that looks good, let me know and I can send the v2 series on the list after > leaving v1 open for a bit longer to collect other feedback and reviews. > > Thanks, > Michael > > On 9/6/2022 11:49 PM, Chiu, Chasel wrote: > > > > Hi Michael, > > > > In this case we intended to provide a single-small function in separate > > library > for platform customization so platforms do not have to override the whole main > library instance, and I think it is not valuable to create another H file to > hold this > single small library function. Is it possible to support such scenario in CI? > > > > Thanks, > > Chasel > > > > > >> -Original Message- > >> From: devel@edk2.groups.io On Behalf Of > >> Michael Kubacki > >> Sent: Tuesday, September 6, 2022 8:19 PM > >> To: devel@edk2.groups.io > >> Cc: Chiu, Chasel ; Desimone, Nathaniel L > >> ; Zeng, Star > >> Subject: [edk2-devel] [PATCH v1 5/7] IntelFsp2WrapperPkg.dec: Remove > >> duplicate LibraryClasses entry > >> > >> From: Michael Kubacki > >> > >> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 > >> > >> The last [LibraryClasses] entry for FspWrapperPlatformMultiPhaseLib > >> points to the same entry as FspWrapperMultiPhaseProcessLib. > >> > >> FspWrapperPlatformMultiPhaseHandler() is the only function > >> implemented in FspWrapperPlatformMultiPhaseLibNull.c and it is only > >> called (not implemented) in PeiFspWrapperMultiPhaseProcessLib.c, > >> so I'd assume: > >> > >> - Producing library: FspWrapperPlatformMultiPhaseLib > >> - Consuming library: FspWrapperMultiPhaseProcessLib > >> > >> But, the API descriptions do not provide any descriptive information: > >> > >> FspWrapperPlatformMultiPhaseHandler(): > >> > >> ``` > >> /** > >>FSP Wrapper Platform MultiPhase Handler > >> > >>@param[in] FspHobListPtr- Pointer to FSP HobList (valid > >> after FSP-M completed) > >>@param[in] ComponentIndex - FSP Component which executing > >> MultiPhase initialization. > >>@param[in] PhaseIndex - Indicates current execution phase > >> of FSP MultiPhase initialization. > >> > >>@retval EFI_STATUSAlways return EFI_SUCCESS > >> > >> **/ > >> ``` > >> > >> In any case, this removes the redundant header file entry so the > >> Library Class Check CI test can pass on the package. > >> > >> Cc: Chasel Chiu > >> Cc: Nate DeSimone > >> Cc: Star Zeng > >> Signed-off-by: Michael Kubacki > >> --- > >> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 4 > >> 1 file changed, 4 deletions(-) > >> > >> diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > >> b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > >> index 95ada0f7a151..c3bbc5c45517 100644 > >> --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > >> +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > >> @@ -32,10 +32,6 @@ [LibraryClasses] > >> ## @libraryclass Provide MultiPhase handling related functions. > >> > >> FspWrapperMultiPhaseProcessLib|Include/Library/FspWrapperMultiPhasePr > >> FspWrapperMultiPhaseProcessLib|oce > >> ssLib.h > >> > >> - ## @libraryclass Provide MultiPhase platform actions related > >> functions. > >> - > >> FspWrapperPlatfor
Re: [edk2-devel] [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning
Thanks for fixing this bug! Reviewed-by: Chasel Chiu > -Original Message- > From: S, Ashraf Ali > Sent: Thursday, March 9, 2023 8:06 AM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali ; Chiu, Chasel > ; > Desimone, Nathaniel L ; Chaganty, Rangasai > V ; Zeng, Star > Subject: [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning > > Function defination should match with declaration. > [-Wlto-type-mismatch] > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Sai Chaganty > Cc: Star Zeng > > Signed-off-by: Ashraf Ali S > --- > IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > index 795bb28c0f..a5a51c804c 100644 > --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > @@ -296,6 +296,7 @@ FspTempRamExitDone2 ( > > **/ > VOID > +EFIAPI > FspWaitForNotify ( >VOID >) > -- > 2.38.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100959): https://edk2.groups.io/g/devel/message/100959 Mute This Topic: https://groups.io/mt/97499164/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning
Fix patch has been pushed with commit message typo and format correction: https://github.com/tianocore/edk2/commit/8820767fb3bad09eeedecc3030d75c9e0cd4cab7 Thanks, Chasel > -Original Message- > From: S, Ashraf Ali > Sent: Thursday, March 9, 2023 8:06 AM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali ; Chiu, Chasel > ; > Desimone, Nathaniel L ; Chaganty, Rangasai > V ; Zeng, Star > Subject: [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning > > Function defination should match with declaration. > [-Wlto-type-mismatch] > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Sai Chaganty > Cc: Star Zeng > > Signed-off-by: Ashraf Ali S > --- > IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > index 795bb28c0f..a5a51c804c 100644 > --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > @@ -296,6 +296,7 @@ FspTempRamExitDone2 ( > > **/ > VOID > +EFIAPI > FspWaitForNotify ( >VOID >) > -- > 2.38.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100980): https://edk2.groups.io/g/devel/message/100980 Mute This Topic: https://groups.io/mt/97499164/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] IntelFsp2Pkg: Fix NASM X64 build warnings.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 2 +- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index cdebe90fab..4a5554dd5f 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -317,7 +317,7 @@ Done: xor eax, eax cmp edx, 0 jnz Exit2 - mov eax, 0800Eh + mov rax, 0800Eh Exit2: jmp rbp diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm index 71624a3aad..ec9140b73c 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -23,7 +23,7 @@ ASM_PFX(AsmGetFspInfoHeader): global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff): DD0x12345678 ; This value must be patched by the build script - and rax, 0x + mov eax, eax ; equal to and rax, 0x ret global ASM_PFX(AsmGetFspInfoHeaderNoStack) @@ -32,5 +32,5 @@ ASM_PFX(AsmGetFspInfoHeaderNoStack): lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] mov ecx, [rcx] sub rax, rcx - and rax, 0x + mov eax, eax ; equal to and rax, 0x jmp rdi -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101307): https://edk2.groups.io/g/devel/message/101307 Mute This Topic: https://groups.io/mt/97667924/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 4 ++-- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index cdebe90fab..56d6abaea6 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -317,7 +317,7 @@ Done: xor eax, eax cmp edx, 0 jnz Exit2 - mov eax, 0800Eh + mov rax, 0800Eh Exit2: jmp rbp @@ -464,7 +464,7 @@ ParamValid: ; Sec Platform Init ; CALL_YMM ASM_PFX(SecPlatformInit) - cmp eax, 0 + cmp rax, 0 jnz TempRamInitExit ; Load microcode diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm index 71624a3aad..ec9140b73c 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -23,7 +23,7 @@ ASM_PFX(AsmGetFspInfoHeader): global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff): DD0x12345678 ; This value must be patched by the build script - and rax, 0x + mov eax, eax ; equal to and rax, 0x ret global ASM_PFX(AsmGetFspInfoHeaderNoStack) @@ -32,5 +32,5 @@ ASM_PFX(AsmGetFspInfoHeaderNoStack): lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] mov ecx, [rcx] sub rax, rcx - and rax, 0x + mov eax, eax ; equal to and rax, 0x jmp rdi -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101356): https://edk2.groups.io/g/devel/message/101356 Mute This Topic: https://groups.io/mt/97678369/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3] IntelFsp2Pkg: Fix NASM X64 build warnings.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 18 +- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 2 -- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index cdebe90fab..b32fa32a89 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -135,9 +135,9 @@ ASM_PFX(LoadMicrocodeDefault): ; LOAD_RBP - cmprsp, 0 + test rsp, rsp jz ParamError - cmprcx, 0 + test rcx, rcx jz ParamError movrsp, rcx @@ -151,13 +151,13 @@ ASM_PFX(LoadMicrocodeDefault): ; UPD structure is compliant with FSP spec 2.4 movrax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] - cmprax, 0 + test rax, rax jz Exit2 cmprax, 0800h jl ParamError movrsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] - cmprsi, 0 + test rsi, rsi jnzCheckMainHeader ParamError: @@ -315,9 +315,9 @@ Done: mov ecx, MSR_IA32_BIOS_SIGN_ID rdmsr ; Get current microcode signature xor eax, eax - cmp edx, 0 + test edx, edx jnz Exit2 - mov eax, 0800Eh + mov rax, 0800Eh Exit2: jmp rbp @@ -464,7 +464,7 @@ ParamValid: ; Sec Platform Init ; CALL_YMM ASM_PFX(SecPlatformInit) - cmp eax, 0 + test rax, rax jnz TempRamInitExit ; Load microcode @@ -476,12 +476,12 @@ ParamValid: ; Call Sec CAR Init LOAD_RCX CALL_YMM ASM_PFX(SecCarInit) - cmp rax, 0 + test rax, rax jnz TempRamInitExit LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) - cmp rax, 0 + test rax, rax jnz TempRamInitExit LOAD_UCODE_STATUS rax ; Restore microcode status if no CAR init error from SLOT 0 in YMM9 (upper 128bits). diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm index 71624a3aad..32a60270b8 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -23,7 +23,6 @@ ASM_PFX(AsmGetFspInfoHeader): global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff): DD0x12345678 ; This value must be patched by the build script - and rax, 0x ret global ASM_PFX(AsmGetFspInfoHeaderNoStack) @@ -32,5 +31,4 @@ ASM_PFX(AsmGetFspInfoHeaderNoStack): lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] mov ecx, [rcx] sub rax, rcx - and rax, 0x jmp rdi -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101526): https://edk2.groups.io/g/devel/message/101526 Mute This Topic: https://groups.io/mt/97768328/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
Hello, Thanks for all the feedbacks and suggestions from everybody! I have sent V3 patch accordingly, please help to review again: https://edk2.groups.io/g/devel/message/101526 Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Tuesday, March 21, 2023 4:05 PM > To: Pedro Falcato ; devel@edk2.groups.io; Ni, Ray > > Cc: Chiu, Chasel ; Zeng, Star > Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build > warnings. > > Reviewing this code in more detail... I think clearing the upper 32-bits is a > bug. > These functions are supposed to return pointers, and since this is X64 code > those > pointers could be anywhere in address space. The fact that the FSP is in XIP > NEM, > which on current Intel platforms just happens to be mapped <4GB does not > mean that this pointer will always be 4GB. Therefore, I believe the correct > course of action is to delete the AND/MOV instructions in question. > > Thanks, > Nate > > -Original Message- > From: Pedro Falcato > Sent: Monday, March 20, 2023 12:31 AM > To: devel@edk2.groups.io; Ni, Ray > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build > warnings. > > On Mon, Mar 20, 2023 at 6:03 AM Ni, Ray wrote: > > > > > ASM_PFX(FspInfoHeaderRelativeOff): > > > > > > DD0x12345678 ; This value must be patched by the > > > build script > > > > > > - and rax, 0x > > > > > > + mov eax, eax ; equal to and rax, 0x > > > > Based on the discussion, we know "mov eax, eax" clears upper 32bits of RAX. > > But this code looks very confusing. Is there any other instruction that can > > do > the same thing? > > Hi Ray, > > Any instruction that writes to the lower 32-bits should zero the upper bits. > (Pardon my AT&T syntax, just reverse the operands for Intel syntax) > > and $0x,%eax gets you a 3 byte opcode (since imm8 is signed, you only > need 0xff as the immediate) and %eax, %eax gets you 2 bytes mov %eax, %eax > gets you 2 bytes > > even something silly like adding 0 to EAX should work. But in a pure > efficiency+size POV, the last 2 instructions should be optimal. > > -- > Pedro -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101527): https://edk2.groups.io/g/devel/message/101527 Mute This Topic: https://groups.io/mt/97678369/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: Fix NASM X64 build warnings.
Patch merged: https://github.com/tianocore/edk2/commit/f6bd3286edfbe5eb6b50946cc8bb89e5c60b9388 Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of Chiu, Chasel > Sent: Tuesday, March 21, 2023 5:14 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: Fix NASM X64 build warnings. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 > > Fix below warnings generated by NASM X64 build: > /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds > /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds > /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds > > Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. > > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 18 +- > IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 2 -- > 2 files changed, 9 insertions(+), 11 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index cdebe90fab..b32fa32a89 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -135,9 +135,9 @@ ASM_PFX(LoadMicrocodeDefault): > ;LOAD_RBP - cmprsp, 0+ test rsp, rspjz ParamError- > cmprcx, 0+ > test rcx, rcxjz ParamErrormovrsp, rcx @@ -151,13 +151,13 @@ > ASM_PFX(LoadMicrocodeDefault): > ; UPD structure is compliant with FSP spec 2.4movrax, qword [rsp > + > LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmprax, 0+ test rax, > raxjz Exit2cmprax, 0800hjl ParamError movrsi, > qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]- cmprsi, 0+ test rsi, > rsi > jnzCheckMainHeader ParamError:@@ -315,9 +315,9 @@ Done: > mov ecx, MSR_IA32_BIOS_SIGN_IDrdmsr ; Get > current > microcode signaturexor eax, eax- cmp edx, 0+ test edx, edx > jnz Exit2- > mov eax, 0800Eh+ mov rax, 0800Eh Exit2: > jmp rbp@@ -464,7 +464,7 @@ ParamValid: >; Sec Platform Init ; CALL_YMM ASM_PFX(SecPlatformInit)- cmp > eax, 0+ > test rax, rax jnz TempRamInitExit; Load microcode@@ -476,12 > +476,12 @@ ParamValid: >; Call Sec CAR Init LOAD_RCX CALL_YMM ASM_PFX(SecCarInit)- cmp > rax, > 0+ test rax, rax jnz TempRamInitExitLOAD_RCX CALL_YMM > ASM_PFX(EstablishStackFsp)- cmp rax, 0+ test rax, rax jnz > TempRamInitExitLOAD_UCODE_STATUS rax ; Restore microcode > status > if no CAR init error from SLOT 0 in YMM9 (upper 128bits).diff --git > a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > index 71624a3aad..32a60270b8 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > @@ -23,7 +23,6 @@ ASM_PFX(AsmGetFspInfoHeader): > global ASM_PFX(FspInfoHeaderRelativeOff) > ASM_PFX(FspInfoHeaderRelativeOff):DD0x12345678 ; This > value > must be patched by the build script- and rax, 0xret global > ASM_PFX(AsmGetFspInfoHeaderNoStack)@@ -32,5 +31,4 @@ > ASM_PFX(AsmGetFspInfoHeaderNoStack): > lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)]mov ecx, [rcx]sub > rax, > rcx- and rax, 0xjmp rdi-- > 2.35.0.windows.1 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#101526): https://edk2.groups.io/g/devel/message/101526 > Mute This Topic: https://groups.io/mt/97768328/1777047 > Group Owner: devel+ow...@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [chasel.c...@intel.com] -=- > =-=-=-=-= > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101859): https://edk2.groups.io/g/devel/message/101859 Mute This Topic: https://groups.io/mt/97768328/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 3/9] IntelFsp2Pkg: Add CpuPageTableLib required by DxeIpl in DSC
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Tan, Dun > Sent: Monday, March 27, 2023 7:43 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; Ni, Ray > > Subject: [PATCH 3/9] IntelFsp2Pkg: Add CpuPageTableLib required by DxeIpl in > DSC > > Add CpuPageTableLib instance required by DxeIpl in QemuFspPkg.dsc of > IntelFsp2Pkg. > > Signed-off-by: Dun Tan > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ray Ni > --- > IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > index 3155812118..52052692dd 100644 > --- a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > +++ b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > @@ -1,7 +1,7 @@ > ## @file > # FSP DSC build file for QEMU platform > # > -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2023, Intel Corporation. All rights > +reserved. > # > #This program and the accompanying materials > #are licensed and made available under the terms and conditions of the > BSD > License > @@ -114,6 +114,7 @@ >DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > > SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf > !endif > + > + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > > > > # > ### > -- > 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102000): https://edk2.groups.io/g/devel/message/102000 Mute This Topic: https://groups.io/mt/97897980/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 17 +++-- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 15 +-- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..606bf0b08b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault): cmpesp, 0 jz ParamError + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + + + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -450,7 +463,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -464,7 +477,7 @@ LoadMicrocode: wrmsr mov eax, 1 cpuid - + jmp Done ; if already one version microcode loaded, go to done Continue: jmp NextMicrocode diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index b32fa32a89..d9407b6fdb 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError movrsp, rcx + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -291,7 +302,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -305,7 +316,7 @@ LoadMicrocode: wrmsr mov eax, 1 cpuid - + jmp Done ; if already one version microcode loaded, go to done Continue: jmp NextMicrocode -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102059): https://edk2.groups.io/g/devel/message/102059 Mute This Topic: https://groups.io/mt/97912018/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 18 ++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 16 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..b902d017ee 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault): cmpesp, 0 jz ParamError + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + + + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -450,7 +463,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -465,9 +478,6 @@ LoadMicrocode: mov eax, 1 cpuid -Continue: - jmp NextMicrocode - Done: mov eax, 1 cpuid diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index b32fa32a89..2a23c33c9b 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError movrsp, rcx + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -291,7 +302,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -306,9 +317,6 @@ LoadMicrocode: mov eax, 1 cpuid -Continue: - jmp NextMicrocode - Done: mov eax, 1 cpuid -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102124): https://edk2.groups.io/g/devel/message/102124 Mute This Topic: https://groups.io/mt/97931383/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
Thanks for reviewing Ray! Please see my reply below inline. > -Original Message- > From: Ni, Ray > Sent: Wednesday, March 29, 2023 10:31 PM > To: Chiu, Chasel ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Zeng, Star > > Subject: RE: [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing > unnecessary delay. > > > > > + mov eax, 1 > > > > + cpuid > > > > + mov ecx, MSR_IA32_BIOS_SIGN_ID > > > > + rdmsr ; Get current microcode signature > > > > + xor eax, eax > > > > + test edx, edx > > > > + jnz Exit2 > > > 1. SDM uses following assembly to read current microcode signature. > > Example 10-9. Assembly Code to Retrieve the Update Revision MOV ECX, > 08BH ;IA32_BIOS_SIGN_ID XOR EAX, EAX ;clear EAX XOR EDX, EDX ;clear EDX > WRMSR ;Load 0 to MSR at 8BH MOV EAX, 1 Cupid MOV ECX, > 08BH ;IA32_BIOS_SIGN_ID rdmsr ;Read Model Specific Register > > > Comparing against yours, I think there are two diffs: > 1). you missed the write-zero to msr 8b I will add this back. > 2). you cleared RAX (I don't know why) This is for returning 0 (EFI_SUCCESS) to caller when microcode already loaded. > > And the existing code "LoadCheck:" actually contains exactly the SDM > recommended logic to get current microcode revision. > Why not use that directly? > > > - jeContinue > > > > + jeDone ; if already one version microcode loaded, go to done > > 2. You changed another behavior: from load all microcodes to load one only. > Can you separate it in a standalone patch and explain in commit? > I guess since the 1st check you added will skip loading when cpu microcode > revision is not 0, so the change here is to align with that behavior. This is another optimization for reducing unnecessary delay and I explained this in commit message (second line). Because that we usually only put one version microcode for one CPU in FV, if LoadMicrocodeDefault() already found one matching microcode and attempted to load it, then it should return with either SUCCESS or ERROR and no need to parse rest of the microcode files in FV. Commit message: FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102193): https://edk2.groups.io/g/devel/message/102193 Mute This Topic: https://groups.io/mt/97931383/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 26 ++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 ++ 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..79f2a20a2c 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): cmpesp, 0 jz ParamError + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -450,7 +466,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -465,10 +481,12 @@ LoadMicrocode: mov eax, 1 cpuid -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index b32fa32a89..3e40678f47 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError movrsp, rcx + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -291,7 +307,7 @@ LoadCheck: ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue + jeDone ; if already one version microcode loaded, go to done LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -306,10 +322,12 @@ LoadMicrocode: mov eax, 1 cpuid -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102334): https://edk2.groups.io/g/devel/message/102334 Mute This Topic: https://groups.io/mt/97984449/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 +++ IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 21 - 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index a222f2e376..016f943b43 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -157,6 +157,9 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; +; Save EBX to MM2 +; +movdmm2, ebx mov eax, 1 cpuid bt edx, 25 @@ -169,6 +172,10 @@ NextAddress: bt ecx, 19 jnc SseError %endif +; +; Restore EBX from MM2 +; +movdebx, mm2 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc index 38c807a311..002a5a1412 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -255,6 +255,10 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; +; Save RBX to R11 +; Save RCX to R10 +; +mov r11, rbx mov r10, rcx mov rax, 1 cpuid @@ -266,7 +270,12 @@ NextAddress: ; bt ecx, 19 jnc SseError -mov rcx, r10 +; +; Restore RBX from R11 +; Restore RCX from R10 +; +mov rbx, r11 +mov rcx, r10 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) @@ -284,6 +293,11 @@ NextAddress: %endmacro %macro ENABLE_AVX 0 +; +; Save RBX to R11 +; Save RCX to R10 +; +mov r11, rbx mov r10, rcx mov eax, 1 cpuid @@ -307,6 +321,11 @@ EnableAvx: xgetbv ; result in edx:eax or eax, 0006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state xsetbv +; +; Restore RBX from R11 +; Restore RCX from R10 +; +mov rbx, r11 mov rcx, r10 %endmacro -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102337): https://edk2.groups.io/g/devel/message/102337 Mute This Topic: https://groups.io/mt/97984838/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
Hi Ray, Yes, the step 3 will be redundant after adding the check for microcode already loaded scenario in earlier point. I will remove it and sent V4 patch. Thanks, Chasel > -Original Message- > From: Ni, Ray > Sent: Sunday, April 2, 2023 11:31 PM > To: devel@edk2.groups.io; Chiu, Chasel > Cc: Desimone, Nathaniel L ; Zeng, Star > > Subject: RE: [edk2-devel] [PATCH v3] IntelFsp2Pkg: LoadMicrocodeDefault() > causing unnecessary delay. > > Chasel, > With your changes, the flow is like: > 1. check revision of loaded microcode, go to Done if it's not zero 2. find > first > matching microcode 3. check revision of loaded microcode, go to Done if it > equals to the matching one 4. load the matching microcode > Done: return fail/success depending on whether the revision of loaded > microcode is zero > > I guess the step #3 is unnecessary because step #1 guarantees that step #3 > would not go to Done. > Can you please confirm? > > > > -----Original Message- > > From: devel@edk2.groups.io On Behalf Of Chiu, > > Chasel > > Sent: Saturday, April 1, 2023 6:57 AM > > To: devel@edk2.groups.io > > Cc: Chiu, Chasel ; Desimone, Nathaniel L > > ; Zeng, Star ; > > Ni, Ray > > Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: LoadMicrocodeDefault() > > causing unnecessary delay. > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 > > > > FSP should support the scenario that CPU microcode already loaded > > before calling LoadMicrocodeDefault(), in this case it should return > > directly without spending more time. > > Also the LoadMicrocodeDefault() should only attempt to load one > > version of the microcode for current CPU and return directly without > > parsing rest of the microcode in FV. > > > > Cc: Nate DeSimone > > Cc: Star Zeng > > Cc: Ray Ni > > Signed-off-by: Chasel Chiu > > --- > > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 26 > > ++ > > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 > > ++ > > 2 files changed, 44 insertions(+), 8 deletions(-) > > > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > index 2cff8b3643..79f2a20a2c 100644 > > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): > > cmpesp, 0 > > > > jz ParamError > > > > > > > > + ; > > > > + ; If microcode already loaded before this function, exit this > > + function with > > SUCCESS. > > > > + ; > > > > + mov ecx, MSR_IA32_BIOS_SIGN_ID > > > > + xor eax, eax ; Clear EAX > > > > + xor edx, edx ; Clear EDX > > > > + wrmsr; Load 0 to MSR at 8Bh > > > > + > > > > + mov eax, 1 > > > > + cpuid > > > > + mov ecx, MSR_IA32_BIOS_SIGN_ID > > > > + rdmsr ; Get current microcode signature > > > > + xor eax, eax > > > > + test edx, edx > > > > + jnz Exit2 > > > > + > > > > ; skip loading Microcode if the MicrocodeCodeSize is zero > > > > ; and report error if size is less than 2k > > > > ; first check UPD header revision > > > > @@ -450,7 +466,7 @@ LoadCheck: > > > > > > ; Verify this microcode update is not already loaded > > > > cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx > > > > - jeContinue > > > > + jeDone ; if already one version microcode loaded, go to done > > > > > > > > LoadMicrocode: > > > > ; EAX contains the linear address of the start of the Update Data > > > > @@ -465,10 +481,12 @@ LoadMicrocode: > > mov eax, 1 > > > > cpuid > > > > > > > > -Continue: > > > > - jmp NextMicrocode > > > > - > > > > Done: > > > > + mov ecx, MSR_IA32_BIOS_SIGN_ID > > > > + xor eax, eax ; Clear EAX > > > > + xor edx, edx ; Clear EDX > > > > + wrmsr; Load 0 to MSR at 8Bh > > > > + > > > > mov eax, 1 > > > > cpuid > > > > mov ecx, MSR_IA32_BIOS_SIGN_ID
[edk2-devel] [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu Reviewed-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 46 -- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 45 - 2 files changed, 48 insertions(+), 43 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..900126b93b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): cmpesp, 0 jz ParamError + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -330,7 +346,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] jne LoadMicrocodeDefault1 test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match LoadMicrocodeDefault1: ; Check if extended header exists @@ -363,7 +379,7 @@ CheckExtSig: cmp dword [edi + ExtSig.ExtSigProcessor], ebx jne LoadMicrocodeDefault2 test dword [edi + ExtSig.ExtSigFlags], edx - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match LoadMicrocodeDefault2: ; Check if any more extended signatures exist add edi, ExtSig.size @@ -435,23 +451,7 @@ LoadMicrocodeDefault4: ; Is valid Microcode start point ? cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0h jzDone - -LoadCheck: - ; Get the revision of the current microcode update loaded - mov ecx, MSR_IA32_BIOS_SIGN_ID - xor eax, eax ; Clear EAX - xor edx, edx ; Clear EDX - wrmsr; Load 0 to MSR at 8Bh - - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr; Get current microcode signature - - ; Verify this microcode update is not already loaded - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - jeContinue - + jmp CheckMainHeader LoadMicrocode: ; EAX contains the linear address of the start of the Update Data ; EDX contains zero @@ -465,10 +465,12 @@ LoadMicrocode: mov eax, 1 cpuid -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index b32fa32a89..698bb063a7 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError movrsp, rcx + ; + ; If microcode already loaded before this function, exit this function with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -198,7 +214,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] jne LoadMicrocodeDefault1 test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] - jnz LoadCheck ; Jif signatur
Re: [edk2-devel] [PATCH 2/5] MinPlatformPkg: Delete UefiCpuLib usage
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Liu, Zhiguang > Sent: Tuesday, April 4, 2023 12:56 AM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH 2/5] MinPlatformPkg: Delete UefiCpuLib usage > > Delete UefiCpuLib usage because UefiCpuPkg/UefiCpuLib is merged to > MdePkg/CpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > Signed-off-by: Zhiguang Liu > --- > Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > index 3749199da7..5ce21cf31e 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > @@ -1,7 +1,7 @@ > ## @file > # Platform description. > # > -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2023, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -60,7 +60,6 @@ >PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf >DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf > > DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib. > inf > - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf > ># ># Framework > -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102499): https://edk2.groups.io/g/devel/message/102499 Mute This Topic: https://groups.io/mt/9809/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.
Patch merged: https://github.com/tianocore/edk2/commit/af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546 Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of Chiu, Chasel > Sent: Friday, March 31, 2023 4:16 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: TempRamInit API should preserve > EBX/RBX register. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 > > FSP specification defines the TempRamInit API preserved register list which > including EBX/RBX, however current implementation unexpectedly overriding > EBX/RBX register that should be fixed. > > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 +++ > IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 21 > - > 2 files changed, 27 insertions(+), 1 deletion(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index a222f2e376..016f943b43 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -157,6 +157,9 @@ NextAddress: > ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test >; > whether the processor supports SSE instruction. ;+; > Save EBX to > MM2+;+movdmm2, ebx mov eax, 1 > cpuid > bt edx, 25@@ -169,6 +172,10 @@ NextAddress: > bt ecx, 19 jnc SseError %endif+ > ;+; Restore EBX > from MM2+;+movdebx, mm2 ; > ; Set OSFXSR bit (bit > #9) & OSXMMEXCPT bit (bit #10)diff --git > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > index 38c807a311..002a5a1412 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -255,6 +255,10 @@ NextAddress: > ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test >; > whether the processor supports SSE instruction. ;+; > Save RBX to > R11+; Save RCX to R10+;+mov r11, rbx >mov r10, > rcx mov rax, 1 cpuid@@ -266,7 +270,12 @@ > NextAddress: > ; bt ecx, 19 jnc SseError- > mov rcx, > r10+;+; Restore RBX from R11+; Restore > RCX from > R10+;+mov rbx, r11+mov rcx, r10 >; ; Set > OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)@@ -284,6 +293,11 @@ > NextAddress: > %endmacro %macro ENABLE_AVX 0+;+; > Save RBX to > R11+; Save RCX to R10+;+mov r11, rbx >mov r10, > rcx mov eax, 1 cpuid@@ -307,6 +321,11 @@ > EnableAvx: > xgetbv ; result in edx:eax or > eax, 0006h ; Set XCR0 > bit #1 and bit #2 to enable SSE state and AVX state xsetbv+ > ;+; > Restore RBX from R11+; Restore RCX from R10+;+ > mov rbx, > r11 mov rcx, r10 %endmacro -- > 2.35.0.windows.1 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#102337): https://edk2.groups.io/g/devel/message/102337 > Mute This Topic: https://groups.io/mt/97984838/1777047 > Group Owner: devel+ow...@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [chasel.c...@intel.com] -=- > =-=-=-=-= > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102507): https://edk2.groups.io/g/devel/message/102507 Mute This Topic: https://groups.io/mt/97984838/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
Patch merged: https://github.com/tianocore/edk2/commit/7df447930c42addaf2cc0d32916141d95ded677e Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of Chiu, Chasel > Sent: Monday, April 3, 2023 11:34 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; Ni, Ray > ; Kuo, Ted > Subject: [edk2-devel] [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing > unnecessary delay. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 > > FSP should support the scenario that CPU microcode already loaded before > calling LoadMicrocodeDefault(), in this case it should return directly without > spending more time. > Also the LoadMicrocodeDefault() should only attempt to load one version of the > microcode for current CPU and return directly without parsing rest of the > microcode in FV. > > This patch also removed unnecessary LoadCheck code after supporting CPU > microcode already loaded scenario. > > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ray Ni > Signed-off-by: Chasel Chiu > Reviewed-by: Ted Kuo > --- > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 46 > -- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 45 > - > 2 files changed, 48 insertions(+), 43 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > index 2cff8b3643..900126b93b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): > cmpesp, 0jz ParamError + ;+ ; If microcode already loaded > before this > function, exit this function with SUCCESS.+ ;+ mov ecx, > MSR_IA32_BIOS_SIGN_ID+ xor eax, eax ; Clear EAX+ xor > edx, > edx ; Clear EDX+ wrmsr; Load 0 to MSR > at 8Bh++ mov > eax, 1+ cpuid+ mov ecx, MSR_IA32_BIOS_SIGN_ID+ rdmsr >; > Get current microcode signature+ xor eax, eax+ test edx, edx+ jnz > Exit2+; > skip loading Microcode if the MicrocodeCodeSize is zero; and report error > if > size is less than 2k; first check UPD header revision@@ -330,7 +346,7 @@ > CheckMainHeader: > cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]jne > LoadMicrocodeDefault1test edx, dword [esi + > MicrocodeHdr.MicrocodeHdrFlags ]- jnz LoadCheck ; Jif signature and > platform ID match+ jnz LoadMicrocode ; Jif signature and platform ID > match > LoadMicrocodeDefault1:; Check if extended header exists@@ -363,7 +379,7 > @@ CheckExtSig: > cmp dword [edi + ExtSig.ExtSigProcessor], ebxjne > LoadMicrocodeDefault2test dword [edi + ExtSig.ExtSigFlags], edx- jnz > LoadCheck ; Jif signature and platform ID match+ jnz LoadMicrocode >; Jif > signature and platform ID match LoadMicrocodeDefault2:; Check if any more > extended signatures existadd edi, ExtSig.size@@ -435,23 +451,7 @@ > LoadMicrocodeDefault4: > ; Is valid Microcode start point ?cmp dword [esi + > MicrocodeHdr.MicrocodeHdrVersion], 0hjzDone--LoadCheck:- ; > Get > the revision of the current microcode update loaded- mov ecx, > MSR_IA32_BIOS_SIGN_ID- xor eax, eax ; Clear EAX- xor > edx, > edx ; Clear EDX- wrmsr; Load 0 to MSR > at 8Bh-- mov eax, > 1- cpuid- mov ecx, MSR_IA32_BIOS_SIGN_ID- rdmsr > ; Get > current microcode signature-- ; Verify this microcode update is not already > loaded- cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx- je > Continue-+ jmp CheckMainHeader LoadMicrocode:; EAX contains the linear > address of the start of the Update Data; EDX contains zero@@ -465,10 > +465,12 @@ LoadMicrocode: > mov eax, 1cpuid -Continue:- jmp NextMicrocode- Done:+ mov > ecx, > MSR_IA32_BIOS_SIGN_ID+ xor eax, eax ; Clear EAX+ xor > edx, > edx ; Clear EDX+ wrmsr; Load 0 to MSR > at 8Bh+mov > eax, 1cpuidmov ecx, MSR_IA32_BIOS_SIGN_IDdiff --git > a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index b32fa32a89..698bb063a7 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): > jz ParamErrormovrsp, rcx + ;+
Re: [edk2-devel] [PATCH v1] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from board package.
Hi Aryeh, Please see below inline for comments. Thanks, Chasel > -Original Message- > From: Chen, Aryeh > Sent: Wednesday, April 12, 2023 4:20 AM > To: devel@edk2.groups.io > Cc: Chen, Aryeh ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH v1] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR > REVISION to update FADT entries from board package. > > From: Aryeh Chen > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4409 > > Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from > board package. > > Signed-off-by: Aryeh Chen > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 2 ++ > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 2 ++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 ++ > 3 files changed, 6 insertions(+) > > diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > index 6e57b638e0..a844d9c445 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > @@ -1096,6 +1096,7 @@ PlatformUpdateTables ( >case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: > FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table; + > FadtHeader->Header.Revision = PcdGet8 (PcdFadtRevision); > FadtHeader->PreferredPmProfile= PcdGet8 > (PcdFadtPreferredPmProfile); FadtHeader->IaPcBootArch > = > PcdGet16 (PcdFadtIaPcBootArch); FadtHeader->Flags > = > PcdGet32 (PcdFadtFlags);@@ -1113,6 +1114,7 @@ PlatformUpdateTables ( > FadtHeader->Gpe1Blk = PcdGet16 > (PcdAcpiGpe1BlockAddress); > FadtHeader->Gpe1BlkLen= PcdGet8 > (PcdAcpiGpe1BlockLength); > FadtHeader->Gpe1Base = PcdGet8 (PcdAcpiGpe1Base);+ > FadtHeader->MinorVersion = PcdGet8 > (PcdFadtMinorRevision); > FadtHeader->XPm1aEvtBlk.Address = PcdGet16 > (PcdAcpiPm1AEventBlockAddress); FadtHeader->XPm1bEvtBlk.Address > = PcdGet16 (PcdAcpiPm1BEventBlockAddress);diff --git > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > index 451034fb8a..9d83cbf73c 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > @@ -67,6 +67,8 @@ >gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtRevision+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorRevision > gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddressdiff --git > a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index e6f714b181..6e44287256 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -346,6 +346,8 @@ > > gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x9 > 025 > gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900 > 00026 > gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x86A5|UINT32|0x9 > 027+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtRevision|0x06|UINT8|0x9030+ To be more align with specification, it looks to me better naming is PcdFadtMajorVersion > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorRevision|0x03|UINT8|0x9 To be more align with specification, it looks to me better naming is PcdFadtMinorVersion > 031 [PcdsFixedAtBuild] -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102892): https://edk2.groups.io/g/devel/message/102892 Mute This Topic: https://groups.io/mt/98216889/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from board package.
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Chen, Aryeh > Sent: Wednesday, April 12, 2023 9:27 AM > To: devel@edk2.groups.io > Cc: Chen, Aryeh ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH v2] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR > REVISION to update FADT entries from board package. > > From: Aryeh Chen > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4409 > > Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from > board package. > > Signed-off-by: Aryeh Chen > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 2 ++ > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 2 ++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 ++ > 3 files changed, 6 insertions(+) > > diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > index 6e57b638e0..e967031a3b 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > @@ -1096,6 +1096,7 @@ PlatformUpdateTables ( >case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: > FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table; + > FadtHeader->Header.Revision = PcdGet8 (PcdFadtMajorVersion); > FadtHeader->PreferredPmProfile= PcdGet8 > (PcdFadtPreferredPmProfile); FadtHeader->IaPcBootArch > = > PcdGet16 (PcdFadtIaPcBootArch); FadtHeader->Flags > = > PcdGet32 (PcdFadtFlags);@@ -1113,6 +1114,7 @@ PlatformUpdateTables ( > FadtHeader->Gpe1Blk = PcdGet16 > (PcdAcpiGpe1BlockAddress); > FadtHeader->Gpe1BlkLen= PcdGet8 > (PcdAcpiGpe1BlockLength); > FadtHeader->Gpe1Base = PcdGet8 (PcdAcpiGpe1Base);+ > FadtHeader->MinorVersion = PcdGet8 (PcdFadtMinorVersion); > FadtHeader->XPm1aEvtBlk.Address = PcdGet16 > (PcdAcpiPm1AEventBlockAddress); FadtHeader->XPm1bEvtBlk.Address > = PcdGet16 (PcdAcpiPm1BEventBlockAddress);diff --git > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > index 451034fb8a..694492112b 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > @@ -67,6 +67,8 @@ >gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMajorVersion+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorVersion > gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddressdiff --git > a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index e6f714b181..784abb828e 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -346,6 +346,8 @@ > > gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x9 > 025 > gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900 > 00026 > gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x86A5|UINT32|0x9 > 027+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMajorVersion|0x06|UINT8|0x90 > 30+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorVersion|0x03|UINT8|0x90 > 31 [PcdsFixedAtBuild] -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102895): https://edk2.groups.io/g/devel/message/102895 Mute This Topic: https://groups.io/mt/98223011/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412
Hi Chinni,
Please help to correct patch format and make sure it can pass verification by
BaseTools/Scripts/PatchCheck.py
Thanks,
Chasel
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Friday, April 14, 2023 1:34 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; Kuo, Ted
> ; Duggapu, Chinni B
> Subject: [PATCH v2] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file
> directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412
>
> After shrinking the FSP (FV) component using FMMT, Image size in FSP info
> header is not in sync with the FV length in FV header.
> This enhancement helps to patch the FSP image size offset with correct length
> &
> can be used to patch any offset directly on the FSP Component Fd .
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ted Kuo
> Signed-off-by: Duggapu Chinni B
> ---
> IntelFsp2Pkg/Tools/PatchFv.py | 14 -
> .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
> 2 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
> index eb130049b5..156c937abe 100644
> --- a/IntelFsp2Pkg/Tools/PatchFv.py
> +++ b/IntelFsp2Pkg/Tools/PatchFv.py
> @@ -165,6 +165,17 @@ class Symbols:
> if not os.path.isdir(fvDir): raise Exception ("'%s' is
> not a valid
> directory!" % fvDir) +#+# if user provided fd name as a
> input, skip rest of
> the flow to+# patch fd directly+# +fdFile =
> os.path.join(fvDir,fvNames + ".fd")+if os.path.exists(fdFile):+
> print("Tool identified Fd file as a input to patch '%s'" %fdFile)+
> self.fdFile =
> fdFile+self.fdSize = os.path.getsize(fdFile)+return
> 0+ # # If
> the Guid.xref is not existing in fvDir, then raise an exception #@@
> -848,8
> +859,9 @@ class Symbols:
> # Print out the usage # def Usage():-print ("PatchFv Version 0.50")+
> print
> ("PatchFv Version 0.60") print ("Usage: \n\tPatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")+print
> ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"") def main(): #diff
> --git
> a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> index 5f1031e729..33bba38a3f 100644
> --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> @@ -1,6 +1,7 @@
> #Name **_PatchFv.py_** - The python script that patches the firmware
> volumes (**FV**) with in the flash device (**FD**) file post FSP build.+From
> version 0.60, script is capable of patching flash device (**FD**) directly.
> #Synopsis @@ -10,6 +11,12 @@ PatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch ["Offset, Value"]+
>| ["Offset, Value, $Command"]+ | ["Offset, Value, $Command,
> @Comment"]+ ```+```+PatchFv FdFileDir FdFileName ["Offset, Value"]++ |
> ["Offset, Value, @Comment"]++ | ["Offset, Value, $Command"]++ | ["Offset,
> Value, $Command, @Comment"]++``` #Description The **_PatchFv.py_** tool
> allows the developer to fix up FD images to follow the@@ -102,6 +109,19 @@
> ModuleGuid:Offset
>< > Convert absolute address into an image offset (expr & FSP_SIZE)
> ```+From version 0.60 tool allows to pass flash device file path as Argument 1
> and +flash device name as Argument 2 and rules for passing offset & value are
> same+as explained in the previous sections.++Example usage:+Argument
> 1+```+ YouPlatformFspBinPkg\+```+Argument 2+```+ Fsp_Rebased_T+```
> ###Special Commands: Special commands must use the **$** symbol as a
> prefix to the command itself.--
> 2.39.1.windows.1
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Re: [edk2-devel] [PATCH v2] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from board package.
Patch merged: https://github.com/tianocore/edk2-platforms/commit/3b7f82b61b552f5bdd415f1bf4ba2866a09ceac0 Thanks, Chasel > -Original Message- > From: Chen, Aryeh > Sent: Wednesday, April 12, 2023 9:27 AM > To: devel@edk2.groups.io > Cc: Chen, Aryeh ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH v2] MinPlatformPkg: Add Pcd for FADT REVISION and MINOR > REVISION to update FADT entries from board package. > > From: Aryeh Chen > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4409 > > Add Pcd for FADT REVISION and MINOR REVISION to update FADT entries from > board package. > > Signed-off-by: Aryeh Chen > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 2 ++ > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 2 ++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 ++ > 3 files changed, 6 insertions(+) > > diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > index 6e57b638e0..e967031a3b 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > @@ -1096,6 +1096,7 @@ PlatformUpdateTables ( >case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: > FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table; + > FadtHeader->Header.Revision = PcdGet8 (PcdFadtMajorVersion); > FadtHeader->PreferredPmProfile= PcdGet8 > (PcdFadtPreferredPmProfile); FadtHeader->IaPcBootArch > = > PcdGet16 (PcdFadtIaPcBootArch); FadtHeader->Flags > = > PcdGet32 (PcdFadtFlags);@@ -1113,6 +1114,7 @@ PlatformUpdateTables ( > FadtHeader->Gpe1Blk = PcdGet16 > (PcdAcpiGpe1BlockAddress); > FadtHeader->Gpe1BlkLen= PcdGet8 > (PcdAcpiGpe1BlockLength); > FadtHeader->Gpe1Base = PcdGet8 (PcdAcpiGpe1Base);+ > FadtHeader->MinorVersion = PcdGet8 (PcdFadtMinorVersion); > FadtHeader->XPm1aEvtBlk.Address = PcdGet16 > (PcdAcpiPm1AEventBlockAddress); FadtHeader->XPm1bEvtBlk.Address > = PcdGet16 (PcdAcpiPm1BEventBlockAddress);diff --git > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > index 451034fb8a..694492112b 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > @@ -67,6 +67,8 @@ >gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset > gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMajorVersion+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorVersion > gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddressdiff --git > a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index e6f714b181..784abb828e 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -346,6 +346,8 @@ > > gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x9 > 025 > gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900 > 00026 > gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x86A5|UINT32|0x9 > 027+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMajorVersion|0x06|UINT8|0x90 > 30+ > gMinPlatformPkgTokenSpaceGuid.PcdFadtMinorVersion|0x03|UINT8|0x90 > 31 [PcdsFixedAtBuild] -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103012): https://edk2.groups.io/g/devel/message/103012 Mute This Topic: https://groups.io/mt/98223011/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly
Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Sunday, April 16, 2023 9:23 PM
> To: devel@edk2.groups.io
> Cc: Duggapu, Chinni B ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Zeng, Star ; Kuo, Ted
>
> Subject: [PATCH v3] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file
> directly
>
> From: "Duggapu, Chinni B"
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4412
>
> After shrinking the FSP (FV) component using FMMT, Image size in FSP info
> header is not in sync with the FV length in FV header.
> This enhancement helps to patch the FSP image size offset with correct length
> &
> can be used to patch any offset directly on the FSP Component Fd.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ted Kuo
> Signed-off-by: Duggapu Chinni B
> ---
> IntelFsp2Pkg/Tools/PatchFv.py | 14 -
> .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
> 2 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
> index eb130049b5..73ab877c71 100644
> --- a/IntelFsp2Pkg/Tools/PatchFv.py
> +++ b/IntelFsp2Pkg/Tools/PatchFv.py
> @@ -165,6 +165,17 @@ class Symbols:
> if not os.path.isdir(fvDir): raise Exception ("'%s' is
> not a valid
> directory!" % fvDir) +#+# if user provided fd name as a
> input, skip rest of
> the flow to+# patch fd directly+#+fdFile =
> os.path.join(fvDir,fvNames + ".fd")+if os.path.exists(fdFile):+
> print("Tool identified Fd file as a input to patch '%s'" %fdFile)+
> self.fdFile =
> fdFile+self.fdSize = os.path.getsize(fdFile)+return
> 0+ # # If
> the Guid.xref is not existing in fvDir, then raise an exception #@@
> -848,8
> +859,9 @@ class Symbols:
> # Print out the usage # def Usage():-print ("PatchFv Version 0.50")+
> print
> ("PatchFv Version 0.60") print ("Usage: \n\tPatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")+print
> ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"") def main(): #diff
> --git
> a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> index 5f1031e729..f28eedf625 100644
> --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> @@ -1,6 +1,7 @@
> #Name **_PatchFv.py_** - The python script that patches the firmware
> volumes (**FV**) with in the flash device (**FD**) file post FSP build.+From
> version 0.60, script is capable of patching flash device (**FD**) directly.
> #Synopsis @@ -10,6 +11,12 @@ PatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch ["Offset, Value"]+
>| ["Offset, Value, $Command"]+ | ["Offset, Value, $Command,
> @Comment"]+ ```+```+PatchFv FdFileDir FdFileName ["Offset, Value"]++ |
> ["Offset, Value, @Comment"]++ | ["Offset, Value, $Command"]++ | ["Offset,
> Value, $Command, @Comment"]++``` #Description The **_PatchFv.py_** tool
> allows the developer to fix up FD images to follow the@@ -102,6 +109,19 @@
> ModuleGuid:Offset
>< > Convert absolute address into an image offset (expr & FSP_SIZE)
> ```+From version 0.60 tool allows to pass flash device file path as Argument 1
> and+flash device name as Argument 2 and rules for passing offset & value are
> same+as explained in the previous sections.++Example usage:+Argument
> 1+```+ YouPlatformFspBinPkg\+```+Argument 2+```+ Fsp_Rebased_T+```
> ###Special Commands: Special commands must use the **$** symbol as a
> prefix to the command itself.--
> 2.39.1.windows.1
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Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly
Patch merged:
https://github.com/tianocore/edk2/commit/b16284e2a0011489f6e16dfcc6af7623c3cbaf0b
Thanks,
Chasel
> -Original Message-
> From: Duggapu, Chinni B
> Sent: Sunday, April 16, 2023 9:23 PM
> To: devel@edk2.groups.io
> Cc: Duggapu, Chinni B ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Zeng, Star ; Kuo, Ted
>
> Subject: [PATCH v3] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file
> directly
>
> From: "Duggapu, Chinni B"
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4412
>
> After shrinking the FSP (FV) component using FMMT, Image size in FSP info
> header is not in sync with the FV length in FV header.
> This enhancement helps to patch the FSP image size offset with correct length
> &
> can be used to patch any offset directly on the FSP Component Fd.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ted Kuo
> Signed-off-by: Duggapu Chinni B
> ---
> IntelFsp2Pkg/Tools/PatchFv.py | 14 -
> .../Tools/UserManuals/PatchFvUserManual.md| 20 +++
> 2 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
> index eb130049b5..73ab877c71 100644
> --- a/IntelFsp2Pkg/Tools/PatchFv.py
> +++ b/IntelFsp2Pkg/Tools/PatchFv.py
> @@ -165,6 +165,17 @@ class Symbols:
> if not os.path.isdir(fvDir): raise Exception ("'%s' is
> not a valid
> directory!" % fvDir) +#+# if user provided fd name as a
> input, skip rest of
> the flow to+# patch fd directly+#+fdFile =
> os.path.join(fvDir,fvNames + ".fd")+if os.path.exists(fdFile):+
> print("Tool identified Fd file as a input to patch '%s'" %fdFile)+
> self.fdFile =
> fdFile+self.fdSize = os.path.getsize(fdFile)+return
> 0+ # # If
> the Guid.xref is not existing in fvDir, then raise an exception #@@
> -848,8
> +859,9 @@ class Symbols:
> # Print out the usage # def Usage():-print ("PatchFv Version 0.50")+
> print
> ("PatchFv Version 0.60") print ("Usage: \n\tPatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")+print
> ("\tPatchFv FdFileDir FdFileName \"Offset, Value\"") def main(): #diff
> --git
> a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> index 5f1031e729..f28eedf625 100644
> --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> @@ -1,6 +1,7 @@
> #Name **_PatchFv.py_** - The python script that patches the firmware
> volumes (**FV**) with in the flash device (**FD**) file post FSP build.+From
> version 0.60, script is capable of patching flash device (**FD**) directly.
> #Synopsis @@ -10,6 +11,12 @@ PatchFv FvBuildDir
> [FvFileBaseNames:]FdFileBaseNameToPatch ["Offset, Value"]+
>| ["Offset, Value, $Command"]+ | ["Offset, Value, $Command,
> @Comment"]+ ```+```+PatchFv FdFileDir FdFileName ["Offset, Value"]++ |
> ["Offset, Value, @Comment"]++ | ["Offset, Value, $Command"]++ | ["Offset,
> Value, $Command, @Comment"]++``` #Description The **_PatchFv.py_** tool
> allows the developer to fix up FD images to follow the@@ -102,6 +109,19 @@
> ModuleGuid:Offset
>< > Convert absolute address into an image offset (expr & FSP_SIZE)
> ```+From version 0.60 tool allows to pass flash device file path as Argument 1
> and+flash device name as Argument 2 and rules for passing offset & value are
> same+as explained in the previous sections.++Example usage:+Argument
> 1+```+ YouPlatformFspBinPkg\+```+Argument 2+```+ Fsp_Rebased_T+```
> ###Special Commands: Special commands must use the **$** symbol as a
> prefix to the command itself.--
> 2.39.1.windows.1
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Re: [edk2-devel] [PATCH 1/1] IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN Coverity issue
That’s good suggestion Pedro!
Ranbir, would you like me to modify your patch to "return 0" during merging?
Thanks,
Chasel
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Pedro
> Falcato
> Sent: Friday, May 19, 2023 5:29 AM
> To: devel@edk2.groups.io; rsi...@ventanamicro.com
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; Ranbir
> Singh
> Subject: Re: [edk2-devel] [PATCH 1/1] IntelFsp2Pkg/Library/BaseFspCommonLib:
> Fix OVERRUN Coverity issue
>
> On Thu, May 18, 2023 at 4:16 PM Ranbir Singh
> wrote:
> >
> > FspData->PerfIdx is getting increased for every call unconditionally
> > in the function SetFspMeasurePoint and hence memory access can happen
> > for out of bound FspData->PerfData[] array entries also.
> >
> > Example -
> >FspData->PerfData is an array of 32 UINT64 entries. Assume a call
> >is made to SetFspMeasurePoint function when the FspData->PerfIdx
> >last value is 31. It gets incremented to 32 at line 400.
> >Any subsequent call to SetFspMeasurePoint functions leads to
> >FspData->PerfData[32] getting accessed which is out of the PerfData
> >array as well as the FSP_GLOBAL_DATA structure boundary.
> >
> > Hence keep array access and index increment inside if block only and
> > return invalid performance timestamp when PerfIdx is invalid.
> >
> > Cc: Chasel Chiu
> > Cc: Nate DeSimone
> > Cc: Star Zeng
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4200
> > Signed-off-by: Ranbir Singh
> > Signed-off-by: Ranbir Singh
> > ---
> > IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> > b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> > index a22b0e7825ad..cda2a7b2478e 100644
> > --- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> > +++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> > @@ -377,7 +377,8 @@ GetFspSiliconInitUpdDataPointer (
> >
> >@param[in] Id Measurement point ID.
> >
> > - @return performance timestamp.
> > + @return performance timestamp if current PerfIdx is valid,
> > + else return 0 as invalid performance timestamp
> > **/
> > UINT64
> > EFIAPI
> > @@ -395,9 +396,10 @@ SetFspMeasurePoint (
> >if (FspData->PerfIdx < sizeof (FspData->PerfData) / sizeof (FspData-
> >PerfData[0])) {
> > FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();
> > ((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;
> > +return FspData->PerfData[(FspData->PerfIdx)++];
> >}
> >
> > - return FspData->PerfData[(FspData->PerfIdx)++];
> > + return (UINT64)0x;
>
> return 0;
>
> Works just as well. You also don't need a cast.
>
> https://godbolt.org/z/e5vvGcWWo
>
> --
> Pedro
>
>
>
>
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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use FFS3
Patch merged: https://github.com/tianocore/edk2/commit/69e10f02111bf7e719237f05233abff4e50016fa Thanks, Chasel > -Original Message- > From: Tan, Ming > Sent: Sunday, May 21, 2023 11:13 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Duggapu, Chinni B > > Subject: [PATCH] IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use FFS3 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4458 > > Original code call PeiServicesInstallFvInfoPpi() with NULL for the FvFormat > parameter, then PeiServicesInstallFvInfoPpi() will assume it use FFS2, then > ASSERT if FSP-S/M use FFS3. > Now set the FvFormat to the info got from FvHeader. > > Cc: Chasel Chiu > Cc: Duggapu Chinni B > Signed-off-by: Ming Tan > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 2 +- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > index ea206a7960..ba0c742fea 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > @@ -217,7 +217,7 @@ FspmWrapperInit ( > ASSERT_EFI_ERROR (Status); PeiServicesInstallFvInfoPpi (- > NULL,+ > &((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 > (PcdFspmBaseAddress))->FileSystemGuid, (VOID *)(UINTN)PcdGet32 > (PcdFspmBaseAddress), (UINT32)((EFI_FIRMWARE_VOLUME_HEADER > *)(UINTN)PcdGet32 (PcdFspmBaseAddress))->FvLength, NULL,diff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > index 091ddb697a..08fe0fdb7e 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > @@ -438,7 +438,7 @@ FspsWrapperInitDispatchMode ( >// FSP-S Wrapper running in Dispatch mode and reports FSP-S FV to PEI > dispatcher. // PeiServicesInstallFvInfoPpi (-NULL,+ > &((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 > (PcdFspsBaseAddress))->FileSystemGuid, (VOID *)(UINTN)PcdGet32 > (PcdFspsBaseAddress), (UINT32)((EFI_FIRMWARE_VOLUME_HEADER > *)(UINTN)PcdGet32 (PcdFspsBaseAddress))->FvLength, NULL,-- > 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105402): https://edk2.groups.io/g/devel/message/105402 Mute This Topic: https://groups.io/mt/99059532/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/1] IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN Coverity issue
Patch merged:
https://github.com/tianocore/edk2/commit/48c53994e649d51a388dc414944c9a9b717a1c3c
Thanks,
Chasel
> -Original Message-
> From: Ranbir Singh
> Sent: Wednesday, May 17, 2023 11:29 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; Ranbir
> Singh
> Subject: [PATCH 1/1] IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN
> Coverity issue
>
> FspData->PerfIdx is getting increased for every call unconditionally
> in the function SetFspMeasurePoint and hence memory access can happen for
> out of bound FspData->PerfData[] array entries also.
>
> Example -
>FspData->PerfData is an array of 32 UINT64 entries. Assume a call
>is made to SetFspMeasurePoint function when the FspData->PerfIdx
>last value is 31. It gets incremented to 32 at line 400.
>Any subsequent call to SetFspMeasurePoint functions leads to
>FspData->PerfData[32] getting accessed which is out of the PerfData
>array as well as the FSP_GLOBAL_DATA structure boundary.
>
> Hence keep array access and index increment inside if block only and return
> invalid performance timestamp when PerfIdx is invalid.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4200
> Signed-off-by: Ranbir Singh
> Signed-off-by: Ranbir Singh
> ---
> IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> index a22b0e7825ad..cda2a7b2478e 100644
> --- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> +++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> @@ -377,7 +377,8 @@ GetFspSiliconInitUpdDataPointer (
> @param[in] Id Measurement point ID. - @return performance
> timestamp.+ @return performance timestamp if current PerfIdx is valid,+
> else return 0 as invalid performance timestamp **/ UINT64 EFIAPI@@ -395,9
> +396,10 @@ SetFspMeasurePoint (
>if (FspData->PerfIdx < sizeof (FspData->PerfData) / sizeof (FspData-
> >PerfData[0])) { FspData->PerfData[FspData->PerfIdx] =
> AsmReadTsc (); ((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;+
> return FspData->PerfData[(FspData->PerfIdx)++]; } - return FspData-
> >PerfData[(FspData->PerfIdx)++];+ return (UINT64)0x; }
> /**--
> 2.34.1
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Re: [edk2-devel] [PATCH v9] MinPlatformPkg: Update HWSignature field in FACS
Thanks for the reviewing Ankit!
It looks to me current version is good enough for merging, if no other
feedbacks I will help to merge it tomorrow.
Thanks,
Chasel
> -Original Message-
> From: Sinha, Ankit
> Sent: Tuesday, May 30, 2023 8:53 AM
> To: Ke, VincentX ; devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Oram, Isaac W ;
> Gao, Liming ; Dong, Eric
> Subject: RE: [PATCH v9] MinPlatformPkg: Update HWSignature field in FACS
>
> Reviewed-by: Ankit Sinha
>
> Thank you,
> Ankit
>
> > -Original Message-
> > From: Ke, VincentX
> > Sent: Wednesday, May 24, 2023 1:39 AM
> > To: devel@edk2.groups.io
> > Cc: Ke, VincentX ; Chiu, Chasel
> > ; Desimone, Nathaniel L
> > ; Oram, Isaac W
> > ; Gao, Liming ;
> > Dong, Eric ; Sinha, Ankit
> > Subject: [PATCH v9] MinPlatformPkg: Update HWSignature field in FACS
> >
> > From: VincentX Ke
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4428
> >
> > Calculating CRC based on each ACPI table.
> > Update HWSignature field in FACS based on CRC while ACPI table changed.
> >
> > Change-Id: Ic0ca66ff10cda0fbcd0683020fab1bc9aea9b78c
> > Signed-off-by: VincentX Ke
> > Cc: Chasel Chiu
> > Cc: Nate DeSimone
> > Cc: Isaac Oram
> > Cc: Liming Gao
> > Cc: Eric Dong
> > Cc: Ankit Sinha
> > Signed-off-by: VincentX Ke
> > ---
> > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 282
> > +++-
> > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 1 +
> > 2 files changed, 215 insertions(+), 68 deletions(-)
> >
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > index 2f2c96f907..ca1c73f6fe 100644
> > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > @@ -1191,98 +1191,244 @@ PlatformUpdateTables ( }
> >
> >
> >
> > /**
> >
> > - This function calculates RCR based on PCI Device ID and Vendor ID
> > from the devices
> >
> > - available on the platform.
> >
> > - It also includes other instances of BIOS change to calculate CRC
> > and provides as
> >
> > - HWSignature filed in FADT table.
> >
> > + Function prototype for GetAcpiTableCount/CalculateAcpiTableCrc.
> >
> > +
> >
> > + @param[in] TableThe pointer to ACPI table.
> >
> > + @param[in] TableIndex The ACPI table index.
> >
> > + @param[in] Context The pointer to UINTN for GetAcpiTableCount.
> >
> > + The pointer to UINT32 array for
> > CalculateAcpiTableCrc.
> >
> > **/
> >
> > +typedef
> >
> > VOID
> >
> > -IsHardwareChange (
> >
> > - VOID
> >
> > +(EFIAPI *ACPI_TABLE_CALLBACK)(
> >
> > + IN EFI_ACPI_COMMON_HEADER *Table,
> >
> > + IN UINTN TableIndex,
> >
> > + IN VOID*Context
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Enumerate all ACPI tables in RSDT/XSDT.
> >
> > +
> >
> > + @param[in] SdtACPI XSDT/RSDT.
> >
> > + @param[in] TablePointerSize Size of table pointer:
> >
> > +4(RSDT) or 8(XSDT).
> >
> > + @param[in] CallbackFunction The pointer to
> > GetAcpiTableCount/CalculateAcpiTableCrc.
> >
> > + @param[in] ContextThe pointer to UINTN for GetAcpiTableCount.
> >
> > +The pointer to UINT32 array for
> > CalculateAcpiTableCrc.
> >
> > +**/
> >
> > +VOID
> >
> > +EnumerateAllAcpiTables (
> >
> > + IN EFI_ACPI_DESCRIPTION_HEADER *Sdt,
> >
> > + IN UINTNTablePointerSize,
> >
> > + IN ACPI_TABLE_CALLBACK CallbackFunction,
> >
> > + IN VOID *Context
> >
> >)
> >
> > {
> >
> > - EFI_STATUS Status;
> >
> > - UINTNIndex;
> >
> > - UINTNHandleCount;
> >
> > - EFI_HANDLE *HandleBuffer;
> >
> > - EFI_PCI_IO_PROTOCOL *PciIo;
> >
> >
Re: [edk2-devel] [PATCH v10] MinPlatformPkg: Update HWSignature field in FACS
Patch merged:
https://github.com/tianocore/edk2-platforms/commit/1a7bd150d39007bfb72c4727feda3184c23efe96
Thanks,
Chasel
> -Original Message-
> From: Ke, VincentX
> Sent: Tuesday, May 30, 2023 7:48 PM
> To: devel@edk2.groups.io
> Cc: Ke, VincentX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Oram, Isaac W ;
> Gao, Liming ; Dong, Eric ;
> Sinha, Ankit
> Subject: [PATCH v10] MinPlatformPkg: Update HWSignature field in FACS
>
> From: VincentX Ke
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4428
>
> Calculating CRC based on each ACPI table.
> Update HWSignature field in FACS based on CRC while ACPI table changed.
>
> Change-Id: Ic0ca66ff10cda0fbcd0683020fab1bc9aea9b78c
> Signed-off-by: VincentX Ke
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Isaac Oram
> Cc: Liming Gao
> Cc: Eric Dong
> Cc: Ankit Sinha
> Signed-off-by: VincentX Ke
> ---
> Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 284
> +++-
> Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 1 +
> 2 files changed, 217 insertions(+), 68 deletions(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index 2f2c96f907..2a833ec99c 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -1191,98 +1191,246 @@ PlatformUpdateTables (
> }
>
>
>
> /**
>
> - This function calculates RCR based on PCI Device ID and Vendor ID from the
> devices
>
> - available on the platform.
>
> - It also includes other instances of BIOS change to calculate CRC and
> provides
> as
>
> - HWSignature filed in FADT table.
>
> + Function prototype for GetAcpiTableCount/CalculateAcpiTableCrc.
>
> +
>
> + @param[in] TableThe pointer to ACPI table.
>
> + @param[in] TableIndex The ACPI table index.
>
> + @param[in] Context The pointer to UINTN for GetAcpiTableCount.
>
> + The pointer to UINT32 array for
> CalculateAcpiTableCrc.
>
> **/
>
> +typedef
>
> VOID
>
> -IsHardwareChange (
>
> - VOID
>
> +(EFIAPI *ACPI_TABLE_CALLBACK)(
>
> + IN EFI_ACPI_COMMON_HEADER *Table,
>
> + IN UINTN TableIndex,
>
> + IN VOID*Context
>
> + );
>
> +
>
> +/**
>
> + Enumerate all ACPI tables in RSDT/XSDT.
>
> +
>
> + @param[in] SdtACPI XSDT/RSDT.
>
> + @param[in] TablePointerSize Size of table pointer:
>
> +4(RSDT) or 8(XSDT).
>
> + @param[in] CallbackFunction The pointer to
> GetAcpiTableCount/CalculateAcpiTableCrc.
>
> + @param[in] ContextThe pointer to UINTN for GetAcpiTableCount.
>
> +The pointer to UINT32 array for
> CalculateAcpiTableCrc.
>
> +**/
>
> +VOID
>
> +EnumerateAllAcpiTables (
>
> + IN EFI_ACPI_DESCRIPTION_HEADER *Sdt,
>
> + IN UINTNTablePointerSize,
>
> + IN ACPI_TABLE_CALLBACK CallbackFunction,
>
> + IN VOID *Context
>
>)
>
> {
>
> - EFI_STATUS Status;
>
> - UINTNIndex;
>
> - UINTNHandleCount;
>
> - EFI_HANDLE *HandleBuffer;
>
> - EFI_PCI_IO_PROTOCOL *PciIo;
>
> - UINT32 CRC;
>
> - UINT32 *HWChange;
>
> - UINTNHWChangeSize;
>
> - UINT32 PciId;
>
> - UINTNHandle;
>
> - EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
>
> - EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE*pFADT;
>
> -
>
> - HandleCount = 0;
>
> - HandleBuffer = NULL;
>
> -
>
> - Status = gBS->LocateHandleBuffer (
>
> - ByProtocol,
>
> - &gEfiPciIoProtocolGuid,
>
> - NULL,
>
> - &HandleCount,
>
> - &HandleBuffer
>
> - );
>
> - if (EFI_ERROR (Status)) {
>
> -return; // PciIO protocol not installed yet!
>
> + UINTN Index;
>
> + UINTN
Re: [edk2-devel] [PATCH] MinPlatform: Add CpuPageTableLib required by CpuMpPeim
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Ni, Ray > Sent: Wednesday, May 31, 2023 2:18 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH] MinPlatform: Add CpuPageTableLib required by CpuMpPeim > > The patch moves the CpuPageTableLib reference from CoreDxeLib.dsc to > CoreCommonLib.dsc since now not only DxeMpInitLib but also CpuMpPei > depends on it. > > Signed-off-by: Ray Ni > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc | 1 + > Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc| 3 +-- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > index dfe7d836d3..300b7d7652 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > @@ -106,6 +106,7 @@ >LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeatures > Lib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf+ > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf# > # Platformdiff --git > a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > index af30f985ca..5a2cb130b3 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > @@ -1,7 +1,7 @@ > ## @file # Platform description. #-# Copyright (c) 2017 - 2021, Intel > Corporation. All rights reserved.+# Copyright (c) 2017 - 2023, Intel > Corporation. All rights reserved. # # SPDX-License-Identifier: > BSD-2-Clause- > Patent #@@ -27,7 +27,6 @@ >LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf > CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE > xceptionHandlerLib.inf- > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf > FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLi > b.inf TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf-- > 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105508): https://edk2.groups.io/g/devel/message/105508 Mute This Topic: https://groups.io/mt/99238376/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] MinPlatform: Add CpuPageTableLib required by CpuMpPeim
Patch merged: https://github.com/tianocore/edk2-platforms/commit/ce9ea07a8b56dc12165ca4f7e975d3b2f798881e Thanks, Chasel > -Original Message- > From: Ni, Ray > Sent: Wednesday, May 31, 2023 2:18 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric > Subject: [PATCH] MinPlatform: Add CpuPageTableLib required by CpuMpPeim > > The patch moves the CpuPageTableLib reference from CoreDxeLib.dsc to > CoreCommonLib.dsc since now not only DxeMpInitLib but also CpuMpPei > depends on it. > > Signed-off-by: Ray Ni > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > --- > Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc | 1 + > Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc| 3 +-- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > index dfe7d836d3..300b7d7652 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > @@ -106,6 +106,7 @@ >LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeatures > Lib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf+ > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf# > # Platformdiff --git > a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > index af30f985ca..5a2cb130b3 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > @@ -1,7 +1,7 @@ > ## @file # Platform description. #-# Copyright (c) 2017 - 2021, Intel > Corporation. All rights reserved.+# Copyright (c) 2017 - 2023, Intel > Corporation. All rights reserved. # # SPDX-License-Identifier: > BSD-2-Clause- > Patent #@@ -27,7 +27,6 @@ >LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf > CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE > xceptionHandlerLib.inf- > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf > FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLi > b.inf TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf-- > 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105575): https://edk2.groups.io/g/devel/message/105575 Mute This Topic: https://groups.io/mt/99238376/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] Get HobListPtr before calling the Multiphase FSPS
Please update the subject per format requirement -
PackageName: title
With this update, Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Aishwarya, KurugoduMelmatamX
>
> Sent: Friday, June 9, 2023 6:40 AM
> To: devel@edk2.groups.io
> Cc: Aishwarya, KurugoduMelmatamX
> ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Duggapu, Chinni B
> ; Chen, Gang C ; Zeng,
> Star ; Kuo, Ted ; S, Ashraf Ali
> ; Mohapatra, Susovan
>
> Subject: [PATCH] Get HobListPtr before calling the Multiphase FSPS
>
> REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480
>
> In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and
> FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will
> be able to get the correct FspHobListPtr value
>
> Signed-off-by: kurugodx
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Duggapu Chinni B
> Cc: Chen Gang C
> Cc: Star Zeng
> Cc: Ted Kuo
> Cc: Ashraf Ali S
> Cc: Susovan Mohapatra
> ---
> .../FspsWrapperPeim/FspsWrapperPeim.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> index 08fe0fdb7e..1d4dd60577 100644
> --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> @@ -336,6 +336,14 @@ PeiMemoryDiscoveredNotify (
>
>DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));
>
> + //
> + // Get FspHobList
> + //
> + GuidHob = GetFirstGuidHob (&gFspHobGuid); ASSERT (GuidHob != NULL);
> + FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob); DEBUG
> + ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
> +
>if (Status == FSP_STATUS_VARIABLE_REQUEST) {
> //
> // call to Variable request handler @@ -356,13 +364,6 @@
> PeiMemoryDiscoveredNotify (
> DEBUG ((DEBUG_ERROR, "ERROR - TestFspSiliconInitApiOutput () fail, Status
> = %r\n", Status));
>}
>
> - //
> - // Now FspHobList complete, process it
> - //
> - GuidHob = GetFirstGuidHob (&gFspHobGuid);
> - ASSERT (GuidHob != NULL);
> - FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
> - DEBUG ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
>PostFspsHobProcess (FspHobListPtr);
>
>//
> --
> 2.41.0.windows.1
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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the Multiphase FSPS
Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Aishwarya, KurugoduMelmatamX
>
> Sent: Sunday, June 11, 2023 10:24 PM
> To: devel@edk2.groups.io
> Cc: Aishwarya, KurugoduMelmatamX
> ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Duggapu, Chinni B
> ; Chen, Gang C ; Zeng,
> Star ; Kuo, Ted ; S, Ashraf Ali
> ; Mohapatra, Susovan
>
> Subject: [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the
> Multiphase FSPS
>
> REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480
>
> In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and
> FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will
> be able to get the correct FspHobListPtr value
>
> Signed-off-by: kurugodx
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Duggapu Chinni B
> Cc: Chen Gang C
> Cc: Star Zeng
> Cc: Ted Kuo
> Cc: Ashraf Ali S
> Cc: Susovan Mohapatra
> ---
> .../FspsWrapperPeim/FspsWrapperPeim.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> index 08fe0fdb7e..1d4dd60577 100644
> --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> @@ -336,6 +336,14 @@ PeiMemoryDiscoveredNotify (
>
>DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));
>
> + //
> + // Get FspHobList
> + //
> + GuidHob = GetFirstGuidHob (&gFspHobGuid); ASSERT (GuidHob != NULL);
> + FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob); DEBUG
> + ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
> +
>if (Status == FSP_STATUS_VARIABLE_REQUEST) {
> //
> // call to Variable request handler @@ -356,13 +364,6 @@
> PeiMemoryDiscoveredNotify (
> DEBUG ((DEBUG_ERROR, "ERROR - TestFspSiliconInitApiOutput () fail, Status
> = %r\n", Status));
>}
>
> - //
> - // Now FspHobList complete, process it
> - //
> - GuidHob = GetFirstGuidHob (&gFspHobGuid);
> - ASSERT (GuidHob != NULL);
> - FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
> - DEBUG ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
>PostFspsHobProcess (FspHobListPtr);
>
>//
> --
> 2.41.0.windows.1
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Re: [edk2-devel] Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team
Hello, edk2 stewards, Could you please help this case? Thanks, Chasel From: devel@edk2.groups.io On Behalf Of cbduggap Sent: Sunday, June 18, 2023 10:28 PM To: devel@edk2.groups.io Subject: [edk2-devel] Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team HI All I signed up to work as Maintainer for InteFsp2Pkg and IntelFsp2WrapperPkg and part of https://github.com/tianocore/edk2/blob/master/Maintainers.txt Need help to add me to the edk-ii-maintainers and edk-ii-reviewers team. Maintainer: https://github.com/orgs/tianocore/teams/edk-ii-maintainers Reviewer: https://github.com/orgs/tianocore/teams/edk-ii-reviewers Thanks, Chinni. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106237): https://edk2.groups.io/g/devel/message/106237 Mute This Topic: https://groups.io/mt/99618174/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the Multiphase FSPS
Patch merged:
https://github.com/tianocore/edk2/commit/ac33eee8b83999ba591af04fe22e773cf8fc8193
Thanks,
Chasel
> -Original Message-
> From: Aishwarya, KurugoduMelmatamX
>
> Sent: Sunday, June 11, 2023 10:24 PM
> To: devel@edk2.groups.io
> Cc: Aishwarya, KurugoduMelmatamX
> ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Duggapu, Chinni B
> ; Chen, Gang C ; Zeng,
> Star ; Kuo, Ted ; S, Ashraf Ali
> ; Mohapatra, Susovan
> Subject: [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the
> Multiphase FSPS
>
> REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480
>
> In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and
> FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will
> be able to get the correct FspHobListPtr value
>
> Signed-off-by: kurugodx
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Duggapu Chinni B
> Cc: Chen Gang C
> Cc: Star Zeng
> Cc: Ted Kuo
> Cc: Ashraf Ali S
> Cc: Susovan Mohapatra
> ---
> .../FspsWrapperPeim/FspsWrapperPeim.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> index 08fe0fdb7e..1d4dd60577 100644
> --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
> @@ -336,6 +336,14 @@ PeiMemoryDiscoveredNotify (
>
>DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));
>
> + //
> + // Get FspHobList
> + //
> + GuidHob = GetFirstGuidHob (&gFspHobGuid); ASSERT (GuidHob != NULL);
> + FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob); DEBUG
> + ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
> +
>if (Status == FSP_STATUS_VARIABLE_REQUEST) {
> //
> // call to Variable request handler @@ -356,13 +364,6 @@
> PeiMemoryDiscoveredNotify (
> DEBUG ((DEBUG_ERROR, "ERROR - TestFspSiliconInitApiOutput () fail,
> Status =
> %r\n", Status));
>}
>
> - //
> - // Now FspHobList complete, process it
> - //
> - GuidHob = GetFirstGuidHob (&gFspHobGuid);
> - ASSERT (GuidHob != NULL);
> - FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
> - DEBUG ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
>PostFspsHobProcess (FspHobListPtr);
>
>//
> --
> 2.41.0.windows.1
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Re: [edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP binary with child FV included
Hi Ted,
One question below inline.
Another minor feedback is the commit/patch subject format should be "Package:
title"
Thanks,
Chasel
> -Original Message-
> From: Kuo, Ted
> Sent: Tuesday, July 18, 2023 7:16 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S, Ashraf
> Ali ; Duggapu, Chinni B ;
> Ng, Ray Han Lim ; Mohapatra, Susovan
>
> Subject: [edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP binary with
> child FV included
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4502
> Update SplitFspBin.py to support child FV in FSP binary. Without the patch,
> the
> tool won't be able to rebase the images in child FV in FSP binary.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ashraf Ali S
> Cc: Chinni B Duggapu
> Cc: Ray Han Lim Ng
> Cc: Susovan Mohapatra
> Signed-off-by: Ted Kuo
> ---
> IntelFsp2Pkg/Tools/SplitFspBin.py | 32 ---
> 1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
> b/IntelFsp2Pkg/Tools/SplitFspBin.py
> index 419e5ba985..2e7550dbb2 100644
> --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> @@ -469,6 +469,7 @@ class FirmwareVolume:
> else: self.FvExtHdr = None self.FfsList = []+
> self.ChildFvList =
> [] def ParseFv(self): fvsize = len(self.FvData)@@ -483,8 +484,18
> @@ class
> FirmwareVolume:
> offset = fvsize else: ffs =
> FirmwareFile (offset,
> self.FvData[offset:offset + int(ffshdr.Size)])-ffs.ParseFfs()-
> self.FfsList.append(ffs)+csoffset = offset + sizeof
> (EFI_FFS_FILE_HEADER)+cshdr =
> EFI_COMMON_SECTION_HEADER.from_buffer (self.FvData, csoffset)+
> #
> check if there is child fv+if (ffs.FfsHdr.Type ==
> EFI_FV_FILETYPE.FIRMWARE_VOLUME_IMAGE and cshdr.Type ==
> EFI_SECTION_TYPE.RAW):+childfvoffset = csoffset + sizeof
Is child FV always with EFI_SECTION_TYPE.RAW? Or it could be other types like
EFI_SECTION_TYPE.FIRMWARE_VOLUME_IMAGE?
> (EFI_COMMON_SECTION_HEADER) + int(cshdr.Size)+childfvhdr =
> EFI_FIRMWARE_VOLUME_HEADER.from_buffer (self.FvData, childfvoffset)+
> childfv = FirmwareVolume (childfvoffset,
> self.FvData[childfvoffset:childfvoffset +
> int(childfvhdr.FvLength)])+childfv.ParseFv ()+
> self.ChildFvList.append(childfv)+else:+
> ffs.ParseFfs()+
> self.FfsList.append(ffs) offset += int(ffshdr.Size)
> offset =
> AlignPtr(offset) @@ -789,6 +800,13 @@ def SplitFspBin (fspfile, outdir,
> nametemplate):
> hfsp.write(fv.FvData) hfsp.close() +def GetImageFromFv
> (fd,
> parentfvoffset, fv, imglist):+for ffs in fv.FfsList:+for sec in
> ffs.SecList:+
> if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or
> PE32+offset = fd.Offset + parentfvoffset + fv.Offset +
> ffs.Offset +
> sec.Offset + sizeof(sec.SecHdr)+imglist.append ((offset,
> len(sec.SecData)
> - sizeof(sec.SecHdr)))+ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile): fd = FirmwareDevice(0, FspBinary) fd.ParseFd
> ()@@ -
> 832,11 +850,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile):
> imglist = [] for fvidx in fsp.FvIdxList: fv =
> fd.FvList[fvidx]-for
> ffs in fv.FfsList:-for sec in ffs.SecList:-
> if sec.SecHdr.Type in
> [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or PE32-
> offset = fd.Offset + fv.Offset + ffs.Offset + sec.Offset + sizeof(sec.SecHdr)-
> imglist.append ((offset, len(sec.SecData) - sizeof(sec.SecHdr)))+
> GetImageFromFv (fd, 0, fv, imglist)+# get image from child fv+
> for
> childfv in fv.ChildFvList:+print ("Get image from child fv of
> fv%d, parent
> fv offset: 0x%x" % (fvidx, fv.Offset))+GetImageFromFv (fd,
> fv.Offset,
> childfv, imglist) fcount = 0 pcount = 0--
> 2.40.1.windows.1
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Re: [edk2-devel][PATCH v2] IntelFsp2Pkg: Support child FV in SplitFspBin.py
Looks good to me. Thanks Ted!
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Kuo, Ted
> Sent: Thursday, July 20, 2023 3:20 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S, Ashraf
> Ali ; Duggapu, Chinni B ;
> Ng, Ray Han Lim ; Mohapatra, Susovan
>
> Subject: [edk2-devel][PATCH v2] IntelFsp2Pkg: Support child FV in
> SplitFspBin.py
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4502
> Update SplitFspBin.py to support child FV in FSP binary. Without the patch,
> the
> tool won't be able to rebase the images in child FV in FSP binary.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ashraf Ali S
> Cc: Chinni B Duggapu
> Cc: Ray Han Lim Ng
> Cc: Susovan Mohapatra
> Signed-off-by: Ted Kuo
> ---
> IntelFsp2Pkg/Tools/SplitFspBin.py | 44 ++-
> 1 file changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
> b/IntelFsp2Pkg/Tools/SplitFspBin.py
> index 419e5ba985..558eaf401a 100644
> --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> @@ -469,6 +469,7 @@ class FirmwareVolume:
> else: self.FvExtHdr = None self.FfsList = []+
> self.ChildFvList =
> [] def ParseFv(self): fvsize = len(self.FvData)@@ -483,8 +484,30
> @@ class
> FirmwareVolume:
> offset = fvsize else: ffs =
> FirmwareFile (offset,
> self.FvData[offset:offset + int(ffshdr.Size)])-ffs.ParseFfs()-
> self.FfsList.append(ffs)+# check if there is child fv+
> childfvfound
> = 0+if (ffs.FfsHdr.Type ==
> EFI_FV_FILETYPE.FIRMWARE_VOLUME_IMAGE):+csoffset = offset
> +
> sizeof (EFI_FFS_FILE_HEADER)+csoffset =
> AlignPtr(csoffset, 4)+
> # find fv section+while csoffset < (offset +
> int(ffs.FfsHdr.Size)):+
> cshdr = EFI_COMMON_SECTION_HEADER.from_buffer (self.FvData, csoffset)+
> if (cshdr.Type == EFI_SECTION_TYPE.FIRMWARE_VOLUME_IMAGE):+
> childfvfound = 1+break+
> else:+#
> check next section+csoffset += int(cshdr.Size)+
> csoffset = AlignPtr(csoffset, 4)+if (childfvfound):+
> childfvoffset
> = csoffset + sizeof (EFI_COMMON_SECTION_HEADER)+
> childfvhdr =
> EFI_FIRMWARE_VOLUME_HEADER.from_buffer (self.FvData, childfvoffset)+
> childfv = FirmwareVolume (childfvoffset,
> self.FvData[childfvoffset:childfvoffset +
> int(childfvhdr.FvLength)])+childfv.ParseFv ()+
> self.ChildFvList.append(childfv)+else:+
> ffs.ParseFfs()+
> self.FfsList.append(ffs) offset += int(ffshdr.Size)
> offset =
> AlignPtr(offset) @@ -789,6 +812,13 @@ def SplitFspBin (fspfile, outdir,
> nametemplate):
> hfsp.write(fv.FvData) hfsp.close() +def GetImageFromFv
> (fd,
> parentfvoffset, fv, imglist):+for ffs in fv.FfsList:+for sec in
> ffs.SecList:+
> if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or
> PE32+offset = fd.Offset + parentfvoffset + fv.Offset +
> ffs.Offset +
> sec.Offset + sizeof(sec.SecHdr)+imglist.append ((offset,
> len(sec.SecData)
> - sizeof(sec.SecHdr)))+ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile): fd = FirmwareDevice(0, FspBinary) fd.ParseFd
> ()@@ -
> 832,11 +862,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile):
> imglist = [] for fvidx in fsp.FvIdxList: fv =
> fd.FvList[fvidx]-for
> ffs in fv.FfsList:-for sec in ffs.SecList:-
> if sec.SecHdr.Type in
> [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or PE32-
> offset = fd.Offset + fv.Offset + ffs.Offset + sec.Offset + sizeof(sec.SecHdr)-
> imglist.append ((offset, len(sec.SecData) - sizeof(sec.SecHdr)))+
> GetImageFromFv (fd, 0, fv, imglist)+# get image from child fv+
> for
> childfv in fv.ChildFvList:+print ("Get image from child fv of
> fv%d, parent
> fv offset: 0x%x" % (fvidx, fv.Offset))+GetImageFromFv (fd,
> fv.Offset,
> childfv, imglist) fcount = 0 pcount = 0--
> 2.40.1.windows.1
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Re: [edk2-devel] [PATCH] MinPlatformPkg: Remove IA32 in PeiFspWrapperPlatformLib
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Hsueh, DoraX > Sent: Monday, July 24, 2023 2:43 AM > To: devel@edk2.groups.io > Cc: Hsueh, DoraX ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Oram, Isaac W ; > Gao, Liming ; Dong, Eric ; > Chuang, Rosen ; Kuo, Ted > Subject: [PATCH] MinPlatformPkg: Remove IA32 in PeiFspWrapperPlatformLib > > From: DoraX Hsueh > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4508 > > Remove IA32 only dependency, Because we need to support both IA32 and X64. > Apply to a modern platform supporting x64. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Isaac Oram > Cc: Liming Gao > Cc: Eric Dong > Cc: Rosen Chuang > Cc: Ted Kuo > Signed-off-by: DoraX Hsueh > --- > .../PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib > /PeiFspWrapperPlatformLib.inf > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib > /PeiFspWrapperPlatformLib.inf > index dafd17dc..489b34cf 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib > /PeiFspWrapperPlatformLib.inf > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib > /PeiFspWrapperPlatformLib.inf > @@ -51,7 +51,7 @@ >IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > >MinPlatformPkg/MinPlatformPkg.dec > > > > -[LibraryClasses.IA32] > > +[LibraryClasses] > >SiliconPolicyInitLib > >SiliconPolicyUpdateLib > >PeiServicesTablePointerLib > > -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107271): https://edk2.groups.io/g/devel/message/107271 Mute This Topic: https://groups.io/mt/100333272/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
When invalid VariableStore FV header detected, current SpiFvbService
will erase both FV and VariableStore headers from flash, however,
it will only rewrite FV header back and cause invalid VariableStore
header.
This patch adding the support for rewriting both FV header and
VariableStore header when VariableStore corruption happened.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
which VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 172
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 4
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 132 insertions(+), 52 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..f29540c62c 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/**
The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
@@ -25,12 +26,12 @@
**/
VOID
InstallFvbProtocol (
- IN EFI_FVB_INSTANCE *FvbInstance
+ IN EFI_FVB_INSTANCE *FvbInstance
)
{
- EFI_FIRMWARE_VOLUME_HEADER*FvHeader;
- EFI_STATUSStatus;
- EFI_HANDLEFvbHandle;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_STATUS Status;
+ EFI_HANDLE FvbHandle;
ASSERT (FvbInstance != NULL);
if (FvbInstance == NULL) {
@@ -52,19 +53,21 @@ InstallFvbProtocol (
//
// FV does not contains extension header, then produce MEMMAP_DEVICE_PATH
//
-FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
&mFvMemmapDevicePathTemplate);
+FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
*)AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
&mFvMemmapDevicePathTemplate);
if (FvbInstance->DevicePath == NULL) {
DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
MEMMAP_DEVICE_PATH failed\n"));
return;
}
-((FV_MEMMAP_DEVICE_PATH *)
FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;
-((FV_MEMMAP_DEVICE_PATH *)
FvbInstance->DevicePath)->MemMapDevPath.EndingAddress = FvbInstance->FvBase +
FvHeader->FvLength - 1;
+
+((FV_MEMMAP_DEVICE_PATH
*)FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;
+((FV_MEMMAP_DEVICE_PATH
*)FvbInstance->DevicePath)->MemMapDevPath.EndingAddress = FvbInstance->FvBase
+ FvHeader->FvLength - 1;
} else {
-FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
&mFvPIWGDevicePathTemplate);
+FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
*)AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
&mFvPIWGDevicePathTemplate);
if (FvbInstance->DevicePath == NULL) {
DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
FV_PIWG_DEVICE_PATH failed\n"));
return;
}
+
CopyGuid (
&((FV_PIWG_DEVICE_PATH *)FvbInstance->DevicePath)->FvDevPath.FvName,
(GUID *)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset)
@@ -103,17 +106,21 @@ FvbInitialize (
VOID
)
{
- EFI_FVB_INSTANCE *FvbInstance;
- EFI_FIRMWARE_VOLUME_HEADER*FvHeader;
- EFI_FV_BLOCK_MAP_ENTRY*PtrBlockMapEntry;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- EFI_STATUSStatus;
- UINTN BufferSize;
- UINTN Idx;
- UINT32MaxLbaSize;
- UINT32BytesWritten;
- UINTN BytesErased;
- UINT64NvStorageFvSize;
+ EFI_FVB_INSTANCE*FvbInstance;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;
+ EFI_PHYSICAL_ADDRESSBaseAddress;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ UINTN Idx;
+ UINT32 MaxLbaSize;
+ UINT32 BytesWritten;
+ UINTN BytesErased;
+ UINT64 NvStorageFvSize;
+ UINT32 ExpectedBytesWritten;
+ VARIABL
[edk2-devel] [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
When invalid VariableStore FV header detected, current SpiFvbService
will erase both FV and VariableStore headers from flash, however,
it will only rewrite FV header back and cause invalid VariableStore
header.
This patch adding the support for rewriting both FV header and
VariableStore header when VariableStore corruption happened.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
which VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 174
++
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 4
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 134 insertions(+), 52 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..6af2dfac10 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/**
The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
@@ -25,12 +26,12 @@
**/
VOID
InstallFvbProtocol (
- IN EFI_FVB_INSTANCE *FvbInstance
+ IN EFI_FVB_INSTANCE *FvbInstance
)
{
- EFI_FIRMWARE_VOLUME_HEADER*FvHeader;
- EFI_STATUSStatus;
- EFI_HANDLEFvbHandle;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_STATUS Status;
+ EFI_HANDLE FvbHandle;
ASSERT (FvbInstance != NULL);
if (FvbInstance == NULL) {
@@ -52,19 +53,21 @@ InstallFvbProtocol (
//
// FV does not contains extension header, then produce MEMMAP_DEVICE_PATH
//
-FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
&mFvMemmapDevicePathTemplate);
+FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
*)AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
&mFvMemmapDevicePathTemplate);
if (FvbInstance->DevicePath == NULL) {
DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
MEMMAP_DEVICE_PATH failed\n"));
return;
}
-((FV_MEMMAP_DEVICE_PATH *)
FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;
-((FV_MEMMAP_DEVICE_PATH *)
FvbInstance->DevicePath)->MemMapDevPath.EndingAddress = FvbInstance->FvBase +
FvHeader->FvLength - 1;
+
+((FV_MEMMAP_DEVICE_PATH
*)FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;
+((FV_MEMMAP_DEVICE_PATH
*)FvbInstance->DevicePath)->MemMapDevPath.EndingAddress = FvbInstance->FvBase
+ FvHeader->FvLength - 1;
} else {
-FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)
AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
&mFvPIWGDevicePathTemplate);
+FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
*)AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
&mFvPIWGDevicePathTemplate);
if (FvbInstance->DevicePath == NULL) {
DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
FV_PIWG_DEVICE_PATH failed\n"));
return;
}
+
CopyGuid (
&((FV_PIWG_DEVICE_PATH *)FvbInstance->DevicePath)->FvDevPath.FvName,
(GUID *)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset)
@@ -103,17 +106,21 @@ FvbInitialize (
VOID
)
{
- EFI_FVB_INSTANCE *FvbInstance;
- EFI_FIRMWARE_VOLUME_HEADER*FvHeader;
- EFI_FV_BLOCK_MAP_ENTRY*PtrBlockMapEntry;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- EFI_STATUSStatus;
- UINTN BufferSize;
- UINTN Idx;
- UINT32MaxLbaSize;
- UINT32BytesWritten;
- UINTN BytesErased;
- UINT64NvStorageFvSize;
+ EFI_FVB_INSTANCE*FvbInstance;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;
+ EFI_PHYSICAL_ADDRESSBaseAddress;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ UINTN Idx;
+ UINT32 MaxLbaSize;
+ UINT32 BytesWritten;
+ UINTN BytesErased;
+ UINT64 NvStorageFvSize;
+ UINT32 ExpectedBytesWritten;
+ VARIA
Re: [edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Thanks for the good catch Ashraf!
I have sent V2 patch for addressing your feedbacks, please help to review again.
Thanks,
Chasel
> -Original Message-
> From: S, Ashraf Ali
> Sent: Saturday, February 4, 2023 8:03 AM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Oram, Isaac W ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: RE: [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm:
> Rewrite VariableStore header.
>
> Hi., Chasel
>
> If the NvStoreBuffer AllocateZeroPool failed then Status variable needs to
> updated.
> Can we have some meaning full debug message rather than just printing the
> GUID name.
> ExpectedBytesWritten will be uninitialed when NvStoreBuffer allocation fails.
> Due to which comparison of BytesWritten and ExpectedBytesWritten will be
> incorrect.
>
>
> -Original Message-
> From: Chiu, Chasel
> Sent: Saturday, February 4, 2023 3:25 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; S, Ashraf Ali
> ;
> Oram, Isaac W ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite
> VariableStore header.
>
> When invalid VariableStore FV header detected, current SpiFvbService will
> erase
> both FV and VariableStore headers from flash, however, it will only rewrite FV
> header back and cause invalid VariableStore header.
>
> This patch adding the support for rewriting both FV header and VariableStore
> header when VariableStore corruption happened.
>
> Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which
> VariableStoreType should be rewritten.
>
> Cc: Ashraf Ali S
> Cc: Isaac Oram
> Cc: Rangasai V Chaganty
> Cc: Ray Ni
> Cc: Michael Kubacki
> Signed-off-by: Chasel Chiu
> ---
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> |
> 172
> +
> +++---
> -
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 4
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> | 8
> 3 files changed, 132 insertions(+), 52 deletions(-)
>
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> index 6b4bcdcfe3..f29540c62c 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
> +++ rviceMm.c
> @@ -12,6 +12,7 @@
> #include #include
> #include
> +#include
> /** The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol@@ -25,12
> +26,12 @@
> **/ VOID InstallFvbProtocol (- IN EFI_FVB_INSTANCE
> *FvbInstance+ IN
> EFI_FVB_INSTANCE *FvbInstance ) {- EFI_FIRMWARE_VOLUME_HEADER
> *FvHeader;- EFI_STATUSStatus;- EFI_HANDLE
> FvbHandle;+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;+ EFI_STATUS
> Status;+ EFI_HANDLE FvbHandle;ASSERT (FvbInstance !=
> NULL); if
> (FvbInstance == NULL) {@@ -52,19 +53,21 @@ InstallFvbProtocol (
> // // FV does not contains extension header, then produce
> MEMMAP_DEVICE_PATH //-FvbInstance->DevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof
> (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplate);+
> FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
> *)AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
> &mFvMemmapDevicePathTemplate); if (FvbInstance->DevicePath == NULL)
> { DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
> MEMMAP_DEVICE_PATH failed\n")); return; }-
> ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)-
> >MemMapDevPath.StartingAddress = FvbInstance->FvBase;-
> ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)-
> >MemMapDevPath.EndingAddress = FvbInstance->FvBase + FvHeader-
> >FvLength - 1;++((FV_MEMMAP_DEVICE_PATH *)FvbInstance->DevicePath)-
> >MemMapDevPath.StartingAddress = FvbInstance->FvBase;+
> ((FV_MEMMAP_DEVICE_PATH *)FvbInstance->DevicePath)-
> >MemMapDevPath.EndingAddress = FvbInstance->FvBase + FvHeader-
> >FvLength - 1; } else {-FvbInstance->DevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof
> (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate);+FvbInstance-
> >DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Allo
[edk2-devel] [edk2-platforms: PATCH v3] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
When invalid VariableStore FV header detected, current SpiFvbService
will erase both FV and VariableStore headers from flash, however,
it will only rewrite FV header back and cause invalid VariableStore
header.
This patch adding the support for rewriting both FV header and
VariableStore header when VariableStore corruption happened.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
which VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 64 +++-
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 4
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 71 insertions(+), 5 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..6338442e1a 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/**
The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
@@ -114,6 +115,10 @@ FvbInitialize (
UINT32BytesWritten;
UINTN BytesErased;
UINT64NvStorageFvSize;
+ UINT32ExpectedBytesWritten;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINT8 VariableStoreType;
+ UINT8 *NvStoreBuffer;
Status = GetVariableFlashNvStorageInfo (&BaseAddress, &NvStorageFvSize);
if (EFI_ERROR (Status)) {
@@ -186,8 +191,57 @@ FvbInitialize (
}
continue;
}
-BytesWritten = FvHeader->HeaderLength;
-Status = SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten,
(UINT8*)FvHeader);
+
+BytesWritten = FvHeader->HeaderLength;
+ExpectedBytesWritten = BytesWritten;
+if (Idx != 0) {
+ Status = SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten, (UINT8
*)FvHeader);
+} else {
+ //
+ // This is Variable Store, rewrite both EFI_FIRMWARE_VOLUME_HEADER
and VARIABLE_STORE_HEADER
+ //
+ NvStoreBuffer = NULL;
+ NvStoreBuffer = AllocateZeroPool (sizeof (VARIABLE_STORE_HEADER) +
FvHeader->HeaderLength);
+ if (NvStoreBuffer != NULL) {
+//
+// Combine FV header and VariableStore header into the buffer.
+//
+CopyMem (NvStoreBuffer, FvHeader, FvHeader->HeaderLength);
+VariableStoreHeader = (VARIABLE_STORE_HEADER *)(NvStoreBuffer +
FvHeader->HeaderLength);
+VariableStoreType = PcdGet8 (PcdFlashVariableStoreType);
+switch (VariableStoreType) {
+ case 0:
+DEBUG ((DEBUG_ERROR, "Type: gEfiVariableGuid\n"));
+CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
+break;
+ case 1:
+DEBUG ((DEBUG_ERROR, "Type: gEfiAuthenticatedVariableGuid\n"));
+CopyGuid (&VariableStoreHeader->Signature,
&gEfiAuthenticatedVariableGuid);
+break;
+ default:
+break;
+}
+
+//
+// Initialize common VariableStore header fields
+//
+VariableStoreHeader->Size = PcdGet32
(PcdFlashNvStorageVariableSize) - FvHeader->HeaderLength;
+VariableStoreHeader->Format= VARIABLE_STORE_FORMATTED;
+VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+VariableStoreHeader->Reserved = 0;
+VariableStoreHeader->Reserved1 = 0;
+//
+// Write buffer to flash
+//
+BytesWritten = FvHeader->HeaderLength + sizeof
(VARIABLE_STORE_HEADER);
+ExpectedBytesWritten = BytesWritten;
+Status = SpiFlashWrite ((UINTN)BaseAddress,
&BytesWritten, NvStoreBuffer);
+FreePool (NvStoreBuffer);
+ } else {
+Status = EFI_OUT_OF_RESOURCES;
+ }
+}
+
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "ERROR - SpiFlashWrite Error %r\n", Status));
if (FvHeader != NULL) {
@@ -195,9 +249,9 @@ FvbInitialize (
}
continue;
}
-if (BytesWritten != FvHeader->HeaderLength) {
- DEBUG ((DEBUG_WARN, "ERROR - BytesWritten != HeaderLength\n"));
- DEBUG ((DEBUG_INFO, " BytesWritten = 0x%X\n HeaderLength = 0x%X\n",
B
Re: [edk2-devel] [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Hello,
I have sent a V3 patch to remove Uncrustify coding style changes. We will do
coding style changes separately later.
Please help to review V3 patch.
Thanks,
Chasel
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chiu, Chasel
> Sent: Monday, February 6, 2023 10:50 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; S, Ashraf Ali
> ;
> Oram, Isaac W ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: [edk2-devel] [edk2-platforms: PATCH v2]
> IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
>
> When invalid VariableStore FV header detected, current SpiFvbService will
> erase
> both FV and VariableStore headers from flash, however, it will only rewrite FV
> header back and cause invalid VariableStore header.
>
> This patch adding the support for rewriting both FV header and VariableStore
> header when VariableStore corruption happened.
>
> Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which
> VariableStoreType should be rewritten.
>
> Cc: Ashraf Ali S
> Cc: Isaac Oram
> Cc: Rangasai V Chaganty
> Cc: Ray Ni
> Cc: Michael Kubacki
> Signed-off-by: Chasel Chiu
> ---
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> |
> 174
> +
> +
>
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 4
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> | 8
> 3 files changed, 134 insertions(+), 52 deletions(-)
>
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> index 6b4bcdcfe3..6af2dfac10 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
> +++ rviceMm.c
> @@ -12,6 +12,7 @@
> #include #include
> #include
> +#include
> /** The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol@@ -25,12
> +26,12 @@
> **/ VOID InstallFvbProtocol (- IN EFI_FVB_INSTANCE
> *FvbInstance+ IN
> EFI_FVB_INSTANCE *FvbInstance ) {- EFI_FIRMWARE_VOLUME_HEADER
> *FvHeader;- EFI_STATUSStatus;- EFI_HANDLE
> FvbHandle;+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;+ EFI_STATUS
> Status;+ EFI_HANDLE FvbHandle;ASSERT (FvbInstance !=
> NULL); if
> (FvbInstance == NULL) {@@ -52,19 +53,21 @@ InstallFvbProtocol (
> // // FV does not contains extension header, then produce
> MEMMAP_DEVICE_PATH //-FvbInstance->DevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof
> (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplate);+
> FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL
> *)AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
> &mFvMemmapDevicePathTemplate); if (FvbInstance->DevicePath == NULL)
> { DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for
> MEMMAP_DEVICE_PATH failed\n")); return; }-
> ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)-
> >MemMapDevPath.StartingAddress = FvbInstance->FvBase;-
> ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)-
> >MemMapDevPath.EndingAddress = FvbInstance->FvBase + FvHeader-
> >FvLength - 1;++((FV_MEMMAP_DEVICE_PATH *)FvbInstance->DevicePath)-
> >MemMapDevPath.StartingAddress = FvbInstance->FvBase;+
> ((FV_MEMMAP_DEVICE_PATH *)FvbInstance->DevicePath)-
> >MemMapDevPath.EndingAddress = FvbInstance->FvBase + FvHeader-
> >FvLength - 1; } else {-FvbInstance->DevicePath =
> (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof
> (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate);+FvbInstance-
> >DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)AllocateRuntimeCopyPool
> (sizeof (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate); if
> (FvbInstance->DevicePath == NULL) { DEBUG ((DEBUG_INFO,
> "SpiFvbServiceSmm.c: Memory allocation for FV_PIWG_DEVICE_PATH
> failed\n")); return; }+ CopyGuid ( &((FV_PIWG_DEVICE_PATH
> *)FvbInstance->DevicePath)->FvDevPath.FvName, (GUID
> *)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset)@@ -103,17
> +106,21 @@ FvbInitialize (
>VOID ) {- EFI_FVB_INSTANCE *FvbInstance;-
> EFI_FIRMWARE_VOLUME_HEADER*FvHeader;-
> EFI_FV
[edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
When invalid VariableStore FV header detected, current SpiFvbService
will erase both FV and VariableStore headers from flash, however,
it will only rewrite FV header back and cause invalid VariableStore
header.
This patch adding the support for rewriting both FV header and
VariableStore header when VariableStore corruption happened.
The Corrupted variable content should be taken care by
FaultTolerantWrite driver later.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
which VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 69 -
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 3 +++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 75 insertions(+), 5 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..052be97872 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/**
The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
@@ -113,7 +114,12 @@ FvbInitialize (
UINT32MaxLbaSize;
UINT32BytesWritten;
UINTN BytesErased;
+ EFI_PHYSICAL_ADDRESS NvStorageBaseAddress;
UINT64NvStorageFvSize;
+ UINT32ExpectedBytesWritten;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINT8 VariableStoreType;
+ UINT8 *NvStoreBuffer;
Status = GetVariableFlashNvStorageInfo (&BaseAddress, &NvStorageFvSize);
if (EFI_ERROR (Status)) {
@@ -124,12 +130,14 @@ FvbInitialize (
// Stay within the current UINT32 size assumptions in the variable stack.
Status = SafeUint64ToUint32 (BaseAddress, &mPlatformFvBaseAddress[0].FvBase);
+ NvStorageBaseAddress = mPlatformFvBaseAddress[0].FvBase;
if (EFI_ERROR (Status)) {
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_ERROR, "[%a] - 64-bit variable storage base address not
supported.\n", __FUNCTION__));
return;
}
Status = SafeUint64ToUint32 (NvStorageFvSize,
&mPlatformFvBaseAddress[0].FvSize);
+ NvStorageFvSize = mPlatformFvBaseAddress[0].FvSize;
if (EFI_ERROR (Status)) {
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_ERROR, "[%a] - 64-bit variable storage size not
supported.\n", __FUNCTION__));
@@ -186,8 +194,59 @@ FvbInitialize (
}
continue;
}
-BytesWritten = FvHeader->HeaderLength;
-Status = SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten,
(UINT8*)FvHeader);
+
+BytesWritten = FvHeader->HeaderLength;
+ExpectedBytesWritten = BytesWritten;
+if (BaseAddress != NvStorageBaseAddress) {
+ Status = SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten, (UINT8
*)FvHeader);
+} else {
+ //
+ // This is Variable Store, rewrite both EFI_FIRMWARE_VOLUME_HEADER
and VARIABLE_STORE_HEADER.
+ // The corrupted Variable content should be taken care by
FaultTolerantWrite driver later.
+ //
+ NvStoreBuffer = NULL;
+ NvStoreBuffer = AllocateZeroPool (sizeof (VARIABLE_STORE_HEADER) +
FvHeader->HeaderLength);
+ if (NvStoreBuffer != NULL) {
+//
+// Combine FV header and VariableStore header into the buffer.
+//
+CopyMem (NvStoreBuffer, FvHeader, FvHeader->HeaderLength);
+VariableStoreHeader = (VARIABLE_STORE_HEADER *)(NvStoreBuffer +
FvHeader->HeaderLength);
+VariableStoreType = PcdGet8 (PcdFlashVariableStoreType);
+switch (VariableStoreType) {
+ case 0:
+DEBUG ((DEBUG_ERROR, "Type: gEfiVariableGuid\n"));
+CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
+break;
+ case 1:
+DEBUG ((DEBUG_ERROR, "Type: gEfiAuthenticatedVariableGuid\n"));
+CopyGuid (&VariableStoreHeader->Signature,
&gEfiAuthenticatedVariableGuid);
+break;
+ default:
+break;
+}
+
+//
+// Initialize common VariableStore header fields
+//
+VariableStoreHeader->Size = (UINT32) (NvStorageFvSize -
FvHeader->HeaderLength);
+VariableStoreHeader->Format= VARIABLE_S
Re: [edk2-devel] [edk2-platforms: PATCH v3] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Thanks for reviewing Michael. Please see my reply below inline and help to review V4 patch again. Thanks, Chasel > -Original Message- > From: Michael Kubacki > Sent: Tuesday, February 7, 2023 12:22 PM > To: devel@edk2.groups.io; Chiu, Chasel > Cc: S, Ashraf Ali ; Oram, Isaac W > ; Chaganty, Rangasai V > ; Ni, Ray ; Kubacki, > Michael > Subject: Re: [edk2-devel] [edk2-platforms: PATCH v3] > IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header. > > Hi Chasel, > > I agree with the high-level problem. Here's some observations. > > 1. I'm not a big fan of implicitly associating index zero of the > mPlatformFvBaseAddress array as the variable FV entry. It could be easy for > that > to silently get out of sync in the future. > > Perhaps you could check if the base address at a given index equals the > variable > store address since it is retrieved via > GetVariableFlashNvStorageInfo() at the beginning of FvbInitialize(). > Done in V4 > 2. VariableFlashInfoLib is meant to abstract var store info with > GetVariableFlashNvStorageInfo(). > > Please use that instead of directly getting it with PcdGet32 > (PcdFlashNvStorageVariableSize). > Done in V4 > 3. Suggest a blank link before the following text for readability. > > // > // Write buffer to flash > // > Done in V4 > 4. Usually there's a few default variables in the var store FV that form a > foundation that the variable HOB gets written upon when the HOB gets flushed. > Does the original var store FV still contain some of those entries? If so, > this just > restores an empty store, so those are known to be lost, right? > > If that's true, please call it out in the patch description. > Since SpiFvbService driver only needs VariableStore information, it should only rewrite FV and VariableStore headers. I added comments in code and commit message to mention about "the corrupted variable content should be taken care by FaultTolerantWrite driver later". Please see if this I good enough. > Thanks, > Michael > > On 2/7/2023 2:42 PM, Chiu, Chasel wrote: > > When invalid VariableStore FV header detected, current SpiFvbService > > will erase both FV and VariableStore headers from flash, however, it > > will only rewrite FV header back and cause invalid VariableStore > > header. > > > > This patch adding the support for rewriting both FV header and > > VariableStore header when VariableStore corruption happened. > > > > Platform has to set PcdFlashVariableStoreType to inform SpiFvbService > > which VariableStoreType should be rewritten. > > > > Cc: Ashraf Ali S > > Cc: Isaac Oram > > Cc: Rangasai V Chaganty > > Cc: Ray Ni > > Cc: Michael Kubacki > > Signed-off-by: Chasel Chiu > > --- > > > > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c > | 64 +++--- > -- > > > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf > | 4 > > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > > | 8 > > 3 files changed, 71 insertions(+), 5 deletions(-) > > > > diff --git > > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ > > iceMm.c > > b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ > > iceMm.c > > index 6b4bcdcfe3..6338442e1a 100644 > > --- > > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ > > iceMm.c > > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvb > > +++ ServiceMm.c > > @@ -12,6 +12,7 @@ > > #include > > > > #include > > > > #include > > > > +#include > > > > > > > > /** > > > > The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol > > > > @@ -114,6 +115,10 @@ FvbInitialize ( > > UINT32BytesWritten; > > > > UINTN BytesErased; > > > > UINT64NvStorageFvSize; > > > > + UINT32ExpectedBytesWritten; > > > > + VARIABLE_STORE_HEADER *VariableStoreHeader; > > > > + UINT8 VariableStoreType; > > > > + UINT8 *NvStoreBuffer; > > > > > > > > Status = GetVariableFlashNvStorageInfo (&BaseAddress, > >
Re: [edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Thanks Michael! I will apply the change during merging!
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Michael
> Kubacki
> Sent: Wednesday, February 8, 2023 4:41 PM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: S, Ashraf Ali ; Oram, Isaac W
> ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: Re: [edk2-devel] [edk2-platforms: PATCH v4]
> IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
>
> Reviewed-by: Michael Kubacki
>
> On the following lines, I recommend moving the assignment until after the if
> block. It seems unnecessary to assign a potentially invalid value to a local
> variable before checking the validation result.
>
>Status = SafeUint64ToUint32 (BaseAddress,
> &mPlatformFvBaseAddress[0].FvBase);
>NvStorageBaseAddress = mPlatformFvBaseAddress[0].FvBase;
>if (EFI_ERROR (Status)) {
> ASSERT_EFI_ERROR (Status);
> DEBUG ((DEBUG_ERROR, "[%a] - 64-bit variable storage base address not
> supported.\n", __FUNCTION__));
> return;
>}
>
> ---
>
> (similar for NvStorageFvSize)
>
> Thanks,
> Michael
>
> On 2/8/2023 5:17 PM, Chiu, Chasel wrote:
> > When invalid VariableStore FV header detected, current SpiFvbService
> > will erase both FV and VariableStore headers from flash, however, it
> > will only rewrite FV header back and cause invalid VariableStore
> > header.
> >
> > This patch adding the support for rewriting both FV header and
> > VariableStore header when VariableStore corruption happened.
> > The Corrupted variable content should be taken care by
> > FaultTolerantWrite driver later.
> >
> > Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
> > which VariableStoreType should be rewritten.
> >
> > Cc: Ashraf Ali S
> > Cc: Isaac Oram
> > Cc: Rangasai V Chaganty
> > Cc: Ray Ni
> > Cc: Michael Kubacki
> > Signed-off-by: Chasel Chiu
> > ---
> >
> > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> | 69
> --
> ---
> >
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 3 +++
> > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> > | 8
> > 3 files changed, 75 insertions(+), 5 deletions(-)
> >
> > diff --git
> > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > index 6b4bcdcfe3..052be97872 100644
> > ---
> > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvb
> > +++ ServiceMm.c
> > @@ -12,6 +12,7 @@
> > #include
> >
> > #include
> >
> > #include
> >
> > +#include
> >
> >
> >
> > /**
> >
> > The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
> >
> > @@ -113,7 +114,12 @@ FvbInitialize (
> > UINT32MaxLbaSize;
> >
> > UINT32BytesWritten;
> >
> > UINTN BytesErased;
> >
> > + EFI_PHYSICAL_ADDRESS NvStorageBaseAddress;
> >
> > UINT64NvStorageFvSize;
> >
> > + UINT32ExpectedBytesWritten;
> >
> > + VARIABLE_STORE_HEADER *VariableStoreHeader;
> >
> > + UINT8 VariableStoreType;
> >
> > + UINT8 *NvStoreBuffer;
> >
> >
> >
> > Status = GetVariableFlashNvStorageInfo (&BaseAddress,
> > &NvStorageFvSize);
> >
> > if (EFI_ERROR (Status)) {
> >
> > @@ -124,12 +130,14 @@ FvbInitialize (
> >
> >
> > // Stay within the current UINT32 size assumptions in the variable
> > stack.
> >
> > Status = SafeUint64ToUint32 (BaseAddress,
> > &mPlatformFvBaseAddress[0].FvBase);
> >
> > + NvStorageBaseAddress = mPlatformFvBaseAddress[0].FvBase;
> >
> > if (EFI_ERROR (Status)) {
> >
> > ASSERT_EFI_ERROR (Status);
> >
> > DEBUG ((DEBUG_ERROR, "[%a] - 64-bit variable storage base
> > address not supported.\n", __FUNCTION__));
> >
> > return;
> >
Re: [edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Thanks Isaac!
> -Original Message-
> From: Oram, Isaac W
> Sent: Wednesday, February 8, 2023 5:39 PM
> To: devel@edk2.groups.io; mikub...@linux.microsoft.com; Chiu, Chasel
>
> Cc: S, Ashraf Ali ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: RE: [edk2-devel] [edk2-platforms: PATCH v4]
> IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
>
> Reviewed-by: Isaac Oram
>
> At some point, we should work to comment the related flows better so that
> code is clear on the different responsibilities for the different paths
> through first
> boots, normal scenarios, reclaims, and error remediation. For now though,
> this
> is fine.
>
> Regards,
> Isaac
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Michael
> Kubacki
> Sent: Wednesday, February 8, 2023 4:41 PM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: S, Ashraf Ali ; Oram, Isaac W
> ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: Re: [edk2-devel] [edk2-platforms: PATCH v4]
> IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
>
> Reviewed-by: Michael Kubacki
>
> On the following lines, I recommend moving the assignment until after the if
> block. It seems unnecessary to assign a potentially invalid value to a local
> variable before checking the validation result.
>
>Status = SafeUint64ToUint32 (BaseAddress,
> &mPlatformFvBaseAddress[0].FvBase);
>NvStorageBaseAddress = mPlatformFvBaseAddress[0].FvBase;
>if (EFI_ERROR (Status)) {
> ASSERT_EFI_ERROR (Status);
> DEBUG ((DEBUG_ERROR, "[%a] - 64-bit variable storage base address not
> supported.\n", __FUNCTION__));
> return;
>}
>
> ---
>
> (similar for NvStorageFvSize)
>
> Thanks,
> Michael
>
> On 2/8/2023 5:17 PM, Chiu, Chasel wrote:
> > When invalid VariableStore FV header detected, current SpiFvbService
> > will erase both FV and VariableStore headers from flash, however, it
> > will only rewrite FV header back and cause invalid VariableStore
> > header.
> >
> > This patch adding the support for rewriting both FV header and
> > VariableStore header when VariableStore corruption happened.
> > The Corrupted variable content should be taken care by
> > FaultTolerantWrite driver later.
> >
> > Platform has to set PcdFlashVariableStoreType to inform SpiFvbService
> > which VariableStoreType should be rewritten.
> >
> > Cc: Ashraf Ali S
> > Cc: Isaac Oram
> > Cc: Rangasai V Chaganty
> > Cc: Ray Ni
> > Cc: Michael Kubacki
> > Signed-off-by: Chasel Chiu
> > ---
> >
> > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> | 69
> --
> ---
> >
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 3 +++
> > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> > | 8
> > 3 files changed, 75 insertions(+), 5 deletions(-)
> >
> > diff --git
> > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > index 6b4bcdcfe3..052be97872 100644
> > ---
> > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServ
> > iceMm.c
> > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvb
> > +++ ServiceMm.c
> > @@ -12,6 +12,7 @@
> > #include
> >
> > #include
> >
> > #include
> >
> > +#include
> >
> >
> >
> > /**
> >
> > The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol
> >
> > @@ -113,7 +114,12 @@ FvbInitialize (
> > UINT32MaxLbaSize;
> >
> > UINT32BytesWritten;
> >
> > UINTN BytesErased;
> >
> > + EFI_PHYSICAL_ADDRESS NvStorageBaseAddress;
> >
> > UINT64NvStorageFvSize;
> >
> > + UINT32ExpectedBytesWritten;
> >
> > + VARIABLE_STORE_HEADER *VariableStoreHeader;
> >
> > + UINT8 VariableStoreType;
> >
> > + UINT8 *NvStoreBuffer;
> >
> >
> >
> > Status = GetVariableFlashNvStorageInfo (&BaseAddress,
> > &NvStorageFvSize);
Re: [edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
Bug fix patch has been merged:
https://github.com/tianocore/edk2-platforms/commit/e95c7988994c73918ffa282e2d2f5af11f8addc4
Thanks,
Chasel
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chiu, Chasel
> Sent: Wednesday, February 8, 2023 2:17 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; S, Ashraf Ali
> ;
> Oram, Isaac W ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: [edk2-devel] [edk2-platforms: PATCH v4]
> IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.
>
> When invalid VariableStore FV header detected, current SpiFvbService will
> erase
> both FV and VariableStore headers from flash, however, it will only rewrite FV
> header back and cause invalid VariableStore header.
>
> This patch adding the support for rewriting both FV header and VariableStore
> header when VariableStore corruption happened.
> The Corrupted variable content should be taken care by FaultTolerantWrite
> driver later.
>
> Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which
> VariableStoreType should be rewritten.
>
> Cc: Ashraf Ali S
> Cc: Isaac Oram
> Cc: Rangasai V Chaganty
> Cc: Ray Ni
> Cc: Michael Kubacki
> Signed-off-by: Chasel Chiu
> ---
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> |
> 69
> --
> ---
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 3 +++
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> | 8
> 3 files changed, 75 insertions(+), 5 deletions(-)
>
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> index 6b4bcdcfe3..052be97872 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
> +++ rviceMm.c
> @@ -12,6 +12,7 @@
> #include #include
> #include
> +#include
> /** The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol@@ -113,7
> +114,12 @@ FvbInitialize (
>UINT32MaxLbaSize; UINT32
>BytesWritten;
> UINTN BytesErased;+ EFI_PHYSICAL_ADDRESS
> NvStorageBaseAddress; UINT64
> NvStorageFvSize;+ UINT32
> ExpectedBytesWritten;+ VARIABLE_STORE_HEADER
> *VariableStoreHeader;+ UINT8
> VariableStoreType;+ UINT8
> *NvStoreBuffer;Status = GetVariableFlashNvStorageInfo (&BaseAddress,
> &NvStorageFvSize); if (EFI_ERROR (Status)) {@@ -124,12 +130,14 @@
> FvbInitialize (
> // Stay within the current UINT32 size assumptions in the variable stack.
> Status = SafeUint64ToUint32 (BaseAddress,
> &mPlatformFvBaseAddress[0].FvBase);+ NvStorageBaseAddress =
> mPlatformFvBaseAddress[0].FvBase; if (EFI_ERROR (Status))
> { ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_ERROR, "[%a] - 64-bit
> variable storage base address not supported.\n", __FUNCTION__)); return;
> }
> Status = SafeUint64ToUint32 (NvStorageFvSize,
> &mPlatformFvBaseAddress[0].FvSize);+ NvStorageFvSize =
> mPlatformFvBaseAddress[0].FvSize; if (EFI_ERROR (Status))
> { ASSERT_EFI_ERROR (Status); DEBUG ((DEBUG_ERROR, "[%a] - 64-bit
> variable storage size not supported.\n", __FUNCTION__));@@ -186,8 +194,59
> @@ FvbInitialize (
>} continue; }-BytesWritten =
> FvHeader->HeaderLength;-
> Status = SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten,
> (UINT8*)FvHeader);++BytesWritten = FvHeader->HeaderLength;+
> ExpectedBytesWritten = BytesWritten;+if (BaseAddress !=
> NvStorageBaseAddress) {+ Status = SpiFlashWrite ((UINTN)BaseAddress,
> &BytesWritten, (UINT8 *)FvHeader);+} else {+ //+ //
> This is
> Variable Store, rewrite both EFI_FIRMWARE_VOLUME_HEADER and
> VARIABLE_STORE_HEADER.+ // The corrupted Variable content should be
> taken care by FaultTolerantWrite driver later.+ //+
> NvStoreBuffer =
> NULL;+ NvStoreBuffer = AllocateZeroPool (sizeof
> (VARIABLE_STORE_HEADER) + FvHeader->HeaderLength);+ if
> (NvStoreBuffer != NULL) {+//+// Combine FV header and
> VariableStore header into the buffer.+//+CopyMem
> (NvStoreBuffer,
> FvHeader, FvHeader->HeaderLength);+VariableStoreHeader =
> (VARIABLE_ST
[edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region.
Platform may implement Other NVS variable region following Regular
variable region and in this case SpiFvbService should include both
region size when calculating the total NVS region size.
One usage model is EventLog NVS region and there could be others.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
| 7 +++
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 7 ---
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
index 942abf95a6..bcde98131d 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
@@ -568,6 +568,13 @@ GetVariableFvInfo (
return;
}
+ //
+ // GetVariableFlashNvStorageInfo () only reports regular variable region
information,
+ // if platform implemented a separate Other variable region following the
regular variable region,
+ // the size should be included as overall NVS variable region size.
+ //
+ NvStoreLength += PcdGet32 (PcdFlashNvStorageOtherVariableSize);
+
Status = GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64);
if (!EFI_ERROR (Status)) {
// Stay within the current UINT32 size assumptions in the variable stack.
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
index 73049eceb2..f40067418a 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
@@ -43,9 +43,10 @@
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageOtherVariableSize ## CONSUMES
[Sources]
FvbInfo.c
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 63dae756ad..7034ab93b0 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -194,3 +194,11 @@
# Other value: reserved for future use.
# @Prompt Flash Variable Store type.
gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x000E
+
+ ## Declares Separate NVS Variable Region Size.
+ # Platform may implement a Regular variable region and an Other variable
region, which will require this PCD
+ # to tell SpiFvbService to include both regions.
+ # 0: No separate Other variable region.
+ # non-zero: The size of a separate Other variable region following the
Regular variable region.
+ # @Prompt Separate NVS Variable Region Size.
+
gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageOtherVariableSize|0x|UINT32|0x000F
--
2.35.0.windows.1
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[edk2-devel] [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Support Additional NVS region.
Platform may implement an additional NVS region following
Regular variable region and in this case SpiFvbService should include
both region size when calculating the total NVS region size.
One usage model is EventLog NVS region and there could be others.
Example NVS flash map for such usage model:
--
|UEI Variable|
--
|EventLog| <= this is Additional variable region
--
|FTW Working |
--
|FTW Spare |
--
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
| 17 +
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 7 ---
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
index 942abf95a6..7be8d9319c 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
@@ -568,6 +568,23 @@ GetVariableFvInfo (
return;
}
+ //
+ // GetVariableFlashNvStorageInfo () only reports regular variable region
information,
+ // if platform implemented an additional NVS region following the regular
variable region,
+ // the both region size should be included as overall NVS region size.
+ // Example NVS flash map for such usage model:
+ // --
+ // |UEI Variable|
+ // --
+ // |EventLog| <= this is Additional variable region
+ // --
+ // |FTW Working |
+ // --
+ // |FTW Spare |
+ // --
+ //
+ NvStoreLength += PcdGet32 (PcdFlashNvStorageAdditionalSize);
+
Status = GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64);
if (!EFI_ERROR (Status)) {
// Stay within the current UINT32 size assumptions in the variable stack.
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
index 73049eceb2..f4009d8d8c 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
@@ -43,9 +43,10 @@
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize## CONSUMES
[Sources]
FvbInfo.c
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 63dae756ad..b10529b69d 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -194,3 +194,11 @@
# Other value: reserved for future use.
# @Prompt Flash Variable Store type.
gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x000E
+
+ ## Declares Additional NVS Variable Region Size.
+ # Platform may implement a Regular variable region and an additional
variable region, which will require this PCD
+ # to tell SpiFvbService to include both regions.
+ # 0: No additional variable region.
+ # non-zero: The size of an additional variable region following the Regular
variable region.
+ # @Prompt Additional NVS Variable Region Size.
+
gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize|0x|UINT32|0x000F
--
2.35.0.windows.1
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[edk2-devel] [edk2-platforms: PATCH v3] IntelSiliconPkg/SpiFvbServiceSmm: Support Additional NVS region.
Platform may implement an additional NVS region following
Regular variable region and in this case SpiFvbService should include
both region size when calculating the total NVS region size.
One usage model is EventLog NVS region and there could be others.
Example NVS flash map for such usage model:
--
|UEI Variable|
--
|EventLog| <= this is Additional NVS region
--
|FTW Working |
--
|FTW Spare |
--
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
| 17 +
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 7 ---
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 8
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
index 942abf95a6..cf5a40bf27 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
@@ -568,6 +568,23 @@ GetVariableFvInfo (
return;
}
+ //
+ // GetVariableFlashNvStorageInfo () only reports regular variable region
information,
+ // if platform implemented an additional NVS region following the regular
variable region,
+ // the both region size should be included as overall NVS region size.
+ // Example NVS flash map for such usage model:
+ // --
+ // |UEI Variable|
+ // --
+ // |EventLog| <= this is Additional NVS region
+ // --
+ // |FTW Working |
+ // --
+ // |FTW Spare |
+ // --
+ //
+ NvStoreLength += PcdGet32 (PcdFlashNvStorageAdditionalSize);
+
Status = GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64);
if (!EFI_ERROR (Status)) {
// Stay within the current UINT32 size assumptions in the variable stack.
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
index 73049eceb2..f4009d8d8c 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
@@ -43,9 +43,10 @@
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize## CONSUMES
[Sources]
FvbInfo.c
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 63dae756ad..b10529b69d 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -194,3 +194,11 @@
# Other value: reserved for future use.
# @Prompt Flash Variable Store type.
gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x000E
+
+ ## Declares Additional NVS Variable Region Size.
+ # Platform may implement a Regular variable region and an additional
variable region, which will require this PCD
+ # to tell SpiFvbService to include both regions.
+ # 0: No additional variable region.
+ # non-zero: The size of an additional variable region following the Regular
variable region.
+ # @Prompt Additional NVS Variable Region Size.
+
gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize|0x|UINT32|0x000F
--
2.35.0.windows.1
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Re: [edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region.
Thanks for good suggestions Isaac and Michael! I have sent V3 patch to apply all the suggestions, please help to review again. Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of Michael > Kubacki > Sent: Thursday, February 9, 2023 8:47 AM > To: devel@edk2.groups.io; Oram, Isaac W ; Chiu, > Chasel > Cc: S, Ashraf Ali ; Chaganty, Rangasai V > ; Ni, Ray ; Kubacki, > Michael > Subject: Re: [edk2-devel] [edk2-platforms: PATCH] > IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. > > Thanks, that's useful background. @chasel, you should probably put this info > in > the commit message so it is captured in source history. > > Given the default value is zero, it seems reasonable. I was also initially > confused > by the name of the PCD. > > Another idea would be something like "PcdFlashNvStorageAdditionalSize". > > Please do at least update the commit message to include additional context. > > Reviewed-by: Michael Kubacki > > On 2/9/2023 11:04 AM, Isaac Oram wrote: > > It is a legacy that exists in current and past implementations. There is a > complex arbitrary relationship between the runtime updateable regions in > existing platform designs. > > There is something like: > > - Variable store (large) > > - Error log (small) > > - Fault tolerant working area (>= size of prior 2 regions) > > - Fault tolerant metadata (small). > > And there are assumptions about ordering and packing built into board flash > layouts. > > > > I don't think that we should introduce "other variable" as a concept, > > because > variable solutions don't support two regions, so it isn't a UEFI variable > region. > OtherUpdatable might be ok, but still seems confusing to me. > > I think that we should add the support for the *ErrorLog* region so that the > open FvbServices can be used by current implementations. Then we should > eliminate the "ErrorLog" use completely. My thought is that this makes the > connection to legacy clear. And also motivates us to eliminate all the > vestigial > references to the ErrorLog in edk2 and edk2-platforms. > > > > New updateable regions should not be hard-coded into this area and should > have a cleaner solution, as Michael suggests. > > > > I understand if we don't want to support legacy or workarounds, but I think > that currently adoption and use of the open content is higher priority. > Which is > why we are requesting this workaround to match "proprietary" FVB services > behavior. > > > > Regards, > > Isaac > > > > -Original Message- > > From: Michael Kubacki > > Sent: Thursday, February 9, 2023 7:40 AM > > To: devel@edk2.groups.io; Chiu, Chasel > > Cc: S, Ashraf Ali ; Oram, Isaac W > > ; Chaganty, Rangasai V > > ; Ni, Ray ; Kubacki, > > Michael > > Subject: Re: [edk2-devel] [edk2-platforms: PATCH] > IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. > > > > Is there a reason this other content can't go into it's own FV? > > > > On 2/9/2023 12:14 AM, Chiu, Chasel wrote: > >> Platform may implement Other NVS variable region following Regular > >> variable region and in this case SpiFvbService should include both > >> region size when calculating the total NVS region size. > >> > >> One usage model is EventLog NVS region and there could be others. > >> > >> Cc: Ashraf Ali S > >> Cc: Isaac Oram > >> Cc: Rangasai V Chaganty > >> Cc: Ray Ni > >> Cc: Michael Kubacki > >> Signed-off-by: Chasel Chiu > >> --- > >> > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon > .c | 7 +++ > >> > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf > | 7 --- > >>Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > >> | 8 > > >>3 files changed, 19 insertions(+), 3 deletions(-) > >> > >> diff --git > >> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer > >> v > >> iceCommon.c > >> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer > >> v > >> iceCommon.c > >> index 942abf95a6..bcde98131d 100644 > >> --- > >> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer > >> v > >> iceCommon.c > >> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/F
[edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Support Additional NVS region.
Platform may implement an additional NVS region following
Regular variable region and in this case SpiFvbService should include
both region size when calculating the total NVS region size.
The PcdFlashNvStorageAdditionalSize is for compatible with legacy
usages that should be deprecated. The new usage model should define
separate regions without implicit connections to UEFI Variable or
FTW regions.
Example NVS flash map for such legacy usage:
Note: PcdFlashNvStorageAdditionalSize is equal to platform
PcdFlashFvNvStorageEventLogSize.
---
|UEFI Variable|
---
|EventLog | <= this is Additional NVS region
---
|FTW Working |
---
|FTW Spare|
---
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
Signed-off-by: Chasel Chiu
Reviewed-by: Michael Kubacki
---
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
| 22 ++
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
| 7 ---
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
| 11 +++
3 files changed, 37 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
index 942abf95a6..fcdc715263 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
@@ -568,6 +568,28 @@ GetVariableFvInfo (
return;
}
+ //
+ // GetVariableFlashNvStorageInfo () only reports regular variable region
information,
+ // if platform implemented an additional NVS region following the regular
variable region,
+ // then both region size should be included as overall NVS region size.
+ //
+ // The below PcdFlashNvStorageAdditionalSize is for compatible with legacy
usages that should be deprecated.
+ // The new usage model should define separate regions without implicit
connections to UEFI Variable or FTW regions.
+ //
+ // Example NVS flash map for such legacy usage:
+ // Note: PcdFlashNvStorageAdditionalSize is equal to platform
PcdFlashFvNvStorageEventLogSize.
+ // ---
+ // |UEFI Variable|
+ // ---
+ // |EventLog | <= this is Additional NVS region
+ // ---
+ // |FTW Working |
+ // ---
+ // |FTW Spare|
+ // ---
+ //
+ NvStoreLength += PcdGet32 (PcdFlashNvStorageAdditionalSize);
+
Status = GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64);
if (!EFI_ERROR (Status)) {
// Stay within the current UINT32 size assumptions in the variable stack.
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
index 73049eceb2..f4009d8d8c 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
@@ -43,9 +43,10 @@
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
- gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
SOMETIMES_CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize## CONSUMES
[Sources]
FvbInfo.c
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 63dae756ad..d73a51ca52 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -194,3 +194,14 @@
# Other value: reserved for future use.
# @Prompt Flash Variable Store type.
gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType|0x00|UINT8|0x000E
+
+ ## Declares Additional NVS Region Size.
+ # Platform may implement a Regular variable region and an additional
region, which will require this PCD
+ # to tell SpiFvbService to include both regions.
+ # Note: This PCD is for compatible with legacy usages that should be
deprecated.
+ # The new usage model should define separate regions without implicit
connections to UEFI Variable or FTW regions.
+ # Example legacy usage is to set this PCD equal to platform
PcdFlashFvNvStorageEventLogSize.
+ # 0: No additional NVS region.
+ # non-zero: The size of an additional NVS region following the Regular
variable re
Re: [edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region.
Hello, Another V4 patch sent for applying more comment/commit message feedbacks form Isaac. Please help to review again. Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of Chiu, Chasel > Sent: Thursday, February 9, 2023 9:26 AM > To: devel@edk2.groups.io; mikub...@linux.microsoft.com; Oram, Isaac W > > Cc: S, Ashraf Ali ; Chaganty, Rangasai V > ; Ni, Ray ; Kubacki, > Michael > Subject: Re: [edk2-devel] [edk2-platforms: PATCH] > IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. > > > Thanks for good suggestions Isaac and Michael! > I have sent V3 patch to apply all the suggestions, please help to review > again. > > Thanks, > Chasel > > > > > -Original Message- > > From: devel@edk2.groups.io On Behalf Of Michael > > Kubacki > > Sent: Thursday, February 9, 2023 8:47 AM > > To: devel@edk2.groups.io; Oram, Isaac W ; > > Chiu, Chasel > > Cc: S, Ashraf Ali ; Chaganty, Rangasai V > > ; Ni, Ray ; Kubacki, > > Michael > > Subject: Re: [edk2-devel] [edk2-platforms: PATCH] > > IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. > > > > Thanks, that's useful background. @chasel, you should probably put > > this info in the commit message so it is captured in source history. > > > > Given the default value is zero, it seems reasonable. I was also > > initially confused by the name of the PCD. > > > > Another idea would be something like "PcdFlashNvStorageAdditionalSize". > > > > Please do at least update the commit message to include additional context. > > > > Reviewed-by: Michael Kubacki > > > > On 2/9/2023 11:04 AM, Isaac Oram wrote: > > > It is a legacy that exists in current and past implementations. > > > There is a > > complex arbitrary relationship between the runtime updateable regions > > in existing platform designs. > > > There is something like: > > > - Variable store (large) > > > - Error log (small) > > > - Fault tolerant working area (>= size of prior 2 regions) > > > - Fault tolerant metadata (small). > > > And there are assumptions about ordering and packing built into > > > board flash > > layouts. > > > > > > I don't think that we should introduce "other variable" as a > > > concept, because > > variable solutions don't support two regions, so it isn't a UEFI variable > > region. > > OtherUpdatable might be ok, but still seems confusing to me. > > > I think that we should add the support for the *ErrorLog* region so > > > that the > > open FvbServices can be used by current implementations. Then we > > should eliminate the "ErrorLog" use completely. My thought is that > > this makes the connection to legacy clear. And also motivates us to > > eliminate all the vestigial references to the ErrorLog in edk2 and edk2- > platforms. > > > > > > New updateable regions should not be hard-coded into this area and > > > should > > have a cleaner solution, as Michael suggests. > > > > > > I understand if we don't want to support legacy or workarounds, but > > > I think > > that currently adoption and use of the open content is higher > > priority. Which is why we are requesting this workaround to match > > "proprietary" FVB services behavior. > > > > > > Regards, > > > Isaac > > > > > > -Original Message- > > > From: Michael Kubacki > > > Sent: Thursday, February 9, 2023 7:40 AM > > > To: devel@edk2.groups.io; Chiu, Chasel > > > Cc: S, Ashraf Ali ; Oram, Isaac W > > > ; Chaganty, Rangasai V > > > ; Ni, Ray ; > > > Kubacki, Michael > > > Subject: Re: [edk2-devel] [edk2-platforms: PATCH] > > IntelSiliconPkg/SpiFvbServiceSmm: Support Other NVS variable region. > > > > > > Is there a reason this other content can't go into it's own FV? > > > > > > On 2/9/2023 12:14 AM, Chiu, Chasel wrote: > > >> Platform may implement Other NVS variable region following Regular > > >> variable region and in this case SpiFvbService should include both > > >> region size when calculating the total NVS region size. > > >> > > >> One usage model is EventLog NVS region and there could be others. > > >> > > >> Cc: Ashraf Ali S > > >> Cc: Isaac Oram > > >> Cc: Rangasai V Chaganty > > >> Cc: R
Re: [edk2-devel] [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Support Additional NVS region.
Thanks for promptly reviewing and good suggestions Michael, Isaac!
I have merged this patch:
https://github.com/tianocore/edk2-platforms/commit/88d44c563d9fd5c95be93e706f9420352ee4c053
Thanks,
Chasel
> -Original Message-
> From: Oram, Isaac W
> Sent: Thursday, February 9, 2023 10:34 AM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: RE: [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm:
> Support Additional NVS region.
>
> Reviewed-by: Isaac Oram
>
> -----Original Message-
> From: Chiu, Chasel
> Sent: Thursday, February 9, 2023 10:27 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; S, Ashraf Ali
> ;
> Oram, Isaac W ; Chaganty, Rangasai V
> ; Ni, Ray ; Kubacki,
> Michael
> Subject: [edk2-platforms: PATCH v4] IntelSiliconPkg/SpiFvbServiceSmm: Support
> Additional NVS region.
>
> Platform may implement an additional NVS region following Regular variable
> region and in this case SpiFvbService should include both region size when
> calculating the total NVS region size.
>
> The PcdFlashNvStorageAdditionalSize is for compatible with legacy usages that
> should be deprecated. The new usage model should define separate regions
> without implicit connections to UEFI Variable or FTW regions.
>
> Example NVS flash map for such legacy usage:
> Note: PcdFlashNvStorageAdditionalSize is equal to platform
> PcdFlashFvNvStorageEventLogSize.
>
> ---
> |UEFI Variable|
> ---
> |EventLog | <= this is Additional NVS region
> ---
> |FTW Working |
> ---
> |FTW Spare|
> ---
>
> Cc: Ashraf Ali S
> Cc: Isaac Oram
> Cc: Rangasai V Chaganty
> Cc: Ray Ni
> Cc: Michael Kubacki
> Signed-off-by: Chasel Chiu
> Reviewed-by: Michael Kubacki
> ---
>
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon
> .c | 22 ++
> Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> | 7 ---
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
>| 11
> +++
> 3 files changed, 37 insertions(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceComm
> on.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceComm
> on.c
> index 942abf95a6..fcdc715263 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceComm
> on.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
> +++ rviceCommon.c
> @@ -568,6 +568,28 @@ GetVariableFvInfo (
> return; } + //+ // GetVariableFlashNvStorageInfo () only reports
> regular
> variable region information,+ // if platform implemented an additional NVS
> region following the regular variable region,+ // then both region size
> should be
> included as overall NVS region size.+ //+ // The below
> PcdFlashNvStorageAdditionalSize is for compatible with legacy usages that
> should be deprecated.+ // The new usage model should define separate regions
> without implicit connections to UEFI Variable or FTW regions.+ //+ //
> Example
> NVS flash map for such legacy usage:+ // Note:
> PcdFlashNvStorageAdditionalSize is equal to platform
> PcdFlashFvNvStorageEventLogSize.+ // ---+ // |UEFI Variable|+
> // -
> --+ // |EventLog | <= this is Additional NVS region+ //
> ---
> + // |FTW Working |+ // ---+ // |FTW Spare|+ //
> ---+
> //+ NvStoreLength += PcdGet32 (PcdFlashNvStorageAdditionalSize);+ Status =
> GetVariableFlashFtwSpareInfo (&NvBaseAddress, &Length64); if (!EFI_ERROR
> (Status)) { // Stay within the current UINT32 size assumptions in the
> variable
> stack.diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.in
> f
> b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.in
> f
> index 73049eceb2..f4009d8d8c 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.in
> f
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
> +++ rviceSmm.inf
> @@ -43,9 +43,10 @@
>IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES-
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES-
> gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ##
> SOMETIMES_CONSUMES+
> gIntelSiliconPkgToken
Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] SpiFvbServiceStandaloneMm: Add changes for rewrite varstore header
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: mikub...@linux.microsoft.com > Sent: Thursday, February 9, 2023 4:52 PM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali ; Oram, Isaac W > ; Chaganty, Rangasai V > ; Ni, Ray ; Chiu, Chasel > > Subject: [edk2-platforms][PATCH v1 1/1] SpiFvbServiceStandaloneMm: Add > changes for rewrite varstore header > > From: Michael Kubacki > > Updates the Standalone MM module to have the necessary INF changes to build > with the following two recent commits made to rewrite the the variable store > header in the MM SPI FVB service. > > - e95c798 > - 88d44c5 > > Cc: Ashraf Ali S > Cc: Isaac Oram > Cc: Rangasai V Chaganty > Cc: Ray Ni > Cc: Chasel Chiu > Signed-off-by: Michael Kubacki > --- > > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandalo > neMm.inf | 4 > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec >| 4 +++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > index 152cf0036fdb..717b6fc00cc6 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe > +++ rviceStandaloneMm.inf > @@ -44,6 +44,8 @@ [Packages] > [Pcd] >gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## > CONSUMES >gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## > SOMETIMES_CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize ## > + CONSUMES > > [Sources] >FvbInfo.c > @@ -60,6 +62,8 @@ [Protocols] > [Guids] >gEfiFirmwareFileSystem2Guid ## CONSUMES >gEfiSystemNvDataFvGuid## CONSUMES > + gEfiVariableGuid ## SOMETIMES_CONSUMES > + gEfiAuthenticatedVariableGuid ## SOMETIMES_CONSUMES > > [Depex] >TRUE > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index d73a51ca5235..cad22acda496 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -188,7 +188,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, > PcdsDynamic, PcdsDynamicEx] > >## Define Flash Variable Store type. ># When Flash Variable Store corruption happened, the SpiFvbService will > recreate Variable Store > - # with valid header information provided by this PCD value. > + # with valid header information provided by this PCD value. > + # Note: This PCD must be FixedAtBuild when using Standalone MM. ># 0: Variable Store is gEfiVariableGuid type. ># 1: Variable Store is gEfiAuthenticatedVariableGuid type. ># Other value: reserved for future use. @@ -199,6 +200,7 @@ > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ># Platform may implement a Regular variable region and an additional > region, > which will require this PCD ># to tell SpiFvbService to include both regions. ># Note: This PCD is for compatible with legacy usages that should be > deprecated. > + # Note: This PCD must be FixedAtBuild when using Standalone MM. ># The new usage model should define separate regions without implicit > connections to UEFI Variable or FTW regions. ># Example legacy usage is to set this PCD equal to platform > PcdFlashFvNvStorageEventLogSize. ># 0: No additional NVS region. > -- > 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100029): https://edk2.groups.io/g/devel/message/100029 Mute This Topic: https://groups.io/mt/96867025/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] SpiFvbServiceStandaloneMm: Add changes for rewrite varstore header
Thanks Michael! Patch has been merged: https://github.com/tianocore/edk2-platforms/commit/e2353ad640d55dafb7315eae2a93b318809ccbe3 > -Original Message- > From: mikub...@linux.microsoft.com > Sent: Thursday, February 9, 2023 4:52 PM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali ; Oram, Isaac W > ; Chaganty, Rangasai V > ; Ni, Ray ; Chiu, Chasel > > Subject: [edk2-platforms][PATCH v1 1/1] SpiFvbServiceStandaloneMm: Add > changes for rewrite varstore header > > From: Michael Kubacki > > Updates the Standalone MM module to have the necessary INF changes to build > with the following two recent commits made to rewrite the the variable store > header in the MM SPI FVB service. > > - e95c798 > - 88d44c5 > > Cc: Ashraf Ali S > Cc: Isaac Oram > Cc: Rangasai V Chaganty > Cc: Ray Ni > Cc: Chasel Chiu > Signed-off-by: Michael Kubacki > --- > > Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandalo > neMm.inf | 4 > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec >| 4 +++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > index 152cf0036fdb..717b6fc00cc6 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandal > oneMm.inf > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe > +++ rviceStandaloneMm.inf > @@ -44,6 +44,8 @@ [Packages] > [Pcd] >gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## > CONSUMES >gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashVariableStoreType ## > SOMETIMES_CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashNvStorageAdditionalSize ## > + CONSUMES > > [Sources] >FvbInfo.c > @@ -60,6 +62,8 @@ [Protocols] > [Guids] >gEfiFirmwareFileSystem2Guid ## CONSUMES >gEfiSystemNvDataFvGuid## CONSUMES > + gEfiVariableGuid ## SOMETIMES_CONSUMES > + gEfiAuthenticatedVariableGuid ## SOMETIMES_CONSUMES > > [Depex] >TRUE > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index d73a51ca5235..cad22acda496 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -188,7 +188,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, > PcdsDynamic, PcdsDynamicEx] > >## Define Flash Variable Store type. ># When Flash Variable Store corruption happened, the SpiFvbService will > recreate Variable Store > - # with valid header information provided by this PCD value. > + # with valid header information provided by this PCD value. > + # Note: This PCD must be FixedAtBuild when using Standalone MM. ># 0: Variable Store is gEfiVariableGuid type. ># 1: Variable Store is gEfiAuthenticatedVariableGuid type. ># Other value: reserved for future use. @@ -199,6 +200,7 @@ > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ># Platform may implement a Regular variable region and an additional > region, > which will require this PCD ># to tell SpiFvbService to include both regions. ># Note: This PCD is for compatible with legacy usages that should be > deprecated. > + # Note: This PCD must be FixedAtBuild when using Standalone MM. ># The new usage model should define separate regions without implicit > connections to UEFI Variable or FTW regions. ># Example legacy usage is to set this PCD equal to platform > PcdFlashFvNvStorageEventLogSize. ># 0: No additional NVS region. > -- > 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100033): https://edk2.groups.io/g/devel/message/100033 Mute This Topic: https://groups.io/mt/96867025/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1] MinPlatformPkg: Update MinDsdt device name from PCI0 to MinDsdt_PC00
Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Chen, Aryeh
> Sent: Tuesday, February 28, 2023 10:37 PM
> To: devel@edk2.groups.io
> Cc: Chen, Aryeh ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Oram, Isaac W ;
> Gao, Liming ; Dong, Eric
> Subject: [PATCH v1] MinPlatformPkg: Update MinDsdt device name from PCI0 to
> MinDsdt_PC00
>
> From: Aryeh Chen
>
> Since AlderLake platform client project align Server project to use PC00.
>
> Signed-off-by: Aryeh Chen
> Cc: Chasel Chiu ,
> Cc: Nate DeSimone ,
> Cc: Isaac Oram ,
> Cc: Liming Gao ,
> Cc: Eric Dong
> ---
> Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
> b/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
> index 4efb8709ac..d84393d465 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/MinDsdt/MinDsdt.asl
> @@ -23,7 +23,7 @@ DefinitionBlock (
>
> //---
> // Begin PCI
> tree object scope
> //
> Device(PCI0) { // PCI Bridge "Host Bridge"+Device(PC00) { // PCI
> Bridge
> "Host Bridge" Name(_HID, EISAID("PNP0A08")) // Indicates PCI
> Express/PCI-X
> Mode2 host hierarchy Name(_CID, EISAID("PNP0A03")) // To support legacy
> OS that doesn't understand the new HID Name(_SEG, 0)--
> 2.26.2.windows.1
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Re: [edk2-devel] [PATCH v1 1/6] IntelFsp2Pkg: Add CpuLib to module INFs that depend on UefiCpuLib
Thanks Yu! Reviewed-by: Chasel Chiu > -Original Message- > From: Pu, Yu > Sent: Friday, April 1, 2022 1:22 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v1 1/6] IntelFsp2Pkg: Add CpuLib to module INFs that > depend on UefiCpuLib > > Step 1 to merge UefiCpuLib to CpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + > IntelFsp2Pkg/FspSecCore/SecMain.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index 7b05cae64130..830471adcf2f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -51,6 +51,7 @@ >FspSwitchStackLib > >FspCommonLib > >FspSecPlatformLib > > + CpuLib > >UefiCpuLib > > > > [Pcd] > > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index 7794255af13d..edb7447d9eff 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -20,6 +20,7 @@ > #include > > #include > > #include > > +#include > > #include > > #include > > > > -- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88450): https://edk2.groups.io/g/devel/message/88450 Mute This Topic: https://groups.io/mt/90179536/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1 2/6] IntelFsp2WrapperPkg: Add CpuLib to module INFs that depend on UefiCpuLib.
Thanks Yu! Reviewed-by: Chasel Chiu > -Original Message- > From: Pu, Yu > Sent: Friday, April 1, 2022 1:22 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v1 2/6] IntelFsp2WrapperPkg: Add CpuLib to module INFs > that depend on UefiCpuLib. > > Step 1 to merge UefiCpuLib to CpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 5d0e0214015f..e2262d693c55 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -37,6 +37,7 @@ >HobLib FspWrapperPlatformLib FspWrapperHobProcessLib+ CpuLib > UefiCpuLib PeCoffGetEntryPointLib PeCoffExtraActionLibdiff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index da0049a65435..0598f85ab3ac 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -38,6 +38,7 @@ >MemoryAllocationLib FspWrapperPlatformLib > FspWrapperHobProcessLib+ CpuLib UefiCpuLib PeCoffGetEntryPointLib > PeCoffExtraActionLib-- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88451): https://edk2.groups.io/g/devel/message/88451 Mute This Topic: https://groups.io/mt/90179537/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
Hi Ted,
Please see my comments inline below.
Thanks,
Chasel
> -Original Message-
> From: Kuo, Ted
> Sent: Monday, April 4, 2022 2:23 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali
> Subject: [edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD
> support for X64
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
> 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
> 2.Added FSPx_UPD_COMMON_FSP24 structures.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ashraf Ali S
> Signed-off-by: Ted Kuo
> ---
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 +
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++--
> IntelFsp2Pkg/Include/FspEas/FspApi.h | 172
> -
> IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +-
> 4 files changed, 278 insertions(+), 18 deletions(-)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> index e7261b41cd..de7f916070 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> @@ -32,6 +32,25 @@ struc FSPM_UPD_COMMON
> .size:
> endstruc
>
> +struc FSPM_UPD_COMMON_FSP24
> +; FSP_UPD_HEADER {
> +.FspUpdHeader: resd 8
> +; }
> +; FSPM_ARCH2_UPD {
> +.Revision: resb 1
> +.Reserved: resb 3
> +.Length resd 1
> +.StackBase: resq 1
> +.StackSize: resq 1
> +.BootLoaderTolumSize: resd 1
> +.BootMode: resd 1
> +.FspEventHandlerresq 1
> +.EnableMultiPhaseMemoryInit resb 1
> +.Reserved1: resb 23
Please remove EnableMultiPhaseMemoryInit as it is not used.
Also the Reserved1 will be 24 bytes instead of 23
> +; }
> +.size:
> +endstruc
> +
> ;
> ; Following functions will be provided in C ; @@ -124,12 +143,22 @@
> ASM_PFX(FspApiCommonContinue):
>popeax
>
> FspStackSetup:
> + movecx, [edx + FSPM_UPD_COMMON.Revision]
> + cmpecx, 3
> + jaeFspmUpdCommon2
> +
>;
>; StackBase = temp memory base, StackSize = temp memory size
>;
>movedi, [edx + FSPM_UPD_COMMON.StackBase]
>movecx, [edx + FSPM_UPD_COMMON.StackSize]
> + jmpChkFspHeapSize
> +
> +FspmUpdCommon2:
> + movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
> + movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
>
> +ChkFspHeapSize:
>;
>; Keep using bootloader stack if heap size % is 0
>;
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> index 7fd3d6d843..25ef99b798 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> @@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
> .FspUpdHeaderRevision:resb1
> .FspUpdHeaderReserved:resb 23
> ; }
> -; FSPT_ARCH_UPD{
> -.FsptArchUpd: resd8
> +; FSPT_ARCH_UPD {
> +.FsptArchRevision:resb1
> +.FsptArchReserved:resb3
> +.FsptArchUpd: resd7
> ; }
> ; FSPT_CORE_UPD {
> .MicrocodeCodeAddr: resd1
> @@ -96,6 +98,25 @@ struc LoadMicrocodeParamsFsp22
> .size:
> endstruc
>
> +struc LoadMicrocodeParamsFsp24
> +; FSP_UPD_HEADER {
> +.FspUpdHeaderSignature: resd2
> +.FspUpdHeaderRevision:resb1
> +.FspUpdHeaderReserved:resb 23
> +; }
> +; FSPT_ARCH2_UPD {
> +.FsptArchRevision:resb1
> +.FsptArchReserved:resb3
> +.FsptArchLength: resd1
> +.FspDebugHandler resq1
> +.MicrocodeCodeAddr: resq1
> +.MicrocodeCodeSize: resq1
> +.CodeRegionBase: resq1
> +.CodeRegionSize: resq1
Please remove 4 elements from the ARCH2 structure:
.MicrocodeCodeAddr: resq1
.MicrocodeCodeSize: resq1
.CodeRegionBase: resq1
.CodeRegionSize: resq1
Also the new CORE_UPD structure is still after ARCH2_UPD structure which having
64bits elements.
> +; }
> +.size:
> +endstruc
> +
> ;
> ; Define SSE macros
> ;
> @@ -172,9 +193,9 @@ ASM_PFX(LoadMicrocodeDefault):
> ; Executed by SBSP and NBSP
> ; Beginning of microcode update region starts on p
Re: [edk2-devel][PATCH v2 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
Hi Ted, Please see my comments inline below. Thanks, Chasel > -Original Message- > From: Kuo, Ted > Sent: Monday, April 4, 2022 2:23 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [edk2-devel][PATCH v2 1/8] IntelFsp2Pkg: X64 compatible changes > to support PEI in 64bit > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 > 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint. > 2.Changed AsmReadEsp to AsmReadStackPointer. > 3.Changed the type of the return value of AsmReadStackPointer > from UINT32 to UINTN. > 4.Changed the type of TemporaryMemoryBase, PermenentMemoryBase > and BootLoaderStack from UINT32 to UINTN. > 5.Some type casting to pointers are UINT32. Changed them to > UINTN to accommodate both IA32 and X64. > 6.Corrected some typos. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: Ted Kuo > --- > IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + > IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 > +- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 > IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 > IntelFsp2Pkg/FspSecCore/SecMain.c | 8 > IntelFsp2Pkg/FspSecCore/SecMain.h | 10 > +- > IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- > 9 files changed, 29 insertions(+), 28 deletions(-) > > diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > index 88f5540fef..66d39cc70c 100644 > --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > @@ -112,6 +112,7 @@ WaitForNotify ( >@retval EFI_OUT_OF_RESOURCES Insufficient resources to create > database > **/ > EFI_STATUS > +EFIAPI > FspNotifyPhasePeimEntryPoint ( >IN EFI_PEI_FILE_HANDLE FileHandle, >IN CONST EFI_PEI_SERVICES **PeiServices > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > index 8046b43745..d40dad5a52 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > @@ -9,14 +9,14 @@ > SECTION .text > > > ;-- > -; UINT32 > +; UINTN > ; EFIAPI > -; AsmReadEsp ( > +; AsmReadStackPointer ( > ; VOID > ; ); > > ;-- > -global ASM_PFX(AsmReadEsp) > -ASM_PFX(AsmReadEsp): > +global ASM_PFX(AsmReadStackPointer) > +ASM_PFX(AsmReadStackPointer): > mov eax, esp > ret > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index 5a7e27c240..ce20639890 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -9,20 +9,20 @@ > ; > > ;-- > > -SECTION .text > +SECTION .text > > > ;-- > ; VOID > ; EFIAPI > ; SecSwitchStack ( > ; UINT32 TemporaryMemoryBase, > -; UINT32 PermenentMemoryBase > +; UINT32 PermanentMemoryBase > ; ); > > ;-- > global ASM_PFX(SecSwitchStack) > ASM_PFX(SecSwitchStack): > ; > -; Save three register: eax, ebx, ecx > +; Save four register: eax, ebx, ecx, edx > ; > push eax > push ebx > @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): > mov dword [eax + 12], edx > mov edx, dword [esp + 16]; Update this function's return address > into permanent memory > mov dword [eax + 16], edx > -mov esp, eax ; From now, esp is pointed to > permanent > memory > +mov esp, eax ; From now, esp is pointed to permanent > memory > > ; > ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ > ASM_PFX(SecSwitchStack): > mov eax, ebp > sub eax, ebx > add eax, ecx > -mov ebp, eax; From now, ebp is pointed to permanent > memory >
Re: [edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
One more comments.
Thanks,
Chasel
> -Original Message-
> From: Chiu, Chasel
> Sent: Wednesday, April 6, 2022 10:40 PM
> To: Kuo, Ted ; devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Zeng, Star
> ; S, Ashraf Ali
> Subject: RE: [edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add
> FSPx_ARCH2_UPD support for X64
>
>
> Hi Ted,
>
> Please see my comments inline below.
>
> Thanks,
> Chasel
>
>
> > -Original Message-
> > From: Kuo, Ted
> > Sent: Monday, April 4, 2022 2:23 PM
> > To: devel@edk2.groups.io
> > Cc: Chiu, Chasel ; Desimone, Nathaniel L
> > ; Zeng, Star ; S,
> > Ashraf Ali
> > Subject: [edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD
> > support for X64
> >
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
> > 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
> > 2.Added FSPx_UPD_COMMON_FSP24 structures.
> >
> > Cc: Chasel Chiu
> > Cc: Nate DeSimone
> > Cc: Star Zeng
> > Cc: Ashraf Ali S
> > Signed-off-by: Ted Kuo
> > ---
> > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 +
> > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++--
> > IntelFsp2Pkg/Include/FspEas/FspApi.h | 172
> > -
> > IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +-
> > 4 files changed, 278 insertions(+), 18 deletions(-)
> >
> > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> > index e7261b41cd..de7f916070 100644
> > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> > @@ -32,6 +32,25 @@ struc FSPM_UPD_COMMON
> > .size:
> > endstruc
> >
> > +struc FSPM_UPD_COMMON_FSP24
> > +; FSP_UPD_HEADER {
> > +.FspUpdHeader: resd 8
> > +; }
> > +; FSPM_ARCH2_UPD {
> > +.Revision: resb 1
> > +.Reserved: resb 3
> > +.Length resd 1
> > +.StackBase: resq 1
> > +.StackSize: resq 1
> > +.BootLoaderTolumSize: resd 1
> > +.BootMode: resd 1
> > +.FspEventHandlerresq 1
> > +.EnableMultiPhaseMemoryInit resb 1
> > +.Reserved1: resb 23
>
>
>
>
> Please remove EnableMultiPhaseMemoryInit as it is not used.
> Also the Reserved1 will be 24 bytes instead of 23
>
>
>
>
> > +; }
> > +.size:
> > +endstruc
> > +
> > ;
> > ; Following functions will be provided in C ; @@ -124,12 +143,22 @@
> > ASM_PFX(FspApiCommonContinue):
> >popeax
> >
> > FspStackSetup:
> > + movecx, [edx + FSPM_UPD_COMMON.Revision]
> > + cmpecx, 3
> > + jaeFspmUpdCommon2
> > +
> >;
> >; StackBase = temp memory base, StackSize = temp memory size
> >;
> >movedi, [edx + FSPM_UPD_COMMON.StackBase]
> >movecx, [edx + FSPM_UPD_COMMON.StackSize]
> > + jmpChkFspHeapSize
> > +
> > +FspmUpdCommon2:
> > + movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
> > + movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
> >
> > +ChkFspHeapSize:
> >;
> >; Keep using bootloader stack if heap size % is 0
> >;
> > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> > index 7fd3d6d843..25ef99b798 100644
> > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> > @@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
> > .FspUpdHeaderRevision:resb1
> > .FspUpdHeaderReserved:resb 23
> > ; }
> > -; FSPT_ARCH_UPD{
> > -.FsptArchUpd: resd8
> > +; FSPT_ARCH_UPD {
> > +.FsptArchRevision:resb1
> > +.FsptArchReserved:resb3
> > +.FsptArchUpd: resd7
> > ; }
> > ; FSPT_CORE_UPD {
> > .MicrocodeCodeAddr: resd1
> > @@ -96,6 +98,25 @@ struc LoadMicrocodeParamsFsp22
> > .size:
> > endstruc
> >
> > +struc LoadMicrocodeParamsFsp24
> > +; FSP_UPD_HEADER {
> > +.FspUpdHeaderSignature: resd2
> > +.FspUpdHeaderRevision:resb1
> > +.FspUpdHeaderReserved:resb 23
> &
Re: [edk2-devel][PATCH v2 8/8] IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
HI Ted,
Please see my comments below inline.
Thanks,
Chasel
> -Original Message-
> From: Kuo, Ted
> Sent: Monday, April 4, 2022 2:23 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali
> Subject: [edk2-devel][PATCH v2 8/8] IntelFsp2WrapperPkg:
> SecFspWrapperPlatformSecLibSample support for X64
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
> 1.Added SecFspWrapperPlatformSecLibSample support for X64.
> 2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
> 3.Moved Fsp.h up one level to be shared across IA32 and X64.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ashraf Ali S
> Signed-off-by: Ted Kuo
> ---
> .../{Ia32 => }/Fsp.h | 0
> .../Ia32/Stack.nasm| 6 +-
> .../SecFspWrapperPlatformSecLibSample.inf | 7 +-
> .../SecRamInitData.c | 32 ++--
> .../X64/PeiCoreEntry.nasm | 149 ++
> .../X64/SecEntry.nasm | 171
> +
> .../X64/Stack.nasm | 73 +
> 7 files changed, 415 insertions(+), 23 deletions(-) rename
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32
> => }/Fsp.h (100%) create mode 100644
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/P
> eiCoreEntry.nasm
> create mode 100644
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/S
> ecEntry.nasm
> create mode 100644
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/S
> tack.nasm
>
> diff --git
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32
> /Fsp.h
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.
> h
> similarity index 100%
> rename from
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/F
> sp.h
> rename to
> IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
> diff --git
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32
> /Stack.nasm
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32
> /Stack.nasm
> index d7394cf286..65e9c2e895 100644
> ---
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32
> /Stack.nasm
> +++
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32
> +++ /Stack.nasm
> @@ -22,7 +22,7 @@
> global ASM_PFX(SecSwitchStack)
> ASM_PFX(SecSwitchStack):
> ;
> -; Save three register: eax, ebx, ecx
> +; Save four register: eax, ebx, ecx, edx
> ;
> push eax
> push ebx
> @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
> mov dword [eax + 12], edx
> mov edx, dword [esp + 16]; Update this function's return address
> into permanent memory
> mov dword [eax + 16], edx
> -mov esp, eax ; From now, esp is pointed to
> permanent
> memory
> +mov esp, eax ; From now, esp is pointed to permanent
> memory
>
> ;
> ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@
> ASM_PFX(SecSwitchStack):
> mov eax, ebp
> sub eax, ebx
> add eax, ecx
> -mov ebp, eax; From now, ebp is pointed to permanent
> memory
> +mov ebp, eax ; From now, ebp is pointed to permanent
> memory
>
> pop edx
> pop ecx
> diff --git
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecF
> spWrapperPlatformSecLibSample.inf
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecF
> spWrapperPlatformSecLibSample.inf
> index 027b127724..7aa4297bcc 100644
> ---
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecF
> spWrapperPlatformSecLibSample.inf
> +++
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecF
> +++ spWrapperPlatformSecLibSample.inf
> @@ -39,13 +39,18 @@
>SecGetPerformance.c
>SecTempRamDone.c
>PlatformInit.c
> + Fsp.h
>
> [Sources.IA32]
> - Ia32/Fsp.h
>Ia32/SecEntry.nasm
>Ia32/PeiCoreEntry.nasm
>Ia32/Stack.nasm
>
> +[Sources.X64]
> + X64/SecEntry.nasm
> + X64/PeiCoreEntry.nasm
> + X64/Stack.nasm
> +
>
> ##
> ##
> #
> # Package Dependency Section - list of Package files that are required for
> diff --git
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecR
> amInitData.c
> b/IntelFsp2WrapperPkg/Library/SecFsp
Re: [edk2-devel] [PATCH v1 01/15] IntelFsp2Pkg: Add CpuLib to module INFs that depend on UefiCpuLib
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Monday, April 11, 2022 5:46 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v1 01/15] IntelFsp2Pkg: Add CpuLib to module INFs that > depend on UefiCpuLib > > There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and > UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build > failure, add CpuLib dependency to all modules that depend on UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + > IntelFsp2Pkg/FspSecCore/SecMain.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index 7b05cae64130..830471adcf2f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -51,6 +51,7 @@ >FspSwitchStackLib FspCommonLib FspSecPlatformLib+ CpuLib > UefiCpuLib [Pcd]diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index 7794255af13d..edb7447d9eff 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -20,6 +20,7 @@ > #include #include > #include +#include #include > #include -- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88758): https://edk2.groups.io/g/devel/message/88758 Mute This Topic: https://groups.io/mt/90407111/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1 02/15] IntelFsp2WrapperPkg: Add CpuLib to module INFs that depend on UefiCpuLib.
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Monday, April 11, 2022 5:46 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v1 02/15] IntelFsp2WrapperPkg: Add CpuLib to module > INFs that depend on UefiCpuLib. > > There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and > UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build > failure, add CpuLib dependency to all modules that depend on UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 5d0e0214015f..e2262d693c55 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -37,6 +37,7 @@ >HobLib FspWrapperPlatformLib FspWrapperHobProcessLib+ CpuLib > UefiCpuLib PeCoffGetEntryPointLib PeCoffExtraActionLibdiff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index da0049a65435..0598f85ab3ac 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -38,6 +38,7 @@ >MemoryAllocationLib FspWrapperPlatformLib > FspWrapperHobProcessLib+ CpuLib UefiCpuLib PeCoffGetEntryPointLib > PeCoffExtraActionLib-- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88759): https://edk2.groups.io/g/devel/message/88759 Mute This Topic: https://groups.io/mt/90407112/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1 09/15] IntelFsp2Pkg: Remove UefiCpuLib from module INFs.
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Monday, April 11, 2022 5:46 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v1 09/15] IntelFsp2Pkg: Remove UefiCpuLib from module > INFs. > > Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the > dependency of UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 - > IntelFsp2Pkg/FspSecCore/SecMain.h | 1 - > IntelFsp2Pkg/IntelFsp2Pkg.dsc | 1 - > IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc | 1 - > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 - > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 1 - > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc | 1 - > 7 files changed, 7 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index 830471adcf2f..c07b49c4045f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -52,7 +52,6 @@ >FspCommonLib FspSecPlatformLib CpuLib- UefiCpuLib [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## > CONSUMESdiff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index edb7447d9eff..7288086cc493 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -21,7 +21,6 @@ > #include #include > #include -#include > #include typedef VOID > (*PEI_CORE_ENTRY) ( \diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75b8..b90be5397d37 > 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc > @@ -27,7 +27,6 @@ >PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDeco > mpressLib.inf- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf > ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseR > eportStatusCodeLibNull.inf > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc > eLibNull.infdiff --git a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > index 961576c9a73a..31558121185d 100644 > --- a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > +++ b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > @@ -107,7 +107,6 @@ > > PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePl > atformHookLibNull.inf > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc > eLibNull.inf > OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLib > Null/OemHookStatusCodeLibNull.inf- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf !if > $(TARGET) == DEBUG > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort > .inf > SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPo > rtLib16550.infdiff --git > a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index e2262d693c55..77af97207990 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -38,7 +38,6 @@ >FspWrapperPlatformLib FspWrapperHobProcessLib CpuLib- UefiCpuLib > PeCoffGetEntryPointLib PeCoffExtraActionLib PerformanceLibdiff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index 0598f85ab3ac..cad9fad96829 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -39,7 +39,6 @@ >FspWrapperPlatformLib FspWrapperHobProcessLib CpuLib- UefiCpuLib > PeCoffGetEntryPointLib PeCoffExtraActionLib PerformanceLibdiff --git > a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > index 21e089000eaf..233cb3d9ce2b 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > @@ -41,7 +41,6 @@ > > DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLi > bNull.inf# UefiCpuPkg- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf > LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf# FSP > Wrapper Lib-- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88760): https://edk2.groups.io/g/devel/message/88760 Mute This Topic: https://groups.io/mt/90407118/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 02/14] IntelFsp2Pkg: Add CpuLib to module INFs that depend on UefiCpuLib
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Tuesday, April 12, 2022 10:52 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v2 02/14] IntelFsp2Pkg: Add CpuLib to module INFs that > depend on UefiCpuLib > > There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and > UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build > failure, add CpuLib dependency to all modules that depend on UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + > IntelFsp2Pkg/FspSecCore/SecMain.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index 7b05cae64130..830471adcf2f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -51,6 +51,7 @@ >FspSwitchStackLib FspCommonLib FspSecPlatformLib+ CpuLib > UefiCpuLib [Pcd]diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index 7794255af13d..edb7447d9eff 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -20,6 +20,7 @@ > #include #include > #include +#include #include > #include -- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88803): https://edk2.groups.io/g/devel/message/88803 Mute This Topic: https://groups.io/mt/90430990/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 03/14] IntelFsp2WrapperPkg: Add CpuLib to module INFs that depend on UefiCpuLib.
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Tuesday, April 12, 2022 10:52 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v2 03/14] IntelFsp2WrapperPkg: Add CpuLib to module > INFs that depend on UefiCpuLib. > > There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and > UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build > failure, add CpuLib dependency to all modules that depend on UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 5d0e0214015f..e2262d693c55 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -37,6 +37,7 @@ >HobLib FspWrapperPlatformLib FspWrapperHobProcessLib+ CpuLib > UefiCpuLib PeCoffGetEntryPointLib PeCoffExtraActionLibdiff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index da0049a65435..0598f85ab3ac 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -38,6 +38,7 @@ >MemoryAllocationLib FspWrapperPlatformLib > FspWrapperHobProcessLib+ CpuLib UefiCpuLib PeCoffGetEntryPointLib > PeCoffExtraActionLib-- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88804): https://edk2.groups.io/g/devel/message/88804 Mute This Topic: https://groups.io/mt/90430992/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 08/14] IntelFsp2Pkg: Remove UefiCpuLib from module INFs.
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Pu, Yu > Sent: Tuesday, April 12, 2022 10:52 PM > To: devel@edk2.groups.io > Cc: Pu, Yu ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [PATCH v2 08/14] IntelFsp2Pkg: Remove UefiCpuLib from module > INFs. > > Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the > dependency of UefiCpuLib. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Yu Pu > --- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 - > IntelFsp2Pkg/FspSecCore/SecMain.h | 1 - > IntelFsp2Pkg/IntelFsp2Pkg.dsc | 1 - > IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc | 1 - > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 - > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 1 - > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc | 1 - > 7 files changed, 7 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > index 830471adcf2f..c07b49c4045f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -52,7 +52,6 @@ >FspCommonLib FspSecPlatformLib CpuLib- UefiCpuLib [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## > CONSUMESdiff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h > b/IntelFsp2Pkg/FspSecCore/SecMain.h > index edb7447d9eff..7288086cc493 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.h > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h > @@ -21,7 +21,6 @@ > #include #include > #include -#include > #include typedef VOID > (*PEI_CORE_ENTRY) ( \diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75b8..b90be5397d37 > 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc > @@ -27,7 +27,6 @@ >PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDeco > mpressLib.inf- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf > ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseR > eportStatusCodeLibNull.inf > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc > eLibNull.infdiff --git a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > index 961576c9a73a..31558121185d 100644 > --- a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > +++ b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc > @@ -107,7 +107,6 @@ > > PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePl > atformHookLibNull.inf > PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanc > eLibNull.inf > OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLib > Null/OemHookStatusCodeLibNull.inf- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf !if > $(TARGET) == DEBUG > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort > .inf > SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPo > rtLib16550.infdiff --git > a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index e2262d693c55..77af97207990 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -38,7 +38,6 @@ >FspWrapperPlatformLib FspWrapperHobProcessLib CpuLib- UefiCpuLib > PeCoffGetEntryPointLib PeCoffExtraActionLib PerformanceLibdiff --git > a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index 0598f85ab3ac..cad9fad96829 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -39,7 +39,6 @@ >FspWrapperPlatformLib FspWrapperHobProcessLib CpuLib- UefiCpuLib > PeCoffGetEntryPointLib PeCoffExtraActionLib PerformanceLibdiff --git > a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > index 21e089000eaf..233cb3d9ce2b 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc > @@ -41,7 +41,6 @@ > > DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLi > bNull.inf# UefiCpuPkg- > UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf > LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf# FSP > Wrapper Lib-- > 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88805): https://edk2.groups.io/g/devel/message/88805 Mute This Topic: https://groups.io/mt/90431011/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH v4 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
Hi Ted, Please see my comments below inline. Thanks, Chasel > -Original Message- > From: Kuo, Ted > Sent: Wednesday, April 13, 2022 10:43 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [edk2-devel][PATCH v4 1/8] IntelFsp2Pkg: X64 compatible changes > to support PEI in 64bit > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 > 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and > PEI_CORE_ENTRY. > 2.Cast FspData from pointer to UINTN and then from UINTN to UINT32. This statement might cause confusion. We can update it later when pushing the patch, no need to send another V5. We actually only cast FspData pointer to UINT32 when verifying the pointer is valid or not, we do not cast it to UINT32 when consuming the data pointer. So we still can support 64bits FspData pointer. > 3.Changed AsmReadEsp to AsmReadStackPointer. > 4.Changed the type of the return value of AsmReadStackPointer > from UINT32 to UINTN. > 5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase > and BootLoaderStack from UINT32 to UINTN. > 6..Some type casting to pointers are UINT32. Changed them to > UINTN to accommodate both IA32 and X64. > 7.Corrected some typos. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: Ted Kuo > --- > IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + > IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 > IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 > IntelFsp2Pkg/FspSecCore/SecMain.c | 8 > IntelFsp2Pkg/FspSecCore/SecMain.h | 18 > ++ > .../Library/BaseFspSwitchStackLib/FspSwitchStackLib.c | 1 > + .../Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- > 10 files changed, 35 insertions(+), 31 deletions(-) > > diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > index 88f5540fef..66d39cc70c 100644 > --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c > @@ -112,6 +112,7 @@ WaitForNotify ( >@retval EFI_OUT_OF_RESOURCES Insufficient resources to create > database > **/ > EFI_STATUS > +EFIAPI > FspNotifyPhasePeimEntryPoint ( >IN EFI_PEI_FILE_HANDLE FileHandle, >IN CONST EFI_PEI_SERVICES **PeiServices > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > index 8046b43745..d40dad5a52 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm > @@ -9,14 +9,14 @@ > SECTION .text > > > ;-- > -; UINT32 > +; UINTN > ; EFIAPI > -; AsmReadEsp ( > +; AsmReadStackPointer ( > ; VOID > ; ); > > ;-- > -global ASM_PFX(AsmReadEsp) > -ASM_PFX(AsmReadEsp): > +global ASM_PFX(AsmReadStackPointer) > +ASM_PFX(AsmReadStackPointer): > mov eax, esp > ret > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index 5a7e27c240..ce20639890 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -9,20 +9,20 @@ > ; > > ;-- > > -SECTION .text > +SECTION .text > > > ;-- > ; VOID > ; EFIAPI > ; SecSwitchStack ( > ; UINT32 TemporaryMemoryBase, > -; UINT32 PermenentMemoryBase > +; UINT32 PermanentMemoryBase > ; ); > > ;-- > global ASM_PFX(SecSwitchStack) > ASM_PFX(SecSwitchStack): > ; > -; Save three register: eax, ebx, ecx > +; Save four register: eax, ebx, ecx, edx > ; > push eax > push ebx > @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): > mov dword [eax + 12], edx > mov edx, dword [esp + 16]; Update this function's return address > into permanent memory > mov dword [eax + 16], edx > -mov esp, eax ; From now,
Re: [edk2-devel][PATCH v4 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
Thanks Ted for updating patch!
For this patch series, Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Kuo,
> Ted
> Sent: Wednesday, April 13, 2022 10:43 AM
> To: devel@edk2.groups.io
> Subject: [edk2-devel][PATCH v4 0/8] Support PEI 64bit in IntelFsp2Pkg and
> IntelFsp2WrapperPkg
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
>
> Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
> IntelFsp2WrapperPkg. The patches below are needed to support these
> drivers/libraries in 64bit.
>
> V2 changes:
> 1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in
> FspApiEntryM.nasm.
> 2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
> 3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
>
> V3 changes:
> 1.Update FSPT_ARCH2_UPD and add FSPT_CORE_UPD back.
> 2.Use 0x instead of MAX_ADDRESS to reflect the default of
> FspData.
> 3.Remove EnableMultiPhaseMemoryInit from FSPM_ARCH2_UPD.
> 4.Bump GenCfgOpt version to 0.57.
>
> V4 changes:
> 1.Added EFIAPI to SwapStack and PEI_CORE_ENTRY.
> 2.Cast FspData from pointer to UINTN and then from UINTN to UINT32.
> 3.Corrected few typos.
>
> Ted Kuo (8):
> IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
> IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
> IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
> IntelFsp2Pkg: FspSecCore support for X64
> IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
> IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
> IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
> IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for
> X64
>
> IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 +
> IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +-
> .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +-
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 30 +-
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 96 +++-
> IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 +-
> IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +-
> IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +-
> IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
> IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 +-
> IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +-
> IntelFsp2Pkg/FspSecCore/SecMain.h | 18 +-
> IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 262 +++
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495
> +
> IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
> IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
> IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
> IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
> IntelFsp2Pkg/Include/FspEas/FspApi.h | 145 +-
> IntelFsp2Pkg/Include/FspGlobalData.h | 51 ++-
> IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +-
> IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
> IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +-
> .../Library/BaseFspCommonLib/FspCommonLib.c| 4 +-
> .../BaseFspSwitchStackLib/FspSwitchStackLib.c | 1 +
> .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
> .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +-
> .../SecFspSecPlatformLibNull.inf | 6 +-
> .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
> .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
> IntelFsp2Pkg/Tools/GenCfgOpt.py| 4 +-
> .../FspmWrapperPeim/FspmWrapperPeim.c | 25 +-
> .../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +-
> .../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 +
> .../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
> .../{Ia32 => }/Fsp.h | 0
> .../Ia32/Stack.nasm| 6 +-
> .../SecFspWrapperPlatformSecLibSample.inf | 7 +-
> .../SecRamInitData.c | 22 +-
> .../X64/PeiCoreEntry.nasm | 149 +++
> .../X64/SecEntry.nasm | 171 +++
> .../X64/Stack.nasm | 73 +++
> 48 files changed, 2413 insertions(+), 110 deletions(-) create mode 100644
> IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
> create mode 100644
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm
> create mode 100
Re: [edk2-devel][PATCH v5 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
Thanks for fixing issues Ted!
For this patch series: Reviewed-by: Chasel Chiu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Kuo,
> Ted
> Sent: Friday, April 15, 2022 4:38 PM
> To: devel@edk2.groups.io
> Subject: [edk2-devel][PATCH v5 0/8] Support PEI 64bit in IntelFsp2Pkg and
> IntelFsp2WrapperPkg
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
>
> Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
> IntelFsp2WrapperPkg. The patches below are needed to support these
> drivers/libraries in 64bit.
>
> V2 changes:
> 1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in
> FspApiEntryM.nasm.
> 2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
> 3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
>
> V3 changes:
> 1.Update FSPT_ARCH2_UPD and add FSPT_CORE_UPD back.
> 2.Use 0x instead of MAX_ADDRESS to reflect the default of
> FspData.
> 3.Remove EnableMultiPhaseMemoryInit from FSPM_ARCH2_UPD.
> 4.Bump GenCfgOpt version to 0.57.
>
> V4 changes:
> 1.Added EFIAPI to SwapStack and PEI_CORE_ENTRY.
> 2.Cast FspData from pointer to UINTN and then from UINTN to UINT32.
> 3.Corrected few typos.
>
> Ted Kuo (8):
> IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
> IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
> IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
> IntelFsp2Pkg: FspSecCore support for X64
> IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
> IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
> IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
> IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for
> X64
>
> V5
> 1.Extend Copyright year to 2022 for the modified files 2.Check
> FSPM_UPD_COMMON_FSP24.Revision before configuring FSP stack.
> 3.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for FSP
> global data in FspApiCallingCheck().
> 4.Remove EnableMultiPhaseSiliconInit from FSPS_ARCH2_UPD.
> 5.Add an additional ExcludedSpecificUpd1 to exclude FSPx_ARCH2_UPD in
> GenCfgOpt.py tool.
>
> IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 3 +-
> IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 10 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 11 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 10 +-
> IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 12 +-
> .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 6 +-
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 32 +-
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 98 +++-
> IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 10 +-
> IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 12 +-
> IntelFsp2Pkg/FspSecCore/SecFsp.c | 12 +-
> IntelFsp2Pkg/FspSecCore/SecFsp.h | 4 +-
> IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 10 +-
> IntelFsp2Pkg/FspSecCore/SecMain.c | 10 +-
> IntelFsp2Pkg/FspSecCore/SecMain.h | 20 +-
> IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 271 +++
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495
> +
> IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
> IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
> IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
> IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
> IntelFsp2Pkg/Include/FspEas/FspApi.h | 139 +-
> IntelFsp2Pkg/Include/FspGlobalData.h | 53 ++-
> IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 16 +-
> IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
> IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 +-
> .../Library/BaseFspCommonLib/FspCommonLib.c| 6 +-
> .../BaseFspSwitchStackLib/FspSwitchStackLib.c | 3 +-
> .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
> .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-
> .../SecFspSecPlatformLibNull.inf | 8 +-
> .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
> .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
> IntelFsp2Pkg/Tools/GenCfgOpt.py| 7 +-
> .../FspmWrapperPeim/FspmWrapperPeim.c | 27 +-
> .../BaseFspWrapperApiLib/FspWrapperApiLib.c| 44 +-
> .../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 23 +-
> .../BaseFspWrapperApiLib/X64/DispatchExecute.c | 47 +-
> .../{Ia32 => }/Fsp.h | 0
> .../Ia32/Stack.nasm| 8 +-
> .../SecFspWrapperPlatformSecLibSample.inf | 9 +-
> .../SecRamInitData.c | 24 +-
> .../X64/PeiCoreEntry.nas
Re: [edk2-devel] [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset and width PCDs
Thanks Michael! For this patch series: Reviewed-by: Chasel Chiu > -Original Message- > From: mikub...@linux.microsoft.com > Sent: Tuesday, April 12, 2022 4:58 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Gao, Liming > ; Dong, Eric > Subject: [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty > offset and width PCDs > > From: Michael Kubacki > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3543 > > Adds PCDs to the MinPlatformPkg DEC file so MinPlatformPkg consumers > (board packages) can customize the DUTY_OFFSET and DUTY_CYCLE values > in their build files. > > The copy of AcpiPlatform in SimicsOpenBoardPkg is also updated to keep > the change in sync with the source MinPlatformPkg module. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Eric Dong > Signed-off-by: Michael Kubacki > > Michael Kubacki (3): > MinPlatformPkg: Add FADT duty offset and duty width PCDs > MinPlatformPkg/AcpiPlatform: Use FADT duty offset and width PCDs > SimicsOpenBoardPkg/AcpiPlatform: Use FADT duty offset and width PCDs > > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > | 3 +++ > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c > | 4 ++-- > > Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Ac > piPlatform.c | 3 +++ > > Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Fa > dt/Fadt.c | 4 ++-- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > | 2 ++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec >| > 15 +++ > > Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Ac > piPlatform.inf | 2 ++ > 7 files changed, 29 insertions(+), 4 deletions(-) > > -- > 2.28.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89251): https://edk2.groups.io/g/devel/message/89251 Mute This Topic: https://groups.io/mt/90405218/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention
Thanks Chinni! Just few comments below inline, please help to check. Would you also help to update commit message format and include Bugzilla link for reference? Thanks, Chasel > -Original Message- > From: devel@edk2.groups.io On Behalf Of > cbduggap > Sent: Thursday, May 12, 2022 5:13 PM > To: devel@edk2.groups.io > Subject: [edk2-devel] [PATCH v2] FSP_TEMP_RAM_INIT API call must follow > X64 Calling Convention > > This API accept one parameter using RCX and this is consumed in mutiple > sub functions. > Signed-off-by: cbduggap > --- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 21 -- > .../Include/SaveRestoreSseAvxNasm.inc | 28 +++ > 2 files changed, 40 insertions(+), 9 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index a9f5f28ed7..cddc41125e 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): > cmprsp, 0jz ParamError- moveax, dword [rsp + 8]; > Parameter pointer- cmpeax, 0+ cmpecx, 0jz ParamError- > mov Do you have corresponding change for IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm to pass parameters by RCX? Please help to update comments for LoadMicrocodeDefault as it still mentioning below old implementation: ; Inputs: ; rsp -> LoadMicrocodeParams pointer > esp, eax+ movesp, ecx ; skip loading Microcode if the > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ - > 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): >; ; Save parameter pointer in rdx ;- mov rdx, qword [rsp + 8]-+ > mov > rdx, rcx ; ; Enable FSP STACK ;@@ -420,7 +418,10 @@ > ASM_PFX(TempRamInitApi): >; ENABLE_SSE ENABLE_AVX-+ ;+ ; Save Input Parameter in YMM10+ ;+ > SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and > YMM6 ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): >; ; Check Parameter ;- mov rax, qword [rsp + 8]- cmp > rax, 0- > mov rax, 08002h+ cmp rcx, 0+ mov rcx, > 08002h jzTempRamInitExit;@@ -456,17 +456,20 > @@ ASM_PFX(TempRamInitApi): > ; Load microcode LOAD_RSP+ LOAD_RCX CALL_YMM Since we have following X64 calling convention to pass parameter by RCX, I think we do not need LOAD_RSP anymore. Please help to check if we still need it. > ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS rax ; Save > microcode return status in SLOT 0 in YMM9 (upper 128bits). ; @note If > return value rax is not 0, microcode did not load, but continue and attempt > to boot.; Call Sec CAR Init LOAD_RSP+ LOAD_RCX CALL_YMM > ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit > LOAD_RSP+ LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp > rax, 0 jnz TempRamInitExitdiff --git > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > index e8bd91669d..38c807a311 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -177,6 +177,30 @@ > LXMMN xmm5, %1, 1 %endmacro +;+; Upper half of > YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+; > Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN > ymm10, xmm5, 1+SXMMN xmm5, 0, rcx+SYMMN ymm10, > 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+; > Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN > ymm10, xmm5, 1+movqrcx, xmm5+%endmacro+ ; ; > YMM7[128:191] for calling stack ; arg 1:Entry@@ -231,6 +255,7 @@ > NextAddress: > ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to > test ; whether the processor supports SSE instruction. > ;+ > mov r10, rcx mov rax, 1 cpuid bt > rdx, 25@@ - > 241,6 +266,7 @@ NextAddress: > ; bt ecx, 19 jnc SseError+ > mov rcx, > r10 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit > #10)@@ -258,6 +284,7 @@ NextAddress: > %endmacro %macro ENABLE_AVX 0+mov r10, rcx > mov eax, 1 cpuid and ecx, 1000h@@ -280,5 > +307,6 > @@ EnableAvx: > xgetbv ; result in edx:eax or > eax, 0006h ; Set > XCR0 bit #1 and bit #2 to enable SSE state and AVX state xsetbv+ > mov rcx, r10 %endmacro -- > 2.36.0.windows.1 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#89694): > https://edk2.groups.
Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks for correcting format and updating patch per feedbacks! Just one more comment below inline and please also help to include patch of IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm for passing API parameter by RCX. You might want to create a patch series: [1/2] IntelFsp2Pkg patch [2/2] IntelFsp2WrapperPkg patch Thanks, Chasel > -Original Message- > From: Duggapu, Chinni B > Sent: Monday, May 16, 2022 6:54 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow > X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > This API accept one parameter using RCX and this is consumed in mutiple > sub functions. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 - > .../Include/SaveRestoreSseAvxNasm.inc | 28 +++ > 2 files changed, 41 insertions(+), 13 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index a9f5f28ed7..9504c96b81 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -114,7 +114,7 @@ endstruc > global ASM_PFX(LoadMicrocodeDefault) > ASM_PFX(LoadMicrocodeDefault):; Inputs:- ; rsp -> > LoadMicrocodeParams pointer+ ; rcx -> LoadMicrocodeParams pointer; > Register Usage:; rsp Preserved; All others destroyed@@ -130,10 > +130,9 @@ ASM_PFX(LoadMicrocodeDefault): > cmprsp, 0jz ParamError- moveax, dword [rsp + 8]; > Parameter pointer- cmpeax, 0+ cmpecx, 0jz ParamError- > mov > esp, eax+ movesp, ecx I think we do not need to modify esp because now esp/rsp only containing return address initialized by caller. ; skip loading Microcode if the > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ - > 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): >; ; Save parameter pointer in rdx ;- mov rdx, qword [rsp + 8]-+ > mov > rdx, rcx ; ; Enable FSP STACK ;@@ -420,7 +418,10 @@ > ASM_PFX(TempRamInitApi): >; ENABLE_SSE ENABLE_AVX-+ ;+ ; Save Input Parameter in YMM10+ ;+ > SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and > YMM6 ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): >; ; Check Parameter ;- mov rax, qword [rsp + 8]- cmp > rax, 0- > mov rax, 08002h+ cmp rcx, 0+ mov rcx, > 08002h jzTempRamInitExit;@@ -455,18 +455,18 > @@ ASM_PFX(TempRamInitApi): >jnz TempRamInitExit; Load microcode- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS > rax ; Save microcode return status in SLOT 0 in YMM9 (upper > 128bits). ; @note If return value rax is not 0, microcode did not load, but > continue and attempt to boot.; Call Sec CAR Init- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit > - LOAD_RSP+ LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp > rax, 0 jnz TempRamInitExitdiff --git > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > index e8bd91669d..38c807a311 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -177,6 +177,30 @@ > LXMMN xmm5, %1, 1 %endmacro +;+; Upper half of > YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+; > Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN > ymm10, xmm5, 1+SXMMN xmm5, 0, rcx+SYMMN ymm10, > 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+; > Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN > ymm10, xmm5, 1+movqrcx, xmm5+%endmacro+ ; ; > YMM7[128:191] for calling stack ; arg 1:Entry@@ -231,6 +255,7 @@ > NextAddress: > ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to > test ; whether the processor supports SSE instruction. > ;+ > mov r10, rcx mov rax, 1 cpuid bt > rdx, 25@@ - > 241,6 +266,7 @@ NextAddress: > ; bt ecx, 19 jnc SseError+ > mov rcx, > r10 ; ; Set OSFXSR bit (bit #9) &am
Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks for clarification! In this case, please use "mov rsp, rcx" to support 64bit addressing. Thanks, Chasel > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 12:33 AM > To: Chiu, Chasel ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Zeng, Star > ; S, Ashraf Ali > Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must > follow X64 Calling Convention > > HI Chasel, > Yes, we don't need to modify esp for LoadMicrocodeDefault. However, this > function does couple of MSR Accesses in b/w that would lead to modify RCX > anyway. > So, if not RSP, we need to use different register to save RCX and consume in > the whole function. > > That's why I have not changed the usage of RSP to hold the input parameter. > > > > Thanks, > Chinni. > > -Original Message- > From: Chiu, Chasel > Sent: Monday, May 16, 2022 5:38 PM > To: Duggapu, Chinni B ; > devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Zeng, Star > ; S, Ashraf Ali > Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must > follow X64 Calling Convention > > > Thanks for correcting format and updating patch per feedbacks! > Just one more comment below inline and please also help to include patch > of > IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\S > ecEntry.nasm for passing API parameter by RCX. > You might want to create a patch series: > [1/2] IntelFsp2Pkg patch > [2/2] IntelFsp2WrapperPkg patch > > Thanks, > Chasel > > > -Original Message- > > From: Duggapu, Chinni B > > Sent: Monday, May 16, 2022 6:54 PM > > To: devel@edk2.groups.io > > Cc: Chiu, Chasel ; Desimone, Nathaniel L > > ; Zeng, Star ; S, > > Ashraf Ali > > Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow > > X64 Calling Convention > > > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > > This API accept one parameter using RCX and this is consumed in > > mutiple sub functions. > > > > Cc: Chasel Chiu > > Cc: Nate DeSimone > > Cc: Star Zeng > > Cc: Ashraf Ali S > > Signed-off-by: cbduggap > > --- > > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 - > > .../Include/SaveRestoreSseAvxNasm.inc | 28 > +++ > > 2 files changed, 41 insertions(+), 13 deletions(-) > > > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > > index a9f5f28ed7..9504c96b81 100644 > > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > > @@ -114,7 +114,7 @@ endstruc > > global ASM_PFX(LoadMicrocodeDefault) > > ASM_PFX(LoadMicrocodeDefault):; Inputs:- ; rsp -> > > LoadMicrocodeParams pointer+ ; rcx -> LoadMicrocodeParams > pointer; > > Register Usage:; rsp Preserved; All others destroyed@@ -130,10 > > +130,9 @@ ASM_PFX(LoadMicrocodeDefault): > > cmprsp, 0jz ParamError- moveax, dword [rsp + 8]; > > Parameter pointer- cmpeax, 0+ cmpecx, 0jz ParamError- > > mov > > esp, eax+ movesp, ecx > > > > I think we do not need to modify esp because now esp/rsp only containing > return address initialized by caller. > > > > ; skip loading Microcode if the > > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ - > > 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): > >; ; Save parameter pointer in rdx ;- mov rdx, qword [rsp + > > 8]-+ > mov > > rdx, rcx ; ; Enable FSP STACK ;@@ -420,7 +418,10 @@ > > ASM_PFX(TempRamInitApi): > >; ENABLE_SSE ENABLE_AVX-+ ;+ ; Save Input Parameter in > YMM10+ ;+ > > SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and > > YMM6 ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): > >; ; Check Parameter ;- mov rax, qword [rsp + 8]- cmp > > rax, 0- > > mov rax, 08002h+ cmp rcx, 0+ mov rcx, > > 08002h jzTempRamInitExit;@@ -455,18 +455,18 > > @@ ASM_PFX(TempRamInitApi): > >jnz TempRamInitExit; Load microcode- LOAD_RSP+ LOAD_RCX > > CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS > > rax ; Save microcode return status in SLOT 0 in YMM9 (upper > > 128bits). ; @note If return value rax is not 0, microcode did not load, > > but > > continue and attempt to boot.; Cal
[edk2-devel] [PATCH V1 1/1] MinPlatformPkg: Add PCDs to update FADT entries from board package
From: Ankit Sinha Adds new PCDs to allow entries in FADT to be customized during platform integration. Board packages will can update these PCDs during boot. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Eric Dong Signed-off-by: Ankit Sinha --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 85 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 24 ++ Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 36 +++-- 3 files changed, 105 insertions(+), 40 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 05fc7799fb13..b3d067def3fa 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -1165,6 +1165,11 @@ PlatformUpdateTables ( // Update the creator revision // TableHeader->CreatorRevision = PcdGet32(PcdAcpiDefaultCreatorRevision); + + // + // Update the oem revision + // + TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision); } } @@ -1187,44 +1192,54 @@ PlatformUpdateTables ( case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table; -FadtHeader->PreferredPmProfile = PcdGet8 (PcdFadtPreferredPmProfile); -FadtHeader->IaPcBootArch = PcdGet16 (PcdFadtIaPcBootArch); -FadtHeader->Flags = PcdGet32 (PcdFadtFlags); +FadtHeader->PreferredPmProfile= PcdGet8 (PcdFadtPreferredPmProfile); +FadtHeader->IaPcBootArch = PcdGet16 (PcdFadtIaPcBootArch); +FadtHeader->Flags = PcdGet32 (PcdFadtFlags); +FadtHeader->AcpiEnable= PcdGet8 (PcdAcpiEnableSwSmi); +FadtHeader->AcpiDisable = PcdGet8 (PcdAcpiDisableSwSmi); +FadtHeader->Pm1aEvtBlk= PcdGet16 (PcdAcpiPm1AEventBlockAddress); +FadtHeader->Pm1bEvtBlk= PcdGet16 (PcdAcpiPm1BEventBlockAddress); +FadtHeader->Pm1aCntBlk= PcdGet16 (PcdAcpiPm1AControlBlockAddress); +FadtHeader->Pm1bCntBlk= PcdGet16 (PcdAcpiPm1BControlBlockAddress); +FadtHeader->Pm2CntBlk = PcdGet16 (PcdAcpiPm2ControlBlockAddress); +FadtHeader->PmTmrBlk = PcdGet16 (PcdAcpiPmTimerBlockAddress); +FadtHeader->Gpe0Blk = PcdGet16 (PcdAcpiGpe0BlockAddress); +FadtHeader->Gpe0BlkLen= PcdGet8 (PcdAcpiGpe0BlockLength); +FadtHeader->Gpe1Blk = PcdGet16 (PcdAcpiGpe1BlockAddress); +FadtHeader->Gpe1Base = PcdGet8 (PcdAcpiGpe1Base); +FadtHeader->DutyWidth = PcdGet8 (PcdAcpiDutyWidth); -FadtHeader->AcpiEnable = PcdGet8 (PcdAcpiEnableSwSmi); -FadtHeader->AcpiDisable = PcdGet8 (PcdAcpiDisableSwSmi); +FadtHeader->XPm1aEvtBlk.Address = PcdGet16 (PcdAcpiPm1AEventBlockAddress); +FadtHeader->XPm1aCntBlk.Address = PcdGet16 (PcdAcpiPm1AControlBlockAddress); +FadtHeader->XPm1bCntBlk.Address = PcdGet16 (PcdAcpiPm1BControlBlockAddress); +FadtHeader->XPm2CntBlk.Address= PcdGet16 (PcdAcpiPm2ControlBlockAddress); +FadtHeader->XPmTmrBlk.Address = PcdGet16 (PcdAcpiPmTimerBlockAddress); +FadtHeader->XGpe0Blk.Address = PcdGet16 (PcdAcpiGpe0BlockAddress); +FadtHeader->XGpe1Blk.Address = PcdGet16 (PcdAcpiGpe1BlockAddress); -FadtHeader->Pm1aEvtBlk = PcdGet16 (PcdAcpiPm1AEventBlockAddress); -FadtHeader->Pm1bEvtBlk = PcdGet16 (PcdAcpiPm1BEventBlockAddress); -FadtHeader->Pm1aCntBlk = PcdGet16 (PcdAcpiPm1AControlBlockAddress); -FadtHeader->Pm1bCntBlk = PcdGet16 (PcdAcpiPm1BControlBlockAddress); -FadtHeader->Pm2CntBlk = PcdGet16 (PcdAcpiPm2ControlBlockAddress); -FadtHeader->PmTmrBlk = PcdGet16 (PcdAcpiPmTimerBlockAddress); -FadtHeader->Gpe0Blk= PcdGet16 (PcdAcpiGpe0BlockAddress); -FadtHeader->Gpe0BlkLen = 0x20; -FadtHeader->Gpe1Blk= PcdGet16 (PcdAcpiGpe1BlockAddress); +FadtHeader->ResetReg.AccessSize = PcdGet8 (PcdAcpiResetRegAccessSize); +FadtHeader->XPm1aEvtBlk.AccessSize= PcdGet8 (PcdAcpiXPm1aEvtBlkAccessSize); +FadtHeader->XPm1bEvtBlk.AccessSize= PcdGet8 (PcdAcpiXPm1bEvtBlkAccessSize); +FadtHeader->XPm1aCntBlk.AccessSize= PcdGet8 (PcdAcpiXPm1aCntBlkAccessSize); +FadtHeader->XPm1bCntBlk.AccessSize= PcdGet8 (PcdAcpiXPm1bCntBlkAccessSize); +FadtHeader->XPm2CntBlk.AccessSize = PcdGet8 (PcdAcpiXPm2CntBlkAccessSize); +FadtHeader->XPmTmrBlk.AccessSize = Pc
Re: [edk2-devel] [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks Chinni! Reviewed-by: Chasel Chiu > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 1:07 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must > follow X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > This API accept one parameter using RCX and this is consumed in mutiple > sub functions. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++- > .../Include/SaveRestoreSseAvxNasm.inc | 28 + > 2 files changed, 48 insertions(+), 19 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index a9f5f28ed7..22dbea1fed 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -114,7 +114,7 @@ endstruc > global ASM_PFX(LoadMicrocodeDefault) > ASM_PFX(LoadMicrocodeDefault):; Inputs:- ; rsp -> > LoadMicrocodeParams pointer+ ; rcx -> LoadMicrocodeParams pointer; > Register Usage:; rsp Preserved; All others destroyed@@ -130,10 > +130,9 @@ ASM_PFX(LoadMicrocodeDefault): > cmprsp, 0jz ParamError- moveax, dword [rsp + 8]; > Parameter pointer- cmpeax, 0+ cmprcx, 0jz ParamError- > mov > esp, eax+ movrsp, rcx ; skip loading Microcode if the > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ - > 144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault): > jneParamError ; UPD structure is compliant with FSP spec 2.4- > mov > eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmp > eax, 0+ movrax, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeSize]+ cmprax, 0jz > Exit2- cmpeax, 0800h+ cmprax, 0800hjl ParamError - mov > esi, > dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]- cmpesi, > 0+ movrsi, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]+ cmprsi, 0jnz > CheckMainHeader ParamError:@@ -256,7 +255,8 @@ CheckAddress: > ; UPD structure is compliant with FSP spec 2.4; Is automatic size > detection ?mov rax, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmp rax, > 0h+ cmp rcx, 0h+ cmp rax, rcxjz > LoadMicrocodeDefault4 ; Address >= microcode region address + > microcode region size?@@ -321,8 +321,7 @@ > ASM_PFX(EstablishStackFsp): >; ; Save parameter pointer in rdx ;- mov rdx, qword [rsp + 8]-+ > mov > rdx, rcx ; ; Enable FSP STACK ;@@ -420,7 +419,10 @@ > ASM_PFX(TempRamInitApi): >; ENABLE_SSE ENABLE_AVX-+ ;+ ; Save Input Parameter in YMM10+ ;+ > SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and > YMM6 ;@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi): >; ; Check Parameter ;- mov rax, qword [rsp + 8]- cmp > rax, 0- > mov rax, 08002h+ cmp rcx, 0+ mov rcx, > 08002h jzTempRamInitExit;@@ -455,18 +456,18 > @@ ASM_PFX(TempRamInitApi): >jnz TempRamInitExit; Load microcode- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS > rax ; Save microcode return status in SLOT 0 in YMM9 (upper > 128bits). ; @note If return value rax is not 0, microcode did not load, but > continue and attempt to boot.; Call Sec CAR Init- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit > - LOAD_RSP+ LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp > rax, 0 jnz TempRamInitExitdiff --git > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > index e8bd91669d..38c807a311 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -177,6 +177,30 @@ > LXMMN xmm5, %1, 1 %endmacro +;+; Upper half of > YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+; > Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN > ymm10, xmm5, 1+SXMMN xmm5, 0, rcx+SYMMN ymm10, > 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+; > Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN > ymm10, xmm5, 1+movqrcx, xmm5+%endmacro+ ; ;
Re: [edk2-devel] [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks Chinni! Reviewed-by: Chasel Chiu > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 1:07 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call > must follow X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > Pass Input parameters using RCX. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > index dbbf63336e..065d80d0e2 100644 > --- > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > +++ > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > @@ -130,6 +130,9 @@ FspHeaderFound: >mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > >add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > > > > + ; Pass Fsp T Udp pointer as Input parameter > > + mov rcx, ASM_PFX(FsptUpdDataPtr) > > + > >; Setup the hardcode stack > >mov rsp, TempRamInitStack > > > > @@ -167,5 +170,4 @@ FspApiFailed: > align 10h > > TempRamInitStack: > > DQ TempRamInitDone > > -DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams > > > > -- > 2.36.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89802): https://edk2.groups.io/g/devel/message/89802 Mute This Topic: https://groups.io/mt/91157609/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v5 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks for fixing a small coding issue! Reviewed-by: Chasel Chiu > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 4:44 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v5 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must > follow X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > This API accept one parameter using RCX and this is consumed in mutiple > sub functions. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++- > .../Include/SaveRestoreSseAvxNasm.inc | 28 + > 2 files changed, 48 insertions(+), 19 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index a9f5f28ed7..7dd89c531a 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -114,7 +114,7 @@ endstruc > global ASM_PFX(LoadMicrocodeDefault) > ASM_PFX(LoadMicrocodeDefault):; Inputs:- ; rsp -> > LoadMicrocodeParams pointer+ ; rcx -> LoadMicrocodeParams pointer; > Register Usage:; rsp Preserved; All others destroyed@@ -130,10 > +130,9 @@ ASM_PFX(LoadMicrocodeDefault): > cmprsp, 0jz ParamError- moveax, dword [rsp + 8]; > Parameter pointer- cmpeax, 0+ cmprcx, 0jz ParamError- > mov > esp, eax+ movrsp, rcx ; skip loading Microcode if the > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ - > 144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault): > jneParamError ; UPD structure is compliant with FSP spec 2.4- > mov > eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmp > eax, 0+ movrax, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeSize]+ cmprax, 0jz > Exit2- cmpeax, 0800h+ cmprax, 0800hjl ParamError - mov > esi, > dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]- cmpesi, > 0+ movrsi, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]+ cmprsi, 0jnz > CheckMainHeader ParamError:@@ -256,7 +255,8 @@ CheckAddress: > ; UPD structure is compliant with FSP spec 2.4; Is automatic size > detection ?mov rax, qword [rsp + > LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmp rax, > 0h+ mov rcx, 0h+ cmp rax, rcxjz > LoadMicrocodeDefault4 ; Address >= microcode region address + > microcode region size?@@ -321,8 +321,7 @@ > ASM_PFX(EstablishStackFsp): >; ; Save parameter pointer in rdx ;- mov rdx, qword [rsp + 8]-+ > mov > rdx, rcx ; ; Enable FSP STACK ;@@ -420,7 +419,10 @@ > ASM_PFX(TempRamInitApi): >; ENABLE_SSE ENABLE_AVX-+ ;+ ; Save Input Parameter in YMM10+ ;+ > SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and > YMM6 ;@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi): >; ; Check Parameter ;- mov rax, qword [rsp + 8]- cmp > rax, 0- > mov rax, 08002h+ cmp rcx, 0+ mov rcx, > 08002h jzTempRamInitExit;@@ -455,18 +456,18 > @@ ASM_PFX(TempRamInitApi): >jnz TempRamInitExit; Load microcode- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS > rax ; Save microcode return status in SLOT 0 in YMM9 (upper > 128bits). ; @note If return value rax is not 0, microcode did not load, but > continue and attempt to boot.; Call Sec CAR Init- LOAD_RSP+ LOAD_RCX > CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit > - LOAD_RSP+ LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp > rax, 0 jnz TempRamInitExitdiff --git > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > index e8bd91669d..38c807a311 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -177,6 +177,30 @@ > LXMMN xmm5, %1, 1 %endmacro +;+; Upper half of > YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+; > Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN > ymm10, xmm5, 1+SXMMN xmm5, 0, rcx+SYMMN ymm10, > 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+; > Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN > ymm10, xmm5, 1+movqrcx, xmm5+
Re: [edk2-devel] [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Thanks Chinni! Reviewed-by: Chasel Chiu > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 4:44 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call > must follow X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > Pass Input parameters using RCX. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > index dbbf63336e..065d80d0e2 100644 > --- > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > +++ > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > @@ -130,6 +130,9 @@ FspHeaderFound: >mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > >add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > > > > + ; Pass Fsp T Udp pointer as Input parameter > > + mov rcx, ASM_PFX(FsptUpdDataPtr) > > + > >; Setup the hardcode stack > >mov rsp, TempRamInitStack > > > > @@ -167,5 +170,4 @@ FspApiFailed: > align 10h > > TempRamInitStack: > > DQ TempRamInitDone > > -DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams > > > > -- > 2.36.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89871): https://edk2.groups.io/g/devel/message/89871 Mute This Topic: https://groups.io/mt/91159382/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
Reviewed-by: Chasel Chiu
Thanks TungLun!
> -Original Message-
> From: Loo, Tung Lun
> Sent: Thursday, May 12, 2022 7:26 AM
> To: devel@edk2.groups.io
> Cc: Loo, Tung Lun ; Desimone, Nathaniel L
> ; Zeng, Star ; Chiu,
> Chasel
> Subject: [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921
>
> This patch adds a couple of fields supported in FSP 2.3 header from both
> header generation and tool support perspective.
>
> Signed-off-by: Loo Tung Lun
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Chasel Chiu
> ---
> IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py | 63
> ++-
>
> IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py | 14 +++---
> 2 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> index 680b90e09d..5271504282 100644
> --- a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> +++ b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> @@ -13,6 +13,7 @@ import tkinter.ttk as ttk
> import tkinter.messagebox as messagebox import tkinter.filedialog as
> filedialog +from pickle import FALSE, TRUE from pathlib import Path from
> GenYamlCfg import CGenYamlCfg, bytes_to_value, \
> bytes_to_bracket_str, value_to_bytes, array_str_to_value@@ -458,7
> +459,10 @@ class FSP_INFORMATION_HEADER(Structure):
> ('NotifyPhaseEntryOffset', c_uint32),
> ('FspMemoryInitEntryOffset', c_uint32), ('TempRamExitEntryOffset',
> c_uint32),-('FspSiliconInitEntryOffset', c_uint32)+
> ('FspSiliconInitEntryOffset', c_uint32),+
> ('FspMultiPhaseSiInitEntryOffset', c_uint32),+
> ('ExtendedImageRevision',
> c_uint16),+('Reserved4', c_uint16) ] @@ -700,6 +704,34 @@
> class FirmwareDevice:
> raise Exception("ERROR: Incorrect FV size in image !")
> self.CheckFsp() +def IsIntegerType(self, val):+if
> sys.version_info[0] <
> 3:+if type(val) in (int, long):+return True+
> else:+if
> type(val) is int:+return True+return False++def
> ConvertRevisionString(self, obj):+for field in obj._fields_:+
>key =
> field[0]+val = getattr(obj, key)+rep = ''++
> if
> self.IsIntegerType(val):+if (key == 'ImageRevision'):+
> FspImageRevisionMajor = ((val >> 24) & 0xFF)+
> FspImageRevisionMinor = ((val >> 16) & 0xFF)+
> FspImageRevisionRevision = ((val >> 8) & 0xFF)+
> FspImageRevisionBuildNumber = (val & 0xFF)+rep = '0x%08X'
> %
> val+elif (key == 'ExtendedImageRevision'):+
> FspImageRevisionRevision |= (val & 0xFF00)+
> FspImageRevisionBuildNumber |= ((val << 8) & 0xFF00)+rep =
> "0x%04X ('%02X.%02X.%04X.%04X')" % (val, FspImageRevisionMajor,
> FspImageRevisionMinor, FspImageRevisionRevision,
> FspImageRevisionBuildNumber)+return rep+ def
> OutputFsp(self): def copy_text_to_clipboard():
> window.clipboard_clear()@@ -721,7 +753,8 @@ class FirmwareDevice:
> self.OutputText = self.OutputText + "Fsp Header Details \n\n"
> while i < len(self.FihList): try:-self.OutputText
> +=
> str(self.BuildList[i].decode()) + "\n"+# self.OutputText +=
> str(self.BuildList[i].decode()) + "\n"+self.OutputText +=
> str(self.BuildList[i]) + "\n" except Exception:
> self.OutputText
> += "No description found\n" self.OutputText += "FSP Header :\n
> "@@ -729,6 +762,8 @@ class FirmwareDevice:
> str(self.FihList[i].Signature.decode('utf-8')) + "\n "
> self.OutputText += "Header Length : " + \
> str(hex(self.FihList[i].HeaderLength)) + "\n "+self.OutputText +=
> "Reserved1 : " + \+str(hex(self.FihList[i].Reserved1)) + "\n "
> self.OutputText += "Header Revision : " + \
> str(hex(self.FihList[i].HeaderRevision)) + "\n " self.OutputText
> +=
> "Spec Version : " + \@@ -743,15 +778,17 @@ class FirmwareDevice:
> str(hex(self.FihList[i].ImageBase)) + "\n "
> self.OutputText +=
> "Image Attribute : &quo
Re: [edk2-devel] [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
Patch pushed:
https://github.com/tianocore/edk2/commit/fa2b212d61dfeb9c00a174280a73a4f573ef617d
Thanks,
Chasel
> -Original Message-
> From: Loo, Tung Lun
> Sent: Thursday, May 12, 2022 7:26 AM
> To: devel@edk2.groups.io
> Cc: Loo, Tung Lun ; Desimone, Nathaniel L
> ; Zeng, Star ; Chiu,
> Chasel
> Subject: [PATCH] IntelFsp2Pkg: Add FSP 2.3 header support
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921
>
> This patch adds a couple of fields supported in FSP 2.3 header from both
> header
> generation and tool support perspective.
>
> Signed-off-by: Loo Tung Lun
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Chasel Chiu
> ---
> IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py | 63
> ++-
> IntelFsp2Pkg/Tools/ConfigEditor/GenYamlCfg.py | 14 +++---
> 2 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> index 680b90e09d..5271504282 100644
> --- a/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> +++ b/IntelFsp2Pkg/Tools/ConfigEditor/ConfigEditor.py
> @@ -13,6 +13,7 @@ import tkinter.ttk as ttk
> import tkinter.messagebox as messagebox import tkinter.filedialog as
> filedialog
> +from pickle import FALSE, TRUE from pathlib import Path from GenYamlCfg
> import CGenYamlCfg, bytes_to_value, \ bytes_to_bracket_str,
> value_to_bytes, array_str_to_value@@ -458,7 +459,10 @@ class
> FSP_INFORMATION_HEADER(Structure):
> ('NotifyPhaseEntryOffset', c_uint32),
> ('FspMemoryInitEntryOffset',
> c_uint32), ('TempRamExitEntryOffset', c_uint32),-
> ('FspSiliconInitEntryOffset', c_uint32)+('FspSiliconInitEntryOffset',
> c_uint32),+('FspMultiPhaseSiInitEntryOffset', c_uint32),+
> ('ExtendedImageRevision', c_uint16),+('Reserved4', c_uint16)
> ] @@ -
> 700,6 +704,34 @@ class FirmwareDevice:
> raise Exception("ERROR: Incorrect FV size in image !")
> self.CheckFsp() +def IsIntegerType(self, val):+if
> sys.version_info[0] < 3:+
> if type(val) in (int, long):+return True+else:+
> if type(val) is
> int:+return True+return False++def
> ConvertRevisionString(self,
> obj):+for field in obj._fields_:+key = field[0]+
> val = getattr(obj,
> key)+rep = ''++if self.IsIntegerType(val):+
> if (key ==
> 'ImageRevision'):+FspImageRevisionMajor = ((val >> 24) &
> 0xFF)+
> FspImageRevisionMinor = ((val >> 16) & 0xFF)+
> FspImageRevisionRevision = ((val >> 8) & 0xFF)+
> FspImageRevisionBuildNumber = (val & 0xFF)+rep = '0x%08X'
> % val+
> elif (key == 'ExtendedImageRevision'):+
> FspImageRevisionRevision |=
> (val & 0xFF00)+FspImageRevisionBuildNumber |= ((val << 8)
> &
> 0xFF00)+rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val,
> FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision,
> FspImageRevisionBuildNumber)+return rep+ def
> OutputFsp(self):
> def copy_text_to_clipboard(): window.clipboard_clear()@@ -721,7
> +753,8 @@ class FirmwareDevice:
> self.OutputText = self.OutputText + "Fsp Header Details \n\n"
> while i <
> len(self.FihList): try:-self.OutputText +=
> str(self.BuildList[i].decode()) + "\n"+# self.OutputText +=
> str(self.BuildList[i].decode()) + "\n"+self.OutputText +=
> str(self.BuildList[i]) + "\n" except Exception:
> self.OutputText +=
> "No description found\n" self.OutputText += "FSP Header :\n "@@
> -729,6
> +762,8 @@ class FirmwareDevice:
> str(self.FihList[i].Signature.decode('utf-8')) + "\n "
> self.OutputText += "Header Length : " + \
> str(hex(self.FihList[i].HeaderLength)) + "\n "+self.OutputText +=
> "Reserved1 : " + \+str(hex(self.FihList[i].Reserved1)) + "\n "
> self.OutputText += "Header Revision : " + \
> str(hex(self.FihList[i].HeaderRevision)) + "\n " self.OutputText
> += "Spec
> Version : "
Re: [edk2-devel] [PATCH V2 1/1] MinPlatformPkg: Add PCDs to update FADT entries from board package
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Wednesday, June 8, 2022 7:23 AM > To: devel@edk2.groups.io > Cc: Sinha, Ankit ; Chiu, Chasel > ; > Gao, Liming ; Dong, Eric ; > Kubacki, Michael > Subject: [PATCH V2 1/1] MinPlatformPkg: Add PCDs to update FADT entries from > board package > > From: Ankit Sinha > > Adds new PCDs to allow entries in FADT to be customized during platform > integration. Board packages will can update these PCDs during boot. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Eric Dong > Cc: Michael Kubacki > > Signed-off-by: Ankit Sinha > --- > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 84 > > Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 23 ++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 43 > +++--- > 3 files changed, 106 insertions(+), 44 deletions(-) > > diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > index 508de9101306..3c9f79de5c6c 100644 > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c > @@ -1165,6 +1165,11 @@ PlatformUpdateTables ( >// Update the creator revision >// >TableHeader->CreatorRevision = PcdGet32(PcdAcpiDefaultCreatorRevision); > + > + // > + // Update the oem revision > + // > + TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision); > } >} > > @@ -1187,44 +1192,53 @@ PlatformUpdateTables ( >case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: > FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table; > > -FadtHeader->PreferredPmProfile = PcdGet8 (PcdFadtPreferredPmProfile); > -FadtHeader->IaPcBootArch = PcdGet16 (PcdFadtIaPcBootArch); > -FadtHeader->Flags = PcdGet32 (PcdFadtFlags); > +FadtHeader->PreferredPmProfile= PcdGet8 > (PcdFadtPreferredPmProfile); > +FadtHeader->IaPcBootArch = PcdGet16 > (PcdFadtIaPcBootArch); > +FadtHeader->Flags = PcdGet32 (PcdFadtFlags); > +FadtHeader->AcpiEnable= PcdGet8 > (PcdAcpiEnableSwSmi); > +FadtHeader->AcpiDisable = PcdGet8 > (PcdAcpiDisableSwSmi); > +FadtHeader->Pm1aEvtBlk= PcdGet16 > (PcdAcpiPm1AEventBlockAddress); > +FadtHeader->Pm1bEvtBlk= PcdGet16 > (PcdAcpiPm1BEventBlockAddress); > +FadtHeader->Pm1aCntBlk= PcdGet16 > (PcdAcpiPm1AControlBlockAddress); > +FadtHeader->Pm1bCntBlk= PcdGet16 > (PcdAcpiPm1BControlBlockAddress); > +FadtHeader->Pm2CntBlk = PcdGet16 > (PcdAcpiPm2ControlBlockAddress); > +FadtHeader->PmTmrBlk = PcdGet16 > (PcdAcpiPmTimerBlockAddress); > +FadtHeader->Gpe0Blk = PcdGet16 > (PcdAcpiGpe0BlockAddress); > +FadtHeader->Gpe0BlkLen= PcdGet8 > (PcdAcpiGpe0BlockLength); > +FadtHeader->Gpe1Blk = PcdGet16 > (PcdAcpiGpe1BlockAddress); > +FadtHeader->Gpe1Base = PcdGet8 > (PcdAcpiGpe1Base); > > -FadtHeader->AcpiEnable = PcdGet8 (PcdAcpiEnableSwSmi); > -FadtHeader->AcpiDisable = PcdGet8 (PcdAcpiDisableSwSmi); > +FadtHeader->XPm1aEvtBlk.Address = PcdGet16 > (PcdAcpiPm1AEventBlockAddress); > +FadtHeader->XPm1aCntBlk.Address = PcdGet16 > (PcdAcpiPm1AControlBlockAddress); > +FadtHeader->XPm1bCntBlk.Address = PcdGet16 > (PcdAcpiPm1BControlBlockAddress); > +FadtHeader->XPm2CntBlk.Address= PcdGet16 > (PcdAcpiPm2ControlBlockAddress); > +FadtHeader->XPmTmrBlk.Address = PcdGet16 > (PcdAcpiPmTimerBlockAddress); > +FadtHeader->XGpe0Blk.Address = PcdGet16 > (PcdAcpiGpe0BlockAddress); > +FadtHeader->XGpe1Blk.Address = PcdGet16 > (PcdAcpiGpe1BlockAddress); > > -FadtHeader->Pm1aEvtBlk = PcdGet16 (PcdAcpiPm1AEventBlockAddress); > -FadtHeader->Pm1bEvtBlk = PcdGet16 (PcdAcpiPm1BEventBlockAddress); > -FadtHeader->Pm1aCntBlk = PcdGet16 (PcdAcpiPm1AControlBlockAddress); > -FadtHeader->Pm1bCntBlk = PcdGet16 (PcdAcpiPm1BControlBlockAddress); > -Fad
Re: [edk2-devel] [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:17 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael > ; Benjamin Doron > ; Soller, Jeremy > Subject: [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate > width of CLK duty cycle in FADT > > Set the location of the DUTY_CYCLE field in the P_CNT register and indicate > the > width of the clock duty cycle to OS power management > > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Benjamin Doron > Cc: Jeremy Soller > Signed-off-by: Nate DeSimone > --- > .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 - > .../GalagoPro3/OpenBoardPkgPcd.dsc| 8 +++- > .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +-- > 3 files changed, 24 insertions(+), 4 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > index 21ee86403d..02080aa864 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc > d.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > +++ Pcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the Aspire VN7-572G board. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -346,6 +346,13 @@ >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and > BIOS Guard not present, measured boot enforcement checking code not present >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + >## ># Platform Configuration >## > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > index 44dacdf082..dce4db17c2 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the GalagoPro3 board. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2019 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -251,6 +251,12 @@ >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > > gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui > d.PcdPciExpressBaseAddress > > gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp > aceGuid.PcdPciExpressRegionLength > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > index 725596cbf7..ccf757e202 100644 > --- > a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d > +++ sc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the KabylakeRvp3 board. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2017 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +78,7 @@ ># so FSP needs more temporary memory for FSP heap + stack size. ># >gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 > + ># ># FSP API mode does not need to enlarge the boot loader stack size ># since the stacks are separate. > @@ -290,6 +291,13 @@ >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 >gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > + # > + # Set the location of the
Re: [edk2-devel] [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:17 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael > > Subject: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate > width of CLK duty cycle in FADT > > Set the location of the DUTY_CYCLE field in the P_CNT register and indicate > the > width of the clock duty cycle to OS power management > > Cc: Chasel Chiu > Cc: Michael Kubacki > Signed-off-by: Nate DeSimone > --- > .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 - > .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 - > 2 files changed, 16 insertions(+), 2 deletions(-) > > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > index 84d4ec1331..8f3cc6ba28 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds > +++ c > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the UpXtreme board. > # > -# Copyright (c) 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2020 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -259,6 +259,13 @@ >gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 > > gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa > ceGuid.PcdPciExpressRegionLength > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + >## ># Platform Configuration >## > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > index 4a7ba4d5f0..4a5d5ef03b 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk > +++ gPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the WhiskeylakeURvp board. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2019 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -242,6 +242,13 @@ >## > > gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa > ceGuid.PcdPciExpressRegionLength > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + >## ># Platform Configuration >## > -- > 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90316): https://edk2.groups.io/g/devel/message/90316 Mute This Topic: https://groups.io/mt/91589973/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:17 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael > ; Chaganty, Rangasai V > ; Kethi Reddy, Deepika > ; Esakkithevar, Kathappan > > Subject: [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate > width of CLK duty cycle in FADT > > Set the location of the DUTY_CYCLE field in the P_CNT register and indicate > the > width of the clock duty cycle to OS power management > > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Rangasai V Chaganty > Cc: Deepika Kethi Reddy > Cc: Kathappan Esakkithevar > Signed-off-by: Nate DeSimone > --- > .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd. > dsc > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd. > dsc > index 589b002d06..68dd08423b 100644 > --- > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd. > dsc > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd > +++ .dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the CometlakeURvp board. > # > -# Copyright (c) 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2020 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -253,6 +253,13 @@ >gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 >gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + ># ># The PCDs are used to control the Windows SMM Security Mitigations Table - > Protection Flags ># > -- > 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90317): https://edk2.groups.io/g/devel/message/90317 Mute This Topic: https://groups.io/mt/91589976/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add FSP Dispatch Mode PCDs
Reviewed-by: Chasel Chiu Thanks, Chasel > -Original Message- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:09 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Sinha, Ankit > ; > Kubacki, Michael ; Soller, Jeremy > > Subject: [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add > FSP Dispatch Mode PCDs > > Adds missing FSP dispatch mode PCDs to the Galago Pro 3. > > Cc: Chasel Chiu > Cc: Ankit Sinha > Cc: Michael Kubacki > Cc: Jeremy Soller > Signed-off-by: Nate DeSimone > --- > .../GalagoPro3/OpenBoardPkgPcd.dsc| 46 +-- > 1 file changed, 42 insertions(+), 4 deletions(-) > > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > index 44dacdf082..28f044df5e 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the GalagoPro3 board. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2019 - 2022, Intel Corporation. All rights > +reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -40,6 +40,26 @@ ># >gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE > > + # > + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs > + #(both inside FSP and outside FSP). > + #Pros: > + # * PEI Main is re-built from source and is always the latest > version > + # * Platform code can link any desired LibraryClass to PEI Main > + #(Ex: Custom DebugLib instance, SerialPortLib, etc.) > + #Cons: > + # * The PEI Main being used to execute FSP PEIMs is not the PEI > Main > + #that the FSP PEIMs were tested with, adding risk of breakage. > + # * Two copies of PEI Main will exist in the final binary, > + ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never > + #executed, wasting space. > + # > + # TRUE: The PEI Main included in FSP is used to dispatch all PEIMs > + #(both inside FSP and outside FSP). PEI Main will not be included > in > + #FvPreMemory. This is the default and is the recommended choice. > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE > + ># ># FSP Base address PCD will be updated in FDF basing on flash map. ># > @@ -52,6 +72,7 @@ >gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004 >gSiPkgTokenSpaceGuid.PcdTsegSize|0x100 > > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 ># ># FSP API mode does not share stack with the boot loader, ># so FSP needs more temporary memory for FSP heap + stack size. > @@ -63,6 +84,24 @@ ># since the stacks are separate. ># >gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2 > +!else > + # > + # In FSP Dispatch mode boot loader stack size must be large > + # enough for executing both boot loader and FSP. > + # > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x4 > +!endif > + > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || > +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) > + > +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceG > ui > +d.PcdPciExpressBaseAddress > + > +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenS > p > +aceGuid.PcdPciExpressRegionLength > +!else > + # > + # FSP Dispatch mode requires more platform memory as boot loader and > +FSP sharing the same > + # platform memory. > + # > + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x550 > +!endif > > [PcdsFeatureFlag.common] >## > @@ -222,7 +261,7 @@ >gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 >gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1 >gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2 > - > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || > +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) ># ># In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild ># (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7 @@ ># 3: Place AP in the Run-Loop state. ># @Prompt The AP wait loop state. >gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 > +!endif > >## &g
Re: [edk2-devel] [edk2-non-osi] [PATCH V1 0/2] Add CometlakeSiliconBinPkg
For this series, Reviewed-by: Chasel Chiu > -Original Message- > From: Desimone, Nathaniel L > Sent: Wednesday, September 2, 2020 3:11 PM > To: devel@edk2.groups.io > Cc: Esakkithevar, Kathappan ; Chaganty, > Rangasai V ; Chiu, Chasel > > Subject: [edk2-non-osi] [PATCH V1 0/2] Add CometlakeSiliconBinPkg > > Adds binary package for Comet Lake. > > Cc: Kathappan Esakkithevar > Cc: Sai Chaganty > Cc: Chasel Chiu > Signed-off-by: Nate DeSimone > > Nate DeSimone (2): > CometlakeSiliconBinPkg: Add package contents > edk2-non-osi: Add CometlakeSiliconBinPkg maintainers > > Maintainers.txt | 4 ++ > .../CnlPchLpChipsetInitTable_Dx.bin | Bin 0 -> 4620 bytes > .../Intel/CometlakeSiliconBinPkg/License.txt | 30 ++ > .../Microcode/IntelMicrocodeLicense.txt | 37 > ++ > .../Microcode/MicrocodeUpdates.inf| 18 + > .../Microcode/m94806EC_00D6.mcb | Bin 0 -> 103424 > bytes > 6 files changed, 89 insertions(+) > create mode 100644 > Silicon/Intel/CometlakeSiliconBinPkg/ChipsetInit/CnlPchLpChipsetInitTable_D > x.bin > create mode 100644 Silicon/Intel/CometlakeSiliconBinPkg/License.txt > create mode 100644 > Silicon/Intel/CometlakeSiliconBinPkg/Microcode/IntelMicrocodeLicense.txt > create mode 100644 > Silicon/Intel/CometlakeSiliconBinPkg/Microcode/MicrocodeUpdates.inf > create mode 100644 > Silicon/Intel/CometlakeSiliconBinPkg/Microcode/m94806EC_00D6.mcb > > -- > 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64957): https://edk2.groups.io/g/devel/message/64957 Mute This Topic: https://groups.io/mt/76577641/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms] [PATCH V1] CometlakeOpenBoardPkg: Add usage of CometlakeSiliconBinPkg
Reviewed-by: Chasel Chiu > -Original Message- > From: Desimone, Nathaniel L > Sent: Wednesday, September 2, 2020 3:15 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Chaganty, Rangasai V > ; Kethi Reddy, Deepika > ; Esakkithevar, Kathappan > > Subject: [edk2-platforms] [PATCH V1] CometlakeOpenBoardPkg: Add usage of > CometlakeSiliconBinPkg > > Updates CometlakeOpenBoardPkg to use CometlakeSiliconBinPkg instead of > CoffeelakeSiliconBinPkg. > > Cc: Chasel Chiu > Cc: Rangasai V Chaganty > Cc: Deepika Kethi Reddy > Cc: Kathappan Esakkithevar > Signed-off-by: Nate DeSimone > --- > .../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc | 5 > +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.d > sc > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.d > sc > index 2d9dcb139f..6de834565a 100644 > --- > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.d > sc > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.d > s > +++ c > @@ -10,7 +10,7 @@ > [Defines] >DEFINE PLATFORM_PACKAGE = MinPlatformPkg >DEFINE PLATFORM_SI_PACKAGE = CoffeelakeSiliconPkg > - DEFINE PLATFORM_SI_BIN_PACKAGE = CoffeelakeSiliconBinPkg > + DEFINE PLATFORM_SI_BIN_PACKAGE = CometlakeSiliconBinPkg >DEFINE PLATFORM_FSP_BIN_PACKAGE = > CometLakeFspBinPkg/CometLake1 >DEFINE PLATFORM_BOARD_PACKAGE= > CometlakeOpenBoardPkg >DEFINE BOARD = CometlakeURvp > @@ -39,7 +39,8 @@ ># ># Include PCD configuration for this board. ># > - !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > > + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > + >!include OpenBoardPkgPcd.dsc >!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc > > -- > 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64961): https://edk2.groups.io/g/devel/message/64961 Mute This Topic: https://groups.io/mt/76577729/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only case.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2883
MpServices Ppi can be replaced by MpServices2 Ppi and MpServices2
Ppi is mandatory for RegisterCpuFeaturesLib functionality,
basing on this we can drop MpServices Ppi usage from the library
and the constraint that both Ppis must be installed.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c | 61
+++--
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 6
+++---
2 files changed, 26 insertions(+), 41 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 64768f7a74..4e558e9fee 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -1,7 +1,7 @@
/** @file
CPU Register Table Library functions.
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include "RegisterCpuFeatures.h"
@@ -75,10 +74,10 @@ GetMpService (
MP_SERVICESMpService;
//
- // Get MP Services Protocol
+ // Get MP Services2 Ppi
//
Status = PeiServicesLocatePpi (
- &gEfiPeiMpServicesPpiGuid,
+ &gEdkiiPeiMpServices2PpiGuid,
0,
NULL,
(VOID **)&MpService.Ppi
@@ -100,17 +99,17 @@ GetProcessorIndex (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
UINTN ProcessorIndex;
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// For two reasons which use NULL for WhoAmI:
// 1. This function will be called by APs and AP should not use PeiServices
Table
// 2. Check WhoAmI implementation, this parameter will not be used.
//
- Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, &ProcessorIndex);
+ Status = CpuMp2Ppi->WhoAmI (CpuMp2Ppi, &ProcessorIndex);
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -131,16 +130,15 @@ GetProcessorInformation (
OUT EFI_PROCESSOR_INFORMATION*ProcessorInfoBuffer
)
{
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
EFI_STATUS Status;
CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
- Status = CpuMpPpi->GetProcessorInfo (
- GetPeiServicesTablePointer(),
- CpuMpPpi,
+ Status = CpuMp2Ppi->GetProcessorInfo (
+ CpuMp2Ppi,
ProcessorNumber,
ProcessorInfoBuffer
);
@@ -162,18 +160,17 @@ StartupAllAPsWorker (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI *CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
- Status = CpuMpPpi->StartupAllAPs (
- GetPeiServicesTablePointer (),
- CpuMpPpi,
+ Status = CpuMp2Ppi->StartupAllAPs (
+ CpuMp2Ppi,
Procedure,
FALSE,
0,
@@ -203,17 +200,7 @@ StartupAllCPUsWorker (
//
// Get MP Services2 Ppi
//
- Status = PeiServicesLocatePpi (
- &gEdkiiPeiMpServices2PpiGuid,
- 0,
- NULL,
- (VOID **)&CpuMp2Ppi
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Wakeup all APs for data collection.
- //
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
Status = CpuMp2Ppi->StartupAllCPUs (
CpuMp2Ppi,
Procedure,
@@ -234,18 +221,17 @@ SwitchNewBsp (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI *CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
- Status = CpuMpPpi->SwitchBSP (
- GetPeiServicesTablePointer (),
- CpuMpPpi,
+ Status = CpuMp2Ppi->SwitchBSP (
+ CpuMp2Ppi,
Re: [edk2-devel] [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only case.
Thanks Ray. This is good catch and it was no issue because both MpServices and
MpServices2 at the same time.
I will update INF.
Thanks,
Chasel
From: Ni, Ray
Sent: Saturday, September 12, 2020 2:37 AM
To: Dong, Eric ; Chiu, Chasel ;
devel@edk2.groups.io
Cc: Chiu, Chasel ; Laszlo Ersek ;
Kumar, Rahul1 ; Desimone, Nathaniel L
Subject: Re: [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2
only case.
A rough check in phone. Why inf file is not changed?
发件人: Dong, Eric mailto:eric.d...@intel.com>>
发送时间: Friday, September 11, 2020 10:31:32 AM
收件人: Chiu, Chasel mailto:chasel.c...@intel.com>>;
devel@edk2.groups.io<mailto:devel@edk2.groups.io>
mailto:devel@edk2.groups.io>>
抄送: Chiu, Chasel mailto:chasel.c...@intel.com>>; Ni, Ray
mailto:ray...@intel.com>>; Laszlo Ersek
mailto:ler...@redhat.com>>; Kumar, Rahul1
mailto:rahul1.ku...@intel.com>>; Desimone, Nathaniel L
mailto:nathaniel.l.desim...@intel.com>>
主题: RE: [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only
case.
Reviewed-by: Eric Dong mailto:eric.d...@intel.com>>
-Original Message-
From: Chasel Chiu mailto:chasel.c...@intel.com>>
Sent: Thursday, September 10, 2020 5:03 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>; Dong,
Eric mailto:eric.d...@intel.com>>; Ni, Ray
mailto:ray...@intel.com>>; Laszlo Ersek
mailto:ler...@redhat.com>>; Kumar, Rahul1
mailto:rahul1.ku...@intel.com>>; Desimone, Nathaniel L
mailto:nathaniel.l.desim...@intel.com>>
Subject: [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only
case.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2883
MpServices Ppi can be replaced by MpServices2 Ppi and MpServices2 Ppi is
mandatory for RegisterCpuFeaturesLib functionality, basing on this we can drop
MpServices Ppi usage from the library and the constraint that both Ppis must be
installed.
Cc: Eric Dong mailto:eric.d...@intel.com>>
Cc: Ray Ni mailto:ray...@intel.com>>
Cc: Laszlo Ersek mailto:ler...@redhat.com>>
Cc: Rahul Kumar mailto:rahul1.ku...@intel.com>>
Cc: Nate DeSimone
mailto:nathaniel.l.desim...@intel.com>>
Signed-off-by: Chasel Chiu mailto:chasel.c...@intel.com>>
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c | 61
+++--
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 6
+++---
2 files changed, 26 insertions(+), 41 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 64768f7a74..4e558e9fee 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLi
+++ b.c
@@ -1,7 +1,7 @@
/** @file
CPU Register Table Library functions.
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights
+ reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include "RegisterCpuFeatures.h"
@@ -75,10 +74,10 @@ GetMpService (
MP_SERVICESMpService;
//
- // Get MP Services Protocol
+ // Get MP Services2 Ppi
//
Status = PeiServicesLocatePpi (
- &gEfiPeiMpServicesPpiGuid,
+ &gEdkiiPeiMpServices2PpiGuid,
0,
NULL,
(VOID **)&MpService.Ppi
@@ -100,17 +99,17 @@ GetProcessorIndex (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
UINTN ProcessorIndex;
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// For two reasons which use NULL for WhoAmI:
// 1. This function will be called by APs and AP should not use PeiServices
Table
// 2. Check WhoAmI implementation, this parameter will not be used.
//
- Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, &ProcessorIndex);
+ Status = CpuMp2Ppi->WhoAmI (CpuMp2Ppi, &ProcessorIndex);
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -131,16 +130,15 @@ GetProcessorInformation (
OUT EFI_PROCESSOR_INFORMATION*ProcessorInfoBuffer
)
{
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
EFI_STATUS Status;
CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
- Status = CpuMpPpi->GetProcessorInfo (
-
[edk2-devel] [PATCH v2] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only case.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2883
MpServices Ppi can be replaced by MpServices2 Ppi and MpServices2
Ppi is mandatory for RegisterCpuFeaturesLib functionality,
basing on this we can drop MpServices Ppi usage from the library
and the constraint that both Ppis must be installed.
Cc: Eric Dong
Cc: Ray Ni
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Nate DeSimone
Signed-off-by: Chasel Chiu
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c | 61
+++--
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf | 5
++---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 6
+++---
3 files changed, 28 insertions(+), 44 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 64768f7a74..4e558e9fee 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -1,7 +1,7 @@
/** @file
CPU Register Table Library functions.
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
#include
#include "RegisterCpuFeatures.h"
@@ -75,10 +74,10 @@ GetMpService (
MP_SERVICESMpService;
//
- // Get MP Services Protocol
+ // Get MP Services2 Ppi
//
Status = PeiServicesLocatePpi (
- &gEfiPeiMpServicesPpiGuid,
+ &gEdkiiPeiMpServices2PpiGuid,
0,
NULL,
(VOID **)&MpService.Ppi
@@ -100,17 +99,17 @@ GetProcessorIndex (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
UINTN ProcessorIndex;
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// For two reasons which use NULL for WhoAmI:
// 1. This function will be called by APs and AP should not use PeiServices
Table
// 2. Check WhoAmI implementation, this parameter will not be used.
//
- Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, &ProcessorIndex);
+ Status = CpuMp2Ppi->WhoAmI (CpuMp2Ppi, &ProcessorIndex);
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -131,16 +130,15 @@ GetProcessorInformation (
OUT EFI_PROCESSOR_INFORMATION*ProcessorInfoBuffer
)
{
- EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
EFI_STATUS Status;
CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
- Status = CpuMpPpi->GetProcessorInfo (
- GetPeiServicesTablePointer(),
- CpuMpPpi,
+ Status = CpuMp2Ppi->GetProcessorInfo (
+ CpuMp2Ppi,
ProcessorNumber,
ProcessorInfoBuffer
);
@@ -162,18 +160,17 @@ StartupAllAPsWorker (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI *CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
- Status = CpuMpPpi->StartupAllAPs (
- GetPeiServicesTablePointer (),
- CpuMpPpi,
+ Status = CpuMp2Ppi->StartupAllAPs (
+ CpuMp2Ppi,
Procedure,
FALSE,
0,
@@ -203,17 +200,7 @@ StartupAllCPUsWorker (
//
// Get MP Services2 Ppi
//
- Status = PeiServicesLocatePpi (
- &gEdkiiPeiMpServices2PpiGuid,
- 0,
- NULL,
- (VOID **)&CpuMp2Ppi
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Wakeup all APs for data collection.
- //
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
Status = CpuMp2Ppi->StartupAllCPUs (
CpuMp2Ppi,
Procedure,
@@ -234,18 +221,17 @@ SwitchNewBsp (
)
{
EFI_STATUS Status;
- EFI_PEI_MP_SERVICES_PPI *CpuMpPpi;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA*CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMpPpi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
- Status = CpuMpPpi->SwitchBSP (
- GetPeiServicesTablePointer (),
- Cp
Re: [edk2-devel] [PATCH v2] UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only case.
Change pushed: 1b461403ee723dab01d5828714cca0b9396a6b3c
Thanks,
Chasel
> -Original Message-
> From: Ni, Ray
> Sent: Monday, September 14, 2020 11:46 AM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Chiu, Chasel ; Dong, Eric ;
> Laszlo Ersek ; Kumar, Rahul1
> ; Desimone, Nathaniel L
>
> Subject: RE: [PATCH v2] UefiCpuPkg/RegisterCpuFeaturesLib: Support
> MpServices2 only case.
>
> Reviewed-by: Ray Ni
>
> > -Original Message-
> > From: Chasel Chiu
> > Sent: Monday, September 14, 2020 9:48 AM
> > To: devel@edk2.groups.io
> > Cc: Chiu, Chasel ; Dong, Eric
> > ; Ni, Ray ; Laszlo Ersek
> > ; Kumar, Rahul1 ;
> Desimone,
> > Nathaniel L
> > Subject: [PATCH v2] UefiCpuPkg/RegisterCpuFeaturesLib: Support
> > MpServices2 only case.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2883
> >
> > MpServices Ppi can be replaced by MpServices2 Ppi and MpServices2 Ppi
> > is mandatory for RegisterCpuFeaturesLib functionality, basing on this
> > we can drop MpServices Ppi usage from the library and the constraint
> > that both Ppis must be installed.
> >
> > Cc: Eric Dong
> > Cc: Ray Ni
> > Cc: Laszlo Ersek
> > Cc: Rahul Kumar
> > Cc: Nate DeSimone
> > Signed-off-by: Chasel Chiu
> > ---
> > UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
> |
> > 61 +++--
> >
> > UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.in
> > f | 5
> > ++---
> > UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
> | 6
> > +++---
> > 3 files changed, 28 insertions(+), 44 deletions(-)
> >
> > diff --git
> > a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.
> > c
> > b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.
> > c
> > index 64768f7a74..4e558e9fee 100644
> > ---
> > a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.
> > c
> > +++
> > b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.
> > c
> > @@ -1,7 +1,7 @@
> > /** @file
> >CPU Register Table Library functions.
> >
> > - Copyright (c) 2016 - 2019, Intel Corporation. All rights
> > reserved.
> > + Copyright (c) 2016 - 2020, Intel Corporation. All rights
> > + reserved.
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -11,7 +11,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> >
> > #include "RegisterCpuFeatures.h"
> > @@ -75,10 +74,10 @@ GetMpService (
> >MP_SERVICESMpService;
> >
> >//
> > - // Get MP Services Protocol
> > + // Get MP Services2 Ppi
> >//
> >Status = PeiServicesLocatePpi (
> > - &gEfiPeiMpServicesPpiGuid,
> > + &gEdkiiPeiMpServices2PpiGuid,
> > 0,
> > NULL,
> > (VOID **)&MpService.Ppi
> > @@ -100,17 +99,17 @@ GetProcessorIndex (
> >)
> > {
> >EFI_STATUS Status;
> > - EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
> > + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
> >UINTN ProcessorIndex;
> >
> > - CpuMpPpi = CpuFeaturesData->MpService.Ppi;
> > + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
> >
> >//
> >// For two reasons which use NULL for WhoAmI:
> >// 1. This function will be called by APs and AP should not use
> > PeiServices Table
> >// 2. Check WhoAmI implementation, this parameter will not be used.
> >//
> > - Status = CpuMpPpi->WhoAmI(NULL, CpuMpPpi, &ProcessorIndex);
> > + Status = CpuMp2Ppi->WhoAmI (CpuMp2Ppi, &ProcessorIndex);
> >ASSERT_EFI_ERROR (Status);
> >return ProcessorIndex;
> > }
> > @@ -131,16 +130,15 @@ GetProcessorInformation (
> >OUT EFI_PROCESSOR_INFORMATION*ProcessorInfoBuffer
> >)
> > {
> > - EFI_PEI_MP_SERVICES_PPI*CpuMpPpi;
> > + EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
> >EFI_STATUS Status;
> >CPU_FEATURES_DATA *CpuFeaturesData;
> >
> >CpuFeaturesData = GetCpuFeaturesData ();
> > - CpuMpPpi = CpuFeaturesData->MpService.Ppi;
> > + CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
> >
> > - Status = CpuMpPpi->GetProcessorInfo (
> > -
Re: [edk2-devel] [PATCH 1/2] IntelFsp2WrapperPkg： remove gPeiTpmInitializationDonePpiGuid from Depex
Reviewed-by: Chasel Chiu > -Original Message- > From: Zhang, Qi1 > Sent: Tuesday, September 15, 2020 2:21 PM > To: devel@edk2.groups.io > Cc: Zhang, Qi1 ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > ; Yao, Jiewen > Subject: [PATCH 1/2] IntelFsp2WrapperPkg： remove > gPeiTpmInitializationDonePpiGuid from Depex > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2963 > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Cc: Jiewen Yao > Signed-off-by: Qi Zhang > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 3 +-- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index c3578397b6..00166e56a0 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -73,5 +73,4 @@ >gEfiPeiFirmwareVolumeInfoMeasurementExcludedPpiGuid## > PRODUCES [Depex]- gEfiPeiMasterBootModePpiGuid AND- > gPeiTpmInitializationDonePpiGuid+ gEfiPeiMasterBootModePpiGuiddiff > --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index 884514747f..aeeca58d6d 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -77,5 +77,4 @@ >FspsWrapperPeim.c [Depex]- gEfiPeiMemoryDiscoveredPpiGuid AND- > gPeiTpmInitializationDonePpiGuid+ gEfiPeiMemoryDiscoveredPpiGuid-- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65304): https://edk2.groups.io/g/devel/message/65304 Mute This Topic: https://groups.io/mt/76859554/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] IntelFsp2Pkg GenCfgOpt.py: Initialize IncLines as empty list
Reviewed-by: Chasel Chiu > -Original Message- > From: devel@edk2.groups.io On Behalf Of > gaoliming > Sent: Wednesday, September 16, 2020 5:58 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [edk2-devel] [PATCH] IntelFsp2Pkg GenCfgOpt.py: Initialize IncLines > as empty list > > IncLines as empty list for the case when InputHeaderFile is not specified. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Liming Gao > --- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py > b/IntelFsp2Pkg/Tools/GenCfgOpt.py index e9de128e..bcced590 100644 > --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py > +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py > @@ -1177,6 +1177,7 @@ EndList > UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', > 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE'] > ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', > 'FSPS_ARCH_UPD'] > > +IncLines = [] > if InputHeaderFile != '': > if not os.path.exists(InputHeaderFile): > self.Error = "Input header file '%s' does not exist" % > InputHeaderFile > -- > 2.27.0.windows.1 > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65324): https://edk2.groups.io/g/devel/message/65324 Mute This Topic: https://groups.io/mt/76884308/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] IntelFsp2Pkg/GenCfgOpt: skip unnecessarily header/BSF recreating.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2967
When no change in FSP UPD DSC files, GenCfgOpt.py should skip
recreating UPD header and BSF files.
This patch added a check to handle this case.
Cc: Maurice Ma
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/Tools/GenCfgOpt.py | 60
++--
1 file changed, 42 insertions(+), 18 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index bcced590ce..af7e14a10a 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -810,6 +810,17 @@ EndList
SubItem['value'] = valuestr
return Error
+def NoDscFileChange (self, OutPutFile):
+NoFileChange = True
+if not os.path.exists(OutPutFile):
+NoFileChange = False
+else:
+DscTime = os.path.getmtime(self._DscFile)
+OutputTime = os.path.getmtime(OutPutFile)
+if DscTime > OutputTime:
+NoFileChange = False
+return NoFileChange
+
def CreateSplitUpdTxt (self, UpdTxtFile):
GuidList =
['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID']
SignatureList = ['0x545F', '0x4D5F','0x535F']# _T, _M, and _S
signature for FSPT, FSPM, FSPS
@@ -823,16 +834,7 @@ EndList
if UpdTxtFile == '':
UpdTxtFile = os.path.join(FvDir,
self._MacroDict[GuidList[Index]] + '.txt')
-ReCreate = False
-if not os.path.exists(UpdTxtFile):
-ReCreate = True
-else:
-DscTime = os.path.getmtime(self._DscFile)
-TxtTime = os.path.getmtime(UpdTxtFile)
-if DscTime > TxtTime:
-ReCreate = True
-
-if not ReCreate:
+if (self.NoDscFileChange (UpdTxtFile)):
# DSC has not been modified yet
# So don't have to re-generate other files
self.Error = 'No DSC file change, skip to create UPD TXT file'
@@ -1056,7 +1058,11 @@ EndList
HeaderFile = os.path.join(FvDir, HeaderFileName)
# Check if header needs to be recreated
-ReCreate = False
+if (self.NoDscFileChange (HeaderFile)):
+# DSC has not been modified yet
+# So don't have to re-generate other files
+self.Error = 'No DSC file change, skip to create UPD header file'
+return 256
TxtBody = []
for Item in self._CfgItemList:
@@ -1382,6 +1388,12 @@ EndList
self.Error = "BSF output file '%s' is invalid" % BsfFile
return 1
+if (self.NoDscFileChange (BsfFile)):
+# DSC has not been modified yet
+# So don't have to re-generate other files
+self.Error = 'No DSC file change, skip to create UPD BSF file'
+return 256
+
Error = 0
OptionDict = {}
BsfFd = open(BsfFile, "w")
@@ -1467,7 +1479,7 @@ EndList
def Usage():
-print ("GenCfgOpt Version 0.55")
+print ("GenCfgOpt Version 0.56")
print ("Usage:")
print ("GenCfgOpt UPDTXT PlatformDscFile BuildFvDir
[-D Macros]")
print ("GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile
[-D Macros]")
@@ -1529,13 +1541,25 @@ def Main():
print ("ERROR: %s !" % (GenCfgOpt.Error))
return Ret
elif sys.argv[1] == "HEADER":
-if GenCfgOpt.CreateHeaderFile(OutFile) != 0:
-print ("ERROR: %s !" % GenCfgOpt.Error)
-return 8
+Ret = GenCfgOpt.CreateHeaderFile(OutFile)
+if Ret != 0:
+# No change is detected
+if Ret == 256:
+print ("INFO: %s !" % (GenCfgOpt.Error))
+else :
+print ("ERROR: %s !" % (GenCfgOpt.Error))
+return 8
+return Ret
elif sys.argv[1] == "GENBSF":
-if GenCfgOpt.GenerateBsfFile(OutFile) != 0:
-print ("ERROR: %s !" % GenCfgOpt.Error)
-return 9
+Ret = GenCfgOpt.GenerateBsfFile(OutFile)
+if Ret != 0:
+# No change is detected
+if Ret == 256:
+print ("INFO: %s !" % (GenCfgOpt.Error))
+else :
+print ("ERROR: %s !" % (GenCfgOpt.Error))
+return 9
+return Ret
else:
if argc < 5:
Usage()
--
2.28.0.windows.1
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Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/2] MinPlatformPkg: Add missing bounds checks to CompressLib
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Nate DeSimone
> Sent: Wednesday, September 30, 2020 8:15 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Liming Gao
> ; Dong, Eric
> Subject: [edk2-platforms] [PATCH V1 1/2] MinPlatformPkg: Add missing bounds
> checks to CompressLib
>
> Current code only as bounds checks in ASSERT macros.
> They are also needed in release mode where ASSERT is not used.
>
> Signed-off-by: Nate DeSimone
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Liming Gao
> Cc: Eric Dong
> ---
> .../MinPlatformPkg/Library/CompressLib/CompressLib.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/Library/CompressLib/CompressLib.c
> b/Platform/Intel/MinPlatformPkg/Library/CompressLib/CompressLib.c
> index 9f93e1ee2d..537eb3b693 100644
> --- a/Platform/Intel/MinPlatformPkg/Library/CompressLib/CompressLib.c
> +++ b/Platform/Intel/MinPlatformPkg/Library/CompressLib/CompressLib.c
> @@ -1002,7 +1002,10 @@ CountTFreq (
> mTFreq[2]++;
>}
> } else {
> - ASSERT((LoopVar3+2)<(2 * NT - 1));
> + ASSERT ((LoopVar3 + 2) < (2 * NT - 1));
> + if ((LoopVar3 + 2) >= (2 * NT - 1)) {
> +return;
> + }
>mTFreq[LoopVar3 + 2]++;
> }
>}
> @@ -1101,7 +1104,10 @@ WriteCLen (
> PutBits (CBIT, Count - 20);
>}
> } else {
> - ASSERT((LoopVar3+2) + ASSERT ((LoopVar3 + 2) < NPT);
> + if ((LoopVar3 + 2) >= NPT) {
> +return;
> + }
>PutBits (mPTLen[LoopVar3 + 2], mPTCode[LoopVar3 + 2]);
> }
>}
> --
> 2.27.0.windows.1
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