There are not only styles to be corrected. I will send a new version soon.
2014-09-20 20:41 GMT+02:00 Joel Sherrill joel.sherr...@oarcorp.com:
Style comments from me. I will let those who know who the HW comment on
that.
On September 20, 2014 1:23:26 PM CDT, tomasz.grego...@gmail.com
tomasz.grego...@gmail.com wrote:
From: Tomasz Gregorek tomasz.grego...@gmail.com
Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will slow down Flash memory for the high speeds.
---
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
.../libbsp/arm/stm32f4/include/stm32f4_flash.h | 41
.../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 94 +
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 211
+
4 files changed, 356 insertions(+)
create mode 100644
c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 59d13ef..d26f914 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -55,6 +55,16 @@
/** @} */
+/**
+ * @name STM32F4 FLASH
+ * @{
+ */
+
+#include bsp/stm32f4_flash.h
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE +
0x40023C00))
+
+/** @} */
+
#include bsp/stm32_i2c.h
/**
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
new file mode 100644
index 000..31b3992
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
@@ -0,0 +1,41 @@
+/**
+ * @file
+ * @ingroup stm32f4_flash
+ * @brief STM32F4 FLASH support.
+ */
+
+/*
+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.
+ *
+ * tomasz.grego...@gmial.com
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+
+#include bsp/utility.h
+
+/**
+ * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
+ * @ingroup stm32f4_flash
+ * @brief STM32F4FXXX FLASH Support
+ * @{
+ */
+
+typedef struct {
+ uint32_t acr;
+ uint32_t keyr;
+ uint32_t optkeyr;
+ uint32_t sr;
+ uint32_t cr;
+ uint32_t optcr;
+ uint32_t optcr1;
+} stm32f4_flash;
+
+/** @} */
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
index 8126340..ce85b8e 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
@@ -56,4 +56,98 @@ typedef struct {
/** @} */
+#define RCC_CR_HSION BSP_BIT32(0)
+#define RCC_CR_HSIRDY BSP_BIT32(1)
+#define RCC_CR_HSITRIM3
+#define RCC_CR_HSICAL 8
+#define RCC_CR_HSEON BSP_BIT32(16)
+#define RCC_CR_HSERDY BSP_BIT32(17)
+#define RCC_CR_HSEBYP BSP_BIT32(18)
+#define RCC_CR_CSSON BSP_BIT32(19)
+#define RCC_CR_PLLON BSP_BIT32(24)
+#define RCC_CR_PLLRDY BSP_BIT32(25)
+#define RCC_CR_PLLI2SON BSP_BIT32(26)
+#define RCC_CR_PLLI2SRDY BSP_BIT32(27)
+
+
+#define RCC_PLLCFGR_PLLM0
+#define RCC_PLLCFGR_PLLN6
+#define RCC_PLLCFGR_PLLP16
+
+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)
+#define RCC_PLLCFGR_PLLSRC_HSI 0
+
+#define RCC_PLLCFGR_PLLQ 24
+
+
+#define RCC_CFGR_SW 0
+#define RCC_CFGR_SW_MASK 3
+#define RCC_CFGR_SW_HSI 0
+#define RCC_CFGR_SW_HSE 1
+#define RCC_CFGR_SW_PLL 2
+
+#define RCC_CFGR_SWS 2
+#define RCC_CFGR_SWS_MASK(3 RCC_CFGR_SWS)
+
+#define RCC_CFGR_SWS_HSI 0
+#define RCC_CFGR_SWS_HSE (1 RCC_CFGR_SWS)
+#define RCC_CFGR_SWS_PLL (2 RCC_CFGR_SWS)
+
+#define RCC_CFGR_HPRE4
+#define RCC_CFGR_HPRE_BY_1 0
+#define RCC_CFGR_HPRE_BY_2 ( 8 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_4 ( 9 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_8 (10 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_16 (11 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_64 (12 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_128 (13 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_256 (14 RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_512 (15 RCC_CFGR_HPRE)
+
+#define RCC_CFGR_PPRE110
+#define RCC_CFGR_PPRE1_BY_1 0
+#define RCC_CFGR_PPRE1_BY_2 (4 RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_4 (5 RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_8 (6 RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_16 (7 RCC_CFGR_PPRE1)
+
+#define RCC_CFGR_PPRE213
+#define RCC_CFGR_PPRE2_BY_1 0
+#define RCC_CFGR_PPRE2_BY_2 (4 RCC_CFGR_PPRE2)
+#define
