Re: Mailbox RPi patch and rtems_cache_* probably broken on RPi

[Pavel Pisa]

Hello all,

I have checked how are rtems_cache_* operations implemented/linked
to the RTEMS RPi1 image and I have found that they are stubbed

   0xad94 :  bx  lr
   0xad98 : bx  lr

RTEMS has been configured as

../../../git/rtems/configure --target=arm-rtems4.12 --prefix=/opt/rtems4.12 \
  --enable-rtems-inlines --disable-multiprocessing --enable-cxx \
  --enable-rdbg --enable-maintainer-mode --enable-tests=samples \
  --disable-networking --enable-posix --disable-itron --disable-ada \
  --disable-expada --disable-multilib --disable-docs \
  --enable-rtemsbsp="raspberrypi"

This seems suspicious.

rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
  _CPU_cache_flush_data_range( d_addr, n_bytes );
#else
  const void * final_address;
...
#endif
#endif
}

and result is that CPU_DATA_CACHE_ALIGNMENT is not defined
for (my) raspberrypi build 

I see cache alignment defined in ARM case only for ARM_ARCH_5TEJ

rtems/c/src/lib/libcpu/arm/shared/include/cache_.h 

#ifdef __ARM_ARCH_5TEJ__
  #include 

  #define CPU_DATA_CACHE_ALIGNMENT 32
  #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32

and then only for Cortex-M

rtems/c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h

so that is strange and even size 32 bytes which is correct only
for subset of CPUs. RPi2 is Cortex-A7 based for example
and it includes 64 bytes length data cache lines.
But it may be better to define smaller value than
larger, because smaller leads to double line flushing
then skipping the lines. But for cache line aligned
allocation it is more disastrous to define smaller
cache line size because then cacheline aligned allocations
would lead to share of device owned area with CPU modified
data which means that data in shared line received
from device can be lost due reading/dirtying other
part from CPU. To make things safe it would worth
to define not only
  CPU_DATA_CACHE_ALIGNMENT
but even
  CPU_MAXIMAL_CACHE_ALIGNMENT
which should be used for allocation.
Or CPU_CACHE_LINE_BYTES plays this role?

If my findins are right that it has to break many things,
DMA, Ethernet controllers accessing main memory etc.

I miss in RTEMS cache manager some operation
to ensure sync of range from data cache to instruction
cache which is important for RTL support.
Such operation can be optimized to not flush
unnecessarily data from shared cache (usually L2)
when we need only to propagate them between local
CPU L1 data to all CPUs L1 code.

Best wishes,

 Pavel
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Re: [PATCH] Subject: Add original BBBIO PWM driver to BBB BSP

[punit vara]

Hi all,

In next patch I will apply changes for working code as well as will
add licence information to pwm.c file. Right now I added URL to
commit. Should I go ahead for further changes ?

Thanks,
Punit Vara

On Wed, Jun 22, 2016 at 12:26 PM, Punit Vara  wrote:
> This patch perform following things:
> - adds original BBBIO PWM code as it is.
> - not added to Makefile otherwise it will break build
> - adds required registers
> - adds declarations to BSP_HEADERS
>
> This code is added from
> 
> https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
> ---
>  c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h |  46 +++
>  c/src/lib/libbsp/arm/beagle/pwm/pwm.c | 407 
> ++
>  c/src/lib/libcpu/arm/shared/include/am335x.h  |  11 +-
>  3 files changed, 463 insertions(+), 1 deletion(-)
>  create mode 100644 c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
>  create mode 100644 c/src/lib/libbsp/arm/beagle/pwm/pwm.c
>
> diff --git a/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h 
> b/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
> new file mode 100644
> index 000..bd70385
> --- /dev/null
> +++ b/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
> @@ -0,0 +1,46 @@
> +/**
> + * @file
> + *
> + * @ingroup arm_beagle
> + *
> + * @brief BeagleBone Black BSP definitions.
> + */
> +
> +/**
> + * Copyright (c) 2016 Punit Vara 
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + */
> +
> +#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
> +#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif /* __cplusplus */
> +
> +/**
> + * @brief  BeagleBone Black PWM functions.
> + */
> +#define BBBIO_PWMSS_COUNT   3
> +#define BBBIO_PWMSS0   0
> +#define BBBIO_PWMSS1   1
> +#define BBBIO_PWMSS2   2
> +
> +/**
> + * @brief  BeagleBone Black PWM API.
> + */
> +int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float 
> dutyB);
> +int BBBIO_PWM_Init();
> +void BBBIO_PWM_Release();
> +int BBBIO_PWMSS_Status(unsigned int PWMID);
> +void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID);
> +void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID);
> +
> +#ifdef __cplusplus
> +}
> +#endif /* __cplusplus */
> +
> +#endif /* LIBBSP_ARM_BEAGLE_BBB_PWM_H */
> diff --git a/c/src/lib/libbsp/arm/beagle/pwm/pwm.c 
> b/c/src/lib/libbsp/arm/beagle/pwm/pwm.c
> new file mode 100644
> index 000..f65ff89
> --- /dev/null
> +++ b/c/src/lib/libbsp/arm/beagle/pwm/pwm.c
> @@ -0,0 +1,407 @@
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "BBBiolib.h"
> +/*---*/
> +/*
> + * PWMSS Registers
> + *
> + * @Source : AM335x Technical Reference Manual ,page 1991
> + *   Table 15-5. PWMSS REGISTERS
> + *
> +*/
> +
> +#define PWMSS0_MMAP_ADDR   0x4830
> +#define PWMSS1_MMAP_ADDR   0x48302000
> +#define PWMSS2_MMAP_ADDR   0x48304000
> +#define PWMSS_MMAP_LEN 0x1000
> +
> +#define PWMSS_IDVER0x0
> +#define PWMSS_SYSCONFIG0x4
> +#define PWMSS_CLKCONFIG0x8
> +#define PWMSS_CLKSTATUS0xC
> +
> +/* EPWM Registers
> + *
> + * @Source : AM335x Technical Reference Manual ,page 2084
> + *   Table 15-58. EPWM REGISTERS
> + *
> +*/
> +#define EPWM_TBCTL 0x0
> +#define EPWM_TBSTS 0x2
> +#define EPWM_TBPHSHR   0x4
> +#define EPWM_TBPHS 0x6
> +#define EPWM_TBCNT 0x8
> +#define EPWM_TBPRD 0xA
> +#define EPWM_CMPCTL0xE
> +#define EPWM_CMPAHR0x10
> +#define EPWM_CMPA  0x12
> +#define EPWM_CMPB  0x14
> +#define EPWM_AQCTLA0x16
> +#define EPWM_AQCTLB0x18
> +#define EPWM_AQSFRC0x1A
> +#define EPWM_AQCSFRC   0x1C
> +#define EPWM_DBCTL 0x1E
> +#define EPWM_DBRED 0x20
> +#define EPWM_DBFED 0x22
> +/*---*/
> +extern int memh;
> +extern volatile unsigned int *CM_ptr;  /*c ontrol module */
> +volatile unsigned int *cm_per_addr;
> +
> +
> +const unsigned int PWMSS_AddressOffset[]={PWMSS0_MMAP_ADDR,
> + PWMSS1_MMAP_ADDR,
> + PWMSS2_MMAP_ADDR};
> +volatile unsigned int *pwmss_ptr[3] ={NULL, NULL, NULL} ;
> +volatile unsigned int *epwm_ptr[3]  ={NULL, NULL, NULL} ;
> +volatile unsigned int *ecap_ptr[3]  ={NULL, NULL, NULL} ;
> +volatile unsigned int *eqep_ptr[3]  ={NULL, NULL, NULL} ;
> +
> +#define TBCTL_CTRMODE_UP0x0
> +#define TBCTL_CTRMODE_DOWN  0x1
> +#define TBCTL_CTRMODE_UPDOWN0x2
> +#define TBCTL_CTRMODE_FREEZE0x3
> +/* 
>