RTEMS 4.11.0 Release
RTEMS 4.11.0 Release: 4.11.0 Date : 16 November 2016 URL: https://ftp.rtems.org/pub/rtems/releases/4.11/4.11.0/ The RTEMS Project is pleased to announce the release of RTEMS 4.11.0. We would like to thank all those who have helped create this release and we would like to acknowledge and thank the patience of our users as we worked to create this release. It has taken a lot longer than we all would have liked and we now look forward to a normal release cycle. To build click on the link and follow the releases README.txt's "Quick Guide to Building" section. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] Remove sparc/sis BSP.
closes #2810.
---
c/src/lib/libbsp/sparc/erc32/clock/ckinit.c | 4 --
c/src/lib/libbsp/sparc/erc32/configure.ac| 13 --
c/src/lib/libbsp/sparc/erc32/make/custom/sis.cfg | 5 ---
c/src/lib/libbsp/sparc/erc32/timer/timer.c | 6 ---
c/src/lib/libbsp/sparc/leon2/clock/ckinit.c | 4 --
c/src/lib/libbsp/sparc/leon2/configure.ac| 6 ---
c/src/lib/libbsp/sparc/leon3/clock/ckinit.c | 4 --
c/src/lib/libbsp/sparc/leon3/configure.ac| 6 ---
c/src/lib/libbsp/sparc/shared/start/start.S | 56
9 files changed, 104 deletions(-)
delete mode 100644 c/src/lib/libbsp/sparc/erc32/make/custom/sis.cfg
diff --git a/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
index fd05a2c..21c82de 100644
--- a/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
+++ b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
@@ -28,10 +28,6 @@
#include
#include
-#if SIMSPARC_FAST_IDLE==1
-#define CLOCK_DRIVER_USE_FAST_IDLE 1
-#endif
-
/*
* The Real Time Clock Counter Timer uses this trap type.
*/
diff --git a/c/src/lib/libbsp/sparc/erc32/configure.ac
b/c/src/lib/libbsp/sparc/erc32/configure.ac
index 28c8f4b..d6dabce 100644
--- a/c/src/lib/libbsp/sparc/erc32/configure.ac
+++ b/c/src/lib/libbsp/sparc/erc32/configure.ac
@@ -30,19 +30,6 @@ of test message) and then exit. In this case, the program
returns control
to the simulator command line before the program has even queued the output
to the uart. Thus sis has no chance of getting the data out.])
-RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
-RTEMS_BSPOPTS_HELP([SIMSPARC_FAST_IDLE],
-[If defined, speed up the clock ticks while the idle task is running so
- time spent in the idle task is minimized. This significantly reduces
- the wall time required to execute the RTEMS test suites.])
-
-RTEMS_BSPOPTS_SET([ENABLE_SIS_QUIRKS],[sis],[1])
-RTEMS_BSPOPTS_SET([ENABLE_SIS_QUIRKS],[*],[0])
-RTEMS_BSPOPTS_HELP([ENABLE_SIS_QUIRKS],
-[If defined, then the SIS simulator specific code in the
- BSP will be enabled. In particular, SIS requires special
- initialization not used on real ERC32 hardware.])
-
RTEMS_BSPOPTS_SET([BSP_POWER_DOWN_AT_FATAL_HALT],[*],[])
RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT],
[If defined, CPU is spinning on fatal exit. Otherwise generate system
diff --git a/c/src/lib/libbsp/sparc/erc32/make/custom/sis.cfg
b/c/src/lib/libbsp/sparc/erc32/make/custom/sis.cfg
deleted file mode 100644
index 1f14475..000
--- a/c/src/lib/libbsp/sparc/erc32/make/custom/sis.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Configuration file for the SPARC/ERC32 Simulator SIS
-#
-
-include $(RTEMS_ROOT)/make/custom/erc32.cfg
diff --git a/c/src/lib/libbsp/sparc/erc32/timer/timer.c
b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
index 4cf638e..05728f8 100644
--- a/c/src/lib/libbsp/sparc/erc32/timer/timer.c
+++ b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
@@ -52,15 +52,9 @@ void benchmark_timer_initialize(void)
}
-#if ENABLE_SIS_QUIRKS
-#define AVG_OVERHEAD 8 /* It typically takes 3.0 microseconds */
- /* to start/stop the timer. */
-#define LEAST_VALID 9 /* Don't trust a value lower than this */
-#else
#define AVG_OVERHEAD 12 /* It typically takes 3.0 microseconds */
/* to start/stop the timer. */
#define LEAST_VALID 13 /* Don't trust a value lower than this */
-#endif
benchmark_timer_t benchmark_timer_read(void)
{
diff --git a/c/src/lib/libbsp/sparc/leon2/clock/ckinit.c
b/c/src/lib/libbsp/sparc/leon2/clock/ckinit.c
index ced5d3f..56a385e 100644
--- a/c/src/lib/libbsp/sparc/leon2/clock/ckinit.c
+++ b/c/src/lib/libbsp/sparc/leon2/clock/ckinit.c
@@ -27,10 +27,6 @@
#include
#include
-#if SIMSPARC_FAST_IDLE==1
-#define CLOCK_DRIVER_USE_FAST_IDLE 1
-#endif
-
static rtems_timecounter_simple leon2_tc;
static uint32_t leon2_tc_get( rtems_timecounter_simple *tc )
diff --git a/c/src/lib/libbsp/sparc/leon2/configure.ac
b/c/src/lib/libbsp/sparc/leon2/configure.ac
index 4f50ca7..cb92d69 100644
--- a/c/src/lib/libbsp/sparc/leon2/configure.ac
+++ b/c/src/lib/libbsp/sparc/leon2/configure.ac
@@ -30,12 +30,6 @@ of test message) and then exit. In this case, the program
returns control
to the simulator command line before the program has even queued the output
to the uart. Thus sis has no chance of getting the data out.])
-RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
-RTEMS_BSPOPTS_HELP([SIMSPARC_FAST_IDLE],
-[If defined, speed up the clock ticks while the idle task is running so
- time spent in the idle task is minimized. This significantly reduces
- the wall time required to execute the RTEMS test suites.])
-
RTEMS_BSPOPTS_SET([BSP_POWER_DOWN_AT_FATAL_HALT],[*],[])
RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT],
[If defined, CPU is spinning on fatal exit. Otherwise generate system
diff --git a/c/src/lib/libbsp/sparc/leon3/clock/ckinit.c
[PATCH 06/26] score: Move CPU_PER_CPU_CONTROL_SIZE
Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
to hide it from .
---
cpukit/score/cpu/arm/rtems/score/cpu.h | 2 --
cpukit/score/cpu/arm/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/bfin/rtems/score/cpu.h | 2 --
cpukit/score/cpu/bfin/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 1 -
cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/i386/rtems/score/cpu.h | 2 --
cpukit/score/cpu/i386/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/lm32/rtems/score/cpu.h | 2 --
cpukit/score/cpu/lm32/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/m32c/rtems/score/cpu.h | 2 --
cpukit/score/cpu/m32c/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/m68k/rtems/score/cpu.h | 2 --
cpukit/score/cpu/m68k/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/mips/rtems/score/cpu.h | 2 --
cpukit/score/cpu/mips/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/moxie/rtems/score/cpu.h| 2 --
cpukit/score/cpu/moxie/rtems/score/cpuimpl.h| 4 +++
cpukit/score/cpu/nios2/rtems/score/cpu.h| 2 --
cpukit/score/cpu/nios2/rtems/score/cpuimpl.h| 4 +++
cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 22 -
cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h | 24 +-
cpukit/score/cpu/or1k/rtems/score/cpu.h | 1 -
cpukit/score/cpu/or1k/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 2 --
cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 4 ++-
cpukit/score/cpu/sh/rtems/score/cpu.h | 2 --
cpukit/score/cpu/sh/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/sparc/rtems/score/cpu.h| 41 ---
cpukit/score/cpu/sparc/rtems/score/cpuimpl.h| 44 -
cpukit/score/cpu/sparc64/rtems/score/cpu.h | 2 --
cpukit/score/cpu/sparc64/rtems/score/cpuimpl.h | 4 +++
cpukit/score/cpu/v850/rtems/score/cpu.h | 2 --
cpukit/score/cpu/v850/rtems/score/cpuimpl.h | 4 +++
34 files changed, 125 insertions(+), 94 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 736898a..21d09a7 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -197,8 +197,6 @@
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
#define CPU_MAXIMUM_PROCESSORS 32
/** @} */
diff --git a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
index 1e9e101..75a2952 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
@@ -5,6 +5,8 @@
*/
/*
+ * Copyright (c) 2013 embedded brains GmbH
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index 30999c2..fb5198e 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -329,8 +329,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x0001
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
#define CPU_MAXIMUM_PROCESSORS 32
/*
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h
b/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h
index 6b8b601..789f2ba 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpuimpl.h
@@ -5,6 +5,8 @@
*/
/*
+ * Copyright (c) 2013 embedded brains GmbH
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 4c9d3fc..23da66b 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -671,7 +671,6 @@ void _CPU_Context_Initialize(
*/
#define CPU_SIZEOF_POINTER 4
#define CPU_EXCEPTION_FRAME_SIZE 260
-#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h
b/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h
index 6b8b601..789f2ba 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h
@@ -5,6 +5,8 @@
*/
/*
+ * Copyright (c) 2013 embedded brains GmbH
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
[PATCH 26/26] score: Robust thread dispatch
On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
---
cpukit/sapi/src/interrtext.c | 3 +-
cpukit/score/cpu/arm/rtems/score/cpu.h| 6 ++
cpukit/score/cpu/bfin/rtems/score/cpu.h | 2 +
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 2 +
cpukit/score/cpu/i386/rtems/score/cpu.h | 2 +
cpukit/score/cpu/lm32/rtems/score/cpu.h | 2 +
cpukit/score/cpu/m32c/rtems/score/cpu.h | 2 +
cpukit/score/cpu/m68k/rtems/score/cpu.h | 1 +
cpukit/score/cpu/mips/rtems/score/cpu.h | 2 +
cpukit/score/cpu/moxie/rtems/score/cpu.h | 2 +
cpukit/score/cpu/nios2/rtems/score/cpu.h | 2 +
cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 12
cpukit/score/cpu/or1k/rtems/score/cpu.h | 2 +
cpukit/score/cpu/powerpc/rtems/score/cpu.h| 2 +
cpukit/score/cpu/sh/rtems/score/cpu.h | 2 +
cpukit/score/cpu/sparc/rtems/score/cpu.h | 2 +
cpukit/score/cpu/sparc64/rtems/score/cpu.h| 2 +
cpukit/score/cpu/v850/rtems/score/cpu.h | 2 +
cpukit/score/include/rtems/score/interr.h | 3 +-
cpukit/score/include/rtems/score/threaddispatch.h | 19 ++-
cpukit/score/src/threaddispatch.c | 15 +
testsuites/smptests/Makefile.am | 1 +
testsuites/smptests/configure.ac | 1 +
testsuites/smptests/smpfatal06/Makefile.am| 19 +++
testsuites/smptests/smpfatal06/init.c | 69 +++
testsuites/smptests/smpfatal06/smpfatal06.doc | 13 +
testsuites/smptests/smpfatal06/smpfatal06.scn | 2 +
testsuites/sptests/spinternalerror02/init.c | 2 +-
28 files changed, 190 insertions(+), 4 deletions(-)
create mode 100644 testsuites/smptests/smpfatal06/Makefile.am
create mode 100644 testsuites/smptests/smpfatal06/init.c
create mode 100644 testsuites/smptests/smpfatal06/smpfatal06.doc
create mode 100644 testsuites/smptests/smpfatal06/smpfatal06.scn
diff --git a/cpukit/sapi/src/interrtext.c b/cpukit/sapi/src/interrtext.c
index edf09db..ce69461 100644
--- a/cpukit/sapi/src/interrtext.c
+++ b/cpukit/sapi/src/interrtext.c
@@ -57,7 +57,8 @@ static const char *const internal_error_text[] = {
"INTERNAL_ERROR_POSIX_INIT_THREAD_ENTRY_IS_NULL",
"INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK",
"INTERNAL_ERROR_THREAD_QUEUE_ENQUEUE_STICKY_FROM_BAD_STATE",
- "INTERNAL_ERROR_BAD_THREAD_DISPATCH_DISABLE_LEVEL"
+ "INTERNAL_ERROR_BAD_THREAD_DISPATCH_DISABLE_LEVEL",
+ "INTERNAL_ERROR_BAD_THREAD_DISPATCH_ENVIRONMENT"
};
const char *rtems_internal_error_text( rtems_fatal_code error )
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 6a57ac8..0cadc81 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -130,6 +130,12 @@
#define CPU_USE_DEFERRED_FP_SWITCH FALSE
+#if defined(ARM_MULTILIB_ARCH_V7M)
+ #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
+#else
+ #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
+#endif
+
#if defined(ARM_MULTILIB_HAS_WFI)
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
#else
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index 85dbf78..046bd50 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -233,6 +233,8 @@ extern "C" {
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
+#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
+
/**
* Does this port provide a CPU dependent IDLE task implementation?
*
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 871f30e..4319203 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -205,6 +205,8 @@ extern "C" {
#define CPU_USE_DEFERRED_FP_SWITCH FALSE
+#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
+
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h
b/cpukit/score/cpu/i386/rtems/score/cpu.h
index f70e2c6..c45d914 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -92,6 +92,8 @@ extern "C" {
#endif
#endif /* __SSE__ */
+#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
+
#define CPU_STACK_GROWS_UP FALSE
/* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h
b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index ed397dc..e6f6c51
[PATCH 17/26] score: Add Per_CPU_Control::Interrupt_frame
Update #2809.
---
cpukit/score/cpu/sparc/cpu.c | 5 -
cpukit/score/include/rtems/score/percpu.h | 28 +---
cpukit/score/src/percpuasm.c | 14 +-
3 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 92d1c66..4aa30db 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -110,11 +110,6 @@ RTEMS_STATIC_ASSERT(
SPARC_MINIMUM_STACK_FRAME_SIZE
);
-RTEMS_STATIC_ASSERT(
- sizeof(CPU_Interrupt_frame) == CPU_INTERRUPT_FRAME_SIZE,
- CPU_Interrupt_frame_size
-);
-
/* https://devel.rtems.org/ticket/2352 */
RTEMS_STATIC_ASSERT(
sizeof(CPU_Interrupt_frame) % CPU_ALIGNMENT == 0,
diff --git a/cpukit/score/include/rtems/score/percpu.h
b/cpukit/score/include/rtems/score/percpu.h
index d2025c0..39190e9 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -9,6 +9,8 @@
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
+ * Copyright (c) 2012, 2016 embedded brains GmbH
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -35,16 +37,28 @@
extern "C" {
#endif
-#if defined( RTEMS_SMP )
+#if defined(RTEMS_SMP)
+ #if defined(RTEMS_PROFILING)
+#define PER_CPU_CONTROL_SIZE_APPROX ( 512 + CPU_INTERRUPT_FRAME_SIZE )
+ #elif defined(RTEMS_DEBUG)
+#define PER_CPU_CONTROL_SIZE_APPROX ( 256 + CPU_INTERRUPT_FRAME_SIZE )
+ #else
+#define PER_CPU_CONTROL_SIZE_APPROX ( 128 + CPU_INTERRUPT_FRAME_SIZE )
+ #endif
+
/*
* This ensures that on SMP configurations the individual per-CPU controls
* are on different cache lines to prevent false sharing. This define can be
* used in assembler code to easily get the per-CPU control for a particular
* processor.
*/
- #if defined( RTEMS_PROFILING )
+ #if PER_CPU_CONTROL_SIZE_APPROX > 1024
+#define PER_CPU_CONTROL_SIZE_LOG2 11
+ #elif PER_CPU_CONTROL_SIZE_APPROX > 512
+#define PER_CPU_CONTROL_SIZE_LOG2 10
+ #elif PER_CPU_CONTROL_SIZE_APPROX > 256
#define PER_CPU_CONTROL_SIZE_LOG2 9
- #elif defined( RTEMS_DEBUG )
+ #elif PER_CPU_CONTROL_SIZE_APPROX > 128
#define PER_CPU_CONTROL_SIZE_LOG2 8
#else
#define PER_CPU_CONTROL_SIZE_LOG2 7
@@ -348,6 +362,10 @@ typedef struct Per_CPU_Control {
*/
volatile bool dispatch_necessary;
+#if defined(RTEMS_SMP)
+ CPU_Interrupt_frame Interrupt_frame;
+#endif
+
/**
* @brief The CPU usage timestamp contains the time point of the last heir
* thread change or last CPU usage update of the executing thread of this
@@ -800,6 +818,10 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control
*_Thread_Get_executing( void )
PER_CPU_OFFSET_EXECUTING + CPU_SIZEOF_POINTER
#define PER_CPU_DISPATCH_NEEDED \
PER_CPU_OFFSET_HEIR + CPU_SIZEOF_POINTER
+#if defined(RTEMS_SMP)
+#define PER_CPU_INTERRUPT_FRAME_AREA \
+ PER_CPU_DISPATCH_NEEDED + 4
+#endif
#define THREAD_DISPATCH_DISABLE_LEVEL \
(SYM(_Per_CPU_Information) + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)
diff --git a/cpukit/score/src/percpuasm.c b/cpukit/score/src/percpuasm.c
index 29bdb13..2908643 100644
--- a/cpukit/score/src/percpuasm.c
+++ b/cpukit/score/src/percpuasm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012, 2016 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -110,6 +110,18 @@ RTEMS_STATIC_ASSERT(
PER_CPU_DISPATCH_NEEDED
);
+#if defined(RTEMS_SMP)
+RTEMS_STATIC_ASSERT(
+ offsetof(Per_CPU_Control, Interrupt_frame) == PER_CPU_INTERRUPT_FRAME_AREA,
+ PER_CPU_INTERRUPT_FRAME_AREA
+);
+
+RTEMS_STATIC_ASSERT(
+ sizeof( CPU_Interrupt_frame ) == CPU_INTERRUPT_FRAME_SIZE,
+ CPU_INTERRUPT_FRAME_SIZE
+);
+#endif
+
#if CPU_ALLOCATE_INTERRUPT_STACK == TRUE \
|| CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE
RTEMS_STATIC_ASSERT(
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 14/26] powerpc: Add up to date CPU_Interrupt_frame
Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to . Update #2809. --- .../powerpc/mpc55xxevb/startup/exc-vector-base.S | 6 +- c/src/lib/libbsp/powerpc/qoriq/start/start.S | 6 +- c/src/lib/libbsp/powerpc/t32mppc/start/start.S | 6 +- .../bspsupport/ppc_exc_async_normal.S | 6 +- .../new-exceptions/bspsupport/ppc_exc_initialize.c | 216 .../powerpc/new-exceptions/bspsupport/vectors.h| 161 +-- cpukit/score/cpu/powerpc/cpu.c | 227 - cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 165 ++- 8 files changed, 399 insertions(+), 394 deletions(-) diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S index b9f0f44..c8103e7 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S @@ -58,7 +58,7 @@ mpc55xx_exc_vector_base: stw r4, GPR4_OFFSET(r1) li r4, 4 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32763 @@ -88,7 +88,7 @@ mpc55xx_exc_vector_base: stw r4, GPR4_OFFSET(r1) li r4, 24 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32752 @@ -98,7 +98,7 @@ mpc55xx_exc_vector_base: nop nop #endif - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32749 diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S index 1418128..6f6771d 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S @@ -344,7 +344,7 @@ bsp_exc_vector_base: stw r4, GPR4_OFFSET(r1) li r4, 4 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32763 @@ -375,7 +375,7 @@ system_call: stw r4, GPR4_OFFSET(r1) li r4, 24 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32752 @@ -385,7 +385,7 @@ system_call: nop nop #endif - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32749 diff --git a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S index 380c019..34e1cfac 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S +++ b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S @@ -109,7 +109,7 @@ bsp_exc_vector_base: stw r4, GPR4_OFFSET(r1) li r4, 4 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32763 b ppc_exc_wrap_async_normal @@ -133,11 +133,11 @@ bsp_exc_vector_base: stw r4, GPR4_OFFSET(r1) li r4, 24 b ppc_exc_wrap_nopush_std - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32752 b ppc_exc_wrap_async_normal - stwur1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1) + stwur1, -CPU_INTERRUPT_FRAME_SIZE(r1) stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) li r4, -32749 b ppc_exc_wrap_async_normal diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 0e71dad..c6cbdce 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -48,7 +48,7 @@ #ifdef RTEMS_PROFILING /* - * The PPC_EXC_MINIMAL_FRAME_SIZE is enough to store this additional
[PATCH 15/26] arm: Provide CPU_Interrupt_frame for ARMv4
Update #2809.
---
cpukit/score/cpu/arm/rtems/score/cpu.h | 2 --
cpukit/score/cpu/arm/rtems/score/cpuimpl.h | 56 +-
2 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index e4f9e37..326abbb 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -687,8 +687,6 @@ typedef struct {
uint32_t reserved_for_stack_alignment;
} CPU_Exception_frame;
-typedef CPU_Exception_frame CPU_Interrupt_frame;
-
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
void _ARM_Exception_default( CPU_Exception_frame *frame );
diff --git a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
index 75a2952..0885c2e 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013, 2016 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -19,6 +19,18 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#ifdef ARM_MULTILIB_ARCH_V4
+
+#if defined(ARM_MULTILIB_VFP_D32)
+#define CPU_INTERRUPT_FRAME_SIZE 240
+#elif defined(ARM_MULTILIB_VFP)
+#define CPU_INTERRUPT_FRAME_SIZE 112
+#else
+#define CPU_INTERRUPT_FRAME_SIZE 40
+#endif
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
#ifndef ASM
#ifdef __cplusplus
@@ -27,6 +39,48 @@ extern "C" {
#ifdef ARM_MULTILIB_ARCH_V4
+typedef struct {
+#ifdef ARM_MULTILIB_VFP
+ uint32_t fpscr;
+#ifdef ARM_MULTILIB_VFP_D32
+ double d16;
+ double d17;
+ double d18;
+ double d19;
+ double d20;
+ double d21;
+ double d22;
+ double d23;
+ double d24;
+ double d25;
+ double d26;
+ double d27;
+ double d28;
+ double d29;
+ double d30;
+ double d31;
+#endif /* ARM_MULTILIB_VFP_D32 */
+ double d0;
+ double d1;
+ double d2;
+ double d3;
+ double d4;
+ double d5;
+ double d6;
+ double d7;
+#endif /* ARM_MULTILIB_VFP */
+ uint32_t r9;
+ uint32_t lr;
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t return_pc;
+ uint32_t return_cpsr;
+ uint32_t r7;
+ uint32_t r12;
+} CPU_Interrupt_frame;
+
#ifdef RTEMS_SMP
static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void )
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 19/26] sparc: Use Per_CPU_Control::isr_dispatch_disable
Update #2751.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S | 10 +-
cpukit/score/cpu/sparc/cpu.c | 6 --
cpukit/score/cpu/sparc/rtems/score/cpuimpl.h | 21 +
3 files changed, 10 insertions(+), 27 deletions(-)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index a842a62..fc89932 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -74,7 +74,7 @@ SYM(_CPU_Context_switch):
std %o6, [%o0 + O6_SP_OFFSET]! save the output registers
! load the ISR stack nesting prevention flag
-ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %o4
+ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
! save it a bit later so we do not waste a couple of cycles
rd %psr, %o2
@@ -217,7 +217,7 @@ done_flushing:
ldd [%o1 + L6_OFFSET], %l6
! Now restore thread specific ISR dispatch prevention flag
-st %o2, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
ldd [%o1 + I0_OFFSET], %i0! restore the input registers
ldd [%o1 + I2_OFFSET], %i2
@@ -594,7 +594,7 @@ profiling_not_outer_most_exit:
nop
! Are we dispatching from a previous ISR in the interrupted thread?
-ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %l7
+ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %l7
orcc %l7, %g0, %g0 ! Is this thread already doing an ISR?
bnz simple_return ! Yes, then do a "simple" exit
nop
@@ -617,7 +617,7 @@ profiling_not_outer_most_exit:
! Set ISR dispatch nesting prevention flag
mov 1,%l6
-st %l6, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
/*
* The following subtract should get us back on the interrupted
@@ -726,7 +726,7 @@ thread_dispatch_done:
! No, then clear out and return
! Zero out ISR stack nesting prevention flag
-st %g0, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
/*
* The CWP in place at this point may be different from
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 4aa30db..a640849 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -23,12 +23,6 @@
#include
#include
-RTEMS_STATIC_ASSERT(
- offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable)
-== SPARC_PER_CPU_ISR_DISPATCH_DISABLE,
- SPARC_PER_CPU_ISR_DISPATCH_DISABLE
-);
-
#if SPARC_HAS_FPU == 1
RTEMS_STATIC_ASSERT(
offsetof( Per_CPU_Control, cpu_per_cpu.fsr)
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
index 51071ab..5563db8 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
@@ -70,21 +70,15 @@
#if ( SPARC_HAS_FPU == 1 )
#define CPU_PER_CPU_CONTROL_SIZE 8
#else
- #define CPU_PER_CPU_CONTROL_SIZE 4
+ #define CPU_PER_CPU_CONTROL_SIZE 0
#endif
-/**
- * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
- * relative to the Per_CPU_Control begin.
- */
-#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
-
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
* Per_CPU_Control begin.
*/
- #define SPARC_PER_CPU_FSR_OFFSET 4
+ #define SPARC_PER_CPU_FSR_OFFSET 0
#endif
#ifndef ASM
@@ -94,14 +88,6 @@ extern "C" {
#endif
typedef struct {
- /**
- * This flag is context switched with each thread. It indicates
- * that THIS thread has an _ISR_Dispatch stack frame on its stack.
- * By using this flag, we can avoid nesting more interrupt dispatching
- * attempts on a previously interrupted thread's stack.
- */
- uint32_t isr_dispatch_disable;
-
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Memory location to store the FSR register during interrupt
@@ -111,6 +97,9 @@ typedef struct {
* floating point operations in progress.
*/
uint32_t fsr;
+
+ /* See Per_CPU_Control::Interrupt_frame */
+ uint32_t reserved_for_alignment_of_interrupt_frame;
#endif
} CPU_Per_CPU_control;
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 22/26] arm: Use Per_CPU_Control::isr_dispatch_disable
Update #2751.
---
cpukit/score/cpu/arm/arm_exc_interrupt.S | 85 ++--
cpukit/score/cpu/arm/cpu.c | 10 +++-
cpukit/score/cpu/arm/cpu_asm.S | 13 -
cpukit/score/cpu/arm/rtems/score/cpu.h | 17 +--
4 files changed, 94 insertions(+), 31 deletions(-)
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S
b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index de5a022..fc02c91 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -43,7 +43,7 @@
#define EXCHANGE_SIZE 16
#define SELF_CPU_CONTROL r7
-#define SP_OF_INTERRUPTED_CONTEXT r9
+#define NON_VOLATILE_SCRATCH r9
#define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR,
SELF_CPU_CONTROL, r12}
#define CONTEXT_SIZE 32
@@ -73,7 +73,7 @@ _ARMV4_Exception_interrupt:
* interrupted context.
*/
stmdb sp!, CONTEXT_LIST
- stmdb sp!, {SP_OF_INTERRUPTED_CONTEXT, lr}
+ stmdb sp!, {NON_VOLATILE_SCRATCH, lr}
#ifdef ARM_MULTILIB_VFP
/* Save VFP context */
@@ -98,7 +98,7 @@ _ARMV4_Exception_interrupt:
ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
/* Switch stack if necessary and save original stack pointer */
- mov SP_OF_INTERRUPTED_CONTEXT, sp
+ mov NON_VOLATILE_SCRATCH, sp
cmp r2, #0
moveq sp, r1
@@ -130,33 +130,68 @@ _ARMV4_Exception_interrupt:
bl bsp_interrupt_dispatch
#endif
- /* Decrement interrupt nest and thread dispatch disable level */
- ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
- ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
- sub r2, #1
- sub r3, #1
- str r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
- str r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+ /* Load some per-CPU variables */
+ ldr r0, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+ ldrbr1, [SELF_CPU_CONTROL, #PER_CPU_DISPATCH_NEEDED]
+ ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_DISPATCH_DISABLE]
+ ldr r3, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
/* Restore stack pointer */
- mov sp, SP_OF_INTERRUPTED_CONTEXT
+ mov sp, NON_VOLATILE_SCRATCH
- /* Check thread dispatch disable level */
- cmp r3, #0
- bne .Lthread_dispatch_done
+ /* Save CPSR in non-volatile register */
+ mrs NON_VOLATILE_SCRATCH, CPSR
- /* Check context switch necessary */
- ldrbr1, [SELF_CPU_CONTROL, #PER_CPU_DISPATCH_NEEDED]
- cmp r1, #0
- beq .Lthread_dispatch_done
+ /* Decrement levels and determine thread dispatch state */
+ eor r1, r0
+ sub r0, #1
+ orr r1, r0
+ orr r1, r2
+ sub r3, #1
-/* This aligns .Lthread_dispatch_done on a 4 byte boundary */
-#ifdef __thumb__
- nop
-#endif /* __thumb__ */
+ /* Store thread dispatch disable and ISR nest levels */
+ str r0, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+ str r3, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
+
+ /*
+* Check thread dispatch necessary, ISR dispatch disable and thread
+* dispatch disable level.
+*/
+ cmp r0, #0
+ bne .Lthread_dispatch_done
/* Thread dispatch */
- bl _Thread_Dispatch
+ mrs NON_VOLATILE_SCRATCH, CPSR
+
+.Ldo_thread_dispatch:
+
+ /* Set ISR dispatch disable and thread dispatch disable level to one */
+ mov r0, #1
+ str r0, [SELF_CPU_CONTROL, #PER_CPU_ISR_DISPATCH_DISABLE]
+ str r0, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+
+ /* Call _Thread_Do_dispatch(), this function will enable interrupts */
+ mov r0, SELF_CPU_CONTROL
+ mov r1, NON_VOLATILE_SCRATCH
+ mov r2, #0x80
+ bic r1, r2
+ bl _Thread_Do_dispatch
+
+ /* Disable interrupts */
+ msr CPSR, NON_VOLATILE_SCRATCH
+
+#ifdef RTEMS_SMP
+ GET_SELF_CPU_CONTROLSELF_CPU_CONTROL
+#endif
+
+ /* Check if we have to do the thread dispatch again */
+ ldrbr0, [SELF_CPU_CONTROL, #PER_CPU_DISPATCH_NEEDED]
+ cmp r0, #0
+ bne .Ldo_thread_dispatch
+
+ /* We are done with thread dispatching */
+ mov r0, #0
+ str r0, [SELF_CPU_CONTROL, #PER_CPU_ISR_DISPATCH_DISABLE]
.Lthread_dispatch_done:
@@ -173,8 +208,8 @@ _ARMV4_Exception_interrupt:
vmsrFPSCR, r0
#endif /* ARM_MULTILIB_VFP */
- /* Restore SP_OF_INTERRUPTED_CONTEXT register and link register */
- ldmia sp!, {SP_OF_INTERRUPTED_CONTEXT, lr}
+ /* Restore NON_VOLATILE_SCRATCH register and link register */
+ ldmia sp!, {NON_VOLATILE_SCRATCH, lr}
/*
* XXX: Remember and restore
[PATCH 24/26] score: Restrict task interrupt level to 0 on SMP
Update #2811.
---
cpukit/score/src/threadinitialize.c | 10 --
testsuites/smptests/smpunsupported01/init.c | 18 +-
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/cpukit/score/src/threadinitialize.c
b/cpukit/score/src/threadinitialize.c
index 2cbe138..9ae2acb 100644
--- a/cpukit/score/src/threadinitialize.c
+++ b/cpukit/score/src/threadinitialize.c
@@ -60,8 +60,14 @@ bool _Thread_Initialize(
Per_CPU_Control *cpu = _Per_CPU_Get_by_index( 0 );
#if defined( RTEMS_SMP )
- if ( rtems_configuration_is_smp_enabled() && !is_preemptible ) {
-return false;
+ if ( rtems_configuration_is_smp_enabled() ) {
+if ( !is_preemptible ) {
+ return false;
+}
+
+if ( isr_level != 0 ) {
+ return false;
+}
}
#endif
diff --git a/testsuites/smptests/smpunsupported01/init.c
b/testsuites/smptests/smpunsupported01/init.c
index 9d69b6b..52c3181 100644
--- a/testsuites/smptests/smpunsupported01/init.c
+++ b/testsuites/smptests/smpunsupported01/init.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2014 On-Line Applications Research Corporation (OAR).
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013, 2016 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -41,6 +41,22 @@ static void test(void)
);
rtems_test_assert(sc == RTEMS_UNSATISFIED);
+
+ mode = RTEMS_INTERRUPT_LEVEL(1);
+
+ if (mode != 0) {
+sc = rtems_task_create(
+ rtems_build_name('T', 'A', 'S', 'K'),
+ RTEMS_MINIMUM_PRIORITY,
+ RTEMS_MINIMUM_STACK_SIZE,
+ mode,
+ RTEMS_DEFAULT_ATTRIBUTES,
+
+);
+rtems_test_assert(sc == RTEMS_UNSATISFIED);
+ } else {
+puts("RTEMS_INTERRUPT_LEVEL(1) not supported on this platform");
+ }
}
static void Init(rtems_task_argument arg)
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 16/26] score: Add Per_CPU_Control::isr_dispatch_disable
Update #2751.
---
cpukit/score/include/rtems/score/percpu.h | 14 +-
cpukit/score/src/percpuasm.c | 6 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/cpukit/score/include/rtems/score/percpu.h
b/cpukit/score/include/rtems/score/percpu.h
index ae789b8..d2025c0 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -290,6 +290,16 @@ typedef struct Per_CPU_Control {
uint32_t isr_nest_level;
/**
+ * @brief Indicetes if an ISR thread dispatch is disabled.
+ *
+ * This flag is context switched with each thread. It indicates that this
+ * thread has an interrupt stack frame on its stack. By using this flag, we
+ * can avoid nesting more interrupt dispatching attempts on a previously
+ * interrupted thread's stack.
+ */
+ uint32_t isr_dispatch_disable;
+
+ /**
* @brief The thread dispatch critical section nesting counter which is used
* to prevent context switches at inopportune moments.
*/
@@ -780,8 +790,10 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control
*_Thread_Get_executing( void )
*/
#define PER_CPU_ISR_NEST_LEVEL \
PER_CPU_END_STACK
-#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \
+#define PER_CPU_ISR_DISPATCH_DISABLE \
PER_CPU_ISR_NEST_LEVEL + 4
+#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \
+ PER_CPU_ISR_DISPATCH_DISABLE + 4
#define PER_CPU_OFFSET_EXECUTING \
PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL + 4
#define PER_CPU_OFFSET_HEIR \
diff --git a/cpukit/score/src/percpuasm.c b/cpukit/score/src/percpuasm.c
index 53e6326..29bdb13 100644
--- a/cpukit/score/src/percpuasm.c
+++ b/cpukit/score/src/percpuasm.c
@@ -84,6 +84,12 @@ RTEMS_STATIC_ASSERT(
);
RTEMS_STATIC_ASSERT(
+ offsetof(Per_CPU_Control, isr_dispatch_disable)
+== PER_CPU_ISR_DISPATCH_DISABLE,
+ PER_CPU_ISR_DISPATCH_DISABLE
+);
+
+RTEMS_STATIC_ASSERT(
offsetof(Per_CPU_Control, thread_dispatch_disable_level)
== PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL,
PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 02/26] sptests/sp37: Better cope with internal padding
---
testsuites/sptests/sp37/init.c | 65 ++
1 file changed, 40 insertions(+), 25 deletions(-)
diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c
index 68b28a6..e87ad9f 100644
--- a/testsuites/sptests/sp37/init.c
+++ b/testsuites/sptests/sp37/init.c
@@ -159,29 +159,33 @@ static void test_isr_level( void )
test_isr_level_for_new_threads( last_proper_level );
}
-#if defined(RTEMS_SMP) && defined(RTEMS_PROFILING)
-static const size_t lock_size =
- offsetof( ISR_lock_Control, Lock.Stats.name )
-+ sizeof( ((ISR_lock_Control *) 0)->Lock.Stats.name );
-#else
-static const size_t lock_size = sizeof( ISR_lock_Control );
-#endif
-
static void test_isr_locks( void )
{
ISR_Level normal_interrupt_level = _ISR_Get_level();
ISR_lock_Control initialized = ISR_LOCK_INITIALIZER("test");
- ISR_lock_Control lock;
+ union {
+ISR_lock_Control lock;
+uint8_t bytes[ sizeof( ISR_lock_Control ) ];
+ } container;
ISR_lock_Context lock_context;
+ size_t i;
+ const uint8_t *initialized_bytes;
- _ISR_lock_Initialize( , "test" );
- rtems_test_assert( memcmp( , , lock_size ) == 0 );
+ memset( , 0xff, sizeof( container ) );
+ _ISR_lock_Initialize( , "test" );
+ initialized_bytes = (const uint8_t *)
+
+ for ( i = 0; i < sizeof( container ); ++i ) {
+if ( container.bytes[ i ] != 0xff ) {
+ rtems_test_assert( container.bytes[ i ] == initialized_bytes[ i] );
+}
+ }
- _ISR_lock_ISR_disable_and_acquire( , _context );
+ _ISR_lock_ISR_disable_and_acquire( , _context );
rtems_test_assert( normal_interrupt_level != _ISR_Get_level() );
- _ISR_lock_Flash( , _context );
+ _ISR_lock_Flash( , _context );
rtems_test_assert( normal_interrupt_level != _ISR_Get_level() );
- _ISR_lock_Release_and_ISR_enable( , _context );
+ _ISR_lock_Release_and_ISR_enable( , _context );
rtems_test_assert( normal_interrupt_level == _ISR_Get_level() );
@@ -191,13 +195,13 @@ static void test_isr_locks( void )
rtems_test_assert( normal_interrupt_level == _ISR_Get_level() );
- _ISR_lock_Acquire( , _context );
+ _ISR_lock_Acquire( , _context );
rtems_test_assert( normal_interrupt_level == _ISR_Get_level() );
- _ISR_lock_Release( , _context );
+ _ISR_lock_Release( , _context );
rtems_test_assert( normal_interrupt_level == _ISR_Get_level() );
- _ISR_lock_Destroy( );
+ _ISR_lock_Destroy( );
_ISR_lock_Destroy( );
}
@@ -216,25 +220,36 @@ static void test_interrupt_locks( void )
{
rtems_mode normal_interrupt_level = get_interrupt_level();
rtems_interrupt_lock initialized = RTEMS_INTERRUPT_LOCK_INITIALIZER("test");
- rtems_interrupt_lock lock;
+ union {
+rtems_interrupt_lock lock;
+uint8_t bytes[ sizeof( rtems_interrupt_lock ) ];
+ } container;
rtems_interrupt_lock_context lock_context;
+ size_t i;
+ const uint8_t *initialized_bytes;
+
+ rtems_interrupt_lock_initialize( , "test" );
+ initialized_bytes = (const uint8_t *)
- rtems_interrupt_lock_initialize( , "test" );
- rtems_test_assert( memcmp( , , lock_size ) == 0 );
+ for ( i = 0; i < sizeof( container ); ++i ) {
+if ( container.bytes[ i ] != 0xff ) {
+ rtems_test_assert( container.bytes[ i ] == initialized_bytes[ i] );
+}
+ }
- rtems_interrupt_lock_acquire( , _context );
+ rtems_interrupt_lock_acquire( , _context );
rtems_test_assert( normal_interrupt_level != get_interrupt_level() );
- rtems_interrupt_lock_release( , _context );
+ rtems_interrupt_lock_release( , _context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
- rtems_interrupt_lock_acquire_isr( , _context );
+ rtems_interrupt_lock_acquire_isr( , _context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
- rtems_interrupt_lock_release_isr( , _context );
+ rtems_interrupt_lock_release_isr( , _context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
- rtems_interrupt_lock_destroy( );
+ rtems_interrupt_lock_destroy( );
rtems_interrupt_lock_destroy( );
}
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 04/26] score: Remove obsolete defines
The thread dispatch inline option is no longer used.
---
cpukit/score/cpu/arm/rtems/score/cpu.h| 7 ---
cpukit/score/cpu/bfin/rtems/score/cpu.h | 23 --
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 20 ---
cpukit/score/cpu/i386/rtems/score/cpu.h | 2 --
cpukit/score/cpu/lm32/rtems/score/cpu.h | 23 --
cpukit/score/cpu/m32c/rtems/score/cpu.h | 23 --
cpukit/score/cpu/m68k/rtems/score/cpu.h | 2 --
cpukit/score/cpu/mips/rtems/score/cpu.h | 19 --
cpukit/score/cpu/moxie/rtems/score/cpu.h | 22 -
cpukit/score/cpu/nios2/rtems/score/cpu.h | 5 -
cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 23 --
cpukit/score/cpu/or1k/rtems/score/cpu.h | 20 ---
cpukit/score/cpu/powerpc/rtems/score/cpu.h| 19 --
cpukit/score/cpu/sh/rtems/score/cpu.h | 19 --
cpukit/score/cpu/sparc/rtems/score/cpu.h | 10 --
cpukit/score/cpu/sparc64/rtems/score/cpu.h| 9 -
cpukit/score/cpu/v850/rtems/score/cpu.h | 24 ---
cpukit/score/include/rtems/score/threaddispatch.h | 11 ---
18 files changed, 281 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 4cdca73..736898a 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -97,13 +97,6 @@
*/
/**@{**/
-/* If someone uses THUMB we assume she wants minimal code size */
-#ifdef __thumb__
- #define CPU_INLINE_ENABLE_DISPATCH FALSE
-#else
- #define CPU_INLINE_ENABLE_DISPATCH TRUE
-#endif
-
#if defined(__ARMEL__)
#define CPU_BIG_ENDIAN FALSE
#define CPU_LITTLE_ENDIAN TRUE
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index 1437277..30999c2 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -31,29 +31,6 @@ extern "C" {
/* conditional compilation parameters */
/**
- * Should the calls to @ref _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * This conditional is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- *
- * @note In general, the @ref _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls @ref _Thread_Enable_dispatch which in turns calls
- * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-
-/**
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 2954628..4c9d3fc 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -50,26 +50,6 @@ extern "C" {
/* conditional compilation parameters */
/*
- * Should the calls to _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * Basically this is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- * [NOTE: In general, the _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls _Thread_Enable_dispatch which in turns calls
- * _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.]
- *
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-
-/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _ISR_Handler_initialization.
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h
b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 8fc62ca..127c12c 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -32,8 +32,6 @@ extern "C" {
/* conditional compilation parameters */
-#define CPU_INLINE_ENABLE_DISPATCH TRUE
-
/*
* Does the CPU follow the simple vectored interrupt model?
*
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h
[PATCH 25/26] score: Add _ISR_Is_enabled()
In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
---
cpukit/score/cpu/arm/rtems/score/cpu.h | 11 +--
cpukit/score/cpu/bfin/rtems/score/cpu.h | 5 +
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 5 +
cpukit/score/cpu/i386/rtems/score/cpu.h | 5 +
cpukit/score/cpu/lm32/rtems/score/cpu.h | 5 +
cpukit/score/cpu/m32c/rtems/score/cpu.h | 5 +
cpukit/score/cpu/m68k/rtems/score/cpu.h | 5 +
cpukit/score/cpu/mips/rtems/score/cpu.h | 5 +
cpukit/score/cpu/moxie/rtems/score/cpu.h | 5 +
cpukit/score/cpu/nios2/nios2-isr-get-level.c | 12
cpukit/score/cpu/nios2/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/no_cpu/rtems/score/cpu.h| 14 ++
cpukit/score/cpu/or1k/rtems/score/cpu.h | 5 +
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 5 +
cpukit/score/cpu/sh/rtems/score/cpu.h| 6 ++
cpukit/score/cpu/sparc/rtems/score/cpu.h | 8
cpukit/score/cpu/sparc64/rtems/score/cpu.h | 5 +
cpukit/score/cpu/v850/rtems/score/cpu.h | 6 ++
cpukit/score/include/rtems/score/isrlevel.h | 12
testsuites/sptests/sp37/init.c | 2 ++
20 files changed, 126 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index b1fabaf..6a57ac8 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -350,8 +350,6 @@ static inline uint32_t arm_interrupt_disable( void )
: [level] "=" (level)
: [basepri] "r" (basepri)
);
-#else
- level = 0;
#endif
return level;
@@ -416,6 +414,15 @@ static inline void arm_interrupt_flash( uint32_t level )
#define _CPU_ISR_Flash( _isr_cookie ) \
arm_interrupt_flash( _isr_cookie )
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+#if defined(ARM_MULTILIB_ARCH_V4)
+ return ( level & 0x80 ) == 0;
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+ return level > 0x80;
+#endif
+}
+
void _CPU_ISR_Set_level( uint32_t level );
uint32_t _CPU_ISR_Get_level( void );
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index d0c21cd..85dbf78 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -667,6 +667,11 @@ typedef struct {
: : "d"(_level) : "R0" ); \
}
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return level != 0;
+}
+
/**
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 9d11a3d..871f30e 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -525,6 +525,11 @@ static inline void epiphany_interrupt_enable(uint32_t
level)
epiphany_interrupt_disable(); \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x2 ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h
b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 4dd98ae..f70e2c6 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -403,6 +403,11 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
#endif
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & EFLAGS_INTR_ENABLE ) != 0;
+}
+
uint32_t _CPU_ISR_Get_level( void );
/* Make sure interrupt stack has space for ISR
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h
b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index 1bba1e4..ed397dc 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -679,6 +679,11 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Flash( _isr_cookie ) \
lm32_flash_interrupts( _isr_cookie );
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x0001 ) != 0;
+}
+
/**
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h
b/cpukit/score/cpu/m32c/rtems/score/cpu.h
index 25953d7..e37cda9 100644
--- a/cpukit/score/cpu/m32c/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32c/rtems/score/cpu.h
@@ -669,6 +669,11 @@ typedef struct {
__asm__ volatile( "fclr I" ); \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x40 ) != 0;
+}
+
/**
* @ingroup
[PATCH 09/26] sparc64: Rename CPU_Minimum_stack_frame
Rename SPARC64-specific CPU_Minimum_stack_frame to
SPARC64_Minimum_stack_frame. Rename SPARC64-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE.
Update #2809.
---
c/src/lib/libbsp/sparc64/shared/start/start.S | 4 +-
c/src/lib/libcpu/sparc64/shared/score/interrupt.S | 2 +-
cpukit/score/cpu/sparc64/context.S| 6 +--
cpukit/score/cpu/sparc64/cpu.c| 2 +-
cpukit/score/cpu/sparc64/rtems/score/cpu.h| 52 +++
5 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/c/src/lib/libbsp/sparc64/shared/start/start.S
b/c/src/lib/libbsp/sparc64/shared/start/start.S
index ca85d69..56ecc05 100644
--- a/c/src/lib/libbsp/sparc64/shared/start/start.S
+++ b/c/src/lib/libbsp/sparc64/shared/start/start.S
@@ -140,10 +140,10 @@ halted: nop
.section BOOTSTRAP
.align CPU_ALIGNMENT
- .space 32768 - CPU_MINIMUM_STACK_FRAME_SIZE ! 32K boot stack grows down
+ .space 32768 - SPARC64_MINIMUM_STACK_FRAME_SIZE ! 32K boot stack grows down
.global StackStart
StackStart:
-.space CPU_MINIMUM_STACK_FRAME_SIZE ! initial stack frame
+.space SPARC64_MINIMUM_STACK_FRAME_SIZE ! initial stack frame
.section BOOTSTRAP
.align CPU_ALIGNMENT
diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S
b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S
index 5aee91a..6f8eb37 100644
--- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S
+++ b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S
@@ -197,7 +197,7 @@ PUBLIC(_ISR_Handler)
* enable traps again.
*/
- sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+ sub %sp, SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp
dont_switch_stacks:
/*
diff --git a/cpukit/score/cpu/sparc64/context.S
b/cpukit/score/cpu/sparc64/context.S
index 8bd0219..e83507d 100644
--- a/cpukit/score/cpu/sparc64/context.S
+++ b/cpukit/score/cpu/sparc64/context.S
@@ -39,7 +39,7 @@
.align 4
PUBLIC(_CPU_Context_save_fp)
SYM(_CPU_Context_save_fp):
-save%sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+save%sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp
/*
* The following enables the floating point unit.
@@ -105,7 +105,7 @@ PUBLIC(_CPU_Context_save_fp)
.align 4
PUBLIC(_CPU_Context_restore_fp)
SYM(_CPU_Context_restore_fp):
-save%sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp
+save%sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE , %sp
/*
* The following enables the floating point unit.
@@ -300,7 +300,7 @@ PUBLIC(_CPU_Context_restore_heir)
.align 4
PUBLIC(_CPU_Context_restore)
SYM(_CPU_Context_restore):
-save%sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+save%sp, -SPARC64_MINIMUM_STACK_FRAME_SIZE, %sp
!rdpr%pstate, %o2
ba SYM(_CPU_Context_restore_heir)
mov %i0, %o1 ! in the delay slot
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index 512ab90..93a4573 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -90,7 +90,7 @@ void _CPU_Context_Initialize(
*/
the_context->o7= ((uint64_t) entry_point) - 8;
-the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE -
STACK_BIAS;
+the_context->o6_sp = stack_high - SPARC64_MINIMUM_STACK_FRAME_SIZE -
STACK_BIAS;
the_context->i6_fp = 0;
/* ABI uses g4 as segment register, make sure it is zeroed */
diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
index 8e4012e..4e95784 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
@@ -238,7 +238,7 @@ typedef struct {
uint64_tsaved_arg4;
uint64_tsaved_arg5;
uint64_tpad0;
-} CPU_Minimum_stack_frame;
+} SPARC64_Minimum_stack_frame;
#endif /* !ASM */
@@ -267,7 +267,7 @@ typedef struct {
#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0
#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8
-#define CPU_MINIMUM_STACK_FRAME_SIZE 0xC0
+#define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0
/*
* Contexts
@@ -474,7 +474,7 @@ typedef struct {
*/
typedef struct {
- CPU_Minimum_stack_frame Stack_frame;
+ SPARC64_Minimum_stack_frame Stack_frame;
uint64_t tstate;
uint64_t tpc;
uint64_t tnpc;
@@ -504,29 +504,29 @@ typedef struct {
* Offsets of fields with CPU_Interrupt_frame for assembly routines.
*/
-#define ISF_TSTATE_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
-#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
-#define ISF_TNPC_OFFSETCPU_MINIMUM_STACK_FRAME_SIZE + 0x10
-#define ISF_PIL_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
-#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
-#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
-#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
-#define ISF_G3_OFFSET
[PATCH 11/26] sparc: Move CPU_Interrupt_frame related defines
Move CPU_Interrupt_frame related defines to .
Update #2809.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S| 2 +-
cpukit/score/cpu/sparc/cpu.c | 7 ++-
cpukit/score/cpu/sparc/rtems/score/cpu.h | 50 -
cpukit/score/cpu/sparc/rtems/score/cpuimpl.h | 51 +-
cpukit/score/cpu/sparc/sparc-context-validate.S| 2 +-
.../cpu/sparc/sparc-context-volatile-clobber.S | 2 +-
6 files changed, 59 insertions(+), 55 deletions(-)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index 3143b10..7a595d1 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -393,7 +393,7 @@ dont_do_the_window:
* REGISTERS SAME AS AT _ISR_Handler
*/
-sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
+sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
! make space for ISF
std %l0, [%sp + ISF_PSR_OFFSET]! save psr, PC
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 5afad17..92d1c66 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -106,7 +106,12 @@ SPARC_ASSERT_ISF_OFFSET(y, Y);
SPARC_ASSERT_ISF_OFFSET(tpc, TPC);
RTEMS_STATIC_ASSERT(
- sizeof(CPU_Interrupt_frame) == CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE,
+ sizeof(SPARC_Minimum_stack_frame) == SPARC_MINIMUM_STACK_FRAME_SIZE,
+ SPARC_MINIMUM_STACK_FRAME_SIZE
+);
+
+RTEMS_STATIC_ASSERT(
+ sizeof(CPU_Interrupt_frame) == CPU_INTERRUPT_FRAME_SIZE,
CPU_Interrupt_frame_size
);
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h
b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index f0f8110..27393b7 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -344,9 +344,6 @@ typedef struct {
/** This macro defines an offset into the stack frame for use in assembly. */
#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
-/** This defines the size of the minimum stack frame. */
-#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
-
#define CPU_MAXIMUM_PROCESSORS 32
/**
@@ -683,53 +680,6 @@ typedef struct {
#endif /* ASM */
-/*
- * Offsets of fields with CPU_Interrupt_frame for assembly routines.
- */
-
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48
-/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_TPC_OFFSET
[PATCH 18/26] score: Allow interrupts during thread dispatch
Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809. --- c/src/lib/libbsp/sparc/shared/irq_asm.S | 19 +-- c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | 29 +-- cpukit/score/cpu/arm/cpu_asm.S| 10 +--- cpukit/score/include/rtems/score/userextimpl.h| 13 +- cpukit/score/src/threaddispatch.c | 17 + cpukit/score/src/threadhandler.c | 3 --- cpukit/score/src/threadloadenv.c | 16 + 7 files changed, 50 insertions(+), 57 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S index 7a595d1..a842a62 100644 --- a/c/src/lib/libbsp/sparc/shared/irq_asm.S +++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S @@ -178,17 +178,22 @@ done_flushing: mov %g4, %wim #if defined(RTEMS_SMP) -! The executing context no longer executes on this processor +/* + * The executing thread no longer executes on this processor. Switch + * the stack to the temporary interrupt stack of this processor. Mark + * the context of the executing thread as not executing. + */ +add %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET] ! Try to update the is executing indicator of the heir context mov 1, %g1 -try_update_is_executing: +.Ltry_update_is_executing: swap[%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1 cmp %g1, 0 -bne check_is_executing +bne .Lcheck_is_executing ! The next load is in a delay slot, which is all right #endif @@ -225,12 +230,12 @@ try_update_is_executing: nop ! delay slot #if defined(RTEMS_SMP) -check_is_executing: +.Lcheck_is_executing: ! Check the is executing indicator of the heir context ld [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1 cmp %g1, 0 -beq try_update_is_executing +beq .Ltry_update_is_executing mov1, %g1 ! We may have a new heir @@ -242,7 +247,7 @@ check_is_executing: ! Update the executing only if necessary to avoid cache line ! monopolization. cmp %g2, %g4 -beq try_update_is_executing +beq .Ltry_update_is_executing mov1, %g1 ! Calculate the heir context pointer @@ -252,7 +257,7 @@ check_is_executing: ! Update the executing st %g4, [%g6 + PER_CPU_OFFSET_EXECUTING] -ba try_update_is_executing +ba .Ltry_update_is_executing mov1, %g1 #endif diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S index 7f3c036..e5b4fcd 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S @@ -402,23 +402,30 @@ PROC (_CPU_Context_switch): #endif #ifdef RTEMS_SMP - /* The executing context no longer executes on this processor */ + /* +* The executing thread no longer executes on this processor. Switch +* the stack to the temporary interrupt stack of this processor. Mark +* the context of the executing thread as not executing. +*/ msync + + GET_SELF_CPU_CONTROLr12 + addir1, r12, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE li r6, 0 stw r6, PPC_CONTEXT_OFFSET_IS_EXECUTING(r3) -check_is_executing: +.Lcheck_is_executing: /* Check the is executing indicator of the heir context */ addir6, r5, PPC_CONTEXT_OFFSET_IS_EXECUTING lwarx r7, r0, r6 cmpwi r7, 0 - bne get_potential_new_heir + bne .Lget_potential_new_heir /* Try to update the is executing indicator of the heir context */ li r7, 1 stwcx. r7, r0, r6 - bne get_potential_new_heir + bne .Lget_potential_new_heir isync #endif @@ -537,22 +544,20 @@ PROC (_CPU_Context_restore): b restore_context #ifdef RTEMS_SMP -get_potential_new_heir: - - GET_SELF_CPU_CONTROLr6 +.Lget_potential_new_heir: /* We may have a new heir */ /* Read the executing and heir */ - lwz r7, PER_CPU_OFFSET_EXECUTING(r6) - lwz r8, PER_CPU_OFFSET_HEIR(r6) + lwz r7, PER_CPU_OFFSET_EXECUTING(r12) + lwz r8, PER_CPU_OFFSET_HEIR(r12) /* * Update the executing only if necessary to avoid cache line *
[PATCH 05/26] score: Add and use _Thread_Dispatch_direct()
This function is useful for operations which synchronously block, e.g.
self restart, self deletion, yield, sleep. It helps to detect if these
operations are called in the wrong context. Since the thread dispatch
necessary indicator is not used, this is more robust in some SMP
situations.
Update #2751.
---
cpukit/posix/src/nanosleep.c | 2 +-
cpukit/posix/src/sched_yield.c| 2 +-
cpukit/rtems/src/taskwakeafter.c | 2 +-
cpukit/sapi/src/interrtext.c | 3 +-
cpukit/score/include/rtems/score/interr.h | 3 +-
cpukit/score/include/rtems/score/threaddispatch.h | 14
cpukit/score/src/threaddispatch.c | 16 +
cpukit/score/src/threadrestart.c | 8 +
testsuites/sptests/Makefile.am| 1 +
testsuites/sptests/configure.ac | 1 +
testsuites/sptests/spfatal29/Makefile.am | 19 ++
testsuites/sptests/spfatal29/spfatal29.doc| 11 ++
testsuites/sptests/spfatal29/spfatal29.scn| 3 ++
testsuites/sptests/spfatal29/testcase.h | 44 +++
testsuites/sptests/spinternalerror02/init.c | 2 +-
15 files changed, 118 insertions(+), 13 deletions(-)
create mode 100644 testsuites/sptests/spfatal29/Makefile.am
create mode 100644 testsuites/sptests/spfatal29/spfatal29.doc
create mode 100644 testsuites/sptests/spfatal29/spfatal29.scn
create mode 100644 testsuites/sptests/spfatal29/testcase.h
diff --git a/cpukit/posix/src/nanosleep.c b/cpukit/posix/src/nanosleep.c
index 38a6b8d..0fec1e4 100644
--- a/cpukit/posix/src/nanosleep.c
+++ b/cpukit/posix/src/nanosleep.c
@@ -96,7 +96,7 @@ static inline int nanosleep_yield( struct timespec *rmtp )
executing = _Thread_Get_executing();
cpu_self = _Thread_Dispatch_disable();
_Thread_Yield( executing );
- _Thread_Dispatch_enable( cpu_self );
+ _Thread_Dispatch_direct( cpu_self );
if ( rmtp ) {
rmtp->tv_sec = 0;
rmtp->tv_nsec = 0;
diff --git a/cpukit/posix/src/sched_yield.c b/cpukit/posix/src/sched_yield.c
index 7e056ce..cbbcb34 100644
--- a/cpukit/posix/src/sched_yield.c
+++ b/cpukit/posix/src/sched_yield.c
@@ -30,6 +30,6 @@ int sched_yield( void )
cpu_self = _Thread_Dispatch_disable();
_Thread_Yield( _Per_CPU_Get_executing( cpu_self ) );
- _Thread_Dispatch_enable( cpu_self );
+ _Thread_Dispatch_direct( cpu_self );
return 0;
}
diff --git a/cpukit/rtems/src/taskwakeafter.c b/cpukit/rtems/src/taskwakeafter.c
index fa5f6f4..568b937 100644
--- a/cpukit/rtems/src/taskwakeafter.c
+++ b/cpukit/rtems/src/taskwakeafter.c
@@ -48,6 +48,6 @@ rtems_status_code rtems_task_wake_after(
ticks
);
}
- _Thread_Dispatch_enable( cpu_self );
+ _Thread_Dispatch_direct( cpu_self );
return RTEMS_SUCCESSFUL;
}
diff --git a/cpukit/sapi/src/interrtext.c b/cpukit/sapi/src/interrtext.c
index 6653022..edf09db 100644
--- a/cpukit/sapi/src/interrtext.c
+++ b/cpukit/sapi/src/interrtext.c
@@ -56,7 +56,8 @@ static const char *const internal_error_text[] = {
"INTERNAL_ERROR_RTEMS_INIT_TASK_ENTRY_IS_NULL",
"INTERNAL_ERROR_POSIX_INIT_THREAD_ENTRY_IS_NULL",
"INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK",
- "INTERNAL_ERROR_THREAD_QUEUE_ENQUEUE_STICKY_FROM_BAD_STATE"
+ "INTERNAL_ERROR_THREAD_QUEUE_ENQUEUE_STICKY_FROM_BAD_STATE",
+ "INTERNAL_ERROR_BAD_THREAD_DISPATCH_DISABLE_LEVEL"
};
const char *rtems_internal_error_text( rtems_fatal_code error )
diff --git a/cpukit/score/include/rtems/score/interr.h
b/cpukit/score/include/rtems/score/interr.h
index dff6101..e23db5c 100644
--- a/cpukit/score/include/rtems/score/interr.h
+++ b/cpukit/score/include/rtems/score/interr.h
@@ -165,7 +165,8 @@ typedef enum {
INTERNAL_ERROR_RTEMS_INIT_TASK_ENTRY_IS_NULL,
INTERNAL_ERROR_POSIX_INIT_THREAD_ENTRY_IS_NULL,
INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK,
- INTERNAL_ERROR_THREAD_QUEUE_ENQUEUE_STICKY_FROM_BAD_STATE
+ INTERNAL_ERROR_THREAD_QUEUE_ENQUEUE_STICKY_FROM_BAD_STATE,
+ INTERNAL_ERROR_BAD_THREAD_DISPATCH_DISABLE_LEVEL
} Internal_errors_Core_list;
typedef CPU_Uint32ptr Internal_errors_t;
diff --git a/cpukit/score/include/rtems/score/threaddispatch.h
b/cpukit/score/include/rtems/score/threaddispatch.h
index 801970a..f4ca096 100644
--- a/cpukit/score/include/rtems/score/threaddispatch.h
+++ b/cpukit/score/include/rtems/score/threaddispatch.h
@@ -95,6 +95,20 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization(
void )
void _Thread_Dispatch( void );
/**
+ * @brief Directly do a thread dispatch.
+ *
+ * Must be called with a thread dispatch disable level of one, otherwise the
+ * INTERNAL_ERROR_BAD_THREAD_DISPATCH_DISABLE_LEVEL will occur. This function
+ * is useful for operations which synchronously block, e.g. self restart, self
+ * deletion, yield, sleep.
+ *
+ * @param[in] cpu_self The current processor.
+ *
+ * @see _Thread_Dispatch().
+ */
+void _Thread_Dispatch_direct( Per_CPU_Control *cpu_self );
[PATCH 21/26] arm: Simplify _ARMV4_Exception_interrupt
Move profiling code closer to bsp_interrupt_disable() to allow re-use of
r9 later.
---
cpukit/score/cpu/arm/arm_exc_interrupt.S | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S
b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index 28da989..de5a022 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -112,16 +112,23 @@ _ARMV4_Exception_interrupt:
str r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
str r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
+ /* Call BSP dependent interrupt dispatcher */
#ifdef RTEMS_PROFILING
cmp r2, #1
- bne .Lprofiling_entry_done
+ bne .Lskip_profiling
bl _CPU_Counter_read
- push{r0, r1}
-.Lprofiling_entry_done:
-#endif
-
- /* Call BSP dependent interrupt dispatcher */
+ mov SELF_CPU_CONTROL, r0
+ bl bsp_interrupt_dispatch
+ bl _CPU_Counter_read
+ mov r2, r0
+ mov r1, SELF_CPU_CONTROL
+ GET_SELF_CPU_CONTROLr0
+ mov SELF_CPU_CONTROL, r0
+ bl _Profiling_Outer_most_interrupt_entry_and_exit
+.Lprofiling_done:
+#else
bl bsp_interrupt_dispatch
+#endif
/* Decrement interrupt nest and thread dispatch disable level */
ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
@@ -131,18 +138,6 @@ _ARMV4_Exception_interrupt:
str r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL]
str r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
-#ifdef RTEMS_PROFILING
- cmp r2, #0
- bne .Lprofiling_exit_done
- bl _CPU_Counter_read
- pop {r1, r3}
- mov r2, r0
- mov r0, SELF_CPU_CONTROL
- bl _Profiling_Outer_most_interrupt_entry_and_exit
- ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
-.Lprofiling_exit_done:
-#endif
-
/* Restore stack pointer */
mov sp, SP_OF_INTERRUPTED_CONTEXT
@@ -239,4 +234,13 @@ _ARMV4_Exception_interrupt:
/* Return from interrupt */
subspc, lr, #4
+#ifdef RTEMS_PROFILING
+#ifdef __thumb__
+.thumb
+#endif
+.Lskip_profiling:
+ bl bsp_interrupt_dispatch
+ b .Lprofiling_done
+#endif
+
#endif /* ARM_MULTILIB_ARCH_V4 */
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 20/26] arm: Use local labels
---
cpukit/score/cpu/arm/arm_exc_interrupt.S | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S
b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index 61a9c3e..28da989 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2009, 2016 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -114,10 +114,10 @@ _ARMV4_Exception_interrupt:
#ifdef RTEMS_PROFILING
cmp r2, #1
- bne profiling_entry_done
+ bne .Lprofiling_entry_done
bl _CPU_Counter_read
push{r0, r1}
-profiling_entry_done:
+.Lprofiling_entry_done:
#endif
/* Call BSP dependent interrupt dispatcher */
@@ -133,14 +133,14 @@ profiling_entry_done:
#ifdef RTEMS_PROFILING
cmp r2, #0
- bne profiling_exit_done
+ bne .Lprofiling_exit_done
bl _CPU_Counter_read
pop {r1, r3}
mov r2, r0
mov r0, SELF_CPU_CONTROL
bl _Profiling_Outer_most_interrupt_entry_and_exit
ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
-profiling_exit_done:
+.Lprofiling_exit_done:
#endif
/* Restore stack pointer */
@@ -148,14 +148,14 @@ profiling_exit_done:
/* Check thread dispatch disable level */
cmp r3, #0
- bne thread_dispatch_done
+ bne .Lthread_dispatch_done
/* Check context switch necessary */
ldrbr1, [SELF_CPU_CONTROL, #PER_CPU_DISPATCH_NEEDED]
cmp r1, #0
- beq thread_dispatch_done
+ beq .Lthread_dispatch_done
-/* This aligns thread_dispatch_done on a 4 byte boundary */
+/* This aligns .Lthread_dispatch_done on a 4 byte boundary */
#ifdef __thumb__
nop
#endif /* __thumb__ */
@@ -163,7 +163,7 @@ profiling_exit_done:
/* Thread dispatch */
bl _Thread_Dispatch
-thread_dispatch_done:
+.Lthread_dispatch_done:
/* Switch to ARM instructions if necessary */
SWITCH_FROM_THUMB_TO_ARM
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 13/26] powerpc: Move legacy CPU_Interrupt_frame
The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx
support. Move it to here.
Update #2809.
---
c/src/lib/libbsp/powerpc/ss555/irq/irq.h | 1 -
c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h | 33 ++
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 31
3 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h
b/c/src/lib/libbsp/powerpc/ss555/irq/irq.h
index 31c4be9..44e3960 100644
--- a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/ss555/irq/irq.h
@@ -44,7 +44,6 @@ int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data*
irq);
int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq);
int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config);
int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config);
-void C_dispatch_irq_handler(CPU_Interrupt_frame *frame, unsigned int excNum);
void C_default_exception_handler(CPU_Exception_frame* excPtr);
/*
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
index c1ec403..8e634d1 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h
@@ -161,6 +161,39 @@ int CPU_irq_level_from_symbolic_name(const
rtems_irq_number name);
extern void CPU_rtems_irq_mng_init(unsigned cpuId);
+typedef struct CPU_Interrupt_frame {
+uint32_t stacklink; /* Ensure this is a real frame (also reg1 save)
*/
+uint32_t calleeLr; /* link register used by callees: SVR4/EABI */
+
+/* This is what is left out of the primary contexts */
+uint32_t gpr0;
+uint32_t gpr2; /* play safe */
+uint32_t gpr3;
+uint32_t gpr4;
+uint32_t gpr5;
+uint32_t gpr6;
+uint32_t gpr7;
+uint32_t gpr8;
+uint32_t gpr9;
+uint32_t gpr10;
+uint32_t gpr11;
+uint32_t gpr12;
+uint32_t gpr13; /* Play safe */
+uint32_t gpr28; /* For internal use by the IRQ handler */
+uint32_t gpr29; /* For internal use by the IRQ handler */
+uint32_t gpr30; /* For internal use by the IRQ handler */
+uint32_t gpr31; /* For internal use by the IRQ handler */
+uint32_t cr; /* Bits of this are volatile, so no-one may save */
+uint32_t ctr;
+uint32_t xer;
+uint32_t lr;
+uint32_t pc;
+uint32_t msr;
+uint32_t pad[3];
+} CPU_Interrupt_frame;
+
+void C_dispatch_irq_handler(CPU_Interrupt_frame *frame, unsigned int excNum);
+
#endif
#endif
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index bd729c0..dc42d99 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -437,37 +437,6 @@ typedef struct {
#endif /* (PPC_HAS_FPU == 1) */
} Context_Control_fp;
-typedef struct CPU_Interrupt_frame {
-uint32_t stacklink; /* Ensure this is a real frame (also reg1 save)
*/
-uint32_t calleeLr; /* link register used by callees: SVR4/EABI */
-
-/* This is what is left out of the primary contexts */
-uint32_t gpr0;
-uint32_t gpr2; /* play safe */
-uint32_t gpr3;
-uint32_t gpr4;
-uint32_t gpr5;
-uint32_t gpr6;
-uint32_t gpr7;
-uint32_t gpr8;
-uint32_t gpr9;
-uint32_t gpr10;
-uint32_t gpr11;
-uint32_t gpr12;
-uint32_t gpr13; /* Play safe */
-uint32_t gpr28; /* For internal use by the IRQ handler */
-uint32_t gpr29; /* For internal use by the IRQ handler */
-uint32_t gpr30; /* For internal use by the IRQ handler */
-uint32_t gpr31; /* For internal use by the IRQ handler */
-uint32_t cr; /* Bits of this are volatile, so no-one may save */
-uint32_t ctr;
-uint32_t xer;
-uint32_t lr;
-uint32_t pc;
-uint32_t msr;
-uint32_t pad[3];
-} CPU_Interrupt_frame;
-
#endif /* ASM */
/*
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 10/26] sparc: Rename CPU_Minimum_stack_frame
Rename SPARC-specific CPU_Minimum_stack_frame to
SPARC_Minimum_stack_frame. Rename SPARC-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE.
Update #2809.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S| 8 ++--
c/src/lib/libbsp/sparc/shared/start/start.S| 2 +-
cpukit/score/cpu/sparc/cpu.c | 2 +-
cpukit/score/cpu/sparc/rtems/score/cpu.h | 46 +++---
cpukit/score/cpu/sparc/sparc-context-validate.S| 2 +-
.../cpu/sparc/sparc-context-volatile-clobber.S | 2 +-
6 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index 4a0c382..3143b10 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -26,7 +26,7 @@
#include
#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
- #define FP_FRAME_OFFSET_FO_F1 (CPU_MINIMUM_STACK_FRAME_SIZE + 0)
+ #define FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
#define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
#define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
#define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
@@ -268,7 +268,7 @@ check_is_executing:
.align 4
PUBLIC(_CPU_Context_restore)
SYM(_CPU_Context_restore):
-save%sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+save%sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
rd %psr, %o2
#if defined(RTEMS_SMP)
! On SPARC the restore path needs also a valid executing context on SMP
@@ -486,7 +486,7 @@ dont_switch_stacks:
* enable traps again.
*/
-sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
/*
* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
@@ -621,7 +621,7 @@ profiling_not_outer_most_exit:
* of the task and subsequent interrupts can operate normally.
*/
-sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+sub %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
or %l0, SPARC_PSR_ET_MASK, %l7! l7 = PSR with ET=1
mov %l7, %psr ! ENABLE TRAPS
diff --git a/c/src/lib/libbsp/sparc/shared/start/start.S
b/c/src/lib/libbsp/sparc/shared/start/start.S
index 46498b8..a7ef9fe 100644
--- a/c/src/lib/libbsp/sparc/shared/start/start.S
+++ b/c/src/lib/libbsp/sparc/shared/start/start.S
@@ -289,7 +289,7 @@ SYM(hard_reset):
mov %sp, %fp! set frame pointer
callSYM(bsp_start_on_secondary_processor) ! does not return
-sub%sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+sub%sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
cpu0:
#endif
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 899ed40..5afad17 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -343,7 +343,7 @@ void _CPU_Context_Initialize(
*/
the_context->o7= ((uint32_t) entry_point) - 8;
-the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
+the_context->o6_sp = stack_high - SPARC_MINIMUM_STACK_FRAME_SIZE;
the_context->i6_fp = 0;
/*
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h
b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index e7fc3b2..f0f8110 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -291,7 +291,7 @@ typedef struct {
uint32_tsaved_arg5;
/** This field pads the structure so ldd and std instructions can be used. */
uint32_tpad0;
-} CPU_Minimum_stack_frame;
+} SPARC_Minimum_stack_frame;
#endif /* ASM */
@@ -345,7 +345,7 @@ typedef struct {
#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
/** This defines the size of the minimum stack frame. */
-#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
+#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
#define CPU_MAXIMUM_PROCESSORS 32
@@ -638,7 +638,7 @@ typedef struct {
*/
typedef struct {
/** On an interrupt, we must save the minimum stack frame. */
- CPU_Minimum_stack_frame Stack_frame;
+ SPARC_Minimum_stack_frame Stack_frame;
/** This is the offset of the PSR on an ISF. */
uint32_t psr;
/** This is the offset of the XXX on an ISF. */
@@ -688,47 +688,47 @@ typedef struct {
*/
/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
+#define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
+#define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
/** This macro defines an offset into the ISF for use in assembly. */
-#define ISF_NPC_OFFSET
[PATCH 08/26] rtems: Conditionally define rtems_interrupt_frame
Update #2808.
---
cpukit/rtems/include/rtems/rtems/types.h| 7 ++-
cpukit/score/cpu/arm/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/bfin/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/i386/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/lm32/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/m32c/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/m68k/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/mips/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/or1k/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/sh/rtems/score/cpu.h | 2 +-
cpukit/score/cpu/sparc/rtems/score/cpu.h| 2 +-
cpukit/score/cpu/sparc64/rtems/score/cpu.h | 2 +-
cpukit/score/include/rtems/score/isr.h | 2 +-
16 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/cpukit/rtems/include/rtems/rtems/types.h
b/cpukit/rtems/include/rtems/rtems/types.h
index 9789476..82c0edd 100644
--- a/cpukit/rtems/include/rtems/rtems/types.h
+++ b/cpukit/rtems/include/rtems/rtems/types.h
@@ -98,13 +98,18 @@ typedef Context_Controlrtems_context;
typedef Context_Control_fp rtems_context_fp;
#endif
+#if (CPU_ISR_PASSES_FRAME_POINTER == TRUE)
/**
* @brief Defines the format of the interrupt stack frame as it appears to a
* user ISR.
*
- * This data structure may not be defined on all ports
+ * This data structure is only provided if the interrupt stack frame is passed
+ * to the ISR handler.
+ *
+ * @see rtems_interrupt_catch().
*/
typedef CPU_Interrupt_framertems_interrupt_frame;
+#endif
/**
* @brief Information structure returned by the Heap Handler via the Region
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 21d09a7..e4f9e37 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -118,7 +118,7 @@
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
-#define CPU_ISR_PASSES_FRAME_POINTER 0
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
#define CPU_HARDWARE_FP FALSE
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index fb5198e..d0c21cd 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -115,7 +115,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 1
+#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/**
* @def CPU_HARDWARE_FP
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 23da66b..9d11a3d 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -117,7 +117,7 @@ extern "C" {
*
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 1
+#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/*
* Does the CPU have hardware floating point?
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h
b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 4ba3b27..4dd98ae 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -60,7 +60,7 @@ extern "C" {
* number (0)?
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 0
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Some family members have no FP, some have an FPU such as the i387
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h
b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index feff8e6..1bba1e4 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -113,7 +113,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 1
+#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/**
* @def CPU_HARDWARE_FP
diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h
b/cpukit/score/cpu/m32c/rtems/score/cpu.h
index 6b9e73e..25953d7 100644
--- a/cpukit/score/cpu/m32c/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32c/rtems/score/cpu.h
@@ -129,7 +129,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 0
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/**
* @def CPU_HARDWARE_FP
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h
b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index 307fae1..f8184dc 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -61,7 +61,7 @@ extern "C" {
* number (0)?
*/
-#define CPU_ISR_PASSES_FRAME_POINTER 0
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Some family members have no FP, some have an FPU such as the
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h
b/cpukit/score/cpu/mips/rtems/score/cpu.h
index d39e17d..4e1eba1 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@
Performance and robustness improvements
This patch set addresses the following tickets: https://devel.rtems.org/ticket/2751 https://devel.rtems.org/ticket/2808 https://devel.rtems.org/ticket/2809 https://devel.rtems.org/ticket/2811 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 12/26] bsps/powerpc: Avoid use of CPU_Interrupt_frame
This type is not relevant for the code since only a pointer is passed
around.
Update #2809.
---
c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
index eacfbb8..7836191 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
@@ -158,10 +158,10 @@ disable_ext_irq( uint32_t mask)
*/
void
ictrl_spurious_handler(uint32_t spurious_mask,
- CPU_Interrupt_frame *cpu_frame)
+ void *cpu_frame)
{
int v;
- extern void (*bsp_spurious_handler)(uint32_t vector, CPU_Interrupt_frame
*);
+ extern void (*bsp_spurious_handler)(uint32_t vector, void *);
for (v=0; v < PPC_IRQ_EXT_MAX; v++) {
if (VEC_TO_EXMSK(v) & spurious_mask) {
@@ -184,7 +184,7 @@ ictrl_spurious_handler(uint32_t spurious_mask,
*/
void
-ictrl_isr(rtems_vector_number vector,CPU_Interrupt_frame *cpu_frame)
+ictrl_isr(rtems_vector_number vector, void *cpu_frame)
{
uint32_t istat,
mask,
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 07/26] bsps/mips: Use
Avoid duplicate mips_vector_isr_handlers() declarations.
---
c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c | 2 +-
c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c | 2 +-
c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c| 3 +--
c/src/lib/libbsp/mips/malta/irq/vectorisrs.c | 2 +-
c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c | 2 +-
c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c | 2 +-
c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h | 2 ++
7 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c
index 182efaa..d8e0712 100644
--- a/c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/csb350/irq/vectorisrs.c
@@ -16,11 +16,11 @@
#include
#include
#include
+#include
#include
#include
#include
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
#include /* for printk */
diff --git a/c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c
index 838f959..e555666 100644
--- a/c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/hurricane/irq/vectorisrs.c
@@ -15,13 +15,13 @@
#include
#include
+#include
#include
#include
#include
#include /* for printk */
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
void mips_default_isr( int vector );
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
diff --git a/c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c
index abb9b30..629c4c4 100644
--- a/c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/jmr3904/irq/vectorisrs.c
@@ -18,8 +18,7 @@
#include
#include /* for printk */
#include
-
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
+#include
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
diff --git a/c/src/lib/libbsp/mips/malta/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/malta/irq/vectorisrs.c
index 5853e5e..a2b9288 100644
--- a/c/src/lib/libbsp/mips/malta/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/malta/irq/vectorisrs.c
@@ -18,9 +18,9 @@
#include
#include
#include
+#include
void mips_default_isr( int vector );
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
#include /* for printk */
diff --git a/c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c
index f130f70..09020c5 100644
--- a/c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/rbtx4925/irq/vectorisrs.c
@@ -15,12 +15,12 @@
#include
#include
+#include
#include
#include
#include
#include /* for printk */
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
void mips_default_isr( int vector );
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
diff --git a/c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c
b/c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c
index e13a776..d38e4f8 100644
--- a/c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c
+++ b/c/src/lib/libbsp/mips/rbtx4938/irq/vectorisrs.c
@@ -15,12 +15,12 @@
#include
#include
+#include
#include
#include
#include
#include /* for printk */
-void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
void mips_default_isr( int vector );
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h
b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h
index d31c334..e142018 100644
--- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h
+++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h
@@ -15,6 +15,8 @@
#ifndef _ISR_ENTRIES_H
#define _ISR_ENTRIES_H 1
+#include
+
extern void mips_install_isr_entries( void );
extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
--
1.8.4.5
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: Update virtio network driver
Hello Jin-Hyun, On Tuesday 15 of November 2016 11:29:05 Pavel Pisa wrote: > Hello Jin-Hyun, > > thanks for update. > > I have returned from my USA holydays now and catching up > with e-mails and work backlogs. > > On Thursday 10 of November 2016 10:42:34 Jinhyun wrote: > > Hi, all! > > > > We removed our RTEMS-virtio driver's dependencies on architecture. We > > used built-in function of gcc, __sync_synchronize(). This function > > generates proper memory barrier for target architecture on compile time. > > In addition, we replaced pcib_conf_read/write functions to > > pci_read/write_config functions. We added several lines of codes for > > exception handling suggested by Pavel Pisa. Thank you, Pavel Pisa. As we > > removed dependencies on CPU architectures, we moved the virtio source > > directory located at > > c/src/lib/libbsp/i386/pc386/ to c/src/lib/libbsp/shared. > > I have done some updates and testing of your work some time ago. > I think I reported that but I am not 100% sure. Please, > look if some changes in my WIP branch are of some use for you OK, I see that it is integrated. Great. Pavel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Update virtio network driver
Hello Jin-Hyun, thanks for update. I have returned from my USA holydays now and catching up with e-mails and work backlogs. On Thursday 10 of November 2016 10:42:34 Jinhyun wrote: > Hi, all! > > We removed our RTEMS-virtio driver's dependencies on architecture. We used > built-in function of gcc, __sync_synchronize(). This function generates > proper memory barrier for target architecture on compile time. In addition, > we replaced pcib_conf_read/write functions to pci_read/write_config > functions. We added several lines of codes for exception handling suggested > by Pavel Pisa. Thank you, Pavel Pisa. As we removed dependencies on CPU > architectures, we moved the virtio source directory located at > c/src/lib/libbsp/i386/pc386/ to c/src/lib/libbsp/shared. I have done some updates and testing of your work some time ago. I think I reported that but I am not 100% sure. Please, look if some changes in my WIP branch are of some use for you https://github.com/ppisa/rtems/commits/devel-virtio As for RTEMS_COMPILER_MEMORY_BARRIER() suggested by Gedare, I am not sure if it is enough in some places. VirtIO is PCI like device and compiler barrier would work if the hypervisor places data into shared buffer from the same CPU. If it runs on different one in parallel with RTEMS driver (in network polled API like mode) then real SMP barrier is more appropriate. Best wishes, Pavel > We plan to enhance the virtio driver for RTEMS, and we have several > additional patches for it. To easily manage this project from our side, we > created Github repository. You can see the latest version of our virtio > driver in our Github: https://github.com/sslab-konkuk/RTEMS-virtio > > Recently, we succeeded to test the virtio with Motorola_powerpc BSP. For > this, we made additional modifications. Motorola_powerpc BSP doesn't > support functions such as rtems_insterrupt_handler_install, so we used > functions such as BSP_install_rtems_irq_handler instead of those. Moreover, > in order to make our virtio work on PowerPC, we added initialization codes > to virtio_pci.c because qemu_fakerom, which is the PowerPC bios of > Motorola_powerpc BSP, doesn't initialize the virtio back-end driver. But > some runtime error is occurred on RTEMS master branch, so we will submit > about it again soon. > > Best regards, > Jin-Hyun. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
