Disable libnetwork on Epiphany?
Hi When you build with --enable-network on epiphany, it fails. Is it even reasonable to think it should build or be deployable? If not, I would like to force it disabled. Thoughts? --joel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[GSoC - x86_64] Final report
Hi! I've written my final report up here: https://blog.whatthedude.com/post/gsoc-final/ Let me know if you have any comments! It's been really fun working with all of you, and I look forward to more! Cheers! ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 0/5] [GSoC - x86_64] Add interrupts and clock driver
Unless someone sees a reason to delay merging this, I plan to merge it today. It is new and should have no impact on anything else. Patches to improve style, etc. can be followups. --joel On Mon, Aug 13, 2018 at 6:27 AM, Amaan Cheval wrote: > This patch series includes all of my remaining work so far on the x86_64 > BSP. It > supports: > > * Static paging support using 1GiB superpages > * RTEMS interrupts > * A fairly accurate clock driver based on the APIC timer calibrated by the > PIT > > ticker.exe passes reliably on -O0 optimization level, and it seems like it > _should_ on -O2 as well, except for the issue I've been describing on this > thread: > > https://lists.rtems.org/pipermail/devel/2018-August/022825.html > > bsps/x86_64/amd64/clock/clock.c | 299 ++ > bsps/x86_64/amd64/config/amd64.cfg| 3 + > bsps/x86_64/amd64/headers.am | 3 + > bsps/x86_64/amd64/include/apic.h | 62 > bsps/x86_64/amd64/include/clock.h | 99 ++ > bsps/x86_64/amd64/include/pic.h | 75 + > bsps/x86_64/amd64/interrupts/idt.c| 151 + > bsps/x86_64/amd64/interrupts/isr_handler.S| 191 +++ > bsps/x86_64/amd64/interrupts/pic.c| 76 + > bsps/x86_64/amd64/start/bspstart.c| 4 + > bsps/x86_64/amd64/start/linkcmds | 6 +- > bsps/x86_64/amd64/start/page.c| 172 ++ > bsps/x86_64/headers.am| 9 + > bsps/x86_64/include/bsp/irq.h | 46 +++ > bsps/x86_64/include/libcpu/page.h | 68 > c/src/lib/libbsp/x86_64/amd64/Makefile.am | 9 +- > cpukit/score/cpu/x86_64/cpu.c | 17 +- > cpukit/score/cpu/x86_64/headers.am| 2 + > cpukit/score/cpu/x86_64/include/rtems/asm.h | 10 + > .../cpu/x86_64/include/rtems/score/cpu.h | 112 +-- > .../cpu/x86_64/include/rtems/score/cpu_asm.h | 104 ++ > .../cpu/x86_64/include/rtems/score/cpuimpl.h | 16 +- > .../cpu/x86_64/include/rtems/score/idt.h | 131 > .../cpu/x86_64/include/rtems/score/x86_64.h | 13 +- > .../cpu/x86_64/x86_64-context-initialize.c| 9 +- > .../score/cpu/x86_64/x86_64-context-switch.S | 8 +- > 26 files changed, 1636 insertions(+), 59 deletions(-) > create mode 100644 bsps/x86_64/amd64/clock/clock.c > create mode 100644 bsps/x86_64/amd64/include/apic.h > create mode 100644 bsps/x86_64/amd64/include/clock.h > create mode 100644 bsps/x86_64/amd64/include/pic.h > create mode 100644 bsps/x86_64/amd64/interrupts/idt.c > create mode 100644 bsps/x86_64/amd64/interrupts/isr_handler.S > create mode 100644 bsps/x86_64/amd64/interrupts/pic.c > create mode 100644 bsps/x86_64/amd64/start/page.c > create mode 100644 bsps/x86_64/headers.am > create mode 100644 bsps/x86_64/include/bsp/irq.h > create mode 100644 bsps/x86_64/include/libcpu/page.h > create mode 100644 cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h > create mode 100644 cpukit/score/cpu/x86_64/include/rtems/score/idt.h > > -- > 2.18.0 > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 3/5] bsps/x86_64: Add paging support with 1GiB super pages
Updates #2898.
---
bsps/x86_64/amd64/start/bspstart.c| 2 +
bsps/x86_64/amd64/start/page.c| 172 ++
bsps/x86_64/headers.am| 5 +
bsps/x86_64/include/libcpu/page.h | 68 +++
c/src/lib/libbsp/x86_64/amd64/Makefile.am | 1 +
.../cpu/x86_64/include/rtems/score/cpu_asm.h | 13 ++
6 files changed, 261 insertions(+)
create mode 100644 bsps/x86_64/amd64/start/page.c
create mode 100644 bsps/x86_64/headers.am
create mode 100644 bsps/x86_64/include/libcpu/page.h
diff --git a/bsps/x86_64/amd64/start/bspstart.c
b/bsps/x86_64/amd64/start/bspstart.c
index 784748ce3f..5a5b46bcec 100644
--- a/bsps/x86_64/amd64/start/bspstart.c
+++ b/bsps/x86_64/amd64/start/bspstart.c
@@ -26,7 +26,9 @@
#include
#include
+#include
void bsp_start(void)
{
+ paging_init();
}
diff --git a/bsps/x86_64/amd64/start/page.c b/bsps/x86_64/amd64/start/page.c
new file mode 100644
index 00..64bdf21707
--- /dev/null
+++ b/bsps/x86_64/amd64/start/page.c
@@ -0,0 +1,172 @@
+/*
+ * This file sets up page sizes to 1GiB (i.e. huge pages, using only the PML4
+ * and PDPT, skipping the PDT, and PT).
+ * We set up identity-page mapping for the 512 GiBs addressable by using static
+ * PML4 and PDPT tables.
+ *
+ * Section 4.5 "4-Level Paging" of Volume 3 of the Intel Software Developer
+ * Manual guides a lot of the code used in this file.
+ */
+
+/*
+ * Copyright (c) 2018.
+ * Amaan Cheval
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+uint64_t amd64_pml4[NUM_PAGE_TABLE_ENTRIES] RTEMS_ALIGNED(4096);
+uint64_t amd64_pdpt[NUM_PAGE_TABLE_ENTRIES] RTEMS_ALIGNED(4096);
+
+bool paging_1gib_pages_supported(void)
+{
+ /*
+ * If CPUID.8001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages are supported
+ * with 4-level paging.
+ */
+ uint32_t a, b, c, d;
+ cpuid(0x8001, , , , );
+ return (d >> 26) & 1;
+}
+
+uint8_t get_maxphysaddr(void)
+{
+ /*
+ * CPUID.8008H:EAX[15:8] reports the linear-address width supported by
the
+ * processor. Generally, this value is 48 if CPUID.8001H:EDX.LM [bit 29]
=
+ * 1 and 32 otherwise.
+ */
+ uint32_t a, b, c, d;
+ cpuid(0x8008, , , , );
+
+ uint8_t maxphysaddr = (a >> 8) & 0xff;
+ /* This width is referred to as MAXPHYADDR. MAXPHYADDR is at most 52. */
+ assert(maxphysaddr <= 52);
+
+ return maxphysaddr;
+}
+
+uint64_t get_mask_for_bits(uint8_t start, uint8_t end)
+{
+ /*
+ * Create a mask that lets you select bits start:end when logically ANDed
with
+ * a value. For eg.
+ * get_mask_for_bits(48, 64) = 0x
+ */
+ uint64_t mask = (((uint64_t) 1 << (end - start)) - 1) << start;
+ return mask;
+}
+
+RTEMS_INLINE_ROUTINE void assert_0s_from_bit(uint64_t entry, uint8_t bit_pos)
+{
+ /* Confirm that bit_pos:64 are all 0s */
+ assert((entry & get_mask_for_bits(bit_pos, 64)) == 0);
+}
+
+uint64_t create_cr3_entry(
+ uint64_t phys_addr, uint8_t maxphysaddr, uint64_t flags
+)
+{
+ /* Confirm PML4 address is aligned on a 4KiB boundary */
+ assert((phys_addr & 0xfff) == 0);
+ uint64_t entry = (phys_addr & get_mask_for_bits(12, maxphysaddr)) | flags;
+
+ /* Confirm that bits maxphysaddr:64 are 0s */
+ assert_0s_from_bit(entry, maxphysaddr);
+ return entry;
+}
+
+uint64_t create_pml4_entry(
+ uint64_t phys_addr, uint8_t maxphysaddr, uint64_t flags
+)
+{
+ /* Confirm address we're writing is aligned on a 4KiB boundary */
+ assert((phys_addr & 0xfff) == 0);
+ uint64_t entry = (phys_addr & get_mask_for_bits(12, maxphysaddr)) | flags;
+
+ /*
+ * Confirm that bits maxphysaddr:64 are 0s; there are other usable bits there
+ * such as
[PATCH 5/5] bsps/x86_64: Add APIC timer based clock driver
The APIC timer is calibrated by running the i8254 PIT for a fraction of a
second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the
APIC counter has ticked. The calibration can be run multiple times (determined
by APIC_TIMER_NUM_CALIBRATIONS) and averaged out.
Updates #2898.
---
bsps/x86_64/amd64/clock/clock.c | 299 ++
bsps/x86_64/amd64/headers.am | 3 +
bsps/x86_64/amd64/include/apic.h | 62
bsps/x86_64/amd64/include/clock.h | 99 ++
bsps/x86_64/amd64/include/pic.h | 75 +
bsps/x86_64/amd64/interrupts/pic.c| 76 +
c/src/lib/libbsp/x86_64/amd64/Makefile.am | 4 +-
.../cpu/x86_64/include/rtems/score/cpu_asm.h | 23 ++
8 files changed, 640 insertions(+), 1 deletion(-)
create mode 100644 bsps/x86_64/amd64/clock/clock.c
create mode 100644 bsps/x86_64/amd64/include/apic.h
create mode 100644 bsps/x86_64/amd64/include/clock.h
create mode 100644 bsps/x86_64/amd64/include/pic.h
create mode 100644 bsps/x86_64/amd64/interrupts/pic.c
diff --git a/bsps/x86_64/amd64/clock/clock.c b/bsps/x86_64/amd64/clock/clock.c
new file mode 100644
index 00..76e537755a
--- /dev/null
+++ b/bsps/x86_64/amd64/clock/clock.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2018.
+ * Amaan Cheval
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Use the amd64_apic_base as an array of 32-bit APIC registers */
+volatile uint32_t *amd64_apic_base;
+static struct timecounter amd64_clock_tc;
+
+extern volatile uint32_t Clock_driver_ticks;
+extern void apic_spurious_handler(void);
+extern void Clock_isr(void *param);
+
+static uint32_t amd64_clock_get_timecount(struct timecounter *tc)
+{
+ return Clock_driver_ticks;
+}
+
+/*
+ * When the CPUID instruction is executed with a source operand of 1 in the EAX
+ * register, bit 9 of the CPUID feature flags returned in the EDX register
+ * indicates the presence (set) or absence (clear) of a local APIC.
+ */
+bool has_apic_support()
+{
+ uint32_t eax, ebx, ecx, edx;
+ cpuid(1, , , , );
+ return (edx >> 9) & 1;
+}
+
+/*
+ * Initializes the APIC by hardware and software enabling it, and sets up the
+ * amd64_apic_base pointer that can be used as a 32-bit addressable array to
+ * access APIC registers.
+ */
+void apic_initialize(void)
+{
+ if ( !has_apic_support() ) {
+printf("warning: cpuid claims no APIC support - trying anyway.\n");
+ }
+
+ /*
+ * The APIC base address is a 36-bit physical address.
+ * We have identity-paging setup at the moment, which makes this simpler, but
+ * that's something to note since the variables below use virtual addresses.
+ *
+ * Bits 0-11 (inclusive) are 0, making the address page (4KiB) aligned.
+ * Bits 12-35 (inclusive) of the MSR point to the rest of the address.
+ */
+ uint64_t apic_base_msr = rdmsr(APIC_BASE_MSR);
+ amd64_apic_base = (uint32_t*) apic_base_msr;
+ amd64_apic_base = (uint32_t*) ((uintptr_t) amd64_apic_base & 0x0ff000);
+
+ /* Hardware enable the APIC just to be sure */
+ wrmsr(
+APIC_BASE_MSR,
+apic_base_msr | APIC_BASE_MSR_ENABLE,
+apic_base_msr >> 32
+ );
+
+ DBG_PRINTF("APIC is at 0x%" PRIxPTR "\n", (uintptr_t) amd64_apic_base);
+ DBG_PRINTF(
+"APIC ID at *0x%" PRIxPTR "=0x%" PRIx32 "\n",
+(uintptr_t) _apic_base[APIC_REGISTER_APICID],
+amd64_apic_base[APIC_REGISTER_APICID]
+ );
+
+ DBG_PRINTF(
+"APIC spurious vector register *0x%" PRIxPTR "=0x%" PRIx32 "\n",
+(uintptr_t) _apic_base[APIC_REGISTER_SPURIOUS],
+
[PATCH 2/5] bsps/x86_64: Reduce default RamSize to 1GiB
Simulators may not always be able to allocate 4GiB easily, and using an
artificially lower RAM may cause a broken heap.
Updates #2898.
---
bsps/x86_64/amd64/start/linkcmds | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/bsps/x86_64/amd64/start/linkcmds b/bsps/x86_64/amd64/start/linkcmds
index 46b1ccbfe7..ecb4a2b835 100644
--- a/bsps/x86_64/amd64/start/linkcmds
+++ b/bsps/x86_64/amd64/start/linkcmds
@@ -23,15 +23,15 @@ HeapSize = DEFINED(HeapSize) ? HeapSize :
RamBase = DEFINED(RamBase)? RamBase :
DEFINED(_RamBase) ? _RamBase : 0x0;
-/* XXX: Defaulting to 4GiB.
+/* XXX: Defaulting to 1GiB.
*/
RamSize = DEFINED(RamSize)? RamSize :
- DEFINED(_RamSize) ? _RamSize : 0x;
+ DEFINED(_RamSize) ? _RamSize : 0x4000;
SECTIONS
{
/* Read-only sections, merged into text segment: */
- PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x40)); . =
SEGMENT_START("text-segment", 0x40) + SIZEOF_HEADERS;
+ PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0010)); .
= SEGMENT_START("text-segment", 0x0010) + SIZEOF_HEADERS;
.interp : { *(.interp) }
.note.gnu.build-id : { *(.note.gnu.build-id) }
.hash : { *(.hash) }
--
2.18.0
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/5] bsps/x86_64: Reorganize header files and compile-options
Updates #2898.
---
bsps/x86_64/amd64/config/amd64.cfg| 3 ++
cpukit/score/cpu/x86_64/headers.am| 1 +
cpukit/score/cpu/x86_64/include/rtems/asm.h | 10
.../cpu/x86_64/include/rtems/score/cpu.h | 5 +-
.../cpu/x86_64/include/rtems/score/cpu_asm.h | 50 +++
.../cpu/x86_64/include/rtems/score/cpuimpl.h | 16 +-
.../cpu/x86_64/include/rtems/score/x86_64.h | 13 -
.../score/cpu/x86_64/x86_64-context-switch.S | 8 +--
8 files changed, 84 insertions(+), 22 deletions(-)
create mode 100644 cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
diff --git a/bsps/x86_64/amd64/config/amd64.cfg
b/bsps/x86_64/amd64/config/amd64.cfg
index 3c4492d9d3..ad861cb867 100644
--- a/bsps/x86_64/amd64/config/amd64.cfg
+++ b/bsps/x86_64/amd64/config/amd64.cfg
@@ -11,3 +11,6 @@ CPU_CFLAGS = -mno-red-zone
# way we can avoid linker-time relocation errors spawning from values being
# larger than their optimized container sizes.
CPU_CFLAGS += -mcmodel=large
+CPU_CFLAGS += -Werror=return-type
+
+LDFLAGS = -Wl,--gc-sections
diff --git a/cpukit/score/cpu/x86_64/headers.am
b/cpukit/score/cpu/x86_64/headers.am
index b3792d00b1..d23c39d99b 100644
--- a/cpukit/score/cpu/x86_64/headers.am
+++ b/cpukit/score/cpu/x86_64/headers.am
@@ -11,6 +11,7 @@ include_rtems_HEADERS += include/rtems/asm.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS =
include_rtems_score_HEADERS += include/rtems/score/cpu.h
+include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h
include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h
include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h
include_rtems_score_HEADERS += include/rtems/score/x86_64.h
diff --git a/cpukit/score/cpu/x86_64/include/rtems/asm.h
b/cpukit/score/cpu/x86_64/include/rtems/asm.h
index 36699140b7..76efc07db3 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/asm.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/asm.h
@@ -84,6 +84,16 @@
#define r14 REG (r14)
#define r15 REG (r15)
+/*
+ * Order of register usage for function arguments as per the calling convention
+ */
+#define REG_ARG0 rdi
+#define REG_ARG1 rsi
+#define REG_ARG2 rdx
+#define REG_ARG3 rcx
+#define REG_ARG4 r8
+#define REG_ARG5 r9
+
// XXX: eax, ax, etc., segment registers
/*
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
index 5c40af7647..557d11109d 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
@@ -40,6 +40,7 @@ extern "C" {
#endif
#include
+#include
#include
#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
@@ -54,7 +55,7 @@ extern "C" {
#define CPU_PROVIDES_IDLE_THREAD_BODYFALSE
#define CPU_STACK_GROWS_UP FALSE
-#define CPU_STRUCTURE_ALIGNMENT __attribute__((aligned ( 64 )))
+#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64)
#define CPU_CACHE_LINE_BYTES 64
#define CPU_MODES_INTERRUPT_MASK 0x0001
#define CPU_MAXIMUM_PROCESSORS 32
@@ -104,7 +105,7 @@ typedef struct {
uint32_t special_interrupt_register;
} CPU_Interrupt_frame;
-#endif /* ASM */
+#endif /* !ASM */
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
new file mode 100644
index 00..ac43a6366d
--- /dev/null
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018.
+ * Amaan Cheval
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_ASM_H
+#define _RTEMS_SCORE_CPU_ASM_H
+
+#if !ASM
+
+#include
+
[PATCH 0/5] [GSoC - x86_64] Add interrupts and clock driver
This patch series includes all of my remaining work so far on the x86_64 BSP. It supports: * Static paging support using 1GiB superpages * RTEMS interrupts * A fairly accurate clock driver based on the APIC timer calibrated by the PIT ticker.exe passes reliably on -O0 optimization level, and it seems like it _should_ on -O2 as well, except for the issue I've been describing on this thread: https://lists.rtems.org/pipermail/devel/2018-August/022825.html bsps/x86_64/amd64/clock/clock.c | 299 ++ bsps/x86_64/amd64/config/amd64.cfg| 3 + bsps/x86_64/amd64/headers.am | 3 + bsps/x86_64/amd64/include/apic.h | 62 bsps/x86_64/amd64/include/clock.h | 99 ++ bsps/x86_64/amd64/include/pic.h | 75 + bsps/x86_64/amd64/interrupts/idt.c| 151 + bsps/x86_64/amd64/interrupts/isr_handler.S| 191 +++ bsps/x86_64/amd64/interrupts/pic.c| 76 + bsps/x86_64/amd64/start/bspstart.c| 4 + bsps/x86_64/amd64/start/linkcmds | 6 +- bsps/x86_64/amd64/start/page.c| 172 ++ bsps/x86_64/headers.am| 9 + bsps/x86_64/include/bsp/irq.h | 46 +++ bsps/x86_64/include/libcpu/page.h | 68 c/src/lib/libbsp/x86_64/amd64/Makefile.am | 9 +- cpukit/score/cpu/x86_64/cpu.c | 17 +- cpukit/score/cpu/x86_64/headers.am| 2 + cpukit/score/cpu/x86_64/include/rtems/asm.h | 10 + .../cpu/x86_64/include/rtems/score/cpu.h | 112 +-- .../cpu/x86_64/include/rtems/score/cpu_asm.h | 104 ++ .../cpu/x86_64/include/rtems/score/cpuimpl.h | 16 +- .../cpu/x86_64/include/rtems/score/idt.h | 131 .../cpu/x86_64/include/rtems/score/x86_64.h | 13 +- .../cpu/x86_64/x86_64-context-initialize.c| 9 +- .../score/cpu/x86_64/x86_64-context-switch.S | 8 +- 26 files changed, 1636 insertions(+), 59 deletions(-) create mode 100644 bsps/x86_64/amd64/clock/clock.c create mode 100644 bsps/x86_64/amd64/include/apic.h create mode 100644 bsps/x86_64/amd64/include/clock.h create mode 100644 bsps/x86_64/amd64/include/pic.h create mode 100644 bsps/x86_64/amd64/interrupts/idt.c create mode 100644 bsps/x86_64/amd64/interrupts/isr_handler.S create mode 100644 bsps/x86_64/amd64/interrupts/pic.c create mode 100644 bsps/x86_64/amd64/start/page.c create mode 100644 bsps/x86_64/headers.am create mode 100644 bsps/x86_64/include/bsp/irq.h create mode 100644 bsps/x86_64/include/libcpu/page.h create mode 100644 cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h create mode 100644 cpukit/score/cpu/x86_64/include/rtems/score/idt.h -- 2.18.0 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
