Re: [PATCH 2/3] cpukit: Change _COMPILING_NEWLIB to _LIBC for helper functions decls

2022-06-14 Thread Chris Johns 
On 15/6/2022 2:42 am, Joel Sherrill wrote:
> This is OK. Changed in newlib here:
> 
> commit 6226bad0eafe762b811c62d1dc096bc0858b0d1a
> Author: Mike Frysinger mailto:vap...@gentoo.org>>
> Date:   Mon Nov 8 22:22:27 2021 -0500
> 
>     change _COMPILING_NEWLIB to _LIBC
>    
>     Use the same name as glibc & gnulib to indicate "newlib itself is
>     being compiled".  This also harmonizes the codebase a bit in that
>     _LIBC was already used in places instead of _COMPILING_NEWLIB.
>    
>     Building for bfin-elf, mips-elf, and x86_64-pc-cygwin produces
>     the same object code.

Thanks. I found another ...

cpukit/libcsupport/src/__gettod.c:#define _COMPILING_NEWLIB

I will update the patch.

Chris
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH 3/3] aarch64/gicv3: Remove accesses to secure registers

2022-06-14 Thread Chris Johns 
On 14/6/2022 11:44 pm, Gedare Bloom wrote:
> On Mon, Jun 13, 2022 at 7:39 PM  wrote:
>>
>> From: Chris Johns 
>>
>> ---
>>  bsps/include/dev/irq/arm-gicv3.h | 18 +++---
>>  1 file changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/bsps/include/dev/irq/arm-gicv3.h 
>> b/bsps/include/dev/irq/arm-gicv3.h
>> index 0d3ef9a1c1..a79368ebdf 100644
>> --- a/bsps/include/dev/irq/arm-gicv3.h
>> +++ b/bsps/include/dev/irq/arm-gicv3.h
>> @@ -300,12 +300,25 @@ static void gicv3_init_dist(volatile gic_dist *dist)
>>}
>>  }
>>
>> +/*
>> + * A better way to access these registers than special opcodes
>> + */
>> +#define isb() __asm __volatile("isb" : : : "memory")
>> +
>> +#define  WRITE_SPECIALREG(reg, _val)\
>> +  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
>> +
>> +#define  gic_icc_write(reg, val)\
>> +do {\
>> +  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
>> +  isb();\
>> +} while (0)
>> +
>>  static void gicv3_init_cpu_interface(uint32_t cpu_index)
>>  {
>>uint32_t sre_value = 0x7;
>>WRITE_SR(ICC_SRE, sre_value);
>>WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
>> -  WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));
> This appears unrelated?

The binary pointer effects the secure interrupts and so cannot be touched on
EL1. It traps into EL3. It makes sense to me it is protected. There is no code
in Petalinux or FreeBSD writing to this register.

>>volatile gic_redist *redist = gicv3_get_redist(cpu_index);
>>uint32_t waker = redist->icrwaker;
>> @@ -322,8 +335,7 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
>>}
>>
>>/* Enable interrupt groups 0 and 1 */
>> -  WRITE_SR(ICC_IGRPEN0, 0x1);
>> -  WRITE_SR(ICC_IGRPEN1, 0x1);
>> +  gic_icc_write(IGRPEN1, 1);
> Removed the write to IGRPEN0?

The write I replaced is touching a secure register and so traps into EL3 when
your TF-A has enabled a secure mode.

The enable is replaced with a write to the EL1 accessible register. This is how
FreeBSD does it so I copied that method rather than the binary opcode approach
which I found complicated.

You need a suitably configured TF-A to run on aarch64. I would be questioning
any TF-A that lets this code run without these changes. The Xilinx 2020.2
vck-190 build of TF-A lets our code run without this patch however 2021.2 had
tightened things. Xilinx and I looked into the history of their TF-A source and
how they build it and came to the conclusion the change in the secure mode has
come from ARM and their TF-A code.

Chris
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH 2/3] bsp/versal: Support more than 4G of RAM

2022-06-14 Thread Chris Johns 
On 15/6/2022 2:43 am, Joel Sherrill wrote:
> OK but the commit message could be a bit more enlightening. 

What about:

 bsp/versal: Make RAM base 64bit to support more than 4G of RAM

> It took me a minute to realize that all this did was change the type
> of the memory length parameter. It actually does not change any 
> lengths to > 4 GB.

Yes it is a constraint on the value and not the value.

Chris
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH 1/3] score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warning

2022-06-14 Thread Joel Sherrill 
Correct the URL in the commit message and push it.

--joel

On Mon, Jun 13, 2022 at 8:57 PM Chris Johns  wrote:

> On 14/6/2022 11:24 am, chr...@rtems.org wrote:
> > From: Chris Johns 
> >
> > The false trigger is covered in:
> >
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104657
>
> This is the link I meant to include ..
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578
>
> I will update commit and push with this link if approved.
>
> Chris
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
>
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH 2/3] bsp/versal: Support more than 4G of RAM

2022-06-14 Thread Joel Sherrill 
OK but the commit message could be a bit more enlightening.

It took me a minute to realize that all this did was change the type
of the memory length parameter. It actually does not change any
lengths to > 4 GB.

--joel

On Mon, Jun 13, 2022 at 8:39 PM  wrote:

> From: Chris Johns 
>
> ---
>  spec/build/bsps/aarch64/xilinx-versal/optramlen.yml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/optramlen.yml
> b/spec/build/bsps/aarch64/xilinx-versal/optramlen.yml
> index ebc36d3139..95347fc7e3 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/optramlen.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/optramlen.yml
> @@ -1,7 +1,7 @@
>  SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
>  actions:
>  - get-integer: null
> -- assert-uint32: null
> +- assert-uint64: null
>  - env-assign: null
>  - format-and-define: null
>  build-type: option
> --
> 2.19.1
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
>
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH 2/3] cpukit: Change _COMPILING_NEWLIB to _LIBC for helper functions decls

2022-06-14 Thread Joel Sherrill 
This is OK. Changed in newlib here:

commit 6226bad0eafe762b811c62d1dc096bc0858b0d1a
Author: Mike Frysinger 
Date:   Mon Nov 8 22:22:27 2021 -0500

change _COMPILING_NEWLIB to _LIBC

Use the same name as glibc & gnulib to indicate "newlib itself is
being compiled".  This also harmonizes the codebase a bit in that
_LIBC was already used in places instead of _COMPILING_NEWLIB.

Building for bfin-elf, mips-elf, and x86_64-pc-cygwin produces
the same object code.

On Mon, Jun 13, 2022 at 8:24 PM  wrote:

> From: Chris Johns 
>
> Updates #4662
> ---
>  cpukit/libcsupport/src/__times.c | 4 ++--
>  cpukit/posix/src/_execve.c   | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/cpukit/libcsupport/src/__times.c
> b/cpukit/libcsupport/src/__times.c
> index 629a7bc633..14625b5aae 100644
> --- a/cpukit/libcsupport/src/__times.c
> +++ b/cpukit/libcsupport/src/__times.c
> @@ -38,9 +38,9 @@
>  #endif
>
>  /*
> - *  Needed to get the prototype for this newlib helper method
> + *  Needed to get the prototype for this libc helper method
>   */
> -#define _COMPILING_NEWLIB
> +#define _LIBC
>
>  #include 
>
> diff --git a/cpukit/posix/src/_execve.c b/cpukit/posix/src/_execve.c
> index 2858d13082..63afadec43 100644
> --- a/cpukit/posix/src/_execve.c
> +++ b/cpukit/posix/src/_execve.c
> @@ -43,9 +43,9 @@
>  #endif
>
>  /*
> - *  Needed to get the prototype for this newlib helper method
> + *  Needed to get the prototype for this libc helper method
>   */
> -#define _COMPILING_NEWLIB
> +#define _LIBC
>
>  #include 
>  #include 
> --
> 2.19.1
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
>
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: Static Analysis Tools for RTEMS

2022-06-14 Thread Joel Sherrill 
On Mon, Jun 13, 2022, 8:38 PM Chris Johns  wrote:

> On 10/6/2022 12:09 am, Joel Sherrill wrote:
> > With Matthew addressing new warnings from GCC 12,
>
> I have posted some warning fixes for the arm and aarch64. They let those
> archs
> build warning free without the testsuite. I hope it helps.
>

When they are committed, the automated jobs will pick them up. I will post
of we gain or lose an issue.

>
> Chris
>
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP

2022-06-14 Thread Duc Doan 
Dear all,

I am proposing a new GPIO API for RTEMS. The current API is kind of tailored to 
some specific hardware and therefore may require some overhead to make it fit 
for others. The one I am proposing is not finished but it is aimed to be simple 
and generic. It has some opaque type structures that need to be implemented by 
BSP. The functions include initialization, configuration, reading, writing, and 
toggle. I took inspiration from the Wiring framework. I also have an example 
implementation for the STM32F4 BSP.

I would love to get feedback from all of you.

Thank you,

Duc Doan

---
 bsps/arm/stm32f4/gpio/gpio.c |  39 +++
 bsps/include/bsp/gpio2.h | 129 +++
 2 files changed, 168 insertions(+)
 create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
 create mode 100644 bsps/include/bsp/gpio2.h

diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..40aea3febd
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,39 @@
+#include 
+#include 
+#include 
+#include 
+
+struct rtems_gpio_t {
+GPIO_TypeDef *port;
+};
+
+struct rtems_gpio_pin_t {
+uint16_t pin_mask;  
+};
+
+struct rtems_gpio_config_t {
+GPIO_InitTypeDef *config;
+}
+
+__weak rtems_status_code rtems_gpio_initialize(void) {
+return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_configure(rtems_gpio_t *gpiox, 
rtems_gpio_config_t *config) {
+HAL_GPIO_Init(gpiox->port, config->config);
+return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_write_pin(rtems_gpio_t *gpiox, rtems_gpio_pin_t 
*pin, rtems_gpio_pin_state value) {
+HAL_GPIO_WritePin(gpiox->port, pin->pin_mask, value);
+return RTEMS_SUCCESSFUL;
+}
+
+rtems_gpio_pin_state rtems_gpio_read_pin(rtems_gpio_t *gpiox, rtems_gpio_pin_t 
*pin) {
+return HAL_GPIO_ReadPin(gpiox->port, pin->pin_mask);
+}
+
+rtems_status_code rtems_gpio_toggle_pin(rtems_gpio_t *gpiox, rtems_gpio_pin_t 
*pin) {
+HAL_GPIO_TogglePin(gpiox->port, pin->pin_mask);
+return RTEMS_SUCCESSFUL;
+}
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..ef10d1729a
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,129 @@
+/**
+  * @file
+  *
+  * @ingroup rtems_gpio2
+  *
+  * @brief RTEMS GPIO new API definition.
+  */
+
+ /*
+  *  Copyright (c) 2022 Duc Doan 
+  *
+  *  The license and distribution terms for this file may be
+  *  found in the file LICENSE in this distribution or at
+  *  http://www.rtems.org/license/LICENSE.
+  */
+
+#ifndef LIBBSP_SHARED_GPIO2_H
+#define LIBBSP_SHARED_GPIO2_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+  * @brief GPIO bit set and reset enumeration.
+  */
+typedef enum {
+RTEMS_GPIO_PIN_SET = 0,
+RTEMS_GPIO_PIN_RESET
+} rtems_gpio_pin_state;
+
+/**
+  * @brief Opaque type for a GPIO object.
+  *To be implemented by BSP.
+  * 
+  * @details This could represent the unit that owns GPIO pins. 
+  *  For example, it would be a port for ARM Cortex-M.
+  */
+typedef struct rtems_gpio_t rtems_gpio_t;
+
+/**
+  * @brief Opaque type for a GPIO pin object.
+  *To be implemented by BSP.
+  */
+typedef struct rtems_gpio_pin_t rtems_gpio_pin_t;
+
+/**
+  * @brief Opaque type for configuration of a GPIO object.
+  *To be implemented by BSP.
+  */
+typedef struct rtems_gpio_config_t;
+
+/** @} */
+
+/**
+  * @name GPIO Functions
+  *
+  * @{
+  */
+
+/**
+  * @brief Initialization for GPIO. To be implemented by User Application.
+  *
+  * @retval RTEMS_SUCCESSFUL GPIO successfully initialized.
+  * @retval RTEMS_UNSATISFIED Could not initialize GPIO object.
+  */
+extern rtems_status_code rtems_gpio_initialize(void);
+
+/**
+  * @brief Configures a GPIO object.
+  *To be implemented by BSP.
+  *
+  * @param[in] gpiox The GPIO object to be configured.
+  * @param[in] config The GPIO configuration object.
+  *
+  * @retval RTEMS_SUCCESSFUL GPIO configured successfully.
+  * @retval RTEMS_UNSATISFIED Could not configure GPIO object.
+  */
+extern rtems_status_code rtems_gpio_configure(rtems_gpio_t *gpiox, 
rtems_gpio_config_t *config);
+
+/**
+  * @brief Writes a digital value to a pin/pins.
+  *
+  * @param[in] gpiox The GPIO object that owns the pin(s).
+  * @param[in] pin The GPIO pin number or pin mask to be written.
+  * @param[in] value The state to be written to the pin(s).
+  *
+  * @retval RTEMS_SUCCESSFUL Pin successfully written.
+  * @retval RTEMS_UNSATISFIED Could not write to pin(s).
+  */
+extern rtems_status_code rtems_gpio_write_pin(rtems_gpio_t *gpiox, 
rtems_gpio_pin_t *pin, rtems_gpio_pin_state value);
+
+/**
+  * @brief Reads the digital value of a pin/pins.
+  *
+  * @param[in] gpiox The GPIO object that owns the pin(s).
+  * @param[in] pin The GPIO pin(s) to be read.
+  *
+  * @retval The state of the pin(s).
+  */
+extern

Re: [PATCH 3/3] aarch64/gicv3: Remove accesses to secure registers

2022-06-14 Thread Gedare Bloom 
On Mon, Jun 13, 2022 at 7:39 PM  wrote:
>
> From: Chris Johns 
>
> ---
>  bsps/include/dev/irq/arm-gicv3.h | 18 +++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/bsps/include/dev/irq/arm-gicv3.h 
> b/bsps/include/dev/irq/arm-gicv3.h
> index 0d3ef9a1c1..a79368ebdf 100644
> --- a/bsps/include/dev/irq/arm-gicv3.h
> +++ b/bsps/include/dev/irq/arm-gicv3.h
> @@ -300,12 +300,25 @@ static void gicv3_init_dist(volatile gic_dist *dist)
>}
>  }
>
> +/*
> + * A better way to access these registers than special opcodes
> + */
> +#define isb() __asm __volatile("isb" : : : "memory")
> +
> +#define  WRITE_SPECIALREG(reg, _val)\
> +  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
> +
> +#define  gic_icc_write(reg, val)\
> +do {\
> +  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
> +  isb();\
> +} while (0)
> +
>  static void gicv3_init_cpu_interface(uint32_t cpu_index)
>  {
>uint32_t sre_value = 0x7;
>WRITE_SR(ICC_SRE, sre_value);
>WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
> -  WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));
This appears unrelated?

>
>volatile gic_redist *redist = gicv3_get_redist(cpu_index);
>uint32_t waker = redist->icrwaker;
> @@ -322,8 +335,7 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
>}
>
>/* Enable interrupt groups 0 and 1 */
> -  WRITE_SR(ICC_IGRPEN0, 0x1);
> -  WRITE_SR(ICC_IGRPEN1, 0x1);
> +  gic_icc_write(IGRPEN1, 1);
Removed the write to IGRPEN0?

>WRITE_SR(ICC_CTLR, 0x0);
>  }
>
> --
> 2.19.1
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH rtems] bsps/atsam: Fix type of options (part 2)

2022-06-14 Thread Christian MAUDERER 

Thanks. I pushed it.

Am 13.06.22 um 19:37 schrieb Joel Sherrill:

Fixes build issues I reported. Please push.

--joel

On Mon, Jun 13, 2022 at 2:18 AM Christian Mauderer 
> wrote:


The patch "bsps/atsam: Fix type of options" missed to adapt some parts
of the yml. With that a custom value works well. But if no value is set,
configure doesn't fall back to the default value but instead just causes
an error. This patch fixes that.
---
  spec/build/bsps/arm/atsam/optconidx.yml  | 3 ++-
  spec/build/bsps/arm/atsam/optcontype.yml | 3 ++-
  2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/spec/build/bsps/arm/atsam/optconidx.yml
b/spec/build/bsps/arm/atsam/optconidx.yml
index 1c0723c594..d58d75e4aa 100644
--- a/spec/build/bsps/arm/atsam/optconidx.yml
+++ b/spec/build/bsps/arm/atsam/optconidx.yml
@@ -1,7 +1,7 @@
  SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
  actions:
  - get-integer: null
-- define-condition: null
+- define: null
  build-type: option
  copyrights:
  - Copyright (C) 2020 embedded brains GmbH
(http://www.embedded-brains.de )
@@ -10,6 +10,7 @@ default-by-variant: []
  description: |
    device index for /dev/console (default 1, e.g. USART1)
  enabled-by: true
+format: '{}'
  links: []
  name: ATSAM_CONSOLE_DEVICE_INDEX
  type: build
diff --git a/spec/build/bsps/arm/atsam/optcontype.yml
b/spec/build/bsps/arm/atsam/optcontype.yml
index fd0daa8999..6846fed5f2 100644
--- a/spec/build/bsps/arm/atsam/optcontype.yml
+++ b/spec/build/bsps/arm/atsam/optcontype.yml
@@ -1,7 +1,7 @@
  SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
  actions:
  - get-integer: null
-- define-condition: null
+- define: null
  build-type: option
  copyrights:
  - Copyright (C) 2020 embedded brains GmbH
(http://www.embedded-brains.de )
@@ -10,6 +10,7 @@ default-by-variant: []
  description: |
    device type for /dev/console, use 0 for USART and 1 for UART
(default USART)
  enabled-by: true
+format: '{}'
  links: []
  name: ATSAM_CONSOLE_DEVICE_TYPE
  type: build
-- 
2.35.3




--

embedded brains GmbH
Herr Christian MAUDERER
Dornierstr. 4
82178 Puchheim
Germany
email:  christian.maude...@embedded-brains.de
phone:  +49-89-18 94 741 - 18
mobile: +49-176-152 206 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel