[PATCH v6] docs/user: add docs for riscv/kendrytek210 BSP variant
This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. V5 cleaned up the text to be no more than 80 characters per line. V6 applied word wrap to paragraphs and replaced hard coded RTEMS major versions with macros. Closes #4876 --- user/bsps/bsps-riscv.rst | 240 ++- 1 file changed, 188 insertions(+), 52 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 41f369f..b4bdf7b 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -8,7 +8,8 @@ riscv (RISC-V) riscv = -This BSP offers 12 variants: +**Each variant in this first group corresponds to a GCC multilib option with +different RISC-V standard extensions.** * rv32i @@ -30,23 +31,26 @@ This BSP offers 12 variants: * rv64imafdc -* frdme310arty +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have +medany code model by default, while rv32 BSPs are medlow. The reason is that +RV32 medlow can access the entire 32-bit address space, while RV64 medlow can +only access addresses below 0x8000. With RV64 medany, it's possible to +perform accesses above 0x8000. The BSP must be started in machine mode. -* mpfs64imafdc +The reference platforms for the rv* variants include the QEMU `virt` and +`spike` machines and the Spike RISC-V ISA simulator. -Each rv* variant corresponds to a GCC multilib. A particular variant reflects an -ISA with ABI and code model choice. All rv64 BSPs have medany code model by -default, while rv32 BSPs are medlow. The reason is that RV32 medlow can access -the entire 32-bit address space, while RV64 medlow can only access addresses -below 0x8000. With RV64 medany, it's possible to perform accesses above -0x8000. +**The BSP also provides the following variants for specific hardware targets:** -The BSP must be started im machine mode. +* frdme310arty - The reference platform for this variant is the Arty FPGA board + with the SiFive Freedom E310 reference design. -The reference platform for this BSP is the QEMU `virt` machine. +* mpfs64imafdc - The reference platform for this variant is the Microchip + PolarFire SoC Icicle Kit. + +* kendrytek210 - The reference platform for this variant is the Kendryte K210 + SoC on the Sipeed MAiX BiT or Maixduino board. -The reference platform for the mpfs64imafdc BSP variant is the Microchip -PolarFire SoC Icicle Kit. Build Configuration Options --- @@ -77,33 +81,41 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. The path to the header file containing the device tree blob. ``BSP_CONSOLE_BAUD`` -The default baud for console driver devices (default 115200). +The default baud for console driver devices (default is 115200). ``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` The maximum number of external interrupts supported by the BSP (default - 64). + is 64). ``RISCV_ENABLE_HTIF_SUPPORT`` Enable the Host/Target Interface (HTIF) support (enabled by default). ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` - The maximum number of NS16550 devices supported by the console driver (2 - by default). + The maximum number of NS16550 devices supported by the console driver + (default is 2). + +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` + Enable the SiFive console UART (disabled by default). ``RISCV_RAM_REGION_BEGIN`` - The begin of the RAM region for linker command file (default is 0x8000). + The begin of the RAM region for linker command file + (default is 0x8000). ``RISCV_RAM_REGION_SIZE`` The size of the RAM region for linker command file (default 64MiB). ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` Enables support sifive Freedom E310 Arty board if defined to a non-zero - value,otherwise it is disabled (disabled by default) + value,otherwise it is disabled (disabled by default). ``RISCV_ENABLE_MPFS_SUPPORT`` Enables support Microchip PolarFire SoC if defined to a non-zero value, otherwise it is disabled (disabled by default). +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` + Enables support for the Kendtryte K210 SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + ``RISCV_BOOT_HARTID`` The boot hartid (processor number) of risc-v cpu by default 0. @@ -123,15 +135,15 @@ The clock driver uses
Re: [PATCH rtems-lwip] rtemslwip/xil_shims: Perform flush with invalidate
On 31/3/2023 8:13 am, Kinsey Moore wrote:
> Xilinx wrote their A53 HAL with the assumption that the CPU did not
> support cache invalidation without a flush, so the flush and
> invalidation functions were combined and all range invalidations are
> promoted to flush/invalidate. The implementation written for lwIP was
> written to the original intent of the function and thus was not flushing
> in some cases when it needed to. This resolves that issue which prevents
> DMA transmit errors in some cases.
> ---
> rtemslwip/zynqmp/xil_shims.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/rtemslwip/zynqmp/xil_shims.c b/rtemslwip/zynqmp/xil_shims.c
> index 2eda0c5..1b1b3cf 100644
> --- a/rtemslwip/zynqmp/xil_shims.c
> +++ b/rtemslwip/zynqmp/xil_shims.c
> @@ -102,7 +102,12 @@ void XScuGic_DisableIntr ( u32 DistBaseAddress, u32
> Int_Id )
>rtems_interrupt_vector_disable( Int_Id );
> }
>
> +/*
> + * The Xilinx code was written such that it assumed there was no
> invalidate-only
> + * functionality on A53 cores. This function must flush and invalidate
> because
> + * of how they mapped things.
> + */
> void Xil_DCacheInvalidateRange( INTPTR adr, INTPTR len )
> {
> - rtems_cache_invalidate_multiple_data_lines( (const void *) adr, len );
> + rtems_cache_flush_multiple_data_lines( (const void *) adr, len );
> }
Does the Xilinx code use Xil_DCacheInvalidateRange in any DMA receive paths? If
it does is this change correct as the invalidate has been removed?
Chris
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Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
On 4/4/2023 12:55 am, Alan Cudmore wrote: > Hi Chris, > Sorry I should have read that and formatted my changes correctly. I submitted > a > v5 patch, but as I sent it, I realized that there are a couple of places where > the RTEMS version macro can be embedded rather than hard-coding "6". I should > have taken more time and avoided flooding the mailing list with extra > traffic. - > But I'm much better at this process now :) > Later today, I'll send a v6 patch with the rtems version macros. Thanks for doing this and the contribution. It is appreciated. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
I submitted a v4 patch for the user/bsps/bsps-riscv.rst page. I improved the instructions for running on Renode by providing a .resc file that would work, rather than modifying an existing script that was used to run Linux. This should work until I have some time to figure out why the 'SetSerialExecution True' keeps ticker from working. Given that defining CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR also works, this seems like a race condition between RTEMS and renode. I don't notice this on any of the physical boards I have tested. I don't understand the implications of telling the clock driver to only use the boot CPU, so I would prefer to leave that alone for now. Thanks, Alan On Sat, Apr 1, 2023 at 11:05 PM Alan Cudmore wrote: > Update on K210/ticker on Renode: > If I define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR in the RISC-V BSP, > ticker works on the unmodified .resc file. > Alan > > On Sat, Apr 1, 2023 at 8:17 PM Alan Cudmore > wrote: > >> Hi Hesham, >> I found a difference between the .resc file I use to run single tests and >> the .resc file that the renode-test uses. >> The resc file where ticker.exe fails has this extra statement: >> $ex='machine SetSerialExecution True' >> If I comment that out, ticker runs on Renode. >> I couldn't find that in the documentation, so I'm going to have to search >> the renode code to see what it does. I'm pretty sure I used to run >> ticker.exe by itself without commenting out that line. >> It's odd because a number of other examples work with the statement like >> smp08.exe, unlimited.exe, hello.exe. >> >> For reference, my renode-test setup for the K210 is here: >> https://github.com/alanc98/k210-rtems-test >> Note that if you run this, the rki test will fail unless you remove the >> last test or build an RKI image for the k210: >> https://github.com/alanc98/rki2/tree/rtems6 >> >> Alan >> >> >> On Sat, Apr 1, 2023 at 6:13 PM Alan Cudmore >> wrote: >> >>> Interesting - I get the same error when I run ticker on renode now. I >>> just tried it on a board and it works. >>> It also still passes the renode-test that I run, which includes ticker >>> ticker along with a dozen other tests. I'll look into why this does not >>> work right now. >>> Thanks, >>> Alan >>> >>> >>> On Sat, Apr 1, 2023 at 5:32 PM Hesham Almatary >>> wrote: >>> Thanks Alan! It Looks good to me. I'd appreciate your help with running on the simulator. I followed your documentation in this patch, but ticker seems to fatal error as follows: "*** FATAL *** fatal source: 6 (RTEMS_FATAL_SOURCE_BSP) CPU: 0 fatal code: 3342 (0x0d0e) RTEMS version: 6.0.0.4021b87e002a094fb0d8ddd099cb8483d6986c8b RTEMS tools: 12.2.1 20221121 (RTEMS 6, RSB 65f83cf973d6f1f8974ea1818e653753b83eaea8-modified, Newlib b9898fc) executing thread ID: 0x09010001 executing thread name: IDLE" This is the log from Renode: 22:28:53.3268 [INFO] Loaded monitor commands from: /home/hesham/Downloads/renode_portable/scripts/monitor.py 22:28:58.0077 [INFO] Including script: /home/hesham/Downloads/renode_portable/scripts/single-node/kendryte_k210.resc 22:28:58.0181 [INFO] System bus created. 22:28:58.8437 [INFO] sysbus: Loading segment of 68760 bytes length at 0x8000. 22:28:58.8568 [INFO] sysbus: Loading segment of 4096 bytes length at 0x80010C98. 22:28:58.8571 [INFO] sysbus: Loading segment of 6217728 bytes length at 0x80012000. 22:28:58.8783 [INFO] cpu1: Setting PC value to 0x8000. 22:28:58.8793 [INFO] cpu2: Setting PC value to 0x8000. 22:28:58.9003 [INFO] machine-0: Machine started. 22:28:58.9704 [WARNING] plic: Unhandled write to offset 0x20, value 0x0. 22:28:58.9790 [WARNING] sysbus: [cpu1: 0x80009FE0] (tag: 'SYSCTL/clk_sel0') ReadDoubleWord from non existing peripheral at 0x50440020, returning 0x. On Sat, 1 Apr 2023 at 21:22, Alan Cudmore wrote: > > Hi Hesham, > I applied your suggestions and sent a v3 patch. > Thanks for the review, > Alan > > > On Sat, Apr 1, 2023 at 1:43 PM Hesham Almatary < heshamelmat...@gmail.com> wrote: >> >> On Fri, 31 Mar 2023 at 17:15, Alan Cudmore wrote: >> > >> > This patch adds the documentation for building and running RTEMS on the Kendryte K210 >> > RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants >> > then the specific hardware targets. In addition a couple of errors were fixed for the >> > generic QEMU commands. >> > >> > V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink >> > to renode.io install instructions. >> > >> > Closes #4876 >> > --- >> > user/bsps/bsps-riscv.rst | 116 ++- >> > 1 file changed, 103 insertions(+), 13
GSoC Proposal Draft - Improve Raspberry Pi 4 BSP
I have drafted my GSoC proposal and uploaded it to Google Docs. You can leave suggestions as comments in the document. https://docs.google.com/document/d/1dL5zl_iSYeyx6ZoOpKjy-CkLh_OvgGDJvblrPH5q6rg/edit?usp=sharing I apologize for not giving you much time for this review. Regards, Utkarsh ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Hi Alan, We have a standard for the documentation source: https://git.rtems.org/rtems-docs/tree/README.txt#n469 Please note the line length. That can be relaxed when pasting in output but we need the written text to be within the bounds. Thanks Chris On 1/4/2023 3:15 am, Alan Cudmore wrote: > This patch adds the documentation for building and running RTEMS on the > Kendryte K210 > RISC-V SoC. The generic riscv introducion was re-arranged to list the > multilib variants > then the specific hardware targets. In addition a couple of errors were fixed > for the > generic QEMU commands. > > V2 corrected a typo, expanded K210 Console UART parameters, and addded a > hyperlink > to renode.io install instructions. > > Closes #4876 > --- > user/bsps/bsps-riscv.rst | 116 ++- > 1 file changed, 103 insertions(+), 13 deletions(-) > > diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst > index 41f369f..af79e6e 100644 > --- a/user/bsps/bsps-riscv.rst > +++ b/user/bsps/bsps-riscv.rst > @@ -8,7 +8,7 @@ riscv (RISC-V) > riscv > = > > -This BSP offers 12 variants: > +**This BSP offers 10 variants, each corresponding to a GCC multilib:** > > * rv32i > > @@ -30,23 +30,22 @@ This BSP offers 12 variants: > > * rv64imafdc > > -* frdme310arty > - > -* mpfs64imafdc > - > -Each rv* variant corresponds to a GCC multilib. A particular variant > reflects an > -ISA with ABI and code model choice. All rv64 BSPs have medany code model by > +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs > have medany code model by > default, while rv32 BSPs are medlow. The reason is that RV32 medlow can > access > the entire 32-bit address space, while RV64 medlow can only access addresses > below 0x8000. With RV64 medany, it's possible to perform accesses above > -0x8000. > +0x8000. The BSP must be started in machine mode. > + > +The reference platform for the rv* variants is the QEMU `virt` machine. > + > +**The BSP also provides the following 3 variants for specific hardware > targets:** > > -The BSP must be started im machine mode. > +* frdme310arty - The reference platform for this variant is the Arty FPGA > board with the Sifive Freedom E310 reference design. > > -The reference platform for this BSP is the QEMU `virt` machine. > +* mpfs64imafdc - The reference platform for this variant is the Microchip > PolarFire SoC Icicle Kit. > + > +* kendrytek210 - The reference platform for this variant is the Kendryte > K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. > > -The reference platform for the mpfs64imafdc BSP variant is the Microchip > -PolarFire SoC Icicle Kit. > > Build Configuration Options > --- > @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be used to > inspect the values. > The maximum number of NS16550 devices supported by the console driver (2 > by default). > > +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` > + Enable the Sifive console UART (disabled by default) > + > ``RISCV_RAM_REGION_BEGIN`` > The begin of the RAM region for linker command file (default is > 0x8000). > > @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be used > to inspect the values. > Enables support Microchip PolarFire SoC if defined to a non-zero > value, otherwise it is disabled (disabled by default). > > +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` > + Enables support for the Kendtryte K210 SoC if defined to a non-zero > + value, otherwise it is disabled (disabled by default). > + > ``RISCV_BOOT_HARTID`` > The boot hartid (processor number) of risc-v cpu by default 0. > > @@ -131,7 +137,7 @@ The console driver supports devices compatible to > > * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). > > -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). > +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). This > console driver is used by the frdme310arty and kendrytek210 BSP variants. > > They are initialized according to the device tree. The console driver does > not > configure the pins or peripheral clocks. The console device is selected > @@ -145,11 +151,13 @@ and spike machines. For instance, to run the > ``rv64imafdc`` BSP with the > following "config.ini" file. > > .. code-block:: none > + > [riscv/rv64imafdc] > > Run the following QEMU command. > > .. code-block:: shell > + > $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE > $ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE > > @@ -160,11 +168,13 @@ For instance, to run the ``rv64imafdc`` BSP with the > following > "config.ini" file. > > .. code-block:: none > + > [riscv/rv64imafdc] > > Run the following Spike command. > > .. code-block:: shell > + > $ spike --isa=rv64imafdc $RTEMS_EXE > > Unlike QEMU, Spike
[PATCH v4] docs/user: add docs for riscv/kendrytek210 BSP variant
This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. Closes #4876 --- user/bsps/bsps-riscv.rst | 136 +++ 1 file changed, 123 insertions(+), 13 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 41f369f..8a27d62 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -8,7 +8,7 @@ riscv (RISC-V) riscv = -This BSP offers 12 variants: +**Each variant in this first group corresponds to a GCC multilib option with different RISC-V standard extensions.** * rv32i @@ -30,23 +30,22 @@ This BSP offers 12 variants: * rv64imafdc -* frdme310arty - -* mpfs64imafdc - -Each rv* variant corresponds to a GCC multilib. A particular variant reflects an -ISA with ABI and code model choice. All rv64 BSPs have medany code model by +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have medany code model by default, while rv32 BSPs are medlow. The reason is that RV32 medlow can access the entire 32-bit address space, while RV64 medlow can only access addresses below 0x8000. With RV64 medany, it's possible to perform accesses above -0x8000. +0x8000. The BSP must be started in machine mode. + +The reference platforms for the rv* variants include the QEMU `virt` and `spike` machines and the Spike RISC-V ISA simulator. + +**The BSP also provides the following 3 variants for specific hardware targets:** -The BSP must be started im machine mode. +* frdme310arty - The reference platform for this variant is the Arty FPGA board with the SiFive Freedom E310 reference design. -The reference platform for this BSP is the QEMU `virt` machine. +* mpfs64imafdc - The reference platform for this variant is the Microchip PolarFire SoC Icicle Kit. + +* kendrytek210 - The reference platform for this variant is the Kendryte K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. -The reference platform for the mpfs64imafdc BSP variant is the Microchip -PolarFire SoC Icicle Kit. Build Configuration Options --- @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. The maximum number of NS16550 devices supported by the console driver (2 by default). +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` + Enable the SiFive console UART (disabled by default) + ``RISCV_RAM_REGION_BEGIN`` The begin of the RAM region for linker command file (default is 0x8000). @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. Enables support Microchip PolarFire SoC if defined to a non-zero value, otherwise it is disabled (disabled by default). +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` + Enables support for the Kendtryte K210 SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + ``RISCV_BOOT_HARTID`` The boot hartid (processor number) of risc-v cpu by default 0. @@ -131,7 +137,7 @@ The console driver supports devices compatible to * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). This console driver is used by the frdme310arty and kendrytek210 BSP variants. They are initialized according to the device tree. The console driver does not configure the pins or peripheral clocks. The console device is selected @@ -145,11 +151,13 @@ and spike machines. For instance, to run the ``rv64imafdc`` BSP with the following "config.ini" file. .. code-block:: none + [riscv/rv64imafdc] Run the following QEMU command. .. code-block:: shell + $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE $ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE @@ -160,11 +168,13 @@ For instance, to run the ``rv64imafdc`` BSP with the following "config.ini" file. .. code-block:: none + [riscv/rv64imafdc] Run the following Spike command. .. code-block:: shell + $ spike --isa=rv64imafdc $RTEMS_EXE Unlike QEMU, Spike supports enabling/disabling a subset of the imafdc extensions @@ -277,6 +287,106 @@ Serial terminal UART1 displays the SMP example messages *** END OF TEST SMP 1 *** +Kendryte K210 +- + +The Kendryte K210 SoC is a dual core
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Hi Chris, Sorry I should have read that and formatted my changes correctly. I submitted a v5 patch, but as I sent it, I realized that there are a couple of places where the RTEMS version macro can be embedded rather than hard-coding "6". I should have taken more time and avoided flooding the mailing list with extra traffic. - But I'm much better at this process now :) Later today, I'll send a v6 patch with the rtems version macros. Thanks, Alan On Sun, Apr 2, 2023 at 10:14 PM Chris Johns wrote: > Hi Alan, > > We have a standard for the documentation source: > > https://git.rtems.org/rtems-docs/tree/README.txt#n469 > > Please note the line length. That can be relaxed when pasting in output > but we > need the written text to be within the bounds. > > Thanks > Chris > > On 1/4/2023 3:15 am, Alan Cudmore wrote: > > This patch adds the documentation for building and running RTEMS on the > Kendryte K210 > > RISC-V SoC. The generic riscv introducion was re-arranged to list the > multilib variants > > then the specific hardware targets. In addition a couple of errors were > fixed for the > > generic QEMU commands. > > > > V2 corrected a typo, expanded K210 Console UART parameters, and addded a > hyperlink > > to renode.io install instructions. > > > > Closes #4876 > > --- > > user/bsps/bsps-riscv.rst | 116 ++- > > 1 file changed, 103 insertions(+), 13 deletions(-) > > > > diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst > > index 41f369f..af79e6e 100644 > > --- a/user/bsps/bsps-riscv.rst > > +++ b/user/bsps/bsps-riscv.rst > > @@ -8,7 +8,7 @@ riscv (RISC-V) > > riscv > > = > > > > -This BSP offers 12 variants: > > +**This BSP offers 10 variants, each corresponding to a GCC multilib:** > > > > * rv32i > > > > @@ -30,23 +30,22 @@ This BSP offers 12 variants: > > > > * rv64imafdc > > > > -* frdme310arty > > - > > -* mpfs64imafdc > > - > > -Each rv* variant corresponds to a GCC multilib. A particular variant > reflects an > > -ISA with ABI and code model choice. All rv64 BSPs have medany code > model by > > +Each variant reflects an ISA with ABI and code model choice. All rv64 > BSPs have medany code model by > > default, while rv32 BSPs are medlow. The reason is that RV32 medlow can > access > > the entire 32-bit address space, while RV64 medlow can only access > addresses > > below 0x8000. With RV64 medany, it's possible to perform accesses > above > > -0x8000. > > +0x8000. The BSP must be started in machine mode. > > + > > +The reference platform for the rv* variants is the QEMU `virt` machine. > > + > > +**The BSP also provides the following 3 variants for specific hardware > targets:** > > > > -The BSP must be started im machine mode. > > +* frdme310arty - The reference platform for this variant is the Arty > FPGA board with the Sifive Freedom E310 reference design. > > > > -The reference platform for this BSP is the QEMU `virt` machine. > > +* mpfs64imafdc - The reference platform for this variant is the > Microchip PolarFire SoC Icicle Kit. > > + > > +* kendrytek210 - The reference platform for this variant is the > Kendryte K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. > > > > -The reference platform for the mpfs64imafdc BSP variant is the Microchip > > -PolarFire SoC Icicle Kit. > > > > Build Configuration Options > > --- > > @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be > used to inspect the values. > > The maximum number of NS16550 devices supported by the console > driver (2 > > by default). > > > > +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` > > + Enable the Sifive console UART (disabled by default) > > + > > ``RISCV_RAM_REGION_BEGIN`` > > The begin of the RAM region for linker command file (default is > 0x8000). > > > > @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be > used to inspect the values. > > Enables support Microchip PolarFire SoC if defined to a non-zero > > value, otherwise it is disabled (disabled by default). > > > > +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` > > + Enables support for the Kendtryte K210 SoC if defined to a non-zero > > + value, otherwise it is disabled (disabled by default). > > + > > ``RISCV_BOOT_HARTID`` > > The boot hartid (processor number) of risc-v cpu by default 0. > > > > @@ -131,7 +137,7 @@ The console driver supports devices compatible to > > > > * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). > > > > -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). > > +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). > This console driver is used by the frdme310arty and kendrytek210 BSP > variants. > > > > They are initialized according to the device tree. The console driver > does not > > configure the pins or peripheral clocks. The console device is selected > > @@ -145,11 +151,13 @@ and spike
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Thanks Alan for investigating this issue and following up with the updates. It's fine to leave it for now, perhaps even report it to Renode if we think it's a problem with their simulator or something. On Sun, 2 Apr 2023 at 17:22, Alan Cudmore wrote: > > I submitted a v4 patch for the user/bsps/bsps-riscv.rst page. > I improved the instructions for running on Renode by providing a .resc file > that would work, rather than modifying an existing script that was used to > run Linux. > > This should work until I have some time to figure out why the > 'SetSerialExecution True' keeps ticker from working. Given that defining > CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR also works, this seems like a race > condition between RTEMS and renode. I don't notice this on any of the > physical boards I have tested. > I don't understand the implications of telling the clock driver to only use > the boot CPU, so I would prefer to leave that alone for now. > > Thanks, > Alan > > > On Sat, Apr 1, 2023 at 11:05 PM Alan Cudmore wrote: >> >> Update on K210/ticker on Renode: >> If I define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR in the RISC-V BSP, ticker >> works on the unmodified .resc file. >> Alan >> >> On Sat, Apr 1, 2023 at 8:17 PM Alan Cudmore wrote: >>> >>> Hi Hesham, >>> I found a difference between the .resc file I use to run single tests and >>> the .resc file that the renode-test uses. >>> The resc file where ticker.exe fails has this extra statement: >>> $ex='machine SetSerialExecution True' >>> If I comment that out, ticker runs on Renode. >>> I couldn't find that in the documentation, so I'm going to have to search >>> the renode code to see what it does. I'm pretty sure I used to run >>> ticker.exe by itself without commenting out that line. >>> It's odd because a number of other examples work with the statement like >>> smp08.exe, unlimited.exe, hello.exe. >>> >>> For reference, my renode-test setup for the K210 is here: >>> https://github.com/alanc98/k210-rtems-test >>> Note that if you run this, the rki test will fail unless you remove the >>> last test or build an RKI image for the k210: >>> https://github.com/alanc98/rki2/tree/rtems6 >>> >>> Alan >>> >>> >>> On Sat, Apr 1, 2023 at 6:13 PM Alan Cudmore wrote: Interesting - I get the same error when I run ticker on renode now. I just tried it on a board and it works. It also still passes the renode-test that I run, which includes ticker ticker along with a dozen other tests. I'll look into why this does not work right now. Thanks, Alan On Sat, Apr 1, 2023 at 5:32 PM Hesham Almatary wrote: > > Thanks Alan! It Looks good to me. I'd appreciate your help with > running on the simulator. I followed your documentation in this patch, > but ticker seems to fatal error as follows: > > "*** FATAL *** > fatal source: 6 (RTEMS_FATAL_SOURCE_BSP) > CPU: 0 > fatal code: 3342 (0x0d0e) > RTEMS version: 6.0.0.4021b87e002a094fb0d8ddd099cb8483d6986c8b > RTEMS tools: 12.2.1 20221121 (RTEMS 6, RSB > 65f83cf973d6f1f8974ea1818e653753b83eaea8-modified, Newlib b9898fc) > executing thread ID: 0x09010001 > executing thread name: IDLE" > > This is the log from Renode: > > 22:28:53.3268 [INFO] Loaded monitor commands from: > /home/hesham/Downloads/renode_portable/scripts/monitor.py > 22:28:58.0077 [INFO] Including script: > /home/hesham/Downloads/renode_portable/scripts/single-node/kendryte_k210.resc > 22:28:58.0181 [INFO] System bus created. > 22:28:58.8437 [INFO] sysbus: Loading segment of 68760 bytes length at > 0x8000. > 22:28:58.8568 [INFO] sysbus: Loading segment of 4096 bytes length at > 0x80010C98. > 22:28:58.8571 [INFO] sysbus: Loading segment of 6217728 bytes length > at 0x80012000. > 22:28:58.8783 [INFO] cpu1: Setting PC value to 0x8000. > 22:28:58.8793 [INFO] cpu2: Setting PC value to 0x8000. > 22:28:58.9003 [INFO] machine-0: Machine started. > 22:28:58.9704 [WARNING] plic: Unhandled write to offset 0x20, value > 0x0. > 22:28:58.9790 [WARNING] sysbus: [cpu1: 0x80009FE0] (tag: > 'SYSCTL/clk_sel0') ReadDoubleWord from non existing peripheral at > 0x50440020, returning 0x. > > > On Sat, 1 Apr 2023 at 21:22, Alan Cudmore wrote: > > > > Hi Hesham, > > I applied your suggestions and sent a v3 patch. > > Thanks for the review, > > Alan > > > > > > On Sat, Apr 1, 2023 at 1:43 PM Hesham Almatary > > wrote: > >> > >> On Fri, 31 Mar 2023 at 17:15, Alan Cudmore > >> wrote: > >> > > >> > This patch adds the documentation for building and running RTEMS on > >> > the Kendryte K210 > >> > RISC-V SoC. The generic riscv introducion was re-arranged to list > >> > the multilib variants > >> > then the specific hardware targets. In addition a couple of errors
[PATCH v5] docs/user: add docs for riscv/kendrytek210 BSP variant
This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. V5 cleaned up the text to be no more than 80 characters per line. Closes #4876 --- user/bsps/bsps-riscv.rst | 182 ++- 1 file changed, 159 insertions(+), 23 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 41f369f..aac2f7c 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -8,7 +8,8 @@ riscv (RISC-V) riscv = -This BSP offers 12 variants: +**Each variant in this first group corresponds to a GCC multilib option with +different RISC-V standard extensions.** * rv32i @@ -30,23 +31,26 @@ This BSP offers 12 variants: * rv64imafdc -* frdme310arty +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have +medany code model by default, while rv32 BSPs are medlow. The reason is that +RV32 medlow can access the entire 32-bit address space, while RV64 medlow can +only access addresses below 0x8000. With RV64 medany, it's possible to +perform accesses above 0x8000. The BSP must be started in machine mode. -* mpfs64imafdc +The reference platforms for the rv* variants include the QEMU `virt` and `spike` +machines and the Spike RISC-V ISA simulator. -Each rv* variant corresponds to a GCC multilib. A particular variant reflects an -ISA with ABI and code model choice. All rv64 BSPs have medany code model by -default, while rv32 BSPs are medlow. The reason is that RV32 medlow can access -the entire 32-bit address space, while RV64 medlow can only access addresses -below 0x8000. With RV64 medany, it's possible to perform accesses above -0x8000. +**The BSP also provides the following variants for specific hardware targets:** -The BSP must be started im machine mode. +* frdme310arty - The reference platform for this variant is the Arty FPGA board + with the SiFive Freedom E310 reference design. -The reference platform for this BSP is the QEMU `virt` machine. +* mpfs64imafdc - The reference platform for this variant is the Microchip + PolarFire SoC Icicle Kit. + +* kendrytek210 - The reference platform for this variant is the Kendryte K210 + SoC on the Sipeed MAiX Bit or MAiXDuino board. -The reference platform for the mpfs64imafdc BSP variant is the Microchip -PolarFire SoC Icicle Kit. Build Configuration Options --- @@ -77,33 +81,41 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. The path to the header file containing the device tree blob. ``BSP_CONSOLE_BAUD`` -The default baud for console driver devices (default 115200). +The default baud for console driver devices (default is 115200). ``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` The maximum number of external interrupts supported by the BSP (default - 64). + is 64). ``RISCV_ENABLE_HTIF_SUPPORT`` Enable the Host/Target Interface (HTIF) support (enabled by default). ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` - The maximum number of NS16550 devices supported by the console driver (2 - by default). + The maximum number of NS16550 devices supported by the console driver + (default is 2). + +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` + Enable the SiFive console UART (disabled by default). ``RISCV_RAM_REGION_BEGIN`` - The begin of the RAM region for linker command file (default is 0x8000). + The begin of the RAM region for linker command file + (default is 0x8000). ``RISCV_RAM_REGION_SIZE`` The size of the RAM region for linker command file (default 64MiB). ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` Enables support sifive Freedom E310 Arty board if defined to a non-zero - value,otherwise it is disabled (disabled by default) + value,otherwise it is disabled (disabled by default). ``RISCV_ENABLE_MPFS_SUPPORT`` Enables support Microchip PolarFire SoC if defined to a non-zero value, otherwise it is disabled (disabled by default). +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` + Enables support for the Kendtryte K210 SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + ``RISCV_BOOT_HARTID`` The boot hartid (processor number) of risc-v cpu by default 0. @@ -123,15 +135,15 @@ The clock driver uses the CLINT timer. Console Driver -- -The console driver supports devices
