[PATCH] microblaze: Move interrupt context save to BSP

[Alex White]

From: Sam Price 

The interrupt context save is now done in the BSP. This avoids an issue
where a register is modified by the interrupt handler before it is
saved. Specifically, the MSR register was modified by the `addi`
instruction in the interrupt handler before the MSR was saved. This
caused the MSR to be saved with the wrong value.

Closes #4962
---
 .../start/_interrupt_handler.S| 21 +++
 cpukit/score/cpu/microblaze/cpu_asm.S | 17 ---
 2 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
index c24807c3e0..cf95eaee2f 100644
--- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
+++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
@@ -45,11 +45,24 @@
/* Subtract stack frame */
addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
 
-   swi r5, r1, 8
+   /* Save stack frame */
+   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+   swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+   swi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+   swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+   swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+   swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+   swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+   swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+   swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+   swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+   swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+   swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+   swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+   mfs r3, rmsr
+   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
 
/* Indicate unknown interrupt source */
-   addi r5, r0, 0xFF
-
braid _ISR_Handler
-   nop
+   addik r5, r0, 0xFF
 #endif /* __rtems__ */
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 0a2c5d8fff..b0bb2b1fa1 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -41,28 +41,11 @@
.align 2
 
 _ISR_Handler:
-   /* Save stack frame */
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
-   swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
-   swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
-   swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
-   swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
-   swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
-   swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
-   swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
-   swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
-   swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
-   swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
-   mfs r3, rmsr
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
-
/* Disable dispatching */
lwi r3, r0, _Per_CPU_Information + 16
addik r3, r3, 1
swi r3, r0, _Per_CPU_Information + 16
 
-   swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-
/* Is SP < INTERRUPT_STACK_LOW? */
lwi r4, r0, _Per_CPU_Information
rsubk r3, r4, r1
-- 
2.34.1

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[PATCH] validation: Add wrapped bsp_interrupt_dispatch for MicroBlaze

[Alex White]

This adds a MicroBlaze-specific bsp_interrupt_dispatch wrapper which
fixes a linker error.
---
 testsuites/validation/tc-score-isr.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/testsuites/validation/tc-score-isr.c 
b/testsuites/validation/tc-score-isr.c
index f29abbbfe8..9891829a84 100644
--- a/testsuites/validation/tc-score-isr.c
+++ b/testsuites/validation/tc-score-isr.c
@@ -128,6 +128,23 @@ void __wrap_bsp_interrupt_dispatch( void )
 }
 #endif
 
+#if defined(__microblaze__)
+void __real_bsp_interrupt_dispatch( uint32_t source );
+
+void __wrap_bsp_interrupt_dispatch( uint32_t source );
+
+void __wrap_bsp_interrupt_dispatch( uint32_t source )
+{
+  register uintptr_t sp __asm__( "1" );
+
+  if ( interrupted_stack_at_multitasking_start == 0 ) {
+interrupted_stack_at_multitasking_start = sp;
+  }
+
+  __real_bsp_interrupt_dispatch( source );
+}
+#endif
+
 #if defined(__PPC__) || defined(__powerpc64__)
 void __real_bsp_interrupt_dispatch( void );
 
-- 
2.34.1

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[PATCH rtems-docs] user/exe: Add MicroBlaze to Dynamic Loader architecture list

[Alex White]

---
 user/exe/loader.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/user/exe/loader.rst b/user/exe/loader.rst
index be2e78e..fdc54a8 100644
--- a/user/exe/loader.rst
+++ b/user/exe/loader.rst
@@ -844,6 +844,7 @@ The following architectures are supported:
  - Intel x86 (i386)
  - LM32
  - M68K
+ - MicroBlaze
  - MIPS
  - Moxie
  - PowerPC
-- 
2.34.1

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[PATCH] microblaze: Fix relocation targets

[Alex White]

Previously the addend was only used in 64 bit relocations. This
behavior was incorrect but did not cause the RTEMS libdl tests to
fail.
---
 cpukit/libdl/rtl-mdreloc-microblaze.c | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/cpukit/libdl/rtl-mdreloc-microblaze.c 
b/cpukit/libdl/rtl-mdreloc-microblaze.c
index 0daba19a47..0956e22bc7 100644
--- a/cpukit/libdl/rtl-mdreloc-microblaze.c
+++ b/cpukit/libdl/rtl-mdreloc-microblaze.c
@@ -141,8 +141,10 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 
   where = (Elf_Addr *)(sect->base + rela->r_offset);
 
+  /* Target value */
+  target = (Elf_Addr)symvalue + addend;
   /* Final PCREL value */
-  Elf_Word pcrel_val = symvalue - ((Elf_Word)where);
+  Elf_Word pcrel_val = target - ((Elf_Word)where);
 
   if (parsing) {
 return rtems_rtl_elf_rel_no_error;
@@ -153,7 +155,6 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 break;
 
   case R_TYPE(64):
-target = (Elf_Addr)symvalue + addend;
 /* Set the lower 16 bits of where to the upper 16 bits of target */
 write16le(where,
   (read16le(where) & 0x) | (target >> 16));
@@ -180,18 +181,18 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 unsigned offset = addr & 3;
 
 /*
- * Combine `symvalue` with `value_down` and `value_up` to form the new
+ * Combine `target` with `value_down` and `value_up` to form the new
  * values to write.
  */
 uint32_t new_value_down = (value_down & ((1 << (offset * 8)) - 1)) |
-  (symvalue << (offset * 8));
+  (target << (offset * 8));
 uint32_t new_value_up = (value_up & ~((1 << (offset * 8)) - 1)) |
-  (symvalue >> ((4 - offset) * 8));
+  (target >> ((4 - offset) * 8));
 
 write32le((void*)addr_down, new_value_down);
 write32le((void*)addr_up, new_value_up);
   } else {
-write32le(where, symvalue);
+write32le(where, target);
   }
 }
 break;
@@ -208,13 +209,13 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 /*
  * Compensate for the fact that the PC is 4 bytes ahead of the instruction
  */
-target = pcrel_val - 4;
+pcrel_val -= 4;
 /* Set the lower 16 bits of where to the upper 16 bits of target */
 write16le(where,
-  (read16le(where) & 0x) | (target >> 16));
+  (read16le(where) & 0x) | (pcrel_val >> 16));
 /* Set the lower 16 bits of where + 4 to the lower 16 bits of target */
 write16le(where + 1,
-  (read16le(where + 1) & 0x) | (target & 0x));
+  (read16le(where + 1) & 0x) | (pcrel_val & 0x));
 
 if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC))
   printf ("rtl: R_MICROBLAZE_64_PCREL %p @ %p in %s\n",
-- 
2.34.1

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[PATCH v2 6/6] microblaze: Add link options to dl07, dl08, and dl09

[Alex White]

This adds `-u__extendsfdf2` to the `ldflags` for the dl07, dl08, and
dl09 tests to force the inclusion of `__extendsfdf2` in the base image.
This function is part of the GCC software floating point library and is
used in the tests to convert floats to doubles when calling `printf`.
---
 spec/build/testsuites/libtests/dl07.yml | 5 -
 spec/build/testsuites/libtests/dl08.yml | 5 -
 spec/build/testsuites/libtests/dl09.yml | 5 -
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/spec/build/testsuites/libtests/dl07.yml 
b/spec/build/testsuites/libtests/dl07.yml
index 31b8e28942..f8e27fa9c3 100644
--- a/spec/build/testsuites/libtests/dl07.yml
+++ b/spec/build/testsuites/libtests/dl07.yml
@@ -33,7 +33,10 @@ enabled-by:
   - BUILD_LIBDL
 includes:
 - testsuites/libtests/dl07
-ldflags: []
+ldflags:
+- enabled-by:
+  - microblaze
+  value: -u__extendsfdf2
 links: []
 prepare-build: null
 prepare-configure: null
diff --git a/spec/build/testsuites/libtests/dl08.yml 
b/spec/build/testsuites/libtests/dl08.yml
index 0467ca3c4c..34ed1ba67b 100644
--- a/spec/build/testsuites/libtests/dl08.yml
+++ b/spec/build/testsuites/libtests/dl08.yml
@@ -38,7 +38,10 @@ enabled-by:
   - BUILD_LIBDL
 includes:
 - testsuites/libtests/dl08
-ldflags: []
+ldflags:
+- enabled-by:
+  - microblaze
+  value: -u__extendsfdf2
 links: []
 prepare-build: null
 prepare-configure: null
diff --git a/spec/build/testsuites/libtests/dl09.yml 
b/spec/build/testsuites/libtests/dl09.yml
index bada446d16..0fcc631122 100644
--- a/spec/build/testsuites/libtests/dl09.yml
+++ b/spec/build/testsuites/libtests/dl09.yml
@@ -33,7 +33,10 @@ enabled-by:
   - BUILD_LIBDL
 includes:
 - testsuites/libtests/dl09
-ldflags: []
+ldflags:
+- enabled-by:
+  - microblaze
+  value: -u__extendsfdf2
 links: []
 prepare-build: null
 prepare-configure: null
-- 
2.34.1

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[PATCH v2 5/6] build: Allow enabled-by in ldflags for link_cc and link_cxx

[Alex White]

This allows for conditionally setting 'ldflags' in scripts that use
`link_cc` and `link_cxx`. The immediate use case is allowing a linker
flag to be used only for MicroBlaze builds of certain tests.
---
 wscript | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/wscript b/wscript
index 280c3929cd..03c6ac1035 100755
--- a/wscript
+++ b/wscript
@@ -353,10 +353,10 @@ class Item(object):
 
 class link(Task):
 
-def __init__(self, item, bic, cmd, env):
+def __init__(self, item, bic, cmd, env, ldflags):
 super(link, self).__init__(self, env=env)
 self.cmd = cmd
-self.ldflags = bic.ldflags + item.data["ldflags"]
+self.ldflags = bic.ldflags + ldflags
 self.stlib = item.data["stlib"]
 self.use = (item.data["use-before"] + bic.use +
 item.data["use-after"])
@@ -382,7 +382,14 @@ class Item(object):
 [],
 )
 
-tsk = link(self, bic, cmd, bld.env)
+ldflags = []
+for ldflag in self.data["ldflags"]:
+if isinstance(ldflag, dict):
+if _is_enabled(bld.env.ENABLE, ldflag["enabled-by"]):
+ldflags.append(ldflag["value"])
+else:
+ldflags.append(ldflag)
+tsk = link(self, bic, cmd, bld.env, ldflags)
 tsk.set_inputs([bld.bldnode.make_node(s) for s in source])
 tsk.set_outputs(bld.bldnode.make_node(target))
 bld.add_to_group(tsk)
-- 
2.34.1

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[PATCH v2 3/6] microblaze: Add dl06 to expected failures

[Alex White]

Updates #4948
---
 spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
index 665d4d0d54..7ff9350cf4 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
@@ -12,5 +12,7 @@ copyrights:
 default: []
 description: ''
 enabled-by: true
-links: []
+links: 
+- role: build-dependency
+  uid: ../../tst-xfail-dl06
 type: build
-- 
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[PATCH v2 4/6] microblaze: Add dl05 to expected failures

[Alex White]

Updates #4949
---
 .../bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml  | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
index 7ff9350cf4..7ae7005bf0 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
@@ -6,6 +6,12 @@ actions:
 state: exclude
 tests:
 - minimum
+- set-test-state:
+reason: |
+  Expected to fail due to GCC issues.
+state: expected-fail
+tests:
+- dl05
 build-type: option
 copyrights:
 - Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
-- 
2.34.1

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[PATCH v2 1/6] microblaze: Add libdl support

[Alex White]

---
 cpukit/libdl/rtl-mdreloc-microblaze.c | 297 ++
 cpukit/libdl/rtl-tls.c|   2 +-
 .../microblaze/include/machine/elf_machdep.h  |  83 +
 spec/build/cpukit/cpumicroblaze.yml   |   3 +
 spec/build/cpukit/objdl.yml   |   2 +
 spec/build/cpukit/objdlmicroblaze.yml |  15 +
 spec/build/cpukit/optlibdl.yml|   1 +
 7 files changed, 402 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/libdl/rtl-mdreloc-microblaze.c
 create mode 100644 cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
 create mode 100644 spec/build/cpukit/objdlmicroblaze.yml

diff --git a/cpukit/libdl/rtl-mdreloc-microblaze.c 
b/cpukit/libdl/rtl-mdreloc-microblaze.c
new file mode 100644
index 00..0daba19a47
--- /dev/null
+++ b/cpukit/libdl/rtl-mdreloc-microblaze.c
@@ -0,0 +1,297 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include "rtl-elf.h"
+#include "rtl-error.h"
+#include 
+#include "rtl-unwind.h"
+#include "rtl-unwind-dw2.h"
+
+uint32_t
+rtems_rtl_elf_section_flags (const rtems_rtl_obj* obj,
+ const Elf_Shdr*  shdr) {
+  (void) obj;
+  (void) shdr;
+  return 0;
+}
+
+uint32_t
+rtems_rtl_elf_arch_parse_section (const rtems_rtl_obj* obj,
+  int  section,
+  const char*  name,
+  const Elf_Shdr*  shdr,
+  const uint32_t   flags) {
+  (void) obj;
+  (void) section;
+  (void) name;
+  (void) shdr;
+  return flags;
+}
+
+bool
+rtems_rtl_elf_arch_section_alloc (const rtems_rtl_obj* obj,
+  rtems_rtl_obj_sect*  sect) {
+  (void) obj;
+  (void) sect;
+  return false;
+}
+
+bool
+rtems_rtl_elf_arch_section_free (const rtems_rtl_obj* obj,
+ rtems_rtl_obj_sect*  sect) {
+  (void) obj;
+  (void) sect;
+  return false;
+}
+
+bool
+rtems_rtl_elf_rel_resolve_sym (Elf_Word type) {
+  return type != 0;
+}
+
+uint32_t rtems_rtl_obj_tramp_alignment (const rtems_rtl_obj* obj)
+{
+  (void) obj;
+  return sizeof(uint32_t);
+}
+
+size_t
+rtems_rtl_elf_relocate_tramp_max_size (void) {
+  /*
+   * Disable by returning 0.
+   */
+  return 0;
+}
+
+rtems_rtl_elf_rel_status
+rtems_rtl_elf_relocate_rel_tramp (rtems_rtl_obj*obj,
+  const Elf_Rel*rel,
+  const rtems_rtl_obj_sect* sect,
+  const char*   symname,
+  const Elf_Bytesyminfo,
+  const Elf_Wordsymvalue) {
+  (void) obj;
+  (void) rel;
+  (void) sect;
+  (void) symname;
+  (void) syminfo;
+  (void) symvalue;
+  return rtems_rtl_elf_rel_no_error;
+}
+
+static void write16le(void *loc, uint16_t val) {
+  *((uint16_t *) loc) = val;
+}
+
+static void write32le(void *loc, uint32_t val) {
+  *((uint32_t *) loc) = val;
+}
+
+static uint16_t read16le(void *loc) {
+  return *((uint16_t *) loc);
+}
+
+static uint32_t read32le(void *loc) {
+  return *((uint32_t *) loc);
+}
+
+static rtems_rtl_elf_rel_status
+rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
+  const Elf_Rela*   rela,
+  const rtems_rtl_obj_sect* sect,
+  const char*   symname,
+  const Elf_Byte 

[PATCH v2 0/6] Add libdl support to MicroBlaze

[Alex White]

Hi,

This patch set adds libdl support to MicroBlaze. All tests pass except for dl05
and dl06. To get dl07, dl08, and dl09 to pass, I added `-u__extendsfdf2` to the
link options.

v2:
- Remove changes to dl07, dl08, and dl09 source code
- Add link options to dl07, dl08, and dl09

Alex

Alex White (6):
  microblaze: Add libdl support
  microblaze: Align exception-related sections
  microblaze: Add dl06 to expected failures
  microblaze: Add dl05 to expected failures
  build: Allow enabled-by in ldflags for link_cc and link_cxx
  microblaze: Add link options to dl07, dl08, and dl09

 cpukit/libdl/rtl-mdreloc-microblaze.c | 297 ++
 cpukit/libdl/rtl-tls.c|   2 +-
 .../microblaze/include/machine/elf_machdep.h  |  83 +
 .../microblaze/microblaze_fpga/linkcmds.yml   |   8 +-
 .../microblaze_fpga/tstkcu105_qemu.yml|  10 +-
 spec/build/cpukit/cpumicroblaze.yml   |   3 +
 spec/build/cpukit/objdl.yml   |   2 +
 spec/build/cpukit/objdlmicroblaze.yml |  15 +
 spec/build/cpukit/optlibdl.yml|   1 +
 spec/build/testsuites/libtests/dl07.yml   |   5 +-
 spec/build/testsuites/libtests/dl08.yml   |   5 +-
 spec/build/testsuites/libtests/dl09.yml   |   5 +-
 wscript   |  13 +-
 13 files changed, 437 insertions(+), 12 deletions(-)
 create mode 100644 cpukit/libdl/rtl-mdreloc-microblaze.c
 create mode 100644 cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
 create mode 100644 spec/build/cpukit/objdlmicroblaze.yml

-- 
2.34.1

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[PATCH v2 2/6] microblaze: Align exception-related sections

[Alex White]

This fixes unaligned data access exceptions found while debugging test
dl05.
---
 spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
index 9a3ca11b51..4f9b310ad3 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
@@ -104,20 +104,20 @@ content: |
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 
 _frodata = . ;
-.rodata : {
+.rodata : ALIGN_WITH_INPUT {
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   CONSTRUCTORS; /* Is this needed? */
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 _erodata = .;
-.eh_frame : {
-  *(.eh_frame)
+.eh_frame : ALIGN_WITH_INPUT {
+  KEEP (*(.eh_frame))
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 .jcr : {
   *(.jcr)
 } > REGION_RODATA AT > REGION_RODATA_LOAD
-.gcc_except_table : {
+.gcc_except_table : ALIGN_WITH_INPUT {
   *(.gcc_except_table)
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 .tdata : ALIGN_WITH_INPUT {
-- 
2.34.1

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Re: [PATCH 2/5] testsuites/libtests: Remove floats from libdl tests

[Alex White]

On Mon, Aug 28, 2023 at 10:31 AM Sam Price  wrote:
>
> Nevermind that would be done at the linker and not at compile time.

I searched for some way to check if soft float routines are being used, but I
couldn't find anything.

Maybe we just remove the conditional altogether? I don't think it's a problem
to have an extra print statement on targets that use hardware floating point
instructions. This would simplify the code and make it more portable.

Alex
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Re: [PATCH 2/5] testsuites/libtests: Remove floats from libdl tests

[Alex White]

On Sun, Aug 27, 2023 at 11:48 PM Chris Johns  wrote:
>
> On 28/8/2023 2:12 pm, Alex White wrote:
> > On Sun, Aug 27, 2023 at 8:38 PM Chris Johns  wrote:
> >> The floats need to stay to make sure there are no issues with this type. I 
> >> see
> >> the tests with floats as valid.
> >>
> >> Is the only missing function `__extendsfdf2`?
> >
> > Yes, that is the only missing function. If I change the floats to doubles, 
> > the
> > need for `__extendsfdf2` goes away and the tests pass. Is that an acceptable
> > solution?
>
> I would happy with doubles being added so they are tested as well but that is
> also outside the scope of your effort :)
>
> Is it easier to add a Microblaze conditional for the use of a double to the 
> base
> image and to forced the symbol to be linked in?

I don't think it's too hard to add a conditional to the base image. For
instance, this modification to dl07 is enough to make it pass on MicroBlaze:

diff --git a/testsuites/libtests/dl07/init.c b/testsuites/libtests/dl07/init.c
index 8db106ba29..7fb1500660 100644
--- a/testsuites/libtests/dl07/init.c
+++ b/testsuites/libtests/dl07/init.c
@@ -67,6 +67,14 @@ static void Init(rtems_task_argument arg)
 
   TEST_BEGIN();
 
+#ifdef __microblaze__
+  /* This is just here to link `__extendsfdf2` into the base image. */
+  {
+float f = 0.;
+printf("f: %f\n", f);
+  }
+#endif /* __microblaze__ */
+
   te = rtems_tarfs_load("/", (void *)TARFILE_START, (size_t)TARFILE_SIZE);
   if (te != 0)
   {

Is that what you were thinking?

Alex
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Re: [PATCH 2/5] testsuites/libtests: Remove floats from libdl tests

[Alex White]

On Sun, Aug 27, 2023 at 8:38 PM Chris Johns  wrote:
> The floats need to stay to make sure there are no issues with this type. I see
> the tests with floats as valid.
>
> Is the only missing function `__extendsfdf2`?

Yes, that is the only missing function. If I change the floats to doubles, the
need for `__extendsfdf2` goes away and the tests pass. Is that an acceptable
solution?

Alex
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[PATCH 2/5] testsuites/libtests: Remove floats from libdl tests

[Alex White]

This patch addresses an issue seen with MicroBlaze in the dl07, dl08,
and dl09 tests by removing the use of floats. The issue relates to the
fact that the MicroBlaze BSPs use software floating point routines. Any
float passed to `printf` is converted to a double automatically because
of default argument promotion with variadic functions. This conversion
is handled by the `__extendsfdf2` libgcc function. The problem is that
the main test executable does not use floating point code, so the
`__extendsfdf2` function is not linked in. This causes a problem when
loading the test objects.

This patch removes the use of floats so that BSPs that use software
floating point routines can still run the tests.
---
 testsuites/libtests/dl07/dl-o1.h   | 11 ---
 testsuites/libtests/dl07/dl-o2.h   |  8 +++-
 testsuites/libtests/dl07/dl-o4.h   |  1 -
 testsuites/libtests/dl07/dl07-o1.c | 16 +---
 testsuites/libtests/dl07/dl07-o2.c | 13 +++--
 testsuites/libtests/dl07/dl07-o3.c |  6 --
 testsuites/libtests/dl07/dl07-o4.c |  5 -
 testsuites/libtests/dl07/dl07-o5.c |  3 ---
 testsuites/libtests/dl08/dl-o1.h   | 11 ---
 testsuites/libtests/dl08/dl-o2.h   |  8 +++-
 testsuites/libtests/dl08/dl-o4.h   |  1 -
 testsuites/libtests/dl08/dl08-o1.c | 16 +---
 testsuites/libtests/dl08/dl08-o2.c | 10 +++---
 testsuites/libtests/dl08/dl08-o3.c |  1 -
 testsuites/libtests/dl08/dl08-o4.c |  2 --
 testsuites/libtests/dl09/dl-o1.h   | 11 ---
 testsuites/libtests/dl09/dl-o2.h   |  8 +++-
 testsuites/libtests/dl09/dl-o4.h   |  1 -
 testsuites/libtests/dl09/dl09-o1.c | 16 +---
 testsuites/libtests/dl09/dl09-o2.c | 10 +++---
 testsuites/libtests/dl09/dl09-o3.c |  1 -
 testsuites/libtests/dl09/dl09-o4.c |  2 --
 22 files changed, 45 insertions(+), 116 deletions(-)

diff --git a/testsuites/libtests/dl07/dl-o1.h b/testsuites/libtests/dl07/dl-o1.h
index 745e548778..74a9e4c935 100644
--- a/testsuites/libtests/dl07/dl-o1.h
+++ b/testsuites/libtests/dl07/dl-o1.h
@@ -29,13 +29,10 @@
 #if !defined(DL01_H)
 #define DL01_H
 
-extern int dl01_bss1;
-extern float   dl01_bss2[30];
-extern chardl01_bss3[10];
-extern int dl01_data1;
-extern float   dl01_data2;
-extern const int   dl01_const1;
-extern const float dl01_const2;
+extern int   dl01_bss1;
+extern char  dl01_bss3[10];
+extern int   dl01_data1;
+extern const int dl01_const1;
 int dl01_func1(void);
 
 #endif
diff --git a/testsuites/libtests/dl07/dl-o2.h b/testsuites/libtests/dl07/dl-o2.h
index d7812c4475..ac56921804 100644
--- a/testsuites/libtests/dl07/dl-o2.h
+++ b/testsuites/libtests/dl07/dl-o2.h
@@ -33,10 +33,8 @@
  * A set of variables in dl-o2 reference by dl-03.
  */
 
-extern int   dl02_bss1;
-extern float dl02_bss2[7];
-extern char  dl02_bss3[21];
-extern int   dl02_data1;
-extern float dl02_data2;
+extern int  dl02_bss1;
+extern char dl02_bss3[21];
+extern int  dl02_data1;
 
 #endif
diff --git a/testsuites/libtests/dl07/dl-o4.h b/testsuites/libtests/dl07/dl-o4.h
index 7ea5139fe9..c49223c23b 100644
--- a/testsuites/libtests/dl07/dl-o4.h
+++ b/testsuites/libtests/dl07/dl-o4.h
@@ -37,7 +37,6 @@
  */
 
 extern int dl04_unresolv_1;
-extern float   dl04_unresolv_2;
 extern chardl04_unresolv_3;
 extern char*   dl04_unresolv_4;
 extern const int   dl04_unresolv_5;
diff --git a/testsuites/libtests/dl07/dl07-o1.c 
b/testsuites/libtests/dl07/dl07-o1.c
index 24a8086c49..229bd582e7 100644
--- a/testsuites/libtests/dl07/dl07-o1.c
+++ b/testsuites/libtests/dl07/dl07-o1.c
@@ -38,14 +38,11 @@
  * separated text and data and this means there is no actual section in the ELF
  * file, the details for this are in the symbols.
  */
-int dl01_bss1;/* unitialised, .bss */
-float   dl01_bss2[30];/* unitialised, .bss */
-chardl01_bss3[10];/* unitialised, .bss */
-int dl01_data1 = 1;   /* initialised, .data */
-float   dl01_data2 = 0.;  /* initialised, .data */
-const int   dl01_const1 = 3;  /* read-only, .const */
-const float dl01_const2 = 0.666;  /* read-only, .const */
-int dl01_func1(void)  /* code, .text */
+int   dl01_bss1;/* unitialised, .bss */
+char  dl01_bss3[10];/* unitialised, .bss */
+int   dl01_data1 = 1;   /* initialised, .data */
+const int dl01_const1 = 3;  /* read-only, .const */
+int dl01_func1(void)/* code, .text */
 {
   return 4;
 }
@@ -63,13 +60,10 @@ int rtems_main_o1 (void)
 {
   printf (DL_NAME ": module: %s\n", dl_localise_file (__FILE__));
   printf (DL_NAME ": dl01_bss1: %4zu: %p: %d\n",   PAINT_VAR 
(dl01_bss1));
-  printf (DL_NAME ": dl01_bss2: %4zu: %p: %f\n",   PAINT_VAR 
(dl01_bss2[0]));
   printf (DL_NAME ": dl01_bss3: %4zu: %p: %02x\n", PAINT_VAR 
(dl01_bss3[0]));
   printf (DL_NAME ":dl01_data1: %4zu: %p: %d\n",   PAINT_VAR 
(dl01_data1));
   /* no  %f in the rtems test 

[PATCH 5/5] microblaze: Add dl05 to expected failures

[Alex White]

Updates #4949
---
 .../bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml  | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
index 7ff9350cf4..7ae7005bf0 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
@@ -6,6 +6,12 @@ actions:
 state: exclude
 tests:
 - minimum
+- set-test-state:
+reason: |
+  Expected to fail due to GCC issues.
+state: expected-fail
+tests:
+- dl05
 build-type: option
 copyrights:
 - Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
-- 
2.34.1

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[PATCH 1/5] microblaze: Add libdl support

[Alex White]

---
 cpukit/libdl/rtl-mdreloc-microblaze.c | 291 ++
 cpukit/libdl/rtl-tls.c|   2 +-
 .../microblaze/include/machine/elf_machdep.h  |  83 +
 spec/build/cpukit/cpumicroblaze.yml   |   3 +
 spec/build/cpukit/objdl.yml   |   2 +
 spec/build/cpukit/objdlmicroblaze.yml |  15 +
 spec/build/cpukit/optlibdl.yml|   1 +
 7 files changed, 396 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/libdl/rtl-mdreloc-microblaze.c
 create mode 100644 cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
 create mode 100644 spec/build/cpukit/objdlmicroblaze.yml

diff --git a/cpukit/libdl/rtl-mdreloc-microblaze.c 
b/cpukit/libdl/rtl-mdreloc-microblaze.c
new file mode 100644
index 00..b8834b203b
--- /dev/null
+++ b/cpukit/libdl/rtl-mdreloc-microblaze.c
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include "rtl-elf.h"
+#include "rtl-error.h"
+#include 
+#include "rtl-unwind.h"
+#include "rtl-unwind-dw2.h"
+
+uint32_t
+rtems_rtl_elf_section_flags (const rtems_rtl_obj* obj,
+ const Elf_Shdr*  shdr) {
+  (void) obj;
+  (void) shdr;
+  return 0;
+}
+
+uint32_t
+rtems_rtl_elf_arch_parse_section (const rtems_rtl_obj* obj,
+  int  section,
+  const char*  name,
+  const Elf_Shdr*  shdr,
+  const uint32_t   flags) {
+  (void) obj;
+  (void) section;
+  (void) name;
+  (void) shdr;
+  return flags;
+}
+
+bool
+rtems_rtl_elf_arch_section_alloc (const rtems_rtl_obj* obj,
+  rtems_rtl_obj_sect*  sect) {
+  (void) obj;
+  (void) sect;
+  return false;
+}
+
+bool
+rtems_rtl_elf_arch_section_free (const rtems_rtl_obj* obj,
+ rtems_rtl_obj_sect*  sect) {
+  (void) obj;
+  (void) sect;
+  return false;
+}
+
+bool
+rtems_rtl_elf_rel_resolve_sym (Elf_Word type) {
+  return type != 0;
+}
+
+size_t
+rtems_rtl_elf_relocate_tramp_max_size (void) {
+  /*
+   * Disable by returning 0.
+   */
+  return 0;
+}
+
+rtems_rtl_elf_rel_status
+rtems_rtl_elf_relocate_rel_tramp (rtems_rtl_obj*obj,
+  const Elf_Rel*rel,
+  const rtems_rtl_obj_sect* sect,
+  const char*   symname,
+  const Elf_Bytesyminfo,
+  const Elf_Wordsymvalue) {
+  (void) obj;
+  (void) rel;
+  (void) sect;
+  (void) symname;
+  (void) syminfo;
+  (void) symvalue;
+  return rtems_rtl_elf_rel_no_error;
+}
+
+static void write16le(void *loc, uint16_t val) {
+  *((uint16_t *) loc) = val;
+}
+
+static void write32le(void *loc, uint32_t val) {
+  *((uint32_t *) loc) = val;
+}
+
+static uint16_t read16le(void *loc) {
+  return *((uint16_t *) loc);
+}
+
+static uint32_t read32le(void *loc) {
+  return *((uint32_t *) loc);
+}
+
+static rtems_rtl_elf_rel_status
+rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
+  const Elf_Rela*   rela,
+  const rtems_rtl_obj_sect* sect,
+  const char*   symname,
+  const Elf_Bytesyminfo,
+  const Elf_Wordsymvalue,
+  const 

[PATCH 4/5] microblaze: Add dl06 to expected failures

[Alex White]

Updates #4948
---
 spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
index 665d4d0d54..7ff9350cf4 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml
@@ -12,5 +12,7 @@ copyrights:
 default: []
 description: ''
 enabled-by: true
-links: []
+links: 
+- role: build-dependency
+  uid: ../../tst-xfail-dl06
 type: build
-- 
2.34.1

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[PATCH 3/5] microblaze: Align exception-related sections

[Alex White]

This fixes unaligned data access exceptions found while debugging test
dl05.
---
 spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
index 9a3ca11b51..4f9b310ad3 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
@@ -104,20 +104,20 @@ content: |
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 
 _frodata = . ;
-.rodata : {
+.rodata : ALIGN_WITH_INPUT {
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   CONSTRUCTORS; /* Is this needed? */
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 _erodata = .;
-.eh_frame : {
-  *(.eh_frame)
+.eh_frame : ALIGN_WITH_INPUT {
+  KEEP (*(.eh_frame))
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 .jcr : {
   *(.jcr)
 } > REGION_RODATA AT > REGION_RODATA_LOAD
-.gcc_except_table : {
+.gcc_except_table : ALIGN_WITH_INPUT {
   *(.gcc_except_table)
 } > REGION_RODATA AT > REGION_RODATA_LOAD
 .tdata : ALIGN_WITH_INPUT {
-- 
2.34.1

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[PATCH 0/5] Add libdl support to MicroBlaze

[Alex White]

Hi,

This patch set adds libdl support to MicroBlaze. All tests pass except for dl05
and dl06. To get dl07, dl08, and dl09 to pass, I removed the use of floating
point numbers from those tests.

Alex

Alex White (5):
  microblaze: Add libdl support
  testsuites/libtests: Remove floats from libdl tests
  microblaze: Align exception-related sections
  microblaze: Add dl06 to expected failures
  microblaze: Add dl05 to expected failures

 cpukit/libdl/rtl-mdreloc-microblaze.c | 291 ++
 cpukit/libdl/rtl-tls.c|   2 +-
 .../microblaze/include/machine/elf_machdep.h  |  83 +
 .../microblaze/microblaze_fpga/linkcmds.yml   |   8 +-
 .../microblaze_fpga/tstkcu105_qemu.yml|  10 +-
 spec/build/cpukit/cpumicroblaze.yml   |   3 +
 spec/build/cpukit/objdl.yml   |   2 +
 spec/build/cpukit/objdlmicroblaze.yml |  15 +
 spec/build/cpukit/optlibdl.yml|   1 +
 testsuites/libtests/dl07/dl-o1.h  |  11 +-
 testsuites/libtests/dl07/dl-o2.h  |   8 +-
 testsuites/libtests/dl07/dl-o4.h  |   1 -
 testsuites/libtests/dl07/dl07-o1.c|  16 +-
 testsuites/libtests/dl07/dl07-o2.c|  13 +-
 testsuites/libtests/dl07/dl07-o3.c|   6 -
 testsuites/libtests/dl07/dl07-o4.c|   5 -
 testsuites/libtests/dl07/dl07-o5.c|   3 -
 testsuites/libtests/dl08/dl-o1.h  |  11 +-
 testsuites/libtests/dl08/dl-o2.h  |   8 +-
 testsuites/libtests/dl08/dl-o4.h  |   1 -
 testsuites/libtests/dl08/dl08-o1.c|  16 +-
 testsuites/libtests/dl08/dl08-o2.c|  10 +-
 testsuites/libtests/dl08/dl08-o3.c|   1 -
 testsuites/libtests/dl08/dl08-o4.c|   2 -
 testsuites/libtests/dl09/dl-o1.h  |  11 +-
 testsuites/libtests/dl09/dl-o2.h  |   8 +-
 testsuites/libtests/dl09/dl-o4.h  |   1 -
 testsuites/libtests/dl09/dl09-o1.c|  16 +-
 testsuites/libtests/dl09/dl09-o2.c|  10 +-
 testsuites/libtests/dl09/dl09-o3.c|   1 -
 testsuites/libtests/dl09/dl09-o4.c|   2 -
 31 files changed, 454 insertions(+), 122 deletions(-)
 create mode 100644 cpukit/libdl/rtl-mdreloc-microblaze.c
 create mode 100644 cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
 create mode 100644 spec/build/cpukit/objdlmicroblaze.yml

-- 
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MicroBlaze Dynamic Loader Test Failures

[Alex White]

Hi,

I am currently working on RTEMS dynamic loader support for MicroBlaze. I got 
most of the dynamic loader tests working, but for a few of them, I had to 
modify the test. I believe the failures are because the MicroBlaze RTEMS port 
uses soft floating point emulation. Tests dl07, dl08, and dl09 fail because the 
objects being loaded include floating point code that requires an extra routine 
from GCC, `__extendsfdf2`, that is not included in the base application.

According to GCC documentation 
(https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html), 
`__extendsfdf2` is used to extend a float to a double. This is needed in test 
dl07, for example, to print `dl01_bss2[0]` on line 66:

printf (DL_NAME ": dl01_bss2: %4zu: %p: %f\n", PAINT_VAR (dl01_bss2[0]));

The modification that I made to get this working was to add the following to 
init.c in each of the three failing tests:

#ifdef __microblaze__
extern double __extendsfdf2 (float a);
/* This ensures that __extendsfdf2 is included in the compiled output. */
double (*extendsfdf2_fp)(float) = &__extendsfdf2;
#endif /* __microblaze__ */

I'm not sure of any way to check whether or not this code should be included 
other than `#ifdef __microblaze__`. This doesn't seem like a great solution, 
though. I searched for a predefined macro that would allow this to be generic 
across different architectures, maybe something indicating software floating 
point, but I couldn't find anything suitable.

Does anyone have a suggestion for a better way to solve this?

Thanks,

Alex
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Re: [PATCH 4/4] bsps/xqspipsu: Use device information from the FCT

[Alex White]

These patches look good to me.

Thanks,

Alex
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[PATCH 2/2] bsps/microblaze: Add device tree support to GPIO

[Alex White]

---
 .../microblaze_fpga/gpio/microblaze-gpio.c| 63 +++
 .../include/bsp/microblaze-gpio.h | 18 ++
 2 files changed, 81 insertions(+)

diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c 
b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
index a12158f1b7..98cc863fd2 100644
--- a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -36,12 +36,75 @@
 #include 
 
 #include 
+#include 
 #include 
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+rtems_status_code microblaze_gpio_init_context_from_fdt(
+  Microblaze_GPIO_context *context,
+  int index
+)
+{
+  if ( context == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+  }
+
+  const char* compatible = "xlnx,xps-gpio-1.00.a";
+  const void *fdt = bsp_fdt_get();
+  int node = fdt_node_offset_by_compatible( fdt, -1, compatible );
+  if ( node < 0 ) {
+return RTEMS_INVALID_NUMBER;
+  }
+  
+  /* Get the desired GPIO node if index is greater than zero. */
+  for(int i = 0; i < index; i++) {
+node = fdt_node_offset_by_compatible( fdt, node, compatible );
+if ( node < 0 ) {
+  return RTEMS_INVALID_NUMBER;
+}
+  }
+
+  const uint32_t *prop;
+  prop = fdt_getprop( fdt, node, "reg", NULL );
+  if ( prop != NULL ) {
+context->regs = (Microblaze_GPIO_registers *) fdt32_to_cpu( prop[0] );
+  } else {
+return RTEMS_INVALID_NUMBER;
+  }
+
+  prop = fdt_getprop( fdt, node, "xlnx,is-dual", NULL );
+  if ( prop != NULL ) {
+context->is_dual = fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+  } else {
+return RTEMS_INVALID_NUMBER;
+  }
+
+  prop = fdt_getprop( fdt, node, "xlnx,interrupt-present", NULL );
+  if ( prop != NULL ) {
+context->has_interrupts = fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+  } else {
+return RTEMS_INVALID_NUMBER;
+  }
+
+  if ( context->has_interrupts ) {
+prop = fdt_getprop( fdt, node, "interrupts", NULL );
+if ( prop != NULL ) {
+  context->irq = fdt32_to_cpu( prop[0] );
+} else {
+  return RTEMS_INVALID_NUMBER;
+}
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+
 void microblaze_gpio_set_data_direction(
   Microblaze_GPIO_context *ctx,
   uint32_t channel,
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h 
b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
index a3d79ff70f..e68e0a78cb 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
@@ -129,6 +129,24 @@ typedef struct {
   bool   has_interrupts;
 } Microblaze_GPIO_context;
 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+/**
+ * @brief Initialize GPIO context from FDT.
+ * 
+ * @param[in] context the GPIO context to initialize
+ * @param[in] index the zero-based GPIO index in the FDT
+ * 
+ * @retval RTEMS_SUCCESSFUL on success
+ * @retval RTEMS_INVALID_NUMBER if the index is invalid or the node is missing 
a
+ * required property
+ * @retval RTEMS_INVALID_ADDRESS if the context is NULL
+ */
+rtems_status_code microblaze_gpio_init_context_from_fdt(
+  Microblaze_GPIO_context *context,
+  int index
+);
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+
 /**
  * @brief Set pin configuration for the specified GPIO channel.
  *
-- 
2.34.1

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[PATCH 1/2] bsps/microblaze: Remove GPIO build system options

[Alex White]

The number of GPIO devices along with each of their particular
configurations is application-specific. Encoding this information as
build options also introduced a lot of clutter.
---
 .../microblaze_fpga/gpio/microblaze-gpio.c| 32 ---
 .../include/bsp/microblaze-gpio.h | 10 --
 .../bsps/microblaze/microblaze_fpga/grp.yml   | 18 ---
 .../microblaze_fpga/optgpio1baseaddress.yml   | 19 ---
 .../microblaze_fpga/optgpio1dualchannel.yml   | 16 --
 .../microblaze_fpga/optgpio1interrupt.yml | 16 --
 .../microblaze_fpga/optgpio1irq.yml   | 18 ---
 .../microblaze_fpga/optgpio2baseaddress.yml   | 19 ---
 .../microblaze_fpga/optgpio2dualchannel.yml   | 16 --
 .../microblaze_fpga/optgpio2enable.yml| 17 --
 .../microblaze_fpga/optgpio2interrupt.yml | 16 --
 .../microblaze_fpga/optgpio2irq.yml   | 18 ---
 12 files changed, 215 deletions(-)
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
 delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
 delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml

diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c 
b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
index 9025840e32..a12158f1b7 100644
--- a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -42,38 +42,6 @@
 extern "C" {
 #endif /* __cplusplus */
 
-Microblaze_GPIO_context gpio1_context = {
-  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
-  .is_dual = true,
-#else
-  .is_dual = false,
-#endif
-  .irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
-  .has_interrupts = true
-#else
-  .has_interrupts = false
-#endif
-};
-
-#if BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-Microblaze_GPIO_context gpio2_context = {
-  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO2_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
-  .is_dual = true,
-#else
-  .is_dual = false,
-#endif
-  .irq = BSP_MICROBLAZE_FPGA_GPIO2_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
-  .has_interrupts = true
-#else
-  .has_interrupts = false
-#endif
-};
-#endif
-
 void microblaze_gpio_set_data_direction(
   Microblaze_GPIO_context *ctx,
   uint32_t channel,
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h 
b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
index 5fe9c44cf8..a3d79ff70f 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
@@ -129,16 +129,6 @@ typedef struct {
   bool   has_interrupts;
 } Microblaze_GPIO_context;
 
-extern Microblaze_GPIO_context gpio1_context;
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-extern Microblaze_GPIO_context gpio2_context;
-#endif
-
-#define gpio1 ((Microblaze_GPIO_context * const) _context)
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-#define gpio2 ((Microblaze_GPIO_context * const) _context)
-#endif
-
 /**
  * @brief Set pin configuration for the specified GPIO channel.
  *
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
index 4f854de2cd..aeaa07dc03 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -28,24 +28,6 @@ links:
   uid: optdcachesize
 - role: build-dependency
   uid: optdtbheaderpath
-- role: build-dependency
-  uid: optgpio2enable
-- role: build-dependency
-  uid: optgpio1baseaddress
-- role: build-dependency
-  uid: optgpio2baseaddress
-- role: build-dependency
-  uid: optgpio1dualchannel
-- role: build-dependency
-  uid: optgpio2dualchannel
-- role: build-dependency
-  uid: optgpio1irq
-- role: build-dependency
-  uid: optgpio2irq
-- role: build-dependency
-  uid: optgpio1interrupt
-- role: build-dependency
-  uid: optgpio2interrupt
 - role: build-dependency
   uid: opticachebaseaddress
 - role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
deleted file mode 100644
index 34a22d566b..00
--- 

[PATCH 0/2] bsps/microblaze: GPIO improvements

[Alex White]

Hi,

This patch set removes the build system options for the GPIO driver and adds
device tree support. The build system options were removed because they are now
supplied by the application or pulled from the device tree. This removes a lot
of clutter and makes the driver more flexible.

Alex

Alex White (2):
  bsps/microblaze: Remove GPIO build system options
  bsps/microblaze: Add device tree support to GPIO

 .../microblaze_fpga/gpio/microblaze-gpio.c| 93 ---
 .../include/bsp/microblaze-gpio.h | 26 --
 .../bsps/microblaze/microblaze_fpga/grp.yml   | 18 
 .../microblaze_fpga/optgpio1baseaddress.yml   | 19 
 .../microblaze_fpga/optgpio1dualchannel.yml   | 16 
 .../microblaze_fpga/optgpio1interrupt.yml | 16 
 .../microblaze_fpga/optgpio1irq.yml   | 18 
 .../microblaze_fpga/optgpio2baseaddress.yml   | 19 
 .../microblaze_fpga/optgpio2dualchannel.yml   | 16 
 .../microblaze_fpga/optgpio2enable.yml| 17 
 .../microblaze_fpga/optgpio2interrupt.yml | 16 
 .../microblaze_fpga/optgpio2irq.yml   | 18 
 12 files changed, 79 insertions(+), 213 deletions(-)
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
 delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
 delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml

-- 
2.34.1

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Re: Static analysis

[Alex White]

You should be able to use `bear` (https://github.com/rizsotto/Bear). I have it 
installed via my package manager.

After a `./waf clean`, run `bear -- ./waf` to generate compile_commands.json. 
Then you should be able to run `cppcheck --project=compile_commands.json`.

Alex
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Re: [rtems-source-builder] devel/qemu-xilinx: Fix source URL

[Alex White]

On Mon, May 8, 2023 at 1:28 PM Gedare Bloom  wrote:
>
> I think the https works though? Or does it break?
>
> I recall there are sometimes issues that users face based on their IT
> site policy that prevents git protocol from working properly while
> https almost always works (tunnels) right.

Hi Gedare,

The build was broken before this patch.

HTTPS does work, yes, and this patch does not change the protocol. This just
changes how the source is handled by the RSB scripts. To get the git handling to
work, the URL needs to start with 'git://'. It still uses HTTPS since it
specifies '?protocol=https' in the URL.

Thanks,

Alex
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[rtems-source-builder] devel/qemu-xilinx: Fix source URL

[Alex White]

The source URL for Xilinx QEMU appears to have been incorrect from the
start. Since we are cloning a git repository, we should use 'git://'.
---
 bare/config/devel/qemu-xilinx-v2020.2-1.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bare/config/devel/qemu-xilinx-v2020.2-1.cfg 
b/bare/config/devel/qemu-xilinx-v2020.2-1.cfg
index 180b621..2c3fb94 100644
--- a/bare/config/devel/qemu-xilinx-v2020.2-1.cfg
+++ b/bare/config/devel/qemu-xilinx-v2020.2-1.cfg
@@ -15,7 +15,7 @@
 #
 # Checkout the version tag and initialize all submodules.
 #
-%source set qemu 
https://github.com/Xilinx/qemu.git?checkout=%{qemu_version}?submodule=dtc?submodule=slirp?submodule=ui/keycodemapdb?submodule=tests/fp/berkeley-softfloat-3?submodule=tests/fp/berkeley-testfloat-3
+%source set qemu 
git://github.com/Xilinx/qemu.git?protocol=https?checkout=%{qemu_version}?submodule=dtc?submodule=slirp?submodule=ui/keycodemapdb?submodule=tests/fp/berkeley-softfloat-3?submodule=tests/fp/berkeley-testfloat-3
 
 #
 # The Qemu build instructions. We use 5.x.x Release 1.
-- 
2.34.1

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[PATCH rtems-docs] user/microblaze: Document GPIO driver

[Alex White]

---
 user/bsps/bsps-microblaze.rst | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index 3ad8179..0f28491 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -80,6 +80,15 @@ from the device tree to configure the QSPI NOR JFFS2 driver. 
The following
 device tree node properties are used to configure the QSPI NOR JFFS2 driver:
 ``reg`` and ``interrupts``.
 
+GPIO Driver
+---
+
+The GPIO driver supports the QEMU emulated Xilinx AXI GPIO v2.0. If device tree
+support is enabled in the build configuration, the GPIO driver will use nodes
+that are compatible with `xlnx,xps-gpio-1.00.a` from the device tree to
+configure the GPIO driver. The following device tree node properties are used 
to
+configure the GPIO driver: ``reg``, ``xlnx,is-dual``,
+``xlnx,interrupt-present``, and ``interrupts``.
 
 Running Executables
 ---
@@ -150,6 +159,16 @@ configuration, the console driver will use the node that 
is compatible with
 following device tree node properties are used to configure the console driver:
 ``reg``, ``status``, ``port-number``, and ``interrupts``.
 
+GPIO Driver
+---
+
+The GPIO driver supports the Xilinx AXI GPIO v2.0. If device tree support is
+enabled in the build configuration, the GPIO driver will use nodes that are
+compatible with `xlnx,xps-gpio-1.00.a` from the device tree to configure the
+GPIO driver. The following device tree node properties are used to configure 
the
+GPIO driver: ``reg``, ``xlnx,is-dual``, ``xlnx,interrupt-present``, and
+``interrupts``.
+
 Debugging
 -
 
-- 
2.34.1

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[PATCH] bsps/microblaze: Add device tree support to GPIO driver

[Alex White]

This removes the ability to statically configure a second GPIO device.
Instead, any number of GPIO devices can be configured using the device
tree. If a device tree is not used, a single GPIO device can still be
configured statically.
---
 .../microblaze_fpga/gpio/microblaze-gpio.c| 188 --
 .../include/bsp/microblaze-gpio.h |  91 -
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  12 +-
 .../microblaze_fpga/optgpio2dualchannel.yml   |  16 --
 .../microblaze_fpga/optgpio2enable.yml|  17 --
 .../microblaze_fpga/optgpio2interrupt.yml |  16 --
 .../microblaze_fpga/optgpio2irq.yml   |  18 --
 ...optgpio2baseaddress.yml => optmaxgpio.yml} |  13 +-
 8 files changed, 181 insertions(+), 190 deletions(-)
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
 delete mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
 delete mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml
 rename spec/build/bsps/microblaze/microblaze_fpga/{optgpio2baseaddress.yml => 
optmaxgpio.yml} (54%)

diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c 
b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
index 9025840e32..b8563b1472 100644
--- a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -34,52 +34,87 @@
  */
 
 #include 
+#include 
 
+#include 
 #include 
 #include 
 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include 
+#include 
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
 
-Microblaze_GPIO_context gpio1_context = {
-  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
-  .is_dual = true,
-#else
-  .is_dual = false,
-#endif
-  .irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
-  .has_interrupts = true
-#else
-  .has_interrupts = false
-#endif
-};
-
-#if BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
-Microblaze_GPIO_context gpio2_context = {
-  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO2_BASE,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
-  .is_dual = true,
-#else
-  .is_dual = false,
-#endif
-  .irq = BSP_MICROBLAZE_FPGA_GPIO2_IRQ,
-#ifdef BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
-  .has_interrupts = true
+static Microblaze_GPIO_context gpio_contexts[BSP_MICROBLAZE_FPGA_MAX_GPIO];
+
+static void microblaze_gpio_initialize( void )
+{
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+  const char* compatible = "xlnx,xps-gpio-1.00.a";
+  const void *fdt = bsp_fdt_get();
+  int node = fdt_node_offset_by_compatible( fdt, -1, compatible );
+  int index = 0;
+  
+  /* Initialize up to BSP_MICROBLAZE_FPGA_MAX_GPIO GPIO contexts. */
+  while ( node != -FDT_ERR_NOTFOUND && index < BSP_MICROBLAZE_FPGA_MAX_GPIO ) {
+const uint32_t *prop;
+
+prop = fdt_getprop( fdt, node, "reg", NULL );
+if ( prop != NULL ) {
+  gpio_contexts[index].regs =
+(Microblaze_GPIO_registers *) fdt32_to_cpu( prop[0] );
+}
+
+prop = fdt_getprop( fdt, node, "xlnx,is-dual", NULL );
+if ( prop != NULL ) {
+  gpio_contexts[index].is_dual =
+fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+}
+
+prop = fdt_getprop( fdt, node, "xlnx,interrupt-present", NULL );
+if ( prop != NULL ) {
+  gpio_contexts[index].has_interrupts =
+fdt32_to_cpu( prop[0] ) != 0 ? true : false;
+}
+
+if ( gpio_contexts[index].has_interrupts ) {
+  prop = fdt_getprop( fdt, node, "interrupts", NULL );
+  if ( prop != NULL ) {
+gpio_contexts[index].irq = fdt32_to_cpu( prop[0] );
+  }
+}
+
+node = fdt_node_offset_by_compatible( fdt, node, compatible );
+index++;
+  }
 #else
-  .has_interrupts = false
-#endif
-};
-#endif
+  gpio_contexts[0].regs =
+(Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE;
+  gpio_contexts[0].is_dual = BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL;
+  gpio_contexts[0].irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ;
+  gpio_contexts[0].has_interrupts = BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT;
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+}
+
+RTEMS_SYSINIT_ITEM(
+  microblaze_gpio_initialize,
+  RTEMS_SYSINIT_DEVICE_DRIVERS,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
 
 void microblaze_gpio_set_data_direction(
-  Microblaze_GPIO_context *ctx,
-  uint32_t channel,
-  uint32_t mask
+  unsigned int gpio_index,
+  uint32_t channel,
+  uint32_t mask
 )
 {
+  assert( gpio_index < BSP_MICROBLAZE_FPGA_MAX_GPIO );
+  Microblaze_GPIO_context *ctx = _contexts[gpio_index];
+
   assert( channel == 1 || (ctx->is_dual && channel == 2) );
 
   if ( channel == 1 ) {
@@ -90,10 +125,13 @@ void microblaze_gpio_set_data_direction(
 }
 
 uint32_t microblaze_gpio_get_data_direction(
-  Microblaze_GPIO_context *ctx,
-  uint32_t 

Re: [PATCH v3 1/3] bsps/microblaze: Allow copying FDT from U-Boot

[Alex White]

On Mon, Apr 10, 2023 at 9:25 PM Chris Johns  wrote:
>
> On 10/4/2023 1:47 pm, Alex White wrote:
> >  .../microblaze_invalidate_dcache_range.S  | 104 ++
>
> Why not provide the RTEMS cache API and use that?

Hi Chris,

Good catch. It would be ideal to provide the existing RTEMS cache API. I have 
created ticket #4895 to track that.

Thanks,

Alex
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[PATCH v3 1/3] bsps/microblaze: Allow copying FDT from U-Boot

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 ++
 .../shared/fdt/microblaze-fdt-support.c   |  36 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 6 files changed, 152 insertions(+), 2 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S

diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 410d4483c6..6890f33395 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -49,14 +49,17 @@ extern "C" {
 
 #ifdef BSP_MICROBLAZE_FPGA_USE_FDT
 #define BSP_FDT_IS_SUPPORTED
+#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
 #endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
 
 void microblaze_enable_icache(void);
 void microblaze_enable_dcache(void);
 void microblaze_invalidate_icache(void);
 void microblaze_invalidate_dcache(void);
+void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int 
len);
 
 #ifdef __cplusplus
 }
diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index d56bee3b19..6c7fc3af23 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -30,6 +30,8 @@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+
.globl _crtinit
.align 2
.ent _crtinit
@@ -75,7 +77,9 @@ _crtinit:
brlid   r15, __init  /* Invoke 
language initialization functions */
nop
 #endif /* __rtems__ */
-
+#ifdef BSP_START_COPY_FDT_FROM_U_BOOT  /* Boot loaders may pass the device 
tree in r5 */
+   brlid   r15, bsp_fdt_copy  /* Do not touch r5 until 
bsp_fdt_copy() is called */
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
addir6, r0, 0  /* 
Initialize argc = 1 and argv = NULL and envp = NULL  */
addir7, r0, 0
 #ifndef __rtems__
diff --git 
a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S 
b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
new file mode 100644
index 00..89d5fff16b
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
@@ -0,0 +1,104 @@
+/**
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+/**
+*
+*
+* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+*Invalidate a Dcache range
+*
+*Parameters:
+*   'cacheaddr' - address in the Dcache where invalidation begins
+*  'len'   - length (in bytes) worth of Dcache to be invalidated
+*
+*
+***/
+
+#include 
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE0x0080
+#define MICROBLAZE_MSR_INTR_ENABLE  0x0002
+
+#ifndef XPAR_MICROBLAZE_USE_DCACHE
+#define XPAR_MICROBLAZE_USE_DCACHE 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
+#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+   .text
+   .globl  microblaze_invalidate_dcache_range
+   .entmicroblaze_invalidate_dcache_range
+   .align  2
+
+microblaze_invalidate_dcache_range:
+#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
+
+#ifdef MB_VERSION_LT_v720   /* Disable 
Dcache and interrupts before invalidating */
+   mfs r9, rmsr
+   andir10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | 
MICROBLAZE_MSR_INTR_ENABLE)
+   mts rmsr, r10
+#endif
+
+BEQIr6, L_done  /* Skip loop 
if size is zero */
+
+ADDr6, r5, r6  /* Compute end 
address */
+ADDIK   r6, r6, -1
+
+ANDIr6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
end down to cache line */
+ANDIr5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0   /* Use a 
different scheme for MB 

[PATCH v3 2/3] bsps/microblaze: Add support for multiple UARTs

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |   2 +
 .../microblaze_fpga/console/console-io.c  | 205 --
 bsps/microblaze/shared/dev/serial/uartlite.c  |   8 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  10 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optmaxuarts.yml   |  21 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 9 files changed, 275 insertions(+), 30 deletions(-)
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 2fda3796b3..009f416508 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -49,8 +49,10 @@ typedef struct {
   rtems_termios_device_context base;
   uintptr_t address;
   uint32_t initial_baud;
+  uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   bool transmitting;
+  uint32_t irq;
 #endif
 } uart_lite_context;
 
diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c 
b/bsps/microblaze/microblaze_fpga/console/console-io.c
index 81c4e73690..c4de3800cc 100644
--- a/bsps/microblaze/microblaze_fpga/console/console-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/console-io.c
@@ -34,39 +34,200 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
 
+#include 
+#include 
+#include 
 #include 
+#include 
 
-uart_lite_context microblaze_qemu_uart_context = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
-  .initial_baud = 115200
-};
-
-static bool fill_uart_base(rtems_termios_device_context *context)
-{
-  uint32_t mblaze_uart_base;
-
-  mblaze_uart_base = try_get_prop_from_device_tree(
-"xlnx,xps-uartlite-1.00.a",
-"reg",
-BSP_MICROBLAZE_FPGA_UART_BASE
-  );
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include 
+#include 
+#endif
 
-  microblaze_qemu_uart_context.address = mblaze_uart_base;
+#include 
 
-  return true;
-}
+#ifndef BSP_MICROBLAZE_FPGA_USE_FDT
+static uart_lite_context uart_lite_instances[] = {
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART_IRQ
+#endif
+  }
+};
 
 const console_device console_device_table[] = {
   {
 .device_file = "/dev/ttyS0",
-.probe = fill_uart_base,
 .handler = _uart_fns,
-.context = _qemu_uart_context.base
+.context = _lite_instances[0].base
   }
 };
 
 const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table );
+#else
+static uart_lite_context uart_lite_instances[BSP_MICROBLAZE_FPGA_MAX_UARTS];
+console_device *dynamic_console_device_table;
+size_t dynamic_console_device_count;
+
+/* Override the console_device_table and console_device_count */
+#define console_device_table dynamic_console_device_table
+#define console_device_count dynamic_console_device_count
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
+
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+static int microblaze_fpga_get_stdout_node(const void *fdt)
+{
+  int node;
+  int len;
+  int offset;
+  const char *console;
+  const char *q;
+
+  node = fdt_path_offset( fdt, "/chosen" );
+  if ( node < 0 ) {
+return 0;
+  }
+
+  console = fdt_getprop( fdt, node, "stdout-path", NULL );
+  if ( console == NULL ) {
+return 0;
+  }
+
+  q = strchr(console, ':');
+  if ( !q ) {
+return 0;
+  }
+  
+  len = q - console;
+
+  /* Get the node specified by stdout-path */
+  offset = fdt_path_offset_namelen( fdt, console, len );
+  if (offset < 0) {
+return 0;
+  }
+  
+  return offset;
+}
+
+static void initialize_uart_arrays(uint32_t max_uarts) {
+  dynamic_console_device_table = calloc(max_uarts, sizeof(console_device));
+  dynamic_console_device_count = max_uarts;
+  
+  for (uint32_t i = 0; i < max_uarts; i++) {
+rtems_termios_device_context_initialize(_lite_instances[i].base, 
"UARTLITE");
+uart_lite_instances[i].initial_baud = 115200;
+
+dynamic_console_device_table[i].device_file = malloc(11);
+snprintf((char *)console_device_table[i].device_file, 11, "/dev/ttyS%u", 
i);
+dynamic_console_device_table[i].handler = _uart_fns;
+dynamic_console_device_table[i].context = _lite_instances[i].base;
+  }
+}
+#endif 
+
+rtems_device_driver console_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  

[PATCH v3 0/3] bsps/microblaze: FDT support and UART driver improvements

[Alex White]

v3:
- Support multiple UARTs only if the BSP is configured to use FDT. This allows
  for flexibility since the user now just has to specify the maximum number of
  UARTs, and the UART configurations will be read from the FDT. In the previous
  version of this patch set, the extra UARTs were all configured at build time
  which was not very flexible and required adding a lot of extra BSP options.

v2:
- Allow UART driver to fill the transmit FIFO rather than just sending one byte
  at a time.

Maldonado, Sergio E. (GSFC-580.0) (3):
  bsps/microblaze: Allow copying FDT from U-Boot
  bsps/microblaze: Add support for multiple UARTs
  bsps/microblaze: Fix UART transmit interrupt

 bsps/microblaze/include/dev/serial/uartlite.h |   4 +
 .../microblaze_fpga/console/console-io.c  | 205 --
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 +
 bsps/microblaze/shared/dev/serial/uartlite.c  |  30 ++-
 .../shared/fdt/microblaze-fdt-support.c   |  36 ++-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  14 ++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +-
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optmaxuarts.yml   |  21 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 13 files changed, 446 insertions(+), 37 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optmaxuarts.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml

-- 
2.34.1

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[PATCH v3 3/3] bsps/microblaze: Fix UART transmit interrupt

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |  2 ++
 bsps/microblaze/shared/dev/serial/uartlite.c  | 22 ++-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 009f416508..f58ae92ef8 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -51,7 +51,9 @@ typedef struct {
   uint32_t initial_baud;
   uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  struct rtems_termios_tty *tty;
   bool transmitting;
+  size_t tx_queued;
   uint32_t irq;
 #endif
 } uart_lite_context;
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index e2007ee24a..611c339371 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -48,8 +48,11 @@ static void microblaze_uart_interrupt( void *arg )
 rtems_termios_enqueue_raw_characters( tty, , 1 );
   }
 
-  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx->address ) ) {
-rtems_termios_dequeue_characters( tty, 1 );
+  if ( ctx->transmitting && XUartLite_IsTransmitEmpty( ctx->address ) ) {
+size_t sent = ctx->tx_queued;
+ctx->transmitting = false;
+ctx->tx_queued = 0;
+rtems_termios_dequeue_characters( tty, sent );
   }
 }
 #endif
@@ -81,6 +84,8 @@ static bool uart_first_open(
   if ( sc != RTEMS_SUCCESSFUL ) {
 return false;
   }
+
+  ctx->tty = tty;
 #endif
 
   return true;
@@ -120,10 +125,17 @@ static void uart_write(
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   if ( n > 0 ) {
+size_t remaining = n;
+const char *p = [0];
+
+while (!XUartLite_IsTransmitFull( ctx->address ) && remaining > 0) {
+  XUartLite_SendByte( ctx->address, *p );
+  p++;
+  remaining--;
+}
+
 ctx->transmitting = true;
-XUartLite_SendByte( ctx->address, s[0] );
-  } else {
-ctx->transmitting = false;
+ctx->tx_queued = n - remaining;
   }
 #else
   size_t i = 0;
-- 
2.34.1

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[PATCH 1/2] user/microblaze: Document QSPI NOR JFFS2 driver

[Alex White]

---
 user/bsps/bsps-microblaze.rst | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index 32aad90..2a8a6dd 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -61,6 +61,16 @@ to include it in the BSP build.
   BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c
 
 
+QSPI NOR JFFS2 Driver
+-
+
+The QSPI NOR JFFS2 driver supports the QEMU emulated n25q512a11 QSPI NOR flash
+device. It is initialized to a page size of 256 bytes and a sector size of 64
+KiB. If device tree support is enabled in the build configuration, the QSPI NOR
+JFFS2 driver will use the node that is compatible with `xlnx,xps-spi-2.00.a`
+from the device tree to configure the QSPI NOR JFFS2 driver.
+
+
 Running Executables
 ---
 
-- 
2.34.1

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[PATCH 2/2] user/microblaze: Document device tree support

[Alex White]

---
 user/bsps/bsps-microblaze.rst | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index 2a8a6dd..864b3c8 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -21,13 +21,21 @@ Clock Driver
 
 
 The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is
-implemented as a simple downcounter.
+implemented as a simple downcounter. If device tree support is enabled in the
+build configuration, the clock driver will use the node that is compatible with
+`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The
+following device tree node properties are used to configure the clock driver:
+``reg``, ``clock-frequency``, and ``interrupts``.
 
 Console Driver
 --
 
 The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is
-initialized to a baud rate of 115200.
+initialized to a baud rate of 115200. If device tree support is enabled in the
+build configuration, the console driver will use the node that is compatible
+with `xlnx,xps-uartlite-1.00.a` from the device tree to configure the console.
+The following device tree node properties are used to configure the console
+driver: ``reg``, ``status``, ``port-number``, and ``interrupts``.
 
 Network Driver
 --
@@ -68,7 +76,9 @@ The QSPI NOR JFFS2 driver supports the QEMU emulated 
n25q512a11 QSPI NOR flash
 device. It is initialized to a page size of 256 bytes and a sector size of 64
 KiB. If device tree support is enabled in the build configuration, the QSPI NOR
 JFFS2 driver will use the node that is compatible with `xlnx,xps-spi-2.00.a`
-from the device tree to configure the QSPI NOR JFFS2 driver.
+from the device tree to configure the QSPI NOR JFFS2 driver. The following
+device tree node properties are used to configure the QSPI NOR JFFS2 driver:
+``reg`` and ``interrupts``.
 
 
 Running Executables
@@ -124,12 +134,21 @@ Clock Driver
 
 
 The clock driver supports the Xilinx AXI Timer v2.0. It is implemented as a
-simple downcounter.
+simple downcounter. If device tree support is enabled in the
+build configuration, the clock driver will use the node that is compatible with
+`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The
+following device tree node properties are used to configure the clock driver:
+``reg``, ``clock-frequency``, and ``interrupts``.
 
 Console Driver
 --
 
-The console driver supports the Xilinx AXI UART Lite v2.0.
+The console driver supports the Xilinx AXI UART Lite v2.0. It is initialized to
+a baud rate of 115200. If device tree support is enabled in the build
+configuration, the console driver will use the node that is compatible with
+`xlnx,xps-uartlite-1.00.a` from the device tree to configure the console. The
+following device tree node properties are used to configure the console driver:
+``reg``, ``status``, ``port-number``, and ``interrupts``.
 
 Debugging
 -
-- 
2.34.1

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[PATCH v2 1/3] bsps/microblaze: Allow copying FDT from U-Boot

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 ++
 .../shared/fdt/microblaze-fdt-support.c   |  36 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 6 files changed, 152 insertions(+), 2 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S

diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 410d4483c6..6890f33395 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -49,14 +49,17 @@ extern "C" {
 
 #ifdef BSP_MICROBLAZE_FPGA_USE_FDT
 #define BSP_FDT_IS_SUPPORTED
+#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
 #endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
 
 void microblaze_enable_icache(void);
 void microblaze_enable_dcache(void);
 void microblaze_invalidate_icache(void);
 void microblaze_invalidate_dcache(void);
+void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int 
len);
 
 #ifdef __cplusplus
 }
diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index d56bee3b19..6c7fc3af23 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -30,6 +30,8 @@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+
.globl _crtinit
.align 2
.ent _crtinit
@@ -75,7 +77,9 @@ _crtinit:
brlid   r15, __init  /* Invoke 
language initialization functions */
nop
 #endif /* __rtems__ */
-
+#ifdef BSP_START_COPY_FDT_FROM_U_BOOT  /* Boot loaders may pass the device 
tree in r5 */
+   brlid   r15, bsp_fdt_copy  /* Do not touch r5 until 
bsp_fdt_copy() is called */
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
addir6, r0, 0  /* 
Initialize argc = 1 and argv = NULL and envp = NULL  */
addir7, r0, 0
 #ifndef __rtems__
diff --git 
a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S 
b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
new file mode 100644
index 00..89d5fff16b
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
@@ -0,0 +1,104 @@
+/**
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+/**
+*
+*
+* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+*Invalidate a Dcache range
+*
+*Parameters:
+*   'cacheaddr' - address in the Dcache where invalidation begins
+*  'len'   - length (in bytes) worth of Dcache to be invalidated
+*
+*
+***/
+
+#include 
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE0x0080
+#define MICROBLAZE_MSR_INTR_ENABLE  0x0002
+
+#ifndef XPAR_MICROBLAZE_USE_DCACHE
+#define XPAR_MICROBLAZE_USE_DCACHE 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
+#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+   .text
+   .globl  microblaze_invalidate_dcache_range
+   .entmicroblaze_invalidate_dcache_range
+   .align  2
+
+microblaze_invalidate_dcache_range:
+#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
+
+#ifdef MB_VERSION_LT_v720   /* Disable 
Dcache and interrupts before invalidating */
+   mfs r9, rmsr
+   andir10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | 
MICROBLAZE_MSR_INTR_ENABLE)
+   mts rmsr, r10
+#endif
+
+BEQIr6, L_done  /* Skip loop 
if size is zero */
+
+ADDr6, r5, r6  /* Compute end 
address */
+ADDIK   r6, r6, -1
+
+ANDIr6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
end down to cache line */
+ANDIr5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0   /* Use a 
different scheme for MB 

[PATCH v2 0/3] bsps/microblaze: FDT support and UART driver improvements

[Alex White]

v2:
- Allow UART driver to fill the transmit FIFO rather than just sending one byte
  at a time.

Maldonado, Sergio E. (GSFC-580.0) (3):
  bsps/microblaze: Allow copying FDT from U-Boot
  bsps/microblaze: Add support for multiple UARTs
  bsps/microblaze: Fix UART transmit interrupt

 bsps/microblaze/include/dev/serial/uartlite.h |   4 +
 .../microblaze_fpga/console/console-io.c  | 229 --
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 
 bsps/microblaze/shared/dev/serial/uartlite.c  |  30 ++-
 .../shared/fdt/microblaze-fdt-support.c   |  36 ++-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  36 +++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +-
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optuart1irq.yml   |  20 ++
 .../optuart1litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart2irq.yml   |  20 ++
 .../optuart2litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart3irq.yml   |  20 ++
 .../optuart3litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart4irq.yml   |  20 ++
 .../optuart4litebaseaddress.yml   |  20 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 .../microblaze_fpga/optuseuart1.yml   |  17 ++
 .../microblaze_fpga/optuseuart2.yml   |  17 ++
 .../microblaze_fpga/optuseuart3.yml   |  17 ++
 .../microblaze_fpga/optuseuart4.yml   |  17 ++
 24 files changed, 705 insertions(+), 31 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart1litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart2irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart2litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart3irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart3litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart4irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart4litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart1.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart2.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart3.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart4.yml

-- 
2.34.1

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[PATCH v2 3/3] bsps/microblaze: Fix UART transmit interrupt

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |  2 ++
 bsps/microblaze/shared/dev/serial/uartlite.c  | 22 ++-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 009f416508..f58ae92ef8 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -51,7 +51,9 @@ typedef struct {
   uint32_t initial_baud;
   uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  struct rtems_termios_tty *tty;
   bool transmitting;
+  size_t tx_queued;
   uint32_t irq;
 #endif
 } uart_lite_context;
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index e2007ee24a..611c339371 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -48,8 +48,11 @@ static void microblaze_uart_interrupt( void *arg )
 rtems_termios_enqueue_raw_characters( tty, , 1 );
   }
 
-  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx->address ) ) {
-rtems_termios_dequeue_characters( tty, 1 );
+  if ( ctx->transmitting && XUartLite_IsTransmitEmpty( ctx->address ) ) {
+size_t sent = ctx->tx_queued;
+ctx->transmitting = false;
+ctx->tx_queued = 0;
+rtems_termios_dequeue_characters( tty, sent );
   }
 }
 #endif
@@ -81,6 +84,8 @@ static bool uart_first_open(
   if ( sc != RTEMS_SUCCESSFUL ) {
 return false;
   }
+
+  ctx->tty = tty;
 #endif
 
   return true;
@@ -120,10 +125,17 @@ static void uart_write(
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   if ( n > 0 ) {
+size_t remaining = n;
+const char *p = [0];
+
+while (!XUartLite_IsTransmitFull( ctx->address ) && remaining > 0) {
+  XUartLite_SendByte( ctx->address, *p );
+  p++;
+  remaining--;
+}
+
 ctx->transmitting = true;
-XUartLite_SendByte( ctx->address, s[0] );
-  } else {
-ctx->transmitting = false;
+ctx->tx_queued = n - remaining;
   }
 #else
   size_t i = 0;
-- 
2.34.1

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[PATCH v2 2/3] bsps/microblaze: Add support for multiple UARTs

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |   2 +
 .../microblaze_fpga/console/console-io.c  | 229 --
 bsps/microblaze/shared/dev/serial/uartlite.c  |   8 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  32 +++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optuart1irq.yml   |  20 ++
 .../optuart1litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart2irq.yml   |  20 ++
 .../optuart2litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart3irq.yml   |  20 ++
 .../optuart3litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart4irq.yml   |  20 ++
 .../optuart4litebaseaddress.yml   |  20 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 .../microblaze_fpga/optuseuart1.yml   |  17 ++
 .../microblaze_fpga/optuseuart2.yml   |  17 ++
 .../microblaze_fpga/optuseuart3.yml   |  17 ++
 .../microblaze_fpga/optuseuart4.yml   |  17 ++
 20 files changed, 534 insertions(+), 24 deletions(-)
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart1litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart2irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart2litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart3irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart3litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart4irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart4litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart1.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart2.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart3.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart4.yml

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 2fda3796b3..009f416508 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -49,8 +49,10 @@ typedef struct {
   rtems_termios_device_context base;
   uintptr_t address;
   uint32_t initial_baud;
+  uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   bool transmitting;
+  uint32_t irq;
 #endif
 } uart_lite_context;
 
diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c 
b/bsps/microblaze/microblaze_fpga/console/console-io.c
index 81c4e73690..72c3a0c989 100644
--- a/bsps/microblaze/microblaze_fpga/console/console-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/console-io.c
@@ -34,38 +34,235 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+#include 
+
+#include 
 #include 
-#include 
+#include 
+#include 
 #include 
 
-#include 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include 
+#include 
+#endif
 
-uart_lite_context microblaze_qemu_uart_context = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
-  .initial_baud = 115200
+#include 
+
+static uart_lite_context uart_lite_instances[] = {
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART1" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART1_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART1
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART1_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART2" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART2_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART2
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART2_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART3" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART3_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART3
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART3_IRQ
+#endif
+  },
+  {
+.base 

Re: [PATCH 2/3] bsps/microblaze: Add support for multiple UARTs

[Alex White]

On Thu, Mar 30, 2023 at 5:54 PM Chris Johns  wrote:
>
> On 31/3/2023 2:55 am, Alex White wrote:
> > On Wed, Mar 29, 2023 at 11:04 PM Chris Johns  wrote:
> >>
> >> On 30/3/2023 12:26 pm, Sam Price wrote:
> >>> Same IP as the regular KCU105.
> >>> The current uart ip is dependent on the fpga.
> >>> I don't believe this modifies the kcu105 bsp, but allows other bsps to
> >>> support up to 4 uarts.
> >>
> >> I am not sure if this patch is OK. If the UART driver is needed for a 
> >> console
> >> does that limits how it's configuration can be handled? If so that means 
> >> the
> >> patch is OK. Adding options for a user's custom IP is questionable.
> >
> > This patch allows the user to use multiple instances of the same UART IP 
> > (AXI UART Lite v2.0) which is currently the only IP supported by the BSP.
>
> What happens if a user needs more than 4 ports? I was discussing such a 
> project
> recently with someone and Microblaze may be an option?
>
> I do not have a better solution at the moment so I am just understand the what
> we accept and why plus how we manage it.

I see your point. A user could come along needing 5, 6, or 7 ports. It's not
sustainable to keep adding ports to the driver like this. It doesn't scale well
at all.

We probably need a build option for the maximum number of ports and a way to
configure the ports at runtime. This should be easy if the user is using a
device tree, but if they aren't, they need a way to specify the configuration of
each port.

It's late so I can't think of a good way to do this right now. Maybe only allow
some small number of ports (one?) to be specified if the user isn't using a
device tree?

Alex
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Re: [PATCH 2/3] bsps/microblaze: Add support for multiple UARTs

[Alex White]

On Wed, Mar 29, 2023 at 11:04 PM Chris Johns  wrote:
>
> On 30/3/2023 12:26 pm, Sam Price wrote:
> > Same IP as the regular KCU105.
> > The current uart ip is dependent on the fpga.
> > I don't believe this modifies the kcu105 bsp, but allows other bsps to
> > support up to 4 uarts.
>
> I am not sure if this patch is OK. If the UART driver is needed for a console
> does that limits how it's configuration can be handled? If so that means the
> patch is OK. Adding options for a user's custom IP is questionable.

This patch allows the user to use multiple instances of the same UART IP (AXI 
UART Lite v2.0) which is currently the only IP supported by the BSP.

Alex
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[PATCH 2/3] bsps/microblaze: Add support for multiple UARTs

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |   2 +
 .../microblaze_fpga/console/console-io.c  | 229 --
 bsps/microblaze/shared/dev/serial/uartlite.c  |   8 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  32 +++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optuart1irq.yml   |  20 ++
 .../optuart1litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart2irq.yml   |  20 ++
 .../optuart2litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart3irq.yml   |  20 ++
 .../optuart3litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart4irq.yml   |  20 ++
 .../optuart4litebaseaddress.yml   |  20 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 .../microblaze_fpga/optuseuart1.yml   |  17 ++
 .../microblaze_fpga/optuseuart2.yml   |  17 ++
 .../microblaze_fpga/optuseuart3.yml   |  17 ++
 .../microblaze_fpga/optuseuart4.yml   |  17 ++
 20 files changed, 534 insertions(+), 24 deletions(-)
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart1litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart2irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart2litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart3irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart3litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart4irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart4litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart1.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart2.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart3.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart4.yml

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 2fda3796b3..009f416508 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -49,8 +49,10 @@ typedef struct {
   rtems_termios_device_context base;
   uintptr_t address;
   uint32_t initial_baud;
+  uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   bool transmitting;
+  uint32_t irq;
 #endif
 } uart_lite_context;
 
diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c 
b/bsps/microblaze/microblaze_fpga/console/console-io.c
index 81c4e73690..72c3a0c989 100644
--- a/bsps/microblaze/microblaze_fpga/console/console-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/console-io.c
@@ -34,38 +34,235 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+#include 
+
+#include 
 #include 
-#include 
+#include 
+#include 
 #include 
 
-#include 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include 
+#include 
+#endif
 
-uart_lite_context microblaze_qemu_uart_context = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
-  .initial_baud = 115200
+#include 
+
+static uart_lite_context uart_lite_instances[] = {
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART1" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART1_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART1
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART1_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART2" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART2_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART2
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART2_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART3" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART3_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART3
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART3_IRQ
+#endif
+  },
+  {
+.base 

[PATCH 3/3] bsps/microblaze: Fix UART transmit interrupt

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |  2 +-
 bsps/microblaze/shared/dev/serial/uartlite.c  | 10 +++---
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 009f416508..c281310d56 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -51,7 +51,7 @@ typedef struct {
   uint32_t initial_baud;
   uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
-  bool transmitting;
+  struct rtems_termios_tty *tty;
   uint32_t irq;
 #endif
 } uart_lite_context;
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index e2007ee24a..f1b3c013a0 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -47,10 +47,6 @@ static void microblaze_uart_interrupt( void *arg )
 char c = (char) XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET );
 rtems_termios_enqueue_raw_characters( tty, , 1 );
   }
-
-  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx->address ) ) {
-rtems_termios_dequeue_characters( tty, 1 );
-  }
 }
 #endif
 
@@ -81,6 +77,8 @@ static bool uart_first_open(
   if ( sc != RTEMS_SUCCESSFUL ) {
 return false;
   }
+
+  ctx->tty = tty;
 #endif
 
   return true;
@@ -120,10 +118,8 @@ static void uart_write(
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   if ( n > 0 ) {
-ctx->transmitting = true;
 XUartLite_SendByte( ctx->address, s[0] );
-  } else {
-ctx->transmitting = false;
+rtems_termios_dequeue_characters( ctx->tty, 1 );
   }
 #else
   size_t i = 0;
-- 
2.34.1

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[PATCH 1/3] bsps/microblaze: Allow copying FDT from U-Boot

[Alex White]

From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 ++
 .../shared/fdt/microblaze-fdt-support.c   |  36 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 6 files changed, 152 insertions(+), 2 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S

diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 410d4483c6..6890f33395 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -49,14 +49,17 @@ extern "C" {
 
 #ifdef BSP_MICROBLAZE_FPGA_USE_FDT
 #define BSP_FDT_IS_SUPPORTED
+#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
 #endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
 
 void microblaze_enable_icache(void);
 void microblaze_enable_dcache(void);
 void microblaze_invalidate_icache(void);
 void microblaze_invalidate_dcache(void);
+void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int 
len);
 
 #ifdef __cplusplus
 }
diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index d56bee3b19..6c7fc3af23 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -30,6 +30,8 @@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+
.globl _crtinit
.align 2
.ent _crtinit
@@ -75,7 +77,9 @@ _crtinit:
brlid   r15, __init  /* Invoke 
language initialization functions */
nop
 #endif /* __rtems__ */
-
+#ifdef BSP_START_COPY_FDT_FROM_U_BOOT  /* Boot loaders may pass the device 
tree in r5 */
+   brlid   r15, bsp_fdt_copy  /* Do not touch r5 until 
bsp_fdt_copy() is called */
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
addir6, r0, 0  /* 
Initialize argc = 1 and argv = NULL and envp = NULL  */
addir7, r0, 0
 #ifndef __rtems__
diff --git 
a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S 
b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
new file mode 100644
index 00..89d5fff16b
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
@@ -0,0 +1,104 @@
+/**
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+/**
+*
+*
+* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+*Invalidate a Dcache range
+*
+*Parameters:
+*   'cacheaddr' - address in the Dcache where invalidation begins
+*  'len'   - length (in bytes) worth of Dcache to be invalidated
+*
+*
+***/
+
+#include 
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE0x0080
+#define MICROBLAZE_MSR_INTR_ENABLE  0x0002
+
+#ifndef XPAR_MICROBLAZE_USE_DCACHE
+#define XPAR_MICROBLAZE_USE_DCACHE 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
+#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+   .text
+   .globl  microblaze_invalidate_dcache_range
+   .entmicroblaze_invalidate_dcache_range
+   .align  2
+
+microblaze_invalidate_dcache_range:
+#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
+
+#ifdef MB_VERSION_LT_v720   /* Disable 
Dcache and interrupts before invalidating */
+   mfs r9, rmsr
+   andir10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | 
MICROBLAZE_MSR_INTR_ENABLE)
+   mts rmsr, r10
+#endif
+
+BEQIr6, L_done  /* Skip loop 
if size is zero */
+
+ADDr6, r5, r6  /* Compute end 
address */
+ADDIK   r6, r6, -1
+
+ANDIr6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
end down to cache line */
+ANDIr5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0   /* Use a 
different scheme for MB 

[PATCH rtems-source-builder] 6: Update MicroBlaze gdb to 12.1

[Alex White]

GDB 11.2 fails to compile on Ubuntu 22.04 for MicroBlaze.
---
 rtems/config/6/rtems-microblaze.bset | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtems/config/6/rtems-microblaze.bset 
b/rtems/config/6/rtems-microblaze.bset
index ea59313..e05fd7b 100644
--- a/rtems/config/6/rtems-microblaze.bset
+++ b/rtems/config/6/rtems-microblaze.bset
@@ -13,7 +13,7 @@
 
 devel/expat-2.4.8-1
 devel/gmp-6.2.1
-tools/rtems-gdb-11.2
+tools/rtems-gdb-12.1
 
 tools/rtems-xilinx-binutils-2.36
 tools/rtems-xilinx-gcc-10-newlib-head
-- 
2.34.1

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[PATCH] bsps/microblaze: Add AXI GPIO driver

[Alex White]

---
 .../microblaze_fpga/gpio/microblaze-gpio.c| 261 ++
 .../include/bsp/microblaze-gpio.h | 321 ++
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  18 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
 .../microblaze_fpga/optgpio1baseaddress.yml   |  20 ++
 .../microblaze_fpga/optgpio1dualchannel.yml   |  17 +
 .../microblaze_fpga/optgpio1interrupt.yml |  17 +
 .../microblaze_fpga/optgpio1irq.yml   |  19 ++
 .../microblaze_fpga/optgpio2baseaddress.yml   |  20 ++
 .../microblaze_fpga/optgpio2dualchannel.yml   |  17 +
 .../microblaze_fpga/optgpio2enable.yml|  18 +
 .../microblaze_fpga/optgpio2interrupt.yml |  17 +
 .../microblaze_fpga/optgpio2irq.yml   |  19 ++
 13 files changed, 766 insertions(+)
 create mode 100644 bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
 create mode 100644 
bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1baseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1dualchannel.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio1interrupt.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2baseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2dualchannel.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2enable.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optgpio2interrupt.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optgpio2irq.yml

diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c 
b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
new file mode 100644
index 00..9025840e32
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI GPIO implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+Microblaze_GPIO_context gpio1_context = {
+  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO1_BASE,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO1_DUAL_CHANNEL
+  .is_dual = true,
+#else
+  .is_dual = false,
+#endif
+  .irq = BSP_MICROBLAZE_FPGA_GPIO1_IRQ,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO1_INTERRUPT
+  .has_interrupts = true
+#else
+  .has_interrupts = false
+#endif
+};
+
+#if BSP_MICROBLAZE_FPGA_GPIO2_ENABLED
+Microblaze_GPIO_context gpio2_context = {
+  .regs = (Microblaze_GPIO_registers *) BSP_MICROBLAZE_FPGA_GPIO2_BASE,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_DUAL_CHANNEL
+  .is_dual = true,
+#else
+  .is_dual = false,
+#endif
+  .irq = BSP_MICROBLAZE_FPGA_GPIO2_IRQ,
+#ifdef BSP_MICROBLAZE_FPGA_GPIO2_INTERRUPT
+  .has_interrupts = true
+#else
+  .has_interrupts = false
+#endif
+};
+#endif
+
+void microblaze_gpio_set_data_direction(
+  Microblaze_GPIO_context *ctx,
+  uint32_t channel,
+  uint32_t mask
+)
+{
+  assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+  if ( channel == 1 ) {
+ctx->regs->gpio_tri = mask;
+  } else if ( ctx->is_dual && channel == 2 ) {
+ctx->regs->gpio2_tri = mask;
+  }
+}
+
+uint32_t microblaze_gpio_get_data_direction(
+  Microblaze_GPIO_context *ctx,
+  uint32_t channel
+)
+{
+  assert( channel == 1 || (ctx->is_dual && channel == 2) );
+
+  

[PATCH 3/3] bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driver

[Alex White]

---
 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h  |   1 +
 .../include/bsp/jffs2_xqspipsu.h  |  62 ++
 bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c   | 186 ++
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |   2 +
 .../aarch64/xilinx-zynqmp/objjffs2qspinor.yml |  22 +++
 5 files changed, 273 insertions(+)
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objjffs2qspinor.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
index 3ffb01d1df..2cbe99f863 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
@@ -53,6 +53,7 @@ extern "C" {
 /* Interrupts vectors */
 #define BSP_TIMER_VIRT_PPI 27
 #define BSP_TIMER_PHYS_NS_PPI 30
+#define ZYNQMP_IRQ_QSPI 47
 #define ZYNQMP_IRQ_I2C_0 49
 #define ZYNQMP_IRQ_I2C_1 50
 #define ZYNQMP_IRQ_UART_0 54
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h 
b/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
new file mode 100644
index 00..ac957bb686
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief XilinxZynqMP QSPI JFFS2 flash driver definitions
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_XILINX_ZYNQMP_JFFS2_XQSPIPSU_H
+#define LIBBSP_XILINX_ZYNQMP_JFFS2_XQSPIPSU_H
+
+#include "xqspipsu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Mount jffs2 filesystem.
+ *
+ * @param[in] mount_dir The directory to mount the filesystem at.
+ * @param[in] qspipsu_ptr A pointer to an initialized QSPI instance.
+ *
+ * @retval 0 Successful operation. Negative number otherwise.
+ */
+int xilinx_zynqmp_nor_jffs2_initialize(
+  const char *mount_dir,
+  XQspiPsu *qspipsu_ptr
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_XILINX_ZYNQMP_JFFS2_XQSPIPSU_H */
diff --git a/bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c 
b/bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c
new file mode 100644
index 00..f647c19ec1
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY 

[PATCH 2/3] bsps: Add Xilinx GQSPI flash helper

[Alex White]

This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
---
 bsps/include/dev/spi/xqspipsu-flash-helper.h |   81 +
 bsps/shared/dev/spi/xqspipsu-flash-helper.c  | 2005 ++
 spec/build/bsps/objqspipsu.yml   |   32 +
 spec/build/bsps/optxpssysctrlbaseaddress.yml |   18 +
 4 files changed, 2136 insertions(+)
 create mode 100644 bsps/include/dev/spi/xqspipsu-flash-helper.h
 create mode 100644 bsps/shared/dev/spi/xqspipsu-flash-helper.c
 create mode 100644 spec/build/bsps/objqspipsu.yml
 create mode 100644 spec/build/bsps/optxpssysctrlbaseaddress.yml

diff --git a/bsps/include/dev/spi/xqspipsu-flash-helper.h 
b/bsps/include/dev/spi/xqspipsu-flash-helper.h
new file mode 100644
index 00..075f7f826d
--- /dev/null
+++ b/bsps/include/dev/spi/xqspipsu-flash-helper.h
@@ -0,0 +1,81 @@
+/**
+* Copyright (C) 2018 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+
+#include "xqspipsu.h"
+
+int QspiPsu_NOR_Initialize(
+  XQspiPsu *QspiPsuInstancePtr,
+  u16 QspiPsuIntrId
+);
+
+/*/
+/**
+ *
+ * This function erases the sectors in the  serial Flash connected to the
+ * QSPIPSU interface.
+ *
+ * @param  QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ * @param  Address contains the address of the first sector which needs to
+ * be erased.
+ * @param  ByteCount contains the total size to be erased.
+ *
+ * @return XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ * @note   None.
+ *
+ 
**/
+int QspiPsu_NOR_Erase(
+  XQspiPsu *QspiPsuPtr,
+  u32 Address,
+  u32 ByteCount
+);
+
+/*/
+/**
+ *
+ * This function writes to the  serial Flash connected to the QSPIPSU 
interface.
+ * All the data put into the buffer must be in the same page of the device with
+ * page boundaries being on 256 byte boundaries.
+ *
+ * @param  QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ * @param  Address contains the address to write data to in the Flash.
+ * @param  ByteCount contains the number of bytes to write.
+ * @param  WriteBfrPtr is pointer to the write buffer (which is to be 
transmitted)
+ *
+ * @return XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ * @note   None.
+ *
+ 
**/
+int QspiPsu_NOR_Write(
+  XQspiPsu *QspiPsuPtr,
+  u32 Address,
+  u32 ByteCount,
+   u8 *WriteBfrPtr
+);
+
+/*/
+/**
+ *
+ * This function performs a read. Default setting is in DMA mode.
+ *
+ * @param  QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ * @param  Address contains the address of the first sector which needs to
+ * be erased.
+ * @param  ByteCount contains the total size to be erased.
+ * @param  ReadBfrPtr is pointer to the read buffer to which valid 
received data
+ * should be written
+ *
+ * @return XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ * @note   None.
+ *
+ 
**/
+int QspiPsu_NOR_Read(
+  XQspiPsu *QspiPsuPtr,
+  u32 Address,
+  u32 ByteCount,
+  u8 **ReadBfrPtr
+);
diff --git a/bsps/shared/dev/spi/xqspipsu-flash-helper.c 
b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
new file mode 100644
index 00..ae9223bef6
--- /dev/null
+++ b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
@@ -0,0 +1,2005 @@
+/**
+* Copyright (C) 2018 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+
+/**
+ * @file xqspipsu_flash_helper.c
+ * 
+ * This file contains flash helper functions for the QSPIPSU driver. It
+ * consists of modified functions from Xilinx's flash example in
+ * examples/xqspipsu_generic_flash_interrupt_example.c of the qspipsu driver.
+ *
+ */
+
+#include "xqspipsu_flash_config.h"
+#include "xqspipsu-flash-helper.h"
+
+#include 
+
+/*
+ * Number of flash pages to be written.
+ */
+#define PAGE_COUNT 32
+
+/*
+ * Max page size to initialize write and read buffer
+ */
+#define MAX_PAGE_SIZE 1024
+
+#define TEST_ADDRESS   0x00
+
+#define ENTER_4B   1
+#define EXIT_4B0
+
+u8 ReadCmd;
+u8 WriteCmd;
+u8 StatusCmd;
+u8 SectorEraseCmd;
+u8 FSRFlag;
+
+static int FlashReadID(XQspiPsu 

[PATCH 0/3] bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driver

[Alex White]

This patchset adds a JFFS2 driver for NOR flash using the Xilinx GQSPI
controller. It includes an imported XQspipsu driver from Xilinx, a series of
helper functions to interface with NOR flash, and a JFFS2 driver that uses the
helper functions.

Alex White (3):
  bsps: Import Xilinx GQSPI driver
  bsps: Add Xilinx GQSPI flash helper
  bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driver

 bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h  |1 +
 .../include/bsp/jffs2_xqspipsu.h  |   62 +
 bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c   |  186 ++
 bsps/include/dev/spi/xqspipsu-flash-helper.h  |   81 +
 bsps/include/dev/spi/xqspipsu.h   |  567 +
 bsps/include/dev/spi/xqspipsu_control.h   |  102 +
 bsps/include/dev/spi/xqspipsu_flash_config.h  |  355 +++
 bsps/include/dev/spi/xqspipsu_hw.h| 1006 +
 bsps/shared/dev/spi/VERSION   |   29 +
 bsps/shared/dev/spi/xqspipsu-flash-helper.c   | 2005 +
 bsps/shared/dev/spi/xqspipsu.c| 1048 +
 bsps/shared/dev/spi/xqspipsu_control.c|  282 +++
 bsps/shared/dev/spi/xqspipsu_hw.c |  768 +++
 bsps/shared/dev/spi/xqspipsu_options.c|  532 +
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |2 +
 .../aarch64/xilinx-zynqmp/objjffs2qspinor.yml |   22 +
 spec/build/bsps/objqspipsu.yml|   32 +
 spec/build/bsps/optxpssysctrlbaseaddress.yml  |   18 +
 18 files changed, 7098 insertions(+)
 create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
 create mode 100644 bsps/aarch64/xilinx-zynqmp/jffs2_xqspipsu.c
 create mode 100644 bsps/include/dev/spi/xqspipsu-flash-helper.h
 create mode 100644 bsps/include/dev/spi/xqspipsu.h
 create mode 100644 bsps/include/dev/spi/xqspipsu_control.h
 create mode 100644 bsps/include/dev/spi/xqspipsu_flash_config.h
 create mode 100644 bsps/include/dev/spi/xqspipsu_hw.h
 create mode 100644 bsps/shared/dev/spi/VERSION
 create mode 100644 bsps/shared/dev/spi/xqspipsu-flash-helper.c
 create mode 100644 bsps/shared/dev/spi/xqspipsu.c
 create mode 100644 bsps/shared/dev/spi/xqspipsu_control.c
 create mode 100644 bsps/shared/dev/spi/xqspipsu_hw.c
 create mode 100644 bsps/shared/dev/spi/xqspipsu_options.c
 create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objjffs2qspinor.yml
 create mode 100644 spec/build/bsps/objqspipsu.yml
 create mode 100644 spec/build/bsps/optxpssysctrlbaseaddress.yml

-- 
2.34.1

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[PATCH 3/5] bsps/microblaze: Add device tree support to AXI interrupt controller

[Alex White]

From: Ryan Long 

---
 .../microblaze_fpga/include/bsp/intc.h|  2 --
 bsps/microblaze/microblaze_fpga/irq/irq.c | 36 ++-
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h 
b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h
index df4554386d..c270c7464f 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h
@@ -65,8 +65,6 @@ typedef struct {
   uint32_t ilr;
 } Microblaze_INTC;
 
-#define _Microblaze_INTC ((volatile Microblaze_INTC *) 
BSP_MICROBLAZE_FPGA_INTC_BASE)
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c 
b/bsps/microblaze/microblaze_fpga/irq/irq.c
index 7148aed8cd..f14eddc799 100644
--- a/bsps/microblaze/microblaze_fpga/irq/irq.c
+++ b/bsps/microblaze/microblaze_fpga/irq/irq.c
@@ -33,15 +33,17 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
 #include 
 #include 
 
 #include 
 
+static volatile Microblaze_INTC *mblaze_intc;
+
 static void ack_interrupt( uint8_t source )
 {
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
-  intc->iar = 0x1 << source;
+  mblaze_intc->iar = 0x1 << source;
 }
 
 rtems_status_code bsp_interrupt_get_attributes(
@@ -79,8 +81,7 @@ rtems_status_code bsp_interrupt_clear( rtems_vector_number 
vector )
 {
   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
 
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
-  intc->iar = 0x1 << vector;
+  mblaze_intc->iar = 0x1 << vector;
 
   return RTEMS_SUCCESSFUL;
 }
@@ -93,10 +94,9 @@ rtems_status_code bsp_interrupt_vector_is_enabled(
   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
   bsp_interrupt_assert( enabled != NULL );
 
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
   uint32_t mask = 1 << vector;
 
-  *enabled = (intc->ier & mask) != 0;
+  *enabled = (mblaze_intc->ier & mask) != 0;
   return RTEMS_SUCCESSFUL;
 }
 
@@ -104,10 +104,9 @@ rtems_status_code bsp_interrupt_vector_enable( 
rtems_vector_number vector )
 {
   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
 
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
   uint32_t mask = 1 << vector;
 
-  intc->ier |= mask;
+  mblaze_intc->ier |= mask;
 
   return RTEMS_SUCCESSFUL;
 }
@@ -116,32 +115,35 @@ rtems_status_code bsp_interrupt_vector_disable( 
rtems_vector_number vector )
 {
   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
 
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
   uint32_t mask = 1 << vector;
 
-  intc->ier &= ~mask;
+  mblaze_intc->ier &= ~mask;
 
   return RTEMS_SUCCESSFUL;
 }
 
 void bsp_interrupt_facility_initialize( void )
 {
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
   /*
* Enable HW interrupts on the interrupt controller. This happens before
* interrupts are enabled on the processor.
*/
-  intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE;
+   mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree(
+"xlnx,xps-intc-1.00.a",
+"reg",
+BSP_MICROBLAZE_FPGA_INTC_BASE
+   );
+
+  mblaze_intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE;
 }
 
 void bsp_interrupt_dispatch( uint32_t source )
 {
-  volatile Microblaze_INTC *intc = _Microblaze_INTC;
   uint32_t vector_number = 0;
 
   if ( source == 0xFF ) {
 /* Read interrupt controller to get the source */
-vector_number = intc->isr & intc->ier;
+vector_number = mblaze_intc->isr & mblaze_intc->ier;
 
 /* Handle and the first interrupt that is set */
 uint8_t interrupt_status = 0;
@@ -149,13 +151,13 @@ void bsp_interrupt_dispatch( uint32_t source )
   interrupt_status = vector_number >> i & 0x1;
   if ( interrupt_status != 0 ) {
 /* save current ILR */
-uint32_t interrupt_levels = intc->ilr;
+uint32_t interrupt_levels = mblaze_intc->ilr;
 /* set ILR to block out every interrupt less than or equal to priority 
of i */
-intc->ilr = 0x >> (32 - i);
+mblaze_intc->ilr = 0x >> (32 - i);
 bsp_interrupt_handler_dispatch( i );
 ack_interrupt( i );
 /* restore ILR */
-intc->ilr = interrupt_levels;
+mblaze_intc->ilr = interrupt_levels;
 break;
   }
 }
-- 
2.34.1

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[PATCH 5/5] bsps/microblaze: Add device tree support to UART Lite

[Alex White]

From: Ryan Long 

---
 .../microblaze_fpga/console/console-io.c  | 19 ++--
 .../microblaze_fpga/console/debug-io.c| 29 +++
 bsps/microblaze/shared/dev/serial/uartlite.c  |  9 +-
 3 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c 
b/bsps/microblaze/microblaze_fpga/console/console-io.c
index cb2e367035..81c4e73690 100644
--- a/bsps/microblaze/microblaze_fpga/console/console-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/console-io.c
@@ -35,20 +35,35 @@
  */
 
 #include 
+#include 
 #include 
 
 #include 
 
 uart_lite_context microblaze_qemu_uart_context = {
   .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
-  .address = BSP_MICROBLAZE_FPGA_UART_BASE,
   .initial_baud = 115200
 };
 
+static bool fill_uart_base(rtems_termios_device_context *context)
+{
+  uint32_t mblaze_uart_base;
+
+  mblaze_uart_base = try_get_prop_from_device_tree(
+"xlnx,xps-uartlite-1.00.a",
+"reg",
+BSP_MICROBLAZE_FPGA_UART_BASE
+  );
+
+  microblaze_qemu_uart_context.address = mblaze_uart_base;
+
+  return true;
+}
+
 const console_device console_device_table[] = {
   {
 .device_file = "/dev/ttyS0",
-.probe = console_device_probe_default,
+.probe = fill_uart_base,
 .handler = _uart_fns,
 .context = _qemu_uart_context.base
   }
diff --git a/bsps/microblaze/microblaze_fpga/console/debug-io.c 
b/bsps/microblaze/microblaze_fpga/console/debug-io.c
index e88f5468a7..d85229ae9e 100644
--- a/bsps/microblaze/microblaze_fpga/console/debug-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/debug-io.c
@@ -37,23 +37,42 @@
 #include 
 #include 
 
+#include 
 #include 
 
+static uint32_t mblaze_uart_base = 0;
+
 static void output_char( char c )
 {
-  if ( c == '\n' ) {
-XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' );
+  if (mblaze_uart_base == 0 ) {
+mblaze_uart_base = try_get_prop_from_device_tree(
+  "xlnx,xps-uartlite-1.00.a",
+  "reg",
+  BSP_MICROBLAZE_FPGA_UART_BASE
+);
+  }
+
+if ( c == '\n' ) {
+XUartLite_SendByte( mblaze_uart_base, '\r' );
   }
-  XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c );
+  XUartLite_SendByte( mblaze_uart_base, c );
 }
 
 static int xUartLite_RecvByte( int minor )
 {
-  if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) {
+  if (mblaze_uart_base == 0 ) {
+mblaze_uart_base = try_get_prop_from_device_tree(
+  "xlnx,xps-uartlite-1.00.a",
+  "reg",
+  BSP_MICROBLAZE_FPGA_UART_BASE
+);
+  }
+
+  if ( XUartLite_IsReceiveEmpty( mblaze_uart_base ) ) {
 return -1;
   }
 
-  return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET 
);
+  return XUartLite_ReadReg( mblaze_uart_base, XUL_RX_FIFO_OFFSET );
 }
 
 static int get_char( void )
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index a5fc4fe82b..953c630759 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -70,8 +70,15 @@ static bool uart_first_open(
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   XUartLite_EnableIntr( ctx->address );
+
+  uint32_t uart_irq_num = try_get_prop_from_device_tree(
+"xlnx,xps-uartlite-1.00.a",
+"interrupts",
+1
+  );
+
   sc = rtems_interrupt_handler_install(
-1,
+uart_irq_num,
 "UART",
 RTEMS_INTERRUPT_SHARED,
 microblaze_uart_interrupt,
-- 
2.34.1

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[PATCH 4/5] bsps/microblaze: Add device tree support to JFFS2 QSPI

[Alex White]

From: Ryan Long 

---
 bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c 
b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
index 39328b6b7c..49859a03f1 100644
--- a/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
+++ b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
@@ -46,6 +46,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #define BLOCK_SIZE (64UL * 1024UL)
@@ -286,12 +287,24 @@ int microblaze_jffs2_initialize( const char* mount_dir )
   int rv = 0;
   int fd = -1;
 
+  uintptr_t mblaze_spi_base = try_get_prop_from_device_tree(
+"xlnx,xps-spi-2.00.a",
+"reg",
+BSP_MICROBLAZE_FPGA_SPI_BASE
+  );
+
+  rtems_vector_number mblaze_spi_irq_num = try_get_prop_from_device_tree(
+"xlnx,xps-spi-2.00.a",
+"interrupts",
+BSP_MICROBLAZE_FPGA_SPI_IRQ_NUM
+  );
+
   rv = spi_bus_register_xilinx_axi(
 BUS_PATH,
-BSP_MICROBLAZE_FPGA_SPI_BASE,
+mblaze_spi_base,
 FLASH_PAGE_SIZE,
 FLASH_NUM_CS,
-BSP_MICROBLAZE_FPGA_SPI_IRQ_NUM
+mblaze_spi_irq_num
   );
   if ( rv != 0 ) {
 return rv;
-- 
2.34.1

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[PATCH 1/5] bsps/microblaze: Add device tree getter

[Alex White]

This allows drivers to read configuration data from the device tree if
the BSP is built with device tree support.
---
 .../include/bsp/microblaze-fdt-support.h  | 65 +
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c | 23 --
 bsps/microblaze/microblaze_fpga/include/bsp.h |  3 +
 .../shared/fdt/microblaze-fdt-support.c   | 72 +++
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  2 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |  3 +-
 .../microblaze/microblaze_fpga/optusefdt.yml  | 15 
 7 files changed, 159 insertions(+), 24 deletions(-)
 create mode 100644 bsps/microblaze/include/bsp/microblaze-fdt-support.h
 delete mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
 create mode 100644 bsps/microblaze/shared/fdt/microblaze-fdt-support.c
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml

diff --git a/bsps/microblaze/include/bsp/microblaze-fdt-support.h 
b/bsps/microblaze/include/bsp/microblaze-fdt-support.h
new file mode 100644
index 00..ede8153c81
--- /dev/null
+++ b/bsps/microblaze/include/bsp/microblaze-fdt-support.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief This header file provides support for the device tree.
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H
+#define LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+/**
+ * @brief Get the value of a property from a compatible node in the device 
tree.
+ * 
+ * @param[in] compatible The 'compatible' string to match against.
+ * @param[in] prop_name The property name.
+ * @param[in] default_value The default value to return if no compatible node
+ *  was found or the property was not found.
+ * 
+ * @return The value of the property or the default value.
+ */
+uint32_t try_get_prop_from_device_tree(
+  const char *compatible,
+  const char *prop_name,
+  uint32_t default_value
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H */
diff --git a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c 
b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
deleted file mode 100644
index 9eb92c5dc6..00
--- a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  COPYRIGHT (c) 2021.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include 
-#include 
-
-#include BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH
-
-const void *bsp_fdt_get(void)
-{
-  return system_dtb;
-}
-
-uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
-{
-  return intr[0];
-}
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 93cf0e4b34..410d4483c6 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -43,12 +43,15 @@ extern "C" {
 
 #include 
 #include 
+#include 
 
 #include 
 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
 #define BSP_FDT_IS_SUPPORTED
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
+#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
 
 void microblaze_enable_icache(void);
 void microblaze_enable_dcache(void);
diff --git a/bsps/microblaze/shared/fdt/microblaze-fdt-support.c 
b/bsps/microblaze/shared/fdt/microblaze-fdt-support.c
new file mode 100644
index 

[PATCH 0/5] bsps/microblaze: Add device tree support

[Alex White]

This patch set adds device tree support to the following MicroBlaze BSP drivers:
- AXI Interrupt Controller
- JFFS2 QSPI
- AXI UART Lite
- AXI Timer clock

Previously, the only way to configure the above drivers was to use build
configuration options. Now when a device tree is present, the BSP will use the
device tree to configure the drivers.

Alex White (2):
  bsps/microblaze: Add device tree getter
  bsps/microblaze: Add device tree support to timer

Ryan Long (3):
  bsps/microblaze: Add device tree support to AXI interrupt controller
  bsps/microblaze: Add device tree support to JFFS2 QSPI
  bsps/microblaze: Add device tree support to UART Lite

 .../include/bsp/microblaze-fdt-support.h  | 65 +
 bsps/microblaze/microblaze_fpga/clock/clock.c | 50 -
 .../microblaze_fpga/console/console-io.c  | 19 -
 .../microblaze_fpga/console/debug-io.c| 29 ++--
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c | 23 --
 .../microblaze_fpga/fs/jffs2_qspi.c   | 17 -
 bsps/microblaze/microblaze_fpga/include/bsp.h |  3 +
 .../microblaze_fpga/include/bsp/intc.h|  2 -
 .../microblaze_fpga/include/bsp/timer.h   |  2 -
 bsps/microblaze/microblaze_fpga/irq/irq.c | 36 +-
 bsps/microblaze/shared/dev/serial/uartlite.c  |  9 ++-
 .../shared/fdt/microblaze-fdt-support.c   | 72 +++
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  2 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |  3 +-
 .../microblaze/microblaze_fpga/optusefdt.yml  | 15 
 15 files changed, 274 insertions(+), 73 deletions(-)
 create mode 100644 bsps/microblaze/include/bsp/microblaze-fdt-support.h
 delete mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
 create mode 100644 bsps/microblaze/shared/fdt/microblaze-fdt-support.c
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optusefdt.yml

-- 
2.34.1

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[PATCH 2/5] bsps/microblaze: Add device tree support to timer

[Alex White]

---
 bsps/microblaze/microblaze_fpga/clock/clock.c | 50 ---
 .../microblaze_fpga/include/bsp/timer.h   |  2 -
 2 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/clock/clock.c 
b/bsps/microblaze/microblaze_fpga/clock/clock.c
index 957d0fdadb..19e960022b 100644
--- a/bsps/microblaze/microblaze_fpga/clock/clock.c
+++ b/bsps/microblaze/microblaze_fpga/clock/clock.c
@@ -33,6 +33,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
 #include 
 #include 
 
@@ -41,17 +42,16 @@
 #include 
 
 static rtems_timecounter_simple mblaze_tc;
+static volatile Microblaze_Timer *mblaze_timer;
 
 static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc )
 {
-  volatile Microblaze_Timer *timer = _Microblaze_Timer;
-  return timer->tcr0;
+  return mblaze_timer->tcr0;
 }
 
 static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc )
 {
-  volatile Microblaze_Timer *timer = _Microblaze_Timer;
-  return ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0;
+  return ( mblaze_timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0;
 }
 
 static uint32_t microblaze_tc_get_timecount( struct timecounter *tc )
@@ -65,32 +65,41 @@ static uint32_t microblaze_tc_get_timecount( struct 
timecounter *tc )
 
 static void microblaze_clock_initialize( void )
 {
-  volatile Microblaze_Timer *timer = _Microblaze_Timer;
+  mblaze_timer = (volatile Microblaze_Timer *) try_get_prop_from_device_tree(
+"xlnx,xps-timer-1.00.a",
+"reg",
+BSP_MICROBLAZE_FPGA_TIMER_BASE
+  );
+
   /* Set load register to 0 */
-  timer->tlr0 = 0;
+  mblaze_timer->tlr0 = 0;
   /* Reset the timer and interrupt */
-  timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0;
+  mblaze_timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | 
MICROBLAZE_TIMER_TCSR0_LOAD0;
   /* Release the reset */
-  timer->tcsr0 = 0;
+  mblaze_timer->tcsr0 = 0;
   /*
* Enable interrupt, auto reload mode, external interrupt signal,
* and down counter
*/
-  timer->tcsr0 =  MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 |
+  mblaze_timer->tcsr0 =  MICROBLAZE_TIMER_TCSR0_ARHT0 | 
MICROBLAZE_TIMER_TCSR0_ENIT0 |
   MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0;
 
   uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
-  uint32_t counter_frequency_in_hz = BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY;
+  uint32_t counter_frequency_in_hz = try_get_prop_from_device_tree(
+"xlnx,xps-timer-1.00.a",
+"clock-frequency",
+BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY
+  );
   uint32_t counter_ticks_per_clock_tick =
 ( counter_frequency_in_hz * us_per_tick ) / 100;
 
   /* Set a reset value for the timer counter */
-  timer->tlr0 = counter_ticks_per_clock_tick;
-  uint32_t control_status_reg = timer->tcsr0;
+  mblaze_timer->tlr0 = counter_ticks_per_clock_tick;
+  uint32_t control_status_reg = mblaze_timer->tcsr0;
   /* Load the reset value into the counter register */
-  timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0;
+  mblaze_timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0;
   /* Enable the timer */
-  timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0;
+  mblaze_timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0;
 
   rtems_timecounter_simple_install(
 _tc,
@@ -102,12 +111,11 @@ static void microblaze_clock_initialize( void )
 
 static void microblaze_clock_at_tick( rtems_timecounter_simple *tc )
 {
-  volatile Microblaze_Timer *timer = _Microblaze_Timer;
-  if ( ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) {
+  if ( ( mblaze_timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) {
 return;
   }
   /* Clear the interrupt */
-  timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT;
+  mblaze_timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT;
 }
 
 static void microblaze_tc_tick( void )
@@ -123,8 +131,14 @@ static void microblaze_clock_handler_install( 
rtems_interrupt_handler isr )
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
 
+  uint32_t clock_irq_num = try_get_prop_from_device_tree(
+"xlnx,xps-timer-1.00.a",
+"interrupts",
+0
+  );
+
   sc = rtems_interrupt_handler_install(
-0,
+clock_irq_num,
 "Clock",
 RTEMS_INTERRUPT_UNIQUE,
 isr,
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h 
b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h
index 562fdd79b0..bd8661d47c 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h
@@ -60,8 +60,6 @@ typedef struct {
   uint32_t tcr0;
 } Microblaze_Timer;
 
-#define _Microblaze_Timer ((volatile Microblaze_Timer *) 
BSP_MICROBLAZE_FPGA_TIMER_BASE)
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
-- 
2.34.1

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[PATCH] bsps/microblaze: Fix console interrupt build errors

[Alex White]

This fixes build errors seen when building with console interrupts
enabled. A few places were missing bspopts.h includes, and one of the
UART functions was not defined.
---
 bsps/microblaze/include/dev/serial/uartlite.h  |  1 +
 .../microblaze/include/dev/serial/uartlite_l.h | 18 ++
 bsps/microblaze/shared/dev/serial/uartlite.c   |  3 ++-
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 6e288d4dc7..2fda3796b3 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -36,6 +36,7 @@
 #ifndef LIBBSP_MICROBLAZE_SHARED_UARTLITE_H
 #define LIBBSP_MICROBLAZE_SHARED_UARTLITE_H
 
+#include 
 #include 
 
 #include 
diff --git a/bsps/microblaze/include/dev/serial/uartlite_l.h 
b/bsps/microblaze/include/dev/serial/uartlite_l.h
index 8c0598e191..834fbb5f75 100644
--- a/bsps/microblaze/include/dev/serial/uartlite_l.h
+++ b/bsps/microblaze/include/dev/serial/uartlite_l.h
@@ -234,6 +234,24 @@ static inline void Xil_Out32(UINTPTR Addr, u32 Value)
   ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
XUL_SR_RX_FIFO_VALID_DATA)
 
+#ifdef __rtems__
+//
+/**
+*
+* Check to see if the transmitter is empty.
+*
+* @param   BaseAddress is the  base address of the device
+*
+* @return  TRUE if the transmitter is empty, FALSE otherwise.
+*
+* @noteC-style Signature:
+*  int XUartLite_IsTransmitEmpty(u32 BaseAddress);
+*
+*/
+#define XUartLite_IsTransmitEmpty(BaseAddress) \
+  ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_EMPTY) == \
+   XUL_SR_TX_FIFO_EMPTY)
+#endif /* __rtems__ */
 
 //
 /**
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index 7387e22635..a5fc4fe82b 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -35,6 +35,7 @@
 
 #include 
 #include 
+#include 
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
 static void microblaze_uart_interrupt( void *arg )
@@ -47,7 +48,7 @@ static void microblaze_uart_interrupt( void *arg )
 rtems_termios_enqueue_raw_characters( tty, , 1 );
   }
 
-  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx ) ) {
+  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx->address ) ) {
 rtems_termios_dequeue_characters( tty, 1 );
   }
 }
-- 
2.34.1

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[PATCH] bsps/microblaze: Fix build option definition order

[Alex White]

The build option definitions were rearranged such that the option
definitions used in the linker script were not available. This caused
linker errors when building.
---
 spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml  | 2 --
 spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml | 2 --
 spec/build/bsps/microblaze/microblaze_fpga/grp.yml| 2 ++
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml
index c31ca37e9b..9ec29f49f6 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml
@@ -11,8 +11,6 @@ family: microblaze_fpga
 includes: []
 install: []
 links:
-- role: build-dependency
-  uid: linkcmds
 - role: build-dependency
   uid: tstkcu105_qemu
 - role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml
index 39a5ca35d1..9a1147297a 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml
@@ -11,8 +11,6 @@ family: microblaze_fpga
 includes: []
 install: []
 links:
-- role: build-dependency
-  uid: linkcmds
 - role: build-dependency
   uid: tstkcu105_qemu
 - role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
index 2473ab8fe8..5fa21e4fa3 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -60,6 +60,8 @@ links:
   uid: ../../objirq
 - role: build-dependency
   uid: ../../objmem
+- role: build-dependency
+  uid: linkcmds
 - role: build-dependency
   uid: ../../bspopts
 type: build
-- 
2.32.0

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Re: linkcmds.yml problems

[Alex White]

On Thu, Jul 7, 2022 at 10:31 AM Sam Price  wrote:
> Is it possible i have a bad python instance ?

I was able to reproduce the linker problem using the latest RTEMS upstream code.

It looks like it was broken by commit a0aaa394b68727d204904b59514cb0f90840ba6f 
from 6 days ago.

I will submit a fix.

Alex

>
>
> --
> Thank you,
>
> Sam Price
> ___
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> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel


From: devel  on behalf of Sam Price 

Sent: Thursday, July 7, 2022 10:30 AM
To: devel@rtems.org
Subject: linkcmds.yml problems

Was trying to build the latest source builder/rtems/libbsd but ran into a 
linker problem.

You ever see this the source linker has

spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml: RAM : ORIGIN = 
_TEXT_START_ADDR, LENGTH = ${BSP_MICROBLAZE_FPGA_RAM_LENGTH}


But the generated linker file is creating

RAM : ORIGIN = _TEXT_START_ADDR, LENGTH =

when building rtems without populating the BSP_MICROBLAZE_FPGA_RAM_LENGTH.



My config.ini has this specified as
configs/config_kcu105_cpu0.ini:BSP_MICROBLAZE_FPGA_RAM_LENGTH=0x1000

Is it possible i have a bad python instance ?


--
Thank you,

Sam Price
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Runtime Loader Exported Symbols Address Size

[Alex White]

Hi,

While testing libdl on AArch64 QEMU, we found a bug where the exported symbol 
table appears to always use 32-bit values for addresses, but where the exported 
symbols table is read in `rtems_rtl_symbol_global_add`, the addresses are 
expected to be of size `sizeof(unsigned long)`.

This did not cause a problem on ARM since `sizeof(unsigned long)` is 4, but 
with AArch64 `sizeof(unsigned long)` is 8. So it is trying to read the address 
as 64 bits instead of 32.

The simple fix is to use an exact-width integer type - like `sizeof(uint32_t)`. 
But this would not allow for 64-bit architectures to use the full address 
space. It would also break on 64-bit RISC-V (see below). Perhaps we could have 
an ifdef to choose a 32 or 64-bit type based on the architecture rather than 
relying on `sizeof(unsigned long)`?

It looks like there is an exception in the rtems-syms tool for 64-bit RISC-V to 
emit 64-bit addresses rather than 32-bit addresses. Is this the right solution? 
Should we add another exception for AArch64?

Thanks,

Alex
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[PATCH rtems-docs] microblaze: Document BSPs and update CPU supplement

[Alex White]

---
 cpu-supplement/xilinx_microblaze.rst |  52 +-
 user/bsps/bsps-microblaze.rst| 149 ++-
 2 files changed, 197 insertions(+), 4 deletions(-)

diff --git a/cpu-supplement/xilinx_microblaze.rst 
b/cpu-supplement/xilinx_microblaze.rst
index 2a92b61..350aeff 100644
--- a/cpu-supplement/xilinx_microblaze.rst
+++ b/cpu-supplement/xilinx_microblaze.rst
@@ -1,10 +1,58 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
+.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
 
 Xilinx MicroBlaze Specific Information
 **
 
+This chapter discusses the dependencies of the *MicroBlaze architecture*
+(https://en.wikipedia.org/wiki/MicroBlaze).
+
+**Architecture Documents**
+
+For information on the MicroBlaze architecture, refer to
+*UG984 MicroBlaze Processor Reference Guide*
+(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
+
+CPU Model Dependent Features
+
+
+There are no CPU model dependent features in this port.
+
+Calling Conventions
+===
+
+Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of
+*UG984 MicroBlaze Processor Reference Guide*
+(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
+
+Interrupt Processing
+
+
+Hardware exceptions, interrupts, and user exceptions are all supported. When a
+hardware exception or user exception occurs, a fatal error will be generated.
+When an interrupt occurs, the interrupt source is determined by reading the
+AXI Interrupt Controller's Interrupt Status Register and masking it with the
+Interrupt Enable Register.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on MicroBlaze with respect to RTEMS.
+Level zero corresponds to interrupts disabled. Level one corresponds to
+interrupts enabled. This is the inverse of how most other architectures handle
+interrupt enable status.
+
+Interrupt Stack
+---
+
+The memory region for the interrupt stack is defined by the BSP.
+
+Default Fatal Error Processing
+==
+
+The default fatal error is BSP-specific.
+
 Symmetric Multiprocessing
 =
 
@@ -13,4 +61,4 @@ SMP is not supported.
 Thread-Local Storage
 
 
-Thread-local storage is not implemented.
+Thread-local storage is supported.
diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index dbb574f..e20df53 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -1,8 +1,153 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
 .. Copyright (C) 2018 embedded brains GmbH
+.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
 
-microblaze (Microblaze)
+microblaze (MicroBlaze)
 ***
 
-There are no Microblaze BSPs yet.
+KCU105 QEMU
+===
+
+The basic hardware initialization is performed by the BSP. This BSP supports 
the
+QEMU emulated Xilinx AXI Interrupt Controller v4.1.
+
+Boot via ELF
+
+
+The executable image is booted by QEMU in ELF format.
+
+Clock Driver
+
+
+The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is
+implemented as a simple downcounter.
+
+Console Driver
+--
+
+The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is
+initialized to a baud rate of 115200.
+
+Network Driver
+--
+
+Support for networking is provided by the libbsd library. Network interface
+configuration is extracted from the device tree binary which, by default, is
+in ` 
`_.
+The device tree source for the default device tree is at `dts/system.dts 
`_.
+
+To replace the default device tree with your own, assuming 
``my_device_tree.dts``
+is the name of your device tree source file, first you must convert your device
+tree to .dtb format.
+
+.. code-block:: none
+
+  $ dtc -I dts -O dtb my_device_tree.dts > my_device_tree.dtb
+
+The device tree blob, ``my_device_tree.dtb``, can now be converted to a C file.
+The name ``system_dtb`` is significant as it is the name expected by the BSP.
+
+.. code-block:: none
+
+  $ rtems-bin2c -C -A 8 -N system_dtb my_device_tree.dtb my_dtb
+
+The ``BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH`` BSP configuration option can then 
be
+set to the path of the resulting source file, ``my_dtb.c``, to include it in 
the
+BSP build.
+
+.. code-block:: none
+
+  BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c
+
+
+Running Executables
+---
+
+A .dtb (device tree blob) file should be provided to QEMU via the ``-hw-dtb``
+option. In the example command below, the 

Re: [PATCH] microblaze: Add AXI GPIO driver

[Alex White]

On Wed, Mar 16, 2022 at 10:27 AM Gedare Bloom  wrote:
>
> On Tue, Mar 15, 2022 at 2:28 PM Alex White  wrote:
> >
> > ---
> >  bsps/include/dev/gpio/xilinx-axi-gpio.h       | 311 ++
> >  bsps/shared/dev/gpio/xilinx-axi-gpio.c        | 221 +
>
> Is this AXI GPIO interface consistent across Xilinx IP?

Hi Gedare,

Thanks for taking a look at this.

As long as the Xilinx AXI GPIO v2.0 IP is being used, this interface
should be usable across any platform.

I realize now that there is an older v1.0 AXI GPIO IP so it would be
wise to specify which version is being supported somewhere.


> > +  /*
> > +   * IP Interrupt Enable Register
> > +   *
> > +   * Provides the ability to independtly control whether interrupts for 
> > each
> typo: independently

Will fix.

>
> > +   * channel are enabled or disabled.
> > +   *
> > +   * 0 - No Channel input interrupt
> > +   * 1 - Channel input interrupt
> > +   */
> > +  uint32_t ip_ier;
> > +} xilinx_axi_gpio;
>
> This `xilinx_` is not a proper namespace for RTEMS. it doesn't
> correspond with any existing components and so it requires some
> discussion and approval to introduce it.

I used the same struct naming scheme as is used in 
bsps/include/dev/spi/xilinx-axi-spi-regs.h.

I guess this is different because it is exposed in the user-facing api?

>
> > +
> > +typedef struct {
> > +  volatile xilinx_axi_gpio *regs;
> > +  bool                      is_dual;
> > +  uint32_t                  irq;
> > +  bool                      has_interrupts;
> > +} xilinx_axi_gpio_context;
> > +
> > +/**
> > + * @brief Set pin configuration for the specified GPIO channel.
> > + *
> > + * Changes the pin configuration for a channel. Bits set to 0 are output, 
> > and
> > + * bits set to 1 are input.
> > + *
> > + * @param[in] ctx the GPIO context
> > + * @param[in] channel the GPIO channel
> > + * @param[in] mask the mask to be applied to @ channel
> > + *
> > + * @retval None
> > + */
> > +void axi_gpio_set_data_direction(
>
> neither is this `axi_`

I realize now that this makes less sense than something like
`xilinx_axi_gpio_set_data_direction` assuming the context struct name
above was accepted.

>
> > +  xilinx_axi_gpio_context *ctx,
>
> Mixing the newly proposed namespaces is also confusing.

I agree.

What would make this easiest? Should I start a new thread on Xilinx AXI
peripheral driver naming in the shared namespace?

Thanks,

Alex
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[PATCH] microblaze: Add AXI GPIO driver

[Alex White]

---
 bsps/include/dev/gpio/xilinx-axi-gpio.h   | 311 ++
 bsps/shared/dev/gpio/xilinx-axi-gpio.c| 221 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
 3 files changed, 534 insertions(+)
 create mode 100644 bsps/include/dev/gpio/xilinx-axi-gpio.h
 create mode 100644 bsps/shared/dev/gpio/xilinx-axi-gpio.c

diff --git a/bsps/include/dev/gpio/xilinx-axi-gpio.h 
b/bsps/include/dev/gpio/xilinx-axi-gpio.h
new file mode 100644
index 00..dbd8748f34
--- /dev/null
+++ b/bsps/include/dev/gpio/xilinx-axi-gpio.h
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief Xilinx AXI GPIO definitions
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef XILINX_AXI_GPIO_H
+#define XILINX_AXI_GPIO_H
+
+#include 
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  /* Channel 1 data values */
+
+  /*
+   * Used to read general purpose input ports and write to general purpose
+   * output ports from channel 1.
+   */
+  uint32_t gpio_data;
+
+  /*
+   * The 3-state control register for channel 1 is used for the dynamic
+   * configuration of ports as input or output. When a bit is set to 1, the
+   * corresponding I/O port is an input port. When a bit is set to 0, it is an
+   * output port.
+   */
+  uint32_t gpio_tri;
+
+  /* Channel 2 data values */
+
+  /*
+   * Used to read general purpose input ports and write to general purpose
+   * output ports from channel 2.
+   */
+  uint32_t gpio2_data;
+
+  /*
+   * The 3-state control register for channel 2 is used for the dynamic
+   * configuration of ports as input or output. When a bit is set to 1, the
+   * corresponding I/O port is an input port. When a bit is set to 0, it is an
+   * output port.
+   */
+  uint32_t gpio2_tri;
+
+  char _unused[272];
+
+  /* Only the 31st bit is used to enable interrupts globally */
+  #define GLOBAL_INTERRUPT_REGISTER_ENABLE BSP_BIT32(31)
+
+  /*
+   * Global Interrupt Enable Register
+   *
+   * Determines whether interrupts are enabled or disabled.
+   *
+   * 0 - Disabled
+   * 1 - Enabled
+   */
+  uint32_t gier;
+
+  char _unused2[12];
+
+  /* Used with ip_isr and ip_ier member variables */
+  #define CHANNEL_1_INTERRUPT_REGISTER BSP_BIT32(0)
+  #define CHANNEL_2_INTERRUPT_REGISTER BSP_BIT32(1)
+
+  /*
+   * IP Status Registers
+   *
+   * Contains the status bit for each channel.
+   *
+   * 0 - Disabled
+   * 1 - Enabled
+   */
+  uint32_t ip_isr;
+
+  char _unused3[4];
+
+  /*
+   * IP Interrupt Enable Register
+   *
+   * Provides the ability to independtly control whether interrupts for each
+   * channel are enabled or disabled.
+   *
+   * 0 - No Channel input interrupt
+   * 1 - Channel input interrupt
+   */
+  uint32_t ip_ier;
+} xilinx_axi_gpio;
+
+typedef struct {
+  volatile xilinx_axi_gpio *regs;
+  bool  is_dual;
+  uint32_t  irq;
+  bool  has_interrupts;
+} xilinx_axi_gpio_context;
+
+/**
+ * @brief Set pin configuration for the specified GPIO channel.
+ *
+ * Changes the pin configuration for a channel. Bits set to 0 are output, and
+ * bits set to 1 are input.
+ *
+ * @param[in] ctx the GPIO context
+ * @param[in] channel the GPIO channel
+ * @param[in] mask the mask to be applied to @ channel
+ *
+ * @retval None
+ */
+void axi_gpio_set_data_direction(
+  xilinx_axi_gpio_context *ctx,
+  uint32_t channel,
+  uint32_t mask
+);
+
+/**
+ * @brief Get pin configuration for specified GPIO channel.
+ *
+ * Gets the 

[PATCH rtems-libbsd] if_xae: Fix non-FDT BSP build error

[Alex White]

This fixes a compiler error that would occur for every BSP that does not
define `BSP_FDT_IS_SUPPORTED`. The fdt headers should always be included
to provide the needed definitions.
---
 freebsd/sys/dev/xilinx/axidma.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/freebsd/sys/dev/xilinx/axidma.c b/freebsd/sys/dev/xilinx/axidma.c
index 20cd7f23..77025c0a 100644
--- a/freebsd/sys/dev/xilinx/axidma.c
+++ b/freebsd/sys/dev/xilinx/axidma.c
@@ -52,11 +52,17 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 
+#ifndef __rtems__
 #ifdef FDT
 #include 
 #include 
 #include 
 #endif
+#else
+#include 
+#include 
+#include 
+#endif /* __rtems__ */
 
 #include 
 #include 
-- 
2.32.0

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Re: [PATCH] microblaze: Add JFFS2 AXI QSPI driver

[Alex White]

ping

On Wed, Mar 2, 2022 at 8:30 PM Alex White  wrote:
>
> This driver has been tested with Micron NOR Flash via AXI Quad SPI.
> ---
>  .../microblaze_fpga/fs/jffs2_qspi.c           | 319 ++
>  .../microblaze_fpga/include/bsp/jffs2_qspi.h  |  56 +++
>  .../bsps/microblaze/microblaze_fpga/grp.yml   |   6 +
>  .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
>  .../microblaze_fpga/optspibaseaddress.yml     |  18 +
>  .../microblaze/microblaze_fpga/optspiirq.yml  |  17 +
>  6 files changed, 418 insertions(+)
>  create mode 100644 bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
>  create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h
>  create mode 100644 
> spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml
>  create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml
>
> diff --git a/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c 
> b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
> new file mode 100644
> index 00..39328b6b7c
> --- /dev/null
> +++ b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
> @@ -0,0 +1,319 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +
> +/**
> + * @file
> + *
> + * @ingroup RTEMSBSPsMicroblaze
> + *
> + * @brief MicroBlaze AXI QSPI JFFS2 flash driver implementation
> + */
> +
> +/*
> + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in the
> + *    documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
> IS"
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> + * POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define BLOCK_SIZE (64UL * 1024UL)
> +#define FLASH_SIZE (32UL * BLOCK_SIZE)
> +#define FLASH_PAGE_SIZE        256
> +#define FLASH_NUM_CS           2
> +#define FLASH_DEVICE_ID        0xbb19 /* Type: 0xbb, Capacity: 0x19 */
> +#define BUS_PATH          "/dev/spi-0"
> +#define FLASH_MOUNT_POINT "/mnt"
> +
> +#define READ_WRITE_EXTRA_BYTES 4
> +#define WRITE_ENABLE_BYTES     1
> +#define SECTOR_ERASE_BYTES     4
> +
> +#define COMMAND_QUAD_WRITE     0x32
> +#define COMMAND_SECTOR_ERASE   0xD8
> +#define COMMAND_QUAD_READ      0x6B
> +#define COMMAND_STATUSREG_READ 0x05
> +#define COMMAND_WRITE_ENABLE   0x06
> +#define FLASH_SR_IS_READY_MASK 0x01
> +
> +typedef struct {
> +  rtems_jffs2_flash_control super;
> +  int                       fd;
> +} flash_control;
> +
> +static uint8_t ReadBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4];
> +static uint8_t WriteBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4];
> +
> +static flash_control *get_flash_control( rtems_jffs2_flash_control *super )
> +{
> +  return (flash_control *) super;
> +}
> +
> +static int flash_wait_for_ready( flash_control *self )
> +{
> +  uint8_t rv     = 0;
> +  uint8_t status = 0;
> +
> +  WriteBuffer[0] = COMMAND_STATUSREG_READ;
> +
> +  struct spi_ioc_transfer mesg = {
> +    .tx_buf        = WriteBuffer,
> +    .rx_buf        = ReadBuffer,
> +    .len           = 2,
> +    .bits_per_word = 8,
> +    .cs            = 0
> +  };
> +
> +  do {
> +    rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ),  );
> +    if ( rv != 0 ) {
> +      return -EIO;
> +    }
> +
> +    status = ReadBuffer[1];
> +  } while ( (status & FLASH_SR_IS_READY

[PATCH] microblaze: Add JFFS2 AXI QSPI driver

[Alex White]

This driver has been tested with Micron NOR Flash via AXI Quad SPI.
---
 .../microblaze_fpga/fs/jffs2_qspi.c   | 319 ++
 .../microblaze_fpga/include/bsp/jffs2_qspi.h  |  56 +++
 .../bsps/microblaze/microblaze_fpga/grp.yml   |   6 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
 .../microblaze_fpga/optspibaseaddress.yml |  18 +
 .../microblaze/microblaze_fpga/optspiirq.yml  |  17 +
 6 files changed, 418 insertions(+)
 create mode 100644 bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
 create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optspibaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optspiirq.yml

diff --git a/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c 
b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
new file mode 100644
index 00..39328b6b7c
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c
@@ -0,0 +1,319 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI QSPI JFFS2 flash driver implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define BLOCK_SIZE (64UL * 1024UL)
+#define FLASH_SIZE (32UL * BLOCK_SIZE)
+#define FLASH_PAGE_SIZE256
+#define FLASH_NUM_CS   2
+#define FLASH_DEVICE_ID0xbb19 /* Type: 0xbb, Capacity: 0x19 */
+#define BUS_PATH  "/dev/spi-0"
+#define FLASH_MOUNT_POINT "/mnt"
+
+#define READ_WRITE_EXTRA_BYTES 4
+#define WRITE_ENABLE_BYTES 1
+#define SECTOR_ERASE_BYTES 4
+
+#define COMMAND_QUAD_WRITE 0x32
+#define COMMAND_SECTOR_ERASE   0xD8
+#define COMMAND_QUAD_READ  0x6B
+#define COMMAND_STATUSREG_READ 0x05
+#define COMMAND_WRITE_ENABLE   0x06
+#define FLASH_SR_IS_READY_MASK 0x01
+
+typedef struct {
+  rtems_jffs2_flash_control super;
+  int   fd;
+} flash_control;
+
+static uint8_t ReadBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4];
+static uint8_t WriteBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4];
+
+static flash_control *get_flash_control( rtems_jffs2_flash_control *super )
+{
+  return (flash_control *) super;
+}
+
+static int flash_wait_for_ready( flash_control *self )
+{
+  uint8_t rv = 0;
+  uint8_t status = 0;
+
+  WriteBuffer[0] = COMMAND_STATUSREG_READ;
+
+  struct spi_ioc_transfer mesg = {
+.tx_buf= WriteBuffer,
+.rx_buf= ReadBuffer,
+.len   = 2,
+.bits_per_word = 8,
+.cs= 0
+  };
+
+  do {
+rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ),  );
+if ( rv != 0 ) {
+  return -EIO;
+}
+
+status = ReadBuffer[1];
+  } while ( (status & FLASH_SR_IS_READY_MASK) != 0 );
+
+  return 0;
+}
+
+static int flash_write_enable( flash_control *self )
+{
+  uint8_t rv = 0;
+
+  rv = flash_wait_for_ready( self );
+  if ( rv != 0 ) {
+return rv;
+  }
+
+  WriteBuffer[0] = COMMAND_WRITE_ENABLE;
+
+  struct spi_ioc_transfer mesg = {
+.tx_buf= WriteBuffer,
+.len   = WRITE_ENABLE_BYTES,
+.bits_per_word = 8,
+.cs= 0
+  };
+
+  rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ),  );
+  if ( rv != 0 ) {
+return -EIO;
+  }
+
+  return 0;
+}
+
+static int flash_read(
+  rtems_jffs2_flash_control *super,
+  uint32_t   offset,
+  unsigned char *buffer,
+  size_t size_of_buffer
+)
+{
+  int rv = 0;
+  uint32_t 

Re: [PATCH rtems-libbsd v2 0/3] MicroBlaze AXI Ethernet Support

[Alex White]

On Mon, Feb 14, 2022 at 7:40 AM Sebastian Huber 
 wrote:
>
> On 10/02/2022 23:12, Alex White wrote:
> > v2:
> > - Reworked patches to follow CONTRIBUTING.md guide
> > - Excluded unneeded vmem calls
> > - Moved ethernet frame alignment handling to the network interface driver
> >
> > This patch set adds support for Xilinx's AXI Ethernet IP core. It has
> > been tested both in QEMU and on the KCU105 board using the default
> > FPGA implementation from the Xilinx's KCU105 PetaLinux BSP.
>
> The patch set in general looks good. For which libbsd branch is this
> import? From which FreeBSD commit did you import the driver code?

Hi Sebastian,

This is for the 6-freebsd-12 branch.

The driver code came from commit 0d1c391 which is the current commit pointed to 
by freebsd-org in the 6-freebsd-12 branch.

These changes rely on some of Chris's changes that were committed to the 
6-freebsd-12 branch with no current plan to merge to the master branch. This 
means that these changes will also have to live on the 6-freebsd-12 branch 
until all of it can be brought over.

Alex
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[PATCH rtems-libbsd v2 0/3] MicroBlaze AXI Ethernet Support

[Alex White]

v2:
- Reworked patches to follow CONTRIBUTING.md guide
- Excluded unneeded vmem calls
- Moved ethernet frame alignment handling to the network interface driver

This patch set adds support for Xilinx's AXI Ethernet IP core. It has
been tested both in QEMU and on the KCU105 board using the default
FPGA implementation from the Xilinx's KCU105 PetaLinux BSP.

Alex White (1):
  if_xae: Port to RTEMS

Jennifer Averett (2):
  Add MicroBlaze support
  if_xae: Import from FreeBSD

 buildset/default.ini  |1 +
 freebsd/sys/dev/mii/tiphy.h   |   57 +
 freebsd/sys/dev/xdma/xdma.c   |  501 
 freebsd/sys/dev/xdma/xdma.h   |  285 +
 freebsd/sys/dev/xdma/xdma_bank.c  |  100 ++
 freebsd/sys/dev/xdma/xdma_mbuf.c  |  151 +++
 freebsd/sys/dev/xdma/xdma_queue.c |  126 ++
 freebsd/sys/dev/xdma/xdma_sg.c|  661 ++
 freebsd/sys/dev/xdma/xdma_sglist.c|  103 ++
 freebsd/sys/dev/xilinx/axidma.c   |  677 ++
 freebsd/sys/dev/xilinx/axidma.h   |   96 ++
 freebsd/sys/dev/xilinx/if_xae.c   | 1108 +
 freebsd/sys/dev/xilinx/if_xaereg.h|  122 ++
 freebsd/sys/dev/xilinx/if_xaevar.h|   80 ++
 .../sys/microblaze/include/machine/in_cksum.h |   83 ++
 libbsd.py |   41 +-
 rtemsbsd/include/bsp/nexus-devices.h  |   10 +-
 rtemsbsd/include/rtems/bsd/local/xdma_if.h|  144 +++
 rtemsbsd/local/xdma_if.c  |   57 +
 .../rtems/bsd/test/network-config.h.in|2 +
 20 files changed, 4401 insertions(+), 4 deletions(-)
 create mode 100644 freebsd/sys/dev/mii/tiphy.h
 create mode 100644 freebsd/sys/dev/xdma/xdma.c
 create mode 100644 freebsd/sys/dev/xdma/xdma.h
 create mode 100644 freebsd/sys/dev/xdma/xdma_bank.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_mbuf.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_queue.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sg.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sglist.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xae.c
 create mode 100644 freebsd/sys/dev/xilinx/if_xaereg.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xaevar.h
 create mode 100644 freebsd/sys/microblaze/include/machine/in_cksum.h
 create mode 100644 rtemsbsd/include/rtems/bsd/local/xdma_if.h
 create mode 100644 rtemsbsd/local/xdma_if.c

-- 
2.30.2

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[PATCH rtems-libbsd v2 1/3] Add MicroBlaze support

[Alex White]

From: Jennifer Averett 

---
 .../sys/microblaze/include/machine/in_cksum.h | 83 +++
 libbsd.py |  6 +-
 2 files changed, 86 insertions(+), 3 deletions(-)
 create mode 100644 freebsd/sys/microblaze/include/machine/in_cksum.h

diff --git a/freebsd/sys/microblaze/include/machine/in_cksum.h 
b/freebsd/sys/microblaze/include/machine/in_cksum.h
new file mode 100644
index ..d55b838b
--- /dev/null
+++ b/freebsd/sys/microblaze/include/machine/in_cksum.h
@@ -0,0 +1,83 @@
+/*-
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *may be used to endorse or promote products derived from this software
+ *without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from tahoe: in_cksum.c  1.2 86/01/05
+ * from:   @(#)in_cksum.c  1.3 (Berkeley) 1/19/91
+ * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
+ * from: src/sys/alpha/include/in_cksum.h,v 1.7 2005/03/02 21:33:20 joerg
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE_IN_CKSUM_H_
+#define_MACHINE_IN_CKSUM_H_1
+
+#include 
+
+#definein_cksum(m, len)in_cksum_skip(m, len, 0)
+
+#if defined(IPVERSION) && (IPVERSION == 4)
+/*
+ * It it useful to have an Internet checksum routine which is inlineable
+ * and optimized specifically for the task of computing IP header checksums
+ * in the normal case (where there are no options and the header length is
+ * therefore always exactly five 32-bit words.
+ */
+#ifdef __CC_SUPPORTS___INLINE
+
+static __inline void
+in_cksum_update(struct ip *ip)
+{
+   int __tmpsum;
+   __tmpsum = (int)ntohs(ip->ip_sum) + 256;
+   ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
+}
+
+#else
+
+#definein_cksum_update(ip) 
\
+   do {\
+   int __tmpsum;   \
+   __tmpsum = (int)ntohs(ip->ip_sum) + 256;\
+   ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));\
+   } while(0)
+
+#endif
+#endif
+
+#ifdef _KERNEL
+#if defined(IPVERSION) && (IPVERSION == 4)
+u_int in_cksum_hdr(const struct ip *ip);
+#endif
+u_short in_addword(u_short sum, u_short b);
+u_short in_pseudo(u_int sum, u_int b, u_int c);
+u_short in_cksum_skip(struct mbuf *m, int len, int skip);
+#endif
+
+#endif /* _MACHINE_IN_CKSUM_H_ */
diff --git a/libbsd.py b/libbsd.py
index 7593e9ba..d57a15c5 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -5186,7 +5186,7 @@ class in_cksum(builder.Module):
 )
 self.addTargetSourceCPUDependentHeaderFiles(
 [ 'arm', 'avr', 'bfin', 'h8300', 'lm32', 'm32c', 'm32r', 'm68k',
-  'nios2', 'sh', 'sparc', 'v850' ],
+  'microblaze', 'nios2', 'sh', 'sparc', 'v850' ],
 'mips',
 [
 'sys/mips/include/in_cksum.h',
@@ -5223,8 +5223,8 @@ class in_cksum(builder.Module):
 self.addCPUDependentFreeBSDSourceFiles(
 [
 'arm', 'avr', 'bfin', 'h8300', 'lm32', 'm32c', 'm32r', 'm68k',
-'mips', 'moxie', 'nios2', 'or1k', 'riscv', 'sh', 'sparc',
-'v850'
+'microblaze', 'mips', 'moxie', 'nios2', 'or1k', 'riscv', 'sh',
+'sparc', 'v850'
 ],
 [
 'sys/mips/mips/in_cksum.c',
-- 
2.30.2

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[PATCH rtems-libbsd v2 2/3] if_xae: Import from FreeBSD

[Alex White]

From: Jennifer Averett 

---
 freebsd/sys/dev/mii/tiphy.h|   57 ++
 freebsd/sys/dev/xdma/xdma.c|  498 +
 freebsd/sys/dev/xdma/xdma.h|  274 +++
 freebsd/sys/dev/xdma/xdma_bank.c   |  100 +++
 freebsd/sys/dev/xdma/xdma_mbuf.c   |  151 
 freebsd/sys/dev/xdma/xdma_queue.c  |  126 
 freebsd/sys/dev/xdma/xdma_sg.c |  648 
 freebsd/sys/dev/xdma/xdma_sglist.c |  103 +++
 freebsd/sys/dev/xilinx/axidma.c|  650 
 freebsd/sys/dev/xilinx/axidma.h|   96 +++
 freebsd/sys/dev/xilinx/if_xae.c| 1099 
 freebsd/sys/dev/xilinx/if_xaereg.h |  122 +++
 freebsd/sys/dev/xilinx/if_xaevar.h |   80 ++
 13 files changed, 4004 insertions(+)
 create mode 100644 freebsd/sys/dev/mii/tiphy.h
 create mode 100644 freebsd/sys/dev/xdma/xdma.c
 create mode 100644 freebsd/sys/dev/xdma/xdma.h
 create mode 100644 freebsd/sys/dev/xdma/xdma_bank.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_mbuf.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_queue.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sg.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sglist.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xae.c
 create mode 100644 freebsd/sys/dev/xilinx/if_xaereg.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xaevar.h

diff --git a/freebsd/sys/dev/mii/tiphy.h b/freebsd/sys/dev/mii/tiphy.h
new file mode 100644
index ..d3c35575
--- /dev/null
+++ b/freebsd/sys/dev/mii/tiphy.h
@@ -0,0 +1,57 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin 
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Texas Instruments DP83867IR/CR Robust, High Immunity
+ * 10/100/1000 Ethernet Physical Layer Transceiver.
+ */
+
+#ifndef _DEV_MII_TIPHY_H_
+#define _DEV_MII_TIPHY_H_
+
+#defineDP83867_PHYCR   0x10/* PHY Control Register 
*/
+#define PHYCR_SGMII_EN (1 << 11)
+#defineDP83867_CFG20x14/* Configuration 
Register 2 */
+#define CFG2_SPEED_OPT_10M_EN  (1 << 6) /* Speed Optimization 
*/
+#define CFG2_SPEED_OPT_ENHANCED_EN (1 << 8)
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_S   10
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_M   (0x3 << 
CFG2_SPEED_OPT_ATTEMPT_CNT_S)
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_1   (0 << 
CFG2_SPEED_OPT_ATTEMPT_CNT_S)
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_2   (1 << 
CFG2_SPEED_OPT_ATTEMPT_CNT_S)
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_4   (2 << 
CFG2_SPEED_OPT_ATTEMPT_CNT_S)
+#define CFG2_SPEED_OPT_ATTEMPT_CNT_8   (3 << 
CFG2_SPEED_OPT_ATTEMPT_CNT_S)
+#define CFG2_INTERRUPT_POLARITY(1 << 13) /* Int pin is active 
low. */
+#defineDP83867_CFG40x31 /* Configuration Register 
4 */
+
+#endif /* !_DEV_MII_TIPHY_H_ */
diff --git a/freebsd/sys/dev/xdma/xdma.c b/freebsd/sys/dev/xdma/xdma.c
new file mode 100644
index ..685fedcc
--- /dev/null
+++ b/freebsd/sys/dev/xdma/xdma.c
@@ -0,0 +1,498 @@
+#include 
+
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2016-2019 Ruslan Bukin 
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
+ * ("CTSRD"), as part of the 

[PATCH rtems-libbsd v2 3/3] if_xae: Port to RTEMS

[Alex White]

---
 buildset/default.ini  |   1 +
 freebsd/sys/dev/xdma/xdma.c   |   3 +
 freebsd/sys/dev/xdma/xdma.h   |  11 ++
 freebsd/sys/dev/xdma/xdma_sg.c|  13 ++
 freebsd/sys/dev/xilinx/axidma.c   |  27 
 freebsd/sys/dev/xilinx/if_xae.c   |   9 ++
 libbsd.py |  35 +
 rtemsbsd/include/bsp/nexus-devices.h  |  10 +-
 rtemsbsd/include/rtems/bsd/local/xdma_if.h| 144 ++
 rtemsbsd/local/xdma_if.c  |  57 +++
 .../rtems/bsd/test/network-config.h.in|   2 +
 11 files changed, 311 insertions(+), 1 deletion(-)
 create mode 100644 rtemsbsd/include/rtems/bsd/local/xdma_if.h
 create mode 100644 rtemsbsd/local/xdma_if.c

diff --git a/buildset/default.ini b/buildset/default.ini
index 454cc74e..1113c26f 100644
--- a/buildset/default.ini
+++ b/buildset/default.ini
@@ -23,6 +23,7 @@ dev_nic = on
 dev_nic_broadcomm = on
 dev_nic_dc = on
 dev_nic_e1000 = on
+dev_nic_xilinx = on
 dev_nic_fxp = on
 dev_nic_re = on
 dev_nic_smc = on
diff --git a/freebsd/sys/dev/xdma/xdma.c b/freebsd/sys/dev/xdma/xdma.c
index 685fedcc..98426f07 100644
--- a/freebsd/sys/dev/xdma/xdma.c
+++ b/freebsd/sys/dev/xdma/xdma.c
@@ -54,6 +54,9 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 #endif
+#ifdef __rtems__
+#define IN_XDMA_C
+#endif /* __rtems__ */
 
 #include 
 
diff --git a/freebsd/sys/dev/xdma/xdma.h b/freebsd/sys/dev/xdma/xdma.h
index 583ad63e..685047ab 100644
--- a/freebsd/sys/dev/xdma/xdma.h
+++ b/freebsd/sys/dev/xdma/xdma.h
@@ -36,6 +36,9 @@
 
 #include 
 #include 
+#ifdef __rtems__
+#include 
+#endif /* __rtems__ */
 
 enum xdma_direction {
XDMA_MEM_TO_MEM,
@@ -181,7 +184,15 @@ struct xdma_intr_handler {
TAILQ_ENTRY(xdma_intr_handler)  ih_next;
 };
 
+#ifndef __rtems__
 static MALLOC_DEFINE(M_XDMA, "xdma", "xDMA framework");
+#else /* __rtems__ */
+#ifdef IN_XDMA_C
+MALLOC_DEFINE(M_XDMA, "xdma", "xDMA framework");
+#else
+MALLOC_DECLARE(M_XDMA);
+#endif
+#endif /* __rtems__ */
 
 #defineXCHAN_LOCK(xchan)   mtx_lock(&(xchan)->mtx_lock)
 #defineXCHAN_UNLOCK(xchan) mtx_unlock(&(xchan)->mtx_lock)
diff --git a/freebsd/sys/dev/xdma/xdma_sg.c b/freebsd/sys/dev/xdma/xdma_sg.c
index c8856c5c..f0e5f187 100644
--- a/freebsd/sys/dev/xdma/xdma_sg.c
+++ b/freebsd/sys/dev/xdma/xdma_sg.c
@@ -75,11 +75,13 @@ xchan_bufs_free_reserved(xdma_channel_t *xchan)
for (i = 0; i < xchan->xr_num; i++) {
xr = >xr_mem[i];
size = xr->buf.size;
+#ifndef __rtems__
if (xr->buf.vaddr) {
pmap_kremove_device(xr->buf.vaddr, size);
kva_free(xr->buf.vaddr, size);
xr->buf.vaddr = 0;
}
+#endif /* __rtems__ */
if (xr->buf.paddr) {
vmem_free(xchan->vmem, xr->buf.paddr, size);
xr->buf.paddr = 0;
@@ -99,12 +101,15 @@ xchan_bufs_alloc_reserved(xdma_channel_t *xchan)
 
xdma = xchan->xdma;
 
+#ifndef __rtems__
if (xchan->vmem == NULL)
return (ENOBUFS);
+#endif /* __rtems__ */
 
for (i = 0; i < xchan->xr_num; i++) {
xr = >xr_mem[i];
size = round_page(xchan->maxsegsize);
+#ifndef __rtems__
if (vmem_alloc(xchan->vmem, size,
M_BESTFIT | M_NOWAIT, )) {
device_printf(xdma->dev,
@@ -116,13 +121,19 @@ xchan_bufs_alloc_reserved(xdma_channel_t *xchan)
xr->buf.size = size;
xr->buf.paddr = addr;
xr->buf.vaddr = kva_alloc(size);
+#else /* __rtems__ */
+   xr->buf.vaddr = calloc(1,size);
+   xr->buf.paddr = xr->buf.vaddr;
+#endif /* __rtems__ */
if (xr->buf.vaddr == 0) {
device_printf(xdma->dev,
"%s: Can't allocate KVA\n", __func__);
xchan_bufs_free_reserved(xchan);
return (ENOMEM);
}
+#ifndef __rtems__
pmap_kenter_device(xr->buf.vaddr, size, addr);
+#endif /* __rtems__ */
}
 
return (0);
@@ -408,6 +419,7 @@ _xdma_load_data_busdma(xdma_channel_t *xchan, struct 
xdma_request *xr,
error = bus_dmamap_load_mbuf_sg(xchan->dma_tag_bufs,
xr->buf.map, xr->m, seg, , BUS_DMA_NOWAIT);
break;
+#ifndef __rtems__
case XR_TYPE_BIO:
slr.nsegs = 0;
slr.error = 0;
@@ -422,6 +434,7 @@ _xdma_load_data_busdma(xdma_channel_t *xchan, struct 
xdma_request *xr,
}
nsegs = slr.nsegs;
break;
+#endif /* __rtems__ */
case XR_TYPE_VIRT:
switch (xr->direction) {
case XDMA_MEM_TO_DEV:
diff --git a/freebsd/sys/dev/xilinx/axidma.c 

[PATCH RSB] microblaze: Add GCC patch to define __ELF__

[Alex White]

This fixes compilation errors in rtems-libbsd.
---
 rtems/config/tools/rtems-xilinx-gcc-10-newlib-head.cfg | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/rtems/config/tools/rtems-xilinx-gcc-10-newlib-head.cfg 
b/rtems/config/tools/rtems-xilinx-gcc-10-newlib-head.cfg
index a83fe46..5366457 100644
--- a/rtems/config/tools/rtems-xilinx-gcc-10-newlib-head.cfg
+++ b/rtems/config/tools/rtems-xilinx-gcc-10-newlib-head.cfg
@@ -44,3 +44,6 @@
 
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4481/0002-config-microblaze-crti.S-Add-single-underscore-init-.patch
 %hash sha512 0002-config-microblaze-crti.S-Add-single-underscore-init-.patch 
bf1ec7eff0dd51d154dd0507edb085458c90a000f5a3ccefb1064147cf8fdafe0111d2094372e164976f2193c289bff9ea63dcad43555c90893272a494b7e779
+
+%patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4589/0001-microblaze-Define-__ELF__-for-RTEMS-target.patch
+%hash sha512 0001-microblaze-Define---ELF---for-RTEMS-target.patch 
39c0666c2e5c560447f00ed913cd07261e9c0db05b0cc549400667013ccf1d4140c0bd7b012d60dd628235bf7ae27564460a45e969e9cff75d14ed94bfd82632
-- 
2.30.2

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[PATCH] microblaze: Change fdt code license to BSD 2-Clause

[Alex White]

---
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c | 28 +++
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c 
b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
index 2b766ece0c..4725af40e0 100644
--- a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
+++ b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
@@ -1,10 +1,28 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /*
- *  COPYRIGHT (c) 2021.
- *  On-Line Applications Research Corporation (OAR).
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
  *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include 
-- 
2.30.2

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Re: [PATCH rtems-libbsd 2/2] microblaze: Finish AXI Ethernet support

[Alex White]

On Thu, Jan 20, 2022 at 12:12 AM Sebastian Huber 
 wrote:
>
> On 20/01/2022 04:54, Alex White wrote:
> > diff --git a/freebsd/sys/netinet/tcp_input.c 
> > b/freebsd/sys/netinet/tcp_input.c
> > index fc111d9c..60f9123a 100644
> > --- a/freebsd/sys/netinet/tcp_input.c
> > +++ b/freebsd/sys/netinet/tcp_input.c
> > @@ -721,6 +721,15 @@ tcp_input(struct mbuf **mp, int *offp, int proto)
> >   }
> >   #endif /* INET */
> >  
> > +#ifdef __rtems__
> > +#ifdef __MICROBLAZE__
> > + /* Ensure that the TCP header is properly aligned in memory. */
> > + struct tcphdr aligned_hdr;
> > + memcpy(_hdr, th, sizeof(struct tcphdr));
> > + th = _hdr;
> > +#endif
> > +#endif
> > +
> >   /*
> >* Check that TCP offset makes sense,
> >* pull out TCP options and adjust length.  XXX
>
> Changes like this should not be hidden in a driver-specific patch. The
> alignment changes are hacks. Why don't you fix the Ethernet frame
> alignment in the network interface driver?
>

I have made the realization while testing fixes for this that if I
change the definition of struct tcphdr in netinet/tcp.h to include
__attribute__((packed)), GCC generates code that avoids the unaligned
memory access. This removes the need for any code to handle memory
alignment of the network headers.

I then noticed that you had some notes on what I think is this same
phenomenon at freebsd/contrib/libpcap/extract.h line 40.

Since, for example, the ip struct in netinet/ip.h is defined as packed,
shouldn't the tcphdr struct be packed, too?

In addition, struct tcphdr is being used to represent raw bytes on the
wire so it makes sense to declare it as packed so no padding is
included.

The initial solution I came up with was to change
newlib/libc/sys/rtems/include/netinet/tcp.h in newlib to add
__attribute__((packed)) to struct tcphdr . This could be added inside
an #ifdef __microblaze__ to minimize impact elsewhere. This would, of
course, diverge from FreeBSD's netinet/tcp.h.

Does that sound like a reasonable solution?

Thanks,

Alex
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Re: [PATCH rtems-libbsd 1/2] microblaze: Add AXI Ethernet support

[Alex White]

On Thu, Jan 20, 2022 at 12:30 AM Chris Johns  wrote:
>
> On 20/1/22 2:54 pm, Alex White wrote:
> > From: Jennifer Averett 
> >  rtemsbsd/rtems/rtems-kernel-vmem.c|   17 +
> > diff --git a/rtemsbsd/rtems/rtems-kernel-vmem.c 
> > b/rtemsbsd/rtems/rtems-kernel-vmem.c
> > index f64fbd17..70708902 100644
> > --- a/rtemsbsd/rtems/rtems-kernel-vmem.c
> > +++ b/rtemsbsd/rtems/rtems-kernel-vmem.c
> > @@ -41,6 +41,11 @@
> >
> >  static MALLOC_DEFINE(M_VMEM, "vmem", "VMEM buffers");
> >
> > +int vmem_add(vmem_t *vm, vmem_addr_t addr, vmem_size_t size, int flags)
> > +{
> > + return 0;
> > +}
> > +
> >  int
> >  vmem_alloc(vmem_t *vm, vmem_size_t size, int flags, vmem_addr_t *addrp)
> >  {
> > @@ -48,6 +53,18 @@ vmem_alloc(vmem_t *vm, vmem_size_t size, int flags, 
> > vmem_addr_t *addrp)
> >   return 0;
> >  }
> >
> > +static int dummy_vmem;
> > +
> > +vmem_t *vmem_create(const char *name, vmem_addr_t base,
> > +vmem_size_t size, vmem_size_t quantum, vmem_size_t qcache_max, int 
> > flags)
> > +{
> > + return _vmem;
> > +}
> > +
> > +void vmem_destroy(vmem_t *vm)
> > +{
> > +}
> > +
> >  void
> >  vmem_free(vmem_t *vm, vmem_addr_t addr, vmem_size_t size)
> >  {
>
> What is pulling this interface in?

The added vmem functions are pulled in by freebsd/sys/dev/xdma/xdma.c

>
> Why have they been stubbed out?

They were stubbed out to provide the minimal implementation needed to get xdma 
working, and xdma
is ultimately used by the AXI Ethernet subsystem.

The alternatives we saw were to pull in the full FreeBSD vmem implementation 
(overkill) or modify
freebsd/sys/dev/xdma/xdma.c to not use vmem functions.

Alex

>
> Chris
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[PATCH rtems-libbsd 1/2] microblaze: Add AXI Ethernet support

[Alex White]

From: Jennifer Averett 

---
 buildset/default.ini  |1 +
 freebsd/sys/dev/mii/tiphy.h   |   57 +
 freebsd/sys/dev/xdma/xdma.c   |  501 
 freebsd/sys/dev/xdma/xdma.h   |  285 +
 freebsd/sys/dev/xdma/xdma_bank.c  |  100 ++
 freebsd/sys/dev/xdma/xdma_mbuf.c  |  151 +++
 freebsd/sys/dev/xdma/xdma_queue.c |  126 ++
 freebsd/sys/dev/xdma/xdma_sg.c|  660 ++
 freebsd/sys/dev/xdma/xdma_sglist.c|  103 ++
 freebsd/sys/dev/xilinx/axidma.c   |  666 ++
 freebsd/sys/dev/xilinx/axidma.h   |   96 ++
 freebsd/sys/dev/xilinx/if_xae.c   |  +
 freebsd/sys/dev/xilinx/if_xaereg.h|  122 ++
 freebsd/sys/dev/xilinx/if_xaevar.h|   80 ++
 .../sys/microblaze/include/machine/in_cksum.h |   82 ++
 freebsd/sys/microblaze/microblaze/in_cksum.c  |  255 
 libbsd.py |   43 +
 rtemsbsd/include/bsp/nexus-devices.h  |   10 +-
 rtemsbsd/include/rtems/bsd/local/xdma_if.h|  144 +++
 rtemsbsd/local/xdma_if.c  |   57 +
 rtemsbsd/rtems/rtems-kernel-vmem.c|   17 +
 21 files changed, 4666 insertions(+), 1 deletion(-)
 create mode 100644 freebsd/sys/dev/mii/tiphy.h
 create mode 100644 freebsd/sys/dev/xdma/xdma.c
 create mode 100644 freebsd/sys/dev/xdma/xdma.h
 create mode 100644 freebsd/sys/dev/xdma/xdma_bank.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_mbuf.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_queue.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sg.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sglist.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xae.c
 create mode 100644 freebsd/sys/dev/xilinx/if_xaereg.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xaevar.h
 create mode 100644 freebsd/sys/microblaze/include/machine/in_cksum.h
 create mode 100644 freebsd/sys/microblaze/microblaze/in_cksum.c
 create mode 100644 rtemsbsd/include/rtems/bsd/local/xdma_if.h
 create mode 100644 rtemsbsd/local/xdma_if.c

diff --git a/buildset/default.ini b/buildset/default.ini
index 454cc74e..1113c26f 100644
--- a/buildset/default.ini
+++ b/buildset/default.ini
@@ -23,6 +23,7 @@ dev_nic = on
 dev_nic_broadcomm = on
 dev_nic_dc = on
 dev_nic_e1000 = on
+dev_nic_xilinx = on
 dev_nic_fxp = on
 dev_nic_re = on
 dev_nic_smc = on
diff --git a/freebsd/sys/dev/mii/tiphy.h b/freebsd/sys/dev/mii/tiphy.h
new file mode 100644
index ..d3c35575
--- /dev/null
+++ b/freebsd/sys/dev/mii/tiphy.h
@@ -0,0 +1,57 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin 
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Texas Instruments DP83867IR/CR Robust, High Immunity
+ * 10/100/1000 Ethernet Physical Layer Transceiver.
+ */
+
+#ifndef _DEV_MII_TIPHY_H_
+#define _DEV_MII_TIPHY_H_
+
+#defineDP83867_PHYCR   0x10/* PHY Control Register 
*/
+#define PHYCR_SGMII_EN (1 << 11)
+#defineDP83867_CFG20x14/* Configuration 
Register 2 */
+#define CFG2_SPEED_OPT_10M_EN  (1 << 6) /* Speed Optimization 
*/
+#define CFG2_SPEED_OPT_ENHANCED_EN (1 << 8)
+#define 

[PATCH rtems-libbsd 2/2] microblaze: Finish AXI Ethernet support

[Alex White]

---
 freebsd/sys/dev/xdma/xdma_sg.c |  3 ++-
 freebsd/sys/dev/xilinx/axidma.c| 14 --
 freebsd/sys/dev/xilinx/if_xae.c|  4 ++--
 freebsd/sys/netinet/tcp_input.c|  9 +
 freebsd/sys/netinet/tcp_subr.c | 10 ++
 freebsd/sys/netinet6/ip6_input.c   | 10 ++
 .../include/rtems/bsd/test/network-config.h.in |  2 ++
 7 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/freebsd/sys/dev/xdma/xdma_sg.c b/freebsd/sys/dev/xdma/xdma_sg.c
index fa69a297..74fad421 100644
--- a/freebsd/sys/dev/xdma/xdma_sg.c
+++ b/freebsd/sys/dev/xdma/xdma_sg.c
@@ -107,6 +107,7 @@ xchan_bufs_alloc_reserved(xdma_channel_t *xchan)
for (i = 0; i < xchan->xr_num; i++) {
xr = >xr_mem[i];
size = round_page(xchan->maxsegsize);
+#ifndef __rtems__
if (vmem_alloc(xchan->vmem, size,
M_BESTFIT | M_NOWAIT, )) {
device_printf(xdma->dev,
@@ -117,10 +118,10 @@ xchan_bufs_alloc_reserved(xdma_channel_t *xchan)

xr->buf.size = size;
xr->buf.paddr = addr;
-#ifndef __rtems__
xr->buf.vaddr = kva_alloc(size);
 #else
xr->buf.vaddr = calloc(1,size);
+   xr->buf.paddr = xr->buf.vaddr;
 #endif
if (xr->buf.vaddr == 0) {
device_printf(xdma->dev,
diff --git a/freebsd/sys/dev/xilinx/axidma.c b/freebsd/sys/dev/xilinx/axidma.c
index 00ae2f1d..4fbb3104 100644
--- a/freebsd/sys/dev/xilinx/axidma.c
+++ b/freebsd/sys/dev/xilinx/axidma.c
@@ -68,6 +68,8 @@ __FBSDID("$FreeBSD$");
 
 #ifdef __rtems__
 #include 
+
+#define AXIDMA_DESCRIPTOR_ALIGNMENT 64
 #endif
 
 #ifdef AXIDMA_DEBUG
@@ -182,6 +184,10 @@ axidma_intr(struct axidma_softc *sc,
 
st.error = errors;
st.transferred = desc->status & BD_CONTROL_LEN_M;
+   /* Handle Control / Status Streams. */
+   if (!st.transferred) {
+   st.transferred = desc->app4 & 0xFF;
+   }
tot_copied += st.transferred;
xchan_seg_done(xchan, );
 
@@ -362,16 +368,20 @@ axidma_desc_alloc(struct axidma_softc *sc, struct 
xdma_channel *xchan,
chan->descs_phys = malloc(nsegments * sizeof(bus_dma_segment_t),
M_DEVBUF, M_NOWAIT | M_ZERO);
chan->mem_size = desc_size * nsegments;
+#ifndef __rtems__
if (vmem_alloc(xchan->vmem, chan->mem_size, M_FIRSTFIT | M_NOWAIT,
>mem_paddr)) {
device_printf(sc->dev, "Failed to allocate memory.\n");
return (-1);
}
-#ifndef __rtems__
chan->mem_vaddr = kva_alloc(chan->mem_size);
pmap_kenter_device(chan->mem_vaddr, chan->mem_size, chan->mem_paddr);
 #else
-   chan->mem_vaddr = calloc(1, chan->mem_size);
+   /* Align DMA descriptors */
+   chan->mem_vaddr = calloc(1, chan->mem_size + 
AXIDMA_DESCRIPTOR_ALIGNMENT - 1);
+   chan->mem_vaddr = ((uintptr_t)chan->mem_vaddr +
+   AXIDMA_DESCRIPTOR_ALIGNMENT - 1) & ~0x3F;
+   chan->mem_paddr = chan->mem_vaddr;
 #endif
 
device_printf(sc->dev, "Allocated chunk %lx %d\n",
diff --git a/freebsd/sys/dev/xilinx/if_xae.c b/freebsd/sys/dev/xilinx/if_xae.c
index 0582a588..3b23c5d4 100644
--- a/freebsd/sys/dev/xilinx/if_xae.c
+++ b/freebsd/sys/dev/xilinx/if_xae.c
@@ -729,7 +729,7 @@ xae_miibus_read_reg(device_t dev, int phy, int reg)
 #if defined(__rtems__) && defined(DEBUG_MII)
dprintf("%s: reg: %d phy %d val 0x%x\n", __func__, reg, phy, rv);
 #endif
-   return (rv);
+   return (rv & 0x);
 }
 
 static int
@@ -980,7 +980,7 @@ xae_attach(device_t dev)
sc->mii_softc = device_get_softc(sc->miibus);
 
/* Apply vcu118 workaround. */
-   // if (OF_getproplen(node, "xlnx,vcu118") >= 0)
+   if (OF_getproplen(node, "xlnx,vcu118") >= 0)
xae_phy_fixup(sc);
 
/* All ready to run, attach the ethernet interface. */
diff --git a/freebsd/sys/netinet/tcp_input.c b/freebsd/sys/netinet/tcp_input.c
index fc111d9c..60f9123a 100644
--- a/freebsd/sys/netinet/tcp_input.c
+++ b/freebsd/sys/netinet/tcp_input.c
@@ -721,6 +721,15 @@ tcp_input(struct mbuf **mp, int *offp, int proto)
}
 #endif /* INET */
 
+#ifdef __rtems__
+#ifdef __MICROBLAZE__
+   /* Ensure that the TCP header is properly aligned in memory. */
+   struct tcphdr aligned_hdr;
+   memcpy(_hdr, th, sizeof(struct tcphdr));
+   th = _hdr;
+#endif
+#endif
+
/*
 * Check that TCP offset makes sense,
 * pull out TCP options and adjust length.  XXX
diff --git a/freebsd/sys/netinet/tcp_subr.c b/freebsd/sys/netinet/tcp_subr.c
index eae696c1..d0025c01 100644
--- a/freebsd/sys/netinet/tcp_subr.c
+++ b/freebsd/sys/netinet/tcp_subr.c
@@ -1520,6 +1520,16 @@ tcp_respond(struct tcpcb *tp, void 

[PATCH rtems-libbsd 0/2] MicroBlaze AXI Ethernet Support

[Alex White]

This patch set adds support for Xilinx's AXI Ethernet IP core. It has
been tested both in QEMU and on the KCU105 board using the default
FPGA implementation from the Xilinx's KCU105 PetaLinux BSP.


Alex White (1):
  microblaze: Finish AXI Ethernet support

Jennifer Averett (1):
  microblaze: Add AXI Ethernet support

 buildset/default.ini  |1 +
 freebsd/sys/dev/mii/tiphy.h   |   57 +
 freebsd/sys/dev/xdma/xdma.c   |  501 
 freebsd/sys/dev/xdma/xdma.h   |  285 +
 freebsd/sys/dev/xdma/xdma_bank.c  |  100 ++
 freebsd/sys/dev/xdma/xdma_mbuf.c  |  151 +++
 freebsd/sys/dev/xdma/xdma_queue.c |  126 ++
 freebsd/sys/dev/xdma/xdma_sg.c|  661 ++
 freebsd/sys/dev/xdma/xdma_sglist.c|  103 ++
 freebsd/sys/dev/xilinx/axidma.c   |  676 ++
 freebsd/sys/dev/xilinx/axidma.h   |   96 ++
 freebsd/sys/dev/xilinx/if_xae.c   |  +
 freebsd/sys/dev/xilinx/if_xaereg.h|  122 ++
 freebsd/sys/dev/xilinx/if_xaevar.h|   80 ++
 .../sys/microblaze/include/machine/in_cksum.h |   82 ++
 freebsd/sys/microblaze/microblaze/in_cksum.c  |  255 
 freebsd/sys/netinet/tcp_input.c   |9 +
 freebsd/sys/netinet/tcp_subr.c|   10 +
 freebsd/sys/netinet6/ip6_input.c  |   10 +
 libbsd.py |   43 +
 rtemsbsd/include/bsp/nexus-devices.h  |   10 +-
 rtemsbsd/include/rtems/bsd/local/xdma_if.h|  144 +++
 rtemsbsd/local/xdma_if.c  |   57 +
 rtemsbsd/rtems/rtems-kernel-vmem.c|   17 +
 .../rtems/bsd/test/network-config.h.in|2 +
 25 files changed, 4708 insertions(+), 1 deletion(-)
 create mode 100644 freebsd/sys/dev/mii/tiphy.h
 create mode 100644 freebsd/sys/dev/xdma/xdma.c
 create mode 100644 freebsd/sys/dev/xdma/xdma.h
 create mode 100644 freebsd/sys/dev/xdma/xdma_bank.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_mbuf.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_queue.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sg.c
 create mode 100644 freebsd/sys/dev/xdma/xdma_sglist.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.c
 create mode 100644 freebsd/sys/dev/xilinx/axidma.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xae.c
 create mode 100644 freebsd/sys/dev/xilinx/if_xaereg.h
 create mode 100644 freebsd/sys/dev/xilinx/if_xaevar.h
 create mode 100644 freebsd/sys/microblaze/include/machine/in_cksum.h
 create mode 100644 freebsd/sys/microblaze/microblaze/in_cksum.c
 create mode 100644 rtemsbsd/include/rtems/bsd/local/xdma_if.h
 create mode 100644 rtemsbsd/local/xdma_if.c

-- 
2.30.2

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH v2 1/2] microblaze: Add support for libbsd.

[Alex White]

From: Jennifer Averett 

---
 .../microblaze_fpga/dts/microblaze-dtb.c  | 962 ++
 .../microblaze/microblaze_fpga/dts/system.dts | 452 
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  21 +
 bsps/microblaze/microblaze_fpga/include/bsp.h |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
 5 files changed, 1441 insertions(+)
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/system.dts
 create mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c

diff --git a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c 
b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
new file mode 100644
index 00..ad72fac0b8
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
@@ -0,0 +1,962 @@
+/*
+ *  Declarations for C structure representing binary file system.dtb
+ *
+ *  WARNING: Automatically generated -- do not edit!
+ */
+
+#include 
+
+const unsigned char system_dtb[] = {
+  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38, 
+  0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, 
+  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5, 
+  0x00, 0x00, 0x1c, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1b, 
+  0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 
+  0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12, 
+  0x00, 0x00, 0x00, 0x26, 0x58, 0x69, 0x6c, 0x69, 0x6e, 0x78, 0x20, 0x4d, 
+  0x69, 0x63, 0x72, 0x6f, 0x42, 0x6c, 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40, 0x30, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x32, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x3d, 0x05, 0xf5, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x02, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x1b, 
+  0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 
+  0x61, 0x7a, 0x65, 0x2d, 0x31, 0x31, 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x54, 
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x65, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x88, 
+  0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x95, 0x63, 0x70, 0x75, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xa1, 0x80, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb2, 
+  0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xd5, 0x00, 0x00, 0x80, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe2, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x26, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 0x61, 
+  0x7a, 0x65, 0x2c, 0x31, 0x31, 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf7, 
+  0x05, 0xf5, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x19, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x2c, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x01, 0x41, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x6a, 
+  0x00, 0x00, 0x00, 

[PATCH v2 2/2] microblaze: Add support for libbsd networking

[Alex White]

This includes fixes and improvements necessary to get libbsd networking
running.
---
 .../microblaze/microblaze_fpga/dts/system.dts |  4 +--
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  3 ++
 bsps/microblaze/microblaze_fpga/include/bsp.h |  5 
 .../bsp/microblaze-dtb.h} | 12 ++--
 bsps/microblaze/microblaze_fpga/irq/irq.c |  2 +-
 .../microblaze_fpga/start/bspstart.c  |  6 
 .../start/microblaze_enable_dcache.S  | 20 +
 .../start/microblaze_enable_icache.S  | 20 +
 .../start/microblaze_invalidate_dcache.S  | 29 +++
 .../start/microblaze_invalidate_icache.S  | 28 ++
 cpukit/score/cpu/microblaze/cpu.c |  1 -
 cpukit/score/cpu/microblaze/cpu_asm.S |  4 +--
 .../bsps/microblaze/microblaze_fpga/grp.yml   | 14 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |  5 +++-
 .../microblaze_fpga/optdcachebaseaddress.yml  | 18 
 .../microblaze_fpga/optdcachelinelen.yml  | 17 +++
 .../microblaze_fpga/optdcachesize.yml | 17 +++
 .../microblaze_fpga/optdtbheaderpath.yml  | 17 +++
 .../microblaze_fpga/opticachebaseaddress.yml  | 18 
 .../microblaze_fpga/opticachelinelen.yml  | 17 +++
 .../microblaze_fpga/opticachesize.yml | 17 +++
 21 files changed, 263 insertions(+), 11 deletions(-)
 rename bsps/microblaze/microblaze_fpga/{dts/microblaze-dtb.c => 
include/bsp/microblaze-dtb.h} (99%)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml

diff --git a/bsps/microblaze/microblaze_fpga/dts/system.dts 
b/bsps/microblaze/microblaze_fpga/dts/system.dts
index 587d569f03..9972e753d2 100644
--- a/bsps/microblaze/microblaze_fpga/dts/system.dts
+++ b/bsps/microblaze/microblaze_fpga/dts/system.dts
@@ -222,7 +222,7 @@
phandle = <0x6>;
dmas = < 0
 1>;
-   dma-names = "rx", "tx";
+   dma-names = "tx", "rx";
memory-region = <_reserved>;
mdio {
#address-cells = <0x1>;
@@ -230,7 +230,7 @@
 
phy@1 {
device_type = "ethernet-phy";
-   reg = <0x1>;
+   reg = <0x7>;
phandle = <0x5>;
};
};
diff --git a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c 
b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
index e92f9e466e..2b766ece0c 100644
--- a/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
+++ b/bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
@@ -8,6 +8,9 @@
  */
 
 #include 
+#include 
+
+#include BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH
 
 const void *bsp_fdt_get(void)
 {
diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 49918c3353..93cf0e4b34 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -50,6 +50,11 @@ extern "C" {
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
 
+void microblaze_enable_icache(void);
+void microblaze_enable_dcache(void);
+void microblaze_invalidate_icache(void);
+void microblaze_invalidate_dcache(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c 
b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h
similarity index 99%
rename from bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
rename to bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h
index ad72fac0b8..e570db21b4 100644
--- a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
+++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h
@@ -4,9 +4,13 @@
  *  WARNING: Automatically generated -- do not edit!
  */
 
+#ifndef __microblaze_dtb_h
+#define __microblaze_dtb_h
+
+#include 
 

[PATCH v2 0/2] microblaze: libbsd support

[Alex White]

v2:
  - Added a new BSP configuration option, "BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH",
which allows the user to override the device tree to match their FPGA
configuration.

This patch set adds support for libbsd to the MicroBlaze BSPs and contains fixes
for issues found while debugging the rtems-libbsd telnetd01 test in QEMU and on
the Xilinx KCU105 board.

Alex White (1):
  microblaze: Add support for libbsd networking

Jennifer Averett (1):
  microblaze: Add support for libbsd.

 .../microblaze/microblaze_fpga/dts/system.dts | 452 
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  24 +
 bsps/microblaze/microblaze_fpga/include/bsp.h |   9 +
 .../include/bsp/microblaze-dtb.h  | 968 ++
 bsps/microblaze/microblaze_fpga/irq/irq.c |   2 +-
 .../microblaze_fpga/start/bspstart.c  |   6 +
 .../start/microblaze_enable_dcache.S  |  20 +
 .../start/microblaze_enable_icache.S  |  20 +
 .../start/microblaze_invalidate_dcache.S  |  29 +
 .../start/microblaze_invalidate_icache.S  |  28 +
 cpukit/score/cpu/microblaze/cpu.c |   1 -
 cpukit/score/cpu/microblaze/cpu_asm.S |   4 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  14 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   5 +
 .../microblaze_fpga/optdcachebaseaddress.yml  |  18 +
 .../microblaze_fpga/optdcachelinelen.yml  |  17 +
 .../microblaze_fpga/optdcachesize.yml |  17 +
 .../microblaze_fpga/optdtbheaderpath.yml  |  17 +
 .../microblaze_fpga/opticachebaseaddress.yml  |  18 +
 .../microblaze_fpga/opticachelinelen.yml  |  17 +
 .../microblaze_fpga/opticachesize.yml |  17 +
 21 files changed, 1698 insertions(+), 5 deletions(-)
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/system.dts
 create mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
 create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml

-- 
2.30.2

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH 2/2] microblaze: Add support for libbsd networking

[Alex White]

This includes fixes and improvements necessary to get libbsd networking
running.
---
 .../microblaze_fpga/dts/microblaze-dtb.c  |  7 +++--
 .../microblaze/microblaze_fpga/dts/system.dts |  4 +--
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  1 +
 bsps/microblaze/microblaze_fpga/include/bsp.h |  5 
 bsps/microblaze/microblaze_fpga/irq/irq.c |  2 +-
 .../microblaze_fpga/start/bspstart.c  |  6 
 .../start/microblaze_enable_dcache.S  | 20 +
 .../start/microblaze_enable_icache.S  | 20 +
 .../start/microblaze_invalidate_dcache.S  | 29 +++
 .../start/microblaze_invalidate_icache.S  | 28 ++
 cpukit/score/cpu/microblaze/cpu.c |  1 -
 cpukit/score/cpu/microblaze/cpu_asm.S |  4 +--
 .../bsps/microblaze/microblaze_fpga/grp.yml   | 12 
 .../bsps/microblaze/microblaze_fpga/obj.yml   |  4 +++
 .../microblaze_fpga/optdcachebaseaddress.yml  | 18 
 .../microblaze_fpga/optdcachelinelen.yml  | 17 +++
 .../microblaze_fpga/optdcachesize.yml | 17 +++
 .../microblaze_fpga/opticachebaseaddress.yml  | 18 
 .../microblaze_fpga/opticachelinelen.yml  | 17 +++
 .../microblaze_fpga/opticachesize.yml | 17 +++
 20 files changed, 237 insertions(+), 10 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml

diff --git a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c 
b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
index ad72fac0b8..2615089012 100644
--- a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
+++ b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
@@ -4,9 +4,10 @@
  *  WARNING: Automatically generated -- do not edit!
  */
 
+#include 
 #include 
 
-const unsigned char system_dtb[] = {
+const unsigned char system_dtb[] RTEMS_ALIGNED(8) = {
   0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38, 
   0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, 
   0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5, 
@@ -307,7 +308,7 @@ const unsigned char system_dtb[] = {
   0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 
   0x00, 0x00, 0x0c, 0xcc, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
   0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
-  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0c, 0xd1, 0x72, 0x78, 0x00, 0x74, 
+  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0c, 0xd1, 0x74, 0x78, 0x00, 0x72, 
   0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
   0x00, 0x00, 0x0c, 0xdb, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01, 
   0x6d, 0x64, 0x69, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
@@ -317,7 +318,7 @@ const unsigned char system_dtb[] = {
   0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0d, 
   0x00, 0x00, 0x00, 0x95, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 
   0x2d, 0x70, 0x68, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x01, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x07, 
   0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0a, 0x62, 
   0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 
   0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x64, 0x6d, 0x61, 0x40, 
diff --git a/bsps/microblaze/microblaze_fpga/dts/system.dts 
b/bsps/microblaze/microblaze_fpga/dts/system.dts
index 587d569f03..9972e753d2 100644
--- a/bsps/microblaze/microblaze_fpga/dts/system.dts
+++ b/bsps/microblaze/microblaze_fpga/dts/system.dts
@@ -222,7 +222,7 @@
phandle = <0x6>;
dmas = < 0
 1>;
-   dma-names = "rx", "tx";
+   dma-names = "tx", "rx";
memory-region = <_reserved>;
mdio {
#address-cells = <0x1>;
@@ -230,7 +230,7 @@
 
phy@1 {
device_type = 

[PATCH 1/2] microblaze: Add support for libbsd.

[Alex White]

From: Jennifer Averett 

---
 .../microblaze_fpga/dts/microblaze-dtb.c  | 962 ++
 .../microblaze/microblaze_fpga/dts/system.dts | 452 
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  21 +
 bsps/microblaze/microblaze_fpga/include/bsp.h |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +
 5 files changed, 1441 insertions(+)
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/system.dts
 create mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c

diff --git a/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c 
b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
new file mode 100644
index 00..ad72fac0b8
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
@@ -0,0 +1,962 @@
+/*
+ *  Declarations for C structure representing binary file system.dtb
+ *
+ *  WARNING: Automatically generated -- do not edit!
+ */
+
+#include 
+
+const unsigned char system_dtb[] = {
+  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38, 
+  0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, 
+  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5, 
+  0x00, 0x00, 0x1c, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1b, 
+  0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 
+  0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12, 
+  0x00, 0x00, 0x00, 0x26, 0x58, 0x69, 0x6c, 0x69, 0x6e, 0x78, 0x20, 0x4d, 
+  0x69, 0x63, 0x72, 0x6f, 0x42, 0x6c, 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40, 0x30, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x32, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x3d, 0x05, 0xf5, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x02, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x1b, 
+  0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 
+  0x61, 0x7a, 0x65, 0x2d, 0x31, 0x31, 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x54, 
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x65, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x88, 
+  0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0x95, 0x63, 0x70, 0x75, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xa1, 0x80, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb2, 
+  0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x00, 0xc3, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xd5, 0x00, 0x00, 0x80, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe2, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x26, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, 0x61, 
+  0x7a, 0x65, 0x2c, 0x31, 0x31, 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf7, 
+  0x05, 0xf5, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x19, 0x00, 0x00, 0x00, 0x10, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x2c, 
+  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 
+  0x00, 0x00, 0x01, 0x41, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x6a, 
+  0x00, 0x00, 0x00, 

[PATCH 0/2] microblaze: libbsd support

[Alex White]

This patch set adds support for libbsd to the MicroBlaze BSPs and contains fixes
for issues found while debugging the rtems-libbsd telnetd01 test in QEMU and on
the Xilinx KCU105 board.

Alex White (1):
  microblaze: Add support for libbsd networking

Jennifer Averett (1):
  microblaze: Add support for libbsd.

 .../microblaze_fpga/dts/microblaze-dtb.c  | 963 ++
 .../microblaze/microblaze_fpga/dts/system.dts | 452 
 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c |  22 +
 bsps/microblaze/microblaze_fpga/include/bsp.h |   9 +
 bsps/microblaze/microblaze_fpga/irq/irq.c |   2 +-
 .../microblaze_fpga/start/bspstart.c  |   6 +
 .../start/microblaze_enable_dcache.S  |  20 +
 .../start/microblaze_enable_icache.S  |  20 +
 .../start/microblaze_invalidate_dcache.S  |  29 +
 .../start/microblaze_invalidate_icache.S  |  28 +
 cpukit/score/cpu/microblaze/cpu.c |   1 -
 cpukit/score/cpu/microblaze/cpu_asm.S |   4 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  12 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   6 +
 .../microblaze_fpga/optdcachebaseaddress.yml  |  18 +
 .../microblaze_fpga/optdcachelinelen.yml  |  17 +
 .../microblaze_fpga/optdcachesize.yml |  17 +
 .../microblaze_fpga/opticachebaseaddress.yml  |  18 +
 .../microblaze_fpga/opticachelinelen.yml  |  17 +
 .../microblaze_fpga/opticachesize.yml |  17 +
 20 files changed, 1673 insertions(+), 5 deletions(-)
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
 create mode 100644 bsps/microblaze/microblaze_fpga/dts/system.dts
 create mode 100644 bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml

-- 
2.27.0

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[PATCH RSB 5] sb: Merge mailer changes from rtems-tools

[Alex White]

This adds the improved mailer.py script from rtems-tools.

Closes #4554
---
 source-builder/sb/mailer.py | 194 +---
 source-builder/sb/options.py|  26 +-
 source-builder/sb/setbuilder.py |   2 +
 3 files changed, 189 insertions(+), 33 deletions(-)

diff --git a/source-builder/sb/mailer.py b/source-builder/sb/mailer.py
index 42b4fa6..1d3cbb5 100644
--- a/source-builder/sb/mailer.py
+++ b/source-builder/sb/mailer.py
@@ -1,21 +1,33 @@
 #
 # RTEMS Tools Project (http://www.rtems.org/)
-# Copyright 2013 Chris Johns (chr...@rtems.org)
+# Copyright 2013-2016 Chris Johns (chr...@rtems.org)
+# Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
 # All rights reserved.
 #
 # This file is part of the RTEMS Tools package in 'rtems-tools'.
 #
-# Permission to use, copy, modify, and/or distribute this software for any
-# purpose with or without fee is hereby granted, provided that the above
-# copyright notice and this permission notice appear in all copies.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
 #
-# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 #
 # Manage emailing results or reports.
@@ -28,18 +40,72 @@ import smtplib
 import socket
 
 import error
+import execute
 import options
 import path
 
+_options = {
+'--mail' : 'Send email report or results.',
+'--use-gitconfig': 'Use mail configuration from git config.',
+'--mail-to'  : 'Email address to send the email to.',
+'--mail-from': 'Email address the report is from.',
+'--smtp-host': 'SMTP host to send via.',
+'--smtp-port': 'SMTP port to send via.',
+'--smtp-user': 'User for SMTP authentication.',
+'--smtp-password': 'Password for SMTP authentication.'
+}
+
 def append_options(opts):
-opts['--mail'] = 'Send email report or results.'
-opts['--smtp-host'] = 'SMTP host to send via.'
-opts['--mail-to'] = 'Email address to send the email too.'
-opts['--mail-from'] = 'Email address the report is from.'
+for o in _options:
+opts[o] = _options[o]
+
+def add_arguments(argsp):
+argsp.add_argument('--mail', help = _options['--mail'], action = 
'store_true')
+argsp.add_argument('--use-gitconfig', help = _options['--use-gitconfig'], 
action = 'store_true')
+no_add = ['--mail', '--use-gitconfig']
+for o in [opt for opt in list(_options) if opt not in no_add]:
+argsp.add_argument(o, help = _options[o], type = str)
 
 class mail:
 def __init__(self, opts):
 self.opts = opts
+self.gitconfig_lines = None
+if opts.find_arg('--use-gitconfig') is not None:
+# Read the output of `git config --list` instead of reading the
+# .gitconfig file directly because Python 2 ConfigParser does not
+# accept tabs at the beginning of lines.
+e = execute.capture_execution()
+exit_code, proc, output = e.open('git config --list', shell=True)
+if exit_code == 0:
+self.gitconfig_lines = output.split(os.linesep)
+
+def _args_are_macros(self):
+return isinstance(self.opts, options.command_line)
+
+def _get_arg(self, arg):
+if self._args_are_macros():
+value = self.opts.find_arg(arg)
+if 

[PATCH rtems-tools 5 5/5] rtems-bsp-builder: Fix mail support

[Alex White]

This fixes a problem with mailer options support that occurred because
check.py uses argparse.ArgumentParser instead of tester.rt.options.

Closes #4553
---
 rtemstoolkit/mailer.py |  5 +++--
 tester/rt/check.py | 17 -
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/rtemstoolkit/mailer.py b/rtemstoolkit/mailer.py
index ae51d78..09e4a26 100644
--- a/rtemstoolkit/mailer.py
+++ b/rtemstoolkit/mailer.py
@@ -61,14 +61,15 @@ def append_options(opts):
 def add_arguments(argsp):
 argsp.add_argument('--mail', help = _options['--mail'], action = 
'store_true')
 argsp.add_argument('--use-gitconfig', help = _options['--use-gitconfig'], 
action = 'store_true')
-for o in list(_options)[1:]:
+no_add = ['--mail', '--use-gitconfig']
+for o in [opt for opt in list(_options) if opt not in no_add]:
 argsp.add_argument(o, help = _options[o], type = str)
 
 class mail:
 def __init__(self, opts):
 self.opts = opts
 self.gitconfig_lines = None
-if opts.find_arg('--use-gitconfig') is not None:
+if self._get_arg('--use-gitconfig'):
 # Read the output of `git config --list` instead of reading the
 # .gitconfig file directly because Python 2 ConfigParser does not
 # accept tabs at the beginning of lines.
diff --git a/tester/rt/check.py b/tester/rt/check.py
index 2a38d99..deac19d 100755
--- a/tester/rt/check.py
+++ b/tester/rt/check.py
@@ -105,7 +105,22 @@ def title():
 return 'RTEMS Tools Project - RTEMS Kernel BSP Builder, %s' % 
(version.string())
 
 def command_line():
-return wrap(('command: ', ' '.join(sys.argv)), lineend = '\\')
+# Filter potentially sensitive mail options out.
+filtered_args = [
+arg for arg in sys.argv
+if all(
+smtp_opt not in arg
+for smtp_opt in [
+'--smtp-host',
+'--mail-to',
+'--mail-from',
+'--smtp-user',
+'--smtp-password',
+'--smtp-port'
+]
+)
+]
+return wrap(('command: ', ' '.join(filtered_args)), lineend = '\\')
 
 def jobs_option_parse(jobs_option):
 try:
-- 
2.27.0

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[PATCH rtems-tools 5 4/5] rtemstoolkit/mailer.py: Add --use-gitconfig option

[Alex White]

This adds the option to pull mail-related configuration values from the
user's git configuration.

Updates #4553
---
 rtemstoolkit/mailer.py | 46 --
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/rtemstoolkit/mailer.py b/rtemstoolkit/mailer.py
index aa804ae..ae51d78 100644
--- a/rtemstoolkit/mailer.py
+++ b/rtemstoolkit/mailer.py
@@ -39,11 +39,13 @@ import smtplib
 import socket
 
 from rtemstoolkit import error
+from rtemstoolkit import execute
 from rtemstoolkit import options
 from rtemstoolkit import path
 
 _options = {
 '--mail' : 'Send email report or results.',
+'--use-gitconfig': 'Use mail configuration from git config.',
 '--mail-to'  : 'Email address to send the email to.',
 '--mail-from': 'Email address the report is from.',
 '--smtp-host': 'SMTP host to send via.',
@@ -58,12 +60,22 @@ def append_options(opts):
 
 def add_arguments(argsp):
 argsp.add_argument('--mail', help = _options['--mail'], action = 
'store_true')
+argsp.add_argument('--use-gitconfig', help = _options['--use-gitconfig'], 
action = 'store_true')
 for o in list(_options)[1:]:
 argsp.add_argument(o, help = _options[o], type = str)
 
 class mail:
 def __init__(self, opts):
 self.opts = opts
+self.gitconfig_lines = None
+if opts.find_arg('--use-gitconfig') is not None:
+# Read the output of `git config --list` instead of reading the
+# .gitconfig file directly because Python 2 ConfigParser does not
+# accept tabs at the beginning of lines.
+e = execute.capture_execution()
+exit_code, proc, output = e.open('git config --list', shell=True)
+if exit_code == 0:
+self.gitconfig_lines = output.split(os.linesep)
 
 def _args_are_macros(self):
 return isinstance(self.opts, options.command_line)
@@ -83,6 +95,16 @@ class mail:
 value = None
 return value
 
+def _get_from_gitconfig(self, variable_name):
+if self.gitconfig_lines is None:
+return None
+
+for line in self.gitconfig_lines:
+if line.startswith(variable_name):
+ls = line.split('=')
+if len(ls) >= 2:
+return ls[1]
+
 def from_address(self):
 
 def _clean(l):
@@ -97,6 +119,12 @@ class mail:
 addr = self._get_arg('--mail-from')
 if addr is not None:
 return addr
+addr = self._get_from_gitconfig('user.email')
+if addr is not None:
+name = self._get_from_gitconfig('user.name')
+if name is not None:
+addr = '%s <%s>' % (name, addr)
+return addr
 mailrc = None
 if 'MAILRC' in os.environ:
 mailrc = os.environ['MAILRC']
@@ -125,6 +153,9 @@ class mail:
 
 def smtp_host(self):
 host = self._get_arg('--smtp-host')
+if host is not None:
+return host
+host = self._get_from_gitconfig('sendemail.smtpserver')
 if host is not None:
 return host
 if self._args_are_macros():
@@ -135,6 +166,9 @@ class mail:
 
 def smtp_port(self):
 port = self._get_arg('--smtp-port')
+if port is not None:
+return port
+port = self._get_from_gitconfig('sendemail.smtpserverport')
 if port is not None:
 return port
 if self._args_are_macros():
@@ -142,10 +176,18 @@ class mail:
 return port
 
 def smtp_user(self):
-return self._get_arg('--smtp-user')
+user = self._get_arg('--smtp-user')
+if user is not None:
+return user
+user = self._get_from_gitconfig('sendemail.smtpuser')
+return user
 
 def smtp_password(self):
-return self._get_arg('--smtp-password')
+password = self._get_arg('--smtp-password')
+if password is not None:
+return password
+password = self._get_from_gitconfig('sendemail.smtppass')
+return password
 
 def send(self, to_addr, subject, body):
 from_addr = self.from_address()
-- 
2.27.0

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[PATCH rtems-tools 5 0/5] Port mailer.py fixes to rtems-tools 5 branch

[Alex White]

Hi,

This patch set adds the changes related to report mailing to rtems-tools 5.

See #4553

Thanks,

Alex White

Alex White (5):
  rtemstoolkit/mailer.py: Return full smtp-host arg value
  rtemstoolkit: Filter mail options from log output
  rtemstoolkit/mailer.py: Add SMTP login options
  rtemstoolkit/mailer.py: Add --use-gitconfig option
  rtems-bsp-builder: Fix mail support

 rtemstoolkit/mailer.py  | 86 +
 rtemstoolkit/options.py | 17 +++-
 tester/rt/check.py  | 17 +++-
 3 files changed, 111 insertions(+), 9 deletions(-)

-- 
2.27.0

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[PATCH rtems-tools 5 3/5] rtemstoolkit/mailer.py: Add SMTP login options

[Alex White]

This adds more options so that the user can authenticate with the SMTP
server.

Updates #4553
---
 rtemstoolkit/mailer.py | 41 +++--
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/rtemstoolkit/mailer.py b/rtemstoolkit/mailer.py
index 3ea9d98..aa804ae 100644
--- a/rtemstoolkit/mailer.py
+++ b/rtemstoolkit/mailer.py
@@ -43,10 +43,13 @@ from rtemstoolkit import options
 from rtemstoolkit import path
 
 _options = {
-'--mail' : 'Send email report or results.',
-'--smtp-host': 'SMTP host to send via.',
-'--mail-to'  : 'Email address to send the email too.',
-'--mail-from': 'Email address the report is from.'
+'--mail' : 'Send email report or results.',
+'--mail-to'  : 'Email address to send the email to.',
+'--mail-from': 'Email address the report is from.',
+'--smtp-host': 'SMTP host to send via.',
+'--smtp-port': 'SMTP port to send via.',
+'--smtp-user': 'User for SMTP authentication.',
+'--smtp-password': 'Password for SMTP authentication.'
 }
 
 def append_options(opts):
@@ -55,7 +58,7 @@ def append_options(opts):
 
 def add_arguments(argsp):
 argsp.add_argument('--mail', help = _options['--mail'], action = 
'store_true')
-for o in ['--smtp-host', '--mail-to', '--mail-from']:
+for o in list(_options)[1:]:
 argsp.add_argument(o, help = _options[o], type = str)
 
 class mail:
@@ -130,12 +133,38 @@ class mail:
 return host
 return 'localhost'
 
+def smtp_port(self):
+port = self._get_arg('--smtp-port')
+if port is not None:
+return port
+if self._args_are_macros():
+port = self.opts.defaults.get_value('%{_mail_smtp_port}')
+return port
+
+def smtp_user(self):
+return self._get_arg('--smtp-user')
+
+def smtp_password(self):
+return self._get_arg('--smtp-password')
+
 def send(self, to_addr, subject, body):
 from_addr = self.from_address()
 msg = "From: %s\r\nTo: %s\r\nSubject: %s\r\n\r\n" % \
 (from_addr, to_addr, subject) + body
+port = self.smtp_port()
+
 try:
-s = smtplib.SMTP(self.smtp_host())
+s = smtplib.SMTP(self.smtp_host(), port, timeout=10)
+
+password = self.smtp_password()
+# If a password is provided, assume that authentication is 
required.
+if password is not None:
+user = self.smtp_user()
+if user is None:
+user = from_addr
+s.starttls()
+s.login(user, password)
+
 s.sendmail(from_addr, [to_addr], msg)
 except smtplib.SMTPException as se:
 raise error.general('sending mail: %s' % (str(se)))
-- 
2.27.0

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[PATCH rtems-tools 5 2/5] rtemstoolkit: Filter mail options from log output

[Alex White]

This filters mail-related options out before logging the command line
options. This is needed to prevent leaking potentially sensitive
information via logs and emails.

Updates #4553
---
 rtemstoolkit/options.py | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/rtemstoolkit/options.py b/rtemstoolkit/options.py
index 32a7016..5ebe3bc 100644
--- a/rtemstoolkit/options.py
+++ b/rtemstoolkit/options.py
@@ -508,7 +508,22 @@ class command_line(object):
 return None
 
 def log_info(self):
-log.output(log.info(self.argv))
+# Filter potentially sensitive mail options out.
+filtered_args = [
+arg for arg in self.argv
+if all(
+smtp_opt not in arg
+for smtp_opt in [
+'--smtp-host',
+'--mail-to',
+'--mail-from',
+'--smtp-user',
+'--smtp-password',
+'--smtp-port'
+]
+)
+]
+log.output(log.info(filtered_args))
 
 def load(opts):
 """
-- 
2.27.0

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[PATCH rtems-tools 5 1/5] rtemstoolkit/mailer.py: Return full smtp-host arg value

[Alex White]

This fixes mail.smtp_host() so that it returns the full argument value
rather than just the second character.

Updates #4553
---
 rtemstoolkit/mailer.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtemstoolkit/mailer.py b/rtemstoolkit/mailer.py
index f8f813c..3ea9d98 100644
--- a/rtemstoolkit/mailer.py
+++ b/rtemstoolkit/mailer.py
@@ -123,7 +123,7 @@ class mail:
 def smtp_host(self):
 host = self._get_arg('--smtp-host')
 if host is not None:
-return host[1]
+return host
 if self._args_are_macros():
 host = self.opts.defaults.get_value('%{_mail_smtp_host}')
 if host is not None:
-- 
2.27.0

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[PATCH rtems-tools] rtems-bsp-builder: Fix mail support

[Alex White]

This fixes a problem with mailer options support that occurred because
check.py uses argparse.ArgumentParser instead of tester.rt.options.
---
 rtemstoolkit/mailer.py |  2 +-
 tester/rt/check.py | 17 -
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/rtemstoolkit/mailer.py b/rtemstoolkit/mailer.py
index 085a2ce..32cbc23 100644
--- a/rtemstoolkit/mailer.py
+++ b/rtemstoolkit/mailer.py
@@ -70,7 +70,7 @@ class mail:
 def __init__(self, opts):
 self.opts = opts
 self.gitconfig_lines = None
-if opts.find_arg('--use-gitconfig') is not None:
+if self._get_arg('--use-gitconfig'):
 # Read the output of `git config --list` instead of reading the
 # .gitconfig file directly because Python 2 ConfigParser does not
 # accept tabs at the beginning of lines.
diff --git a/tester/rt/check.py b/tester/rt/check.py
index c01c25d..ec92e7e 100755
--- a/tester/rt/check.py
+++ b/tester/rt/check.py
@@ -105,7 +105,22 @@ def title():
 return 'RTEMS Tools Project - RTEMS Kernel BSP Builder, %s' % 
(version.string())
 
 def command_line():
-return wrap(('command: ', ' '.join(sys.argv)), lineend = '\\')
+# Filter potentially sensitive mail options out.
+filtered_args = [
+arg for arg in sys.argv
+if all(
+smtp_opt not in arg
+for smtp_opt in [
+'--smtp-host',
+'--mail-to',
+'--mail-from',
+'--smtp-user',
+'--smtp-password',
+'--smtp-port'
+]
+)
+]
+return wrap(('command: ', ' '.join(filtered_args)), lineend = '\\')
 
 def jobs_option_parse(jobs_option):
 try:
-- 
2.27.0

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[PATCH RSB] Update to dtc 1.6.1

[Alex White]

This bumps the dtc version from 1.6.0 to 1.6.1. Building 1.6.0 on
FreeBSD 13 was unsuccessful, but 1.6.1 appears to build fine.
---
 bare/config/devel/dtc-1.6.1-1.cfg  | 18 ++
 bare/config/devel/dtc.bset |  2 +-
 bare/config/devel/qemu-couverture.bset |  2 +-
 rtems/config/6/rtems-microblaze.bset   |  2 +-
 rtems/config/6/rtems-moxie.bset|  2 +-
 rtems/config/7/rtems-moxie.bset|  2 +-
 6 files changed, 23 insertions(+), 5 deletions(-)
 create mode 100644 bare/config/devel/dtc-1.6.1-1.cfg

diff --git a/bare/config/devel/dtc-1.6.1-1.cfg 
b/bare/config/devel/dtc-1.6.1-1.cfg
new file mode 100644
index 000..54aed09
--- /dev/null
+++ b/bare/config/devel/dtc-1.6.1-1.cfg
@@ -0,0 +1,18 @@
+#
+# DTC (Device Tree Compiler) 1.6.1
+#
+
+%if %{release} == %{nil}
+%define release 1
+%endif
+
+%include %{_configdir}/base.cfg
+
+%define dtc_version 1.6.1
+
+%hash sha256 dtc-%{dtc_version}.tar.gz 
38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
+
+#
+# The DTC build instructions. We use 1.x.x Release 1.
+#
+%include %{_configdir}/dtc-1-1.cfg
diff --git a/bare/config/devel/dtc.bset b/bare/config/devel/dtc.bset
index 54521f6..56fb61e 100644
--- a/bare/config/devel/dtc.bset
+++ b/bare/config/devel/dtc.bset
@@ -4,4 +4,4 @@
 
 %define release 1
 
-devel/dtc-1.4.1-1
+devel/dtc-1.6.1-1
diff --git a/bare/config/devel/qemu-couverture.bset 
b/bare/config/devel/qemu-couverture.bset
index fd5547c..60bec8e 100644
--- a/bare/config/devel/qemu-couverture.bset
+++ b/bare/config/devel/qemu-couverture.bset
@@ -22,5 +22,5 @@ devel/gettext-0.18.3.1-1
 devel/libffi-3.0.13-1
 devel/pixman-0.32.4-1
 devel/glib-2.48.2-1
-devel/dtc-1.6.0-1
+devel/dtc-1.6.1-1
 devel/qemu-couverture-git-1
diff --git a/rtems/config/6/rtems-microblaze.bset 
b/rtems/config/6/rtems-microblaze.bset
index 3eb7a89..050a217 100644
--- a/rtems/config/6/rtems-microblaze.bset
+++ b/rtems/config/6/rtems-microblaze.bset
@@ -6,7 +6,7 @@
 #
 %include 6/rtems-base.bset
 
-devel/dtc-1.6.0-1
+devel/dtc-1.6.1-1
 
 #
 # Build gdb first to raise the Python install error as early as possible.
diff --git a/rtems/config/6/rtems-moxie.bset b/rtems/config/6/rtems-moxie.bset
index a191c5d..0771def 100644
--- a/rtems/config/6/rtems-moxie.bset
+++ b/rtems/config/6/rtems-moxie.bset
@@ -2,5 +2,5 @@
 %define rtems_arch moxie
 %define win32-gdb-disable-sim
 %define with_libgomp
-devel/dtc-1.6.0-1
+devel/dtc-1.6.1-1
 %include 6/rtems-default.bset
diff --git a/rtems/config/7/rtems-moxie.bset b/rtems/config/7/rtems-moxie.bset
index 60fe7f4..5aecffa 100644
--- a/rtems/config/7/rtems-moxie.bset
+++ b/rtems/config/7/rtems-moxie.bset
@@ -2,5 +2,5 @@
 %define rtems_arch moxie
 %define win32-gdb-disable-sim
 %define with_libgomp
-devel/dtc-1.6.0-1
+devel/dtc-1.6.1-1
 %include 7/rtems-default.bset
-- 
2.27.0

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[PATCH RSB] microblaze: Fix FreeBSD 13 build

[Alex White]

This bumps the dtc version included in the MicroBlaze toolchain from
1.6.0 to 1.6.1. Building 1.6.0 on FreeBSD 13 was unsuccessful, but 1.6.1
appears to build fine.
---
 bare/config/devel/dtc-1.6.1-1.cfg| 18 ++
 rtems/config/6/rtems-microblaze.bset |  2 +-
 2 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 bare/config/devel/dtc-1.6.1-1.cfg

diff --git a/bare/config/devel/dtc-1.6.1-1.cfg 
b/bare/config/devel/dtc-1.6.1-1.cfg
new file mode 100644
index 000..54aed09
--- /dev/null
+++ b/bare/config/devel/dtc-1.6.1-1.cfg
@@ -0,0 +1,18 @@
+#
+# DTC (Device Tree Compiler) 1.6.1
+#
+
+%if %{release} == %{nil}
+%define release 1
+%endif
+
+%include %{_configdir}/base.cfg
+
+%define dtc_version 1.6.1
+
+%hash sha256 dtc-%{dtc_version}.tar.gz 
38a6257f2c23cb9dfa1781ac4ad122d8358e1a22d33b2da0eb492c190644a376
+
+#
+# The DTC build instructions. We use 1.x.x Release 1.
+#
+%include %{_configdir}/dtc-1-1.cfg
diff --git a/rtems/config/6/rtems-microblaze.bset 
b/rtems/config/6/rtems-microblaze.bset
index 3eb7a89..050a217 100644
--- a/rtems/config/6/rtems-microblaze.bset
+++ b/rtems/config/6/rtems-microblaze.bset
@@ -6,7 +6,7 @@
 #
 %include 6/rtems-base.bset
 
-devel/dtc-1.6.0-1
+devel/dtc-1.6.1-1
 
 #
 # Build gdb first to raise the Python install error as early as possible.
-- 
2.27.0

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[PATCH] bsps/microblaze: Fix uart interrupt conditional code

[Alex White]

This includes bspopts.h so that the #define is not lost. This also adds
a macro that was missing when console interrupts were enabled.
---
 bsps/microblaze/include/dev/serial/uartlite.h |  1 +
 .../include/dev/serial/uartlite_l.h   | 20 +++
 2 files changed, 21 insertions(+)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 6e288d4dc7..c77b3286a6 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -38,6 +38,7 @@
 
 #include 
 
+#include 
 #include 
 
 #ifdef __cplusplus
diff --git a/bsps/microblaze/include/dev/serial/uartlite_l.h 
b/bsps/microblaze/include/dev/serial/uartlite_l.h
index 8c0598e191..96271d73ca 100644
--- a/bsps/microblaze/include/dev/serial/uartlite_l.h
+++ b/bsps/microblaze/include/dev/serial/uartlite_l.h
@@ -253,6 +253,26 @@ static inline void Xil_Out32(UINTPTR Addr, u32 Value)
  XUL_SR_TX_FIFO_FULL)
 
 
+#ifdef __rtems__
+//
+/**
+*
+* Check to see if the transmitter is empty.
+*
+* @param   BaseAddress is the  base address of the device
+*
+* @return  TRUE if the transmitter is empty, FALSE otherwise.
+*
+* @noteC-style Signature:
+*  int XUartLite_IsTransmitEmpty(u32 BaseAddress);
+*
+*/
+#define XUartLite_IsTransmitEmpty(BaseAddress) \
+   ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_EMPTY) == \
+ XUL_SR_TX_FIFO_EMPTY)
+#endif
+
+
 //
 /**
 *
-- 
2.27.0

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[PATCH RSB] rtems-tools-6.cfg: Bump hash to include MicroBlaze

[Alex White]

Hash: 323007a6b520140a20b2e268c90b78ff67afaf45
---
 rtems/config/tools/rtems-tools-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-tools-6.cfg 
b/rtems/config/tools/rtems-tools-6.cfg
index cfb..4158753 100644
--- a/rtems/config/tools/rtems-tools-6.cfg
+++ b/rtems/config/tools/rtems-tools-6.cfg
@@ -10,14 +10,14 @@
  %define rtems_tools_source rtems-tools-%{rtems_tools_version}
  %define rtems_tools_ext xz
 %else
- %define rtems_tools_version 40a7058bd4d7681ca6be7a14f09a1275ea4fbde4
+ %define rtems_tools_version 323007a6b520140a20b2e268c90b78ff67afaf45
  %define rtems_tools_ext bz2
 %endif
 
 %define rtems_tools_source rtems-tools-%{rtems_tools_version}
 %source set rtems-tools 
https://git.rtems.org/rtems-tools/snapshot/%{rtems_tools_source}.tar.%{rtems_tools_ext}
 %hash   sha512 rtems-tools-%{rtems_tools_version}.tar.bz2 \
- 
nlwNKLP2UXRMRfK0SU0Bpd+9sOvRoRaXRRTj0lzx9jkqGMwwU4lB19uLhTnH88u1jGOrhVSkNunIHvbi9SayAg==
+ 
yo5i1HEaYyOOX8JJGr+kok0vIEZGpXjeZmA44gqTow101PhtlwhebvgTS0SeMe8L68wTDqdjZe5QVnsjKgYOhw==
 
 #
 # Optionally enable/disable building the RTEMS Tools via the command line.
-- 
2.32.0

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Re:

[Alex White]

Hi,

Ignore this. It looks like my ".patch" file was malformed somehow. I will see 
if I can fix it and resend.

Alex

From: devel  on behalf of Alex White 

Sent: Monday, October 18, 2021 10:01 AM
To: devel@rtems.org 
Subject:

>From c47d01739f2abf79a1423ea3cdcc7e98c621b222 Mon Sep 17 00:00:00 2001
From: Alex White 
Date: Thu, 14 Oct 2021 01:44:08 -0500
Subject: [PATCH RSB] rtems-tools-6.cfg: Bump hash to include MicroBlaze

Hash: 323007a6b520140a20b2e268c90b78ff67afaf45
---
 rtems/config/tools/rtems-tools-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-tools-6.cfg 
b/rtems/config/tools/rtems-tools-6.cfg
index cfb..4158753 100644
--- a/rtems/config/tools/rtems-tools-6.cfg
+++ b/rtems/config/tools/rtems-tools-6.cfg
@@ -10,14 +10,14 @@
  %define rtems_tools_source rtems-tools-%{rtems_tools_version}
  %define rtems_tools_ext xz
 %else
- %define rtems_tools_version 40a7058bd4d7681ca6be7a14f09a1275ea4fbde4
+ %define rtems_tools_version 323007a6b520140a20b2e268c90b78ff67afaf45
  %define rtems_tools_ext bz2
 %endif

 %define rtems_tools_source rtems-tools-%{rtems_tools_version}
 %source set rtems-tools 
https://git.rtems.org/rtems-tools/snapshot/%{rtems_tools_source}.tar.%{rtems_tools_ext}
 %hash   sha512 rtems-tools-%{rtems_tools_version}.tar.bz2 \
- 
nlwNKLP2UXRMRfK0SU0Bpd+9sOvRoRaXRRTj0lzx9jkqGMwwU4lB19uLhTnH88u1jGOrhVSkNunIHvbi9SayAg==
+ 
yo5i1HEaYyOOX8JJGr+kok0vIEZGpXjeZmA44gqTow101PhtlwhebvgTS0SeMe8L68wTDqdjZe5QVnsjKgYOhw==

 #
 # Optionally enable/disable building the RTEMS Tools via the command line.
--
2.32.0

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[no subject]

[Alex White]

>From c47d01739f2abf79a1423ea3cdcc7e98c621b222 Mon Sep 17 00:00:00 2001
From: Alex White 
Date: Thu, 14 Oct 2021 01:44:08 -0500
Subject: [PATCH RSB] rtems-tools-6.cfg: Bump hash to include MicroBlaze

Hash: 323007a6b520140a20b2e268c90b78ff67afaf45
---
 rtems/config/tools/rtems-tools-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-tools-6.cfg 
b/rtems/config/tools/rtems-tools-6.cfg
index cfb..4158753 100644
--- a/rtems/config/tools/rtems-tools-6.cfg
+++ b/rtems/config/tools/rtems-tools-6.cfg
@@ -10,14 +10,14 @@
  %define rtems_tools_source rtems-tools-%{rtems_tools_version}
  %define rtems_tools_ext xz
 %else
- %define rtems_tools_version 40a7058bd4d7681ca6be7a14f09a1275ea4fbde4
+ %define rtems_tools_version 323007a6b520140a20b2e268c90b78ff67afaf45
  %define rtems_tools_ext bz2
 %endif
 
 %define rtems_tools_source rtems-tools-%{rtems_tools_version}
 %source set rtems-tools 
https://git.rtems.org/rtems-tools/snapshot/%{rtems_tools_source}.tar.%{rtems_tools_ext}
 %hash   sha512 rtems-tools-%{rtems_tools_version}.tar.bz2 \
- 
nlwNKLP2UXRMRfK0SU0Bpd+9sOvRoRaXRRTj0lzx9jkqGMwwU4lB19uLhTnH88u1jGOrhVSkNunIHvbi9SayAg==
+ 
yo5i1HEaYyOOX8JJGr+kok0vIEZGpXjeZmA44gqTow101PhtlwhebvgTS0SeMe8L68wTDqdjZe5QVnsjKgYOhw==
 
 #
 # Optionally enable/disable building the RTEMS Tools via the command line.
-- 
2.32.0

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[PATCH v2 2/3] bsps: Add MicroBlaze FPGA BSP

[Alex White]

From: Hesham ALMatary 

---
 .../microblaze_fpga/console/console-io.c  |  74 +
 .../microblaze/microblaze_fpga/include/bsp.h  |  48 ++
 .../microblaze/microblaze_fpga/include/tm27.h |  48 ++
 .../microblaze/microblaze_fpga/start/start.S  | 109 +
 .../startup/_exception_handler.S  |  38 +
 .../startup/_interrupt_handler.S  |  38 +
 .../microblaze_fpga/startup/sim-crtinit.S |  86 +++
 .../shared/include/linker-symbols.h   | 104 +
 cpukit/score/cpu/microblaze/cpu.c |  47 +-
 .../microblaze/microblaze-context-switch.S|  89 +++
 cpukit/score/cpu/microblaze/rtems/asm.h   |   2 +-
 cpukit/score/cpu/microblaze/rtems/score/cpu.h | 145 ++
 .../cpu/microblaze/rtems/score/microblaze.h   |  35 -
 13 files changed, 784 insertions(+), 79 deletions(-)
 create mode 100644 
c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h
 create mode 100644 c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S
 create mode 100644 
c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S
 create mode 100644 
c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S
 create mode 100644 
c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S
 create mode 100644 c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h
 create mode 100644 cpukit/score/cpu/microblaze/microblaze-context-switch.S

diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c 
b/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
new file mode 100644
index 00..47592967ac
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * @ingroup microblaze_uart
+ *
+ * @brief Console Configuration.
+ */
+
+/*
+ *  Copyright (C) 2015 Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+console_tbl Console_Configuration_Ports [] = {
+{
+  .sDeviceName = "/dev/ttyS0",
+  .deviceType = SERIAL_CUSTOM,
+  .pDeviceFns = _uart_fns,
+  .deviceProbe = NULL,
+  .pDeviceFlow = NULL,
+  .ulCtrlPort1 = UART_BASEADDRESS,
+  .ulCtrlPort2 = 0,
+  .ulClock = 9600,
+  .ulIntVector = 0
+}
+};
+
+#define PORT_COUNT \
+  (sizeof(Console_Configuration_Ports) \
+/ sizeof(Console_Configuration_Ports [0]))
+
+unsigned long Console_Configuration_Count = PORT_COUNT;
+
+static void output_char(char c)
+{
+  const console_fns *con =
+Console_Configuration_Ports [Console_Port_Minor].pDeviceFns;
+
+  if (c == '\n') {
+con->deviceWritePolled((int) Console_Port_Minor, '\r');
+  }
+  con->deviceWritePolled((int) Console_Port_Minor, c);
+}
+
+BSP_output_char_function_type BSP_output_char = output_char;
+
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h 
b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
new file mode 100644
index 00..cb72835571
--- /dev/null
+++ b/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h
@@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2015 Hesham Almatary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ *