[PATCH rtems-lwip v4 7/7] stm32: Convert to Unix line endings
This patch converts all files imported from ST to Unix line endings
using dos2unix.
---
rtemslwip/stm32f4/lwipopts.h | 294 ++---
stm32/driver/dp83848.c | 1328 +++
stm32/driver/dp83848.h | 872 +++
stm32/ethernetif.c | 1972 +-
stm32/ethernetif.h | 108 +-
5 files changed, 2287 insertions(+), 2287 deletions(-)
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
index aa6b95b..eec98c7 100644
--- a/rtemslwip/stm32f4/lwipopts.h
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -1,147 +1,147 @@
-/* USER CODE BEGIN Header */
-/**
-
**
- * File Name : Target/lwipopts.h
- * Description: This file overrides LwIP stack default configuration
- * done in opt.h file.
-
**
- * @attention
- *
- * Copyright (c) 2022 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
-
**
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion
--*/
-#ifndef __LWIPOPTS__H__
-#define __LWIPOPTS__H__
-
-/*-*/
-/* Current version of LwIP supported by CubeMx: 2.1.2 -*/
-/*-*/
-
-/* Within 'USER CODE' section, code will be kept by default at each generation
*/
-/* USER CODE BEGIN 0 */
-#include
-/* USER CODE END 0 */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
-/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
-/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
-#define WITH_RTOS 1
-/*- CHECKSUM_BY_HARDWARE disabled -*/
-#define CHECKSUM_BY_HARDWARE 0
-/*-*/
-
-/* LwIP Stack Parameters (modified compared to initialization value in opt.h)
-*/
-/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
-/*- Default value in ETH configuration GUI in CubeMx: 1524 -*/
-#define ETH_RX_BUFFER_SIZE 1536
-/*- Value in opt.h for NO_SYS: 0 -*/
-#define NO_SYS 0
-/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
-#define SYS_LIGHTWEIGHT_PROT 1
-/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
-#define MEM_ALIGNMENT 4
-/*- Default Value for H7 devices: 0x30044000 -*/
-//#define LWIP_RAM_HEAP_POINTER 0x20017f58
-/*- Value supported for H7 devices: 1 -*/
-#define LWIP_SUPPORT_CUSTOM_PBUF 1
-/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
-#define LWIP_ETHERNET 1
-/*- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID |
LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
-#define LWIP_DNS_SECURE 7
-/*- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS -
1))/TCP_MSS -*/
-#define TCP_SND_QUEUELEN 9
-/*- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2),
(2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
-#define TCP_SNDLOWAT 1071
-/*- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5)
-*/
-#define TCP_SNDQUEUELOWAT 5
-/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
-#define TCP_WND_UPDATE_THRESHOLD 536
-/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
-//#define LWIP_NETIF_LINK_CALLBACK 0
-/*- Value in opt.h for LWIP_NETCONN: 1 -*/
-#define LWIP_NETCONN 1
-/*- Value in opt.h for LWIP_SOCKET: 1 -*/
-#define LWIP_SOCKET 1
-/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
-//#define RECV_BUFSIZE_DEFAULT 20
-/*- Value in opt.h for LWIP_STATS: 1 -*/
-#define LWIP_STATS 0
-/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
-#define CHECKSUM_GEN_IP 0
-/*- Value in opt.h for CHECKSUM_GEN_UDP: 1 -*/
-#define CHECKSUM_GEN_UDP 0
-/*- Value in opt.h for CHECKSUM_GEN_TCP: 1 -*/
-#define CHECKSUM_GEN_TCP 0
-/*- Value in opt.h for CHECKSUM_GEN_ICMP: 1 -*/
-#define CHECKSUM_GEN_ICMP 0
-/*- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -*/
-#define CHECKSUM_GEN_ICMP6 0
-/*- Value in opt.h for CHECKSUM_CHECK_IP: 1 -*/
-#define CHECKSUM_CHECK_IP 0
-/*- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -*/
-#define CHECKSUM_CHECK_UDP 0
-/*- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -*/
-#define CHECKSUM_CHECK_TCP 0
-/*- Value in opt.h for CHECKSUM_CHECK_ICMP: 1 -*/
[PATCH rtems-lwip v4 6/7] lwip.py: Add STM32 lwIP port to build
---
lwip.py | 21 +
1 file changed, 21 insertions(+)
diff --git a/lwip.py b/lwip.py
index 2d93d3e..63e1f1d 100644
--- a/lwip.py
+++ b/lwip.py
@@ -92,6 +92,20 @@ common_source_files = [
'rtemslwip/bsd_compat/rtems-kernel-program.c'
]
+stm32_drv_incl = [
+'stm32',
+'stm32/driver'
+]
+
+stm32_drv_src = [
+'stm32/ethernetif.c',
+'stm32/driver/dp83848.c'
+]
+
+stm32_stm32f4_drv_incl = [
+'rtemslwip/stm32f4'
+]
+
def build(bld):
source_files = []
@@ -127,6 +141,13 @@ def build(bld):
drv_incl.append('cpsw/src/include')
driver_source.extend(walk_sources('cpsw/src'))
+# These files will only compile for STM32F4 BSPs
+if bsp == 'stm32f4':
+driver_source.extend(walk_sources('rtemslwip/stm32f4'))
+drv_incl.extend(stm32_drv_incl)
+driver_source.extend(stm32_drv_src)
+drv_incl.extend(stm32_stm32f4_drv_incl)
+
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
--
2.37.2
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[PATCH rtems-lwip v4 3/7] Add STM32 Ethernet source
This patch adds ST's Ethernet and lwIP port and DP83848 driver. The
files are generated using STM32CubeIDE with STM32F4 Cube FW v1.27.1,
under RTOS mode.
---
COPYING.stm32 | 28 ++
ORIGIN.stm32 | 2 +
stm32/driver/dp83848.c | 664 +++
stm32/driver/dp83848.h | 436
stm32/ethernetif.c | 879 +
stm32/ethernetif.h | 47 +++
6 files changed, 2056 insertions(+)
create mode 100644 COPYING.stm32
create mode 100644 ORIGIN.stm32
create mode 100644 stm32/driver/dp83848.c
create mode 100644 stm32/driver/dp83848.h
create mode 100644 stm32/ethernetif.c
create mode 100644 stm32/ethernetif.h
diff --git a/COPYING.stm32 b/COPYING.stm32
new file mode 100644
index 000..f42052b
--- /dev/null
+++ b/COPYING.stm32
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *this list of conditions and the following disclaimer in the documentation
+ *and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+
diff --git a/ORIGIN.stm32 b/ORIGIN.stm32
new file mode 100644
index 000..afc15ed
--- /dev/null
+++ b/ORIGIN.stm32
@@ -0,0 +1,2 @@
+The files under stm32/ directory are generated using STM32CubeIDE with
+STM32F4 Cube FW v1.27.1, under RTOS mode.
diff --git a/stm32/driver/dp83848.c b/stm32/driver/dp83848.c
new file mode 100644
index 000..2c5d59b
--- /dev/null
+++ b/stm32/driver/dp83848.c
@@ -0,0 +1,664 @@
+/**
+
**
+ * @filedp83848.c
+ * @author MCD Application Team
+ * @brief This file provides a set of functions needed to manage the DP83848
+ * PHY devices.
+
**
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *opensource.org/licenses/BSD-3-Clause
+ *
+
**
+ */
+
+/* Includes
--*/
+#include "dp83848.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @defgroup DP83848 DP83848
+ * @{
+ */
+
+/* Private typedef
---*/
+/* Private define
*/
+/** @defgroup DP83848_Private_Defines DP83848 Private Defines
+ * @{
+ */
+#define DP83848_SW_RESET_TO((uint32_t)500U)
+#define DP83848_INIT_TO((uint32_t)2000U)
+#define DP83848_MAX_DEV_ADDR ((uint32_t)31U)
+/**
+ * @}
+ */
+
+/* Private macro
-*/
+/* Private variables
-*/
+/* Private function prototypes
---*/
+/* Private functions
-*/
+/** @defgroup DP83848_Private_Functions DP83848 Private Functions
+ * @{
+ */
+
+/**
+ * @brief Register IO functions to component object
+ * @param pObj: device object of DP83848_Object_t.
+ * @param ioctx: holds device IO functions.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ERROR if missing mandatory function
+ */
+int32_t DP83848_RegisterBusIO(dp83848_Object_t *pObj, dp83848_IOCtx_t
[PATCH rtems-lwip v4 5/7] RTEMS port of lwIP for STM32 and STM32F4 BSP
---
rtemslwip/stm32f4/stm32f4_lwip.c | 39 +++
rtemslwip/stm32f4/stm32f4_lwip.h | 34 ++
stm32/ethernetif.c | 107 +++
stm32/ethernetif.h | 7 ++
4 files changed, 187 insertions(+)
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.c b/rtemslwip/stm32f4/stm32f4_lwip.c
new file mode 100644
index 000..4aee9fd
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "stm32f4_lwip.h"
+
+extern ETH_HandleTypeDef heth;
+
+__attribute__((weak)) void Error_Handler(void) {
+__disable_irq();
+while (1)
+{
+}
+}
+
+void ETH_IRQHandler(void) {
+HAL_ETH_IRQHandler();
+}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.h b/rtemslwip/stm32f4/stm32f4_lwip.h
new file mode 100644
index 000..50c3666
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H
+#define LIBLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H
+
+#include
+
+void ErrorHandler(void);
+void ETH_IRQHandler(void);
+
+#endif /* LIBLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H */
diff --git a/stm32/ethernetif.c b/stm32/ethernetif.c
index 02a85b4..ac023a0 100644
--- a/stm32/ethernetif.c
+++ b/stm32/ethernetif.c
@@ -19,7 +19,12 @@
/* USER CODE END Header */
/* Includes
--*/
+#ifndef __rtems__
#include "main.h"
+#else
+#include
+#include
+#endif /* __rtems__ */
#include "lwip/opt.h"
#include "lwip/timeouts.h"
#include "netif/ethernet.h"
@@ -28,7 +33,9 @@
#include "ethernetif.h"
#include "dp83848.h"
#include
+#ifndef __rtems__
#include "cmsis_os.h"
+#endif /* __rtems__ */
#include "lwip/tcpip.h"
/* Within 'USER CODE' section, code will be kept by default at each generation
*/
@@ -38,7 +45,12 @@
/* Private define
*/
/* The time to block waiting for input. */
+#ifndef __rtems__
#define TIME_WAITING_FOR_INPUT (
[PATCH rtems-lwip v4 4/7] rtemslwip: Add STM32F4 lwipopts.h and netstart.c
ault Value for ETHARP_DEBUG: LWIP_DBG_OFF ---*/
+/*-*/
+/* USER CODE BEGIN 1 */
+//#define LWIP_DEBUG 1
+#define LWIP_ARP 1
+
+#define LWIP_NETIF_API 1
+
+#define NO_SYS_NO_TIMERS 0
+
+#define IP_REASSEMBLY 0
+#define IP_FRAG 0
+#define LWIP_IPV4 1
+#define LWIP_IPV6 1
+
+#define LWIP_TCPIP_CORE_LOCKING 1
+#define TCPIP_THREAD_STACKSIZE 1024
+#define TCPIP_THREAD_PRIO 24
+#define TCPIP_MBOX_SIZE 6
+#define SLIPIF_THREAD_STACKSIZE 1024
+#define SLIPIF_THREAD_PRIO 3
+#define DEFAULT_THREAD_STACKSIZE 1024
+#define DEFAULT_THREAD_PRIO 3
+#define DEFAULT_UDP_RECVMBOX_SIZE 6
+#define DEFAULT_TCP_RECVMBOX_SIZE 6
+#define DEFAULT_ACCEPTMBOX_SIZE 6
+
+#define LWIP_DHCP 1
+#define DHCP_DOES_ARP_CHECK 1
+
+#define LWIP_DNS1
+
+#define LWIP_AUTOIP 1
+#define LWIP_DHCP_AUTOIP_COOP ((LWIP_DHCP) && (LWIP_AUTOIP))
+
+#define LWIP_TIMEVAL_PRIVATE 0
+#define LWIP_COMPAT_SOCKETS 1
+#define LWIP_RAW 0
+
+#define SO_REUSE 1
+/* USER CODE END 1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__LWIPOPTS__H__ */
diff --git a/rtemslwip/stm32f4/netstart.c b/rtemslwip/stm32f4/netstart.c
new file mode 100644
index 000..fed7aae
--- /dev/null
+++ b/rtemslwip/stm32f4/netstart.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "lwip/init.h"
+#include "lwip/netif.h"
+#include "ethernetif.h"
+
+int start_networking(
+ struct netif *net_interface,
+ ip_addr_t *ipaddr,
+ ip_addr_t *netmask,
+ ip_addr_t *gateway,
+ unsigned char *mac_ethernet_address
+)
+{
+ tcpip_init( NULL, NULL );
+
+ set_mac_addr(mac_ethernet_address);
+
+ netif_add(
+net_interface,
+>u_addr.ip4,
+>u_addr.ip4,
+>u_addr.ip4,
+NULL,
+ethernetif_init,
+tcpip_input
+ );
+
+ netif_set_default(net_interface);
+
+ if (netif_is_link_up(net_interface)) {
+netif_set_up(net_interface);
+
+sys_thread_new(
+ "stm32f4_ethernet_link_thread",
+ ethernet_link_thread,
+ net_interface,
+ 1024,
+ DEFAULT_THREAD_PRIO
+);
+
+return 0;
+ } else {
+netif_set_down(net_interface);
+ }
+
+ return -1;
+}
--
2.37.2
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[PATCH rtems-lwip v4 2/7] lwip.py: Use ant_glob instead of os.walk()
Updates #4714 --- lwip.py | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/lwip.py b/lwip.py index 2b0c205..2d93d3e 100644 --- a/lwip.py +++ b/lwip.py @@ -110,15 +110,7 @@ def build(bld): source_files.extend(common_source_files) def walk_sources(path): -sources = [] -for root, dirs, files in os.walk(path): -for name in files: -ext = os.path.splitext(name)[1] -src_root = os.path.split(root) -path = os.path.join(src_root[0], src_root[1]) -if ext == '.c' or ext == '.S': -sources.append(os.path.join(path, name)) -return sources +return bld.path.ant_glob([path + '/**/*.c', path + '/**/*.S']) if arch == 'arm': # These files will not compile for BSPs other than TMS570 -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-lwip v4 1/7] lwip.py: Change arch and bsp check method
---
lwip.py | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/lwip.py b/lwip.py
index 84eef2c..2b0c205 100644
--- a/lwip.py
+++ b/lwip.py
@@ -99,6 +99,8 @@ def build(bld):
drv_incl = []
arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
bld.env.RTEMS_ARCH_BSP)
+arch = rtems.arch(bld.env.RTEMS_ARCH_BSP)
+bsp = rtems.bsp(bld.env.RTEMS_ARCH_BSP)
with open('file-import.json', 'r') as cf:
files = json.load(cf)
for f in files['files-to-import']:
@@ -118,27 +120,33 @@ def build(bld):
sources.append(os.path.join(path, name))
return sources
-# These files will not compile for BSPs other than TMS570
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-tms570ls3137_hdk'):
-drv_incl.append('uLan/ports/driver/tms570_emac')
-drv_incl.append('uLan/ports/os')
-driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+if arch == 'arm':
+# These files will not compile for BSPs other than TMS570
+if bsp in ['tms570ls3137_hdk', 'tms570ls3137_hdk_intram',
+ 'tms570ls3137_hdk_sdram', 'tms570ls3137_hdk_with_loader']:
+drv_incl.append('uLan/ports/driver/tms570_emac')
+drv_incl.append('uLan/ports/os')
+driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+
+# These files will only compile for BeagleBone BSPs
+if bsp in ['beagleboneblack', 'beaglebonewhite']:
+driver_source.extend(walk_sources('rtemslwip/beaglebone'))
+drv_incl.append('rtemslwip/beaglebone')
+drv_incl.append('cpsw/src/include')
+driver_source.extend(walk_sources('cpsw/src'))
-# These files will only compile for BeagleBone BSPs
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-beaglebone'):
-driver_source.extend(walk_sources('rtemslwip/beaglebone'))
-drv_incl.append('rtemslwip/beaglebone')
-drv_incl.append('cpsw/src/include')
-driver_source.extend(walk_sources('cpsw/src'))
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
is_aarch64_bsp = False
is_qemu = False
-if bld.env.RTEMS_ARCH_BSP.startswith('aarch64-rtems6-xilinx_zynqmp'):
+if arch == 'aarch64' and bsp in ['xilinx_zynqmp_lp64_qemu',
+ 'xilinx_zynqmp_lp64_zu3eg',
+ 'xilinx_zynqmp_ilp32_qemu',
+ 'xilinx_zynqmp_ilp32_zu3eg']:
is_xilinx_bsp = True
is_aarch64_bsp = True
-if bld.env.RTEMS_ARCH_BSP.endswith('_qemu'):
+if bsp in ['xilinx_zynqmp_lp64_qemu', 'xilinx_zynqmp_ilp32_qemu']:
is_qemu = True
if is_xilinx_bsp:
drv_incl.extend(xilinx_drv_incl)
--
2.37.2
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[PATCH rtems-lwip v4 0/7] lwIP port for STM32F4 BSP
This patch set aims to port RTEMS lwIP for STM32F4 BSP. It also contains generic drivers for STM32 chips in general. It is tested with a TCP echo server application on STM32F407 Discovery Board. Prerequisite: this patch set requires my STM32F4 patches to be applied because it uses STM32 HAL. v2: - Changes the arch and BSP check to use rtems.arch and rtems.bsp - Updates #4714: replace os.walk by ant_glob - Group STM32F4 BSP-specific files together v3: - Make BSP check exact - Add ORIGIN.stm32 and COPYING.stm32 - Imported files under stm32/ are now generated by STM32CubeIDE under RTOS mode - Remove unused lwip.c v4: - Fix improper code addition - Fix aarch64 BSP list in lwip.py - Remove unused lwip.h Duc Doan (7): lwip.py: Change arch and bsp check method lwip.py: Use ant_glob instead of os.walk() Add STM32 Ethernet source rtemslwip: Add STM32F4 lwipopts.h and netstart.c RTEMS port of lwIP for STM32 and STM32F4 BSP lwip.py: Add STM32 lwIP port to build stm32: Convert to Unix line endings COPYING.stm32| 28 + ORIGIN.stm32 | 2 + lwip.py | 69 ++- rtemslwip/stm32f4/lwipopts.h | 147 + rtemslwip/stm32f4/netstart.c | 73 +++ rtemslwip/stm32f4/stm32f4_lwip.c | 39 ++ rtemslwip/stm32f4/stm32f4_lwip.h | 34 ++ stm32/driver/dp83848.c | 664 + stm32/driver/dp83848.h | 436 ++ stm32/ethernetif.c | 986 +++ stm32/ethernetif.h | 54 ++ 11 files changed, 2508 insertions(+), 24 deletions(-) create mode 100644 COPYING.stm32 create mode 100644 ORIGIN.stm32 create mode 100644 rtemslwip/stm32f4/lwipopts.h create mode 100644 rtemslwip/stm32f4/netstart.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h create mode 100644 stm32/driver/dp83848.c create mode 100644 stm32/driver/dp83848.h create mode 100644 stm32/ethernetif.c create mode 100644 stm32/ethernetif.h -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH rtems-lwip v3 1/7] lwip.py: Change arch and bsp check method
I realized that I am not using the latest rtems, so I did not see those BSPs.
Should I create another patch to add the correct BSPs?
Thanks,
Duc
From: devel on behalf of Kinsey Moore
Sent: Thursday, September 8, 2022 12:52:15 PM
To: devel@rtems.org
Subject: Re: [PATCH rtems-lwip v3 1/7] lwip.py: Change arch and bsp check method
On 9/8/2022 11:34, Duc Doan wrote:
> ---
> lwip.py | 31 ++-
> 1 file changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/lwip.py b/lwip.py
> index 84eef2c..1f0b8e2 100644
> --- a/lwip.py
> +++ b/lwip.py
> @@ -99,6 +99,8 @@ def build(bld):
> drv_incl = []
> arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
> bld.env.RTEMS_ARCH_BSP)
...
> is_qemu = False
> -if bld.env.RTEMS_ARCH_BSP.startswith('aarch64-rtems6-xilinx_zynqmp'):
> +if arch == 'aarch64' and bsp in ['xilinx_zynqmp_ultra96']:
> is_xilinx_bsp = True
> is_aarch64_bsp = True
> -if bld.env.RTEMS_ARCH_BSP.endswith('_qemu'):
> +if bsp in ['xilinx_zynq_a9_qemu']:
> is_qemu = True
> if is_xilinx_bsp:
> drv_incl.extend(xilinx_drv_incl)
The BSPs mentioned here for AArch64 are actually ARM BSPs. The proper
set of BSPs to be used here are:
xilinx_zynqmp_lp64_qemu
xilinx_zynqmp_lp64_zu3eg
xilinx_zynqmp_ilp32_qemu
xilinx_zynqmp_ilp32_zu3eg
At some point, the lwIP build needs to get better about managing which BSPs it
supports, but that's not a task for you here and now.
Kinsey
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[PATCH rtems-lwip v3 7/7] stm32: Convert to Unix line endings
This patch converts all files imported from ST to Unix line endings
---
rtemslwip/stm32f4/lwipopts.h | 294 ++---
stm32/driver/dp83848.c | 1328 +++
stm32/driver/dp83848.h | 872 +++
stm32/ethernetif.c | 1970 +-
stm32/ethernetif.h | 106 +-
stm32/lwip.h | 156 +--
6 files changed, 2363 insertions(+), 2363 deletions(-)
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
index aa6b95b..eec98c7 100644
--- a/rtemslwip/stm32f4/lwipopts.h
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -1,147 +1,147 @@
-/* USER CODE BEGIN Header */
-/**
-
**
- * File Name : Target/lwipopts.h
- * Description: This file overrides LwIP stack default configuration
- * done in opt.h file.
-
**
- * @attention
- *
- * Copyright (c) 2022 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
-
**
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion
--*/
-#ifndef __LWIPOPTS__H__
-#define __LWIPOPTS__H__
-
-/*-*/
-/* Current version of LwIP supported by CubeMx: 2.1.2 -*/
-/*-*/
-
-/* Within 'USER CODE' section, code will be kept by default at each generation
*/
-/* USER CODE BEGIN 0 */
-#include
-/* USER CODE END 0 */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
-/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
-/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
-#define WITH_RTOS 1
-/*- CHECKSUM_BY_HARDWARE disabled -*/
-#define CHECKSUM_BY_HARDWARE 0
-/*-*/
-
-/* LwIP Stack Parameters (modified compared to initialization value in opt.h)
-*/
-/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
-/*- Default value in ETH configuration GUI in CubeMx: 1524 -*/
-#define ETH_RX_BUFFER_SIZE 1536
-/*- Value in opt.h for NO_SYS: 0 -*/
-#define NO_SYS 0
-/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
-#define SYS_LIGHTWEIGHT_PROT 1
-/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
-#define MEM_ALIGNMENT 4
-/*- Default Value for H7 devices: 0x30044000 -*/
-//#define LWIP_RAM_HEAP_POINTER 0x20017f58
-/*- Value supported for H7 devices: 1 -*/
-#define LWIP_SUPPORT_CUSTOM_PBUF 1
-/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
-#define LWIP_ETHERNET 1
-/*- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID |
LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
-#define LWIP_DNS_SECURE 7
-/*- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS -
1))/TCP_MSS -*/
-#define TCP_SND_QUEUELEN 9
-/*- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2),
(2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
-#define TCP_SNDLOWAT 1071
-/*- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5)
-*/
-#define TCP_SNDQUEUELOWAT 5
-/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
-#define TCP_WND_UPDATE_THRESHOLD 536
-/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
-//#define LWIP_NETIF_LINK_CALLBACK 0
-/*- Value in opt.h for LWIP_NETCONN: 1 -*/
-#define LWIP_NETCONN 1
-/*- Value in opt.h for LWIP_SOCKET: 1 -*/
-#define LWIP_SOCKET 1
-/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
-//#define RECV_BUFSIZE_DEFAULT 20
-/*- Value in opt.h for LWIP_STATS: 1 -*/
-#define LWIP_STATS 0
-/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
-#define CHECKSUM_GEN_IP 0
-/*- Value in opt.h for CHECKSUM_GEN_UDP: 1 -*/
-#define CHECKSUM_GEN_UDP 0
-/*- Value in opt.h for CHECKSUM_GEN_TCP: 1 -*/
-#define CHECKSUM_GEN_TCP 0
-/*- Value in opt.h for CHECKSUM_GEN_ICMP: 1 -*/
-#define CHECKSUM_GEN_ICMP 0
-/*- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -*/
-#define CHECKSUM_GEN_ICMP6 0
-/*- Value in opt.h for CHECKSUM_CHECK_IP: 1 -*/
-#define CHECKSUM_CHECK_IP 0
-/*- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -*/
-#define CHECKSUM_CHECK_UDP 0
-/*- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -*/
-#define CHECKSUM_CHECK_TCP 0
-/*- Value in opt.h for
[PATCH rtems-lwip v3 6/7] lwip.py: Add STM32 lwIP port to build
---
lwip.py | 21 +
1 file changed, 21 insertions(+)
diff --git a/lwip.py b/lwip.py
index 593f0e0..2d8769d 100644
--- a/lwip.py
+++ b/lwip.py
@@ -92,6 +92,20 @@ common_source_files = [
'rtemslwip/bsd_compat/rtems-kernel-program.c'
]
+stm32_drv_incl = [
+'stm32',
+'stm32/driver'
+]
+
+stm32_drv_src = [
+'stm32/ethernetif.c',
+'stm32/driver/dp83848.c'
+]
+
+stm32_stm32f4_drv_incl = [
+'rtemslwip/stm32f4'
+]
+
def build(bld):
source_files = []
@@ -127,6 +141,13 @@ def build(bld):
drv_incl.append('cpsw/src/include')
driver_source.extend(walk_sources('cpsw/src'))
+# These files will only compile for STM32F4 BSPs
+if bsp == 'stm32f4':
+driver_source.extend(walk_sources('rtemslwip/stm32f4'))
+drv_incl.extend(stm32_drv_incl)
+driver_source.extend(stm32_drv_src)
+drv_incl.extend(stm32_stm32f4_drv_incl)
+
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
--
2.37.2
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[PATCH rtems-lwip v3 5/7] RTEMS port of lwIP for STM32 and STM32F4 BSP
---
rtemslwip/stm32f4/stm32f4_lwip.c | 14
rtemslwip/stm32f4/stm32f4_lwip.h | 9 +++
stm32/ethernetif.c | 110 ++-
stm32/ethernetif.h | 8 ++-
stm32/lwip.h | 2 +
5 files changed, 140 insertions(+), 3 deletions(-)
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.c b/rtemslwip/stm32f4/stm32f4_lwip.c
new file mode 100644
index 000..1f4f07e
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.c
@@ -0,0 +1,14 @@
+#include "stm32f4_lwip.h"
+
+extern ETH_HandleTypeDef heth;
+
+__attribute__((weak)) void Error_Handler(void) {
+__disable_irq();
+while (1)
+{
+}
+}
+
+void ETH_IRQHandler(void) {
+HAL_ETH_IRQHandler();
+}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.h b/rtemslwip/stm32f4/stm32f4_lwip.h
new file mode 100644
index 000..8a2b03a
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.h
@@ -0,0 +1,9 @@
+#ifndef LIPLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H
+#define LIPLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H
+
+#include
+
+void ErrorHandler(void);
+void ETH_IRQHandler(void);
+
+#endif /* LIPLWIP_RTEMSLWIP_STM32F4_STM32F4_LWIP_H */
diff --git a/stm32/ethernetif.c b/stm32/ethernetif.c
index 7a82c51..e71ac8f 100644
--- a/stm32/ethernetif.c
+++ b/stm32/ethernetif.c
@@ -19,7 +19,12 @@
/* USER CODE END Header */
/* Includes
--*/
+#ifndef __rtems__
#include "main.h"
+#else
+#include
+#include
+#endif /* __rtems__ */
#include "lwip/opt.h"
#include "lwip/timeouts.h"
#include "netif/ethernet.h"
@@ -28,7 +33,9 @@
#include "ethernetif.h"
#include "dp83848.h"
#include
+#ifndef __rtems__
#include "cmsis_os.h"
+#endif /* __rtems__ */
#include "lwip/tcpip.h"
/* Within 'USER CODE' section, code will be kept by default at each generation
*/
@@ -38,7 +45,12 @@
/* Private define
*/
/* The time to block waiting for input. */
+#ifndef __rtems__
#define TIME_WAITING_FOR_INPUT ( portMAX_DELAY )
+#else
+#define TIME_WAITING_FOR_INPUT ( RTEMS_NO_TIMEOUT )
+#endif /* __rtems__ */
+
/* USER CODE BEGIN OS_THREAD_STACK_SIZE_WITH_RTOS */
/* Stack size of the interface thread */
#define INTERFACE_THREAD_STACK_SIZE ( 350 )
@@ -109,12 +121,20 @@ ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /*
Ethernet Tx DMA Descriptor
/* USER CODE END 2 */
+#ifndef __rtems__
osSemaphoreId RxPktSemaphore = NULL; /* Semaphore to signal incoming packets
*/
osSemaphoreId TxPktSemaphore = NULL; /* Semaphore to signal transmit packet
complete */
+#else
+rtems_id RxPktSemaphore; /* Semaphore to signal incoming packets */
+rtems_id TxPktSemaphore; /* Semaphore to signal transmit packet complete */
+#endif /* __rtems__ */
/* Global Ethernet handle */
ETH_HandleTypeDef heth;
ETH_TxPacketConfig TxConfig;
+#ifdef __rtems__
+static uint8_t *MACAddr;
+#endif /* __rtems__ */
/* Private function prototypes
---*/
int32_t ETH_PHY_IO_Init(void);
@@ -144,7 +164,11 @@ void pbuf_free_custom(struct pbuf *p);
*/
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth)
{
+#ifndef __rtems__
osSemaphoreRelease(RxPktSemaphore);
+#else
+ rtems_semaphore_release(RxPktSemaphore);
+#endif /* __rtems__ */
}
/**
* @brief Ethernet Tx Transfer completed callback
@@ -153,7 +177,11 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *handlerEth)
*/
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *handlerEth)
{
+#ifndef __rtems__
osSemaphoreRelease(TxPktSemaphore);
+#else
+ rtems_semaphore_release(TxPktSemaphore);
+#endif /* __rtems__ */
}
/**
* @brief Ethernet DMA transfer error callback
@@ -164,12 +192,21 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *handlerEth)
{
if((HAL_ETH_GetDMAError(handlerEth) & ETH_DMASR_RBUS) == ETH_DMASR_RBUS)
{
- osSemaphoreRelease(RxPktSemaphore);
+#ifndef __rtems__
+osSemaphoreRelease(RxPktSemaphore);
+#else
+rtems_semaphore_release(RxPktSemaphore);
+#endif /* __rtems__ */
}
}
/* USER CODE BEGIN 4 */
-
+#ifdef __rtems__
+void set_mac_addr(uint8_t *mac_addr)
+{
+ MACAddr = mac_addr;
+}
+#endif /* __rtems__ */
/* USER CODE END 4 */
/***
@@ -186,15 +223,20 @@ static void low_level_init(struct netif *netif)
{
HAL_StatusTypeDef hal_eth_init_status = HAL_OK;
/* USER CODE BEGIN OS_THREAD_ATTR_CMSIS_RTOS_V2 */
+#ifndef __rtems__
osThreadAttr_t attributes;
+#endif /* __rtems__ */
/* USER CODE END OS_THREAD_ATTR_CMSIS_RTOS_V2 */
uint32_t duplex, speed = 0;
int32_t PHYLinkState = 0;
ETH_MACConfigTypeDef MACConf = {0};
/* Start ETH HAL Init */
+#ifndef __rtems__
uint8_t MACAddr[6] ;
+#endif /* __rtems__ */
heth.Instance = ETH;
+#ifndef __rtems__
MACAddr[0] = 0x02;
[PATCH rtems-lwip v3 3/7] Add STM32 Ethernet source
This patch adds ST's Ethernet and lwIP port and DP83848 driver. The
files are generated using STM32CubeIDE with STM32F4 Cube FW v1.27.1,
under RTOS mode.
---
COPYING.stm32 | 28 ++
ORIGIN.stm32 | 2 +
stm32/driver/dp83848.c | 664 +++
stm32/driver/dp83848.h | 436
stm32/ethernetif.c | 879 +
stm32/ethernetif.h | 47 +++
stm32/lwip.h | 76
7 files changed, 2132 insertions(+)
create mode 100644 COPYING.stm32
create mode 100644 ORIGIN.stm32
create mode 100644 stm32/driver/dp83848.c
create mode 100644 stm32/driver/dp83848.h
create mode 100644 stm32/ethernetif.c
create mode 100644 stm32/ethernetif.h
create mode 100644 stm32/lwip.h
diff --git a/COPYING.stm32 b/COPYING.stm32
new file mode 100644
index 000..f42052b
--- /dev/null
+++ b/COPYING.stm32
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *this list of conditions and the following disclaimer in the documentation
+ *and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+
diff --git a/ORIGIN.stm32 b/ORIGIN.stm32
new file mode 100644
index 000..afc15ed
--- /dev/null
+++ b/ORIGIN.stm32
@@ -0,0 +1,2 @@
+The files under stm32/ directory are generated using STM32CubeIDE with
+STM32F4 Cube FW v1.27.1, under RTOS mode.
diff --git a/stm32/driver/dp83848.c b/stm32/driver/dp83848.c
new file mode 100644
index 000..2c5d59b
--- /dev/null
+++ b/stm32/driver/dp83848.c
@@ -0,0 +1,664 @@
+/**
+
**
+ * @filedp83848.c
+ * @author MCD Application Team
+ * @brief This file provides a set of functions needed to manage the DP83848
+ * PHY devices.
+
**
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *opensource.org/licenses/BSD-3-Clause
+ *
+
**
+ */
+
+/* Includes
--*/
+#include "dp83848.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @defgroup DP83848 DP83848
+ * @{
+ */
+
+/* Private typedef
---*/
+/* Private define
*/
+/** @defgroup DP83848_Private_Defines DP83848 Private Defines
+ * @{
+ */
+#define DP83848_SW_RESET_TO((uint32_t)500U)
+#define DP83848_INIT_TO((uint32_t)2000U)
+#define DP83848_MAX_DEV_ADDR ((uint32_t)31U)
+/**
+ * @}
+ */
+
+/* Private macro
-*/
+/* Private variables
-*/
+/* Private function prototypes
---*/
+/* Private functions
-*/
+/** @defgroup DP83848_Private_Functions DP83848 Private Functions
+ * @{
+ */
+
+/**
+ * @brief Register IO functions to component object
+ * @param pObj: device object of DP83848_Object_t.
+ * @param ioctx: holds device IO functions.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ERROR if missing mandatory function
+ */
+int32_t
[PATCH rtems-lwip v3 4/7] rtemslwip: Add STM32F4 lwipopts.h and netstart.c
ault Value for ETHARP_DEBUG: LWIP_DBG_OFF ---*/
+/*-*/
+/* USER CODE BEGIN 1 */
+//#define LWIP_DEBUG 1
+#define LWIP_ARP 1
+
+#define LWIP_NETIF_API 1
+
+#define NO_SYS_NO_TIMERS 0
+
+#define IP_REASSEMBLY 0
+#define IP_FRAG 0
+#define LWIP_IPV4 1
+#define LWIP_IPV6 1
+
+#define LWIP_TCPIP_CORE_LOCKING 1
+#define TCPIP_THREAD_STACKSIZE 1024
+#define TCPIP_THREAD_PRIO 24
+#define TCPIP_MBOX_SIZE 6
+#define SLIPIF_THREAD_STACKSIZE 1024
+#define SLIPIF_THREAD_PRIO 3
+#define DEFAULT_THREAD_STACKSIZE 1024
+#define DEFAULT_THREAD_PRIO 3
+#define DEFAULT_UDP_RECVMBOX_SIZE 6
+#define DEFAULT_TCP_RECVMBOX_SIZE 6
+#define DEFAULT_ACCEPTMBOX_SIZE 6
+
+#define LWIP_DHCP 1
+#define DHCP_DOES_ARP_CHECK 1
+
+#define LWIP_DNS1
+
+#define LWIP_AUTOIP 1
+#define LWIP_DHCP_AUTOIP_COOP ((LWIP_DHCP) && (LWIP_AUTOIP))
+
+#define LWIP_TIMEVAL_PRIVATE 0
+#define LWIP_COMPAT_SOCKETS 1
+#define LWIP_RAW 0
+
+#define SO_REUSE 1
+/* USER CODE END 1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__LWIPOPTS__H__ */
diff --git a/rtemslwip/stm32f4/netstart.c b/rtemslwip/stm32f4/netstart.c
new file mode 100644
index 000..74edac6
--- /dev/null
+++ b/rtemslwip/stm32f4/netstart.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "lwip.h"
+#include "lwip/init.h"
+#include "lwip/netif.h"
+#include "ethernetif.h"
+
+int start_networking(
+ struct netif *net_interface,
+ ip_addr_t *ipaddr,
+ ip_addr_t *netmask,
+ ip_addr_t *gateway,
+ unsigned char *mac_ethernet_address
+)
+{
+ tcpip_init( NULL, NULL );
+
+ set_mac_addr(mac_ethernet_address);
+
+ netif_add(
+net_interface,
+>u_addr.ip4,
+>u_addr.ip4,
+>u_addr.ip4,
+NULL,
+ethernetif_init,
+tcpip_input
+ );
+
+ netif_set_default(net_interface);
+
+ if (netif_is_link_up(net_interface)) {
+netif_set_up(net_interface);
+
+sys_thread_new(
+ "stm32f4_ethernet_link_thread",
+ ethernet_link_thread,
+ net_interface,
+ 1024,
+ DEFAULT_THREAD_PRIO
+);
+
+return 0;
+ } else {
+netif_set_down(net_interface);
+ }
+
+ return -1;
+}
--
2.37.2
___
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[PATCH rtems-lwip v3 2/7] lwip.py: Use ant_glob instead of os.walk()
Updates #4714 --- lwip.py | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/lwip.py b/lwip.py index 1f0b8e2..593f0e0 100644 --- a/lwip.py +++ b/lwip.py @@ -110,15 +110,7 @@ def build(bld): source_files.extend(common_source_files) def walk_sources(path): -sources = [] -for root, dirs, files in os.walk(path): -for name in files: -ext = os.path.splitext(name)[1] -src_root = os.path.split(root) -path = os.path.join(src_root[0], src_root[1]) -if ext == '.c' or ext == '.S': -sources.append(os.path.join(path, name)) -return sources +return bld.path.ant_glob([path + '/**/*.c', path + '/**/*.S']) if arch == 'arm': # These files will not compile for BSPs other than TMS570 -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-lwip v3 0/7] lwIP port for STM32F4 BSP
This patch set aims to port RTEMS lwIP for STM32F4 BSP. It also contains generic drivers for STM32 chips in general. It is tested with a TCP echo server application on STM32F407 Discovery Board. Prerequisite: this patch set requires my STM32F4 patches to be applied because it uses STM32 HAL. v2: - Changes the arch and BSP check to use rtems.arch and rtems.bsp - Updates #4714: replace os.walk by ant_glob - Group STM32F4 BSP-specific files together v3: - Make BSP check exact - Add ORIGIN.stm32 and COPYING.stm32 - Imported files under stm32/ are now generated by STM32CubeIDE under RTOS mode - Remove unused lwip.c Duc Doan (7): lwip.py: Change arch and bsp check method lwip.py: Use ant_glob instead of os.walk() Add STM32 Ethernet source rtemslwip: Add STM32F4 lwipopts.h and netstart.c RTEMS port of lwIP for STM32 and STM32F4 BSP lwip.py: Add STM32 lwIP port to build stm32: Convert to Unix line endings COPYING.stm32| 28 + ORIGIN.stm32 | 2 + lwip.py | 66 ++- rtemslwip/stm32f4/lwipopts.h | 147 + rtemslwip/stm32f4/netstart.c | 74 +++ rtemslwip/stm32f4/stm32f4_lwip.c | 14 + rtemslwip/stm32f4/stm32f4_lwip.h | 9 + stm32/driver/dp83848.c | 664 + stm32/driver/dp83848.h | 436 ++ stm32/ethernetif.c | 985 +++ stm32/ethernetif.h | 53 ++ stm32/lwip.h | 78 +++ 12 files changed, 2532 insertions(+), 24 deletions(-) create mode 100644 COPYING.stm32 create mode 100644 ORIGIN.stm32 create mode 100644 rtemslwip/stm32f4/lwipopts.h create mode 100644 rtemslwip/stm32f4/netstart.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h create mode 100644 stm32/driver/dp83848.c create mode 100644 stm32/driver/dp83848.h create mode 100644 stm32/ethernetif.c create mode 100644 stm32/ethernetif.h create mode 100644 stm32/lwip.h -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-lwip v3 1/7] lwip.py: Change arch and bsp check method
---
lwip.py | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/lwip.py b/lwip.py
index 84eef2c..1f0b8e2 100644
--- a/lwip.py
+++ b/lwip.py
@@ -99,6 +99,8 @@ def build(bld):
drv_incl = []
arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
bld.env.RTEMS_ARCH_BSP)
+arch = rtems.arch(bld.env.RTEMS_ARCH_BSP)
+bsp = rtems.bsp(bld.env.RTEMS_ARCH_BSP)
with open('file-import.json', 'r') as cf:
files = json.load(cf)
for f in files['files-to-import']:
@@ -118,27 +120,30 @@ def build(bld):
sources.append(os.path.join(path, name))
return sources
-# These files will not compile for BSPs other than TMS570
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-tms570ls3137_hdk'):
-drv_incl.append('uLan/ports/driver/tms570_emac')
-drv_incl.append('uLan/ports/os')
-driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+if arch == 'arm':
+# These files will not compile for BSPs other than TMS570
+if bsp in ['tms570ls3137_hdk', 'tms570ls3137_hdk_intram', \
+ 'tms570ls3137_hdk_sdram', 'tms570ls3137_hdk_with_loader']:
+drv_incl.append('uLan/ports/driver/tms570_emac')
+drv_incl.append('uLan/ports/os')
+driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+
+# These files will only compile for BeagleBone BSPs
+if bsp in ['beagleboneblack', 'beaglebonewhite']:
+driver_source.extend(walk_sources('rtemslwip/beaglebone'))
+drv_incl.append('rtemslwip/beaglebone')
+drv_incl.append('cpsw/src/include')
+driver_source.extend(walk_sources('cpsw/src'))
-# These files will only compile for BeagleBone BSPs
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-beaglebone'):
-driver_source.extend(walk_sources('rtemslwip/beaglebone'))
-drv_incl.append('rtemslwip/beaglebone')
-drv_incl.append('cpsw/src/include')
-driver_source.extend(walk_sources('cpsw/src'))
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
is_aarch64_bsp = False
is_qemu = False
-if bld.env.RTEMS_ARCH_BSP.startswith('aarch64-rtems6-xilinx_zynqmp'):
+if arch == 'aarch64' and bsp in ['xilinx_zynqmp_ultra96']:
is_xilinx_bsp = True
is_aarch64_bsp = True
-if bld.env.RTEMS_ARCH_BSP.endswith('_qemu'):
+if bsp in ['xilinx_zynq_a9_qemu']:
is_qemu = True
if is_xilinx_bsp:
drv_incl.extend(xilinx_drv_incl)
--
2.37.2
___
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[PATCH rtems-lwip v2 6/7] lwip.py: Add STM32 lwIP port to build
---
lwip.py | 22 ++
1 file changed, 22 insertions(+)
diff --git a/lwip.py b/lwip.py
index 9425dc8..bb382cd 100644
--- a/lwip.py
+++ b/lwip.py
@@ -92,6 +92,21 @@ common_source_files = [
'rtemslwip/bsd_compat/rtems-kernel-program.c'
]
+stm32_drv_incl = [
+'stm32',
+'stm32/driver'
+]
+
+stm32_drv_src = [
+'stm32/ethernetif.c',
+'stm32/lwip.c',
+'stm32/driver/dp83848.c'
+]
+
+stm32_stm32f4_drv_incl = [
+'rtemslwip/stm32f4'
+]
+
def build(bld):
source_files = []
@@ -126,6 +141,13 @@ def build(bld):
drv_incl.append('cpsw/src/include')
driver_source.extend(walk_sources('cpsw/src'))
+# These files will only compile for STM32F4 BSPs
+if bsp == 'stm32f4':
+driver_source.extend(walk_sources('rtemslwip/stm32f4'))
+drv_incl.extend(stm32_drv_incl)
+driver_source.extend(stm32_drv_src)
+drv_incl.extend(stm32_stm32f4_drv_incl)
+
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
--
2.37.2
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[PATCH rtems-lwip v2 4/7] rtemslwip: Add STM32F4 lwipopts.h and netstart.c
---
rtemslwip/stm32f4/lwipopts.h | 141 +++
rtemslwip/stm32f4/netstart.c | 52 +
2 files changed, 193 insertions(+)
create mode 100644 rtemslwip/stm32f4/lwipopts.h
create mode 100644 rtemslwip/stm32f4/netstart.c
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
new file mode 100644
index 000..49a19e4
--- /dev/null
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -0,0 +1,141 @@
+/* USER CODE BEGIN Header */
+/**
+
**
+ * File Name : Target/lwipopts.h
+ * Description: This file overrides LwIP stack default configuration
+ * done in opt.h file.
+
**
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
**
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion
--*/
+#ifndef __LWIPOPTS__H__
+#define __LWIPOPTS__H__
+
+/*-*/
+/* Current version of LwIP supported by CubeMx: 2.1.2 -*/
+/*-*/
+
+/* Within 'USER CODE' section, code will be kept by default at each generation
*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
+/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
+/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
+#define WITH_RTOS 0
+/*- CHECKSUM_BY_HARDWARE disabled -*/
+#define CHECKSUM_BY_HARDWARE 0
+/*-*/
+
+/* LwIP Stack Parameters (modified compared to initialization value in opt.h)
-*/
+/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
+/*- Default value in ETH configuration GUI in CubeMx: 1524 -*/
+#define ETH_RX_BUFFER_SIZE 1536
+/*- Value in opt.h for NO_SYS: 0 -*/
+#define NO_SYS 0
+/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
+#define SYS_LIGHTWEIGHT_PROT 0
+/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
+#define MEM_ALIGNMENT 4
+/*- Default Value for H7 devices: 0x30044000 -*/
+#define LWIP_RAM_HEAP_POINTER 0x20017f58
+/*- Value supported for H7 devices: 1 -*/
+#define LWIP_SUPPORT_CUSTOM_PBUF 1
+/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
+#define LWIP_ETHERNET 1
+/*- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID |
LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
+#define LWIP_DNS_SECURE 7
+/*- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS -
1))/TCP_MSS -*/
+#define TCP_SND_QUEUELEN 9
+/*- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2),
(2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
+#define TCP_SNDLOWAT 1071
+/*- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5)
-*/
+#define TCP_SNDQUEUELOWAT 5
+/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
+#define TCP_WND_UPDATE_THRESHOLD 536
+/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
+#define LWIP_NETIF_LINK_CALLBACK 1
+/*- Value in opt.h for LWIP_NETCONN: 1 -*/
+#define LWIP_NETCONN 1
+/*- Value in opt.h for LWIP_SOCKET: 1 -*/
+#define LWIP_SOCKET 1
+/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
+#define RECV_BUFSIZE_DEFAULT 20
+/*- Value in opt.h for LWIP_STATS: 1 -*/
+#define LWIP_STATS 0
+/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
+#define CHECKSUM_GEN_IP 0
+/*- Value in opt.h for CHECKSUM_GEN_UDP: 1 -*/
+#define CHECKSUM_GEN_UDP 0
+/*- Value in opt.h for CHECKSUM_GEN_TCP: 1 -*/
+#define CHECKSUM_GEN_TCP 0
+/*- Value in opt.h for CHECKSUM_GEN_ICMP: 1 -*/
+#define CHECKSUM_GEN_ICMP 0
+/*- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -*/
+#define CHECKSUM_GEN_ICMP6 0
+/*- Value in opt.h for CHECKSUM_CHECK_IP: 1 -*/
+#define CHECKSUM_CHECK_IP 0
+/*- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -*/
+#define CHECKSUM_CHECK_UDP 0
+/*- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -*/
+#define CHECKSUM_CHECK_TCP 0
+/*- Value in opt.h for CHECKSUM_CHECK_ICMP: 1 -*/
+#define CHECKSUM_CHECK_ICMP 0
+/*- Value in opt.h for CHECKSUM_CHECK_ICMP6: 1 -*/
+#define CHECKSUM_CHECK_ICMP6 0
+/*- Default Value for ETHARP_DEBUG: LWIP_DBG_OFF
[PATCH rtems-lwip v2 5/7] RTEMS port of lwIP for STM32 and STM32F4 BSP
---
rtemslwip/stm32f4/lwipopts.h | 24 ++-
rtemslwip/stm32f4/netstart.c | 29 +++-
rtemslwip/stm32f4/stm32f4_lwip.c | 14 ++
rtemslwip/stm32f4/stm32f4_lwip.h | 9 +
stm32/ethernetif.c | 288 +--
stm32/ethernetif.h | 14 +-
stm32/lwip.c | 103 +++
stm32/lwip.h | 2 +
8 files changed, 374 insertions(+), 109 deletions(-)
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
index 49a19e4..41cc68f 100644
--- a/rtemslwip/stm32f4/lwipopts.h
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -28,7 +28,7 @@
/* Within 'USER CODE' section, code will be kept by default at each generation
*/
/* USER CODE BEGIN 0 */
-
+#include
/* USER CODE END 0 */
#ifdef __cplusplus
@@ -38,7 +38,7 @@
/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
-#define WITH_RTOS 0
+#define WITH_RTOS 1
/*- CHECKSUM_BY_HARDWARE disabled -*/
#define CHECKSUM_BY_HARDWARE 0
/*-*/
@@ -50,11 +50,11 @@
/*- Value in opt.h for NO_SYS: 0 -*/
#define NO_SYS 0
/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
-#define SYS_LIGHTWEIGHT_PROT 0
+#define SYS_LIGHTWEIGHT_PROT 1
/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
#define MEM_ALIGNMENT 4
/*- Default Value for H7 devices: 0x30044000 -*/
-#define LWIP_RAM_HEAP_POINTER 0x20017f58
+//#define LWIP_RAM_HEAP_POINTER 0x20017f58
/*- Value supported for H7 devices: 1 -*/
#define LWIP_SUPPORT_CUSTOM_PBUF 1
/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
@@ -70,13 +70,13 @@
/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
#define TCP_WND_UPDATE_THRESHOLD 536
/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
-#define LWIP_NETIF_LINK_CALLBACK 1
+//#define LWIP_NETIF_LINK_CALLBACK 0
/*- Value in opt.h for LWIP_NETCONN: 1 -*/
#define LWIP_NETCONN 1
/*- Value in opt.h for LWIP_SOCKET: 1 -*/
#define LWIP_SOCKET 1
/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
-#define RECV_BUFSIZE_DEFAULT 20
+//#define RECV_BUFSIZE_DEFAULT 20
/*- Value in opt.h for LWIP_STATS: 1 -*/
#define LWIP_STATS 0
/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
@@ -115,9 +115,19 @@
#define LWIP_IPV6 1
#define LWIP_TCPIP_CORE_LOCKING 1
+#define TCPIP_THREAD_STACKSIZE 1024
+#define TCPIP_THREAD_PRIO 24
+#define TCPIP_MBOX_SIZE 6
+#define SLIPIF_THREAD_STACKSIZE 1024
+#define SLIPIF_THREAD_PRIO 3
+#define DEFAULT_THREAD_STACKSIZE 1024
+#define DEFAULT_THREAD_PRIO 3
+#define DEFAULT_UDP_RECVMBOX_SIZE 6
+#define DEFAULT_TCP_RECVMBOX_SIZE 6
+#define DEFAULT_ACCEPTMBOX_SIZE 6
#define LWIP_DHCP 1
-#define DHCP_DOES_ARP_CHECK 0
+#define DHCP_DOES_ARP_CHECK 1
#define LWIP_DNS1
diff --git a/rtemslwip/stm32f4/netstart.c b/rtemslwip/stm32f4/netstart.c
index 88e846a..6ddcc81 100644
--- a/rtemslwip/stm32f4/netstart.c
+++ b/rtemslwip/stm32f4/netstart.c
@@ -26,7 +26,10 @@
#include
#include
-#include
+#include "lwip.h"
+#include "lwip/init.h"
+#include "lwip/netif.h"
+#include "ethernetif.h"
int start_networking(
struct netif *net_interface,
@@ -38,15 +41,35 @@ int start_networking(
{
tcpip_init( NULL, NULL );
- netif_add(net_interface, ipaddr, netmask, gw, NULL, _init,
_input);
+ set_mac_addr(mac_ethernet_address);
+
+ netif_add(
+net_interface,
+>u_addr.ip4,
+>u_addr.ip4,
+>u_addr.ip4,
+NULL,
+ethernetif_init,
+tcpip_input
+ );
netif_set_default(net_interface);
if (netif_is_link_up(net_interface)) {
netif_set_up(net_interface);
+
+sys_thread_new(
+ "stm32f4_ethernet_link_thread",
+ ethernet_link_thread,
+ net_interface,
+ 1024,
+ DEFAULT_THREAD_PRIO
+);
+
+return 0;
} else {
netif_set_down(net_interface);
}
- return 0;
+ return -1;
}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.c b/rtemslwip/stm32f4/stm32f4_lwip.c
new file mode 100644
index 000..1f4f07e
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.c
@@ -0,0 +1,14 @@
+#include "stm32f4_lwip.h"
+
+extern ETH_HandleTypeDef heth;
+
+__attribute__((weak)) void Error_Handler(void) {
+__disable_irq();
+while (1)
+{
+}
+}
+
+void ETH_IRQHandler(void) {
+HAL_ETH_IRQHandler();
+}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.h b/rtemslwip/stm32f4/stm32f4_lwip.h
new file mode 100644
index 000..8a2b03a
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.h
@@ -0,0
[PATCH rtems-lwip v2 3/7] Add STM32 Ethernet source
This patch adds ST's Ethernet and lwIP port and DP83848 driver. The
files are generated using STM32CubeIDE with STM32F4 Cube FW v1.27.1,
under no RTOS mode.
---
stm32/driver/dp83848.c | 664 +
stm32/driver/dp83848.h | 436
stm32/ethernetif.c | 737 +
stm32/ethernetif.h | 45 +++
stm32/lwip.c | 260 +++
stm32/lwip.h | 76 +
6 files changed, 2218 insertions(+)
create mode 100644 stm32/driver/dp83848.c
create mode 100644 stm32/driver/dp83848.h
create mode 100644 stm32/ethernetif.c
create mode 100644 stm32/ethernetif.h
create mode 100644 stm32/lwip.c
create mode 100644 stm32/lwip.h
diff --git a/stm32/driver/dp83848.c b/stm32/driver/dp83848.c
new file mode 100644
index 000..2c5d59b
--- /dev/null
+++ b/stm32/driver/dp83848.c
@@ -0,0 +1,664 @@
+/**
+
**
+ * @filedp83848.c
+ * @author MCD Application Team
+ * @brief This file provides a set of functions needed to manage the DP83848
+ * PHY devices.
+
**
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *opensource.org/licenses/BSD-3-Clause
+ *
+
**
+ */
+
+/* Includes
--*/
+#include "dp83848.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @defgroup DP83848 DP83848
+ * @{
+ */
+
+/* Private typedef
---*/
+/* Private define
*/
+/** @defgroup DP83848_Private_Defines DP83848 Private Defines
+ * @{
+ */
+#define DP83848_SW_RESET_TO((uint32_t)500U)
+#define DP83848_INIT_TO((uint32_t)2000U)
+#define DP83848_MAX_DEV_ADDR ((uint32_t)31U)
+/**
+ * @}
+ */
+
+/* Private macro
-*/
+/* Private variables
-*/
+/* Private function prototypes
---*/
+/* Private functions
-*/
+/** @defgroup DP83848_Private_Functions DP83848 Private Functions
+ * @{
+ */
+
+/**
+ * @brief Register IO functions to component object
+ * @param pObj: device object of DP83848_Object_t.
+ * @param ioctx: holds device IO functions.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ERROR if missing mandatory function
+ */
+int32_t DP83848_RegisterBusIO(dp83848_Object_t *pObj, dp83848_IOCtx_t *ioctx)
+{
+ if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
+ {
+return DP83848_STATUS_ERROR;
+ }
+
+ pObj->IO.Init = ioctx->Init;
+ pObj->IO.DeInit = ioctx->DeInit;
+ pObj->IO.ReadReg = ioctx->ReadReg;
+ pObj->IO.WriteReg = ioctx->WriteReg;
+ pObj->IO.GetTick = ioctx->GetTick;
+
+ return DP83848_STATUS_OK;
+}
+
+/**
+ * @brief Initialize the DP83848 and configure the needed hardware resources
+ * @param pObj: device object DP83848_Object_t.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ADDRESS_ERROR if cannot find device address
+ * DP83848_STATUS_READ_ERROR if connot read register
+ * DP83848_STATUS_WRITE_ERROR if connot write to register
+ * DP83848_STATUS_RESET_TIMEOUT if cannot perform a software reset
+ */
+ int32_t DP83848_Init(dp83848_Object_t *pObj)
+ {
+ uint32_t tickstart = 0, regvalue = 0, addr = 0;
+ int32_t status = DP83848_STATUS_OK;
+
+ if(pObj->Is_Initialized == 0)
+ {
+ if(pObj->IO.Init != 0)
+ {
+ /* GPIO and Clocks initialization */
+ pObj->IO.Init();
+ }
+
+ /* for later check */
+ pObj->DevAddr = DP83848_MAX_DEV_ADDR + 1;
+
+ /* Get the device address from special mode register */
+ for(addr = 0; addr <= DP83848_MAX_DEV_ADDR; addr ++)
+ {
+ if(pObj->IO.ReadReg(addr, DP83848_SMR, ) < 0)
+ {
+ status = DP83848_STATUS_READ_ERROR;
+ /* Can't read from this device address
+continue with next address */
+ continue;
+ }
+
+ if((regvalue & DP83848_SMR_PHY_ADDR) == addr)
+ {
+ pObj->DevAddr = addr;
+ status = DP83848_STATUS_OK;
+ break;
+ }
+ }
+
+ if(pObj->DevAddr > DP83848_MAX_DEV_ADDR)
+ {
+ status = DP83848_STATUS_ADDRESS_ERROR;
+ }
+
+ /* if device address is matched */
+
[PATCH rtems-lwip v2 2/7] lwip.py: Use ant_glob instead of os.walk()
Updates #4714 --- lwip.py | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/lwip.py b/lwip.py index 9db5348..9425dc8 100644 --- a/lwip.py +++ b/lwip.py @@ -110,15 +110,7 @@ def build(bld): source_files.extend(common_source_files) def walk_sources(path): -sources = [] -for root, dirs, files in os.walk(path): -for name in files: -ext = os.path.splitext(name)[1] -src_root = os.path.split(root) -path = os.path.join(src_root[0], src_root[1]) -if ext == '.c' or ext == '.S': -sources.append(os.path.join(path, name)) -return sources +return bld.path.ant_glob([path + '/**/*.c', path + '/**/*.S']) if arch == 'arm': # These files will not compile for BSPs other than TMS570 -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-lwip v2 1/7] lwip.py: Change arch and bsp check method
---
lwip.py | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/lwip.py b/lwip.py
index 84eef2c..9db5348 100644
--- a/lwip.py
+++ b/lwip.py
@@ -99,6 +99,8 @@ def build(bld):
drv_incl = []
arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
bld.env.RTEMS_ARCH_BSP)
+arch = rtems.arch(bld.env.RTEMS_ARCH_BSP)
+bsp = rtems.bsp(bld.env.RTEMS_ARCH_BSP)
with open('file-import.json', 'r') as cf:
files = json.load(cf)
for f in files['files-to-import']:
@@ -118,27 +120,29 @@ def build(bld):
sources.append(os.path.join(path, name))
return sources
-# These files will not compile for BSPs other than TMS570
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-tms570ls3137_hdk'):
-drv_incl.append('uLan/ports/driver/tms570_emac')
-drv_incl.append('uLan/ports/os')
-driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+if arch == 'arm':
+# These files will not compile for BSPs other than TMS570
+if bsp.startswith('tms570ls3137_hdk'):
+drv_incl.append('uLan/ports/driver/tms570_emac')
+drv_incl.append('uLan/ports/os')
+driver_source.extend(walk_sources('uLan/ports/driver/tms570_emac'))
+
+# These files will only compile for BeagleBone BSPs
+if bsp.startswith('beaglebone'):
+driver_source.extend(walk_sources('rtemslwip/beaglebone'))
+drv_incl.append('rtemslwip/beaglebone')
+drv_incl.append('cpsw/src/include')
+driver_source.extend(walk_sources('cpsw/src'))
-# These files will only compile for BeagleBone BSPs
-if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-beaglebone'):
-driver_source.extend(walk_sources('rtemslwip/beaglebone'))
-drv_incl.append('rtemslwip/beaglebone')
-drv_incl.append('cpsw/src/include')
-driver_source.extend(walk_sources('cpsw/src'))
# These files will only compile for BSPs on Xilinx hardware
is_xilinx_bsp = False
is_aarch64_bsp = False
is_qemu = False
-if bld.env.RTEMS_ARCH_BSP.startswith('aarch64-rtems6-xilinx_zynqmp'):
+if arch == 'aarch64' and bsp.startswith('xilinx_zynqmp'):
is_xilinx_bsp = True
is_aarch64_bsp = True
-if bld.env.RTEMS_ARCH_BSP.endswith('_qemu'):
+if bsp.endswith('_qemu'):
is_qemu = True
if is_xilinx_bsp:
drv_incl.extend(xilinx_drv_incl)
--
2.37.2
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[PATCH rtems-lwip v2 0/7] lwIP port for STM32F4 BSP
This patch set aims to port RTEMS lwIP for STM32F4 BSP. It also contains generic drivers for STM32 chips in general. It is tested with a TCP echo server application on STM32F407 Discovery Board. Prerequisite: this patch set requires my STM32F4 patches to be applied because it uses STM32 HAL. v2: - Changes the arch and BSP check to use rtems.arch and rtems.bsp - Updates #4714: replace os.walk by ant_glob - Group STM32F4 BSP-specific files together Duc Doan (7): lwip.py: Change arch and bsp check method lwip.py: Use ant_glob instead of os.walk() Add STM32 Ethernet source rtemslwip: Add STM32F4 lwipopts.h and netstart.c RTEMS port of lwIP for STM32 and STM32F4 BSP lwip.py: Add STM32 lwIP port to build stm32: Convert to Unix line endings lwip.py | 66 ++- rtemslwip/stm32f4/lwipopts.h | 151 + rtemslwip/stm32f4/netstart.c | 75 +++ rtemslwip/stm32f4/stm32f4_lwip.c | 14 + rtemslwip/stm32f4/stm32f4_lwip.h | 9 + stm32/driver/dp83848.c | 664 + stm32/driver/dp83848.h | 436 ++ stm32/ethernetif.c | 989 +++ stm32/ethernetif.h | 53 ++ stm32/lwip.c | 207 +++ stm32/lwip.h | 78 +++ 11 files changed, 2718 insertions(+), 24 deletions(-) create mode 100644 rtemslwip/stm32f4/lwipopts.h create mode 100644 rtemslwip/stm32f4/netstart.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h create mode 100644 stm32/driver/dp83848.c create mode 100644 stm32/driver/dp83848.h create mode 100644 stm32/ethernetif.c create mode 100644 stm32/ethernetif.h create mode 100644 stm32/lwip.c create mode 100644 stm32/lwip.h -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH rtems-lwip 4/5] lwip.py: Add STM32 lwIP port to build
Hello Chris,
Thank you for pointing them out. I'll fix them in the next patch set.
Best,
Duc
On Mon, 2022-09-05 at 09:05 +1000, Chris Johns wrote:
> On 4/9/2022 11:25 am, Duc Doan wrote:
> > ---
> > lwip.py | 20 +++-
> > 1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/lwip.py b/lwip.py
> > index 84eef2c..d806b64 100644
> > --- a/lwip.py
> > +++ b/lwip.py
> > @@ -92,6 +92,17 @@ common_source_files = [
> > 'rtemslwip/bsd_compat/rtems-kernel-program.c'
> > ]
> >
> > +stm32f4_drv_incl = [
> > + 'rtemslwip/stm32f4',
> > + 'stm32',
> > + 'stm32/driver'
> > +]
> > +
> > +stm32f4_drv_src = [
> > + 'stm32',
> > + 'stm32/driver'
> > +]
> > +
>
> Please group the BSP specific file sets together rather than
> spreading them
> across the common source files. I suggest after the Xilinx ones.
>
> > def build(bld):
> > source_files = []
> > @@ -150,13 +161,20 @@ def build(bld):
> >
> > driver_source.extend(walk_sources('rtemslwip/zynqmp_hardware'))
> > driver_source.extend(xilinx_aarch64_driver_source)
> > drv_incl.extend(xilinx_aarch64_drv_incl)
> > +
> > + # These files will only compile for STM32F4 BSPs
> > + if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-stm32f4'):
>
> This is wrong because the version is hard coded. I see you have
> copied what is
> in the file and they are also wrong.
>
> The formal arch and bsp format is arch/bsp and these tests expose an
> internal
> implementation detail from rtems_waf.
>
> I suggest the code be changed to add:
>
> arch = rtems.arch(bld.env.RTEMS_ARCH_BSP)
> bsp = rtems.bsp(bld.env.RTEMS_ARCH_BSP)
>
> and all the tests changed to:
>
> if arch == 'arm' and bsp == 'stm32f4':
>
> > + driver_source.extend(walk_sources('rtemslwip/stm32f4'))
> > + drv_incl.extend(stm32f4_drv_incl)
> > + for s in stm32f4_drv_src:
> > + driver_source.extend(walk_sources(s))
> >
> > lwip_obj_incl = []
> > lwip_obj_incl.extend(drv_incl)
> > lwip_obj_incl.extend(bsd_compat_incl)
> > lwip_obj_incl.extend(common_includes)
> >
> > - bld(features='c',
> > + bld(features ='c',
>
> The coding standard tool has the previous format.
>
> > target='lwip_obj',
> > cflags='-g -Wall -O0',
> > includes=' '.join(lwip_obj_incl),
>
> Thanks
> Chris
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[PATCH rtems-lwip 4/5] lwip.py: Add STM32 lwIP port to build
---
lwip.py | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/lwip.py b/lwip.py
index 84eef2c..d806b64 100644
--- a/lwip.py
+++ b/lwip.py
@@ -92,6 +92,17 @@ common_source_files = [
'rtemslwip/bsd_compat/rtems-kernel-program.c'
]
+stm32f4_drv_incl = [
+'rtemslwip/stm32f4',
+'stm32',
+'stm32/driver'
+]
+
+stm32f4_drv_src = [
+'stm32',
+'stm32/driver'
+]
+
def build(bld):
source_files = []
@@ -150,13 +161,20 @@ def build(bld):
driver_source.extend(walk_sources('rtemslwip/zynqmp_hardware'))
driver_source.extend(xilinx_aarch64_driver_source)
drv_incl.extend(xilinx_aarch64_drv_incl)
+
+# These files will only compile for STM32F4 BSPs
+if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-stm32f4'):
+driver_source.extend(walk_sources('rtemslwip/stm32f4'))
+drv_incl.extend(stm32f4_drv_incl)
+for s in stm32f4_drv_src:
+driver_source.extend(walk_sources(s))
lwip_obj_incl = []
lwip_obj_incl.extend(drv_incl)
lwip_obj_incl.extend(bsd_compat_incl)
lwip_obj_incl.extend(common_includes)
-bld(features='c',
+bld(features ='c',
target='lwip_obj',
cflags='-g -Wall -O0',
includes=' '.join(lwip_obj_incl),
--
2.37.2
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[PATCH rtems-lwip 1/5] Add STM32 Ethernet source
This patch adds ST's Ethernet and lwIP port and DP83848 driver. The
files are generated using STM32CubeIDE with STM32F4 Cube FW v1.27.1,
under no RTOS mode.
---
stm32/driver/dp83848.c | 664 +
stm32/driver/dp83848.h | 436
stm32/ethernetif.c | 737 +
stm32/ethernetif.h | 45 +++
stm32/lwip.c | 260 +++
stm32/lwip.h | 76 +
6 files changed, 2218 insertions(+)
create mode 100644 stm32/driver/dp83848.c
create mode 100644 stm32/driver/dp83848.h
create mode 100644 stm32/ethernetif.c
create mode 100644 stm32/ethernetif.h
create mode 100644 stm32/lwip.c
create mode 100644 stm32/lwip.h
diff --git a/stm32/driver/dp83848.c b/stm32/driver/dp83848.c
new file mode 100644
index 000..2c5d59b
--- /dev/null
+++ b/stm32/driver/dp83848.c
@@ -0,0 +1,664 @@
+/**
+
**
+ * @filedp83848.c
+ * @author MCD Application Team
+ * @brief This file provides a set of functions needed to manage the DP83848
+ * PHY devices.
+
**
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *opensource.org/licenses/BSD-3-Clause
+ *
+
**
+ */
+
+/* Includes
--*/
+#include "dp83848.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Component
+ * @{
+ */
+
+/** @defgroup DP83848 DP83848
+ * @{
+ */
+
+/* Private typedef
---*/
+/* Private define
*/
+/** @defgroup DP83848_Private_Defines DP83848 Private Defines
+ * @{
+ */
+#define DP83848_SW_RESET_TO((uint32_t)500U)
+#define DP83848_INIT_TO((uint32_t)2000U)
+#define DP83848_MAX_DEV_ADDR ((uint32_t)31U)
+/**
+ * @}
+ */
+
+/* Private macro
-*/
+/* Private variables
-*/
+/* Private function prototypes
---*/
+/* Private functions
-*/
+/** @defgroup DP83848_Private_Functions DP83848 Private Functions
+ * @{
+ */
+
+/**
+ * @brief Register IO functions to component object
+ * @param pObj: device object of DP83848_Object_t.
+ * @param ioctx: holds device IO functions.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ERROR if missing mandatory function
+ */
+int32_t DP83848_RegisterBusIO(dp83848_Object_t *pObj, dp83848_IOCtx_t *ioctx)
+{
+ if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
+ {
+return DP83848_STATUS_ERROR;
+ }
+
+ pObj->IO.Init = ioctx->Init;
+ pObj->IO.DeInit = ioctx->DeInit;
+ pObj->IO.ReadReg = ioctx->ReadReg;
+ pObj->IO.WriteReg = ioctx->WriteReg;
+ pObj->IO.GetTick = ioctx->GetTick;
+
+ return DP83848_STATUS_OK;
+}
+
+/**
+ * @brief Initialize the DP83848 and configure the needed hardware resources
+ * @param pObj: device object DP83848_Object_t.
+ * @retval DP83848_STATUS_OK if OK
+ * DP83848_STATUS_ADDRESS_ERROR if cannot find device address
+ * DP83848_STATUS_READ_ERROR if connot read register
+ * DP83848_STATUS_WRITE_ERROR if connot write to register
+ * DP83848_STATUS_RESET_TIMEOUT if cannot perform a software reset
+ */
+ int32_t DP83848_Init(dp83848_Object_t *pObj)
+ {
+ uint32_t tickstart = 0, regvalue = 0, addr = 0;
+ int32_t status = DP83848_STATUS_OK;
+
+ if(pObj->Is_Initialized == 0)
+ {
+ if(pObj->IO.Init != 0)
+ {
+ /* GPIO and Clocks initialization */
+ pObj->IO.Init();
+ }
+
+ /* for later check */
+ pObj->DevAddr = DP83848_MAX_DEV_ADDR + 1;
+
+ /* Get the device address from special mode register */
+ for(addr = 0; addr <= DP83848_MAX_DEV_ADDR; addr ++)
+ {
+ if(pObj->IO.ReadReg(addr, DP83848_SMR, ) < 0)
+ {
+ status = DP83848_STATUS_READ_ERROR;
+ /* Can't read from this device address
+continue with next address */
+ continue;
+ }
+
+ if((regvalue & DP83848_SMR_PHY_ADDR) == addr)
+ {
+ pObj->DevAddr = addr;
+ status = DP83848_STATUS_OK;
+ break;
+ }
+ }
+
+ if(pObj->DevAddr > DP83848_MAX_DEV_ADDR)
+ {
+ status = DP83848_STATUS_ADDRESS_ERROR;
+ }
+
+ /* if device address is matched */
+
[PATCH rtems-lwip 3/5] RTEMS port of lwIP for STM32 and STM32F4 BSP
---
rtemslwip/stm32f4/lwipopts.h | 24 ++-
rtemslwip/stm32f4/netstart.c | 29 +++-
rtemslwip/stm32f4/stm32f4_lwip.c | 14 ++
rtemslwip/stm32f4/stm32f4_lwip.h | 9 +
stm32/ethernetif.c | 288 +--
stm32/ethernetif.h | 14 +-
stm32/lwip.c | 103 +++
stm32/lwip.h | 2 +
8 files changed, 374 insertions(+), 109 deletions(-)
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c
create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
index 49a19e4..41cc68f 100644
--- a/rtemslwip/stm32f4/lwipopts.h
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -28,7 +28,7 @@
/* Within 'USER CODE' section, code will be kept by default at each generation
*/
/* USER CODE BEGIN 0 */
-
+#include
/* USER CODE END 0 */
#ifdef __cplusplus
@@ -38,7 +38,7 @@
/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
-#define WITH_RTOS 0
+#define WITH_RTOS 1
/*- CHECKSUM_BY_HARDWARE disabled -*/
#define CHECKSUM_BY_HARDWARE 0
/*-*/
@@ -50,11 +50,11 @@
/*- Value in opt.h for NO_SYS: 0 -*/
#define NO_SYS 0
/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
-#define SYS_LIGHTWEIGHT_PROT 0
+#define SYS_LIGHTWEIGHT_PROT 1
/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
#define MEM_ALIGNMENT 4
/*- Default Value for H7 devices: 0x30044000 -*/
-#define LWIP_RAM_HEAP_POINTER 0x20017f58
+//#define LWIP_RAM_HEAP_POINTER 0x20017f58
/*- Value supported for H7 devices: 1 -*/
#define LWIP_SUPPORT_CUSTOM_PBUF 1
/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
@@ -70,13 +70,13 @@
/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
#define TCP_WND_UPDATE_THRESHOLD 536
/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
-#define LWIP_NETIF_LINK_CALLBACK 1
+//#define LWIP_NETIF_LINK_CALLBACK 0
/*- Value in opt.h for LWIP_NETCONN: 1 -*/
#define LWIP_NETCONN 1
/*- Value in opt.h for LWIP_SOCKET: 1 -*/
#define LWIP_SOCKET 1
/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
-#define RECV_BUFSIZE_DEFAULT 20
+//#define RECV_BUFSIZE_DEFAULT 20
/*- Value in opt.h for LWIP_STATS: 1 -*/
#define LWIP_STATS 0
/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
@@ -115,9 +115,19 @@
#define LWIP_IPV6 1
#define LWIP_TCPIP_CORE_LOCKING 1
+#define TCPIP_THREAD_STACKSIZE 1024
+#define TCPIP_THREAD_PRIO 24
+#define TCPIP_MBOX_SIZE 6
+#define SLIPIF_THREAD_STACKSIZE 1024
+#define SLIPIF_THREAD_PRIO 3
+#define DEFAULT_THREAD_STACKSIZE 1024
+#define DEFAULT_THREAD_PRIO 3
+#define DEFAULT_UDP_RECVMBOX_SIZE 6
+#define DEFAULT_TCP_RECVMBOX_SIZE 6
+#define DEFAULT_ACCEPTMBOX_SIZE 6
#define LWIP_DHCP 1
-#define DHCP_DOES_ARP_CHECK 0
+#define DHCP_DOES_ARP_CHECK 1
#define LWIP_DNS1
diff --git a/rtemslwip/stm32f4/netstart.c b/rtemslwip/stm32f4/netstart.c
index 88e846a..6ddcc81 100644
--- a/rtemslwip/stm32f4/netstart.c
+++ b/rtemslwip/stm32f4/netstart.c
@@ -26,7 +26,10 @@
#include
#include
-#include
+#include "lwip.h"
+#include "lwip/init.h"
+#include "lwip/netif.h"
+#include "ethernetif.h"
int start_networking(
struct netif *net_interface,
@@ -38,15 +41,35 @@ int start_networking(
{
tcpip_init( NULL, NULL );
- netif_add(net_interface, ipaddr, netmask, gw, NULL, _init,
_input);
+ set_mac_addr(mac_ethernet_address);
+
+ netif_add(
+net_interface,
+>u_addr.ip4,
+>u_addr.ip4,
+>u_addr.ip4,
+NULL,
+ethernetif_init,
+tcpip_input
+ );
netif_set_default(net_interface);
if (netif_is_link_up(net_interface)) {
netif_set_up(net_interface);
+
+sys_thread_new(
+ "stm32f4_ethernet_link_thread",
+ ethernet_link_thread,
+ net_interface,
+ 1024,
+ DEFAULT_THREAD_PRIO
+);
+
+return 0;
} else {
netif_set_down(net_interface);
}
- return 0;
+ return -1;
}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.c b/rtemslwip/stm32f4/stm32f4_lwip.c
new file mode 100644
index 000..1f4f07e
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.c
@@ -0,0 +1,14 @@
+#include "stm32f4_lwip.h"
+
+extern ETH_HandleTypeDef heth;
+
+__attribute__((weak)) void Error_Handler(void) {
+__disable_irq();
+while (1)
+{
+}
+}
+
+void ETH_IRQHandler(void) {
+HAL_ETH_IRQHandler();
+}
diff --git a/rtemslwip/stm32f4/stm32f4_lwip.h b/rtemslwip/stm32f4/stm32f4_lwip.h
new file mode 100644
index 000..8a2b03a
--- /dev/null
+++ b/rtemslwip/stm32f4/stm32f4_lwip.h
@@ -0,0
[PATCH rtems-lwip 0/5] lwIP port for STM32F4 BSP
This patch set aims to port RTEMS lwIP for STM32F4 BSP. It also contains generic drivers for STM32 chips in general. It is tested with a TCP echo server application on STM32F407 Discovery Board. Prerequisite: this patch set requires my STM32F4 patches to be applied because it uses STM32 HAL. Duc Doan (5): Add STM32 Ethernet source rtemslwip: Add STM32F4 lwipopts.h and netstart.c RTEMS port of lwIP for STM32 and STM32F4 BSP lwip.py: Add STM32 lwIP port to build stm32: Convert to Unix line endings lwip.py | 20 +- rtemslwip/stm32f4/lwipopts.h | 151 + rtemslwip/stm32f4/netstart.c | 75 +++ rtemslwip/stm32f4/stm32f4_lwip.c | 14 + rtemslwip/stm32f4/stm32f4_lwip.h | 9 + stm32/driver/dp83848.c | 664 + stm32/driver/dp83848.h | 436 ++ stm32/ethernetif.c | 989 +++ stm32/ethernetif.h | 53 ++ stm32/lwip.c | 207 +++ stm32/lwip.h | 78 +++ 11 files changed, 2695 insertions(+), 1 deletion(-) create mode 100644 rtemslwip/stm32f4/lwipopts.h create mode 100644 rtemslwip/stm32f4/netstart.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.c create mode 100644 rtemslwip/stm32f4/stm32f4_lwip.h create mode 100644 stm32/driver/dp83848.c create mode 100644 stm32/driver/dp83848.h create mode 100644 stm32/ethernetif.c create mode 100644 stm32/ethernetif.h create mode 100644 stm32/lwip.c create mode 100644 stm32/lwip.h -- 2.37.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems-lwip 2/5] rtemslwip: Add STM32F4 lwipopts.h and netstart.c
---
rtemslwip/stm32f4/lwipopts.h | 141 +++
rtemslwip/stm32f4/netstart.c | 52 +
2 files changed, 193 insertions(+)
create mode 100644 rtemslwip/stm32f4/lwipopts.h
create mode 100644 rtemslwip/stm32f4/netstart.c
diff --git a/rtemslwip/stm32f4/lwipopts.h b/rtemslwip/stm32f4/lwipopts.h
new file mode 100644
index 000..49a19e4
--- /dev/null
+++ b/rtemslwip/stm32f4/lwipopts.h
@@ -0,0 +1,141 @@
+/* USER CODE BEGIN Header */
+/**
+
**
+ * File Name : Target/lwipopts.h
+ * Description: This file overrides LwIP stack default configuration
+ * done in opt.h file.
+
**
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
**
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion
--*/
+#ifndef __LWIPOPTS__H__
+#define __LWIPOPTS__H__
+
+/*-*/
+/* Current version of LwIP supported by CubeMx: 2.1.2 -*/
+/*-*/
+
+/* Within 'USER CODE' section, code will be kept by default at each generation
*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* STM32CubeMX Specific Parameters (not defined in opt.h)
-*/
+/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
+/*- WITH_RTOS disabled (Since FREERTOS is not set) -*/
+#define WITH_RTOS 0
+/*- CHECKSUM_BY_HARDWARE disabled -*/
+#define CHECKSUM_BY_HARDWARE 0
+/*-*/
+
+/* LwIP Stack Parameters (modified compared to initialization value in opt.h)
-*/
+/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
+/*- Default value in ETH configuration GUI in CubeMx: 1524 -*/
+#define ETH_RX_BUFFER_SIZE 1536
+/*- Value in opt.h for NO_SYS: 0 -*/
+#define NO_SYS 0
+/*- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -*/
+#define SYS_LIGHTWEIGHT_PROT 0
+/*- Value in opt.h for MEM_ALIGNMENT: 1 -*/
+#define MEM_ALIGNMENT 4
+/*- Default Value for H7 devices: 0x30044000 -*/
+#define LWIP_RAM_HEAP_POINTER 0x20017f58
+/*- Value supported for H7 devices: 1 -*/
+#define LWIP_SUPPORT_CUSTOM_PBUF 1
+/*- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
+#define LWIP_ETHERNET 1
+/*- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID |
LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
+#define LWIP_DNS_SECURE 7
+/*- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS -
1))/TCP_MSS -*/
+#define TCP_SND_QUEUELEN 9
+/*- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2),
(2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
+#define TCP_SNDLOWAT 1071
+/*- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5)
-*/
+#define TCP_SNDQUEUELOWAT 5
+/*- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4,
TCP_MSS*4) -*/
+#define TCP_WND_UPDATE_THRESHOLD 536
+/*- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -*/
+#define LWIP_NETIF_LINK_CALLBACK 1
+/*- Value in opt.h for LWIP_NETCONN: 1 -*/
+#define LWIP_NETCONN 1
+/*- Value in opt.h for LWIP_SOCKET: 1 -*/
+#define LWIP_SOCKET 1
+/*- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -*/
+#define RECV_BUFSIZE_DEFAULT 20
+/*- Value in opt.h for LWIP_STATS: 1 -*/
+#define LWIP_STATS 0
+/*- Value in opt.h for CHECKSUM_GEN_IP: 1 -*/
+#define CHECKSUM_GEN_IP 0
+/*- Value in opt.h for CHECKSUM_GEN_UDP: 1 -*/
+#define CHECKSUM_GEN_UDP 0
+/*- Value in opt.h for CHECKSUM_GEN_TCP: 1 -*/
+#define CHECKSUM_GEN_TCP 0
+/*- Value in opt.h for CHECKSUM_GEN_ICMP: 1 -*/
+#define CHECKSUM_GEN_ICMP 0
+/*- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -*/
+#define CHECKSUM_GEN_ICMP6 0
+/*- Value in opt.h for CHECKSUM_CHECK_IP: 1 -*/
+#define CHECKSUM_CHECK_IP 0
+/*- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -*/
+#define CHECKSUM_CHECK_UDP 0
+/*- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -*/
+#define CHECKSUM_CHECK_TCP 0
+/*- Value in opt.h for CHECKSUM_CHECK_ICMP: 1 -*/
+#define CHECKSUM_CHECK_ICMP 0
+/*- Value in opt.h for CHECKSUM_CHECK_ICMP6: 1 -*/
+#define CHECKSUM_CHECK_ICMP6 0
+/*- Default Value for ETHARP_DEBUG: LWIP_DBG_OFF
[rtems-tools PATCH] linkers: Update rtems-score-thread.ini
The signature for _Thread_Close() was different in rtems-score-thread.ini and in cpukit/include/rtems/score/threadimpl.h. This changes _Thread_Close() in the .ini file to comply with the new function prototype in threadimpl.h. --- linkers/rtems-score-thread.ini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linkers/rtems-score-thread.ini b/linkers/rtems-score-thread.ini index 974bcfd..f0a1b86 100644 --- a/linkers/rtems-score-thread.ini +++ b/linkers/rtems-score-thread.ini @@ -38,7 +38,7 @@ _Thread_Start = Status_Control, Thread_Control*, const Thread_Entry_information* _Thread_Yield = void, Thread_Control* _Thread_Set_life_protection = Thread_Life_state, Thread_Life_state _Thread_Kill_zombies = void, void -_Thread_Close = void, Thread_Control*, Thread_Control*, Thread_Close_context* +_Thread_Close = Status_Control, Thread_Control*, Thread_Control*, Thread_queue_Context* _Thread_Clear_state = States_Control, Thread_Control*, States_Control _Thread_Set_state = States_Control, Thread_Control*, States_Control _Thread_Load_environment = void, Thread_Control* -- 2.37.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/1] build/cpukit: Add confdefs/face.h to install rule
Updates #4691 --- spec/build/cpukit/librtemscpu.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/spec/build/cpukit/librtemscpu.yml b/spec/build/cpukit/librtemscpu.yml index 2b12507bff..1270ca131b 100644 --- a/spec/build/cpukit/librtemscpu.yml +++ b/spec/build/cpukit/librtemscpu.yml @@ -191,6 +191,7 @@ install: - cpukit/include/rtems/confdefs/clock.h - cpukit/include/rtems/confdefs/console.h - cpukit/include/rtems/confdefs/extensions.h + - cpukit/include/rtems/confdefs/face.h - cpukit/include/rtems/confdefs/inittask.h - cpukit/include/rtems/confdefs/initthread.h - cpukit/include/rtems/confdefs/iodrivers.h -- 2.37.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/1] Add confdefs/face.h to install rule
Duc Doan (1): build/cpukit: Add confdefs/face.h to install rule spec/build/cpukit/librtemscpu.yml | 1 + 1 file changed, 1 insertion(+) -- 2.37.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Adding third-party source with Apache-2.0 license
Dear all, I am working on a project that needs to include ST's STM32F4 HAL into RTEMS, specifically release v1.27.1 at: https://github.com/STMicroelectronics/STM32CubeF4. However, the CMSIS files in this repository have Apache-2.0 license. What do you think about this? Should I add them to RTEMS, or is there anything I need to do to include these sources? Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v6 10/10] bsps/arm/stm32f4: ADC API implementation
---
bsps/arm/stm32f4/adc/adc.c| 495 ++
bsps/arm/stm32f4/include/bsp/stm32f4_adc.h| 198 +++
spec/build/bsps/arm/stm32f4/grp.yml | 2 +
spec/build/bsps/arm/stm32f4/obj.yml | 3 +
spec/build/bsps/arm/stm32f4/optnumadcctrl.yml | 16 +
5 files changed, 714 insertions(+)
create mode 100644 bsps/arm/stm32f4/adc/adc.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_adc.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumadcctrl.yml
diff --git a/bsps/arm/stm32f4/adc/adc.c b/bsps/arm/stm32f4/adc/adc.c
new file mode 100644
index 00..61ced0f4c9
--- /dev/null
+++ b/bsps/arm/stm32f4/adc/adc.c
@@ -0,0 +1,495 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup stm32f4_adc
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+#if defined(ADC3)
+#define NUM_ADC 3
+#elif defined(ADC2)
+#define NUM_ADC 2
+#else
+#define NUM_ADC 1
+#endif
+
+/** Helpers */
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define stm32f4_adc_get_adc_from_base(_base) \
+RTEMS_CONTAINER_OF(_base, stm32f4_adc, base)
+
+void adc_irq_handler(void *arg);
+
+/**
+ * @brief Data structure for non-blocking read.
+ */
+typedef struct {
+uint32_t adc_value;
+rtems_adc_status status;
+} stm32f4_adc_data;
+static stm32f4_adc_data adc_data[NUM_ADC] = {0};
+
+/**
+ * @brief Configure the ADC channel to be the specified one.
+ * An ADC contains multiple channels, so before each operation, we should
+ * select the wanted channel.
+ */
+static rtems_status_code stm32f4_adc_select_channel(
+rtems_adc *base
+);
+
+/***/
+/**
+ * ADC objects that have simple lock for mutex.
+ */
+#ifdef ADC1
+static ADC_TypeDef_Protected _ADC1_protected = { ADC1, false };
+ADC_TypeDef_Protected *const ADC1_protected = &_ADC1_protected;
+
+static rtems_status_code stm32f4_adc_get_adc1(uint32_t id, rtems_adc **out);
+#endif
+#ifdef ADC2
+static ADC_TypeDef_Protected _ADC2_protected = { ADC2, false };
+ADC_TypeDef_Protected *const ADC2_protected = &_ADC2_protected;
+
+static rtems_status_code stm32f4_adc_get_adc2(uint32_t id, rtems_adc **out);
+#endif
+#ifdef ADC3
+static ADC_TypeDef_Protected _ADC3_protected = { ADC3, false };
+ADC_TypeDef_Protected *const ADC3_protected = &_ADC3_protected;
+
+static rtems_status_code stm32f4_adc_get_adc3(uint32_t id, rtems_adc **out);
+#endif
+
+/* Helpers */
+#define STM32F4_GET_ADC_NUMBER(ADCx) \
+( (uintptr_t) ( ADCx ) == (uintptr_t) ADC1 ? 1 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC2 ? 2 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC3 ? 3 : \
+ 0 )
+#define STM32F4_GET_ADCx_FROM_NUMBER(num) (\
+( num ) == 1 ? ADC1 :\
+( num ) == 2 && NUM_ADC >= 2 ? ADC2 :\
+( num ) == 3 && NUM_ADC == 3 ? ADC3 :\
+ NULL)
+#define STM32F4_GET_ADCx_PROTECTED_FROM_NUMBER(num) (\
+( num ) == 1 ? ADC1_protected : \
+( num ) == 2 && NUM_ADC >= 2 ? ADC2_protected : \
+( num ) == 3 && NUM_ADC == 3 ? ADC3_protected : \
+ NULL)
+#define STM32F4_GET_LL_ADC_CHANNEL(num)(\
+
[PATCH v6 09/10] bsps: Add ADC API
---
bsps/include/bsp/adc.h | 407 +++
bsps/shared/dev/adc/adc.c| 249 +++
spec/build/bsps/bspopts.yml | 2 +
spec/build/bsps/obj.yml | 1 +
spec/build/bsps/optmaxnumadc.yml | 16 ++
5 files changed, 675 insertions(+)
create mode 100644 bsps/include/bsp/adc.h
create mode 100644 bsps/shared/dev/adc/adc.c
create mode 100644 spec/build/bsps/optmaxnumadc.yml
diff --git a/bsps/include/bsp/adc.h b/bsps/include/bsp/adc.h
new file mode 100644
index 00..97e596317b
--- /dev/null
+++ b/bsps/include/bsp/adc.h
@@ -0,0 +1,407 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup adc
+ *
+ * RTEMS ADC API.
+ *
+ * This API is created to improve portability for ADC-related operations.
+ *
+ * Drivers need to register each ADC controller to the manager using
+ * @ref rtems_adc_register(). Then, users can get an ADC object of a controller
+ * by specifying the index of that controller (starting from 0, the first
+ * registered ADC).
+ *
+ * Sometimes, ADCs are integrated into a GPIO pin (such as on-chip ADC). If so,
+ * additional effort to set the pin mode to analog might be required.
+ *
+ * The general process to use ADC API:
+ * - Get an ADC object using @ref rtems_adc_get()
+ * - Configure ADC object with rtems_adc_set_* functions
+ * - Call @ref rtems_adc_init()
+ * - The ADC object should be ready by now
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_ADC_H
+#define LIBBSP_BSP_ADC_H
+
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern volatile int *adc_dummy;
+/**
+ * @brief Macro to link BSP source file.
+ *
+ * There might be a case that a BSP GPIO source file is not linked because
+ * of no reference. Use this macro to create a dummy variable to link with
+ * GPIO API. This macro should be placed outside of any function.
+ */
+#define RTEMS_ADC_LINK() \
+static int ___dummy___ = 0;\
+volatile int *adc_dummy = &___dummy___;
+
+/**
+ * Configure the maximum number of ADC controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_ADC_MAXIMUM_CONTROLLERS is a build option.
+ * If it is not defined, it will default to BSP_ADC_NUM_CONTROLLERS.
+ * If BSP's number of controllers is not defined, it will default
+ * to 0.
+ */
+#ifndef CONFIGURE_ADC_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_ADC_NUM_CONTROLLERS
+#define CONFIGURE_ADC_MAXIMUM_CONTROLLERS 0
+#else
+#define CONFIGURE_ADC_MAXIMUM_CONTROLLERS BSP_ADC_NUM_CONTROLLERS
+#endif /* BSP_ADC_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_ADC_MAXIMUM_CONTROLLERS */
+
+typedef enum {
+RTEMS_ADC_NOT_STARTED = 0,
+RTEMS_ADC_NOT_READY,
+RTEMS_ADC_READY
+} rtems_adc_status;
+
+/**
+ * @brief Data alignment.
+ */
+typedef enum {
+RTEMS_ADC_ALIGN_LEFT,
+RTEMS_ADC_ALIGN_RIGHT
+} rtems_adc_align;
+
+/**
+ * @brief Enumeration of reference voltages.
+ */
+typedef enum {
+RTEMS_ADC_REF_DEFAULT = 0,
+RTEMS_ADC_REF_INTERNAL,
+RTEMS_ADC_REF_EXTERNAL,
+RTEMS_ADC_REF_BSP_SPECIFIC = 100
+} rtems_adc_ref;
+
+#define RTEMS_ADC_NO_TIMEOUT 0xU
+
+typedef void (*rtems_adc_isr)(void *);
+typedef double (*rtems_adc_tf) (void *params, uint32_t raw_value);
+typedef struct rtems_adc_handlers rtems_adc_handlers;
+typedef struct rtems_adc_config rtems_adc_config;
+typedef struct rtems_adc rtems_adc;
+
+/**
+ * @brief Driver-specific handlers.
+ * Each driver need to create an object of this structure to supply to
+ * the API.
+ */
+struct rtems_
[PATCH v6 08/10] bsps/arm/stm32f4: GPIO Implementation
---
bsps/arm/stm32f4/gpio/gpio.c | 557 ++
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 281 +
spec/build/bsps/arm/stm32f4/grp.yml | 6 +-
spec/build/bsps/arm/stm32f4/obj.yml | 4 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
5 files changed, 862 insertions(+), 2 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..34b1d62cc0
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup stm32f4_gpio
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef * const GPIOx[] = {
+#ifdef GPIOA_BASE
+GPIOA
+#endif /* GPIOA_BASE */
+#ifdef GPIOB_BASE
+, GPIOB
+#endif /* GPIOB_BASE */
+#ifdef GPIOC_BASE
+, GPIOC
+#endif /* GPIOC_BASE */
+#ifdef GPIOD_BASE
+, GPIOD
+#endif /* GPIOD_BASE */
+#ifdef GPIOE_BASE
+, GPIOE
+#endif /* GPIOE_BASE */
+#ifdef GPIOF_BASE
+, GPIOF
+#endif /* GPIOF_BASE */
+#ifdef GPIOG_BASE
+, GPIOG
+#endif /* GPIOG_BASE */
+#ifdef GPIOH_BASE
+, GPIOH
+#endif /* GPIOH_BASE */
+#ifdef GPIOI_BASE
+, GPIOI
+#endif /* GPIOI_BASE */
+#ifdef GPIOJ_BASE
+, GPIOJ
+#endif /* GPIOJ_BASE */
+#ifdef GPIOK_BASE
+, GPIOK
+#endif /* GPIOK_BASE */
+};
+
+static unsigned int const EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ])
+
+/**
+ * @brief Converts intermediate pin number to 0-15.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PIN_0_15(interm_pin) (( interm_pin ) % 16)
+
+/**
+ * @brief Converts pin number from 0-15 to HA
[PATCH v6 07/10] bsps: Add GPIO API
---
bsps/include/bsp/gpio2.h | 524 ++
bsps/shared/dev/gpio/gpio2.c | 207
spec/build/bsps/bspopts.yml | 2 +
spec/build/bsps/obj.yml | 2 +-
spec/build/bsps/optmaxnumgpio.yml | 16 +
5 files changed, 750 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio2.c
create mode 100644 spec/build/bsps/optmaxnumgpio.yml
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e2a2e3b1e5
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,524 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup gpio2
+ *
+ * RTEMS new GPIO API.
+ *
+ * This API is created to improve portability and simplicity for GPIO.
+ *
+ * This API maps GPIO pins into a flat numbering system, counting from 0.
+ * This pin number is often referred to as a virtual pin number. A GPIO pin
+ * is represented by the structure @ref rtems_gpio. This structure may also
+ * be referred to as a "GPIO object". A "driver" could mean a BSP or a
+ * device driver. A GPIO controller may refer to a physical GPIO controller,
+ * an ADC, a DAC, or just a group of pins that contains one or more pins.
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS is a build option.
+ * If it is not defined, it will default to BSP_GPIO_NUM_CONTROLLERS.
+ * If BSP's number of controllers is not defined, it will default
+ * to 16.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 16
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Macro to initialize rtems_gpio.
+ *
+ * @param gpioh pointer to GPIO handlers
+ */
+#define RTEMS_GPIO_BUILD_BASE(_gpio_handlers) \
+(rtems_gpio) { .virtual_pin = 0,\
+ .gpio_handlers = ( _gpio_handlers ) \
+};
+
+extern int *gpio_dummy;
+/**
+ * @brief Macro to link BSP source file.
+ *
+ * There might be a case that a BSP GPIO source file is not linked because
+ * of no reference. Use this macro to create a dummy variable to link with
+ * GPIO API. This macro should be placed outside of any function.
+ */
+#define RTEMS_GPIO_LINK() \
+static int ___dummy___ = 0; \
+int *gpio_dummy = &___dummy___;
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 100
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL = 0,
+RTEMS_GPIO_PULLUP = 1,
+RTEMS_GPIO_PULLDOWN
[PATCH v6 06/10] bsps/arm/stm32f4: Make bspstart use HAL
This patch changes bspstart to use HAL for clock and sysyem
initialization.
---
bsps/arm/stm32f4/start/bspstart.c | 199 --
1 file changed, 186 insertions(+), 13 deletions(-)
diff --git a/bsps/arm/stm32f4/start/bspstart.c
b/bsps/arm/stm32f4/start/bspstart.c
index 0ec5ac27b5..2297430844 100644
--- a/bsps/arm/stm32f4/start/bspstart.c
+++ b/bsps/arm/stm32f4/start/bspstart.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ * Copyright (c) 2022 Duc Doan (dtbpkmte at gmail.com).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -7,15 +8,23 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+#ifndef __rtems__
#include
+#endif /* __rtems__ */
+#ifdef __rtems__
+#include
+#include
+#endif /* __rtems__ */
#ifdef STM32F4_FAMILY_F4
+#ifndef __rtems__
#include
#include
@@ -24,28 +33,191 @@ static rtems_status_code set_system_clk(
uint32_t hse_clk,
uint32_t hse_flag
);
+#endif /* __rtems__ */
+
+#ifdef __rtems__
+/* Get number of milliseconds elapsed since startup */
+uint32_t HAL_GetTick(void)
+{
+ return rtems_clock_get_ticks_since_boot() *
+rtems_configuration_get_milliseconds_per_tick();
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+static void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state
*/
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+static rtems_status_code SystemClock_Config(void)
+{
+/** Configure the main internal regulator output voltage
+*/
+__HAL_RCC_PWR_CLK_ENABLE();
+__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+uint32_t use_hse = STM32F4_USE_HSE, sys_clk = STM32F4_SYSCLK / 100L,
hse_clk = STM32F4_HSE_FREQUENCY / 100L, src_clk;
+uint32_t sys_clk_src;
+uint32_t flash_latency = FLASH_LATENCY_0;
+uint32_t pll_m = 0, pll_n = 0, pll_p = 0, pll_q = 0;
+uint32_t apbpre1 = 0, apbpre2 = 0;
+
+if (sys_clk == 16 && hse_clk != 16) {
+sys_clk_src = RCC_SYSCLKSOURCE_HSI;
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+flash_latency = FLASH_LATENCY_0;
+} else if (sys_clk == hse_clk) {
+sys_clk_src = RCC_SYSCLKSOURCE_HSE;
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+flash_latency = FLASH_LATENCY_0;
+} else {
+sys_clk_src = RCC_SYSCLKSOURCE_PLLCLK;
+if (sys_clk > 180) {
+return RTEMS_INVALID_NUMBER;
+} else if (sys_clk >= 96) {
+pll_n = sys_clk << 1;
+pll_p = RCC_PLLP_DIV2;
+} else if (sys_clk >= 48) {
+pll_n = sys_clk << 2;
+pll_p = RCC_PLLP_DIV4;
+} else if (sys_clk >= 24) {
+pll_n = sys_clk << 3;
+pll_p = RCC_PLLP_DIV8;
+} else {
+return RTEMS_INVALID_NUMBER;
+}
+
+if (hse_clk == 0 || use_hse == 0) {
+src_clk = 16;
+use_hse = 0;
+} else {
+src_clk = hse_clk;
+}
+
+pll_m = src_clk;
+
+pll_q = ((long) (src_clk * pll_n)) / pll_m / 48;
+if (pll_q < 2) {
+pll_q = 2;
+}
+
+/* APB1 prescaler, APB1 clock must be < 42MHz */
+apbpre1 = (sys_clk * 100) / 42;
+
+if ( apbpre1 <= 100 ) {
+apbpre1 = RCC_HCLK_DIV1;
+} else if (apbpre1 <= 200) {
+apbpre1 = RCC_HCLK_DIV2;
+} else if (apbpre1 <= 400) {
+apbpre1 = RCC_HCLK_DIV4;
+} else if (apbpre1 <= 800) {
+apbpre1 = RCC_HCLK_DIV8;
+} else if (apbpre1) {
+apbpre1 = RCC_HCLK_DIV16;
+}
+
+/* APB2 prescaler, APB2 clock must be < 84MHz */
+apbpre2 = (sys_clk * 100) / 84;
+
+if (apbpre2 <= 100) {
+apbpre2 = RCC_HCLK_DIV1;
+} else if (apbpre2 <= 200) {
+apbpre2 = RCC_HCLK_DIV2;
+} else if (apbpre2 <= 400) {
+apbpre2 = RCC_HCLK_DIV4;
+} else if (apbpre2 <= 800) {
+apbpre2 = RCC_HCLK_DIV8;
+} else {
+apbpre2 = RCC_HCLK_DIV16;
+}
+
+if (use_hse) {
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+} else {
[PATCH v6 05/10] bsps/arm/stm32f4: Add HAL to build
/hal/stm32f4xx_ll_gpio.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_i2c.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_lptim.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_pwr.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_rcc.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_rng.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_rtc.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_sdmmc.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_spi.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_tim.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_usart.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_usb.c
+- bsps/arm/stm32f4/hal/stm32f4xx_ll_utils.c
+- bsps/arm/stm32f4/hal/system_stm32f4xx.c
- bsps/arm/shared/irq/irq-armv7m.c
- bsps/arm/shared/irq/irq-dispatch-armv7m.c
- bsps/arm/shared/start/bsp-start-memcpy.S
diff --git a/spec/build/bsps/arm/stm32f4/optenhal.yml
b/spec/build/bsps/arm/stm32f4/optenhal.yml
new file mode 100644
index 00..3c1599a3d6
--- /dev/null
+++ b/spec/build/bsps/arm/stm32f4/optenhal.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+default: true
+default-by-variant: []
+description: |
+ Use HAL driver
+enabled-by: true
+format: '{}'
+links: []
+name: USE_HAL_DRIVER
+type: build
diff --git a/spec/build/bsps/arm/stm32f4/opthse.yml
b/spec/build/bsps/arm/stm32f4/opthse.yml
new file mode 100644
index 00..d63f9e81a0
--- /dev/null
+++ b/spec/build/bsps/arm/stm32f4/opthse.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+default: 800
+default-by-variant: []
+description: |
+ HSE frequency in Hz
+enabled-by: true
+format: '{}'
+links: []
+name: STM32F4_HSE_FREQUENCY
+type: build
diff --git a/spec/build/bsps/arm/stm32f4/optusehse.yml
b/spec/build/bsps/arm/stm32f4/optusehse.yml
new file mode 100644
index 00..192232f294
--- /dev/null
+++ b/spec/build/bsps/arm/stm32f4/optusehse.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+default: 0
+default-by-variant: []
+description: |
+ Use HSI for PLL by default, set it to 1 to use HSE for PLL.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32F4_USE_HSE
+type: build
diff --git a/spec/build/bsps/arm/stm32f4/optvariant.yml
b/spec/build/bsps/arm/stm32f4/optvariant.yml
new file mode 100644
index 00..f2583c5b95
--- /dev/null
+++ b/spec/build/bsps/arm/stm32f4/optvariant.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+actions:
+- get-string: null
+- script: |
+variants = ["STM32F405xx", "STM32F415xx", "STM32F407xx", "STM32F417xx",
"STM32F427xx", "STM32F437xx", "STM32F429xx", "STM32F439xx", "STM32F401xC",
"STM32F401xE", "STM32F410Tx", "STM32F410Rx", "STM32F411xE", "STM32F446xx",
"STM32F469xx", "STM32F479xx", "STM32F412Cx", "STM32F412Rx", "STM32F412Vx",
"STM32F413xx", "STM32F423xx"]
+if value not in variants:
+conf.fatal(
+"STM32F4 chip variant '{}' is not one of {}".format(
+value, variants
+)
+)
+conf.define_cond(value, True)
+build-type: option
+default: STM32F407xx
+default-by-variant: []
+enabled-by: true
+format: '{}'
+links: []
+name: STM32F4_VARIANT
+description: |
+ Select the STM32F4 series chip variant out of STM32F405xx, STM32F415xx,
STM32F407xx, STM32F417xx, STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx,
STM32F401xC, STM32F401xE, STM32F410Tx, STM32F410Rx, STM32F411xE, STM32F446xx,
STM32F469xx, STM32F479xx, STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F413xx,
and STM32F423xx.
+type: build
--
2.37.1
___
devel mailing list
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[PATCH v6 04/10] bsps/arm/stm32f4: Include STM32F4 HAL
This patch adds STM32F4 HAL files taken from ST's repository at: https://github.com/STMicroelectronics/STM32CubeF4, Release v1.27.1, commit 52757b5e33259a088509a777a9e3a5b971194c7d. The device headers are copied from Drivers/CMSIS/Device/ST/STM32F4xx/Include. The HAL and LL files are copied from Drivers/STM32F4xx_HAL_Driver/Inc. The HAL and LL source files are copied from: Drivers/STM32F4xx_HAL_Driver/Src. Due to great size, I cannot send the patch via email. Please find it at https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/b8aeedfe8cfecf248b279e846d11080f9511910b --- .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 + .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 + bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 +
[PATCH v6 00/10] New GPIO, ADC API and STM32F4 BSP implementation
Dear all, These patches are to address the issues in my previous versions. These include GPIO API, ADC API and STM32F4 BSP implementation for them. My repository is at: https://github.com/dtbpkmte/GSoC-2022-RTEMS (master branch). The sample application code for these APIs can be found at: https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. STM32F4 HAL source code is taken from ST's repo at: https://github.com/STMicroelectronics/STM32CubeF4.git (Commit ID: 52757b5, Release v1.27.1). v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM v3: - Removed rtems_gpio_begin() - bsp_gpio_register_controllers() now needs to be called from hook1 (can be configured by option STM32F4_ENABLE_GENERIC_GPIO) - Updated license text for API files and STM32F4 GPIO files v4: - Fixed GPIO port guards - Fixed potential memory-leak bug of STM32F4 GPIO interrupt system - Added comments to STM32F4 GPIO functions and made them extern v5: - Replace old HAL source code with the one from official repository to remove CRLF - Added a peripherals API, which is a framework to add more APIs that operates on a GPIO pin - Changed GPIO API to comply with the peripherals API - Changed ADC API to comply with the peripherals API - Changed STM32F4 implementation v6: - Split commits that add CMSIS and HAL - Removed peripheral API - Changed ADC API: this is now separate from GPIO API Duc Doan (10): bsps/arm: Convert CMSIS files from CRLF to LF bsps/arm: Changed CMSIS files to v5 build/bsps/arm: Add new CMSIS files v5 to build bsps/arm/stm32f4: Include STM32F4 HAL bsps/arm/stm32f4: Add HAL to build bsps/arm/stm32f4: Make bspstart use HAL bsps: Add GPIO API bsps/arm/stm32f4: GPIO Implementation bsps: Add ADC API bsps/arm/stm32f4: ADC API implementation bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 3460 +-- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 524 +- bsps/arm/include/core_cm7.h | 5186 ++-- bsps/arm/include/core_cmFunc.h| 172 +- bsps/arm/include/core_cmInstr.h | 174 +- bsps/arm/include/core_cmSimd.h| 192 +- bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/adc/adc.c| 495 + bsps/arm/stm32f4/gpio/gpio.c | 557 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4
Re: [PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Sat, 2022-07-30 at 22:19 +0200, o...@c-mauderer.de wrote: > > > > Am 30.07.22 um 21:41 schrieb Karel Gardas: > > On 7/30/22 16:32, o...@c-mauderer.de wrote: > > > > bsps/arm/include/cmsis_compiler.h | 266 + > > > > bsps/arm/include/cmsis_gcc.h | 3460 +-- > > > > bsps/arm/include/cmsis_version.h | 39 + > > > > bsps/arm/include/core_cm4.h | 524 +- > > > > bsps/arm/include/core_cm7.h | 5186 ++-- > > > > bsps/arm/include/mpu_armv7.h | 270 + > > > > > > Are the cmsis files from the same source or directly from ARM? > > > > > > The cmsis_gcc.h has a lot of changes compared to the earlier > > > version > > > that has been present in RTEMS. A lot of the changes seem to be > > > whitespace changes. Can these be avoided somehow (for example by > > > using > > > dos2unix before overwriting the file)? > > > > > > In the discord chat there was one suggestion from Ho Kaido to > > > move the > > > files one level down and make them BSP specific. I'm not sure > > > whether > > > I'm for or against that idea. Advantage is that it makes BSPs > > > independant from each other. Disadvantage is that it duplicates > > > code. > > > > > > I think I would try to avoid moving them down due to the code > > > duplication but it raises the question: Which BSPs use the files > > > too > > > and did you try whether they still compile after the upgrade? > > > > We have had this dicussion with Duc on discord IIRC when he > > started. He > > needed new CMSIS (v5) version due to new HAL which Duc claims > > depends on > > them. I have not verified that claim personally. > > > > New CMSIS v5 brings obviously: > > > > - by ARM maintained code (v4 is unmaintained IIRC) > > > > but also: > > > > - license change from BSD to Apache-2 > > > > At that time I've told Duc to continue with the code and not to > > worry > > about license changes -- as this would be longer discussion anyway. > > Not > > sure, but IIRC he also wrote to Sebastian asking for clarification > > -- > > well, not sure about that. Certainly IIRC I suggested that. > > > > Anyway, I took Duc code and try H7 BSPs and to my surprise they > > compiles > > more or less all without any compilation related issue. Well, I've > > not > > tried M4 variants. So far I've not run full tester on this. I'll, > > but > > first I'd like to test his API if it's possible to also use with > > H7. > > > > BTW: if RTEMS prefer old unmaintained BSD-3 ARM CSMIS code, then > > it's > > perhaps possible to go in F4 HAL history back and grab just the > > three > > with the v4 dependency. On the other hand, for ARM Apache-2 seems > > to be > > the way forward and for some ST.com depended code too -- so I guess > > RTEMS project will need to live with that fact somehow. > > > > Thanks, > > Karel > > > > Hello Karel, > > thanks for the clarification. I have to be honest: I missed the > license > change. That is a bit of a difficult one and will cause a discussion. > @Duc: We need a new LICENSE file in the top level that represents > that. Maybe split the CMSIS update into a separate patch so that it > is > clear why there is a new license file (if the license is only for the > CMSIS and not for the STM HAL too). > Do you mean I need to add a LICENSE.Apache-2.0 file in rtems source root? I found this file being shipped with STM HAL: https://github.com/STMicroelectronics/STM32CubeF4/blob/master/Drivers/CMSIS/LICENSE.txt Should I copy this file and rename it to LICENSE.Apache-2.0? Best, Duc > But my main concern was another one: Which BSPs use the CMSIS files? > Beneath the stm32 variants, that's at least the atsam and imxrt. > Maybe I > missed some more. We should at least make sure that these BSPs are > compile-clean with the updated cmsis headers. > > Best regards > > Christian ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Tue, 2022-08-02 at 07:26 +0200, Christian MAUDERER wrote: > That page most likely ignores line endings. Try it with `file` or > `dos2unix -i`: > > > sh> git co master > [...] > sh> file bsps/arm/include/cmsis_gcc.h > bsps/arm/include/cmsis_gcc.h: C source, ASCII text, with CRLF, LF > line > terminators > sh> dos2unix -i bsps/arm/include/cmsis_gcc.h > 1374 1 0 no_bom text > bsps/arm/include/cmsis_gcc.h > sh> git co duc/master > [...] > sh> file bsps/arm/include/cmsis_gcc.h > bsps/arm/include/cmsis_gcc.h: C source, ASCII text > sh> dos2unix -i bsps/arm/include/cmsis_gcc.h > 0 2085 0 no_bom text > bsps/arm/include/cmsis_gcc.h > sh> > > > The three numbers of dos2unix output is (in this order): Number of > DOS > line endings, number of UNIX line endings, number of MAC line > endings. > > So line endings changed from CRLF to only LF. Either make that two > steps > (first changing the old one to LF in one commit and then updating it > in > another) or change the new file to use the CRLF format of the old > one. > > Best regards > > Christian > > Thank you, this knowledge is new to me. I will change them to LF. Best, Duc ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v5 2/4] bsps: New GPIO API & peripherals API framework
Hello Christian, On Mon, 2022-08-01 at 20:29 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > Am 01.08.22 um 05:50 schrieb Duc Doan: > > Hello Christian, > > > > On Sat, 2022-07-30 at 17:50 +0200, o...@c-mauderer.de wrote: > > > Hello Duc, > > > > > > Am 24.07.22 um 14:01 schrieb Duc Doan: > > > > --- > > > > bsps/include/bsp/gpio2.h | 528 > > > > > > > > bsps/include/bsp/periph_api.h | 142 +++ > > > > bsps/shared/dev/gpio/gpio.c | 212 ++ > > > > bsps/shared/dev/periph_api/periph_api.c | 101 + > > > > spec/build/bsps/obj.yml | 4 +- > > > > 5 files changed, 986 insertions(+), 1 deletion(-) > > > > create mode 100644 bsps/include/bsp/gpio2.h > > > > create mode 100644 bsps/include/bsp/periph_api.h > > > > create mode 100644 bsps/shared/dev/gpio/gpio.c > > > > create mode 100644 bsps/shared/dev/periph_api/periph_api.c > > > > > > > > diff --git a/bsps/include/bsp/gpio2.h > > > > b/bsps/include/bsp/gpio2.h > > > > > > I'm not really happy with the "2" in the name. But at the moment > > > I > > > don't > > > have a much better idea either. But if you call it "gpio2", you > > > should > > > call the C files "gpio2" too. Maybe "dev/gpio/gpio.h" similar to > > > the > > > "dev/i2c/i2c.h"? > > > > > > > I will rename the C file to "gpio2.c" for now. > > > > > > new file mode 100644 > > > > index 00..9cb1c720ab > > > > --- /dev/null > > > > +++ b/bsps/include/bsp/gpio2.h > > > > @@ -0,0 +1,528 @@ > > > > +/* SPDX-License-Identifier: BSD-2-Clause */ > > > > + > > > > > > Your file is missing some general doxygen group information. Take > > > a > > > look > > > at for example bsps/include/ofw/ofw.h. > > > > > > > Thanks for the reminder, I will add that. > > > > > > +/* > > > > + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) > > > > + * > > > > + * Redistribution and use in source and binary forms, with or > > > > without > > > > + * modification, are permitted provided that the following > > > > conditions > > > > + * are met: > > > > + * 1. Redistributions of source code must retain the above > > > > copyright > > > > + * notice, this list of conditions and the following > > > > disclaimer. > > > > + * 2. Redistributions in binary form must reproduce the above > > > > copyright > > > > + * notice, this list of conditions and the following > > > > disclaimer > > > > in the > > > > + * documentation and/or other materials provided with the > > > > distribution. > > > > + * > > > > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND > > > > CONTRIBUTORS "AS IS" > > > > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > > > > LIMITED TO, THE > > > > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A > > > > PARTICULAR PURPOSE > > > > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR > > > > CONTRIBUTORS BE > > > > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, > > > > EXEMPLARY, OR > > > > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, > > > > PROCUREMENT OF > > > > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR > > > > PROFITS; OR > > > > BUSINESS > > > > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF > > > > LIABILITY, > > > > WHETHER IN > > > > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE > > > > OR > > > > OTHERWISE) > > > > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF > > > > ADVISED OF THE > > > > + * POSSIBILITY OF SUCH DAMAGE. > > > > + */ > > > > + > > > > +#ifndef LIBBSP_BSP_GPIO2_H > > > > +#define LIBBSP_BSP_GPIO2_H > > > > + > > > > +#include > > > > +#include > > > > + > > > > +/** > > > > + * Configure the maximum number of GPIO
Re: [PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Mon, 2022-08-01 at 20:32 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > Am 01.08.22 um 04:13 schrieb Duc Doan: > > Hello Christian, > > > > On Sun, 2022-07-31 at 20:01 +0200, o...@c-mauderer.de wrote: > > > Hello Duc, > > > > > > Am 31.07.22 um 17:07 schrieb Duc Doan: > > > > Hello Christian, > > > > > > > > On Sat, 2022-07-30 at 16:32 +0200, o...@c-mauderer.de wrote: > > > > > Hello Duc, > > > > > > > > > > general note for the patch: Please write in the commit > > > > > message > > > > > where > > > > > you > > > > > got the sources from. That can be a link to a github repo > > > > > including a > > > > > commit ID or a link to the zip file from ST (including a > > > > > date, > > > > > version > > > > > or similar information). If you moved some stuff around > > > > > compared > > > > > to > > > > > the > > > > > original structure: Please describe about what you did. For > > > > > example > > > > > in > > > > > the imxrt I just added the cp commands that I used: > > > > > > > > > > > > > > > https://git.rtems.org/rtems/commit/bsps/arm/imxrt?id=48f6a6c302a3e1a3f8915e2503d0fe618d1af285 > > > > > > > > > > Not the best solution but at least someone else can find out > > > > > roughly > > > > > what I did. > > > > > > > > > > > > > Ah yes, I will do that. I thought I only needed to put the > > > > description > > > > in the email before. > > > > > > > > > Am 24.07.22 um 14:01 schrieb Duc Doan: > > > > > > This patch is too large so I cannot send via email. Please > > > > > > find > > > > > > it > > > > > > here: > > > > > > https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/6f1fbc7dd7a5e0877d8bff11e1b21558928dbc16 > > > > > > > > > > > > --- > > > > > > .gitignore | 1 + > > > > > > > > > > You added a "patches" directory to the gitignore. That looks > > > > > like > > > > > a > > > > > change that is specific to your method of working. These kind > > > > > of > > > > > changes > > > > > should normall not be pushed. > > > > > > > > > > If you want to ignore stuff specific to your work > > > > > environment, I > > > > > recommend to use a global .gitignore file. Git has a > > > > > "core.excludesfile" > > > > > config for that. > > > > > > > > > > > > > Thanks for the suggestion, I will fix that. > > > > > > > > > > bsps/arm/include/cmsis_compiler.h | 266 + > > > > > > bsps/arm/include/cmsis_gcc.h | 3460 > > > > > > +-- > > > > > > bsps/arm/include/cmsis_version.h | 39 + > > > > > > bsps/arm/include/core_cm4.h | 524 > > > > > > +- > > > > > > bsps/arm/include/core_cm7.h | 5186 > > > > > > ++-- > > > > > > bsps/arm/include/mpu_armv7.h | 270 + > > > > > > > > > > Are the cmsis files from the same source or directly from > > > > > ARM? > > > > > > > > > > > > > They are from the same source (STM HAL v1.27.1). > > > > > > > > > The cmsis_gcc.h has a lot of changes compared to the earlier > > > > > version > > > > > that has been present in RTEMS. A lot of the changes seem to > > > > > be > > > > > whitespace changes. Can these be avoided somehow (for example > > > > > by > > > > > using > > > > > dos2unix before overwriting the file)? > > > > > > > > > > > > > From what I've just read about dos2unix, it converts line > > > > breaks > > > > from > > > > CRLF to LF (please correct me if I'm wrong). How will this > > > > command > > > > resolve t
Re: [PATCH v5 2/4] bsps: New GPIO API & peripherals API framework
Hello Christian, On Sat, 2022-07-30 at 17:50 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > Am 24.07.22 um 14:01 schrieb Duc Doan: > > --- > > bsps/include/bsp/gpio2.h | 528 > > > > bsps/include/bsp/periph_api.h | 142 +++ > > bsps/shared/dev/gpio/gpio.c | 212 ++ > > bsps/shared/dev/periph_api/periph_api.c | 101 + > > spec/build/bsps/obj.yml | 4 +- > > 5 files changed, 986 insertions(+), 1 deletion(-) > > create mode 100644 bsps/include/bsp/gpio2.h > > create mode 100644 bsps/include/bsp/periph_api.h > > create mode 100644 bsps/shared/dev/gpio/gpio.c > > create mode 100644 bsps/shared/dev/periph_api/periph_api.c > > > > diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h > > I'm not really happy with the "2" in the name. But at the moment I > don't > have a much better idea either. But if you call it "gpio2", you > should > call the C files "gpio2" too. Maybe "dev/gpio/gpio.h" similar to the > "dev/i2c/i2c.h"? > I will rename the C file to "gpio2.c" for now. > > new file mode 100644 > > index 00..9cb1c720ab > > --- /dev/null > > +++ b/bsps/include/bsp/gpio2.h > > @@ -0,0 +1,528 @@ > > +/* SPDX-License-Identifier: BSD-2-Clause */ > > + > > Your file is missing some general doxygen group information. Take a > look > at for example bsps/include/ofw/ofw.h. > Thanks for the reminder, I will add that. > > +/* > > + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) > > + * > > + * Redistribution and use in source and binary forms, with or > > without > > + * modification, are permitted provided that the following > > conditions > > + * are met: > > + * 1. Redistributions of source code must retain the above > > copyright > > + * notice, this list of conditions and the following > > disclaimer. > > + * 2. Redistributions in binary form must reproduce the above > > copyright > > + * notice, this list of conditions and the following disclaimer > > in the > > + * documentation and/or other materials provided with the > > distribution. > > + * > > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND > > CONTRIBUTORS "AS IS" > > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > > LIMITED TO, THE > > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A > > PARTICULAR PURPOSE > > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR > > CONTRIBUTORS BE > > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, > > EXEMPLARY, OR > > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, > > PROCUREMENT OF > > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR > > BUSINESS > > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, > > WHETHER IN > > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR > > OTHERWISE) > > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF > > ADVISED OF THE > > + * POSSIBILITY OF SUCH DAMAGE. > > + */ > > + > > +#ifndef LIBBSP_BSP_GPIO2_H > > +#define LIBBSP_BSP_GPIO2_H > > + > > +#include > > +#include > > + > > +/** > > + * Configure the maximum number of GPIO controllers used in > > + * a application. > > + * > > + * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be > > + * defined in application code. If it is not defined, > > + * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's > > + * number of controllers is not defined, it will default > > + * to 1. > > + */ > > +#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS > > How do you manage that the CONFIGURE_GPIO_MAXIMUM_CONTROLLERS from > the > application is visible here? > I forgot to remove this CONFIGURE_GPIO_MAXIMUM_CONTROLLERS thing. At first I wanted to do something like confdef but couldn't, so I changed to use BSP_GPIO_NUM_CONTROLLERS, which is a build option. I will delete that code. However, if you have a document about how confdef works, it would be helpful for me and I may be able to make that CONFIGURE_GPIO_MAXIMUM_CONTROLLERS work. > > + > > +#ifndef BSP_GPIO_NUM_CONTROLLERS > > +#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1 > > +#else > > +#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS > > BSP_GPIO_NUM_CONTROLLERS > > +#endif /* BSP_GPIO_NUM_CONTROLLERS */ > > + > > +#endif /* CONFIGURE_GPIO_MAXIMU
Re: [PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Sun, 2022-07-31 at 20:01 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > Am 31.07.22 um 17:07 schrieb Duc Doan: > > Hello Christian, > > > > On Sat, 2022-07-30 at 16:32 +0200, o...@c-mauderer.de wrote: > > > Hello Duc, > > > > > > general note for the patch: Please write in the commit message > > > where > > > you > > > got the sources from. That can be a link to a github repo > > > including a > > > commit ID or a link to the zip file from ST (including a date, > > > version > > > or similar information). If you moved some stuff around compared > > > to > > > the > > > original structure: Please describe about what you did. For > > > example > > > in > > > the imxrt I just added the cp commands that I used: > > > > > > > > > https://git.rtems.org/rtems/commit/bsps/arm/imxrt?id=48f6a6c302a3e1a3f8915e2503d0fe618d1af285 > > > > > > Not the best solution but at least someone else can find out > > > roughly > > > what I did. > > > > > > > Ah yes, I will do that. I thought I only needed to put the > > description > > in the email before. > > > > > Am 24.07.22 um 14:01 schrieb Duc Doan: > > > > This patch is too large so I cannot send via email. Please find > > > > it > > > > here: > > > > https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/6f1fbc7dd7a5e0877d8bff11e1b21558928dbc16 > > > > > > > > --- > > > > .gitignore | 1 + > > > > > > You added a "patches" directory to the gitignore. That looks like > > > a > > > change that is specific to your method of working. These kind of > > > changes > > > should normall not be pushed. > > > > > > If you want to ignore stuff specific to your work environment, I > > > recommend to use a global .gitignore file. Git has a > > > "core.excludesfile" > > > config for that. > > > > > > > Thanks for the suggestion, I will fix that. > > > > > > bsps/arm/include/cmsis_compiler.h | 266 + > > > > bsps/arm/include/cmsis_gcc.h | 3460 +-- > > > > bsps/arm/include/cmsis_version.h | 39 + > > > > bsps/arm/include/core_cm4.h | 524 +- > > > > bsps/arm/include/core_cm7.h | 5186 ++-- > > > > bsps/arm/include/mpu_armv7.h | 270 + > > > > > > Are the cmsis files from the same source or directly from ARM? > > > > > > > They are from the same source (STM HAL v1.27.1). > > > > > The cmsis_gcc.h has a lot of changes compared to the earlier > > > version > > > that has been present in RTEMS. A lot of the changes seem to be > > > whitespace changes. Can these be avoided somehow (for example by > > > using > > > dos2unix before overwriting the file)? > > > > > > > From what I've just read about dos2unix, it converts line breaks > > from > > CRLF to LF (please correct me if I'm wrong). How will this command > > resolve the whitespace changes? > > I haven't looked at the exact type of whitespace changes. I had the > impression that the difference is most likely only the line ending. > It > didn't look like tab / space issue. Is it a tab / space issue? > I've looked at the some files and noticed that the difference is mostly additional code/code change (e.g. adding support for ARMv8), but not whitespace changes. > > > > > In the discord chat there was one suggestion from Ho Kaido to > > > move > > > the > > > files one level down and make them BSP specific. I'm not sure > > > whether > > > I'm for or against that idea. Advantage is that it makes BSPs > > > independant from each other. Disadvantage is that it duplicates > > > code. > > > > > > I think I would try to avoid moving them down due to the code > > > duplication but it raises the question: Which BSPs use the files > > > too > > > and > > > did you try whether they still compile after the upgrade? > > > > > > > Until now I only know of STM32H7 BSP that is using the CMSIS files. > > I > > tried compiling it before and Karel also confirmed that the BSP > > compiles. > > Just as an example: core_cm4/7.h is included at least in
Re: [PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Sat, 2022-07-30 at 16:32 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > general note for the patch: Please write in the commit message where > you > got the sources from. That can be a link to a github repo including a > commit ID or a link to the zip file from ST (including a date, > version > or similar information). If you moved some stuff around compared to > the > original structure: Please describe about what you did. For example > in > the imxrt I just added the cp commands that I used: > > > https://git.rtems.org/rtems/commit/bsps/arm/imxrt?id=48f6a6c302a3e1a3f8915e2503d0fe618d1af285 > > Not the best solution but at least someone else can find out roughly > what I did. > Ah yes, I will do that. I thought I only needed to put the description in the email before. > Am 24.07.22 um 14:01 schrieb Duc Doan: > > This patch is too large so I cannot send via email. Please find it > > here: > > https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/6f1fbc7dd7a5e0877d8bff11e1b21558928dbc16 > > > > --- > > .gitignore | 1 + > > You added a "patches" directory to the gitignore. That looks like a > change that is specific to your method of working. These kind of > changes > should normall not be pushed. > > If you want to ignore stuff specific to your work environment, I > recommend to use a global .gitignore file. Git has a > "core.excludesfile" > config for that. > Thanks for the suggestion, I will fix that. > > bsps/arm/include/cmsis_compiler.h | 266 + > > bsps/arm/include/cmsis_gcc.h | 3460 +-- > > bsps/arm/include/cmsis_version.h | 39 + > > bsps/arm/include/core_cm4.h | 524 +- > > bsps/arm/include/core_cm7.h | 5186 ++-- > > bsps/arm/include/mpu_armv7.h | 270 + > > Are the cmsis files from the same source or directly from ARM? > They are from the same source (STM HAL v1.27.1). > The cmsis_gcc.h has a lot of changes compared to the earlier version > that has been present in RTEMS. A lot of the changes seem to be > whitespace changes. Can these be avoided somehow (for example by > using > dos2unix before overwriting the file)? > From what I've just read about dos2unix, it converts line breaks from CRLF to LF (please correct me if I'm wrong). How will this command resolve the whitespace changes? > In the discord chat there was one suggestion from Ho Kaido to move > the > files one level down and make them BSP specific. I'm not sure whether > I'm for or against that idea. Advantage is that it makes BSPs > independant from each other. Disadvantage is that it duplicates code. > > I think I would try to avoid moving them down due to the code > duplication but it raises the question: Which BSPs use the files too > and > did you try whether they still compile after the upgrade? > Until now I only know of STM32H7 BSP that is using the CMSIS files. I tried compiling it before and Karel also confirmed that the BSP compiles. > > > .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c | 1679 ++ > > .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c | 2307 ++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c | 4423 > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c | 2126 ++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ > > bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c | 775 + > > bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + > > .
[PATCH 1/1] bsps/stm32f4: Fix usart_write_polled()
---
bsps/arm/stm32f4/console/console-config.c | 4 +++-
bsps/arm/stm32f4/console/usart.c | 6 ++
bsps/arm/stm32f4/include/bsp/usart.h | 3 +++
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/bsps/arm/stm32f4/console/console-config.c
b/bsps/arm/stm32f4/console/console-config.c
index 13557ed186..43c82144b0 100644
--- a/bsps/arm/stm32f4/console/console-config.c
+++ b/bsps/arm/stm32f4/console/console-config.c
@@ -83,7 +83,9 @@ console_tbl Console_Configuration_Ports [] = {
},
#endif
};
-
+#ifdef __rtems__
+console_tbl *stm32f4_default_console_tbl_ptr = _Configuration_Ports[0];
+#endif /* __rtems__ */
#define PORT_COUNT \
(sizeof(Console_Configuration_Ports) \
/ sizeof(Console_Configuration_Ports [0]))
diff --git a/bsps/arm/stm32f4/console/usart.c b/bsps/arm/stm32f4/console/usart.c
index 37566ef9d7..706ab9d9f0 100644
--- a/bsps/arm/stm32f4/console/usart.c
+++ b/bsps/arm/stm32f4/console/usart.c
@@ -165,8 +165,14 @@ static int usart_read_polled(int minor)
static void usart_write_polled(int minor, char c)
{
+#ifndef __rtems__
const console_tbl *ct = Console_Port_Tbl [minor];
volatile stm32f4_usart *usart = usart_get_regs(ct);
+#endif /* __rtems__ */
+#ifdef __rtems__
+ const console_tbl *ct = stm32f4_default_console_tbl_ptr;
+ volatile stm32f4_usart *usart = usart_get_regs(ct);
+#endif /* __rtems__ */
while ((usart->sr & STM32F4_USART_SR_TXE) == 0) {
/* Wait */
diff --git a/bsps/arm/stm32f4/include/bsp/usart.h
b/bsps/arm/stm32f4/include/bsp/usart.h
index 3c9fd3fd96..3ac8fce583 100644
--- a/bsps/arm/stm32f4/include/bsp/usart.h
+++ b/bsps/arm/stm32f4/include/bsp/usart.h
@@ -29,6 +29,9 @@ extern "C" {
#endif /* __cplusplus */
extern const console_fns stm32f4_usart_fns;
+#ifdef __rtems__
+extern console_tbl *stm32f4_default_console_tbl_ptr;
+#endif /* __rtems__ */
/** @} */
--
2.37.1
___
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[PATCH 0/1] *** bsps/stm32f4: Fix simple console driver bug ***
The console does not work for applications that use simple console driver, including testsuites applications. The reason is that Console_Port_Tbl is NULL, which causes a fatal error when trying to get the console_tbl and usart instance. This patch fixes that by making usart_write_polled use a default console_tbl instead of a value from Console_Port_Tbl. This default instance is the USART with smallest number that is enabled (the first element in Console_Configuration_Ports). Duc Doan (1): bsps/stm32f4: Fix usart_write_polled() bsps/arm/stm32f4/console/console-config.c | 4 +++- bsps/arm/stm32f4/console/usart.c | 6 ++ bsps/arm/stm32f4/include/bsp/usart.h | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) -- 2.37.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
GSoC 2022 - Midterm Deliverables - Duc Doan
Dear mentors and RTEMS community, This email is to announce the deliverables I have for phase 1 of GSoC 2022. Please find my midterm blog post at: https://medium.com/@dtbpkmte/gsoc-2022-rtems-midterm-report-cdc994459362 (this includes the links to my repositories and code documentations). My code is submitted to devel mailing list. The newest version is v5. Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v4 3/7] bsps: Add GPIO API
Hello, On Mon, 2022-07-25 at 11:42 +1000, Chris Johns wrote: > On 23/7/2022 1:53 pm, Duc Doan wrote: > > This is the new GPIO API. The header file is > > gpio2.h. > > --- > > bsps/include/bsp/gpio2.h | 526 > > > > bsps/shared/dev/gpio/gpio.c | 189 + > > spec/build/bsps/obj.yml | 2 +- > > 3 files changed, 716 insertions(+), 1 deletion(-) > > create mode 100644 bsps/include/bsp/gpio2.h > > create mode 100644 bsps/shared/dev/gpio/gpio.c > > > > diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h > > new file mode 100644 > > index 00..e4a106da8b > > --- /dev/null > > +++ b/bsps/include/bsp/gpio2.h > > @@ -0,0 +1,526 @@ > > +/** > > + * @file > > + * > > + * @ingroup rtems_gpio2 > > + * > > + * @brief RTEMS GPIO new API definition. > > + */ > > + > > +/* > > +* Copyright (c) 2022 Duc Doan > > +* > > +* The license and distribution terms for this file may be > > +* found in the file LICENSE in this distribution or at > > +* http://www.rtems.org/license/LICENSE. > > Please consider using the BSD license. > > Chris This is fixed in my v5 patch set. Best, Duc ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v5 4/4] bsps/stm32f4: Implementation for GPIO and ADC
---
bsps/arm/stm32f4/adc/adc.c| 655 ++
bsps/arm/stm32f4/gpio/gpio.c | 542 +++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_adc.h| 209 ++
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 273
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/include/bsp/stm32f4_periph.h | 50 ++
bsps/arm/stm32f4/start/bspstart.c | 7 +-
bsps/arm/stm32f4/start/bspstarthook.c | 8 +
bsps/arm/stm32f4/start/periph.c | 58 ++
spec/build/bsps/arm/stm32f4/grp.yml | 6 +-
spec/build/bsps/arm/stm32f4/obj.yml | 5 +
spec/build/bsps/arm/stm32f4/optengpio.yml | 16 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
14 files changed, 1856 insertions(+), 10 deletions(-)
create mode 100644 bsps/arm/stm32f4/adc/adc.c
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_adc.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_periph.h
create mode 100644 bsps/arm/stm32f4/start/periph.c
create mode 100644 spec/build/bsps/arm/stm32f4/optengpio.yml
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/adc/adc.c b/bsps/arm/stm32f4/adc/adc.c
new file mode 100644
index 00..21baa9ee2c
--- /dev/null
+++ b/bsps/arm/stm32f4/adc/adc.c
@@ -0,0 +1,655 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+
+#if defined(ADC3)
+#define NUM_ADC 3
+#elif defined(ADC2)
+#define NUM_ADC 2
+#else
+#define NUM_ADC 1
+#endif
+
+/** Interrupt manager */
+typedef struct {
+void *arg;
+stm32f4_gpio *gpio;
+} stm32f4_interrupt_arg;
+
+typedef struct {
+stm32f4_interrupt_arg arg;
+rtems_gpio_isr isr;
+} stm32f4_interrupt;
+
+void adc_irq_handler(void *arg);
+
+static stm32f4_interrupt isr_table[NUM_ADC];
+
+/**
+ * This tells if there is already an ISR registered at each
+ * table index (element set to true).
+ */
+static bool isr_registered[NUM_ADC] = {0};
+
+typedef struct {
+uint32_t adc_value;
+rtems_adc_status status;
+} stm32f4_adc_data;
+static stm32f4_adc_data adc_data[NUM_ADC] = {0};
+
+static rtems_status_code stm32f4_adc_select_channel(
+rtems_gpio *base
+);
+
+/***/
+#ifdef ADC1
+static ADC_TypeDef_Protected _ADC1_protected = { ADC1, false };
+ADC_TypeDef_Protected *const ADC1_protected = &_ADC1_protected;
+#endif
+#ifdef ADC2
+static ADC_TypeDef_Protected _ADC2_protected = { ADC2, false };
+ADC_TypeDef_Protected *const ADC2_protected = &_ADC2_protected;
+#endif
+#ifdef ADC3
+static ADC_TypeDef_Protected _ADC3_protected = { ADC3, false };
+ADC_TypeDef_Protected *const ADC3_protected = &_ADC3_protected;
+#endif
+
+/* Helpers */
+#define STM32F4_GET_ADC_NUMBER(ADCx) \
+( (uintptr_t) ( ADCx ) == (uintptr_t) ADC1 ? 1 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC2 ? 2 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC3 ? 3 : \
+ 0 )
+#define STM32F4_GET_ADCx_FROM_NUMBER(num) (\
+( num ) == 1 ? ADC1 :\
+( num ) == 2 && NUM_ADC >= 2 ? ADC2 :\
+( num ) == 3 && NUM_ADC == 3 ? ADC3 :\
+ NULL)
+#define STM32F4_GET_ADCx_PROTECTED_
[PATCH v5 3/4] bsps: Add ADC API
---
bsps/include/bsp/adc.h| 292 ++
bsps/shared/dev/adc/adc.c | 200 +++
spec/build/bsps/bspopts.yml | 4 +
spec/build/bsps/obj.yml | 2 +
spec/build/bsps/optenadc.yml | 16 ++
spec/build/bsps/optnumadc.yml | 16 ++
6 files changed, 530 insertions(+)
create mode 100644 bsps/include/bsp/adc.h
create mode 100644 bsps/shared/dev/adc/adc.c
create mode 100644 spec/build/bsps/optenadc.yml
create mode 100644 spec/build/bsps/optnumadc.yml
diff --git a/bsps/include/bsp/adc.h b/bsps/include/bsp/adc.h
new file mode 100644
index 00..d168e1b201
--- /dev/null
+++ b/bsps/include/bsp/adc.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_ADC_H
+#define LIBBSP_BSP_ADC_H
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef enum {
+RTEMS_ADC_NOT_STARTED = 0,
+RTEMS_ADC_NOT_READY,
+RTEMS_ADC_READY
+} rtems_adc_status;
+
+typedef enum {
+RTEMS_ADC_ALIGN_LEFT,
+RTEMS_ADC_ALIGN_RIGHT
+} rtems_adc_align;
+
+typedef enum {
+RTEMS_ADC_NB_INTERRUPT,
+RTEMS_ADC_NB_DMA
+} rtems_adc_nb_mode;
+
+/**
+ * @brief Enumeration of reference voltages.
+ */
+typedef enum {
+RTEMS_ADC_REF_DEFAULT = 0,
+RTEMS_ADC_REF_INTERNAL,
+RTEMS_ADC_REF_EXTERNAL
+} rtems_adc_ref;
+
+#define RTEMS_ADC_NO_TIMEOUT 0xU
+
+typedef void (*rtems_adc_isr)(void *);
+typedef double (*rtems_adc_tf) (void *params, uint32_t raw_value);
+typedef struct rtems_adc_handlers rtems_adc_handlers;
+typedef struct rtems_adc_api rtems_adc_api;
+
+/**
+ * @brief Macro to help creating a rtems_adc_api object.
+ *
+ * Each BSP/driver must define its own handlers and create an object
+ * of this struct with pointers to those handlers.
+ */
+#define RTEMS_ADC_BUILD_API(\
+_init, \
+_read_raw, \
+_start_read_raw_nb, \
+_read_raw_nb, \
+_set_resolution,\
+_set_alignment, \
+_configure_interrupt, \
+_remove_interrupt, \
+_enable_interrupt, \
+_disable_interrupt) \
+{ \
+.base = { \
+.api_type = RTEMS_PERIPH_API_TYPE_ADC, \
+.init = _init \
+}, \
+.read_raw = ( _read_raw ), \
+.start_read_raw_nb = ( _start_read_raw_nb ),\
+.read_raw_nb = ( _read_raw_nb ),\
+.set_resolution = ( _set_resolution ), \
+.set_alignment = ( _set_alignment ),\
+.configure_interrupt = ( _configure_interrupt ),\
+.remove_interrupt = ( _remove_interrupt ), \
+.enable_interrupt = ( _enable_interrupt ), \
+.disable_interrupt = ( _disable_interrupt ),\
+};
+
+struct rtems_adc_api {
+/**
+ * @brief Co
[PATCH v5 2/4] bsps: New GPIO API & peripherals API framework
---
bsps/include/bsp/gpio2.h| 528
bsps/include/bsp/periph_api.h | 142 +++
bsps/shared/dev/gpio/gpio.c | 212 ++
bsps/shared/dev/periph_api/periph_api.c | 101 +
spec/build/bsps/obj.yml | 4 +-
5 files changed, 986 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/include/bsp/periph_api.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
create mode 100644 bsps/shared/dev/periph_api/periph_api.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..9cb1c720ab
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,528 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Macro to initialize rtems_gpio.
+ *
+ * @param gpioh pointer to GPIO handlers
+ */
+#define RTEMS_GPIO_BUILD_BASE(_gpio_handlers) \
+(rtems_gpio) { .virtual_pin = 0,\
+ .gpio_handlers = ( _gpio_handlers ), \
+ .api = NULL \
+};
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+#include
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+
[PATCH v5 1/4] bsps/stm32f4 Include STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/6f1fbc7dd7a5e0877d8bff11e1b21558928dbc16 --- .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 3460 +-- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 524 +- bsps/arm/include/core_cm7.h | 5186 ++-- bsps/arm/include/mpu_armv7.h | 270 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 + .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 + bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 +
[PATCH v5 0/4] *** New GPIO, ADC API and STM32F4 BSP implementation ***
Dear all, These patches add a new GPIO API and a framework for adding more peripheral APIs, with the example of ADC API. There is also implementation for these components for STM32F4 BSP. The core idea of my work on this peripherals API and new GPIO API is to add portability and simplify application code by using one identity for a GPIO pin that supports multiple types of operations. For example, a pin can be used as a basic GPIO, an ADC pin, a DAC pin or a PWM pin, but it's still represented by only one object (rtems_gpio). Different functionalities of the pin can be assigned through the peripherals API. In short, a pin can have 2 functions at the same time: digital GPIO and one extra function. In this system, an API is represented by a structure containing a member that identifies the API's type and other members being pointers to the API functions. A pointer to an object of this structure is stored inside a GPIO object to add functionalities to that pin. Application can change the pin's API pointer at runtime, which adds flexibility. An example application could be as follow: /**/ // Get pin object, same as before rtems_gpio *pin; rtems_gpio_get(); // Digital mode rtems_gpio_set_pin_mode(pin, RTEMS_GPIO_PINMODE_OUTPUT); rtems_gpio_set_pull(pin, RTEMS_GPIO_NOPULL); // Set the pin to HIGH rtems_gpio_write(pin, RTEMS_GPIO_PIN_SET); // Set ADC mode rtems_gpio_set_pin_mode(pin, RTEMS_GPIO_PINMODE_ANALOG); rtems_periph_api_set_api(pin, RTEMS_PERIPH_TYPE_ADC); // Analog read uint32_t result; rtems_adc_read_raw(pin, ); /**/ My repository is at: https://github.com/dtbpkmte/GSoC-2022-RTEMS (master branch). The sample application code for these APIs can be found at: https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. STM32F4 HAL source code is taken from ST's repo at: https://github.com/STMicroelectronics/STM32CubeF4.git (Commit ID: 52757b5, Release v1.27.1). v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM v3: - Removed rtems_gpio_begin() - bsp_gpio_register_controllers() now needs to be called from hook1 (can be configured by option STM32F4_ENABLE_GENERIC_GPIO) - Updated license text for API files and STM32F4 GPIO files v4: - Fixed GPIO port guards - Fixed potential memory-leak bug of STM32F4 GPIO interrupt system - Added comments to STM32F4 GPIO functions and made them extern v5: - Replace old HAL source code with the one from official repository to remove CRLF - Added a peripherals API, which is a framework to add more APIs that operates on a GPIO pin - Changed GPIO API to comply with the peripherals API - Changed ADC API to comply with the peripherals API - Changed STM32F4 implementation Duc Doan (4): bsps/stm32f4 Include STM32F4 HAL bsps: New GPIO API & peripherals API framework bsps: Add ADC API bsps/stm32f4: Implementation for GPIO and ADC .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 3460 +-- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 524 +- bsps/arm/include/core_cm7.h | 5186 ++-- bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/adc/adc.c| 655 + bsps/arm/stm32f4/gpio/gpio.c | 542 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_e
Re: [PATCH v4 1/7] bsps/stm32f4 Include STM32F4 HAL
Hello Christian, On Sat, 2022-07-23 at 10:31 +0200, o...@c-mauderer.de wrote: > Hello Duc, > > Am 23.07.22 um 09:37 schrieb Duc Doan: > > Hello Karel, > > > > On Sat, 2022-07-23 at 09:09 +0200, Karel Gardas wrote: > > > > > > Duc, > > > > > > where have you taken F4 HAL exactly? I'm asking since your import > > > is > > > full of CRLF line endings which we try hard to eliminate in RTEMS > > > while > > > original is not. Proof: > > > > > > $ git clone https://github.com/STMicroelectronics/STM32CubeF4.git > > > Cloning into 'STM32CubeF4'... > > > remote: Enumerating objects: 75365, done. > > > remote: Counting objects: 100% (1271/1271), done. > > > remote: Compressing objects: 100% (48/48), done. > > > remote: Total 75365 (delta 1231), reused 1229 (delta 1221), pack- > > > reused > > > 74094 > > > Receiving objects: 100% (75365/75365), 157.59 MiB | 6.87 MiB/s, > > > done. > > > Resolving deltas: 100% (46903/46903), done. > > > Updating files: 100% (39125/39125), done. > > > rtems@silence:~/vcs$ cd STM32CubeF4/ > > > rtems@silence:~/vcs/STM32CubeF4$ > > > rtems@silence:~/vcs/STM32CubeF4$ > > > rtems@silence:~/vcs/STM32CubeF4$ git ls-files --eol|grep crlf > > > rtems@silence:~/vcs/STM32CubeF4$ > > > > > > > > > Please use the command above to review your CRLF files. > > > > > > Thanks, > > > Karel > > > > > > > I took the HAL from ST's website by downloading the zip. And yes, > > when > > I tried the command, all HAL files have CRLF. I will remove them in > > the > > next patch set. > > Have you thought about using the STM32CubeF4 repo that Karel linked > instead of the ZIP file as a source? > > Can you please add the source for your files to the commit > description? > If you used a zip, provide the link, date, version (if available) and > maybe a checksum of the file. If you used a git repository (which I > would prefer), provide a link and the commit ID. That makes it > simpler > to some when find the sources that you used. > > Best regards > > Christian > Yes, in the next patch set I will replace the HAL files by those from the repo Karel linked. I will remember to provide the link and commit ID in the commit message. Best, Duc Doan > > > > Thanks for the reminder, > > > > Duc Doan > > ___ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v4 1/7] bsps/stm32f4 Include STM32F4 HAL
Hello Karel, On Sat, 2022-07-23 at 09:09 +0200, Karel Gardas wrote: > > Duc, > > where have you taken F4 HAL exactly? I'm asking since your import is > full of CRLF line endings which we try hard to eliminate in RTEMS > while > original is not. Proof: > > $ git clone https://github.com/STMicroelectronics/STM32CubeF4.git > Cloning into 'STM32CubeF4'... > remote: Enumerating objects: 75365, done. > remote: Counting objects: 100% (1271/1271), done. > remote: Compressing objects: 100% (48/48), done. > remote: Total 75365 (delta 1231), reused 1229 (delta 1221), pack- > reused > 74094 > Receiving objects: 100% (75365/75365), 157.59 MiB | 6.87 MiB/s, done. > Resolving deltas: 100% (46903/46903), done. > Updating files: 100% (39125/39125), done. > rtems@silence:~/vcs$ cd STM32CubeF4/ > rtems@silence:~/vcs/STM32CubeF4$ > rtems@silence:~/vcs/STM32CubeF4$ > rtems@silence:~/vcs/STM32CubeF4$ git ls-files --eol|grep crlf > rtems@silence:~/vcs/STM32CubeF4$ > > > Please use the command above to review your CRLF files. > > Thanks, > Karel > I took the HAL from ST's website by downloading the zip. And yes, when I tried the command, all HAL files have CRLF. I will remove them in the next patch set. Thanks for the reminder, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v4 7/7] bsps/stm32f4: Fix GPIO port guards and ISR bug
Changes GPIO port guards from variant to #ifdef
of ports. Fixed ISR memory-leak bug. Changed GPIO
functions to extern and added comments for them.
---
bsps/arm/stm32f4/gpio/gpio.c| 182
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 167 ++
2 files changed, 238 insertions(+), 111 deletions(-)
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
index ac4d3b4f56..5bcff71b2d 100644
--- a/bsps/arm/stm32f4/gpio/gpio.c
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -54,58 +54,6 @@ static rtems_status_code stm32f4_gpio_destroy(
rtems_gpio *base
);
-static rtems_status_code stm32f4_gpio_init(
-rtems_gpio *base
-);
-
-static rtems_status_code stm32f4_gpio_deinit(
-rtems_gpio *base
-);
-
-static rtems_status_code stm32f4_gpio_set_pin_mode(
-rtems_gpio *base,
-rtems_gpio_pin_mode mode
-);
-
-static rtems_status_code stm32f4_gpio_set_pull(
-rtems_gpio *base,
-rtems_gpio_pull pull
-);
-
-static rtems_status_code stm32f4_gpio_configure_interrupt(
-rtems_gpio *base,
-rtems_gpio_isr isr,
-void *arg,
-rtems_gpio_interrupt_trig trig,
-rtems_gpio_pull pull
-);
-
-static rtems_status_code stm32f4_gpio_remove_interrupt(
-rtems_gpio *base
-);
-
-static rtems_status_code stm32f4_gpio_enable_interrupt(
-rtems_gpio *base
-);
-
-static rtems_status_code stm32f4_gpio_disable_interrupt(
-rtems_gpio *base
-);
-
-static rtems_status_code stm32f4_gpio_read(
-rtems_gpio *base,
-rtems_gpio_pin_state *value
-);
-
-static rtems_status_code stm32f4_gpio_write(
-rtems_gpio *base,
-rtems_gpio_pin_state value
-);
-
-static rtems_status_code stm32f4_gpio_toggle(
-rtems_gpio *base
-);
-
/*/
/**
@@ -126,11 +74,39 @@ static const rtems_gpio_handlers stm32f4_gpio_handlers = {
};
static GPIO_TypeDef * const GPIOx[] = {
-GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
-GPIOF, GPIOG, GPIOH, GPIOI,
-#ifdef STM32F429X
-GPIOJ, GPIOK
-#endif /* STM32F429X */
+#ifdef GPIOA_BASE
+GPIOA
+#endif /* GPIOA_BASE */
+#ifdef GPIOB_BASE
+, GPIOB
+#endif /* GPIOB_BASE */
+#ifdef GPIOC_BASE
+, GPIOC
+#endif /* GPIOC_BASE */
+#ifdef GPIOD_BASE
+, GPIOD
+#endif /* GPIOD_BASE */
+#ifdef GPIOE_BASE
+, GPIOE
+#endif /* GPIOE_BASE */
+#ifdef GPIOF_BASE
+, GPIOF
+#endif /* GPIOF_BASE */
+#ifdef GPIOG_BASE
+, GPIOG
+#endif /* GPIOG_BASE */
+#ifdef GPIOH_BASE
+, GPIOH
+#endif /* GPIOH_BASE */
+#ifdef GPIOI_BASE
+, GPIOI
+#endif /* GPIOI_BASE */
+#ifdef GPIOJ_BASE
+, GPIOJ
+#endif /* GPIOJ_BASE */
+#ifdef GPIOK_BASE
+, GPIOK
+#endif /* GPIOK_BASE */
};
static unsigned int const EXTIx_IRQn[] = {
@@ -206,6 +182,7 @@ typedef struct {
} stm32f4_interrupt;
static stm32f4_interrupt isr_table[16];
+static bool isr_registered[16] = {0};
void exti_handler(void *arg);
@@ -253,41 +230,61 @@ rtems_status_code stm32f4_gpio_init(rtems_gpio *base) {
stm32f4_gpio *gpio = get_gpio_from_base(base);
switch ((uintptr_t) gpio->port) {
+#ifdef GPIOA_BASE
case (uintptr_t) GPIOA:
__HAL_RCC_GPIOA_CLK_ENABLE();
break;
+#endif /* GPIOA_BASE */
+#ifdef GPIOB_BASE
case (uintptr_t) GPIOB:
__HAL_RCC_GPIOB_CLK_ENABLE();
break;
+#endif /* GPIOB_BASE */
+#ifdef GPIOC_BASE
case (uintptr_t) GPIOC:
__HAL_RCC_GPIOC_CLK_ENABLE();
break;
+#endif /* GPIOC_BASE */
+#ifdef GPIOD_BASE
case (uintptr_t) GPIOD:
__HAL_RCC_GPIOD_CLK_ENABLE();
break;
+#endif /* GPIOD_BASE */
+#ifdef GPIOE_BASE
case (uintptr_t) GPIOE:
__HAL_RCC_GPIOE_CLK_ENABLE();
break;
+#endif /* GPIOE_BASE */
+#ifdef GPIOF_BASE
case (uintptr_t) GPIOF:
__HAL_RCC_GPIOF_CLK_ENABLE();
break;
+#endif /* GPIOF_BASE */
+#ifdef GPIOG_BASE
case (uintptr_t) GPIOG:
__HAL_RCC_GPIOG_CLK_ENABLE();
break;
+#endif /* GPIOG_BASE */
+#ifdef GPIOH_BASE
case (uintptr_t) GPIOH:
__HAL_RCC_GPIOH_CLK_ENABLE();
break;
+#endif /* GPIOH_BASE */
+#ifdef GPIOI_BASE
case (uintptr_t) GPIOI:
__HAL_RCC_GPIOI_CLK_ENABLE();
break;
-#ifdef STM32F429X
+#endif /* GPIOI_BASE */
+#ifdef GPIOJ_BASE
case (uintptr_t) GPIOJ:
__HAL_RCC_GPIOJ_CLK_ENABLE();
break;
+#endif /* GPIOJ_BASE */
+#ifdef GPIOK_BASE
case (uintptr_t) GPIOK:
__HAL_RCC_GPIOK_CLK_ENABLE();
break;
-#endif /* STM32F429X */
+#endif /* GPIOK_BASE */
default:
return RTEMS_UNSATISFIED;
}
@@ -295,50 +292,6 @@ rtems_status_code stm32f4_gpio_init(rtems_gpio *base) {
}
rtems_status_code stm32f4_gpio_deinit(rtems_gpio *base) {
-/*
-stm32f4_gpio *gpio = get_gpio_from_base(base);
-
-switch ((uintptr_t) gpio->port) {
-case (uintptr_t)
[PATCH v4 6/7] bsps/stm32f4: Add missing GPIO functionality
---
bsps/arm/stm32f4/gpio/gpio.c| 32 +
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 20 +
2 files changed, 52 insertions(+)
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
index efc005bd9f..ac4d3b4f56 100644
--- a/bsps/arm/stm32f4/gpio/gpio.c
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -562,3 +562,35 @@ void exti_handler(void *arg) {
}
}
+/ STM32F4 Other specific GPIO functions /
+void stm32f4_gpio_lock_pin(
+rtems_gpio *base
+)
+{
+stm32f4_gpio *gpio = get_gpio_from_base(base);
+LL_GPIO_LockPin(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin)
+);
+}
+
+void stm32f4_gpio_set_af(
+rtems_gpio *base,
+uint32_t alternate
+)
+{
+stm32f4_gpio *gpio = get_gpio_from_base(base);
+if (gpio->pin < 8)
+LL_GPIO_SetAFPin_0_7(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin),
+alternate
+);
+else
+LL_GPIO_SetAFPin_8_15(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin),
+alternate
+);
+}
+
diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
index eecd87b3fd..814b1b4105 100644
--- a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
+++ b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
@@ -53,4 +53,24 @@ typedef struct {
GPIO_TypeDef *port;
} stm32f4_gpio;
+/**
+ * @brief Lock configuration of a pin.
+ *
+ * @param[in] base The pointer to the GPIO object.
+ */
+extern void stm32f4_gpio_lock_pin(
+rtems_gpio *base
+);
+
+/**
+ * @brief Sets the alternate function for a pin.
+ *
+ * @param[in] base The pointer to the GPIO object.
+ * @param alternate Alternate function, from 0-15.
+ */
+extern void stm32f4_gpio_set_af(
+rtems_gpio *base,
+uint32_t alternate
+);
+
#endif /* LIBBSP_ARM_STM32F4_BSP_GPIO */
--
2.36.1
___
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[PATCH v4 5/7] bsps: Update license text
This patch updates the license text of GPIO API files and STM32F4 GPIO files. --- bsps/arm/stm32f4/gpio/gpio.c| 35 +++ bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 27 --- bsps/include/bsp/gpio2.h| 37 + bsps/shared/dev/gpio/gpio.c | 33 -- 4 files changed, 91 insertions(+), 41 deletions(-) diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c index d7cac7fd58..efc005bd9f 100644 --- a/bsps/arm/stm32f4/gpio/gpio.c +++ b/bsps/arm/stm32f4/gpio/gpio.c @@ -1,19 +1,28 @@ -/** - * @file - * - * @ingroup rtems_bsp/arm/stm32f4 - * - * @brief RTEMS GPIO new API implementation for STM32F4. - * - * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP - */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2022 Duc Doan + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h index 8f21539709..eecd87b3fd 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2022 Duc Doan + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_STM32F4_BSP_GPIO diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h index e4a106da8b..0040e30505 100644 --- a/bsps/include/bsp/gpio2.h +++ b/bsps/include/bsp/gpio2.h @@ -1,18 +1,29 @@ -/** - * @file - * - * @ingroup rtems_gpio2 - * - * @brief RTEMS GPIO new API definition. - */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* -* Copyright (c) 2022 Duc Doan -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rtems.org/license/LICENSE. -*/ + * Copyright (C) 2022 Duc Doan (d
[PATCH v4 4/7] bsps/stm32f4: Add GPIO implementation for STM32F4
---
bsps/arm/stm32f4/gpio/gpio.c | 555 ++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/start/bspstart.c | 7 +-
bsps/arm/stm32f4/start/bspstarthook.c | 8 +
spec/build/bsps/arm/stm32f4/grp.yml | 6 +-
spec/build/bsps/arm/stm32f4/obj.yml | 1 +
spec/build/bsps/arm/stm32f4/optengpio.yml | 16 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
10 files changed, 658 insertions(+), 9 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 spec/build/bsps/arm/stm32f4/optengpio.yml
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..d7cac7fd58
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,555 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_bsp/arm/stm32f4
+ *
+ * @brief RTEMS GPIO new API implementation for STM32F4.
+ *
+ * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP
+ */
+
+/*
+ * Copyright (c) 2022 Duc Doan
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include
+#include
+#include
+#include
+
+/*** Helpers */
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define get_gpio_from_base(base) \
+RTEMS_CONTAINER_OF(base, stm32f4_gpio, base)
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_init(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_deinit(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+);
+
+static rtems_status_code stm32f4_gpio_set_pull(
+rtems_gpio *base,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_configure_interrupt(
+rtems_gpio *base,
+rtems_gpio_isr isr,
+void *arg,
+rtems_gpio_interrupt_trig trig,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_remove_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_enable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_disable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_read(
+rtems_gpio *base,
+rtems_gpio_pin_state *value
+);
+
+static rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+);
+
+static rtems_status_code stm32f4_gpio_toggle(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.init = stm32f4_gpio_init,
+.deinit = stm32f4_gpio_deinit,
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef * const GPIOx[] = {
+GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
+GPIOF, GPIOG, GPIOH, GPIOI,
+#ifdef STM32F429X
+GPIOJ, GPIOK
+#endif /* STM32F429X */
+};
+
+static unsigned int const EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ])
+
+/**
+ * @brief Converts
[PATCH v4 3/7] bsps: Add GPIO API
This is the new GPIO API. The header file is
gpio2.h.
---
bsps/include/bsp/gpio2.h| 526
bsps/shared/dev/gpio/gpio.c | 189 +
spec/build/bsps/obj.yml | 2 +-
3 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e4a106da8b
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,526 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_gpio2
+ *
+ * @brief RTEMS GPIO new API definition.
+ */
+
+/*
+* Copyright (c) 2022 Duc Doan
+*
+* The license and distribution terms for this file may be
+* found in the file LICENSE in this distribution or at
+* http://www.rtems.org/license/LICENSE.
+*/
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to an initialize handler.
+ *
+ * This handler could be used to perform some set up steps for
+ * a GPIO object (which means a pin or a port).
+ */
+rtems_status_code (*init)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a deinitialize handler.
+ *
+ * This handler could be used to deinitialize a GPIO object.
+ */
+rtems_status_code (*deinit)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+ * Pin modes are from rtems_gpio_pin_mode enumeration.
+ */
+rtems_status_code (*set_pin_mode)(rtems_gpio *, rtems_gpio_pin_mode);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pull resistor mode.
+ *
+ * Pull resistor modes are from rtems_gpio_pull enumeration.
+ */
+rtems_status_code (*set_pull)(rtems_gpio *, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for configuring
+ *interrupt of a pin.
+ *
+ * This handler should register ISR and its argument, interrupt
+ * trigger mode, and pull resister mode for the pin.
+ *
+ * @note Enabling interrupt should be done in enable_interrupt()
+ * handler.
+ */
+rtems_status_code (*configure_interrupt)(rtems_gpio *, rtems_gpio_isr,
void *, rtems_gpio_interrupt_trig, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for removing
+ *interrupt settings of a pin.
+ *
+ * Interrupt settings can be ISR address, pin configuration, etc.
+ */
+rtems_status_code (*remove_interrupt)(rtems_gpio *);
+
+/**
+ * @brief This member is t
[PATCH v4 2/7] bsps/arm: Integrate and build STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/e21e1fa527da67533f797ed3dc6fc70cf245725b --- .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/hal/system_stm32f4xx.c | 747 + bsps/arm/stm32f4/include/bsp.h| 4 + bsps/arm/stm32f4/include/bsp/io.h | 4 + .../stm32f4/include/stm32_assert_template.h |56 - bsps/arm/stm32f4/include/stm32f401xc.h| 8641 +++ bsps/arm/stm32f4/include/stm32f401xe.h| 8641 +++ bsps/arm/stm32f4/include/stm32f405xx.h| 14310 +++ bsps/arm/stm32f4/include/stm32f407xx.h| 15607 bsps/arm/stm32f4/include/stm32f410cx.h| 7357 ++ bsps/arm/stm32f4/include/stm32f410rx.h| 7361 ++ bsps/arm/stm32f4/include/stm32f410tx.h| 7306 ++ bsps/arm/stm32f4/include/stm32f411xe.h| 8680 +++ bsps/arm/stm32f4/include/stm32f412cx.h| 13507 ++ bsps/arm/stm32f4/include/stm32f412rx.h| 14500 +++ bsps/arm/stm32f4/include/stm32f412vx.h| 14512 +++ bsps/arm/stm32f4/include/stm32f412zx.h| 14537 +++ bsps/arm/stm32f4/include/stm32f413xx.h| 15462 bsps/arm/stm32f4/include/stm32f415xx.h| 14595 +++ bsps/arm/stm32f4/include/stm32f417xx.h| 15887 bsps/arm/stm32f4/include/stm32f423xx.h| 15615 bsps/arm/stm32f4/include/stm32f427xx.h| 16827 + bsps/arm/stm32f4/include/stm32f429xx.h| 17185 + bsps/arm/stm32f4/include/stm32f437xx.h| 17129 + bsps/arm/stm32f4/include/stm32f439xx.h| 17479 + bsps/arm/stm32f4/include/stm32f446xx.h| 15981 bsps/arm/stm32f4/include/stm32f469xx.h| 20278 +++ bsps/arm/stm32f4/include/stm32f479xx.h| 20575 bsps/arm/stm32f4/include/stm32f4xx.h | 305 + ...l_conf_template.h => stm32f4xx_hal_conf.h} | 6 + bsps/arm/stm32f4/include/system_stm32f4xx.h | 104 + bsps/arm/stm32f4/start/bspstart.c | 202 +- bsps/arm/stm32f4/start/bspstart_old.c | 297 + spec/build/bsps/arm/grp.yml | 5 +- spec/build/bsps/arm/stm32f4/grp.yml |12 +- spec/build/bsps/arm/stm32f4/obj.yml | 220 + spec/build/bsps/arm/stm32f4/optenhal.yml |16 + spec/build/bsps/arm/stm32f4/opthse.yml|17 + spec/build/bsps/arm/stm32f4/optusehse.yml |16 + spec/build/bsps/arm/stm32f4/optvariant.yml|24 + spec/build/bsps/obj.yml | 1 + 49 files changed, 331831 insertions(+), 2443 deletions(-) create mode 100644 bsps/arm/include/cmsis_compiler.h create mode 100644 bsps/arm/include/cmsis_version.h create mode 100644 bsps/arm/include/legacy/cmsis_gcc.h create mode 100644 bsps/arm/include/legacy/core_cm7.h create mode 100644 bsps/arm/include/mpu_armv7.h create mode 100644 bsps/arm/stm32f4/hal/system_stm32f4xx.c delete mode 100644 bsps/arm/stm32f4/include/stm32_assert_template.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xc.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f405xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f407xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410tx.h create mode 100644 bsps/arm/stm32f4/include/stm32f411xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f412cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412vx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412zx.h create mode 100644 bsps/arm/stm32f4/include/stm32f413xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f415xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f417xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f423xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f427xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f429xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f437xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f439xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f446xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f469xx.h create mode 100644
[PATCH v4 1/7] bsps/stm32f4 Include STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/098ca07151bb9186c7681c45f8474cf1441acb40 --- .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 + bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 +++ .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 +++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 ++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 + bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 +++ .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 + bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dac.c | 280 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma.c | 423 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma2d.c | 594 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_exti.c | 212 + bsps/arm/stm32f4/hal/stm32f4xx_ll_fmc.c | 1498
[PATCH v4 0/7] *** New GPIO API and implementation for STM32F4 BSP ***
Dear all, These patches add a new GPIO API that aims at portability. GPIO of STM32F4 BSP has been implemented using this API. The sample application code can be found at https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. The newest branch is stm32f4-gpio. v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM v3: - Removed rtems_gpio_begin() - bsp_gpio_register_controllers() now needs to be called from hook1 (can be configured by option STM32F4_ENABLE_GENERIC_GPIO) - Updated license text for API files and STM32F4 GPIO files v4: - Fixed GPIO port guards - Fixed potential memory-leak bug of STM32F4 GPIO interrupt system - Added comments to STM32F4 GPIO functions and made them extern Duc Doan (7): bsps/stm32f4 Include STM32F4 HAL bsps/arm: Integrate and build STM32F4 HAL bsps: Add GPIO API bsps/stm32f4: Add GPIO implementation for STM32F4 bsps: Update license text bsps/stm32f4: Add missing GPIO functionality bsps/stm32f4: Fix GPIO port guards and ISR bug .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/gpio/gpio.c | 556 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c
Re: [Feedback needed] Proposal for ADC API
Hello Sebastian, On Tue, 2022-07-19 at 14:00 +0200, Sebastian Huber wrote: > Hello, > > we should also consider to use existing APIs and implementations for > stuff we do not yet have in RTEMS, for example: > > https://docs.zephyrproject.org/latest/hardware/peripherals/adc.html > > The Zephyr project uses device trees to statically configure device > drivers: > > https://docs.zephyrproject.org/latest/build/dts/index.html > > This is quite interesting for lower end targets. > Can you please explain more about your thoughts and maybe some directions for me? Do you mean we should find ways to change the way our current APIs work with static constructions instead of adding new APIs? Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[Feedback needed] Proposal for ADC API
Hello,
I would like to propose an ADC API that aims to create an interface for
reading analog value conveniently with blocking/non-blocking styles and
support custom transfer function for each pin. The API depends on the
new GPIO API.
Here are some features of the ADC API:
- Blocking/non-blocking read
- Interrupt
- Assign a transfer function to a pin, so that the result of a read()
function may already be converted to a desired output
- Setting some common options: resolution, data alignment
The changes I needed to make to the GPIO API:
- Add members to rtems_gpio struct: adc_handlers, adc_tf (only if
option BSP_ENABLE_ADC is defined 1)
I implemented ADC for STM32F4 using this API. The current state of
STM32F4 ADC:
- Using single channel conversion, regular group
- Pins that belong to multiple ADCs use ADC1
- Non-blocking read uses EOCS interrupt
- Supports up to 3 user-defined ISR, one for each ADC
Example API calls:
//
// Get GPIO objects and configure pin in ANALOG mode
rtems_gpio_get(POT_VPIN, );
rtems_gpio_init(pot);
rtems_gpio_set_pin_mode(pot, RTEMS_GPIO_PINMODE_ANALOG);
rtems_gpio_set_pull(pot, RTEMS_GPIO_NOPULL);
// Setting resolution
rtems_adc_set_resolution(pot, 10);
// Blocking read
rtems_adc_read_raw(pot, _value);
// Non-blocking read
rtems_adc_start_read_nb(pot);
rtems_adc_read_raw_nb(pot, _value);
// Reading with transfer function y = 6x + 5
uint32_t params[] = {6, 5};
rtems_adc_assign_tf(pot, linear1, params);
double tf_result;
rtems_adc_read(pot, _result);
...
double linear1(void *params, uint32_t raw) {
uint32_t *p = (uint32_t *) params;
return ((double) raw) * p[0] + p[1];
}
...
/**/
Sample applications can be found in the RTEMS_ADC_* folders in this
repo: https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps
Please have a look at these files:
- Modified GPIO API:
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/include/bsp/gpio2.h
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/shared/dev/gpio/gpio.c
- ADC API:
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/include/bsp/adc.h
https://github.com/dtbpkmte/GSoC-2022-RTEMS/tree/adc-api/bsps/shared/dev/adc
- STM32F4 GPIO:
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/arm/stm32f4/gpio/gpio.c
- STM32F4 ADC:
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/arm/stm32f4/include/bsp/stm32f4_adc.h
https://github.com/dtbpkmte/GSoC-2022-RTEMS/blob/adc-api/bsps/arm/stm32f4/adc/adc.c
The code still has bugs and I am fixing/writing test applications and
adding documentation. I would appreciate all feedback. Thank you very
much.
Best,
Duc Doan
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v3 0/5] *** New GPIO API and implementation for STM32F4 BSP ***
Hello, This blog of mine describes the API and shows how to use/implement the API for a BSP/driver: https://medium.com/@dtbpkmte/gsoc-2022-rtems-coding-period-week-4-gpio-wiki-1f10e5c4458 Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/1] bsps/stm32f4: Add missing GPIO functionality
---
bsps/arm/stm32f4/gpio/gpio.c| 32 +
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 20 +
2 files changed, 52 insertions(+)
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
index efc005bd9f..ac4d3b4f56 100644
--- a/bsps/arm/stm32f4/gpio/gpio.c
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -562,3 +562,35 @@ void exti_handler(void *arg) {
}
}
+/ STM32F4 Other specific GPIO functions /
+void stm32f4_gpio_lock_pin(
+rtems_gpio *base
+)
+{
+stm32f4_gpio *gpio = get_gpio_from_base(base);
+LL_GPIO_LockPin(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin)
+);
+}
+
+void stm32f4_gpio_set_af(
+rtems_gpio *base,
+uint32_t alternate
+)
+{
+stm32f4_gpio *gpio = get_gpio_from_base(base);
+if (gpio->pin < 8)
+LL_GPIO_SetAFPin_0_7(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin),
+alternate
+);
+else
+LL_GPIO_SetAFPin_8_15(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin),
+alternate
+);
+}
+
diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
index eecd87b3fd..814b1b4105 100644
--- a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
+++ b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
@@ -53,4 +53,24 @@ typedef struct {
GPIO_TypeDef *port;
} stm32f4_gpio;
+/**
+ * @brief Lock configuration of a pin.
+ *
+ * @param[in] base The pointer to the GPIO object.
+ */
+extern void stm32f4_gpio_lock_pin(
+rtems_gpio *base
+);
+
+/**
+ * @brief Sets the alternate function for a pin.
+ *
+ * @param[in] base The pointer to the GPIO object.
+ * @param alternate Alternate function, from 0-15.
+ */
+extern void stm32f4_gpio_set_af(
+rtems_gpio *base,
+uint32_t alternate
+);
+
#endif /* LIBBSP_ARM_STM32F4_BSP_GPIO */
--
2.36.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/1] Add STM32F4 GPIO functionality
This patch adds GPIO functionality of STM32F4 that the GPIO API does not cover. It includes locking pins and setting alternate function. Duc Doan (1): bsps/stm32f4: Add missing GPIO functionality bsps/arm/stm32f4/gpio/gpio.c| 32 + bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 20 + 2 files changed, 52 insertions(+) -- 2.36.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3 5/5] bsps: Update license text
This patch updates the license text of GPIO API files and STM32F4 GPIO files. --- bsps/arm/stm32f4/gpio/gpio.c| 35 +++ bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 27 --- bsps/include/bsp/gpio2.h| 37 + bsps/shared/dev/gpio/gpio.c | 33 -- 4 files changed, 91 insertions(+), 41 deletions(-) diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c index d7cac7fd58..efc005bd9f 100644 --- a/bsps/arm/stm32f4/gpio/gpio.c +++ b/bsps/arm/stm32f4/gpio/gpio.c @@ -1,19 +1,28 @@ -/** - * @file - * - * @ingroup rtems_bsp/arm/stm32f4 - * - * @brief RTEMS GPIO new API implementation for STM32F4. - * - * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP - */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2022 Duc Doan + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h index 8f21539709..eecd87b3fd 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2022 Duc Doan + * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_STM32F4_BSP_GPIO diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h index e4a106da8b..0040e30505 100644 --- a/bsps/include/bsp/gpio2.h +++ b/bsps/include/bsp/gpio2.h @@ -1,18 +1,29 @@ -/** - * @file - * - * @ingroup rtems_gpio2 - * - * @brief RTEMS GPIO new API definition. - */ +/* SPDX-License-Identifier: BSD-2-Clause */ /* -* Copyright (c) 2022 Duc Doan -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rtems.org/license/LICENSE. -*/ + * Copyright (C) 2022 Duc Doan (d
[PATCH v3 4/5] bsps/stm32f4: Add GPIO implementation for STM32F4
---
bsps/arm/stm32f4/gpio/gpio.c | 555 ++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/start/bspstart.c | 7 +-
bsps/arm/stm32f4/start/bspstarthook.c | 8 +
spec/build/bsps/arm/stm32f4/grp.yml | 6 +-
spec/build/bsps/arm/stm32f4/obj.yml | 1 +
spec/build/bsps/arm/stm32f4/optengpio.yml | 16 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
10 files changed, 658 insertions(+), 9 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 spec/build/bsps/arm/stm32f4/optengpio.yml
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..d7cac7fd58
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,555 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_bsp/arm/stm32f4
+ *
+ * @brief RTEMS GPIO new API implementation for STM32F4.
+ *
+ * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP
+ */
+
+/*
+ * Copyright (c) 2022 Duc Doan
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include
+#include
+#include
+#include
+
+/*** Helpers */
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define get_gpio_from_base(base) \
+RTEMS_CONTAINER_OF(base, stm32f4_gpio, base)
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_init(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_deinit(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+);
+
+static rtems_status_code stm32f4_gpio_set_pull(
+rtems_gpio *base,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_configure_interrupt(
+rtems_gpio *base,
+rtems_gpio_isr isr,
+void *arg,
+rtems_gpio_interrupt_trig trig,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_remove_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_enable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_disable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_read(
+rtems_gpio *base,
+rtems_gpio_pin_state *value
+);
+
+static rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+);
+
+static rtems_status_code stm32f4_gpio_toggle(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.init = stm32f4_gpio_init,
+.deinit = stm32f4_gpio_deinit,
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef * const GPIOx[] = {
+GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
+GPIOF, GPIOG, GPIOH, GPIOI,
+#ifdef STM32F429X
+GPIOJ, GPIOK
+#endif /* STM32F429X */
+};
+
+static unsigned int const EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ])
+
+/**
+ * @brief Converts
[PATCH v3 3/5] bsps: Add GPIO API
This is the new GPIO API. The header file is
gpio2.h.
---
bsps/include/bsp/gpio2.h| 526
bsps/shared/dev/gpio/gpio.c | 189 +
spec/build/bsps/obj.yml | 2 +-
3 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e4a106da8b
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,526 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_gpio2
+ *
+ * @brief RTEMS GPIO new API definition.
+ */
+
+/*
+* Copyright (c) 2022 Duc Doan
+*
+* The license and distribution terms for this file may be
+* found in the file LICENSE in this distribution or at
+* http://www.rtems.org/license/LICENSE.
+*/
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to an initialize handler.
+ *
+ * This handler could be used to perform some set up steps for
+ * a GPIO object (which means a pin or a port).
+ */
+rtems_status_code (*init)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a deinitialize handler.
+ *
+ * This handler could be used to deinitialize a GPIO object.
+ */
+rtems_status_code (*deinit)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+ * Pin modes are from rtems_gpio_pin_mode enumeration.
+ */
+rtems_status_code (*set_pin_mode)(rtems_gpio *, rtems_gpio_pin_mode);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pull resistor mode.
+ *
+ * Pull resistor modes are from rtems_gpio_pull enumeration.
+ */
+rtems_status_code (*set_pull)(rtems_gpio *, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for configuring
+ *interrupt of a pin.
+ *
+ * This handler should register ISR and its argument, interrupt
+ * trigger mode, and pull resister mode for the pin.
+ *
+ * @note Enabling interrupt should be done in enable_interrupt()
+ * handler.
+ */
+rtems_status_code (*configure_interrupt)(rtems_gpio *, rtems_gpio_isr,
void *, rtems_gpio_interrupt_trig, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for removing
+ *interrupt settings of a pin.
+ *
+ * Interrupt settings can be ISR address, pin configuration, etc.
+ */
+rtems_status_code (*remove_interrupt)(rtems_gpio *);
+
+/**
+ * @brief This member is t
[PATCH v3 2/5] bsps/arm: Integrate and build STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/tree/2baea7f3ffb178d581b3c6b6b7c1b63f8ac55852 --- .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/hal/system_stm32f4xx.c | 747 + bsps/arm/stm32f4/include/bsp.h| 4 + bsps/arm/stm32f4/include/bsp/io.h | 4 + .../stm32f4/include/stm32_assert_template.h |56 - bsps/arm/stm32f4/include/stm32f401xc.h| 8641 +++ bsps/arm/stm32f4/include/stm32f401xe.h| 8641 +++ bsps/arm/stm32f4/include/stm32f405xx.h| 14310 +++ bsps/arm/stm32f4/include/stm32f407xx.h| 15607 bsps/arm/stm32f4/include/stm32f410cx.h| 7357 ++ bsps/arm/stm32f4/include/stm32f410rx.h| 7361 ++ bsps/arm/stm32f4/include/stm32f410tx.h| 7306 ++ bsps/arm/stm32f4/include/stm32f411xe.h| 8680 +++ bsps/arm/stm32f4/include/stm32f412cx.h| 13507 ++ bsps/arm/stm32f4/include/stm32f412rx.h| 14500 +++ bsps/arm/stm32f4/include/stm32f412vx.h| 14512 +++ bsps/arm/stm32f4/include/stm32f412zx.h| 14537 +++ bsps/arm/stm32f4/include/stm32f413xx.h| 15462 bsps/arm/stm32f4/include/stm32f415xx.h| 14595 +++ bsps/arm/stm32f4/include/stm32f417xx.h| 15887 bsps/arm/stm32f4/include/stm32f423xx.h| 15615 bsps/arm/stm32f4/include/stm32f427xx.h| 16827 + bsps/arm/stm32f4/include/stm32f429xx.h| 17185 + bsps/arm/stm32f4/include/stm32f437xx.h| 17129 + bsps/arm/stm32f4/include/stm32f439xx.h| 17479 + bsps/arm/stm32f4/include/stm32f446xx.h| 15981 bsps/arm/stm32f4/include/stm32f469xx.h| 20278 +++ bsps/arm/stm32f4/include/stm32f479xx.h| 20575 bsps/arm/stm32f4/include/stm32f4xx.h | 305 + ...l_conf_template.h => stm32f4xx_hal_conf.h} | 6 + bsps/arm/stm32f4/include/system_stm32f4xx.h | 104 + bsps/arm/stm32f4/start/bspstart.c | 202 +- bsps/arm/stm32f4/start/bspstart_old.c | 297 + spec/build/bsps/arm/grp.yml | 5 +- spec/build/bsps/arm/stm32f4/grp.yml |12 +- spec/build/bsps/arm/stm32f4/obj.yml | 220 + spec/build/bsps/arm/stm32f4/optenhal.yml |16 + spec/build/bsps/arm/stm32f4/opthse.yml|17 + spec/build/bsps/arm/stm32f4/optusehse.yml |16 + spec/build/bsps/arm/stm32f4/optvariant.yml|24 + spec/build/bsps/obj.yml | 1 + 49 files changed, 331831 insertions(+), 2443 deletions(-) create mode 100644 bsps/arm/include/cmsis_compiler.h create mode 100644 bsps/arm/include/cmsis_version.h create mode 100644 bsps/arm/include/legacy/cmsis_gcc.h create mode 100644 bsps/arm/include/legacy/core_cm7.h create mode 100644 bsps/arm/include/mpu_armv7.h create mode 100644 bsps/arm/stm32f4/hal/system_stm32f4xx.c delete mode 100644 bsps/arm/stm32f4/include/stm32_assert_template.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xc.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f405xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f407xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410tx.h create mode 100644 bsps/arm/stm32f4/include/stm32f411xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f412cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412vx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412zx.h create mode 100644 bsps/arm/stm32f4/include/stm32f413xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f415xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f417xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f423xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f427xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f429xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f437xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f439xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f446xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f469xx.h create mode 100644
[PATCH v3 1/5] bsps/stm32f4 Include STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/tree/f7ed35b5ce25a5410e72e4950d27ea86afbfe5c4 --- .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 + bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 +++ .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 +++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 ++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 + bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 +++ .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 + bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dac.c | 280 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma.c | 423 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma2d.c | 594 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_exti.c | 212 + bsps/arm/stm32f4/hal/stm32f4xx_ll_fmc.c | 1498
[PATCH v3 0/5] *** New GPIO API and implementation for STM32F4 BSP ***
Hello, This patch adds a new GPIO API that aims at portability. GPIO of STM32F4 BSP has been implemented using this API. The sample application code can be found at https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM v3: - Removed rtems_gpio_begin() - bsp_gpio_register_controllers() now needs to be called from hook1 (can be configured by option STM32F4_ENABLE_GENERIC_GPIO) - Updated license text for API files and STM32F4 GPIO files Duc Doan (5): bsps/stm32f4 Include STM32F4 HAL bsps/arm: Integrate and build STM32F4 HAL bsps: Add GPIO API bsps/stm32f4: Add GPIO implementation for STM32F4 bsps: Update license text .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/gpio/gpio.c | 564 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554
Re: [PATCH v2 3/4] bsps: Add GPIO API
Hello Karel, On Thu, 2022-07-07 at 14:36 +0200, Karel Gardas wrote: > > Hello Duc, > > just two notes which bothers me most. > > On 7/7/22 13:34, Duc Doan wrote: > > This is the new GPIO API. The header file is > > gpio2.h. > > --- > > bsps/include/bsp/gpio2.h | 538 > > > > bsps/shared/dev/gpio/gpio.c | 196 + > > spec/build/bsps/obj.yml | 2 +- > > 3 files changed, 735 insertions(+), 1 deletion(-) > > create mode 100644 bsps/include/bsp/gpio2.h > > create mode 100644 bsps/shared/dev/gpio/gpio.c > > > > diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h > > new file mode 100644 > > index 00..e99967cd47 > > --- /dev/null > > +++ b/bsps/include/bsp/gpio2.h > > @@ -0,0 +1,538 @@ > > +/** > > + * @file > > + * > > + * @ingroup rtems_gpio2 > > + * > > + * @brief RTEMS GPIO new API definition. > > + */ > > + > > +/* > > +* Copyright (c) 2022 Duc Doan > > +* > > +* The license and distribution terms for this file may be > > +* found in the file LICENSE in this distribution or at > > +* http://www.rtems.org/license/LICENSE. > > +*/ > > RTEMS project (Joel & others) perform huge effort in a way on > relicensing RTEMS to BSD license. Please use new license header > instead > of this one which is old -- from GPL days. Open few random RTEMS > files > and you will see few license headers. Look for example into ... > randomly > picked :-) -- > bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c and > modify this to your name/email... > Thank you for the reminder. I was actually copying from a random source file before. I will change it in the next version. > > > +/** > > + * @brief Performs setup for GPIO functionality. > > + * > > + * This function calls bsp_gpio_register_controllers() and may > > + * perform additional initialization steps for GPIO > > functionality. > > + * It should be called by users before all GPIO operations, > > ideally > > + * when the application starts. > > + */ > > +extern void rtems_gpio_begin( > > + void > > +); > > I don't like this _begin mentality here. I think this should be all > done > by BSP code based on actual BSP configuration. > Something like: > STM32F4_ENABLE_GENERIC_GPIO implemented as optengpio.yml in f4 spec > and > then based on its C preprocessor value just calls > bsp_gpio_register_controllers from probably hook_1 and be done with > that. > > Sorry about that, 'begin' is too much RDBMS hooked thing here and > when I > see 'begin' I also expect 'commit' or 'rollback' somewhere down the > line. :-) > > Thanks, > Karel > I see, it makes sense to call that function automatically. I actually tried to do so using RTEMS_SYSINIT_ITEM but failed. I will try putting it into the hook. Best, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 2/4] bsps/arm: Integrate and build STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/tree/2baea7f3ffb178d581b3c6b6b7c1b63f8ac55852 --- .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/hal/system_stm32f4xx.c | 747 + bsps/arm/stm32f4/include/bsp.h| 4 + bsps/arm/stm32f4/include/bsp/io.h | 4 + .../stm32f4/include/stm32_assert_template.h |56 - bsps/arm/stm32f4/include/stm32f401xc.h| 8641 +++ bsps/arm/stm32f4/include/stm32f401xe.h| 8641 +++ bsps/arm/stm32f4/include/stm32f405xx.h| 14310 +++ bsps/arm/stm32f4/include/stm32f407xx.h| 15607 bsps/arm/stm32f4/include/stm32f410cx.h| 7357 ++ bsps/arm/stm32f4/include/stm32f410rx.h| 7361 ++ bsps/arm/stm32f4/include/stm32f410tx.h| 7306 ++ bsps/arm/stm32f4/include/stm32f411xe.h| 8680 +++ bsps/arm/stm32f4/include/stm32f412cx.h| 13507 ++ bsps/arm/stm32f4/include/stm32f412rx.h| 14500 +++ bsps/arm/stm32f4/include/stm32f412vx.h| 14512 +++ bsps/arm/stm32f4/include/stm32f412zx.h| 14537 +++ bsps/arm/stm32f4/include/stm32f413xx.h| 15462 bsps/arm/stm32f4/include/stm32f415xx.h| 14595 +++ bsps/arm/stm32f4/include/stm32f417xx.h| 15887 bsps/arm/stm32f4/include/stm32f423xx.h| 15615 bsps/arm/stm32f4/include/stm32f427xx.h| 16827 + bsps/arm/stm32f4/include/stm32f429xx.h| 17185 + bsps/arm/stm32f4/include/stm32f437xx.h| 17129 + bsps/arm/stm32f4/include/stm32f439xx.h| 17479 + bsps/arm/stm32f4/include/stm32f446xx.h| 15981 bsps/arm/stm32f4/include/stm32f469xx.h| 20278 +++ bsps/arm/stm32f4/include/stm32f479xx.h| 20575 bsps/arm/stm32f4/include/stm32f4xx.h | 305 + ...l_conf_template.h => stm32f4xx_hal_conf.h} | 6 + bsps/arm/stm32f4/include/system_stm32f4xx.h | 104 + bsps/arm/stm32f4/start/bspstart.c | 202 +- bsps/arm/stm32f4/start/bspstart_old.c | 297 + spec/build/bsps/arm/grp.yml | 5 +- spec/build/bsps/arm/stm32f4/grp.yml |12 +- spec/build/bsps/arm/stm32f4/obj.yml | 220 + spec/build/bsps/arm/stm32f4/optenhal.yml |16 + spec/build/bsps/arm/stm32f4/opthse.yml|17 + spec/build/bsps/arm/stm32f4/optusehse.yml |16 + spec/build/bsps/arm/stm32f4/optvariant.yml|24 + spec/build/bsps/obj.yml | 1 + 49 files changed, 331831 insertions(+), 2443 deletions(-) create mode 100644 bsps/arm/include/cmsis_compiler.h create mode 100644 bsps/arm/include/cmsis_version.h create mode 100644 bsps/arm/include/legacy/cmsis_gcc.h create mode 100644 bsps/arm/include/legacy/core_cm7.h create mode 100644 bsps/arm/include/mpu_armv7.h create mode 100644 bsps/arm/stm32f4/hal/system_stm32f4xx.c delete mode 100644 bsps/arm/stm32f4/include/stm32_assert_template.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xc.h create mode 100644 bsps/arm/stm32f4/include/stm32f401xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f405xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f407xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f410tx.h create mode 100644 bsps/arm/stm32f4/include/stm32f411xe.h create mode 100644 bsps/arm/stm32f4/include/stm32f412cx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412rx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412vx.h create mode 100644 bsps/arm/stm32f4/include/stm32f412zx.h create mode 100644 bsps/arm/stm32f4/include/stm32f413xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f415xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f417xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f423xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f427xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f429xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f437xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f439xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f446xx.h create mode 100644 bsps/arm/stm32f4/include/stm32f469xx.h create mode 100644
[PATCH v2 4/4] bsps/stm32f4: Add GPIO implementation for STM32F4
---
bsps/arm/stm32f4/gpio/gpio.c | 555 ++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/start/bspstart.c | 7 +-
spec/build/bsps/arm/stm32f4/grp.yml | 4 +-
spec/build/bsps/arm/stm32f4/obj.yml | 1 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
8 files changed, 632 insertions(+), 9 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..d7cac7fd58
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,555 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_bsp/arm/stm32f4
+ *
+ * @brief RTEMS GPIO new API implementation for STM32F4.
+ *
+ * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP
+ */
+
+/*
+ * Copyright (c) 2022 Duc Doan
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include
+#include
+#include
+#include
+
+/*** Helpers */
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define get_gpio_from_base(base) \
+RTEMS_CONTAINER_OF(base, stm32f4_gpio, base)
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_init(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_deinit(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+);
+
+static rtems_status_code stm32f4_gpio_set_pull(
+rtems_gpio *base,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_configure_interrupt(
+rtems_gpio *base,
+rtems_gpio_isr isr,
+void *arg,
+rtems_gpio_interrupt_trig trig,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_remove_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_enable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_disable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_read(
+rtems_gpio *base,
+rtems_gpio_pin_state *value
+);
+
+static rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+);
+
+static rtems_status_code stm32f4_gpio_toggle(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.init = stm32f4_gpio_init,
+.deinit = stm32f4_gpio_deinit,
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef * const GPIOx[] = {
+GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
+GPIOF, GPIOG, GPIOH, GPIOI,
+#ifdef STM32F429X
+GPIOJ, GPIOK
+#endif /* STM32F429X */
+};
+
+static unsigned int const EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ])
+
+/**
+ * @brief Converts intermediate pin number to 0-15.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15
[PATCH v2 3/4] bsps: Add GPIO API
This is the new GPIO API. The header file is
gpio2.h.
---
bsps/include/bsp/gpio2.h| 538
bsps/shared/dev/gpio/gpio.c | 196 +
spec/build/bsps/obj.yml | 2 +-
3 files changed, 735 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e99967cd47
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,538 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_gpio2
+ *
+ * @brief RTEMS GPIO new API definition.
+ */
+
+/*
+* Copyright (c) 2022 Duc Doan
+*
+* The license and distribution terms for this file may be
+* found in the file LICENSE in this distribution or at
+* http://www.rtems.org/license/LICENSE.
+*/
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to an initialize handler.
+ *
+ * This handler could be used to perform some set up steps for
+ * a GPIO object (which means a pin or a port).
+ */
+rtems_status_code (*init)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a deinitialize handler.
+ *
+ * This handler could be used to deinitialize a GPIO object.
+ */
+rtems_status_code (*deinit)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+ * Pin modes are from rtems_gpio_pin_mode enumeration.
+ */
+rtems_status_code (*set_pin_mode)(rtems_gpio *, rtems_gpio_pin_mode);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pull resistor mode.
+ *
+ * Pull resistor modes are from rtems_gpio_pull enumeration.
+ */
+rtems_status_code (*set_pull)(rtems_gpio *, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for configuring
+ *interrupt of a pin.
+ *
+ * This handler should register ISR and its argument, interrupt
+ * trigger mode, and pull resister mode for the pin.
+ *
+ * @note Enabling interrupt should be done in enable_interrupt()
+ * handler.
+ */
+rtems_status_code (*configure_interrupt)(rtems_gpio *, rtems_gpio_isr,
void *, rtems_gpio_interrupt_trig, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for removing
+ *interrupt settings of a pin.
+ *
+ * Interrupt settings can be ISR address, pin configuration, etc.
+ */
+rtems_status_code (*remove_interrupt)(rtems_gpio *);
+
+/**
+ * @brief This member is t
[PATCH v2 1/4] bsps/stm32f4 Include STM32F4 HAL
This patch is too large so I cannot send via email. Please find it here: https://github.com/dtbpkmte/GSoC-2022-RTEMS/tree/f7ed35b5ce25a5410e72e4950d27ea86afbfe5c4. --- .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 + bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 +++ .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 +++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 ++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 + bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 +++ .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 + bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dac.c | 280 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma.c | 423 + bsps/arm/stm32f4/hal/stm32f4xx_ll_dma2d.c | 594 ++ bsps/arm/stm32f4/hal/stm32f4xx_ll_exti.c | 212 + bsps/arm/stm32f4/hal/stm32f4xx_ll_fmc.c | 1498
[PATCH v2 0/4] *** New GPIO API and implementation for STM32F4 BSP ***
Hello, This patch adds a new GPIO API that aims at portability. GPIO of STM32F4 BSP has been implemented using this API. The sample application code can be found at https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM Duc Doan (4): bsps/stm32f4 Include STM32F4 HAL bsps/arm: Integrate and build STM32F4 HAL bsps: Add GPIO API bsps/stm32f4: Add GPIO implementation for STM32F4 .gitignore| 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 4066 +-- bsps/arm/include/core_cm7.h | 582 +- bsps/arm/include/legacy/cmsis_gcc.h | 1375 ++ bsps/arm/include/legacy/core_cm7.h| 2515 ++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/gpio/gpio.c | 555 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 + .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 ++ bsps/arm
Re: [PATCH] bsps/arm/stm32f4 Optimize get pin and change from HAL to LL
Hello Cedric,
On Thu, 2022-07-07 at 10:32 +0200, Cedric Berger wrote:
> Hello,
>
> On 07.07.22 09:35, Duc Doan wrote:
> > Actually my project is focused on STM32F4, but it is nice that the
> > code
> > could be extensible to H7. However, I can't think of a good way to
> > use
> > that code with H7 right now; do you think that the code can be
> > copied
> > and pasted to H7 BSP? Or is there a better way to share the code
> > among
> > all STM32 BSPs?
>
> I've a lot of experience with STM32 dev, but not with RTEMS, so I'm
> not
> the best person to answer that question.
>
> If you want to expand support for the H7 now, maybe Karel or someone
> else on the list can point you to the right way.
>
> What I can say by reading your "[PATCH 4/4]" file is that I don't see
> what would not work for the H7. If it compiles on H7, it's likely to
> work as is (except for the GPIO port lists, you'd need other ifdefs
> like
> you do for STM32F429X, or maybe just keep
> stm32f4_gpio_init/stm32f4_gpio_deinit separate for F4 and H7).
>
> Maybe it's as simple as renaming the identifiers from stm32f4_gpio =>
> stm32_gpio for clarity for most functions, and declaring these files
> in
> the H7 scripts.
>
I think I will wait for Karel's opinion about that.
> BTW: by rereading your "[PATCH 4/4]" file I noticed that there is
> something else you need to be careful:
>
> I don't know how the lifecycle of init/deinit is intended to work,
> but
> the stm32f4_gpio_deinit() function is dangerous:
>
> The problem is that if you disable the clock of, say, GPIOA, it will
> also make all alternate function IPs that uses these pins stop
> working.
>
> So if you are using the HAL for example for the Ethernet IP, the
> board
> I'm working with will also call the following functions in it's
> initialization routine:
>
> HAL_ETH_MspInit()
> {
> ...
> __HAL_RCC_GPIOG_CLK_ENABLE();
> __HAL_RCC_GPIOC_CLK_ENABLE();
> __HAL_RCC_GPIOA_CLK_ENABLE();
> ...
> }
>
> So your "stm32f4_gpio_deinit" routine will make all IPs that share
> the
> pins with the GPIO port also stop working.
>
> The trivial fix is of course to make "stm32f4_gpio_deinit" do
> nothing.
>
> Cedric
>
You are right, I forgot that disabling the clock affects the whole
port. I made deinit() do nothing.
Best,
Duc Doan
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Re: [PATCH] bsps/arm/stm32f4 Optimize get pin and change from HAL to LL
Hello Cedric,
On Wed, 2022-07-06 at 16:41 +0200, Cedric Berger wrote:
> One more detail and one question follows:
>
> > static unsigned int EXTIx_IRQn[] = {
> > EXTI0_IRQn,
> > EXTI1_IRQn,
>
> Detail: You should really mark all constants like that "const": on a
> STM32 with little RAM, the constants stays in FLASH and that makes a
> difference.
>
Thanks, I will change that.
> Finally, sorry for my ignorance - I don't know the overall plan on
> that
> project here - but I'm sure that code is 99.5% compatible with the
> STM32H7. Do you plan to enable it there too?
Actually my project is focused on STM32F4, but it is nice that the code
could be extensible to H7. However, I can't think of a good way to use
that code with H7 right now; do you think that the code can be copied
and pasted to H7 BSP? Or is there a better way to share the code among
all STM32 BSPs?
Best,
Duc Doan
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[PATCH] Fix missing cppflags
Please apply this patch in order to build the BSP. Best, Duc Doan --- spec/build/bsps/arm/grp.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml index b33cc9cdda..d4d259b60c 100644 --- a/spec/build/bsps/arm/grp.yml +++ b/spec/build/bsps/arm/grp.yml @@ -1,7 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: group +cflags: [] copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] enabled-by: true includes: [] install: -- 2.36.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] STM32F4 GPIO: Remove old comments
---
bsps/arm/stm32f4/gpio/gpio.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
index b632236d8d..8e3f7c7131 100644
--- a/bsps/arm/stm32f4/gpio/gpio.c
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -330,11 +330,6 @@ rtems_status_code stm32f4_gpio_deinit(rtems_gpio *base) {
return RTEMS_SUCCESSFUL;
}
-/**
- * @note Warning: only one pin can be passed as argument
- * @note If using interrupt mode, use rtems_gpio_configure_interrupt().
- * @note If using alternate mode, use rtems_gpio_configure().
- */
rtems_status_code stm32f4_gpio_set_pin_mode(
rtems_gpio *base,
rtems_gpio_pin_mode mode
@@ -374,9 +369,6 @@ rtems_status_code stm32f4_gpio_set_pin_mode(
return RTEMS_SUCCESSFUL;
}
-/**
- * @note Warning: only one pin can be passed as argument
- */
rtems_status_code stm32f4_gpio_set_pull(
rtems_gpio *base,
rtems_gpio_pull pull
@@ -404,12 +396,6 @@ rtems_status_code stm32f4_gpio_set_pull(
return RTEMS_SUCCESSFUL;
}
-/**
- * TODO
- *
- * @note This function defaults to not using pull resistor.
- * Use rtems_gpio_set_pull() afterwards to change.
- */
rtems_status_code stm32f4_gpio_configure_interrupt(
rtems_gpio *base,
rtems_gpio_isr isr,
--
2.36.1
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[PATCH] bsps/arm/stm32f4 Optimize get pin and change from HAL to LL
Hello Cedric,
Thank you for your feedback. I agree with you that there are places that could
be optimized out. Here is a new patch for that.
Best,
Duc Doan
---
bsps/arm/stm32f4/gpio/gpio.c | 87
1 file changed, 29 insertions(+), 58 deletions(-)
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
index e971f91140..b632236d8d 100644
--- a/bsps/arm/stm32f4/gpio/gpio.c
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -22,9 +22,18 @@
#include
/*** Helpers */
-static stm32f4_gpio *get_gpio_from_base(
-rtems_gpio *base
-);
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define get_gpio_from_base(base) \
+RTEMS_CONTAINER_OF(base, stm32f4_gpio, base)
/*** GPIO API ***/
static rtems_status_code stm32f4_gpio_get(
@@ -115,44 +124,6 @@ static GPIO_TypeDef *GPIOx[] = {
#endif /* STM32F429X */
};
-static uint16_t GPIO_PIN_x[] = {
-GPIO_PIN_0,
-GPIO_PIN_1,
-GPIO_PIN_2,
-GPIO_PIN_3,
-GPIO_PIN_4,
-GPIO_PIN_5,
-GPIO_PIN_6,
-GPIO_PIN_7,
-GPIO_PIN_8,
-GPIO_PIN_9,
-GPIO_PIN_10,
-GPIO_PIN_11,
-GPIO_PIN_12,
-GPIO_PIN_13,
-GPIO_PIN_14,
-GPIO_PIN_15
-};
-
-static uint32_t LL_EXTI_LINE_x[] = {
-LL_EXTI_LINE_0,
-LL_EXTI_LINE_1,
-LL_EXTI_LINE_2,
-LL_EXTI_LINE_3,
-LL_EXTI_LINE_4,
-LL_EXTI_LINE_5,
-LL_EXTI_LINE_6,
-LL_EXTI_LINE_7,
-LL_EXTI_LINE_8,
-LL_EXTI_LINE_9,
-LL_EXTI_LINE_10,
-LL_EXTI_LINE_11,
-LL_EXTI_LINE_12,
-LL_EXTI_LINE_13,
-LL_EXTI_LINE_14,
-LL_EXTI_LINE_15
-};
-
static unsigned int EXTIx_IRQn[] = {
EXTI0_IRQn,
EXTI1_IRQn,
@@ -200,13 +171,13 @@ static unsigned int EXTIx_IRQn[] = {
* @brief Converts pin number from 0-15 to HAL pin mask.
* @param pin is the pin number from 0-15
*/
-#define STM32F4_GET_HAL_GPIO_PIN(pin) (GPIO_PIN_x[( pin )])
+#define STM32F4_GET_HAL_GPIO_PIN(pin) ((uint16_t) (1 << ( pin )))
/**
* @brief Get EXTI Line from pin number 0-15
* @param pin is the pin number from 0-15
*/
-#define STM32F4_GET_LL_EXTI_LINE(pin) (LL_EXTI_LINE_x[( pin )])
+#define STM32F4_GET_LL_EXTI_LINE(pin) (0x1UL << ( pin ))
/**
* @brief Get EXTI IRQ number from pin 0-15
@@ -229,14 +200,6 @@ static stm32f4_interrupt isr_table[16];
void exti_handler(void *arg);
-/* Helpers implementation /
-
-static stm32f4_gpio *get_gpio_from_base(
-rtems_gpio *base
-)
-{
-return RTEMS_CONTAINER_OF(base, stm32f4_gpio, base);
-}
/** STM32F4 GPIO API functions /
@@ -523,7 +486,8 @@ rtems_status_code stm32f4_gpio_remove_interrupt(
rtems_status_code sc = rtems_interrupt_handler_remove(
STM32F4_GET_EXTI_IRQn(gpio->pin),
exti_handler,
-_table[gpio->pin].arg);
+_table[gpio->pin].arg
+);
if (sc == RTEMS_SUCCESSFUL) {
isr_table[gpio->pin] = (stm32f4_interrupt){0};
}
@@ -554,9 +518,12 @@ rtems_status_code stm32f4_gpio_write(
)
{
stm32f4_gpio *gpio = get_gpio_from_base(base);
-uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin);
-HAL_GPIO_WritePin(gpio->port, pin_mask, value);
+if (value)
+LL_GPIO_SetOutputPin(gpio->port, STM32F4_GET_HAL_GPIO_PIN(gpio->pin));
+else
+LL_GPIO_ResetOutputPin(gpio->port,
STM32F4_GET_HAL_GPIO_PIN(gpio->pin));
+
return RTEMS_SUCCESSFUL;
}
@@ -566,9 +533,11 @@ rtems_status_code stm32f4_gpio_read(
)
{
stm32f4_gpio *gpio = get_gpio_from_base(base);
-uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin);
-*value = HAL_GPIO_ReadPin(gpio->port, pin_mask);
+*value = LL_GPIO_IsInputPinSet(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin)
+);
return RTEMS_SUCCESSFUL;
}
@@ -577,9 +546,11 @@ rtems_status_code stm32f4_gpio_toggle(
)
{
stm32f4_gpio *gpio = get_gpio_from_base(base);
-uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin);
-HAL_GPIO_TogglePin(gpio->port, pin_mask);
+LL_GPIO_TogglePin(
+gpio->port,
+STM32F4_GET_HAL_GPIO_PIN(gpio->pin)
+);
return RTEMS_SUCCESSFUL;
}
--
2.36.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 0/4] Creating a new GPIO API and adding implementation for STM32F4 BSP
Hello, Please find my patches here: PATCH 1/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/df255bbc3ff80a596ff329964fe0673f0141a522 PATCH 2/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/5a814d4e5f8af3f78ffcf62a7e7da331843f168a PATCH 3/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/d226d07b8985da2f4135340dac9593089d64b49d PATCH 4/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/f415cc0a2b58f0ae5f2219f2ef96ca7c429d66f6 They were too big that I could not send via email. Best, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 4/4] STM32F4 GPIO: Add GPIO implementation for STM32F4
---
bsps/arm/stm32f4/gpio/gpio.c | 595 ++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/start/bspstart.c | 11 +-
spec/build/bsps/arm/stm32f4/grp.yml | 4 +-
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
7 files changed, 674 insertions(+), 10 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..e971f91140
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,595 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_bsp/arm/stm32f4
+ *
+ * @brief RTEMS GPIO new API implementation for STM32F4.
+ *
+ * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP
+ */
+
+/*
+ * Copyright (c) 2022 Duc Doan
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include
+#include
+#include
+#include
+
+/*** Helpers */
+static stm32f4_gpio *get_gpio_from_base(
+rtems_gpio *base
+);
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_init(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_deinit(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+);
+
+static rtems_status_code stm32f4_gpio_set_pull(
+rtems_gpio *base,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_configure_interrupt(
+rtems_gpio *base,
+rtems_gpio_isr isr,
+void *arg,
+rtems_gpio_interrupt_trig trig,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_remove_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_enable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_disable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_read(
+rtems_gpio *base,
+rtems_gpio_pin_state *value
+);
+
+static rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+);
+
+static rtems_status_code stm32f4_gpio_toggle(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.init = stm32f4_gpio_init,
+.deinit = stm32f4_gpio_deinit,
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef *GPIOx[] = {
+GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
+GPIOF, GPIOG, GPIOH, GPIOI,
+#ifdef STM32F429X
+GPIOJ, GPIOK
+#endif /* STM32F429X */
+};
+
+static uint16_t GPIO_PIN_x[] = {
+GPIO_PIN_0,
+GPIO_PIN_1,
+GPIO_PIN_2,
+GPIO_PIN_3,
+GPIO_PIN_4,
+GPIO_PIN_5,
+GPIO_PIN_6,
+GPIO_PIN_7,
+GPIO_PIN_8,
+GPIO_PIN_9,
+GPIO_PIN_10,
+GPIO_PIN_11,
+GPIO_PIN_12,
+GPIO_PIN_13,
+GPIO_PIN_14,
+GPIO_PIN_15
+};
+
+static uint32_t LL_EXTI_LINE_x[] = {
+LL_EXTI_LINE_0,
+LL_EXTI_LINE_1,
+LL_EXTI_LINE_2,
+LL_EXTI_LINE_3,
+LL_EXTI_LINE_4,
+LL_EXTI_LINE_5,
+LL_EXTI_LINE_6,
+LL_EXTI_LINE_7,
+LL_EXTI_LINE_8,
+LL_EXTI_LINE_9,
+LL_EXTI_LINE_10,
+LL_EXTI_LINE_11,
+LL_EXTI_LINE_12,
+LL_EXTI_LINE_13,
+LL_EXTI_LINE_14,
+LL_EXTI_LINE_15
+};
+
+static unsigned int EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin
[PATCH 3/4] GPIO API: Add GPIO API
---
bsps/include/bsp/gpio2.h| 538
bsps/shared/dev/gpio/gpio.c | 196 +
spec/build/bsps/obj.yml | 2 +-
3 files changed, 735 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e99967cd47
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,538 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_gpio2
+ *
+ * @brief RTEMS GPIO new API definition.
+ */
+
+/*
+* Copyright (c) 2022 Duc Doan
+*
+* The license and distribution terms for this file may be
+* found in the file LICENSE in this distribution or at
+* http://www.rtems.org/license/LICENSE.
+*/
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to an initialize handler.
+ *
+ * This handler could be used to perform some set up steps for
+ * a GPIO object (which means a pin or a port).
+ */
+rtems_status_code (*init)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a deinitialize handler.
+ *
+ * This handler could be used to deinitialize a GPIO object.
+ */
+rtems_status_code (*deinit)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+ * Pin modes are from rtems_gpio_pin_mode enumeration.
+ */
+rtems_status_code (*set_pin_mode)(rtems_gpio *, rtems_gpio_pin_mode);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pull resistor mode.
+ *
+ * Pull resistor modes are from rtems_gpio_pull enumeration.
+ */
+rtems_status_code (*set_pull)(rtems_gpio *, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for configuring
+ *interrupt of a pin.
+ *
+ * This handler should register ISR and its argument, interrupt
+ * trigger mode, and pull resister mode for the pin.
+ *
+ * @note Enabling interrupt should be done in enable_interrupt()
+ * handler.
+ */
+rtems_status_code (*configure_interrupt)(rtems_gpio *, rtems_gpio_isr,
void *, rtems_gpio_interrupt_trig, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for removing
+ *interrupt settings of a pin.
+ *
+ * Interrupt settings can be ISR address, pin configuration, etc.
+ */
+rtems_status_code (*remove_interrupt)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for enabling
+ *
[PATCH 0/4] Creating a new GPIO API and adding implementation for STM32F4 BSP
Hello, This patch adds a new GPIO API that aims at portability. GPIO of STM32F4 BSP has been implemented using this API. The sample application code can be found at https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. Best, Duc Doan .gitignore | 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h| 4066 ++-- bsps/arm/include/core_cm7.h| 582 +- bsps/arm/include/legacy/cmsis_gcc.h| 1375 ++ bsps/arm/include/legacy/core_cm7.h | 2515 +++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/gpio/gpio.c | 595 + bsps/arm/stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ bsps/arm/stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c| 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c| 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c| 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c | 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c | 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c| 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c | 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c| 6864 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c| 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c| 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c | 2484 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c| 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c| 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c| 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c| 3784 bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c| 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c| 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c| 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c | 1308 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c | 2784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 bsps/arm/stm32f4/hal
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Christian, I have been writing the complete API and also implementation for STM32F4. A patch is coming soon. On Mon, 2022-06-27 at 13:33 +0200, Christian MAUDERER wrote: > Regarding pin groups: I think it's worth to think a bit about how the > structure could be extended. You don't have to implement it right now > but you should have a plan what could be possible. > > From my point of view, there are two directions how that could be > implemented: Masks or lists. > > If you have a mask (like 0x00108 for pin 3 and pin 8) it has the > advantage that it works fast for most controllers. Difficult is that > it > adds a limit to the maximum pin number depending on the size of the > mask. With that it works only for a few hardware models. > > The other option is to add a list of pins instead of a mask. That > makes > it inefficient because most controllers will have to collect pins > into > masks and work with that. > > Hm. Difficult. Maybe someone else has a good idea for that in the > next > few days. I am thinking of later adding separate functions that handle pin groups. I think it's quite hard to integrate into current functions because of using virtual pin. I have an assumption that needs confirmation: all microcontrollers (or most of them) have register size equal to word size, and pin masks should be at word size. Is that assumption correct? If so, maybe we can just use unsigned int (or uintptr_t) for pin masks? Best, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Christian and Karel,
On Mon, 2022-06-27 at 08:29 +0200, Christian MAUDERER wrote:
> Please think about whether you want to start at 0 or at 1!
>
I want it to start at 0.
>
> Be really careful with that syntax. If you use increasing numbers
> like
> you suggested, every controller would have to know it's own offest.
> On
> the other hand, if there is a unique number to each pin, you don't
> necessarily need the "ctrl" pointer at all. You can just use
> something like
>
> rtems_gpio_write(60, RTEMS_GPIO_PIN_SET);
>
> That's an advantage from the usage perspective because you don't have
> to
> fetch the GPIO controller and can work with a single pin number.
>
> Disadvantage is a overhead in the API: You have to create some global
> table with GPIO controllers and their first and last pins. That table
> has to be searched for every operation. In the worst case it adds a
> loop
> over the table with one comparison for each entry. Most systems
> should
> only have a hand full of GPIO controller so it's not too much but
> it's a
> lot more than just one pointer de-referencing. There could be methods
> to
> optimize the search so the loop might isn't the best solution. But
> every
> search is slower than if you already have the pointer.
>
> It's more or less a trade-off. There are good arguments for both
> directions. I think I have seen both directions implemented in
> different
> situations.
>
You are right; having both ctrl and virtual pin number is abundant.
Karel's email gave me some inspiration to (hopefully) improve this:
On Mon, 2022-06-27 at 10:25 +0200, Karel Gardas wrote:
> In fact I guess ctrl structure would contain some BSP specific data
> and
> since bsp_gpio_get_ctrl is BSP specific function for f4 that means in
> ctrl you will save your GPIOx and pin number -- e.g. hardware
> specific
> pin representation.
>
> This means on write/read you do not need to map virtual pin ->
> physical
> pin again, but in fact use physical pin from ctrl and be as fast as
> possible.
>
Actually as of now, my ctrl structure only has pointers to handlers and
GPIOx (F4 only). Pin number was not in there, but I am thinking
including pin number inside that structure might work. The changes I
want to make would be:
- ctrl structure will now include both pointers to handlers and BSP-
specific physical port/pin
struct rtems_gpio_ctrl {
rtems_gpio_handlers_t *handlers;
}
struct stm32f4_gpio_ctrl {
rtems_gpio_ctrl base;
GPIO_TypeDef *GPIOx;
uint32_t pin; //physical
}
- I will create 2 internal tables (based on Christian's suggestion) to
store the last pins of each controller and pointers to the get_ctrl()
functions. For example, if STM32 has 16 pins per port and 4 ports in
total, my table would be:
uint32_t table[MAX_CONTROLLERS] = {16, 32, 48, 64};
These numbers and the controller pointers are added to the tables by
calling a register() function for each controller. BSPs need to
implement an initialize() function. The prototype of initialize() is
provided by the GPIO API. initialize() needs to be called before any
GPIO operation in the application.
If GPIO expanders exist, their drivers need to have similar initialize
functions that call the register().
Currently I can only think of binary search as a faster method than a
for loop. rtems_gpio_get_ctrl(virtual_pin) will search for the correct
controller, call the BSP/driver-specific get_ctrl(), and return the
result.
- Because pin number is now in ctrl, functions only need to provide
pointer to ctrl object.
Below is an example program with a fake STM32 with 4 GPIOs/16 pins
each. Two GPIO expanders (exA, exB) are used.
/** API header ***/
void register(void (*get_ctrl) (uint32_t pin), uint32_t num_pins); //
shared, already implemented
void initialize(void); // to be implemented by BSP
/** stm32f4 gpio.c **/
void rtems_gpio_initialize(void) {
register(stm32f4_get_ctrl, 16); // port A
register(stm32f4_get_ctrl, 16); // port B
register(stm32f4_get_ctrl, 16); // port C
register(stm32f4_get_ctrl, 16); // port D
}
/* application blink.c ***/
// initialization
rtems_gpio_initialize();
exA_initialize(); // registers pins to the table
exB_initialize(); // registers pins to the table
uint32_t led_pin = 60; // just a random number
rtems_gpio_ctrl_t *led_ctrl = rtems_gpio_get_ctrl(60);
rtems_gpio_write(led_ctrl, RTEMS_GPIO_PIN_SET);
/* END OF EXAMPLE **/
The only place where the search must be done is now in get_ctrl(), so
read/write operations are still fast. One drawback of this approach
might be the support for pin groups, but currently I have quite little
clue about that.
What do you think about these changes?
Thank you,
Duc Doan
> >
> > This, however, only ret
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Karel and Christian, I am thinking of this way: referring to a pin using a number. Each BSP will map that pin number to its specific port and pin. For example, for STM32F4 which has 16 pins per GPIO port, pin 6 will correspond to GPIOA pin 6, and pin 20 will correspond to GPIOB pin 4. The get controller function will be as follow: rtems_gpio_ctrl_t *bsp_gpio_get_ctrl(uint32_t pin); This function must be implemented by each BSP. This will take the pin number and return the corresponding controller object. The example application could be as follow: rtems_gpio_ctrl_t *ctrl0 = bsp_gpio_get_ctrl(60); //corresponds to GPIOD pin 12 on F4 rtems_gpio_write(ctrl, 60, RTEMS_GPIO_PIN_SET); This, however, only returns integrated GPIO from a BSP. In order to use a GPIO expansion, a separate function must be used. Each GPIO expander driver will have its own get_ctrl function. For example, when using 2 different expanders exA and exB: rtems_gpio_ctrl_t *exA_ctrl = exA_get_ctrl(pin); rtems_gpio_ctrl_t *exB_ctrl = exB_get_ctrl(pin); I think this method will assure that it compiles and works on all BSPs but needs an additional function to get the controller of an expander. A drawback might be added computation because of translating abstract pin number to physical pin/port. What do you think about this? Best, Duc Doan On Sun, 2022-06-26 at 20:48 +0200, Karel Gardas wrote: > On 6/26/22 10:49, Duc Doan wrote: > > > > #define rtems_gpio_get_ctrl(_driver, _arg, _out) \ > > > > _driver##_gpio_get_ctrl( _arg , _out ) > > > > > > > > In the application code: > > > > > > > > rtems_gpio_get_ctrl(stm32f4, GPIOD, _ctrl); > > > > rtems_gpio_get_ctrl(stm32f4, GPIOA, _ctrl); > > > > > > It's only a different method of writing the same. It won't solve > > > Karels > > > problem because it still wouldn't compile on another BSP. > > > > > > > Do you mean this application code should compile on other BSPs > > without > > changing the source? > > Yes, that's exactly what portability means and that's exactly what is > desired outcome of the API here -- if I'm not mistaken in your > project > outcome specification. :-) > > I'm not expert here, so please bear with me, but as I see it, you > will > need to come with some abstraction for groups and pins and write API > around it. Then in BSP you will perform/provide a mapping between > your > abstracted group/pins construct and between actual hardware. This > way, > if I take example from stm32f4 and try to compile on rpi4, it will > compile well -- but it will not run well (probably!) of course. But > API > wise, it will compile. Now, to make it run, I'll need to connect LED > example following BSP specific mapping and for that I need to consult > BSP docs. > > > I am a bit confused about that because I thought > > at least we still need to specify the pin/port. And if we have > > multiple > > GPIO controllers, we still need to select one right? > > Yes, and this needs to be done in abstract manner mapped down into > actual BSP implementation code. Abstract mapping here ensure > portability > between BSPs/boards. > > E.g. for stm32f4 you do not select GPIOA group and pin1, but you > select > group 0 and pin 1 and in f4 BSP this group 0 is mapped to GPIOA and > pin > 1 is mapped to its pin 1. -- something like that. > > Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Christian and Karel, On Sun, 2022-06-26 at 10:02 +0200, o...@c-mauderer.de wrote: > Hello Karel and Duc, > > Am 26.06.22 um 09:24 schrieb Duc Doan: > > Hello Karel, > > > > I came up with this solution: making a macro that returns a > > function > > depending on driver/BSP name. > > > > /** > > * @brief Get an GPIO control object. > > * > > * This macro requires BSPs/drivers to correctly implement > > * function _gpio_get_ctrl(void *arg, > > * rtems_gpio_ctrl_t **out). > > * > > * @param _driver is the name of the BSP/GPIO driver > > * @param[in] _arg is the void pointer to an argument type > > * defined by BSP/driver > > * @param[out] _out is the pointer to the pointer to where > > * the output object will be stored > > */ > > #define rtems_gpio_get_ctrl(_driver, _arg, _out) \ > > _driver##_gpio_get_ctrl( _arg , _out ) > > > > In the application code: > > > > rtems_gpio_get_ctrl(stm32f4, GPIOD, _ctrl); > > rtems_gpio_get_ctrl(stm32f4, GPIOA, _ctrl); > > It's only a different method of writing the same. It won't solve > Karels > problem because it still wouldn't compile on another BSP. > Do you mean this application code should compile on other BSPs without changing the source? I am a bit confused about that because I thought at least we still need to specify the pin/port. And if we have multiple GPIO controllers, we still need to select one right? Best, Duc Doan > > > > What do you think about this? > > > > Best, > > > > Duc Doan > > > > On Sat, 2022-06-25 at 21:46 +0200, Karel Gardas wrote: > > > > > > Hello Duc, > > > > > > one reminder, your API should be more or less portable. That > > > means > > > the > > > example which you produce as a testing example should be API-wise > > > portable between various BSPs. Is that clear? > > > > > > I know, I know, sometimes user led 1 on F4 is on different > > > port/pin > > > on > > > F7 and then on H7 you get it on even different port/pin, but! > > > > > > > stm32f4_gpio_get_ctrl(GPIOD, ); > > > > > > do you expect this to be called from app running on RPi4 for > > > example? > > > Or > > > on beagle bone white? Or on stm32h757i-eval board? > > > > > > Please generalize and make that bit portable too. > > I think that approach is due to my suggestion to have a low overhead > and > use the pointers more or less directly. A really portable method > would > be to use for example device files. But for GPIO that would add a lot > of > overhead which isn't good for a fast interface like that. > > Another problem that I added for Duc is that I told that I might want > to > register I2C GPIO expanders during the application startup. > > A possibility could be to have some general bsp_gpio_get_ctrl(...) > function that returns the controllers for the integrated GPIOs of a > chip > regardless of the chip. If you have an extra I2C expander, that will > be > a separate function. > > Best regards > > Christian > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Christian, On Sun, 2022-06-26 at 09:50 +0200, o...@c-mauderer.de wrote: > Is setting the pull really independent of the mode? Most controller > that > I know have a pull-Up only on Inputs. Sometimes on an Open-Drain > output. > Sometimes in another controller (but you might ignore that option). > Somethimes you can also set a different strength like 10k pull-up or > 100k pull-up. > > Best regards > > Christian On STM32 I saw that there is open drain output, so pull resister could be necessary. I think separating the pull from the mode makes it more flexible without complicating the configuration too much. About the strength, I think it should be in the BSP/driver-specific configuration structure because not every controller has it. Best, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Proposal for new GPIO API and example implementation for STM32F4 BSP
Hello Karel, I came up with this solution: making a macro that returns a function depending on driver/BSP name. /** * @brief Get an GPIO control object. * * This macro requires BSPs/drivers to correctly implement * function _gpio_get_ctrl(void *arg, * rtems_gpio_ctrl_t **out). * * @param _driver is the name of the BSP/GPIO driver * @param[in] _arg is the void pointer to an argument type *defined by BSP/driver * @param[out] _out is the pointer to the pointer to where * the output object will be stored */ #define rtems_gpio_get_ctrl(_driver, _arg, _out) \ _driver##_gpio_get_ctrl( _arg , _out ) In the application code: rtems_gpio_get_ctrl(stm32f4, GPIOD, _ctrl); rtems_gpio_get_ctrl(stm32f4, GPIOA, _ctrl); What do you think about this? Best, Duc Doan On Sat, 2022-06-25 at 21:46 +0200, Karel Gardas wrote: > > Hello Duc, > > one reminder, your API should be more or less portable. That means > the > example which you produce as a testing example should be API-wise > portable between various BSPs. Is that clear? > > I know, I know, sometimes user led 1 on F4 is on different port/pin > on > F7 and then on H7 you get it on even different port/pin, but! > > > stm32f4_gpio_get_ctrl(GPIOD, ); > > do you expect this to be called from app running on RPi4 for example? > Or > on beagle bone white? Or on stm32h757i-eval board? > > Please generalize and make that bit portable too. > > Thanks, > Karel > > On 6/25/22 15:00, Duc Doan wrote: > > Hello Christian, > > > > I forgot to send the sample code. Here it a code to turn on an LED: > > > > /*/ > > > > // Obtain the pointer to the instance (port D) > > rtems_gpio_ctrl_t *ctrl; > > stm32f4_gpio_get_ctrl(GPIOD, ); > > > > // enable clocks for port D > > rtems_gpio_initialize(ctrl); > > > > // configure the pin > > rtems_gpio_set_pin_mode(ctrl, _PIN, > > RTEMS_GPIO_PINMODE_OUTPUT_PP); > > rtems_gpio_set_pull(ctrl, _PIN, RTEMS_GPIO_PULLUP); > > > > // output to LED > > rtems_gpio_write(ctrl, _PIN, RTEMS_GPIO_PIN_SET); > > > > /*/ > > > > Best, > > > > Duc Doan > > ___ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
