From: Christian Mauderer <christian.maude...@embedded-brains.de>
---
.../contrib/libraries/libboard/source/board_memories.c | 10 ++++++----
.../atsam/contrib/libraries/libchip/source/sdramc.c | 4 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
b/bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
index e2f04caa8c..354196ab95 100644
--- a/bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
+++ b/bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
@@ -196,7 +196,8 @@ void BOARD_ConfigureSdram(void)
SDRAMC->SDRAMC_MDR = BOARD_Sdram_Config.sdramc_mdr;
#endif /* __rtems__ */
- /* 4. A minimum pause of 200 ��s is provided to precede any signal
toggle.*/
+ /* 4. A minimum pause of 200 microseconds is provided to precede any
+ signal toggle.*/
for (i = 0; i < 100000; i++);
/* 5. (1)A NOP command is issued to the SDRAM devices. The application
must
@@ -277,10 +278,11 @@ void BOARD_ConfigureSdram(void)
/* 11. Write the refresh rate into the count field in the SDRAMC Refresh
Timer register. (Refresh rate = delay between refresh cycles).
- The SDRAM device requires a refresh every 15.625 ��s or 7.81 ��s.
+ The SDRAM device requires a refresh every 15.625 or 7.81 microseconds.
With a 100 MHz frequency, the Refresh Timer Counter Register must be set
- with the value 1562(15.625 ��s x 100 MHz) or 781(7.81 ��s x 100 MHz). */
- // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ��s
+ with the value 1562(15.625 us x 100 MHz) or 781(7.81 us x 100 MHz). */
+ /* For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625
+ microseconds. */
/* ((32 x 10(^-3))/2048) x150 x (10^6) */
#ifndef __rtems__
SDRAMC->SDRAMC_TR = 1562;
diff --git a/bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
b/bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
index ab5f2d8ec8..aca4a4448e 100644
--- a/bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
+++ b/bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
@@ -128,8 +128,8 @@ extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
/* Step 4 */
- /* A minimum pause of 200 ��s is provided to precede any signal toggle.
- (6 core cycles per iteration) */
+ /* A minimum pause of 200 microseconds is provided to precede any signal
+ toggle. (6 core cycles per iteration) */
for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);
/* Step 5. */
--
2.29.2
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