Re: [PATCH v2 1/6] cpukit/aarch64: Use correct interrupt level types

2021-10-01 Thread Kinsey Moore 

On 9/30/2021 23:24, Gedare Bloom wrote:

If the rest of the patch set isn't ready, please split this out for
separate submission. It looks fine to me.


It appears not. I'll go ahead and get this patch committed and remove it 
from the set.



Thanks,

Kinsey

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH v2 1/6] cpukit/aarch64: Use correct interrupt level types

2021-10-01 Thread Sebastian Huber 

On 01/10/2021 06:24, Gedare Bloom wrote:

If the rest of the patch set isn't ready, please split this out for
separate submission. It looks fine to me.


Yes, sorry for the slow review. I somehow overlooked this patch set.

--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH v2 1/6] cpukit/aarch64: Use correct interrupt level types

2021-09-30 Thread Gedare Bloom 
If the rest of the patch set isn't ready, please split this out for
separate submission. It looks fine to me.

On Wed, Sep 22, 2021 at 6:17 PM Kinsey Moore  wrote:
>
> All other architectures use uint32_t for interrupt levels and there is
> no reason not to do so on AArch64.
> ---
>  cpukit/score/cpu/aarch64/cpu.c | 4 ++--
>  cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
> index d09403a349..b36f55ae17 100644
> --- a/cpukit/score/cpu/aarch64/cpu.c
> +++ b/cpukit/score/cpu/aarch64/cpu.c
> @@ -146,7 +146,7 @@ void _CPU_Context_Initialize(
>}
>  }
>
> -void _CPU_ISR_Set_level( uint64_t level )
> +void _CPU_ISR_Set_level( uint32_t level )
>  {
>/* Set the mask bit if interrupts are disabled */
>level = level ? AARCH64_PSTATE_I : 0;
> @@ -156,7 +156,7 @@ void _CPU_ISR_Set_level( uint64_t level )
>);
>  }
>
> -uint64_t _CPU_ISR_Get_level( void )
> +uint32_t _CPU_ISR_Get_level( void )
>  {
>uint64_t level;
>
> diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
> b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> index 82f74193a2..ae7e2bdcba 100644
> --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> @@ -204,9 +204,9 @@ static inline void 
> _AARCH64_Instruction_synchronization_barrier( void )
>__asm__ volatile ( "isb" : : : "memory" );
>  }
>
> -void _CPU_ISR_Set_level( uint64_t level );
> +void _CPU_ISR_Set_level( uint32_t level );
>
> -uint64_t _CPU_ISR_Get_level( void );
> +uint32_t _CPU_ISR_Get_level( void );
>
>  #if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
>  uint64_t AArch64_interrupt_disable( void );
> --
> 2.30.2
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH v2 1/6] cpukit/aarch64: Use correct interrupt level types

2021-09-22 Thread Kinsey Moore 
All other architectures use uint32_t for interrupt levels and there is
no reason not to do so on AArch64.
---
 cpukit/score/cpu/aarch64/cpu.c | 4 ++--
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index d09403a349..b36f55ae17 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -146,7 +146,7 @@ void _CPU_Context_Initialize(
   }
 }
 
-void _CPU_ISR_Set_level( uint64_t level )
+void _CPU_ISR_Set_level( uint32_t level )
 {
   /* Set the mask bit if interrupts are disabled */
   level = level ? AARCH64_PSTATE_I : 0;
@@ -156,7 +156,7 @@ void _CPU_ISR_Set_level( uint64_t level )
   );
 }
 
-uint64_t _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
 {
   uint64_t level;
 
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index 82f74193a2..ae7e2bdcba 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -204,9 +204,9 @@ static inline void 
_AARCH64_Instruction_synchronization_barrier( void )
   __asm__ volatile ( "isb" : : : "memory" );
 }
 
-void _CPU_ISR_Set_level( uint64_t level );
+void _CPU_ISR_Set_level( uint32_t level );
 
-uint64_t _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
 
 #if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
 uint64_t AArch64_interrupt_disable( void );
-- 
2.30.2

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel