Re: [Discuss-gnuradio] Low-cost hardware options
On 15.01.2011 03:10, Marcus D. Leech wrote: I've posted my latest thoughts at: http://www.sbrac.org/files/digital_receiver2.pdf This version has some BOM cost estimates for most of the items, and shows a new I counted $75, let's say $100 (incl. voltage conrollers, R/C), plus $50 for PCB (if we order more units). Is $150 a realistic value for material and PCB? Plus $150 to $250 for a cheap FPGA board, or even a cheaper USB board. Not too much for a hobby instrument. But I would suggest an option to switch to a second input, directly into the ADC, to cover the range DC to 10 MHz, or to attach an external RF, IF (e.g. from an amateur radio). Or a second board without mixer, just replacing it on the FMC connector, similar to the USRP daughterboard system. ADC by a factor of 3, but it would eliminate the need for a FPGA on the host interface side of that FMC connector. So, you're trading a more expensive digital-receiver section for a cheaper host interface section. For example, by using an AD6652, one could easily conceive of nothing more than a cheap EZ-FX2 USB-2.0 implementation on the host-interface side. I looked at the CY7C68013 EZ-USB FX2 data sheet. Is it true that we wouldn't need any FPGA glue logic to control the receiver, for the frequency synthesizer, flow control etc. ? There are lots of IO pins and busses on the FX2. The embedded 8051 µC could be used to control the receiver. For at least USB-3.0 and 1GiGe, you pretty-much *need* an FPGA on the host-interface board to do all the relevant protocol goop anyway, so perhaps making that FPGA large enough I think for USB you don't have to deal with the protocol. USB chips will handle this, similar to the EZ-USB. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Low-cost hardware options
On 01/15/2011 05:01 AM, Moeller wrote: But I would suggest an option to switch to a second input, directly into the ADC, to cover the range DC to 10 MHz, or to attach an external RF, IF (e.g. from an amateur radio). Or a second board without mixer, just replacing it on the FMC connector, similar to the USRP daughterboard system. Yes, I considered that, too, and it would be cheap to do. I'll update the block diagram. I looked at the CY7C68013 EZ-USB FX2 data sheet. Is it true that we wouldn't need any FPGA glue logic to control the receiver, for the frequency synthesizer, flow control etc. ? There are lots of IO pins and busses on the FX2. The embedded 8051 µC could be used to control the receiver. We'd likely need a *little* bit of glue logic to interface to a smart ADC like the AD6652, something that a little CPLD would work just fine for. I think for USB you don't have to deal with the protocol. USB chips will handle this, similar to the EZ-USB. There aren't a lot of USB-3.0 chips out at the moment--most implementations that I can see are FPGA-based, hence the comment. But something like the EZ-FX2, but support USB-3.0 instead may emerge at some point. Don't know--anyone else have a good view into where USB-3.0 is going? -- Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Low-cost hardware options
On 01/15/2011 08:53 AM, Marcus D. Leech wrote: Yes, I considered that, too, and it would be cheap to do. I'll update the block diagram. Updated the diagram to include external (non-mixed) input capability, right before the anti-alias filters, using a Hitite RF switch. Also upgraded to the next speed-grade of the ADC, to give 40Msps, and changed the spec on the anti-alias filters to suit. http://www.sbrac.org/files/digital_receiver2.pdf With PCB, the BOM costs shouldn't be more than about $125.00 for this board. With a larger physical board, you might be able to route this on only two layers, making the PCB relatively cheap. So, let me propose that we put some stakes in the ground, to focus the discussion a little: o Assume a dumb ADC o The AD9238 is still in production, available through Digikey, and available in the 40Msps version for $18.65. o Assume that some kind of FPGA will interface to the outside world, and provide first-level DSP services (DDC, CIC Decimator and FIR filtering, etc). o Assume a generic interface to an FPGA host-transport platform o I've shown an FMC connector, which is fine for boards like the SP601 o The Nexsys2 from Digilent uses a different connector o Choose one and have a super-cheap adapter card? o Have both connectors on the board, and be clever? [Could become a routing nightmare] I'll observe that the Nexsys2 provides academic discounts of about $50.00 on the Nexsys2, which could be a real boost to the starving-student crowd. -- Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Low-cost hardware options
Also upgraded to the next speed-grade of the ADC, to give 40Msps... You spec'd only a 12-bit ADC. In my naive view, resolution seems like it's more important to SDR than samples per second. Resolution is how you avoid losing weak signals when you are of necessity sampling a wide band. Can we improve on this to get a 14- or 16-bit ADC, perhaps with a lower sampling rate, at a reasonable price? As I recall from early USRP days, clock jitter makes a real mess of doing anything important with an SDR. If you can't trust your clock, you don't know when your samples happened, which makes all the computation a lot fuzzier. That's why the USRP didn't synthesize its sampling clock -- nobody back then built a synthesized clock that had low enough jitter. Does this ADF4351 qualify? And what kinds of interactions are there between that clock and the clock on the ADC? Shouldn't the downsampler and the digitizer both be using the same clock, or a clock that's derived from the same clock? Is there a way to use i2c programmable width filters instead of the 20 MHz lowpass filters, to narrow the bandwidth of the signal being digitized down to just the range of interest? This would help ameliorate the low-res ADC by filtering out nearby loud-yet-uninteresting signals. Finally, don't assume that a USB3 chip will easily support downgrading to a USB2 connection. It ought to be that way, but might not be. The EZ-FX2 chip does support both USB1 and USB2, but in the last ten years, nobody ever got around to programming the USRP firmware to actually make it work with USB1. That became somewhat moot as USB2 became standard in everything. Similarly, the GigE interface on the USRP2 has never supported downgrading to 100 Mbit Ethernet, even though that's part of the GigE spec. However, now that they've switched to using a UDP-based protocol rather than an Ethernet-frame-based protocol (finally - hooray!), you can plug the USRP2 into a switch. Switches all allow 10, 100, and 1000 Mbit/sec Ethernet to communicate. If you're going to put 1GE on this device rather than USB2 or USB3, I suggest including a switch chip too, so it will transparently talk to any speed of Ethernet. GigE is still too uncommon on laptops these days. John ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Low-cost hardware options
On Sat, Jan 15, 2011 at 9:56 PM, John Gilmore g...@toad.com wrote: Also upgraded to the next speed-grade of the ADC, to give 40Msps... You spec'd only a 12-bit ADC. In my naive view, resolution seems like it's more important to SDR than samples per second. Resolution is how you avoid losing weak signals when you are of necessity sampling a wide band. Can we improve on this to get a 14- or 16-bit ADC, perhaps with a lower sampling rate, at a reasonable price? It's all about power, right? So you may sacrifice sample rate for accuracy, but you can gain those bits back in the digital domain via filtering. Only if you really want to see more than the 72dB of dynamic range the ADC supplies do you somewhat get screwed, I think. I've heard of people recovering very narrowband signals with narrowband blockers where the desired signal is below the dynamic range at their fastest sample rate, but through digital filtering were able to bring the signal out of that noise floor. I haven't done it myself. In my opinion, being able to play with emerging wireless standards in the 1MHz to 20MHz or even 40MHz bandwidth area is more appealing than being able to pull them from the muck. I was reading about the WHDI wireless HD technology and thought it would be very interesting to read about and sample. Link here: http://www.whdi.org/Technology/ I know plenty of people will disagree with me so it's just an opinion. As I recall from early USRP days, clock jitter makes a real mess of doing anything important with an SDR. If you can't trust your clock, you don't know when your samples happened, which makes all the computation a lot fuzzier. That's why the USRP didn't synthesize its sampling clock -- nobody back then built a synthesized clock that had low enough jitter. Does this ADF4351 qualify? And what kinds of interactions are there between that clock and the clock on the ADC? Shouldn't the downsampler and the digitizer both be using the same clock, or a clock that's derived from the same clock? Clock jitter is pretty detrimental with a high IF, but with baseband sampling, I can't imagine even the clock an FPGA synthesizes to be too terrible. You may not be able to do 1024-QAM, but for modest modulations I am sure it should be fine. On the other hand, Silicon Labs seems to make some pretty spectacular clock synthesis chips with single-digit picosecond RMS or even sub picosecond RMS jitter numbers. Is there a way to use i2c programmable width filters instead of the 20 MHz lowpass filters, to narrow the bandwidth of the signal being digitized down to just the range of interest? This would help ameliorate the low-res ADC by filtering out nearby loud-yet-uninteresting signals. By that time, there's a good chance the damage has been done with the RF mixing. The real way, on the RX side of things, would be to use preselector filters so mixing products and other bad things don't get in the way. This is especially true for direct conversion receivers where you have DC, gain and phase imbalances coming into the ADC. When you have large blockers or jammers, they replicate themselves through those imbalances and it just becomes a huge mess to try to deal with. But, back to your point about I2C programmable width filters, Skyworks makes some that are SPI. The SKY73202-364LF is one for direct conversion receivers or for reconstruction filters for DACs. Link here: http://www.skyworksinc.com/Product.aspx?ProductID=400 Relatively inexpensive as well. Finally, don't assume that a USB3 chip will easily support downgrading to a USB2 connection. It ought to be that way, but might not be. The EZ-FX2 chip does support both USB1 and USB2, but in the last ten years, nobody ever got around to programming the USRP firmware to actually make it work with USB1. That became somewhat moot as USB2 became standard in everything. Superspeed USB explicitly states that there are two connections - the superspeed wires and the USB2 wires. When superspeed is present, both methods of communication must be supported. In fact, it even states that they can be used in tandem. Similarly, the GigE interface on the USRP2 has never supported downgrading to 100 Mbit Ethernet, even though that's part of the GigE spec. However, now that they've switched to using a UDP-based protocol rather than an Ethernet-frame-based protocol (finally - hooray!), you can plug the USRP2 into a switch. Switches all allow 10, 100, and 1000 Mbit/sec Ethernet to communicate. If you're going to put 1GE on this device rather than USB2 or USB3, I suggest including a switch chip too, so it will transparently talk to any speed of Ethernet. GigE is still too uncommon on laptops these days. John Brian ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Low-cost hardware options
On Sat, 15 Jan 2011, Brian Padalino wrote: It's all about power, right? So you may sacrifice sample rate for accuracy, but you can gain those bits back in the digital domain via filtering. Only if you really want to see more than the 72dB of dynamic range the ADC supplies do you somewhat get screwed, I think. I've heard of people recovering very narrowband signals with narrowband blockers where the desired signal is below the dynamic range at their fastest sample rate, but through digital filtering were able to bring the signal out of that noise floor. I haven't done it myself. Of course. This is the principle that underlies Sigma-Delta ADCs. In my view wider bandwidth and lower resolution is the way to go because it gives the user a usefull trade off. That is, the user can opt for a full bandwidth of F_s / 2 at the ADC's resolution or a narrower bandwidth with processing gain. The processing gain is F_s / (2 * B) where B is the bandwidth of the discrete filter. Having said that it is usefull to maximize 2 * F_s / b with respect to purchase cost where b is the number of ADC bits. Cheers -- Peter F Bradshaw: http://www.exadios.com (public keys avaliable there). Personal site: http://personal.exadios.com I love truth, and the way the government still uses it occasionally to keep us guessing. - Sam Kekovich. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
[Discuss-gnuradio] Low-cost hardware options
I've posted my latest thoughts at: http://www.sbrac.org/files/digital_receiver2.pdf This version has some BOM cost estimates for most of the items, and shows a new PLL, the ADF4351, which is a new chip from AD, coming out later this spring, which is pin compatible with the ADF4350, and includes a lower minimum output frequency, which means extending the range downwards to about 18MHz from about 68MHz. Cool. Going to a AD6652 (which has built-in DDC and CIC decimators) increases the price of the ADC by a factor of 3, but it would eliminate the need for a FPGA on the host interface side of that FMC connector. So, you're trading a more expensive digital-receiver section for a cheaper host interface section. For example, by using an AD6652, one could easily conceive of nothing more than a cheap EZ-FX2 USB-2.0 implementation on the host-interface side. For at least USB-3.0 and 1GiGe, you pretty-much *need* an FPGA on the host-interface board to do all the relevant protocol goop anyway, so perhaps making that FPGA large enough to do DDC and CIC decimation as well as the host interface goop is the right trade-off. Love to hear more opinions -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
