[Bug 42490] NUTMEG DP to VGA bridge not working

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42490

Alex Deucher  changed:

   What|Removed |Added

 AssignedTo|xorg-driver-ati at lists.x.org |dri-devel at 
lists.freedesktop
   ||.org
  QAContact|xorg-team at lists.x.org   |
Summary|[drm:atom_op_jump] *ERROR*  |NUTMEG DP to VGA bridge not
   |atombios stuck in loop for  |working
   |more than 5secs aborting|
Product|xorg|DRI
  Component|Driver/Radeon   |DRM/Radeon

--- Comment #6 from Alex Deucher  2011-11-02 14:51:58 PDT 
---
The DP to VGA bridge chips on a llano APUs are problematic in a lot of cases. 
You might try a newer kernel or use a digital port (HDMI, DP, DVI) in the
meantime.

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[Bug 31943] drm EDID checking is too strict

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=31943

--- Comment #18 from Kai-Uwe Behrmann  2011-11-02 14:27:16 PDT 
---
Is this duplicate?
https://bugs.freedesktop.org/show_bug.cgi?id=32343

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[Bug 28426] hardware cursor corruption with radeon+kms

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28426

--- Comment #9 from Francesco R  2011-11-02 12:39:09 
PDT ---
sorry, I've switched to nvidia, cannot test

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[PATCH 8/8] drm/ttm: introduce callback for ttm_tt populate & unpopulate

[j.gli...@gmail.com]

From: Jerome Glisse 

Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.

Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/nouveau/nouveau_bo.c   |3 +
 drivers/gpu/drm/radeon/radeon_ttm.c|2 +
 drivers/gpu/drm/ttm/ttm_bo_util.c  |   31 ++-
 drivers/gpu/drm/ttm/ttm_bo_vm.c|   13 ++--
 drivers/gpu/drm/ttm/ttm_page_alloc.c   |   42 ++
 drivers/gpu/drm/ttm/ttm_tt.c   |   97 +++
 drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c |3 +
 include/drm/ttm/ttm_bo_driver.h|   41 --
 include/drm/ttm/ttm_page_alloc.h   |   18 ++
 9 files changed, 125 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index b060fa4..7e5ca3f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -28,6 +28,7 @@
  */

 #include "drmP.h"
+#include "ttm/ttm_page_alloc.h"

 #include "nouveau_drm.h"
 #include "nouveau_drv.h"
@@ -1050,6 +1051,8 @@ nouveau_bo_fence(struct nouveau_bo *nvbo, struct 
nouveau_fence *fence)

 struct ttm_bo_driver nouveau_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
+   .ttm_tt_populate = _page_alloc_ttm_tt_populate,
+   .ttm_tt_unpopulate = _page_alloc_ttm_tt_unpopulate,
.invalidate_caches = nouveau_bo_invalidate_caches,
.init_mem_type = nouveau_bo_init_mem_type,
.evict_flags = nouveau_bo_evict_flags,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 53ff62b..490afce 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -584,6 +584,8 @@ struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device 
*bdev,

 static struct ttm_bo_driver radeon_bo_driver = {
.ttm_tt_create = _ttm_tt_create,
+   .ttm_tt_populate = _page_alloc_ttm_tt_populate,
+   .ttm_tt_unpopulate = _page_alloc_ttm_tt_unpopulate,
.invalidate_caches = _invalidate_caches,
.init_mem_type = _init_mem_type,
.evict_flags = _evict_flags,
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 082fcae..60f204d 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -244,7 +244,7 @@ static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void 
*src,
unsigned long page,
pgprot_t prot)
 {
-   struct page *d = ttm_tt_get_page(ttm, page);
+   struct page *d = ttm->pages[page];
void *dst;

if (!d)
@@ -281,7 +281,7 @@ static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void 
*dst,
unsigned long page,
pgprot_t prot)
 {
-   struct page *s = ttm_tt_get_page(ttm, page);
+   struct page *s = ttm->pages[page];
void *src;

if (!s)
@@ -342,6 +342,12 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
if (old_iomap == NULL && ttm == NULL)
goto out2;

+   if (ttm->state == tt_unpopulated) {
+   ret = ttm->bdev->driver->ttm_tt_populate(ttm);
+   if (ret)
+   goto out1;
+   }
+
add = 0;
dir = 1;

@@ -502,10 +508,16 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
 {
struct ttm_mem_reg *mem = >mem; pgprot_t prot;
struct ttm_tt *ttm = bo->ttm;
-   struct page *d;
-   int i;
+   int ret;

BUG_ON(!ttm);
+
+   if (ttm->state == tt_unpopulated) {
+   ret = ttm->bdev->driver->ttm_tt_populate(ttm);
+   if (ret)
+   return ret;
+   }
+
if (num_pages == 1 && (mem->placement & TTM_PL_FLAG_CACHED)) {
/*
 * We're mapping a single page, and the desired
@@ -513,18 +525,9 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
 */

map->bo_kmap_type = ttm_bo_map_kmap;
-   map->page = ttm_tt_get_page(ttm, start_page);
+   map->page = ttm->pages[start_page];
map->virtual = kmap(map->page);
} else {
-   /*
-* Populate the part we're mapping;
-*/
-   for (i = start_page; i < start_page + num_pages; ++i) {
-   d = ttm_tt_get_page(ttm, i);
-   if (!d)
-   return -ENOMEM;
-   }
-
/*
 * We need to use vmap to get the desired page protection
 * or to make the buffer object look contiguous.
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 221b924..bc1d751 100644
--- 

[PATCH 7/8] drm/ttm: merge ttm_backend and ttm_tt

[j.gli...@gmail.com]

From: Jerome Glisse 

ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/nouveau/nouveau_bo.c|   14 ++-
 drivers/gpu/drm/nouveau/nouveau_drv.h   |5 +-
 drivers/gpu/drm/nouveau/nouveau_sgdma.c |  188 --
 drivers/gpu/drm/radeon/radeon_ttm.c |  222 ---
 drivers/gpu/drm/ttm/ttm_agp_backend.c   |   88 +
 drivers/gpu/drm/ttm/ttm_bo.c|9 +-
 drivers/gpu/drm/ttm/ttm_tt.c|   59 ++---
 drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c  |   66 +++--
 include/drm/ttm/ttm_bo_driver.h |  104 ++-
 9 files changed, 295 insertions(+), 460 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 7226f41..b060fa4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -343,8 +343,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, 
u32 val)
*mem = val;
 }

-static struct ttm_backend *
-nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
+static struct ttm_tt *
+nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
+ unsigned long size, uint32_t page_flags,
+ struct page *dummy_read_page)
 {
struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
struct drm_device *dev = dev_priv->dev;
@@ -352,11 +354,13 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device 
*bdev)
switch (dev_priv->gart_info.type) {
 #if __OS_HAS_AGP
case NOUVEAU_GART_AGP:
-   return ttm_agp_backend_init(bdev, dev->agp->bridge);
+   return ttm_agp_tt_create(bdev, dev->agp->bridge,
+size, page_flags, dummy_read_page);
 #endif
case NOUVEAU_GART_PDMA:
case NOUVEAU_GART_HW:
-   return nouveau_sgdma_init_ttm(dev);
+   return nouveau_sgdma_create_ttm(bdev, size, page_flags,
+   dummy_read_page);
default:
NV_ERROR(dev, "Unknown GART type %d\n",
 dev_priv->gart_info.type);
@@ -1045,7 +1049,7 @@ nouveau_bo_fence(struct nouveau_bo *nvbo, struct 
nouveau_fence *fence)
 }

 struct ttm_bo_driver nouveau_bo_driver = {
-   .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
+   .ttm_tt_create = _ttm_tt_create,
.invalidate_caches = nouveau_bo_invalidate_caches,
.init_mem_type = nouveau_bo_init_mem_type,
.evict_flags = nouveau_bo_evict_flags,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h 
b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 29837da..0c53e39 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1000,7 +1000,10 @@ extern int nouveau_sgdma_init(struct drm_device *);
 extern void nouveau_sgdma_takedown(struct drm_device *);
 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
   uint32_t offset);
-extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
+extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
+  unsigned long size,
+  uint32_t page_flags,
+  struct page *dummy_read_page);

 /* nouveau_debugfs.c */
 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c 
b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index b75258a..bc2ab90 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -8,44 +8,23 @@
 #define NV_CTXDMA_PAGE_MASK  (NV_CTXDMA_PAGE_SIZE - 1)

 struct nouveau_sgdma_be {
-   struct ttm_backend backend;
+   struct ttm_tt ttm;
struct drm_device *dev;
-
-   dma_addr_t *pages;
-   unsigned nr_pages;
-   bool unmap_pages;
-
u64 offset;
-   bool bound;
 };

 static int
-nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
-  struct page **pages, struct page *dummy_read_page,
-  dma_addr_t *dma_addrs)
+nouveau_sgdma_dma_map(struct ttm_tt *ttm)
 {
-   struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
+   struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
struct drm_device *dev = nvbe->dev;
int i;

-   NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
-
-   nvbe->pages = dma_addrs;
-   nvbe->nr_pages = num_pages;
-   nvbe->unmap_pages = true;
-
-   /* this code path isn't called and is incorrect anyways */
-   if (0) { /* dma_addrs[0] != DMA_ERROR_CODE) { */
-   

[PATCH 6/8] drm/ttm: test for dma_address array allocation failure

[j.gli...@gmail.com]

From: Jerome Glisse 

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/ttm/ttm_tt.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2dd45ca..58ea7dc 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -298,7 +298,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, 
unsigned long size,
ttm->dummy_read_page = dummy_read_page;

ttm_tt_alloc_page_directory(ttm);
-   if (!ttm->pages) {
+   if (!ttm->pages || !ttm->dma_address) {
ttm_tt_destroy(ttm);
printk(KERN_ERR TTM_PFX "Failed allocating page table\n");
return NULL;
-- 
1.7.1

[PATCH 5/8] drm/ttm: convert page allocation to use page ptr array instead of list V2

[j.gli...@gmail.com]

From: Jerome Glisse 

Use the ttm_tt page ptr array for page allocation, move the list to
array unwinding into the page allocation functions.

V2 split the fix to use ttm put page as a separate fix
properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not
set

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/ttm/ttm_memory.c |   44 +
 drivers/gpu/drm/ttm/ttm_page_alloc.c |   70 +++---
 drivers/gpu/drm/ttm/ttm_tt.c |   61 ++
 include/drm/ttm/ttm_memory.h |   11 +++--
 include/drm/ttm/ttm_page_alloc.h |   17 
 5 files changed, 101 insertions(+), 102 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index e70ddd8..3a3a58b 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -543,41 +543,53 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, 
uint64_t memory,
 }
 EXPORT_SYMBOL(ttm_mem_global_alloc);

-int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
- struct page *page,
- bool no_wait, bool interruptible)
+int ttm_mem_global_alloc_pages(struct ttm_mem_global *glob,
+  struct page **pages,
+  unsigned npages,
+  bool no_wait, bool interruptible)
 {

struct ttm_mem_zone *zone = NULL;
+   unsigned i;
+   int r;

/**
 * Page allocations may be registed in a single zone
 * only if highmem or !dma32.
 */
-
+   for (i = 0; i < npages; i++) {
 #ifdef CONFIG_HIGHMEM
-   if (PageHighMem(page) && glob->zone_highmem != NULL)
-   zone = glob->zone_highmem;
+   if (PageHighMem(pages[i]) && glob->zone_highmem != NULL)
+   zone = glob->zone_highmem;
 #else
-   if (glob->zone_dma32 && page_to_pfn(page) > 0x0010UL)
-   zone = glob->zone_kernel;
+   if (glob->zone_dma32 && page_to_pfn(pages[i]) > 0x0010UL)
+   zone = glob->zone_kernel;
 #endif
-   return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait,
-interruptible);
+   r = ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait,
+ interruptible);
+   if (r) {
+   return r;
+   }
+   }
+   return 0;
 }

-void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page)
+void ttm_mem_global_free_pages(struct ttm_mem_global *glob,
+  struct page **pages, unsigned npages)
 {
struct ttm_mem_zone *zone = NULL;
+   unsigned i;

+   for (i = 0; i < npages; i++) {
 #ifdef CONFIG_HIGHMEM
-   if (PageHighMem(page) && glob->zone_highmem != NULL)
-   zone = glob->zone_highmem;
+   if (PageHighMem(pages[i]) && glob->zone_highmem != NULL)
+   zone = glob->zone_highmem;
 #else
-   if (glob->zone_dma32 && page_to_pfn(page) > 0x0010UL)
-   zone = glob->zone_kernel;
+   if (glob->zone_dma32 && page_to_pfn(pages[i]) > 0x0010UL)
+   zone = glob->zone_kernel;
 #endif
-   ttm_mem_global_free_zone(glob, zone, PAGE_SIZE);
+   ttm_mem_global_free_zone(glob, zone, PAGE_SIZE);
+   }
 }


diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 727e93d..e94ff12 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -619,8 +619,10 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool 
*pool,
  * @return count of pages still required to fulfill the request.
  */
 static unsigned ttm_page_pool_get_pages(struct ttm_page_pool *pool,
-   struct list_head *pages, int ttm_flags,
-   enum ttm_caching_state cstate, unsigned count)
+   struct list_head *pages,
+   int ttm_flags,
+   enum ttm_caching_state cstate,
+   unsigned count)
 {
unsigned long irq_flags;
struct list_head *p;
@@ -664,13 +666,14 @@ out:
  * On success pages list will hold count number of correctly
  * cached pages.
  */
-int ttm_get_pages(struct list_head *pages, int flags,
- enum ttm_caching_state cstate, unsigned count,
- dma_addr_t *dma_address)
+int ttm_get_pages(struct page **pages, unsigned npages, int flags,
+ enum ttm_caching_state cstate, dma_addr_t *dma_address)
 {
struct ttm_page_pool *pool = ttm_get_pool(flags, cstate);
struct page *p = NULL;
+   struct list_head plist;
gfp_t gfp_flags = GFP_USER;
+   unsigned count = 0;
int 

[PATCH 4/8] drm/ttm: use ttm put pages function to properly restore cache attribute

[j.gli...@gmail.com]

From: Jerome Glisse 

On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/ttm/ttm_tt.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 8b7a6d0..3fb4c6d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -89,7 +89,10 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, 
int index)
}
return p;
 out_err:
-   put_page(p);
+   INIT_LIST_HEAD();
+   list_add(>lru, );
+   ttm_put_pages(, 1, ttm->page_flags,
+ ttm->caching_state, >dma_address[index]);
return NULL;
 }

-- 
1.7.1

[PATCH 3/8] drm/ttm: remove unused backend flags field

[j.gli...@gmail.com]

From: Jerome Glisse 

This field is not use by any of the driver just drop it.

Signed-off-by: Jerome Glisse 
Reviewed-by: Konrad Rzeszutek Wilk 
---
 drivers/gpu/drm/radeon/radeon_ttm.c |1 -
 include/drm/ttm/ttm_bo_driver.h |2 --
 2 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 0b5468b..97c76ae 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -787,7 +787,6 @@ struct ttm_backend *radeon_ttm_backend_create(struct 
radeon_device *rdev)
return NULL;
}
gtt->backend.bdev = >mman.bdev;
-   gtt->backend.flags = 0;
gtt->backend.func = _backend_func;
gtt->rdev = rdev;
gtt->pages = NULL;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 9da182b..6d17140 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -106,7 +106,6 @@ struct ttm_backend_func {
  * struct ttm_backend
  *
  * @bdev: Pointer to a struct ttm_bo_device.
- * @flags: For driver use.
  * @func: Pointer to a struct ttm_backend_func that describes
  * the backend methods.
  *
@@ -114,7 +113,6 @@ struct ttm_backend_func {

 struct ttm_backend {
struct ttm_bo_device *bdev;
-   uint32_t flags;
struct ttm_backend_func *func;
 };

-- 
1.7.1

[PATCH 2/8] drm/ttm: remove split btw highmen and lowmem page

[j.gli...@gmail.com]

From: Jerome Glisse 

Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case of allocation whole buffer.

Signed-off-by: Jerome Glisse 
Reviewed-by: Konrad Rzeszutek Wilk 
---
 drivers/gpu/drm/ttm/ttm_tt.c|   11 ++-
 include/drm/ttm/ttm_bo_driver.h |7 ---
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 82a1161..8b7a6d0 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -69,7 +69,7 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int 
index)
struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
int ret;

-   while (NULL == (p = ttm->pages[index])) {
+   if (NULL == (p = ttm->pages[index])) {

INIT_LIST_HEAD();

@@ -85,10 +85,7 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, 
int index)
if (unlikely(ret != 0))
goto out_err;

-   if (PageHighMem(p))
-   ttm->pages[--ttm->first_himem_page] = p;
-   else
-   ttm->pages[++ttm->last_lomem_page] = p;
+   ttm->pages[index] = p;
}
return p;
 out_err:
@@ -270,8 +267,6 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
ttm_put_pages(, count, ttm->page_flags, ttm->caching_state,
  ttm->dma_address);
ttm->state = tt_unpopulated;
-   ttm->first_himem_page = ttm->num_pages;
-   ttm->last_lomem_page = -1;
 }

 void ttm_tt_destroy(struct ttm_tt *ttm)
@@ -315,8 +310,6 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, 
unsigned long size,

ttm->glob = bdev->glob;
ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
-   ttm->first_himem_page = ttm->num_pages;
-   ttm->last_lomem_page = -1;
ttm->caching_state = tt_cached;
ttm->page_flags = page_flags;

diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 37527d6..9da182b 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -136,11 +136,6 @@ enum ttm_caching_state {
  * @dummy_read_page: Page to map where the ttm_tt page array contains a NULL
  * pointer.
  * @pages: Array of pages backing the data.
- * @first_himem_page: Himem pages are put last in the page array, which
- * enables us to run caching attribute changes on only the first part
- * of the page array containing lomem pages. This is the index of the
- * first himem page.
- * @last_lomem_page: Index of the last lomem page in the page array.
  * @num_pages: Number of pages in the page array.
  * @bdev: Pointer to the current struct ttm_bo_device.
  * @be: Pointer to the ttm backend.
@@ -157,8 +152,6 @@ enum ttm_caching_state {
 struct ttm_tt {
struct page *dummy_read_page;
struct page **pages;
-   long first_himem_page;
-   long last_lomem_page;
uint32_t page_flags;
unsigned long num_pages;
struct ttm_bo_global *glob;
-- 
1.7.1

[PATCH 1/8] drm/ttm: remove userspace backed ttm object support

[j.gli...@gmail.com]

From: Jerome Glisse 

This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.

Signed-off-by: Jerome Glisse 
Reviewed-by: Konrad Rzeszutek Wilk 
---
 drivers/gpu/drm/ttm/ttm_bo.c|   22 
 drivers/gpu/drm/ttm/ttm_tt.c|  105 +--
 include/drm/ttm/ttm_bo_api.h|5 --
 include/drm/ttm/ttm_bo_driver.h |   24 -
 4 files changed, 1 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 617b646..4bde335 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -342,22 +342,6 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, 
bool zero_alloc)
if (unlikely(bo->ttm == NULL))
ret = -ENOMEM;
break;
-   case ttm_bo_type_user:
-   bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
-   page_flags | TTM_PAGE_FLAG_USER,
-   glob->dummy_read_page);
-   if (unlikely(bo->ttm == NULL)) {
-   ret = -ENOMEM;
-   break;
-   }
-
-   ret = ttm_tt_set_user(bo->ttm, current,
- bo->buffer_start, bo->num_pages);
-   if (unlikely(ret != 0)) {
-   ttm_tt_destroy(bo->ttm);
-   bo->ttm = NULL;
-   }
-   break;
default:
printk(KERN_ERR TTM_PFX "Illegal buffer object type\n");
ret = -EINVAL;
@@ -907,16 +891,12 @@ static uint32_t ttm_bo_select_caching(struct 
ttm_mem_type_manager *man,
 }

 static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man,
-bool disallow_fixed,
 uint32_t mem_type,
 uint32_t proposed_placement,
 uint32_t *masked_placement)
 {
uint32_t cur_flags = ttm_bo_type_flags(mem_type);

-   if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && disallow_fixed)
-   return false;
-
if ((cur_flags & proposed_placement & TTM_PL_MASK_MEM) == 0)
return false;

@@ -961,7 +941,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
man = >man[mem_type];

type_ok = ttm_bo_mt_compatible(man,
-   bo->type == ttm_bo_type_user,
mem_type,
placement->placement[i],
_flags);
@@ -1009,7 +988,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
if (!man->has_type)
continue;
if (!ttm_bo_mt_compatible(man,
-   bo->type == ttm_bo_type_user,
mem_type,
placement->busy_placement[i],
_flags))
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 58c271e..82a1161 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -62,43 +62,6 @@ static void ttm_tt_free_page_directory(struct ttm_tt *ttm)
ttm->dma_address = NULL;
 }

-static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
-{
-   int write;
-   int dirty;
-   struct page *page;
-   int i;
-   struct ttm_backend *be = ttm->be;
-
-   BUG_ON(!(ttm->page_flags & TTM_PAGE_FLAG_USER));
-   write = ((ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0);
-   dirty = ((ttm->page_flags & TTM_PAGE_FLAG_USER_DIRTY) != 0);
-
-   if (be)
-   be->func->clear(be);
-
-   for (i = 0; i < ttm->num_pages; ++i) {
-   page = ttm->pages[i];
-   if (page == NULL)
-   continue;
-
-   if (page == ttm->dummy_read_page) {
-   BUG_ON(write);
-   continue;
-   }
-
-   if (write && dirty && !PageReserved(page))
-   set_page_dirty_lock(page);
-
-   ttm->pages[i] = NULL;
-   ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE);
-   put_page(page);
-   }
-   ttm->state = tt_unpopulated;
-   ttm->first_himem_page = ttm->num_pages;
-   ttm->last_lomem_page = -1;
-}
-
 static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
 {
struct page *p;
@@ -325,10 +288,7 @@ void ttm_tt_destroy(struct ttm_tt *ttm)
}

if (likely(ttm->pages != NULL)) {
-   if (ttm->page_flags & TTM_PAGE_FLAG_USER)
-  

[RFC] ttm merge ttm_backend & ttm_t V2

[j.gli...@gmail.com]

Hi,

So attached is last batch of patch, i split the ttm put page
fix and i fixed a bug in the pages alloc when clear flags
wasn't set. I tested them on a bunch of radeon and everythings
seems fine (several gl app, firefox, compositor ...). I will
do more testing on agp and nouveau tomorrow.

The last patch add callback for populating and unpopulating
(better name if any welcome) a ttm_tt. Allowing the driver
to choose btw different choice, idea is that Konrad dma
allocator would provide helper function the driver can
call.

I choosed to allocate all page at once because ttm_tt object
are meant to be bind and thus to be fully populated in their
lifetime (vmwgfx might be different in this regard). It
simplify code in several place. I didn't see any performances
impact in the few gl benchmark i ran.

Konrad so i am planning on rebasing the last 4 patch of your
patchset on top of that. They will likely shrink in size a
bit.

Cheers,
Jerome Glisse

[Bug 35460] [855GM] Corruptions with linux-2.6.38 & xf-video-intel-2.14.901

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=35460

--- Comment #12 from Bruno  2011-11-02 11:24:34 PDT 
---
(In reply to comment #10 with patch from comment #11)
> Created attachment 52920 [details] [review]
> 
> Test-feedback highly appreciated.

Running now for two days with the patch, no negative effect seen though some
more time will be needed to produce a solid answer whether it fixes the cursors
as the corruption is not that regular (at least no noticed any cursor
corruption since I applied the patch).

Will report back in a week or so unless I see corruption in which case I will
report earlier.

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[PATCH] drm/radeon/kms: don't poll forever if MC GDDR link training fails

[alexdeuc...@gmail.com]

From: Alex Deucher 

Bail if we hit the timeout limit.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/ni.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 56afaff..722cfb3 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -261,8 +261,11 @@ int ni_mc_load_microcode(struct radeon_device *rdev)
WREG32(MC_SEQ_SUP_CNTL, 0x0001);

/* wait for training to complete */
-   while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
-   udelay(10);
+   for (i = 0; i < rdev->usec_timeout; i++) {
+   if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
+   break;
+   udelay(1);
+   }

if (running)
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
-- 
1.7.3.4

[Bug 41592] [Radeon] The display often freezes with gnome-shell 3.2

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=41592

Michel D?nzer  changed:

   What|Removed |Added

 Status|RESOLVED|VERIFIED

--- Comment #18 from Michel D?nzer  2011-11-02 10:53:24 
PDT ---
> [ 4192.459] (II) RADEON(0): radeon_dri2_flip_event_handler:981
> fevent[0x17e2360] width 1366 pitch 5632 (/4 1408)
> [ 4193.043] (II) RADEON(0): radeon_dri2_schedule_flip:619 fevent[0x184a890]

BTW, these are harmless debug messages which are suppressed by default.
Somebody or something seems to have increased the X server's log level.

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Adam Jackson]

On 11/2/11 5:13 PM, Keith Packard wrote:
> On Wed, 02 Nov 2011 16:35:51 -0400, Adam Jackson  wrote:
>
>> It is?  The DP 1.1a text for lane count is "For Rev.1.1, only the
>> following three values are supported. All other values are reserved."
>
> Yeah, if you look at the MAX_LINK_RATE field, we assume that it has a
> useful value. I'll bet they were thinking of letting the spec support
> things like alternate clock rates or 3 lanes or something, and the 1.1
> version just tied things down to allow only sensible values there.
>
> How about we just always use the DPCD value?

Looks good.

Reviewed-by: Adam Jackson 

- ajax

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Adam Jackson]

On 11/2/11 4:05 PM, Keith Packard wrote:
> On Wed, 02 Nov 2011 15:36:20 -0400, Adam Jackson  wrote:
>
>> The VBT is going to be crap.
>
> The only question then is what to do with hardware that doesn't have the
> DPCD value -- that's "new" in revision 0x11, after all.

It is?  The DP 1.1a text for lane count is "For Rev.1.1, only the 
following three values are supported. All other values are reserved."  I 
don't think that implies anything about what it meant in 1.0.  It does 
say that bits 7:5 of that register are reserved in 1.0 though; since it 
doesn't have any versioning on bits 4:0 I'd think that means they're 
interpreted the same in 1.0 as in 1.1.

Unless you have a copy of the 1.0 spec?

Again, not that it probably matters much.  I think the installed base of 
DP 1.0 sinks is zero, I've literally never seen one.

> How about this:
>
> commit 34ebe02cc78f20ae6b7865c5087c3b5ac7810185
> Author: Keith Packard
> Date:   Wed Nov 2 13:03:47 2011 -0700
>
>  drm/i915: Use DPCD value for max DP lanes where possible
>
>  Fall back to the VBT value for eDP monitors only when DPCD is missing
>  the value.
>
>  Signed-off-by: Keith Packard

Reviewed-by: Adam Jackson 

- ajax

[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=41971

--- Comment #13 from Mike Lothian  2011-11-02 09:02:00 
PDT ---
Is there a way for switcheroo to detect a muxless laptop and automatically
switch it off (if it isn't already)

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Adam Jackson]

On 11/2/11 1:31 PM, Keith Packard wrote:
> On Wed, 02 Nov 2011 13:13:52 -0400, Adam Jackson  wrote:
>
>> Given the choice of trusting DPCD or the VBT, I'd definitely prefer
>> DPCD.
>
> Except that the DPCD is coded into the monitor while the VBT is done by
> the platform. And, it's the platform which may neglect to connect some
> of the wires.

My reasoning about this has been:

The maximum link configuration in DPCD is going to fit - and minimally 
fit - the maximum supported configuration (depth/rate/size/etc), because 
otherwise the hardware would have been more expensive to produce.

The VBT is going to be crap.

But as always, "do what the Windows driver does" seems like a good 
strategy.  Do we know?

> Any bets on how long until we find a machine that has right value in the
> VBT and the wrong one in DPCD? Or a machine with wrong values in both places?

I will happily pay $20 to the first person to find a monitor with broken 
link/lane in DPCD, on the understanding that they take it (the $20) to 
the nearest hardware store, buy a hammer, and smash the monitor. 
Preferably with the video uploaded to youtube.

- ajax

[PATCH 1/5] drm: add plane support

[Jesse Barnes]

On Wed,  2 Nov 2011 13:03:19 -0700
Jesse Barnes  wrote:

> Planes are a bit like half-CRTCs.  They have a location and fb, but
> don't drive outputs directly.  Add support for handling them to the core
> KMS code.

Accidentally left out the ->destroy hook in this one.  The drm-overlays
branch at git://people.freedesktop.org/~jbarnes/linux has a fixed
version, along with a couple of fixes for issues Chris and Dan pointed
out.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center
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[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Alex Deucher]

On Wed, Nov 2, 2011 at 2:54 PM, Keith Packard  wrote:
> On Tue, ?1 Nov 2011 23:20:26 -0700, Keith Packard  
> wrote:
>
>> ? ? ? ? ? ? ? intel_dp = enc_to_intel_dp(encoder);
>> - ? ? ? ? ? ? if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
>> + ? ? ? ? ? ? if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
>> is_pch_edp(intel_dp)) {
>> ? ? ? ? ? ? ? ? ? ? ? lane_count = intel_dp->lane_count;
>> ? ? ? ? ? ? ? ? ? ? ? break;
>> - ? ? ? ? ? ? } else if (is_edp(intel_dp)) {
>> + ? ? ? ? ? ? } else if (is_cpu_edp(intel_dp)) {
>> ? ? ? ? ? ? ? ? ? ? ? lane_count = dev_priv->edp.lanes;
>> ? ? ? ? ? ? ? ? ? ? ? break;
>
> Thinking about this one more time -- if we ever want to use
> dev_priv->edp.lanes, we should use it in
> intel_dp_max_lane_count. intel_dp_set_m_n should use
> intel_dp->lane_count unconditionally as that's the value we've used
> everywhere else for mode setting.
>
> Perhaps we should use it for monitors that don't include the
> MAX_LANE_COUNT field in the dpcd? Perhaps we should use it on all eDP
> monitors?

FWIW, we rely on the DPCD field for eDP just like DP.  Our vbios LCD
tables don't contain DP lane or rate info.

Alex

[PATCH] drm/radeon/kms: fix DP setup on TRAVIS bridges

[alexdeuc...@gmail.com]

From: Alex Deucher 

Supposedly both NUTMEG and TRAVIS should use the same
panel mode, but switching the panel mode for TRAVIS
gets things working.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=41569

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_dp.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c 
b/drivers/gpu/drm/radeon/atombios_dp.c
index ff47186..a0de485 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -560,9 +560,12 @@ static void radeon_dp_set_panel_mode(struct drm_encoder 
*encoder,
if (!ASIC_IS_DCE4(rdev))
return;

-   if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
-   ENCODER_OBJECT_ID_NONE)
+   if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
+   ENCODER_OBJECT_ID_NUTMEG)
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+   else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
+ENCODER_OBJECT_ID_TRAVIS)
+   panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
u8 tmp = radeon_read_dpcd_reg(radeon_connector, 
DP_EDP_CONFIGURATION_CAP);
if (tmp & 1)
-- 
1.7.3.4

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 02 Nov 2011 16:35:51 -0400, Adam Jackson  wrote:

> It is?  The DP 1.1a text for lane count is "For Rev.1.1, only the 
> following three values are supported. All other values are reserved."

Yeah, if you look at the MAX_LINK_RATE field, we assume that it has a
useful value. I'll bet they were thinking of letting the spec support
things like alternate clock rates or 3 lanes or something, and the 1.1
version just tied things down to allow only sensible values there.

How about we just always use the DPCD value?

commit e0fafa5dee031ef6174eadb005a5f01d13da931d
Author: Keith Packard 
Date:   Wed Nov 2 13:03:47 2011 -0700

drm/i915: Use DPCD value for max DP lanes.

The BIOS VBT value for an eDP panel has been shown to be incorrect on
one machine, and we haven't found any machines where the DPCD value
was wrong, so we'll use the DPCD value everywhere.

Signed-off-by: Keith Packard 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 02b56ce..5056d29 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -154,16 +154,12 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
 static int
 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 {
-   int max_lane_count = 4;
-
-   if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
-   max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
-   switch (max_lane_count) {
-   case 1: case 2: case 4:
-   break;
-   default:
-   max_lane_count = 4;
-   }
+   int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
+   switch (max_lane_count) {
+   case 1: case 2: case 4:
+   break;
+   default:
+   max_lane_count = 4;
}
return max_lane_count;
 }
@@ -765,12 +761,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
drm_display_mode *mode,
continue;

intel_dp = enc_to_intel_dp(encoder);
-   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
is_pch_edp(intel_dp)) {
+   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
+   intel_dp->base.type == INTEL_OUTPUT_EDP)
+   {
lane_count = intel_dp->lane_count;
break;
-   } else if (is_cpu_edp(intel_dp)) {
-   lane_count = dev_priv->edp.lanes;
-   break;
}
}

-- 
keith.packard at intel.com
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[Bug 42514] [r300g] EVE online: some shaders are failing

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42514

--- Comment #3 from Pavel Ondra?ka  2011-11-02 
06:43:44 PDT ---
Forgot to mention, GPU is RV530.

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[Bug 42514] [r300g] EVE online: some shaders are failing

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42514

--- Comment #2 from Pavel Ondra?ka  2011-11-02 
06:42:30 PDT ---
Created attachment 53054
  --> https://bugs.freedesktop.org/attachment.cgi?id=53054
RADEON_DEBUG=fp log

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[Bug 42514] [r300g] EVE online: some shaders are failing

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42514

--- Comment #1 from Pavel Ondra?ka  2011-11-02 
06:42:01 PDT ---
Created attachment 53053
  --> https://bugs.freedesktop.org/attachment.cgi?id=53053
terminal output

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[Bug 42514] New: [r300g] EVE online: some shaders are failing

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42514

 Bug #: 42514
   Summary: [r300g] EVE online: some shaders are failing
Classification: Unclassified
   Product: Mesa
   Version: git
  Platform: Other
OS/Version: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/r300
AssignedTo: dri-devel at lists.freedesktop.org
ReportedBy: pavel.ondracka at email.cz


There are failing shaders in EVE Online:

Part of wine output, full log attached:

fixme:d3d_shader:print_glsl_info_log Info log received from GLSL shader #32:
fixme:d3d_shader:print_glsl_info_log 0:84(30): error: array index must be <
245
fixme:d3d_shader:print_glsl_info_log 0:84(35): error: type mismatch
fixme:d3d_shader:print_glsl_info_log 0:84(35): error: Operands to
arithmetic operators must be numeric
fixme:d3d_shader:print_glsl_info_log 0:91(30): error: array index must be <
245
fixme:d3d_shader:print_glsl_info_log 0:91(35): error: type mismatch
fixme:d3d_shader:print_glsl_info_log 0:91(35): error: Operands to
arithmetic operators must be numeric
fixme:d3d_shader:print_glsl_info_log 0:93(17): error: array index must be <
245
fixme:d3d_shader:print_glsl_info_log 0:93(22): error: type mismatch

Apitrace here: http://pavel.ondracka.cz/EVE.trace 

Mesa: 6d3d0ca9e9ef0d0a1e3ba0940f7127298e078a7d
Kernel: 3.1.0-5.fc16
libdrm: 2.4.26-3.fc16
Wine: 1.3.31

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[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=41971

--- Comment #12 from Alex Deucher  2011-11-02 06:37:47 PDT 
---
(In reply to comment #11)
> 
> When no module is loaded is the card still drawing power?

It depends whether the bios turns it on by default or not.  If it's off, you
are not drawing power.  If it's on, you can turn it off via vgaswitcheroo.

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[Bug 41971] [kms] Muxless radeon takes 20 seconds to fetch rom

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=41971

--- Comment #11 from Mike Lothian  2011-11-02 06:29:06 
PDT ---
I've removed the vgaswitcheroo and radeon options from my kernel and my boot
time has returned to normal, as I have a muxless laptop not having the card
available makes no difference just now 

When no module is loaded is the card still drawing power?

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[Bug 38554] Hibernate broken when KMS enabled on Radeon Mobility M6 LY

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=38554

--- Comment #1 from Orion Poplawski  2011-11-02 
13:14:53 UTC ---
I seem to be hitting exactly the same problem in Fedora 16 with
3.1.0-5.fc16.i686.

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Adam Jackson]

On 11/2/11 12:20 PM, Jesse Barnes wrote:

> @@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
> drm_display_mode *mode,
>   continue;
>
>   intel_dp = enc_to_intel_dp(encoder);
> - if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
> + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
> is_pch_edp(intel_dp)) {
>   lane_count = intel_dp->lane_count;
>   break;
> - } else if (is_edp(intel_dp)) {
> + } else if (is_cpu_edp(intel_dp)) {
>   lane_count = dev_priv->edp.lanes;
>   break;
>   }
>
> I guess this means we can't trust the BIOS settings for PCH eDP?

Given the choice of trusting DPCD or the VBT, I'd definitely prefer DPCD.

- ajax

[RFC] ttm merge ttm_backend & ttm_tt

[Konrad Rzeszutek Wilk]

> > I don't know why it was done that way, but I wrote the TTM DMA code
> > to be optimized for that (and it has the code to reverse direction - b/c
> > the testcases I used initially had the a,b,c,d,e,f order when doing 
> > get_pages
> > and put_pages) - but I can alter the code to do it in the forward fashion 
> > instead
> > of the reverse fashion.. Better yet, it removes around 70 lines of code 
> > from the
> > TTM DMA.
> 
> Order in which we put them back on the list can be easily change, either
> by use of add_tail or by iterating array from end to begining. i am not
> sure how much this can impact things.

Neither am I. I can run some perf numbers when playing tuxracer and see if there
is a disadvantage/advantage.

> 
> > Anyhow, it might be noting that in the commit description and perhaps make 
> > a bug-fix
> > for the put_pages being called in the error path instead of ttm_put_pages 
> > as a seperate
> > patch as you suggested.
> > 
> > 
> > [PATCH 6/6] drm/ttm: merge ttm_backend and ttm_tt
> > 
> > That is going to be a bit tricky. You are using the pci_map_page, which 
> > should not
> > be used if the pages have been allocated via the pci_alloc_coherent (they 
> > are already
> > mapped). Perhaps a simple check such as:
> > 
> > if !(ttm->be && ttm->be->func && ttm->be->func->get_pages) {
> > ttm->dma_address[i] = pci_map_page(dev->pdev, ...)
> > }
> 
> Your dma change are not suppose to be on top of that, idea is to add yet
> another callbacks populate+free_page which will do either pci map page
> or just use your code (ie use dma alloc and store dma addr into the
> array). So there is a missing piece here before adding your dma code.
> I just wanted to keep ttm_tt & ttm_backend merge as simple as possible
> without major change. Adding the populate + get_page callback sounded
> like good candidate for another patch.



> > What base should I be looking at? Is this the base that Dave has for 3.2?
> 
> Should apply on top of linus master kernel as of yesterday.

Oh.. very very *very* fresh.

[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 02 Nov 2011 15:36:20 -0400, Adam Jackson  wrote:

> The VBT is going to be crap.

The only question then is what to do with hardware that doesn't have the
DPCD value -- that's "new" in revision 0x11, after all.

How about this:

commit 34ebe02cc78f20ae6b7865c5087c3b5ac7810185
Author: Keith Packard 
Date:   Wed Nov 2 13:03:47 2011 -0700

drm/i915: Use DPCD value for max DP lanes where possible

Fall back to the VBT value for eDP monitors only when DPCD is missing
the value.

Signed-off-by: Keith Packard 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 02b56ce..93b082a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -154,6 +154,8 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
 static int
 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 {
+   struct drm_device *dev = intel_dp->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
int max_lane_count = 4;

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
@@ -164,6 +166,8 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
default:
max_lane_count = 4;
}
+   } else if (is_edp(intel_dp)) {
+   max_lane_count = dev_priv->edp.lanes;
}
return max_lane_count;
 }
@@ -765,12 +769,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
drm_display_mode *mode,
continue;

intel_dp = enc_to_intel_dp(encoder);
-   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
is_pch_edp(intel_dp)) {
+   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
+   intel_dp->base.type == INTEL_OUTPUT_EDP)
+   {
lane_count = intel_dp->lane_count;
break;
-   } else if (is_cpu_edp(intel_dp)) {
-   lane_count = dev_priv->edp.lanes;
-   break;
}
}



-- 
keith.packard at intel.com
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[PATCH 5/5] drm/i915: add destination color key support

[Jesse Barnes]

Add new ioctls for getting and setting the current destination color
key.  This allows for simple overlay display control by matching a color
key value in the primary plane before blending the overlay on top.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_dma.c   |2 +
 drivers/gpu/drm/i915/intel_drv.h  |6 +++
 drivers/gpu/drm/i915/intel_overlay2.c |   72 +
 include/drm/i915_drm.h|   16 +++
 4 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2eac955..2d163e8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2294,6 +2294,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, 
DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, 
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, 
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+   DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_DESTKEY, intel_overlay_set_destkey, 
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+   DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_DESTKEY, intel_overlay_get_destkey, 
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
 };

 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 39b3ae7..016ef54 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -407,4 +407,10 @@ extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);

+extern int intel_overlay_set_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+extern int intel_overlay_get_destkey(struct drm_device *dev, void *data,
+struct drm_file *file_priv);
+
+
 #endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_overlay2.c 
b/drivers/gpu/drm/i915/intel_overlay2.c
index 5d376d9..dd6ede5 100644
--- a/drivers/gpu/drm/i915/intel_overlay2.c
+++ b/drivers/gpu/drm/i915/intel_overlay2.c
@@ -99,6 +99,7 @@ ivb_update_plane(struct drm_plane *plane, struct 
drm_framebuffer *fb,
/* must disable */
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
sprctl |= SPRITE_ENABLE;
+   sprctl |= SPRITE_DEST_KEY;

/* Sizes are 0 based */
src_w--;
@@ -388,6 +389,77 @@ out_unlock:
return ret;
 }

+int intel_overlay_set_destkey(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+   struct drm_intel_set_sprite_destkey *set = data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_mode_object *obj;
+   struct drm_plane *plane;
+   struct intel_plane *intel_plane;
+   int ret = 0;
+
+   if (!dev_priv)
+   return -EINVAL;
+
+   if (set->value > 0xff)
+   return -EINVAL;
+
+   mutex_lock(>mode_config.mutex);
+
+   obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
+   if (!obj) {
+   ret = -EINVAL;
+   goto out_unlock;
+   }
+
+   plane = obj_to_plane(obj);
+   intel_plane = to_intel_plane(plane);
+
+   mutex_lock(>struct_mutex);
+   I915_WRITE(SPRKEYVAL(intel_plane->pipe), set->value);
+   I915_WRITE(SPRKEYMSK(intel_plane->pipe), 0xff);
+   POSTING_READ(SPRKEYMSK(intel_plane->pipe));
+   mutex_unlock(>struct_mutex);
+
+out_unlock:
+   mutex_unlock(>mode_config.mutex);
+   return ret;
+}
+
+int intel_overlay_get_destkey(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+   struct drm_intel_get_sprite_destkey *get = data;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_mode_object *obj;
+   struct drm_plane *plane;
+   struct intel_plane *intel_plane;
+   int ret = 0;
+
+   if (!dev_priv)
+   return -EINVAL;
+
+   mutex_lock(>mode_config.mutex);
+
+   obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
+   if (!obj) {
+   ret = -EINVAL;
+   goto out_unlock;
+   }
+
+   plane = obj_to_plane(obj);
+   intel_plane = to_intel_plane(plane);
+
+   mutex_lock(>struct_mutex);
+   get->value = I915_READ(SPRKEYVAL(intel_plane->pipe));
+   mutex_unlock(>struct_mutex);
+
+out_unlock:
+   mutex_unlock(>mode_config.mutex);
+   return ret;
+}
+
 static struct drm_plane_funcs intel_plane_funcs;

 static uint32_t snb_plane_formats[] = {
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 28c0d11..f9a390b 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -198,6 

[PATCH 4/5] drm/i915: add SNB and IVB video sprite support

[Jesse Barnes]

The video sprites support various video surface formats natively and can
handle scaling as well.  So add support for them using the new DRM core
overlay support functions.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/i915_reg.h   |  123 +
 drivers/gpu/drm/i915/intel_display.c  |   29 ++-
 drivers/gpu/drm/i915/intel_drv.h  |   23 ++
 drivers/gpu/drm/i915/intel_fb.c   |6 +
 drivers/gpu/drm/i915/intel_overlay2.c |  438 +
 6 files changed, 610 insertions(+), 10 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_overlay2.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ae6a7c..6193471 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
  intel_dvo.o \
  intel_ringbuffer.o \
  intel_overlay.o \
+ intel_overlay2.o \
  intel_opregion.o \
  dvo_ch7xxx.o \
  dvo_ch7017.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416..b2270fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2450,6 +2450,8 @@
 #define WM3_LP_ILK 0x45110
 #define  WM3_LP_EN (1<<31)
 #define WM1S_LP_ILK0x45120
+#define WM2S_LP_IVB0x45124
+#define WM3S_LP_IVB0x45128
 #define  WM1S_LP_EN(1<<31)

 /* Memory latency timer register */
@@ -2666,6 +2668,127 @@
 #define _DSPBSURF  0x7119C
 #define _DSPBTILEOFF   0x711A4

+/* Sprite A control */
+#define _DVSACNTR  0x72180
+#define   DVS_ENABLE   (1<<31)
+#define   DVS_GAMMA_ENABLE (1<<30)
+#define   DVS_PIXFORMAT_MASK   (3<<25)
+#define   DVS_FORMAT_YUV422(0<<25)
+#define   DVS_FORMAT_RGBX101010(1<<25)
+#define   DVS_FORMAT_RGBX888   (2<<25)
+#define   DVS_FORMAT_RGBX161616(3<<25)
+#define   DVS_SOURCE_KEY   (1<<22)
+#define   DVS_RGB_ORDER_RGBX   (1<<20)
+#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
+#define   DVS_YUV_ORDER_YUYV   (0<<16)
+#define   DVS_YUV_ORDER_UYVY   (1<<16)
+#define   DVS_YUV_ORDER_YVYU   (2<<16)
+#define   DVS_YUV_ORDER_VYUY   (3<<16)
+#define   DVS_DEST_KEY (1<<2)
+#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
+#define   DVS_TILED(1<<10)
+#define _DVSASTRIDE0x72188
+#define _DVSAPOS   0x7218c
+#define _DVSASIZE  0x72190
+#define _DVSAKEYVAL0x72194
+#define _DVSAKEYMSK0x72198
+#define _DVSASURF  0x7219c
+#define _DVSAKEYMAXVAL 0x721a0
+#define _DVSATILEOFF   0x721a4
+#define _DVSASURFLIVE  0x721ac
+#define _DVSASCALE 0x72204
+#define   DVS_SCALE_ENABLE (1<<31)
+#define   DVS_FILTER_MASK  (3<<29)
+#define   DVS_FILTER_MEDIUM(0<<29)
+#define   DVS_FILTER_ENHANCING (1<<29)
+#define   DVS_FILTER_SOFTENING (2<<29)
+#define _DVSAGAMC  0x72300
+
+#define _DVSBCNTR  0x73180
+#define _DVSBSTRIDE0x73188
+#define _DVSBPOS   0x7318c
+#define _DVSBSIZE  0x73190
+#define _DVSBKEYVAL0x73194
+#define _DVSBKEYMSK0x73198
+#define _DVSBSURF  0x7319c
+#define _DVSBKEYMAXVAL 0x731a0
+#define _DVSBTILEOFF   0x731a4
+#define _DVSBSURFLIVE  0x731ac
+#define _DVSBSCALE 0x73204
+#define _DVSBGAMC  0x73300
+
+#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
+#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
+#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
+#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
+#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
+#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+
+#define _SPRA_CTL  0x70280
+#define   SPRITE_ENABLE(1<<31)
+#define   SPRITE_GAMMA_ENABLE  (1<<30)
+#define   SPRITE_PIXFORMAT_MASK(7<<25)
+#define   SPRITE_FORMAT_YUV422 (0<<25)
+#define   SPRITE_FORMAT_RGBX101010 (1<<25)
+#define   SPRITE_FORMAT_RGBX888(2<<25)
+#define   SPRITE_FORMAT_RGBX161616 (3<<25)
+#define   SPRITE_FORMAT_YUV444 (4<<25)
+#define   SPRITE_FORMAT_XBGR101010 (5<<25)
+#define   SPRITE_CSC_ENABLE(1<<24)
+#define   SPRITE_SOURCE_KEY(1<<22)
+#define   SPRITE_RGB_ORDER_RGBX(1<<20) /* only for 888 and 
161616 */
+#define   SPRITE_YUV_TO_RGB_CSC_DISABLE(1<<19)
+#define   SPRITE_YUV_CSC_FORMAT_BT709  (1<<18) /* 0 is BT601 */
+#define   SPRITE_YUV_BYTE_ORDER_MASK   (3<<16)
+#define   SPRITE_YUV_ORDER_YUYV(0<<16)
+#define   SPRITE_YUV_ORDER_UYVY(1<<16)
+#define   SPRITE_YUV_ORDER_YVYU

[PATCH 3/5] drm/i915: rename existing overlay support to "legacy"

[Jesse Barnes]

The old overlay block has all sorts of quirks and is very different than
ILK+ video sprites.  So rename it to legacy to make that clear and clash
less with core overlay support.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |2 +-
 drivers/gpu/drm/i915/i915_drv.h  |   12 ++--
 drivers/gpu/drm/i915/i915_irq.c  |2 +-
 drivers/gpu/drm/i915/intel_display.c |2 +-
 drivers/gpu/drm/i915/intel_drv.h |4 +-
 drivers/gpu/drm/i915/intel_overlay.c |  126 +-
 6 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8e95d66..b6d0bbc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -825,7 +825,7 @@ static int i915_error_state(struct seq_file *m, void 
*unused)
}

if (error->overlay)
-   intel_overlay_print_error_state(m, error->overlay);
+   intel_legacy_overlay_print_error_state(m, error->overlay);

if (error->display)
intel_display_print_error_state(m, dev, error->display);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06a37f4..b96c174 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -118,8 +118,8 @@ struct intel_opregion {
 };
 #define OPREGION_SIZE(8*1024)

-struct intel_overlay;
-struct intel_overlay_error_state;
+struct intel_legacy_overlay;
+struct intel_legacy_overlay_error_state;

 struct drm_i915_master_private {
drm_local_map_t *sarea;
@@ -191,7 +191,7 @@ struct drm_i915_error_state {
u32 cache_level:2;
} *active_bo, *pinned_bo;
u32 active_bo_count, pinned_bo_count;
-   struct intel_overlay_error_state *overlay;
+   struct intel_legacy_overlay_error_state *overlay;
struct intel_display_error_state *display;
 };

@@ -343,7 +343,7 @@ typedef struct drm_i915_private {
struct intel_opregion opregion;

/* overlay */
-   struct intel_overlay *overlay;
+   struct intel_legacy_overlay *overlay;

/* LVDS info */
int backlight_level;  /* restore backlight to this value */
@@ -1309,8 +1309,8 @@ extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);

 /* overlay */
 #ifdef CONFIG_DEBUG_FS
-extern struct intel_overlay_error_state 
*intel_overlay_capture_error_state(struct drm_device *dev);
-extern void intel_overlay_print_error_state(struct seq_file *m, struct 
intel_overlay_error_state *error);
+extern struct intel_legacy_overlay_error_state 
*intel_legacy_overlay_capture_error_state(struct drm_device *dev);
+extern void intel_legacy_overlay_print_error_state(struct seq_file *m, struct 
intel_legacy_overlay_error_state *error);

 extern struct intel_display_error_state 
*intel_display_capture_error_state(struct drm_device *dev);
 extern void intel_display_print_error_state(struct seq_file *m,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9ee2729..36f2837 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -998,7 +998,7 @@ static void i915_capture_error_state(struct drm_device *dev)

do_gettimeofday(>time);

-   error->overlay = intel_overlay_capture_error_state(dev);
+   error->overlay = intel_legacy_overlay_capture_error_state(dev);
error->display = intel_display_capture_error_state(dev);

spin_lock_irqsave(_priv->error_lock, flags);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0727fc8..660168a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3180,7 +3180,7 @@ static void intel_crtc_dpms_overlay(struct intel_crtc 
*intel_crtc, bool enable)

mutex_lock(>struct_mutex);
dev_priv->mm.interruptible = false;
-   (void) intel_overlay_switch_off(intel_crtc->overlay);
+   (void) intel_legacy_overlay_switch_off(intel_crtc->overlay);
dev_priv->mm.interruptible = true;
mutex_unlock(>struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 23c5622..467fb4a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -161,7 +161,7 @@ struct intel_crtc {
bool busy; /* is scanout buffer being updated frequently? */
struct timer_list idle_timer;
bool lowfreq_avail;
-   struct intel_overlay *overlay;
+   struct intel_legacy_overlay *overlay;
struct intel_unpin_work *unpin_work;
int fdi_lanes;

@@ -370,7 +370,7 @@ extern void intel_finish_page_flip_plane(struct drm_device 
*dev, int plane);

 extern void intel_setup_overlay(struct drm_device *dev);
 extern void intel_cleanup_overlay(struct drm_device *dev);
-extern int intel_overlay_switch_off(struct intel_overlay 

[PATCH 2/5] drm: add an fb creation ioctl that takes a pixel format

[Jesse Barnes]

To properly support the various plane formats supported by different
hardware, the kernel must know the pixel format of a framebuffer object.
So add a new ioctl taking a format argument corresponding to a fourcc
name from videodev2.h.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/drm_crtc.c|  105 -
 drivers/gpu/drm/drm_crtc_helper.c |   50 +-
 drivers/gpu/drm/drm_drv.c |1 +
 drivers/gpu/drm/i915/intel_display.c  |   34 +-
 drivers/gpu/drm/i915/intel_drv.h  |2 +-
 drivers/gpu/drm/i915/intel_fb.c   |   11 ++--
 drivers/gpu/drm/nouveau/nouveau_display.c |4 +-
 drivers/gpu/drm/radeon/radeon_display.c   |4 +-
 drivers/gpu/drm/radeon/radeon_fb.c|   18 +++--
 drivers/gpu/drm/radeon/radeon_mode.h  |2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c   |2 +-
 drivers/staging/gma500/framebuffer.c  |2 +-
 include/drm/drm.h |1 +
 include/drm/drm_crtc.h|7 ++-
 include/drm/drm_crtc_helper.h |4 +-
 include/drm/drm_mode.h|   26 +++
 include/linux/videodev2.h |1 +
 17 files changed, 231 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 0e129b1..ff47554 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1889,6 +1889,42 @@ out:
return ret;
 }

+/* Original addfb only supported RGB formats, so figure out which one */
+uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
+{
+   uint32_t fmt;
+
+   switch (bpp) {
+   case 8:
+   fmt = V4L2_PIX_FMT_RGB332;
+   break;
+   case 16:
+   if (depth == 15)
+   fmt = V4L2_PIX_FMT_RGB555;
+   else
+   fmt = V4L2_PIX_FMT_RGB565;
+   break;
+   case 24:
+   fmt = V4L2_PIX_FMT_RGB24;
+   break;
+   case 32:
+   if (depth == 24)
+   fmt = V4L2_PIX_FMT_RGB24;
+   else if (depth == 30)
+   fmt = V4L2_PIX_FMT_INTC_RGB30;
+   else
+   fmt = V4L2_PIX_FMT_RGB32;
+   break;
+   default:
+   DRM_ERROR("bad bpp, assuming RGB24 pixel format\n");
+   fmt = V4L2_PIX_FMT_RGB24;
+   break;
+   }
+
+   return fmt;
+}
+EXPORT_SYMBOL(drm_mode_legacy_fb_format);
+
 /**
  * drm_mode_addfb - add an FB to the graphics configuration
  * @inode: inode from the ioctl
@@ -1909,7 +1945,74 @@ out:
 int drm_mode_addfb(struct drm_device *dev,
   void *data, struct drm_file *file_priv)
 {
-   struct drm_mode_fb_cmd *r = data;
+   struct drm_mode_fb_cmd *or = data;
+   struct drm_mode_fb_cmd2 r;
+   struct drm_mode_config *config = >mode_config;
+   struct drm_framebuffer *fb;
+   int ret = 0;
+
+   /* Use new struct with format internally */
+   r.fb_id = or->fb_id;
+   r.width = or->width;
+   r.height = or->height;
+   r.pitches[0] = or->pitch;
+   r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
+   r.handle = or->handle;
+
+   if (!drm_core_check_feature(dev, DRIVER_MODESET))
+   return -EINVAL;
+
+   if ((config->min_width > r.width) || (r.width > config->max_width)) {
+   DRM_ERROR("mode new framebuffer width not within limits\n");
+   return -EINVAL;
+   }
+   if ((config->min_height > r.height) || (r.height > config->max_height)) 
{
+   DRM_ERROR("mode new framebuffer height not within limits\n");
+   return -EINVAL;
+   }
+
+   mutex_lock(>mode_config.mutex);
+
+   /* TODO check buffer is sufficiently large */
+   /* TODO setup destructor callback */
+
+   fb = dev->mode_config.funcs->fb_create(dev, file_priv, );
+   if (IS_ERR(fb)) {
+   DRM_ERROR("could not create framebuffer\n");
+   ret = PTR_ERR(fb);
+   goto out;
+   }
+
+   or->fb_id = fb->base.id;
+   list_add(>filp_head, _priv->fbs);
+   DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id);
+
+out:
+   mutex_unlock(>mode_config.mutex);
+   return ret;
+}
+
+/**
+ * drm_mode_addfb2 - add an FB to the graphics configuration
+ * @inode: inode from the ioctl
+ * @filp: file * from the ioctl
+ * @cmd: cmd from ioctl
+ * @arg: arg from ioctl
+ *
+ * LOCKING:
+ * Takes mode config lock.
+ *
+ * Add a new FB to the specified CRTC, given a user request with format.
+ *
+ * Called by the user via ioctl.
+ *
+ * RETURNS:
+ * Zero on success, errno on failure.
+ */
+int drm_mode_addfb2(struct drm_device *dev,
+   void *data, struct drm_file *file_priv)
+{
+   struct drm_mode_fb_cmd2 *r = data;
struct drm_mode_config *config = >mode_config;

[PATCH 1/5] drm: add plane support

[Jesse Barnes]

Planes are a bit like half-CRTCs.  They have a location and fb, but
don't drive outputs directly.  Add support for handling them to the core
KMS code.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/drm_crtc.c |  236 +++-
 drivers/gpu/drm/drm_drv.c  |3 +
 include/drm/drm.h  |3 +
 include/drm/drm_crtc.h |   76 ++-
 include/drm/drm_mode.h |   33 ++
 5 files changed, 348 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index fe738f0..0e129b1 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -535,6 +535,48 @@ void drm_encoder_cleanup(struct drm_encoder *encoder)
 }
 EXPORT_SYMBOL(drm_encoder_cleanup);

+void drm_plane_init(struct drm_device *dev, struct drm_plane *plane,
+   unsigned long possible_crtcs,
+   const struct drm_plane_funcs *funcs,
+   uint32_t *formats, uint32_t format_count)
+{
+   mutex_lock(>mode_config.mutex);
+
+   plane->dev = dev;
+   drm_mode_object_get(dev, >base, DRM_MODE_OBJECT_PLANE);
+   plane->funcs = funcs;
+   plane->format_types = kmalloc(sizeof(uint32_t) * format_count,
+ GFP_KERNEL);
+   if (!plane->format_types) {
+   DRM_DEBUG_KMS("out of memory when allocating plane\n");
+   drm_mode_object_put(dev, >base);
+   return;
+   }
+
+   memcpy(plane->format_types, formats, format_count);
+   plane->format_count = format_count;
+   plane->possible_crtcs = possible_crtcs;
+
+   list_add_tail(>head, >mode_config.plane_list);
+   dev->mode_config.num_plane++;
+
+   mutex_unlock(>mode_config.mutex);
+}
+EXPORT_SYMBOL(drm_plane_init);
+
+void drm_plane_cleanup(struct drm_plane *plane)
+{
+   struct drm_device *dev = plane->dev;
+
+   mutex_lock(>mode_config.mutex);
+   kfree(plane->format_types);
+   drm_mode_object_put(dev, >base);
+   list_del(>head);
+   dev->mode_config.num_plane--;
+   mutex_unlock(>mode_config.mutex);
+}
+EXPORT_SYMBOL(drm_plane_cleanup);
+
 /**
  * drm_mode_create - create a new display mode
  * @dev: DRM device
@@ -866,6 +908,7 @@ void drm_mode_config_init(struct drm_device *dev)
INIT_LIST_HEAD(>mode_config.encoder_list);
INIT_LIST_HEAD(>mode_config.property_list);
INIT_LIST_HEAD(>mode_config.property_blob_list);
+   INIT_LIST_HEAD(>mode_config.plane_list);
idr_init(>mode_config.crtc_idr);

mutex_lock(>mode_config.mutex);
@@ -1466,6 +1509,193 @@ out:
 }

 /**
+ * drm_mode_getplane_res - get plane info
+ * @dev: DRM device
+ * @data: ioctl data
+ * @file_priv: DRM file info
+ *
+ * Return an plane count and set of IDs.
+ */
+int drm_mode_getplane_res(struct drm_device *dev, void *data,
+   struct drm_file *file_priv)
+{
+   struct drm_mode_get_plane_res *plane_resp = data;
+   struct drm_mode_config *config;
+   struct drm_plane *plane;
+   uint32_t __user *plane_ptr;
+   int copied = 0, ret = 0;
+
+   if (!drm_core_check_feature(dev, DRIVER_MODESET))
+   return -EINVAL;
+
+   mutex_lock(>mode_config.mutex);
+   config = >mode_config;
+
+   /*
+* This ioctl is called twice, once to determine how much space is
+* needed, and the 2nd time to fill it.
+*/
+   if (config->num_plane &&
+   (plane_resp->count_planes >= config->num_plane)) {
+   plane_ptr = (uint32_t *)(unsigned long)plane_resp->plane_id_ptr;
+
+   list_for_each_entry(plane, >plane_list, head) {
+   if (put_user(plane->base.id, plane_ptr + copied)) {
+   ret = -EFAULT;
+   goto out;
+   }
+   copied++;
+   }
+   }
+   plane_resp->count_planes = config->num_plane;
+
+out:
+   mutex_unlock(>mode_config.mutex);
+   return ret;
+}
+
+/**
+ * drm_mode_getplane - get plane info
+ * @dev: DRM device
+ * @data: ioctl data
+ * @file_priv: DRM file info
+ *
+ * Return plane info, including formats supported, gamma size, any
+ * current fb, etc.
+ */
+int drm_mode_getplane(struct drm_device *dev, void *data,
+   struct drm_file *file_priv)
+{
+   struct drm_mode_get_plane *plane_resp = data;
+   struct drm_mode_object *obj;
+   struct drm_plane *plane;
+   uint32_t __user *format_ptr;
+   int ret = 0;
+
+   if (!drm_core_check_feature(dev, DRIVER_MODESET))
+   return -EINVAL;
+
+   mutex_lock(>mode_config.mutex);
+   obj = drm_mode_object_find(dev, plane_resp->plane_id,
+  DRM_MODE_OBJECT_PLANE);
+   if (!obj) {
+   ret = -EINVAL;
+   goto out;
+   }
+   plane = obj_to_plane(obj);
+
+   if (plane->crtc)
+ 

[PATCH] DRM planes

[Jesse Barnes]

In response to feedback, I've adjusted the new addfb2 ioctl to take per
component pitch and offset args.  Generally, the offset[0] field will be
0, but it's conceivable that some metadata could be stored at the start
of a given buffer, and an offset[0] allows the client to skip past that.
Similarly, pitch[0] will typically describe the whole buffer, but it's
possible to simply string together several planes into a single object
where individual pitch components matter.

Userland patches are available in the drm-overlays branches of my
personal libdrm and xf86-video-intel trees at freedesktop.org.  The
xf86-video-intel side works well enough to handle clipping (using a new
i915 specific ioctl for setting a destination color key) and play
videos, albeit without nice flipping.

Assuming no major objections, I think this is finally ready for
drm-next.

Thanks,
Jesse

[RFC] ttm merge ttm_backend & ttm_tt

[Jerome Glisse]

On Wed, Nov 02, 2011 at 11:04:43AM -0400, Konrad Rzeszutek Wilk wrote:
> On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote:
> > Hi,
> > 
> > So attached is patch serie (sorry for that i am away of my normal mail
> > config) which ultimately merge ttm_backend & ttm_tt it allows to get
> > rid of data duplication btw the two, especialy btw ttm_tt and driver
> > specific backend. So net result is less 300lines of code accross ttm
> > and driver.
> > 
> > Konrad given some of the upstream nouveau change, your patchserie
> > conflict and would lead to revert some nouveau fixes. I believe the
> > intention is to get the ttm-dma code into 3.3 (3.2 seems late but
> > dunno). If 3.3 is the aim than i will rebase your patch on top of this
> > serie, this should lower the number of change your serie needed.
> > 
> > Note that this is early code, only compile tested, i just wanted to
> > get feedback to know if anyone has objection on that.
> > 
> > For quick review, first 5 patches can be ignored, they are cleanup and
> > dead code removal or small fixes. The real action is in the last
> > patch.
> > 
> > Next set is to move page allocation through ttm_helper into the driver
> > thus making the whole dma stuff a driver business, driver who don't
> > care about dma (like vmw) could ignore it, while driver that have to
> > would deal with it through ttm_helper.
> 
> I took a look at them (1-3 are good. Please put Reviewed-by on them). The 
> 
> [PATCH 4/6] drm/ttm: convert page allocation to use page ptr array instead of 
> list
> 
> has a interesting side effect - previously the list was used so on the 
> get_pages
> the order of pages was:
> 
>  a,b,c,d,e,f
> 
> and when one was putting pages back, the list was iterated as so:
> 
>  for (i = 0; i < ttm->num_pages; ++i) {
>.. list_add(_page->lru, );
>/* list_add is like a stack, items are put in the front */
>  }
>  ttm_put_pages(,..);
> 
> which meant that the list would have the items in:
>  f,e,d,c,b,a
> 
> order. The TTM pool code would iterate over those in that order
> and call __free_page. Which means some performance drawback when the
> memory had to be iterated forward and then backwards, thought it probably
> was cached in the L3 cache, so probably no biggie.
> 
> I don't know why it was done that way, but I wrote the TTM DMA code
> to be optimized for that (and it has the code to reverse direction - b/c
> the testcases I used initially had the a,b,c,d,e,f order when doing get_pages
> and put_pages) - but I can alter the code to do it in the forward fashion 
> instead
> of the reverse fashion.. Better yet, it removes around 70 lines of code from 
> the
> TTM DMA.

Order in which we put them back on the list can be easily change, either
by use of add_tail or by iterating array from end to begining. i am not
sure how much this can impact things.

> Anyhow, it might be noting that in the commit description and perhaps make a 
> bug-fix
> for the put_pages being called in the error path instead of ttm_put_pages as 
> a seperate
> patch as you suggested.
> 
> 
> [PATCH 6/6] drm/ttm: merge ttm_backend and ttm_tt
> 
> That is going to be a bit tricky. You are using the pci_map_page, which 
> should not
> be used if the pages have been allocated via the pci_alloc_coherent (they are 
> already
> mapped). Perhaps a simple check such as:
> 
>   if !(ttm->be && ttm->be->func && ttm->be->func->get_pages) {
>   ttm->dma_address[i] = pci_map_page(dev->pdev, ...)
>   }

Your dma change are not suppose to be on top of that, idea is to add yet
another callbacks populate+free_page which will do either pci map page
or just use your code (ie use dma alloc and store dma addr into the
array). So there is a missing piece here before adding your dma code.
I just wanted to keep ttm_tt & ttm_backend merge as simple as possible
without major change. Adding the populate + get_page callback sounded
like good candidate for another patch.

> That long ttm->be && ttm->be->func can probably be wrapped in a nice macro
> and be put in ttm_page_alloc.h as:
> 
> diff --git a/include/drm/ttm/ttm_page_alloc.h 
> b/include/drm/ttm/ttm_page_alloc.h
> index daf5db6..39d6076 100644
> --- a/include/drm/ttm/ttm_page_alloc.h
> +++ b/include/drm/ttm/ttm_page_alloc.h
> @@ -30,6 +30,12 @@
>  #include "ttm_memory.h"
>  
>  #ifdef CONFIG_SWIOTLB
> +static inline bool ttm_dma_inuse(struct ttm_tt *ttm)
> +{
> + if (ttm && ttm->be && ttm->be->func && ttm->be->func->get_pages)
> + return true;
> + return false;
> +}
>  extern bool ttm_dma_override(struct ttm_backend_func *be);
>  
>  extern int ttm_dma_disable;
> @@ -47,6 +53,11 @@ void ttm_dma_page_alloc_fini(void);
>  extern int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
>  #else
>  #define ttm_dma_disable (1)
> +
> +static inline bool ttm_dma_inuse(struct ttm_tt *ttm)
> +{
> + return false;
> +}
>  static inline bool ttm_dma_override(struct ttm_backend_func *be)
>  {
>   

[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=40024

--- Comment #7 from Andrew Randrianasulu  2011-11-02 
05:15:55 PDT ---
from #nouveau channel:

http://people.freedesktop.org/~cbrill/dri-log/index.php?channel=nouveau_html=true_names==2011-08-19



15:53 #nouveau: < MaximLevitsky> mupuf: one thing though, that memtimings don't
seem to affect much, is that normal?
15:54 #nouveau: < MaximLevitsky> they are used, that for sure:
15:54 #nouveau: < MaximLevitsky> 4.864469] [drm] nouveau :01:00.0: Using
memory type: GGDR2
15:57 #nouveau: < mupuf> MaximLevitsky: the lowest perflvl should be faster
15:57 #nouveau: < mupuf> up to 4 times faster 



Yes, nvidia is not amd/ati. But memory always important, it seems

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[PATCH] drm/radeon: set hpd polarity at init time so hotplug detect works

[Alex Deucher]

On Wed, Nov 2, 2011 at 10:27 AM, Jerome Glisse  wrote:
> On Tue, Nov 01, 2011 at 05:27:26PM -0400, Alex Deucher wrote:
>> On Fri, Oct 28, 2011 at 5:52 PM, ? wrote:
>> > From: Jerome Glisse 
>> >
>> > Polarity needs to be set accordingly to connector status (connected
>> > or disconnected). Set it up at module init so first hotplug works
>> > reliably no matter what is the initial set of connector.
>>
>> Thinking about this more, we should probably do this on resume as
>> well. ?Calling it in hpd_init should cover all the bases.
>>
>> Alex
>>
>
> Good catch :)
>

Dave,

Do you want to revert Jerome's original patch or should I remove it as
part of this patch and resend?

Alex

> Reviewed-by: Jerome Glisse 
>
>> >
>> > Signed-off-by: Jerome Glisse 
>> > cc: stable at kernel.org
>> > ---
>> > ?drivers/gpu/drm/radeon/radeon_connectors.c | ? ?1 +
>> > ?1 files changed, 1 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
>> > b/drivers/gpu/drm/radeon/radeon_connectors.c
>> > index dec6cbe..bfdd48b 100644
>> > --- a/drivers/gpu/drm/radeon/radeon_connectors.c
>> > +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
>> > @@ -1789,6 +1789,7 @@ radeon_add_atom_connector(struct drm_device *dev,
>> > ? ? ? ? ? ? ? ? ? ? ? ?connector->polled = DRM_CONNECTOR_POLL_CONNECT;
>> > ? ? ? ?} else
>> > ? ? ? ? ? ? ? ?connector->polled = DRM_CONNECTOR_POLL_HPD;
>> > + ? ? ? radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
>> >
>> > ? ? ? ?connector->display_info.subpixel_order = subpixel_order;
>> > ? ? ? ?drm_sysfs_connector_add(connector);
>> > --
>> > 1.7.6.4
>> >
>> > ___
>> > dri-devel mailing list
>> > dri-devel at lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>> >
>
>> From 90a532b643cbe882497eaadb78f7d1997af6e22b Mon Sep 17 00:00:00 2001
>> From: Alex Deucher 
>> Date: Tue, 1 Nov 2011 17:23:15 -0400
>> Subject: [PATCH] drm/radeon/kms: set HPD polarity in hpd_init()
>>
>> Polarity needs to be set accordingly to connector status (connected
>> or disconnected). Set it up in hpd_init() so first hotplug works
>> reliably no matter what is the initial set of connector. hpd_init()
>> also covers resume so HPD will work correctly after resume as well.
>>
>> Signed-off-by: Alex Deucher 
>> Cc: stable at kernel.org
>> ---
>> ?drivers/gpu/drm/radeon/evergreen.c | ? ?1 +
>> ?drivers/gpu/drm/radeon/r100.c ? ? ?| ? ?1 +
>> ?drivers/gpu/drm/radeon/r600.c ? ? ?| ? 19 +--
>> ?drivers/gpu/drm/radeon/rs600.c ? ? | ? ?1 +
>> ?4 files changed, 12 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/evergreen.c 
>> b/drivers/gpu/drm/radeon/evergreen.c
>> index db9027d..7ce9c87 100644
>> --- a/drivers/gpu/drm/radeon/evergreen.c
>> +++ b/drivers/gpu/drm/radeon/evergreen.c
>> @@ -353,6 +353,7 @@ void evergreen_hpd_init(struct radeon_device *rdev)
>> ? ? ? ? ? ? ? default:
>> ? ? ? ? ? ? ? ? ? ? ? break;
>> ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
>> ? ? ? }
>> ? ? ? if (rdev->irq.installed)
>> ? ? ? ? ? ? ? evergreen_irq_set(rdev);
>> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
>> index 8f8b8fa..4191eaf 100644
>> --- a/drivers/gpu/drm/radeon/r100.c
>> +++ b/drivers/gpu/drm/radeon/r100.c
>> @@ -536,6 +536,7 @@ void r100_hpd_init(struct radeon_device *rdev)
>> ? ? ? ? ? ? ? default:
>> ? ? ? ? ? ? ? ? ? ? ? break;
>> ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
>> ? ? ? }
>> ? ? ? if (rdev->irq.installed)
>> ? ? ? ? ? ? ? r100_irq_set(rdev);
>> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
>> index 3aa46d7..4d85398 100644
>> --- a/drivers/gpu/drm/radeon/r600.c
>> +++ b/drivers/gpu/drm/radeon/r600.c
>> @@ -762,13 +762,14 @@ void r600_hpd_init(struct radeon_device *rdev)
>> ? ? ? struct drm_device *dev = rdev->ddev;
>> ? ? ? struct drm_connector *connector;
>>
>> - ? ? if (ASIC_IS_DCE3(rdev)) {
>> - ? ? ? ? ? ? u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 
>> DC_HPDx_RX_INT_TIMER(0xfa);
>> - ? ? ? ? ? ? if (ASIC_IS_DCE32(rdev))
>> - ? ? ? ? ? ? ? ? ? ? tmp |= DC_HPDx_EN;
>> + ? ? list_for_each_entry(connector, >mode_config.connector_list, head) 
>> {
>> + ? ? ? ? ? ? struct radeon_connector *radeon_connector = 
>> to_radeon_connector(connector);
>> +
>> + ? ? ? ? ? ? if (ASIC_IS_DCE3(rdev)) {
>> + ? ? ? ? ? ? ? ? ? ? u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 
>> DC_HPDx_RX_INT_TIMER(0xfa);
>> + ? ? ? ? ? ? ? ? ? ? if (ASIC_IS_DCE32(rdev))
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? tmp |= DC_HPDx_EN;
>>
>> - ? ? ? ? ? ? list_for_each_entry(connector, 
>> >mode_config.connector_list, head) {
>> - ? ? ? ? ? ? ? ? ? ? struct radeon_connector *radeon_connector = 
>> to_radeon_connector(connector);
>> ? ? ? ? ? ? ? ? ? ? ? switch (radeon_connector->hpd.hpd) {
>> ? ? ? ? ? ? ? ? ? ? ? case RADEON_HPD_1:
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Tue,  1 Nov 2011 23:20:26 -0700, Keith Packard  wrote:

>   intel_dp = enc_to_intel_dp(encoder);
> - if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
> + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
> is_pch_edp(intel_dp)) {
>   lane_count = intel_dp->lane_count;
>   break;
> - } else if (is_edp(intel_dp)) {
> + } else if (is_cpu_edp(intel_dp)) {
>   lane_count = dev_priv->edp.lanes;
>   break;

Thinking about this one more time -- if we ever want to use
dev_priv->edp.lanes, we should use it in
intel_dp_max_lane_count. intel_dp_set_m_n should use
intel_dp->lane_count unconditionally as that's the value we've used
everywhere else for mode setting.

Perhaps we should use it for monitors that don't include the
MAX_LANE_COUNT field in the dpcd? Perhaps we should use it on all eDP
monitors?

-- 
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[PATCH] DRM: EXYNOS: Add EXYNOS DRM maintainer entry

[Kyungmin Park]

From: Kyungmin Park 

As Exynos DRM is merged at mainline. Also update the maintainer entry.

Signed-off-by: Kyungmin Park 
---
diff --git a/MAINTAINERS b/MAINTAINERS
index 5d6941f..1deeac9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2327,6 +2327,13 @@ S:   Supported
 F: drivers/gpu/drm/i915
 F: include/drm/i915*

+DRM DRIVERS FOR EXYNOS
+M: Inki Dae 
+L: dri-devel at lists.freedesktop.org
+S: Supported
+F: drivers/gpu/drm/exynos
+F: include/drm/exynos*
+
 DSCC4 DRIVER
 M: Francois Romieu 
 L: netdev at vger.kernel.org

[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=40024

--- Comment #6 from Andrew Randrianasulu  2011-11-02 
04:31:12 PDT ---
for memtimings on radeon 7500 (changed via rovclock, while running proprietary
driver) see forum post  here and down :

http://forums.gentoo.org/viewtopic-p-3687568.html#3687568

---copy--

#rovclock -i
Radeon overclock 0.6e by Hasw (hasw at hasw.net)

Found ATI card on 01:00, device id: 0x4c57
I/O base address: 0x3000
Video BIOS shadow found @ 0xc
Reference clock from BIOS: 27.0 MHz
Memory size: 32768 kB
Memory channels: 2, CD,CH only: 0
tRcdRD:   9
tRcdWR:   4
tRP:  8
tRAS: 18
tRRD: 3
tR2W-CL:  3
tWR:  4
tW2R: 2
tW2Rsb:   1
tR2R: 2
tRFC: 20
tWL(0.5): 2
tCAS: 3
tCMD: 0
tSTR: 1
XTAL: 27.0 MHz, RefDiv: 6

Core: 258.75 MHz, Mem: 364.50 MHz

copy-end-

And after over-clocking, note, some timings were lowered

copy2

UberPinguin ubrpngn # rovclock -i
Radeon overclock 0.6e by Hasw (hasw at hasw.net)

Found ATI card on 01:00, device id: 0x4c57
I/O base address: 0x3000
Video BIOS shadow found @ 0xc
Reference clock from BIOS: 27.0 MHz
Memory size: 32768 kB
Memory channels: 2, CD,CH only: 0
tRcdRD:   5
tRcdWR:   2
tRP:  4
tRAS: 14
tRRD: 3
tR2W-CL:  2
tWR:  3
tW2R: 0
tW2Rsb:   1
tR2R: 1
tRFC: 14
tWL(0.5): 2
tCAS: 3
tCMD: 0
tSTR: 1
XTAL: 27.0 MHz, RefDiv: 6

Core: 290.25 MHz, Mem: 380.25 MHz
--copy2 ends


reported speed boost: 

from ~647fps to ~1018 in glxgears

guess 260 ->290 engine and 364 -> 380 mem  can't explain such big boost alone?

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Adam Jackson]

On 11/2/11 2:20 AM, Keith Packard wrote:

> + if (intel_dp->link_configuration [1] & 
> DP_LANE_COUNT_ENHANCED_FRAME_EN)
> + intel_dp->DP |= DP_ENHANCED_FRAMING;
> +
> + /*
> +  * Check for DPCD version>  1.1 and enhanced framing support
> +  */
> + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
> + (intel_dp->dpcd[DP_MAX_LANE_COUNT] & 
> DP_ENHANCED_FRAME_CAP)) {
> + intel_dp->link_configuration[1] |= 
> DP_LANE_COUNT_ENHANCED_FRAME_EN;
> + intel_dp->DP |= DP_ENHANCED_FRAMING;
> + }

Redundant.  You've already done the link_configuration |= above in the 
common code.  You can drop the second if chunk altogether.

In related news, the corresponding section for this in TRANS_DP_CTL 
setup appears to turn on enhanced framing unconditionally.  This is 
probably not a big deal, I don't think I've ever seen a display not 
support it, but.

- ajax

RFC: Radeon multi ring support branch

[Christian König]

On 31.10.2011 16:05, Jerome Glisse wrote:
> On Sat, Oct 29, 2011 at 03:00:28PM +0200, Christian K?nig wrote:
>> Hello everybody,
>>
>> to support multiple compute rings, async DMA engines and UVD we need
>> to teach the radeon kernel module how to sync buffers between
>> different rings and make some changes to the command submission
>> ioctls.
>>
>> Since we can't release any documentation about async DMA or UVD
>> (yet), my current branch concentrates on getting the additional
>> compute rings on cayman running. Unfortunately those rings have
>> hardware bugs that can't be worked around, so they are actually not
>> very useful in a production environment, but they should do quite
>> well for this testing purpose.
>>
>> The branch can be found here:
>> http://cgit.freedesktop.org/~deathsimple/linux/log/
>>
>> Since some of the patches are quite intrusive, constantly rebaseing
>> them could get a bit painful. So I would like to see most of the
>> stuff included into drm-next, even if we don't make use of the new
>> functionality right now.
>>
>> Comments welcome,
>> Christian.
> So for all patches except the interface change see below
> Reviewed-by: Jerome Glisse
>
> For the interface change, as discussed previously, i believe prio
> should be a userspace argument, kernel could override it.
>
>
Yeah, I'm still not sure what we should do about the priority.

Say for example we have 2 processes. Process A is sending compute jobs 
both with high and low priority, while process B is sending jobs with 
only high priority. Unfortunately the jobs send by B doesn't utilizes 
the hardware to its limits, so that even jobs on a lower priority rings 
get their share of the compute resources.

The effect is that it reverses the priority A wants for its jobs. The 
high priority jobs of A get executed much slower than the low priority 
jobs of A, because B is spamming the hight priority ring with its under 
utilizing jobs.

In such a situation it would be better to adjust the job scheduling a 
bit so that jobs of process A gets on ring 1 on jobs from B get on ring 
2, but I have now idea how to detect such a situation. Anyway, the 
primary goal of the different compute rings is to separate compute from 
GFX so that even with big compute jobs running the system still stays 
responsible to user input, so I think adding a better scheduling for 
compute jobs can be done much later.

Christian.

[RFC] ttm merge ttm_backend & ttm_tt

[Konrad Rzeszutek Wilk]

On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote:
> Hi,
> 
> So attached is patch serie (sorry for that i am away of my normal mail
> config) which ultimately merge ttm_backend & ttm_tt it allows to get
> rid of data duplication btw the two, especialy btw ttm_tt and driver
> specific backend. So net result is less 300lines of code accross ttm
> and driver.
> 
> Konrad given some of the upstream nouveau change, your patchserie
> conflict and would lead to revert some nouveau fixes. I believe the
> intention is to get the ttm-dma code into 3.3 (3.2 seems late but
> dunno). If 3.3 is the aim than i will rebase your patch on top of this
> serie, this should lower the number of change your serie needed.
> 
> Note that this is early code, only compile tested, i just wanted to
> get feedback to know if anyone has objection on that.
> 
> For quick review, first 5 patches can be ignored, they are cleanup and
> dead code removal or small fixes. The real action is in the last
> patch.
> 
> Next set is to move page allocation through ttm_helper into the driver
> thus making the whole dma stuff a driver business, driver who don't
> care about dma (like vmw) could ignore it, while driver that have to
> would deal with it through ttm_helper.

I took a look at them (1-3 are good. Please put Reviewed-by on them). The 

[PATCH 4/6] drm/ttm: convert page allocation to use page ptr array instead of 
list

has a interesting side effect - previously the list was used so on the get_pages
the order of pages was:

 a,b,c,d,e,f

and when one was putting pages back, the list was iterated as so:

 for (i = 0; i < ttm->num_pages; ++i) {
   .. list_add(_page->lru, );
   /* list_add is like a stack, items are put in the front */
 }
 ttm_put_pages(,..);

which meant that the list would have the items in:
 f,e,d,c,b,a

order. The TTM pool code would iterate over those in that order
and call __free_page. Which means some performance drawback when the
memory had to be iterated forward and then backwards, thought it probably
was cached in the L3 cache, so probably no biggie.

I don't know why it was done that way, but I wrote the TTM DMA code
to be optimized for that (and it has the code to reverse direction - b/c
the testcases I used initially had the a,b,c,d,e,f order when doing get_pages
and put_pages) - but I can alter the code to do it in the forward fashion 
instead
of the reverse fashion.. Better yet, it removes around 70 lines of code from the
TTM DMA.

Anyhow, it might be noting that in the commit description and perhaps make a 
bug-fix
for the put_pages being called in the error path instead of ttm_put_pages as a 
seperate
patch as you suggested.


[PATCH 6/6] drm/ttm: merge ttm_backend and ttm_tt

That is going to be a bit tricky. You are using the pci_map_page, which should 
not
be used if the pages have been allocated via the pci_alloc_coherent (they are 
already
mapped). Perhaps a simple check such as:

if !(ttm->be && ttm->be->func && ttm->be->func->get_pages) {
ttm->dma_address[i] = pci_map_page(dev->pdev, ...)
}

That long ttm->be && ttm->be->func can probably be wrapped in a nice macro
and be put in ttm_page_alloc.h as:

diff --git a/include/drm/ttm/ttm_page_alloc.h b/include/drm/ttm/ttm_page_alloc.h
index daf5db6..39d6076 100644
--- a/include/drm/ttm/ttm_page_alloc.h
+++ b/include/drm/ttm/ttm_page_alloc.h
@@ -30,6 +30,12 @@
 #include "ttm_memory.h"

 #ifdef CONFIG_SWIOTLB
+static inline bool ttm_dma_inuse(struct ttm_tt *ttm)
+{
+   if (ttm && ttm->be && ttm->be->func && ttm->be->func->get_pages)
+   return true;
+   return false;
+}
 extern bool ttm_dma_override(struct ttm_backend_func *be);

 extern int ttm_dma_disable;
@@ -47,6 +53,11 @@ void ttm_dma_page_alloc_fini(void);
 extern int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
 #else
 #define ttm_dma_disable (1)
+
+static inline bool ttm_dma_inuse(struct ttm_tt *ttm)
+{
+   return false;
+}
 static inline bool ttm_dma_override(struct ttm_backend_func *be)
 {
return false;


Hmm, I am also not clear what you are using as base? 3.1 does not seem
to have a whole bunch of the things your code is doing. Like the
be->func->clear call from nouveau_sgdma.c.

What base should I be looking at? Is this the base that Dave has for 3.2?

[Bug 28426] hardware cursor corruption with radeon+kms

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28426

--- Comment #8 from Michel D?nzer  2011-11-02 03:53:49 
PDT ---
Kernel 3.0.7 has one HW cursor fix, 3.1 has more and other HW cursor changes.
Do any of those help?

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[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

[Keith Packard]

On Wed, 02 Nov 2011 09:12:13 +, Chris Wilson  
wrote:

> This would seem to be a separate chunk to initiate training on only the
> lanes we intend to use.
> -Chris

Here's that patch separated out:

commit e7fecae483754ca9a42312be18f58ceb454702fe
Author: Keith Packard 
Date:   Wed Nov 2 10:17:59 2011 -0700

drm/i915: Initiate DP link training only on the lanes we'll be using

Limit the link training setting command to the lanes needed for the
current mode. It seems vaguely possible that a monitor will try to
train the other lanes and fail in some way, so this seems like the
safer plan.

Signed-off-by: Keith Packard 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a4fa64..02b56ce 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1567,8 +1567,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,

ret = intel_dp_aux_native_write(intel_dp,
DP_TRAINING_LANE0_SET,
-   intel_dp->train_set, 4);
-   if (ret != 4)
+   intel_dp->train_set,
+   intel_dp->lane_count);
+   if (ret != intel_dp->lane_count)
return false;

return true;


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[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Keith Packard]

On Wed, 2 Nov 2011 09:23:10 -0700, Jesse Barnes  
wrote:

> Note that PP_READY will incorrectly depend on some other register
> values, so in some configs the panel will happily power up even if
> PP_READY isn't set yet...

Here's the new version of that chunk:

@@ -906,32 +905,56 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
}
 }

-static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+#define IDLE_ON_MASK   (PP_ON | 0| PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE  (PP_ON | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_ON_IDLE)
+
+#define IDLE_OFF_MASK  (PP_ON | 0| PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_OFF_VALUE (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+#define IDLE_CYCLE_MASK(PP_ON | 0| PP_SEQUENCE_MASK | 
PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE   (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
+  u32 mask,
+  u32 value)
 {


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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 02 Nov 2011 11:29:53 -0400, Adam Jackson  wrote:

> Redundant.  You've already done the link_configuration |= above in the 
> common code.  You can drop the second if chunk altogether.

Here's the new version of that chunk of patch:

@@ -850,32 +864,45 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_write_eld(encoder, adjusted_mode);
}
-
memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
intel_dp->link_configuration[0] = intel_dp->link_bw;
intel_dp->link_configuration[1] = intel_dp->lane_count;
intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
-
/*
 * Check for DPCD version > 1.1 and enhanced framing support
 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
intel_dp->link_configuration[1] |= 
DP_LANE_COUNT_ENHANCED_FRAME_EN;
-   intel_dp->DP |= DP_ENHANCED_FRAMING;
}

-   /* CPT DP's pipe select is decided in TRANS_DP_CTL */
-   if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
-   intel_dp->DP |= DP_PIPEB_SELECT;
+   /* Split out the IBX/CPU vs CPT settings */

-   if (is_cpu_edp(intel_dp)) {
-   /* don't miss out required setting for eDP */
-   intel_dp->DP |= DP_PLL_ENABLE;
-   if (adjusted_mode->clock < 20)
-   intel_dp->DP |= DP_PLL_FREQ_160MHZ;
-   else
-   intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+   if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
+   intel_dp->DP |= intel_dp->color_range;
+
+   if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+   intel_dp->DP |= DP_SYNC_HS_HIGH;
+   if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+   intel_dp->DP |= DP_SYNC_VS_HIGH;
+   intel_dp->DP |= DP_LINK_TRAIN_OFF;
+
+   if (intel_dp->link_configuration[1] & 
DP_LANE_COUNT_ENHANCED_FRAME_EN)
+   intel_dp->DP |= DP_ENHANCED_FRAMING;
+
+   if (intel_crtc->pipe == 1)
+   intel_dp->DP |= DP_PIPEB_SELECT;
+
+   if (is_cpu_edp(intel_dp)) {
+   /* don't miss out required setting for eDP */
+   intel_dp->DP |= DP_PLL_ENABLE;
+   if (adjusted_mode->clock < 20)
+   intel_dp->DP |= DP_PLL_FREQ_160MHZ;
+   else
+   intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+   }
+   } else {
+   intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
}
 }

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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 02 Nov 2011 13:13:52 -0400, Adam Jackson  wrote:

> Given the choice of trusting DPCD or the VBT, I'd definitely prefer
> DPCD.

Except that the DPCD is coded into the monitor while the VBT is done by
the platform. And, it's the platform which may neglect to connect some
of the wires. In any case, if we want to look at these values, we should
be doing it before computing the M/N ratio so that we actually set the
hardware up correctly.

Any bets on how long until we find a machine that has right value in the
VBT and the wrong one in DPCD? Or a machine with wrong values in both places?

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[Bug 39272] Ridiculous performances with HD5870

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=39272

--- Comment #1 from Andrew Randrianasulu  2011-11-02 
03:28:48 PDT ---
Try patch from https://bugs.freedesktop.org/show_bug.cgi?id=38917 ?

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[PATCH] drm/radeon: set hpd polarity at init time so hotplug detect works

[Jerome Glisse]

On Tue, Nov 01, 2011 at 05:27:26PM -0400, Alex Deucher wrote:
> On Fri, Oct 28, 2011 at 5:52 PM,   wrote:
> > From: Jerome Glisse 
> >
> > Polarity needs to be set accordingly to connector status (connected
> > or disconnected). Set it up at module init so first hotplug works
> > reliably no matter what is the initial set of connector.
> 
> Thinking about this more, we should probably do this on resume as
> well.  Calling it in hpd_init should cover all the bases.
> 
> Alex
> 

Good catch :)

Reviewed-by: Jerome Glisse 

> >
> > Signed-off-by: Jerome Glisse 
> > cc: stable at kernel.org
> > ---
> > ?drivers/gpu/drm/radeon/radeon_connectors.c | ? ?1 +
> > ?1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
> > b/drivers/gpu/drm/radeon/radeon_connectors.c
> > index dec6cbe..bfdd48b 100644
> > --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> > +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> > @@ -1789,6 +1789,7 @@ radeon_add_atom_connector(struct drm_device *dev,
> > ? ? ? ? ? ? ? ? ? ? ? ?connector->polled = DRM_CONNECTOR_POLL_CONNECT;
> > ? ? ? ?} else
> > ? ? ? ? ? ? ? ?connector->polled = DRM_CONNECTOR_POLL_HPD;
> > + ? ? ? radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
> >
> > ? ? ? ?connector->display_info.subpixel_order = subpixel_order;
> > ? ? ? ?drm_sysfs_connector_add(connector);
> > --
> > 1.7.6.4
> >
> > ___
> > dri-devel mailing list
> > dri-devel at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
> >

> From 90a532b643cbe882497eaadb78f7d1997af6e22b Mon Sep 17 00:00:00 2001
> From: Alex Deucher 
> Date: Tue, 1 Nov 2011 17:23:15 -0400
> Subject: [PATCH] drm/radeon/kms: set HPD polarity in hpd_init()
> 
> Polarity needs to be set accordingly to connector status (connected
> or disconnected). Set it up in hpd_init() so first hotplug works
> reliably no matter what is the initial set of connector. hpd_init()
> also covers resume so HPD will work correctly after resume as well.
> 
> Signed-off-by: Alex Deucher 
> Cc: stable at kernel.org
> ---
>  drivers/gpu/drm/radeon/evergreen.c |1 +
>  drivers/gpu/drm/radeon/r100.c  |1 +
>  drivers/gpu/drm/radeon/r600.c  |   19 +--
>  drivers/gpu/drm/radeon/rs600.c |1 +
>  4 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen.c 
> b/drivers/gpu/drm/radeon/evergreen.c
> index db9027d..7ce9c87 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -353,6 +353,7 @@ void evergreen_hpd_init(struct radeon_device *rdev)
>   default:
>   break;
>   }
> + radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
>   }
>   if (rdev->irq.installed)
>   evergreen_irq_set(rdev);
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index 8f8b8fa..4191eaf 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -536,6 +536,7 @@ void r100_hpd_init(struct radeon_device *rdev)
>   default:
>   break;
>   }
> + radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
>   }
>   if (rdev->irq.installed)
>   r100_irq_set(rdev);
> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
> index 3aa46d7..4d85398 100644
> --- a/drivers/gpu/drm/radeon/r600.c
> +++ b/drivers/gpu/drm/radeon/r600.c
> @@ -762,13 +762,14 @@ void r600_hpd_init(struct radeon_device *rdev)
>   struct drm_device *dev = rdev->ddev;
>   struct drm_connector *connector;
>  
> - if (ASIC_IS_DCE3(rdev)) {
> - u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 
> DC_HPDx_RX_INT_TIMER(0xfa);
> - if (ASIC_IS_DCE32(rdev))
> - tmp |= DC_HPDx_EN;
> + list_for_each_entry(connector, >mode_config.connector_list, head) {
> + struct radeon_connector *radeon_connector = 
> to_radeon_connector(connector);
> +
> + if (ASIC_IS_DCE3(rdev)) {
> + u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 
> DC_HPDx_RX_INT_TIMER(0xfa);
> + if (ASIC_IS_DCE32(rdev))
> + tmp |= DC_HPDx_EN;
>  
> - list_for_each_entry(connector, 
> >mode_config.connector_list, head) {
> - struct radeon_connector *radeon_connector = 
> to_radeon_connector(connector);
>   switch (radeon_connector->hpd.hpd) {
>   case RADEON_HPD_1:
>   WREG32(DC_HPD1_CONTROL, tmp);
> @@ -798,10 +799,7 @@ void r600_hpd_init(struct radeon_device *rdev)
>   default:
>   break;
>   }
> - }
> - } else {
> - list_for_each_entry(connector, 
> 

RFC: Radeon multi ring support branch

[Jerome Glisse]

On Wed, Nov 02, 2011 at 11:12:42AM +0100, Christian K?nig wrote:
> On 31.10.2011 16:05, Jerome Glisse wrote:
> >On Sat, Oct 29, 2011 at 03:00:28PM +0200, Christian K?nig wrote:
> >>Hello everybody,
> >>
> >>to support multiple compute rings, async DMA engines and UVD we need
> >>to teach the radeon kernel module how to sync buffers between
> >>different rings and make some changes to the command submission
> >>ioctls.
> >>
> >>Since we can't release any documentation about async DMA or UVD
> >>(yet), my current branch concentrates on getting the additional
> >>compute rings on cayman running. Unfortunately those rings have
> >>hardware bugs that can't be worked around, so they are actually not
> >>very useful in a production environment, but they should do quite
> >>well for this testing purpose.
> >>
> >>The branch can be found here:
> >>http://cgit.freedesktop.org/~deathsimple/linux/log/
> >>
> >>Since some of the patches are quite intrusive, constantly rebaseing
> >>them could get a bit painful. So I would like to see most of the
> >>stuff included into drm-next, even if we don't make use of the new
> >>functionality right now.
> >>
> >>Comments welcome,
> >>Christian.
> >So for all patches except the interface change see below
> >Reviewed-by: Jerome Glisse
> >
> >For the interface change, as discussed previously, i believe prio
> >should be a userspace argument, kernel could override it.
> >
> >
> Yeah, I'm still not sure what we should do about the priority.
> 
> Say for example we have 2 processes. Process A is sending compute
> jobs both with high and low priority, while process B is sending
> jobs with only high priority. Unfortunately the jobs send by B
> doesn't utilizes the hardware to its limits, so that even jobs on a
> lower priority rings get their share of the compute resources.
> 
> The effect is that it reverses the priority A wants for its jobs.
> The high priority jobs of A get executed much slower than the low
> priority jobs of A, because B is spamming the hight priority ring
> with its under utilizing jobs.
> 
> In such a situation it would be better to adjust the job scheduling
> a bit so that jobs of process A gets on ring 1 on jobs from B get on
> ring 2, but I have now idea how to detect such a situation. Anyway,
> the primary goal of the different compute rings is to separate
> compute from GFX so that even with big compute jobs running the
> system still stays responsible to user input, so I think adding a
> better scheduling for compute jobs can be done much later.
> 
> Christian.

I think this was already pointed out, my idea was to have the prio
argument in ioctl and have kernel override it. For instance i was
thinking the drm master could set for each process what is the
top priority this process can get, so which ever process is drm
master would choose. Or we could do some kind of userspace daemon
that would have special right from kernel/drm pov and would be
able to set the max priority each process get on the gpu.

But as a first step just getting the prio as an argument sounds
what we should do as right now we won't be doing anykind of
real GPU scheduling.

Cheers,
Jerome

[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

[Keith Packard]

On Wed, 02 Nov 2011 09:12:13 +, Chris Wilson  
wrote:

> This would seem to be a separate chunk to initiate training on only the
> lanes we intend to use.

Yeah, this got left in during some debugging; it might be a good thing
to do, but it's completely separate. I've pulled it out into a separate
patch.

-- 
keith.packard at intel.com
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[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Keith Packard]

On Wed, 2 Nov 2011 09:23:10 -0700, Jesse Barnes  
wrote:

> Note that PP_READY will incorrectly depend on some other register
> values, so in some configs the panel will happily power up even if
> PP_READY isn't set yet...

Yeah, I'd like to understand why PP_READY isn't getting set; we should
have all of the other pieces ready before we turn on the panel. But,
given that it's really just a sanity check, it probably doesn't make
sense to spin for 5 seconds waiting for a bit to turn on that won't.

I've just removed that bit from the IDLE_ON_MASK and IDLE_ON_VALUE.

-- 
keith.packard at intel.com
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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 2 Nov 2011 09:20:19 -0700, Jesse Barnes  
wrote:

> But I was curious about this hunk:
> 
> @@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
> drm_display_mode *mode,
>   continue;
>  
>   intel_dp = enc_to_intel_dp(encoder);
> - if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
> + if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
> is_pch_edp(intel_dp)) {
>   lane_count = intel_dp->lane_count;
>   break;
> - } else if (is_edp(intel_dp)) {
> + } else if (is_cpu_edp(intel_dp)) {
>   lane_count = dev_priv->edp.lanes;
>   break;
>   }
> 
> I guess this means we can't trust the BIOS settings for PCH eDP?

I'm pretty sure this isn't the right place to look at this value in any
case; we're setting the m/n ratios after already deciding how many lanes
to use. Getting this wrong means sending the wrong timing to the
monitor, not setting a different mode.

In any case, my AIO box sets the BIOS value to 1, when it needs 2 lanes
for the mode it uses.

-- 
keith.packard at intel.com
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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

On Wed, 02 Nov 2011 11:29:53 -0400, Adam Jackson  wrote:

> Redundant.  You've already done the link_configuration |= above in the 
> common code.  You can drop the second if chunk altogether.

Thanks for catching this mistake; cut programming without the cut part...

> In related news, the corresponding section for this in TRANS_DP_CTL 
> setup appears to turn on enhanced framing unconditionally.  This is 
> probably not a big deal, I don't think I've ever seen a display not 
> support it, but.

Yeah, it's actually a huge pain because TRANS_DP_CTL is set up in
ironlake_pch_enable, which is part of the crtc enable path not the
encoder mode set path, and getting to the appropriate intel_dp structure
takes a walk through all of the encoders to find the matching one.

I think we could move the TRANS_DP_CTL code into intel_dp.c where it
belongs; this chunk was stuck inside ironlake_crtc_dpms by Zhenyu last
year when DP/eDP support for Sandybridge and Cougarpoint was added in
commit e3421a189447c0b8cd0aff5c299f53b5ab7c38f6.

Most of the TRANS_DP_CTL chunk inside ironlake_pch_enable should just
get moved to intel_dp_mode_set, but I don't know if the
TRANS_DP_OUTPUT_ENABLE bit needs to be set before
intel_enable_transcoder is called; if it does, then we'd need to
preserve that piece inside ironlake_pch_enable, otherwise that bit would
move to intel_dp_commit.

-- 
keith.packard at intel.com
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[PATCH 5/5] vmwgfx: Fix hw cursor position

[Thomas Hellstrom]

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Jakob Bornecrantz 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 1cebf64..5ccce1c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -176,7 +176,9 @@ err_unreserve:
return 0;
}

-   vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
+   vmw_cursor_update_position(dev_priv, true,
+  du->cursor_x + du->hotspot_x,
+  du->cursor_y + du->hotspot_y);

return 0;
 }
@@ -191,7 +193,8 @@ int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, 
int y)
du->cursor_y = y + crtc->y;

vmw_cursor_update_position(dev_priv, shown,
-  du->cursor_x, du->cursor_y);
+  du->cursor_x + du->hotspot_x,
+  du->cursor_y + du->hotspot_y);

return 0;
 }
-- 
1.7.4.4

[PATCH 4/5] vmwgfx: Infrastructure for explicit placement

[Thomas Hellstrom]

Make it possible to use explicit placement
(although not hooked up with a user-space interface yet)
and relax the single framebuffer limit to only apply to implicit placement.

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Jakob Bornecrantz 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h  |1 +
 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c  |1 +
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c |   52 ++---
 3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
index 815cf99..af8e6e5 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
@@ -102,6 +102,7 @@ struct vmw_display_unit {
 */
int gui_x;
int gui_y;
+   bool is_implicit;
 };

 #define vmw_crtc_to_du(x) \
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index bbfe381..90c5e39 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -337,6 +337,7 @@ static int vmw_ldu_init(struct vmw_private *dev_priv, 
unsigned unit)
ldu->base.pref_width = 800;
ldu->base.pref_height = 600;
ldu->base.pref_mode = NULL;
+   ldu->base.is_implicit = true;

drm_connector_init(dev, connector, _legacy_connector_funcs,
   DRM_MODE_CONNECTOR_VIRTUAL);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index ea65834..4defdcf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -36,9 +36,9 @@
container_of(x, struct vmw_screen_object_unit, base.connector)

 struct vmw_screen_object_display {
-   unsigned num_active;
+   unsigned num_implicit;

-   struct vmw_framebuffer *fb;
+   struct vmw_framebuffer *implicit_fb;
 };

 /**
@@ -51,7 +51,7 @@ struct vmw_screen_object_unit {
struct vmw_dma_buffer *buffer; /**< Backing store buffer */

bool defined;
-   bool active;
+   bool active_implicit;
 };

 static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
@@ -75,10 +75,10 @@ static void vmw_sou_del_active(struct vmw_private *vmw_priv,
 {
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;

-   if (sou->active) {
-   if (--(ld->num_active) == 0)
-   ld->fb = NULL;
-   sou->active = false;
+   if (sou->active_implicit) {
+   if (--(ld->num_implicit) == 0)
+   ld->implicit_fb = NULL;
+   sou->active_implicit = false;
}
 }

@@ -88,12 +88,12 @@ static void vmw_sou_add_active(struct vmw_private *vmw_priv,
 {
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;

-   BUG_ON(!ld->num_active && ld->fb);
+   BUG_ON(!ld->num_implicit && ld->implicit_fb);

-   if (!sou->active) {
-   ld->fb = vfb;
-   sou->active = true;
-   ld->num_active++;
+   if (!sou->active_implicit && sou->base.is_implicit) {
+   ld->implicit_fb = vfb;
+   sou->active_implicit = true;
+   ld->num_implicit++;
}
 }

@@ -132,8 +132,13 @@ static int vmw_sou_fifo_create(struct vmw_private 
*dev_priv,
(sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
cmd->obj.size.width = mode->hdisplay;
cmd->obj.size.height = mode->vdisplay;
-   cmd->obj.root.x = x;
-   cmd->obj.root.y = y;
+   if (sou->base.is_implicit) {
+   cmd->obj.root.x = x;
+   cmd->obj.root.y = y;
+   } else {
+   cmd->obj.root.x = sou->base.gui_x;
+   cmd->obj.root.y = sou->base.gui_y;
+   }

/* Ok to assume that buffer is pinned in vram */
vmw_bo_get_guest_ptr(>buffer->base, >obj.backingStore.ptr);
@@ -280,10 +285,11 @@ static int vmw_sou_crtc_set_config(struct drm_mode_set 
*set)
}

/* sou only supports one fb active at the time */
-   if (dev_priv->sou_priv->fb && vfb &&
-   !(dev_priv->sou_priv->num_active == 1 &&
- sou->active) &&
-   dev_priv->sou_priv->fb != vfb) {
+   if (sou->base.is_implicit &&
+   dev_priv->sou_priv->implicit_fb && vfb &&
+   !(dev_priv->sou_priv->num_implicit == 1 &&
+ sou->active_implicit) &&
+   dev_priv->sou_priv->implicit_fb != vfb) {
DRM_ERROR("Multiple framebuffers not supported\n");
return -EINVAL;
}
@@ -439,12 +445,13 @@ static int vmw_sou_init(struct vmw_private *dev_priv, 
unsigned unit)
encoder = >base.encoder;
connector = >base.connector;

-   sou->active = false;
+   sou->active_implicit = false;

sou->base.pref_active = (unit == 0);
sou->base.pref_width = 800;
sou->base.pref_height = 600;
sou->base.pref_mode = NULL;
+   sou->base.is_implicit = true;

[PATCH 3/5] vmwgfx: Make the preferred autofit mode have a 60Hz vrefresh

[Thomas Hellstrom]

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Jakob Bornecrantz 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |   24 +++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index f9a0f98..1cebf64 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1662,6 +1662,28 @@ static struct drm_display_mode 
vmw_kms_connector_builtin[] = {
{ DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
 };

+/**
+ * vmw_guess_mode_timing - Provide fake timings for a
+ * 60Hz vrefresh mode.
+ *
+ * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
+ * members filled in.
+ */
+static void vmw_guess_mode_timing(struct drm_display_mode *mode)
+{
+   mode->hsync_start = mode->hdisplay + 50;
+   mode->hsync_end = mode->hsync_start + 50;
+   mode->htotal = mode->hsync_end + 50;
+
+   mode->vsync_start = mode->vdisplay + 50;
+   mode->vsync_end = mode->vsync_start + 50;
+   mode->vtotal = mode->vsync_end + 50;
+
+   mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
+   mode->vrefresh = drm_mode_vrefresh(mode);
+}
+
+
 int vmw_du_connector_fill_modes(struct drm_connector *connector,
uint32_t max_width, uint32_t max_height)
 {
@@ -1684,7 +1706,7 @@ int vmw_du_connector_fill_modes(struct drm_connector 
*connector,
return 0;
mode->hdisplay = du->pref_width;
mode->vdisplay = du->pref_height;
-   mode->vrefresh = drm_mode_vrefresh(mode);
+   vmw_guess_mode_timing(mode);
if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
   mode->vdisplay)) {
drm_mode_probed_add(connector, mode);
-- 
1.7.4.4

[PATCH 2/5] vmwgfx: Remove screen object active list

[Thomas Hellstrom]

It isn't used for anything. Replace with an active bool.

Also make a couple of functions return void instead of int
since their return value wasn't checked anyway.

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Jakbo Bornecrantz 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c |   52 ++
 1 files changed, 15 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index edfecc7..ea65834 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -36,8 +36,6 @@
container_of(x, struct vmw_screen_object_unit, base.connector)

 struct vmw_screen_object_display {
-   struct list_head active;
-
unsigned num_active;

struct vmw_framebuffer *fb;
@@ -53,13 +51,11 @@ struct vmw_screen_object_unit {
struct vmw_dma_buffer *buffer; /**< Backing store buffer */

bool defined;
-
-   struct list_head active;
+   bool active;
 };

 static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
 {
-   list_del_init(>active);
vmw_display_unit_cleanup(>base);
kfree(sou);
 }
@@ -74,48 +70,31 @@ static void vmw_sou_crtc_destroy(struct drm_crtc *crtc)
vmw_sou_destroy(vmw_crtc_to_sou(crtc));
 }

-static int vmw_sou_del_active(struct vmw_private *vmw_priv,
+static void vmw_sou_del_active(struct vmw_private *vmw_priv,
  struct vmw_screen_object_unit *sou)
 {
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;
-   if (list_empty(>active))
-   return 0;
-
-   /* Must init otherwise list_empty(>active) will not work. */
-   list_del_init(>active);
-   if (--(ld->num_active) == 0)
-   ld->fb = NULL;

-   return 0;
+   if (sou->active) {
+   if (--(ld->num_active) == 0)
+   ld->fb = NULL;
+   sou->active = false;
+   }
 }

-static int vmw_sou_add_active(struct vmw_private *vmw_priv,
+static void vmw_sou_add_active(struct vmw_private *vmw_priv,
  struct vmw_screen_object_unit *sou,
  struct vmw_framebuffer *vfb)
 {
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;
-   struct vmw_screen_object_unit *entry;
-   struct list_head *at;

BUG_ON(!ld->num_active && ld->fb);
-   ld->fb = vfb;

-   if (!list_empty(>active))
-   return 0;
-
-   at = >active;
-   list_for_each_entry(entry, >active, active) {
-   if (entry->base.unit > sou->base.unit)
-   break;
-
-   at = >active;
+   if (!sou->active) {
+   ld->fb = vfb;
+   sou->active = true;
+   ld->num_active++;
}
-
-   list_add(>active, at);
-
-   ld->num_active++;
-
-   return 0;
 }

 /**
@@ -303,7 +282,7 @@ static int vmw_sou_crtc_set_config(struct drm_mode_set *set)
/* sou only supports one fb active at the time */
if (dev_priv->sou_priv->fb && vfb &&
!(dev_priv->sou_priv->num_active == 1 &&
- !list_empty(>active)) &&
+ sou->active) &&
dev_priv->sou_priv->fb != vfb) {
DRM_ERROR("Multiple framebuffers not supported\n");
return -EINVAL;
@@ -460,7 +439,7 @@ static int vmw_sou_init(struct vmw_private *dev_priv, 
unsigned unit)
encoder = >base.encoder;
connector = >base.connector;

-   INIT_LIST_HEAD(>active);
+   sou->active = false;

sou->base.pref_active = (unit == 0);
sou->base.pref_width = 800;
@@ -509,7 +488,6 @@ int vmw_kms_init_screen_object_display(struct vmw_private 
*dev_priv)
if (unlikely(!dev_priv->sou_priv))
goto err_no_mem;

-   INIT_LIST_HEAD(_priv->sou_priv->active);
dev_priv->sou_priv->num_active = 0;
dev_priv->sou_priv->fb = NULL;

@@ -546,7 +524,7 @@ int vmw_kms_close_screen_object_display(struct vmw_private 
*dev_priv)

drm_vblank_cleanup(dev);

-   if (!list_empty(_priv->sou_priv->active))
+   if (dev_priv->sou_priv->num_active > 0)
DRM_ERROR("Still have active outputs when unloading driver");

kfree(dev_priv->sou_priv);
-- 
1.7.4.4

[PATCH 1/5] vmwgfx: Screen object cleanups

[Thomas Hellstrom]

Remove unused member.
No need to pin / unpin fb.

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Jakob Bornecrantz 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c |   16 ++--
 1 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 0660d3c..edfecc7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -39,7 +39,6 @@ struct vmw_screen_object_display {
struct list_head active;

unsigned num_active;
-   unsigned last_num_active;

struct vmw_framebuffer *fb;
 };
@@ -84,12 +83,8 @@ static int vmw_sou_del_active(struct vmw_private *vmw_priv,

/* Must init otherwise list_empty(>active) will not work. */
list_del_init(>active);
-   if (--(ld->num_active) == 0) {
-   BUG_ON(!ld->fb);
-   if (ld->fb->unpin)
-   ld->fb->unpin(ld->fb);
+   if (--(ld->num_active) == 0)
ld->fb = NULL;
-   }

return 0;
 }
@@ -103,13 +98,7 @@ static int vmw_sou_add_active(struct vmw_private *vmw_priv,
struct list_head *at;

BUG_ON(!ld->num_active && ld->fb);
-   if (vfb != ld->fb) {
-   if (ld->fb && ld->fb->unpin)
-   ld->fb->unpin(ld->fb);
-   if (vfb->pin)
-   vfb->pin(vfb);
-   ld->fb = vfb;
-   }
+   ld->fb = vfb;

if (!list_empty(>active))
return 0;
@@ -522,7 +511,6 @@ int vmw_kms_init_screen_object_display(struct vmw_private 
*dev_priv)

INIT_LIST_HEAD(_priv->sou_priv->active);
dev_priv->sou_priv->num_active = 0;
-   dev_priv->sou_priv->last_num_active = 0;
dev_priv->sou_priv->fb = NULL;

ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
-- 
1.7.4.4

[PATCH -fixes 0/5] vmwgfx fixes

[Thomas Hellstrom]

The patch series was intended to be preceded by this mail.
A bunch of fixes for 3.2 for vmwgfx.

/Thomas

[Intel-gfx] [PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Jesse Barnes]

On Wed, 02 Nov 2011 00:31:40 -0700
Keith Packard  wrote:

> On Tue,  1 Nov 2011 23:20:27 -0700, Keith Packard  
> wrote:
> 
> > -static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
> > +#define IDLE_ON_MASK   (PP_ON | PP_READY | PP_SEQUENCE_MASK | 
> > 0 | PP_SEQUENCE_STATE_MASK)
> > +#define IDLE_ON_VALUE  (PP_ON | PP_READY | PP_SEQUENCE_NONE | 0
> >  | PP_SEQUENCE_STATE_ON_IDLE)
> 
> A bit more testing -- looks like the MacBook Air doesn't mange to get
> PP_READY set when it's time to turn the panel on. I should look at this
> a bit more closely; there's no reason it shouldn't be set. But, nothing
> bad seems to happen if we simply ignore the PP_READY bit
> 
> +#define IDLE_ON_MASK (PP_ON | 0  | PP_SEQUENCE_MASK | 0  
>| PP_SEQUENCE_STATE_MASK)
> +#define IDLE_ON_VALUE(PP_ON | 0  | PP_SEQUENCE_NONE | 0  
>| PP_SEQUENCE_STATE_ON_IDLE)

Note that PP_READY will incorrectly depend on some other register
values, so in some configs the panel will happily power up even if
PP_READY isn't set yet...

-- 
Jesse Barnes, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Jesse Barnes]

On Tue,  1 Nov 2011 23:20:26 -0700
Keith Packard  wrote:

> PCH eDP has many of the same needs as regular PCH DP connections,
> including the DP_CTl bit settings, the TRANS_DP_CTL register.
> 
> Signed-off-by: Keith Packard 
> ---
>  drivers/gpu/drm/i915/intel_display.c |3 +-
>  drivers/gpu/drm/i915/intel_dp.c  |  112 
> --
>  2 files changed, 81 insertions(+), 34 deletions(-)
> 

Might be nice to have some function pointers to handle the different
types better.  But that could be a separate cleanup.  I'd rather have
duplicated code than fragile code...

Reviewed-by: Jesse Barnes 

But I was curious about this hunk:

@@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
drm_display_mode *mode,
continue;

intel_dp = enc_to_intel_dp(encoder);
-   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
+   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
is_pch_edp(intel_dp)) {
lane_count = intel_dp->lane_count;
break;
-   } else if (is_edp(intel_dp)) {
+   } else if (is_cpu_edp(intel_dp)) {
lane_count = dev_priv->edp.lanes;
break;
}

I guess this means we can't trust the BIOS settings for PCH eDP?

-- 
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[Intel-gfx] [PATCH 2/7] drm/i915: Remove link_status field from intel_dp structure

[Jesse Barnes]

On Tue,  1 Nov 2011 23:20:25 -0700
Keith Packard  wrote:

> No persistent data was ever stored here, so link_status is instead
> allocated on the stack as needed.
> 
> Signed-off-by: Keith Packard 
> ---

I like this cleanup.

Reviewed-by: Jesse Barnes 

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[Intel-gfx] [PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

[Keith Packard]

On Wed, 2 Nov 2011 09:02:55 -0700, Jesse Barnes  
wrote:

> Can't we just set UNLOCK_REGS at load time and have asserts sprinkled
> here and there?

I think we'd need it at resume time as well; it seemed easier to just
set it every time we touch the register.

-- 
keith.packard at intel.com
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[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

[Chris Wilson]

On Tue,  1 Nov 2011 23:20:29 -0700, Keith Packard  wrote:
> Instead of going through the sequence just once, run through the whole
> set up to 5 times to see if something can work. This isn't part of the
> DP spec, but the BIOS seems to do it, and given that link training
> failure is so bad, it seems reasonable to follow suit.
> 
> Signed-off-by: Keith Packard 
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   41 +-
>  1 files changed, 27 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6be6a04..bf20a35 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1576,8 +1576,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  
>   ret = intel_dp_aux_native_write(intel_dp,
>   DP_TRAINING_LANE0_SET,
> - intel_dp->train_set, 4);
> - if (ret != 4)
> + intel_dp->train_set,
> + intel_dp->lane_count);
> + if (ret != intel_dp->lane_count)
>   return false;

This would seem to be a separate chunk to initiate training on only the
lanes we intend to use.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[Intel-gfx] [PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

[Jesse Barnes]

On Tue,  1 Nov 2011 23:20:24 -0700
Keith Packard  wrote:

> Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to
> ensure that writes will be respected, move this to a common function
> to make the driver cleaner.
> 
> No functional changes.
> 
> Signed-off-by: Keith Packard 
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   37 +++--
>  1 files changed, 19 insertions(+), 18 deletions(-)

Can't we just set UNLOCK_REGS at load time and have asserts sprinkled
here and there?

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[PATCH] vmwgfx: Reinstate the update_layout ioctl

[Thomas Hellstrom]

Dave,

I saw the other two patches going into drm-fixes-staging, but this one 
was not included.
It's pretty important because it fixes fighting when setting monitor 
topology between gnome-settings-daemon and the vmware-user daemon.

Thanks
Thomas



On 10/25/2011 11:35 PM, Thomas Hellstrom wrote:
> We need to redefine a connector as "connected" if it matches a window
> in the host preferred GUI layout.
> Otherwise "smart" window managers would turn on Xorg outputs that we don't
> want to be on.
>
> This reinstates the update_layout and adds the following information to
> the modesetting system.
> a) Connection status<->  Equivalent to real hardware connection status
> b) Preferred mode<->  Equivalent to real hardware reading EDID
> c) Host window position<->  Equivalent to a real hardware scanout address
> dynamic register.
>
> It should be noted that there is no assumption here about what should be
> displayed and where. Only how to access the host windows.
>
> This also bumps minor to signal availability of the new IOCTL.
>
> Based on code originally written by Jakob Bornecrantz
>
> Signed-off-by: Thomas Hellstrom
> ---
>   drivers/gpu/drm/vmwgfx/vmwgfx_drv.c |6 +++
>   drivers/gpu/drm/vmwgfx/vmwgfx_drv.h |6 ++-
>   drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |   66 
> ++-
>   drivers/gpu/drm/vmwgfx/vmwgfx_kms.h |9 -
>   include/drm/vmwgfx_drm.h|   51 +--
>   5 files changed, 107 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 
> b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> index b8eb8cd..0bc20c1 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> @@ -103,6 +103,9 @@
>   #define DRM_IOCTL_VMW_PRESENT_READBACK  \
>   DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,\
>struct drm_vmw_present_readback_arg)
> +#define DRM_IOCTL_VMW_UPDATE_LAYOUT  \
> + DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,   \
> +  struct drm_vmw_update_layout_arg)
>
>   /**
>* The core DRM version of this macro doesn't account for
> @@ -165,6 +168,9 @@ static struct drm_ioctl_desc vmw_ioctls[] = {
>   VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
> vmw_present_readback_ioctl,
> DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
> + VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
> +   vmw_kms_update_layout_ioctl,
> +   DRM_MASTER | DRM_UNLOCKED),
>   };
>
>   static struct pci_device_id vmw_pci_id_list[] = {
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 
> b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
> index 30589d0..8cca91a 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
> @@ -40,9 +40,9 @@
>   #include "ttm/ttm_module.h"
>   #include "vmwgfx_fence.h"
>
> -#define VMWGFX_DRIVER_DATE "20111008"
> +#define VMWGFX_DRIVER_DATE "20111025"
>   #define VMWGFX_DRIVER_MAJOR 2
> -#define VMWGFX_DRIVER_MINOR 2
> +#define VMWGFX_DRIVER_MINOR 3
>   #define VMWGFX_DRIVER_PATCHLEVEL 0
>   #define VMWGFX_FILE_PAGE_OFFSET 0x0010
>   #define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
> @@ -633,6 +633,8 @@ int vmw_kms_readback(struct vmw_private *dev_priv,
>struct drm_vmw_fence_rep __user *user_fence_rep,
>struct drm_vmw_rect *clips,
>uint32_t num_clips);
> +int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file_priv);
>
>   /**
>* Overlay control - vmwgfx_overlay.c
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 
> b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> index 8b14dfd..f9a0f98 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> @@ -1517,6 +1517,8 @@ int vmw_du_update_layout(struct vmw_private *dev_priv, 
> unsigned num,
>   du->pref_width = rects[du->unit].w;
>   du->pref_height = rects[du->unit].h;
>   du->pref_active = true;
> + du->gui_x = rects[du->unit].x;
> + du->gui_y = rects[du->unit].y;
>   } else {
>   du->pref_width = 800;
>   du->pref_height = 600;
> @@ -1572,12 +1574,14 @@ vmw_du_connector_detect(struct drm_connector 
> *connector, bool force)
>   uint32_t num_displays;
>   struct drm_device *dev = connector->dev;
>   struct vmw_private *dev_priv = vmw_priv(dev);
> + struct vmw_display_unit *du = vmw_connector_to_du(connector);
>
>   mutex_lock(_priv->hw_mutex);
>   num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
>   mutex_unlock(_priv->hw_mutex);
>
> - return ((vmw_connector_to_du(connector)->unit<  num_displays) ?
> + return ((vmw_connector_to_du(connector)->unit<  num_displays&&
> +  du->pref_active) ?
> 

[Bug 28426] hardware cursor corruption with radeon+kms

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28426

J?rg Billeter  changed:

   What|Removed |Added

 CC||j at bitron.ch

--- Comment #7 from J?rg Billeter  2011-11-02 00:50:41 PDT ---
I have the same issue with a Radeon HD 4770 and two 1920x1200 monitors
connected via DVI. I'm currently running Linux 3.0.6 and xf86-video-ati 6.14.2,
but I've been seeing this for a long time.

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[RFC] ttm merge ttm_backend & ttm_tt

[Thomas Hellstrom]

On 11/02/2011 02:11 AM, Jerome Glisse wrote:
> Hi,
>
> So attached is patch serie (sorry for that i am away of my normal mail
> config) which ultimately merge ttm_backend&  ttm_tt it allows to get
> rid of data duplication btw the two, especialy btw ttm_tt and driver
> specific backend. So net result is less 300lines of code accross ttm
> and driver.
>
>
Jerome,
I'm positive to the idea. Since ttm_tt is supposed to consist of code 
that is shared between the backends, and backends now have callbacks for 
almost everything ttm_tt could probably go away.

I'd haven't looked at the patches yet, though. I try to do that soonish 
and get back.

/Thomas

[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #13 from Alexander Sabourenkov  
2011-11-02 00:41:39 PDT ---
Yes, thank you.

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #12 from Vadim  2011-11-01 21:56:03 PDT ---
Created attachment 53033
  --> https://bugs.freedesktop.org/attachment.cgi?id=53033
[PATCH] r600g: take into account PSIZE output for spi mapping

Does this patch help?

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[Bug 40024] Power management does not work on ATI Mobility Radeon 9700

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=40024

--- Comment #5 from Andrew Randrianasulu  2011-11-02 
04:00:35 UTC ---
Probably bad advice, but what if user  executes rovclock [1] on top of KMS ?

 [1] - http://www.thinkwiki.org/wiki/Rovclock - has some info about min. clocks
 Also, not looked into modern KMS code yet, but people on #nouveau reported
their cards need proper memtimings, are we (radeon) setting them (on combios
and atombios cards )

There was another thread on Phoronix, with dynpm discussion, basically down to
"it will work if we start to re-clock memory early, before vblank period, so at
most few lines will be corrupted" but i can't find patches on dri-devel :(

http://phoronix.com/forums/showthread.php?57084-Gallium3D-Pipe-Video-To-Be-Merged-To-Mesa-Master=218105#post218105

ahlaht 

Date 07/12/2011
-

"2. The engine clock and voltage can be changed freely without syncing to
vblank and so it should work fine with multiple monitors too. (This is very
cool.) There is no flickering provided CRTCs are kept ON while doing the
reclocking. (But there is probably some good reason why the code turns them OFF
by default.)

 3. The memory reclocking is much harder to do without flickering. Even if
synced perfectly to vblank the time runs out in the end and visible display
corruption occurs. The solution is to start the reclocking just few lines
BEFORE vblank. This way if there is any flickering it's limited to the last few
lines only.

 4. When idle and working properly dynpm doesn't use any more power than the
"low" profile, but it still responds immediately to any gpu load.

 I'm currently testing if these hacks are stable. I had some crashes when
writing them, but I think the problems should be fixed now..."

-

I'm sure i saw patches ... but where?! kernel bugzilla?

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #11 from Alexander Sabourenkov  
2011-11-01 18:41:06 PDT ---
Problem manifests itself only when gl_PointSize is set in the shader. Corrected
patch attached.

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

Alexander Sabourenkov  changed:

   What|Removed |Added

  Attachment #53030|0   |1
is obsolete||

--- Comment #10 from Alexander Sabourenkov  
2011-11-01 18:40:05 PDT ---
Created attachment 53031
  --> https://bugs.freedesktop.org/attachment.cgi?id=53031
piglit test case for the problem as a patch

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

Alexander Sabourenkov  changed:

   What|Removed |Added

  Attachment #53029|0   |1
is obsolete||

--- Comment #9 from Alexander Sabourenkov  2011-11-01 
18:03:56 PDT ---
Created attachment 53030
  --> https://bugs.freedesktop.org/attachment.cgi?id=53030
piglit test case for the problem as a patch

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #8 from Alexander Sabourenkov  2011-11-01 
17:54:54 PDT ---
Created attachment 53029
  --> https://bugs.freedesktop.org/attachment.cgi?id=53029
piglit test case for the problem

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #7 from Alexander Sabourenkov  2011-11-01 
17:53:45 PDT ---
Further reducing shaders I got to this point:

#version 120
#line 2 0

varying float idx;

void main() { 
vec2 posn2 = posz*posn;
idx = 0.625;
gl_Position = gl_ModelViewProjectionMatrix*vec4(128, 128, 0.0, 1.0);
gl_PointSize = 128;
}

#version 120
#line 2 0
varying float idx;

void main() {
gl_FragColor = vec4(idx, 0, 0, 1);
}

This is in fact very close to glsl-novertexdata from the piglit.

Which still does not work on r600g and swrast while working ok on r600c and
llvmpipe.

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[Bug 42435] Suspected loss of varyings between shaders

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=42435

--- Comment #6 from Alexander Sabourenkov  2011-11-01 
17:31:52 PDT ---
Created attachment 53028
  --> https://bugs.freedesktop.org/attachment.cgi?id=53028
xterm corruption screenshot

xterm corruption screenshot, got it right after I first run those shaders:

#version 120
#line 2 0

uniform float posz;
uniform float width;
attribute vec2 posn;

varying float idx;

void main() { 
vec2 posn2 = posz*posn;
idx = posn2.x/width;
gl_Position = gl_ModelViewProjectionMatrix*vec4(posn2.x, posn2.y, 0.0,
1.0);
gl_PointSize = posz;
}
#version 120
#line 2 0
uniform sampler2D ansi;

varying float idx;

void main() {
vec2 pc = gl_PointCoord;
gl_FragColor = texture2D(ansi, vec2(0.5, 0));
}

 - got grey screen as expected, and then reset fragment shader back to 

#version 120
#line 2 0
uniform sampler2D ansi;

varying float idx;

void main() {
vec2 pc = gl_PointCoord;
gl_FragColor = texture2D(ansi, vec2(idx, 0));
}

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[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Keith Packard]

On Tue,  1 Nov 2011 23:20:27 -0700, Keith Packard  wrote:

> -static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
> +#define IDLE_ON_MASK (PP_ON | PP_READY | PP_SEQUENCE_MASK | 0
>  | PP_SEQUENCE_STATE_MASK)
> +#define IDLE_ON_VALUE(PP_ON | PP_READY | PP_SEQUENCE_NONE | 0
>  | PP_SEQUENCE_STATE_ON_IDLE)

A bit more testing -- looks like the MacBook Air doesn't mange to get
PP_READY set when it's time to turn the panel on. I should look at this
a bit more closely; there's no reason it shouldn't be set. But, nothing
bad seems to happen if we simply ignore the PP_READY bit

+#define IDLE_ON_MASK   (PP_ON | 0  | PP_SEQUENCE_MASK | 0  
   | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE  (PP_ON | 0  | PP_SEQUENCE_NONE | 0  
   | PP_SEQUENCE_STATE_ON_IDLE)

-- 
keith.packard at intel.com
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[RFC] ttm merge ttm_backend & ttm_tt

[Konrad Rzeszutek Wilk]

On Tue, Nov 01, 2011 at 11:05:49PM -0400, Jerome Glisse wrote:
> On Tue, Nov 1, 2011 at 9:29 PM, Konrad Rzeszutek Wilk
>  wrote:
> > On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote:
> >> Hi,
> >>
> >> So attached is patch serie (sorry for that i am away of my normal mail
> >> config) which ultimately merge ttm_backend & ttm_tt it allows to get
> >> rid of data duplication btw the two, especialy btw ttm_tt and driver
> >> specific backend. So net result is less 300lines of code accross ttm
> >> and driver.
> >>
> >> Konrad given some of the upstream nouveau change, your patchserie
> >> conflict and would lead to revert some nouveau fixes. I believe the
> >> intention is to get the ttm-dma code into 3.3 (3.2 seems late but
> >> dunno). If 3.3 is the aim than i will rebase your patch on top of this
> >
> > Yup. 3.3.
> 
> So basicly the issue is that nouveau now abuse the ttm dma_address
> array to store the result of the pci map page, issue is then to either
> code your ttm page code or pci unmap when unmapping. This can be

Right. The crux is that you can't do pci unmap on coherent pages, so there
has to be some bool to figure out if your are doing ttm page code or
pci map/unmap.

> worked around, i have half a rebase patch already. But i believe if
> ttm_backend & ttm_tt are merge and with proper page callback helper,
> nouveau could be more easily adapted.

Ok.
> 
> Anyway both approach can be taken either you patch on top or bottom.

I would recommend ttm page code at the bottom as I do not think there
is going to be much change to that code - but your code is still fresh
and you might want to redo it some way or another way, fix bugs, etc - which
could mean extra merge conflict issues if the ttm page code is on top.

Thought you could also ditch some of the patches (the ones that deal
with the drivers):
0003-ttm-radeon-nouveau-Check-the-DMA-address-from-TTM-ag.patch

That should make the amount of changes to nouveau|radeon smaller..

These could also be expunged:
0004-ttm-Wrap-ttm_-put-get-_pages-and-extract-GFP_-and-ca.patch
0005-ttm-Get-rid-of-temporary-scaffolding.patch

?
> As it's somewhat different issue.

Right, git rebase/merge conflict resolution work - or hopefully no work :-)

[PATCH 7/7] drm/i915: Remove trailing white space

[Keith Packard]

Found a couple of bare tabs in intel_dp.c

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_dp.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bf20a35..7ebeb01 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1054,7 +1054,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp 
*intel_dp, bool sync)

DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
-   
+
intel_dp->want_panel_vdd = false;

if (sync) {
@@ -2402,7 +2402,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)

cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
PANEL_LIGHT_ON_DELAY_SHIFT;
-   
+
cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
PANEL_LIGHT_OFF_DELAY_SHIFT;

-- 
1.7.7

[PATCH 6/7] drm/i915: Try harder during dp pattern 1 link training

[Keith Packard]

Instead of going through the sequence just once, run through the whole
set up to 5 times to see if something can work. This isn't part of the
DP spec, but the BIOS seems to do it, and given that link training
failure is so bad, it seems reasonable to follow suit.

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_dp.c |   41 +-
 1 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6be6a04..bf20a35 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1576,8 +1576,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,

ret = intel_dp_aux_native_write(intel_dp,
DP_TRAINING_LANE0_SET,
-   intel_dp->train_set, 4);
-   if (ret != 4)
+   intel_dp->train_set,
+   intel_dp->lane_count);
+   if (ret != intel_dp->lane_count)
return false;

return true;
@@ -1593,7 +1594,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
int i;
uint8_t voltage;
bool clock_recovery = false;
-   int tries;
+   int voltage_tries, loop_tries;
u32 reg;
uint32_t DP = intel_dp->DP;

@@ -1620,7 +1621,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DP &= ~DP_LINK_TRAIN_MASK;
memset(intel_dp->train_set, 0, 4);
voltage = 0xff;
-   tries = 0;
+   voltage_tries = 0;
+   loop_tries = 0;
clock_recovery = false;
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre 
emphasis values */
@@ -1663,17 +1665,28 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (i = 0; i < intel_dp->lane_count; i++)
if ((intel_dp->train_set[i] & 
DP_TRAIN_MAX_SWING_REACHED) == 0)
break;
-   if (i == intel_dp->lane_count)
-   break;
-
-   /* Check to see if we've tried the same voltage 5 times */
-   if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 
voltage) {
-   ++tries;
-   if (tries == 5)
+   if (i == intel_dp->lane_count) {
+   ++loop_tries;
+   if (loop_tries == 5) {
+   DRM_DEBUG_KMS("too many full retries, give 
up\n");
break;
-   } else
-   tries = 0;
-   voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+   }
+   memset(intel_dp->train_set, 0, 4);
+   voltage_tries = 0;
+   continue;
+   } else {
+
+   /* Check to see if we've tried the same voltage 5 times 
*/
+   if ((intel_dp->train_set[0] & 
DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+   ++voltage_tries;
+   if (voltage_tries == 5) {
+   DRM_DEBUG_KMS("too many voltage 
retries, give up\n");
+   break;
+   }
+   } else
+   voltage_tries = 0;
+   voltage = intel_dp->train_set[0] & 
DP_TRAIN_VOLTAGE_SWING_MASK;
+   }

/* Compute new intel_dp->train_set as requested by target */
intel_get_adjust_train(intel_dp, link_status);
-- 
1.7.7

[PATCH 5/7] drm/i915: Make DP prepare/commit consistent with DP dpms

[Keith Packard]

Make sure the sequence of operations in all three functions makes
sense:

 1) The backlight must be off unless the screen is running
 2) The link must be running to turn the eDP panel on/off
 3) The CPU eDP PLL must be running until everything is off

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_dp.c |   22 +-
 1 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d6c6608..6be6a04 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1234,17 +1234,18 @@ static void intel_dp_prepare(struct drm_encoder 
*encoder)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

+   ironlake_edp_backlight_off(intel_dp);
+   ironlake_edp_panel_off(intel_dp);
+
/* Wake up the sink first */
ironlake_edp_panel_vdd_on(intel_dp);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   intel_dp_link_down(intel_dp);
ironlake_edp_panel_vdd_off(intel_dp, false);

/* Make sure the panel is off before trying to
 * change the mode
 */
-   ironlake_edp_backlight_off(intel_dp);
-   intel_dp_link_down(intel_dp);
-   ironlake_edp_panel_off(intel_dp);
 }

 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1276,16 +1277,20 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
uint32_t dp_reg = I915_READ(intel_dp->output_reg);

if (mode != DRM_MODE_DPMS_ON) {
+   ironlake_edp_backlight_off(intel_dp);
+   ironlake_edp_panel_off(intel_dp);
+
ironlake_edp_panel_vdd_on(intel_dp);
-   if (is_edp(intel_dp))
-   ironlake_edp_backlight_off(intel_dp);
intel_dp_sink_dpms(intel_dp, mode);
intel_dp_link_down(intel_dp);
-   ironlake_edp_panel_off(intel_dp);
-   if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
-   ironlake_edp_pll_off(encoder);
ironlake_edp_panel_vdd_off(intel_dp, false);
+
+   if (is_cpu_edp(intel_dp))
+   ironlake_edp_pll_off(encoder);
} else {
+   if (is_cpu_edp(intel_dp))
+   ironlake_edp_pll_on(encoder);
+
ironlake_edp_panel_vdd_on(intel_dp);
intel_dp_sink_dpms(intel_dp, mode);
if (!(dp_reg & DP_PORT_EN)) {
@@ -1293,7 +1298,6 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
ironlake_edp_panel_on(intel_dp);
ironlake_edp_panel_vdd_off(intel_dp, true);
intel_dp_complete_link_train(intel_dp);
-   ironlake_edp_backlight_on(intel_dp);
} else
ironlake_edp_panel_vdd_off(intel_dp, false);
ironlake_edp_backlight_on(intel_dp);
-- 
1.7.7

[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Keith Packard]

The panel power sequencing hardware tracks the stages of panel power
sequencing and signals when the panel is completely on or off. Instead
of blindly assuming the panel timings will work, poll the panel power
status register until it shows the correct values.

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/i915_reg.h |   17 -
 drivers/gpu/drm/i915/intel_dp.c |  138 +--
 2 files changed, 87 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416..275d149 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1553,12 +1553,21 @@
  */
 #define   PP_READY (1 << 30)
 #define   PP_SEQUENCE_NONE (0 << 28)
-#define   PP_SEQUENCE_ON   (1 << 28)
-#define   PP_SEQUENCE_OFF  (2 << 28)
-#define   PP_SEQUENCE_MASK 0x3000
+#define   PP_SEQUENCE_POWER_UP (1 << 28)
+#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
+#define   PP_SEQUENCE_MASK (3 << 28)
+#define   PP_SEQUENCE_SHIFT28
 #define   PP_CYCLE_DELAY_ACTIVE(1 << 27)
-#define   PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
 #define   PP_SEQUENCE_STATE_MASK 0x000f
+#define   PP_SEQUENCE_STATE_OFF_IDLE   (0x0 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_1   (0x1 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_2   (0x2 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_3   (0x3 << 0)
+#define   PP_SEQUENCE_STATE_ON_IDLE(0x8 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_0(0x9 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_2(0xa << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
+#define   PP_SEQUENCE_STATE_RESET  (0xf << 0)
 #define PP_CONTROL 0x61204
 #define   POWER_TARGET_ON  (1 << 0)
 #define PP_ON_DELAYS   0x61208
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 185fae6..d6c6608 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -66,7 +66,6 @@ struct intel_dp {
struct drm_display_mode *panel_fixed_mode;  /* for eDP */
struct delayed_work panel_vdd_work;
bool want_panel_vdd;
-   unsigned long panel_off_jiffies;
 };

 /**
@@ -915,32 +914,56 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
}
 }

-static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+#define IDLE_ON_MASK   (PP_ON | PP_READY | PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE  (PP_ON | PP_READY | PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_ON_IDLE)
+
+#define IDLE_OFF_MASK  (PP_ON | 0| PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_OFF_VALUE (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+#define IDLE_CYCLE_MASK(PP_ON | 0| PP_SEQUENCE_MASK | 
PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE   (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
+  u32 mask,
+  u32 value)
 {
-   unsigned long   off_time;
-   unsigned long   delay;
+   struct drm_device *dev = intel_dp->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;

-   DRM_DEBUG_KMS("Wait for panel power off time\n");
+   DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
+ mask, value,
+ I915_READ(PCH_PP_STATUS),
+ I915_READ(PCH_PP_CONTROL));

-   if (ironlake_edp_have_panel_power(intel_dp) ||
-   ironlake_edp_have_panel_vdd(intel_dp))
+   if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value,
+ 5000,
+ 10))
{
-   DRM_DEBUG_KMS("Panel still on, no delay needed\n");
-   return;
+   DRM_ERROR("Panel status timeout: status %08x control %08x\n",
+ I915_READ(PCH_PP_STATUS),
+ I915_READ(PCH_PP_CONTROL));
}
+}

-   off_time = intel_dp->panel_off_jiffies + 
msecs_to_jiffies(intel_dp->panel_power_down_delay);
-   if (time_after(jiffies, off_time)) {
-   DRM_DEBUG_KMS("Time already passed");
-   return;
-   }
-   delay = jiffies_to_msecs(off_time - jiffies);
-   if (delay > intel_dp->panel_power_down_delay)
-   delay = intel_dp->panel_power_down_delay;
-   DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
-   msleep(delay);
+static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
+{
+   DRM_DEBUG_KMS("Wait for panel power on\n");
+   ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 }

+static void ironlake_wait_panel_off(struct intel_dp *intel_dp)

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

PCH eDP has many of the same needs as regular PCH DP connections,
including the DP_CTl bit settings, the TRANS_DP_CTL register.

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_display.c |3 +-
 drivers/gpu/drm/i915/intel_dp.c  |  112 --
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9fa342e..53eb29e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2933,7 +2933,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)

/* For PCH DP, enable TRANS_DP_CTL */
if (HAS_PCH_CPT(dev) &&
-   intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+   (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c0c482..185fae6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
drm_display_mode *mode,
continue;

intel_dp = enc_to_intel_dp(encoder);
-   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
+   if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 
is_pch_edp(intel_dp)) {
lane_count = intel_dp->lane_count;
break;
-   } else if (is_edp(intel_dp)) {
+   } else if (is_cpu_edp(intel_dp)) {
lane_count = dev_priv->edp.lanes;
break;
}
@@ -808,6 +808,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
  struct drm_display_mode *adjusted_mode)
 {
struct drm_device *dev = encoder->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_crtc *crtc = intel_dp->base.base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -820,18 +821,31 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
ironlake_edp_pll_off(encoder);
}

-   intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-   intel_dp->DP |= intel_dp->color_range;
+   /*
+* There are three kinds of DP registers:
+*
+*  IBX PCH
+*  CPU
+*  CPT PCH
+*
+* IBX PCH and CPU are the same for almost everything,
+* except that the CPU DP PLL is configured in this
+* register
+*
+* CPT PCH is quite different, having many bits moved
+* to the TRANS_DP_CTL register instead. That
+* configuration happens (oddly) in ironlake_pch_enable
+*/

-   if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
-   intel_dp->DP |= DP_SYNC_HS_HIGH;
-   if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
-   intel_dp->DP |= DP_SYNC_VS_HIGH;
+   /* Preserve the BIOS-computed detected bit. This is
+* supposed to be read-only.
+*/
+   intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+   intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

-   if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
-   intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
-   else
-   intel_dp->DP |= DP_LINK_TRAIN_OFF;
+   /* Handle DP bits in common between all three register formats */
+
+   intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

switch (intel_dp->lane_count) {
case 1:
@@ -850,32 +864,54 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_write_eld(encoder, adjusted_mode);
}
-
memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
intel_dp->link_configuration[0] = intel_dp->link_bw;
intel_dp->link_configuration[1] = intel_dp->lane_count;
intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
-
/*
 * Check for DPCD version > 1.1 and enhanced framing support
 */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
intel_dp->link_configuration[1] |= 
DP_LANE_COUNT_ENHANCED_FRAME_EN;
-   intel_dp->DP |= DP_ENHANCED_FRAMING;
}

-   /* CPT DP's pipe select is decided in TRANS_DP_CTL */
-   if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
-   intel_dp->DP |= DP_PIPEB_SELECT;
+   /* Split out the IBX/CPU vs CPT 

[PATCH 2/7] drm/i915: Remove link_status field from intel_dp structure

[Keith Packard]

No persistent data was ever stored here, so link_status is instead
allocated on the stack as needed.

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_dp.c |   65 +-
 1 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index efe5f9e..2c0c482 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -58,7 +58,6 @@ struct intel_dp {
struct i2c_algo_dp_aux_data algo;
bool is_pch_edp;
uint8_t train_set[4];
-   uint8_t link_status[DP_LINK_STATUS_SIZE];
int panel_power_up_delay;
int panel_power_down_delay;
int panel_power_cycle_delay;
@@ -1285,11 +1284,11 @@ intel_dp_aux_native_read_retry(struct intel_dp 
*intel_dp, uint16_t address,
  * link status information
  */
 static bool
-intel_dp_get_link_status(struct intel_dp *intel_dp)
+intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t 
link_status[DP_LINK_STATUS_SIZE])
 {
return intel_dp_aux_native_read_retry(intel_dp,
  DP_LANE0_1_STATUS,
- intel_dp->link_status,
+ link_status,
  DP_LINK_STATUS_SIZE);
 }

@@ -1301,27 +1300,25 @@ intel_dp_link_status(uint8_t 
link_status[DP_LINK_STATUS_SIZE],
 }

 static uint8_t
-intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+intel_get_adjust_request_voltage(uint8_t adjust_request[2],
 int lane)
 {
-   int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
int s = ((lane & 1) ?
 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
-   uint8_t l = intel_dp_link_status(link_status, i);
+   uint8_t l = adjust_request[lane>>1];

return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 }

 static uint8_t
-intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
  int lane)
 {
-   int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
int s = ((lane & 1) ?
 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
-   uint8_t l = intel_dp_link_status(link_status, i);
+   uint8_t l = adjust_request[lane>>1];

return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 }
@@ -1362,15 +1359,18 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 }

 static void
-intel_get_adjust_train(struct intel_dp *intel_dp)
+intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t 
link_status[DP_LINK_STATUS_SIZE])
 {
+   struct drm_device *dev = intel_dp->base.base.dev;
uint8_t v = 0;
uint8_t p = 0;
int lane;
+   uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - 
DP_LANE0_1_STATUS);
+   int voltage_max;

for (lane = 0; lane < intel_dp->lane_count; lane++) {
-   uint8_t this_v = 
intel_get_adjust_request_voltage(intel_dp->link_status, lane);
-   uint8_t this_p = 
intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
+   uint8_t this_v = 
intel_get_adjust_request_voltage(adjust_request, lane);
+   uint8_t this_p = 
intel_get_adjust_request_pre_emphasis(adjust_request, lane);

if (this_v > v)
v = this_v;
@@ -1389,7 +1389,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp)
 }

 static uint32_t
-intel_dp_signal_levels(uint8_t train_set, int lane_count)
+intel_dp_signal_levels(uint8_t train_set)
 {
uint32_tsignal_levels = 0;

@@ -1458,9 +1458,8 @@ static uint8_t
 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  int lane)
 {
-   int i = DP_LANE0_1_STATUS + (lane >> 1);
int s = (lane & 1) * 4;
-   uint8_t l = intel_dp_link_status(link_status, i);
+   uint8_t l = link_status[lane>>1];

return (l >> s) & 0xf;
 }
@@ -1485,18 +1484,18 @@ intel_clock_recovery_ok(uint8_t 
link_status[DP_LINK_STATUS_SIZE], int lane_count
 DP_LANE_CHANNEL_EQ_DONE|\
 DP_LANE_SYMBOL_LOCKED)
 static bool
-intel_channel_eq_ok(struct intel_dp *intel_dp)
+intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t 
link_status[DP_LINK_STATUS_SIZE])
 {
uint8_t lane_align;
uint8_t lane_status;
int lane;

-   lane_align = intel_dp_link_status(intel_dp->link_status,
+   lane_align = intel_dp_link_status(link_status,
  DP_LANE_ALIGN_STATUS_UPDATED);
if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
return false;
for (lane = 0; 

[PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

[Keith Packard]

Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to
ensure that writes will be respected, move this to a common function
to make the driver cleaner.

No functional changes.

Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_dp.c |   37 +++--
 1 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7259034..efe5f9e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -906,6 +906,19 @@ static void ironlake_wait_panel_off(struct intel_dp 
*intel_dp)
msleep(delay);
 }

+/* Read the current pp_control value, unlocking the register if it
+ * is locked
+ */
+
+static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+{
+   u32 control = I915_READ(PCH_PP_CONTROL);
+
+   control &= ~PANEL_UNLOCK_MASK;
+   control |= PANEL_UNLOCK_REGS;
+   return control;
+}
+
 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 {
struct drm_device *dev = intel_dp->base.base.dev;
@@ -926,9 +939,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp 
*intel_dp)
}

ironlake_wait_panel_off(intel_dp);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp |= EDP_FORCE_VDD;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -951,9 +962,7 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp 
*intel_dp)
u32 pp;

if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) 
{
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp &= ~EDP_FORCE_VDD;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -1012,9 +1021,7 @@ static void ironlake_edp_panel_on(struct intel_dp 
*intel_dp)
return;

ironlake_wait_panel_off(intel_dp);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);

if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
@@ -1049,9 +1056,7 @@ static void ironlake_edp_panel_off(struct drm_encoder 
*encoder)

if (!is_edp(intel_dp))
return;
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);

if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
@@ -1098,9 +1103,7 @@ static void ironlake_edp_backlight_on(struct intel_dp 
*intel_dp)
 * allowing it to appear.
 */
msleep(intel_dp->backlight_on_delay);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp |= EDP_BLC_ENABLE;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -1116,9 +1119,7 @@ static void ironlake_edp_backlight_off(struct intel_dp 
*intel_dp)
return;

DRM_DEBUG_KMS("\n");
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp &= ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp &= ~EDP_BLC_ENABLE;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
-- 
1.7.7

[PATCH 0/7] drm/i915: Fix PCH eDP support for SNB

[Keith Packard]

Here's a patch sequence which makes my PCH-connected eDP panel
work. The main bug was a pile of places where the driver was
incorrectly treating a PCH connected eDP panel like a CPU connected
eDP panel, setting incorrect bits in the DP_CTL register and failing
to configure the TRANS_DP_CTL register entirely.

Beyond that, this eDP panel appears very sensitive to panel power
sequencing, and I found a bunch of minor errors there. I switched from
using blind timings to polling the panel power sequencing status
register to make sure we waited until that thought things were done,
and so that any panel power sequencing errors would show up in the
kernel log.

Finally, I noticed that the BIOS tried harder to get the link trained,
by simply starting over when it failed and trying the whole sequence
up to 5 times. This is not part of the DP spec, but given how bad
failing to train a panel is, it seems like it might be a good idea.

The three most interesting patches are the one which handles PCH eDP
more like PCH DP, the one which switches to using the panel power
sequencing hardware for all delays and finally the patch which tries
to do the panel power-up/down in the same order for both
dp_prepare/commit and dp_dpms.

All of these patches are on my pch-edp-fixes branch at

git://people.freedesktop.org/~keithp/linux

If you've got a PCH connected eDP display, I'd love to know if this
makes it work. If you've got a CPU connected eDP display or PCH
connected DP, please see if this causes any problems.

(I've got several machines failing to resume with this patch, but I've
checked and it's not the fault of anything in the i915 directory;
applying this sequence to v3.1 makes suspend/resume work fine).

[RFC] ttm merge ttm_backend & ttm_tt

[Jerome Glisse]

On Tue, Nov 1, 2011 at 9:29 PM, Konrad Rzeszutek Wilk
 wrote:
> On Tue, Nov 01, 2011 at 09:11:37PM -0400, Jerome Glisse wrote:
>> Hi,
>>
>> So attached is patch serie (sorry for that i am away of my normal mail
>> config) which ultimately merge ttm_backend & ttm_tt it allows to get
>> rid of data duplication btw the two, especialy btw ttm_tt and driver
>> specific backend. So net result is less 300lines of code accross ttm
>> and driver.
>>
>> Konrad given some of the upstream nouveau change, your patchserie
>> conflict and would lead to revert some nouveau fixes. I believe the
>> intention is to get the ttm-dma code into 3.3 (3.2 seems late but
>> dunno). If 3.3 is the aim than i will rebase your patch on top of this
>
> Yup. 3.3.

So basicly the issue is that nouveau now abuse the ttm dma_address
array to store the result of the pci map page, issue is then to either
code your ttm page code or pci unmap when unmapping. This can be
worked around, i have half a rebase patch already. But i believe if
ttm_backend & ttm_tt are merge and with proper page callback helper,
nouveau could be more easily adapted.

Anyway both approach can be taken either you patch on top or bottom.
As it's somewhat different issue.

Cheers,
Jerome

[PATCH 0/7] drm/i915: Fix PCH eDP support for SNB

[Keith Packard]

Here's a patch sequence which makes my PCH-connected eDP panel
work. The main bug was a pile of places where the driver was
incorrectly treating a PCH connected eDP panel like a CPU connected
eDP panel, setting incorrect bits in the DP_CTL register and failing
to configure the TRANS_DP_CTL register entirely.

Beyond that, this eDP panel appears very sensitive to panel power
sequencing, and I found a bunch of minor errors there. I switched from
using blind timings to polling the panel power sequencing status
register to make sure we waited until that thought things were done,
and so that any panel power sequencing errors would show up in the
kernel log.

Finally, I noticed that the BIOS tried harder to get the link trained,
by simply starting over when it failed and trying the whole sequence
up to 5 times. This is not part of the DP spec, but given how bad
failing to train a panel is, it seems like it might be a good idea.

The three most interesting patches are the one which handles PCH eDP
more like PCH DP, the one which switches to using the panel power
sequencing hardware for all delays and finally the patch which tries
to do the panel power-up/down in the same order for both
dp_prepare/commit and dp_dpms.

All of these patches are on my pch-edp-fixes branch at

git://people.freedesktop.org/~keithp/linux

If you've got a PCH connected eDP display, I'd love to know if this
makes it work. If you've got a CPU connected eDP display or PCH
connected DP, please see if this causes any problems.

(I've got several machines failing to resume with this patch, but I've
checked and it's not the fault of anything in the i915 directory;
applying this sequence to v3.1 makes suspend/resume work fine).

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[PATCH 1/7] drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control

[Keith Packard]

Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to
ensure that writes will be respected, move this to a common function
to make the driver cleaner.

No functional changes.

Signed-off-by: Keith Packard kei...@keithp.com
---
 drivers/gpu/drm/i915/intel_dp.c |   37 +++--
 1 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7259034..efe5f9e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -906,6 +906,19 @@ static void ironlake_wait_panel_off(struct intel_dp 
*intel_dp)
msleep(delay);
 }
 
+/* Read the current pp_control value, unlocking the register if it
+ * is locked
+ */
+
+static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+{
+   u32 control = I915_READ(PCH_PP_CONTROL);
+
+   control = ~PANEL_UNLOCK_MASK;
+   control |= PANEL_UNLOCK_REGS;
+   return control;
+}
+
 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 {
struct drm_device *dev = intel_dp-base.base.dev;
@@ -926,9 +939,7 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp 
*intel_dp)
}
 
ironlake_wait_panel_off(intel_dp);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp |= EDP_FORCE_VDD;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -951,9 +962,7 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp 
*intel_dp)
u32 pp;
 
if (!intel_dp-want_panel_vdd  ironlake_edp_have_panel_vdd(intel_dp)) 
{
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp = ~EDP_FORCE_VDD;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -1012,9 +1021,7 @@ static void ironlake_edp_panel_on(struct intel_dp 
*intel_dp)
return;
 
ironlake_wait_panel_off(intel_dp);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
 
if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
@@ -1049,9 +1056,7 @@ static void ironlake_edp_panel_off(struct drm_encoder 
*encoder)
 
if (!is_edp(intel_dp))
return;
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
 
if (IS_GEN5(dev)) {
/* ILK workaround: disable reset around power sequence */
@@ -1098,9 +1103,7 @@ static void ironlake_edp_backlight_on(struct intel_dp 
*intel_dp)
 * allowing it to appear.
 */
msleep(intel_dp-backlight_on_delay);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp |= EDP_BLC_ENABLE;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
@@ -1116,9 +1119,7 @@ static void ironlake_edp_backlight_off(struct intel_dp 
*intel_dp)
return;
 
DRM_DEBUG_KMS(\n);
-   pp = I915_READ(PCH_PP_CONTROL);
-   pp = ~PANEL_UNLOCK_MASK;
-   pp |= PANEL_UNLOCK_REGS;
+   pp = ironlake_get_pp_control(dev_priv);
pp = ~EDP_BLC_ENABLE;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
-- 
1.7.7

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[PATCH 5/7] drm/i915: Make DP prepare/commit consistent with DP dpms

[Keith Packard]

Make sure the sequence of operations in all three functions makes
sense:

 1) The backlight must be off unless the screen is running
 2) The link must be running to turn the eDP panel on/off
 3) The CPU eDP PLL must be running until everything is off

Signed-off-by: Keith Packard kei...@keithp.com
---
 drivers/gpu/drm/i915/intel_dp.c |   22 +-
 1 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d6c6608..6be6a04 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1234,17 +1234,18 @@ static void intel_dp_prepare(struct drm_encoder 
*encoder)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
+   ironlake_edp_backlight_off(intel_dp);
+   ironlake_edp_panel_off(intel_dp);
+
/* Wake up the sink first */
ironlake_edp_panel_vdd_on(intel_dp);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+   intel_dp_link_down(intel_dp);
ironlake_edp_panel_vdd_off(intel_dp, false);
 
/* Make sure the panel is off before trying to
 * change the mode
 */
-   ironlake_edp_backlight_off(intel_dp);
-   intel_dp_link_down(intel_dp);
-   ironlake_edp_panel_off(intel_dp);
 }
 
 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1276,16 +1277,20 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
uint32_t dp_reg = I915_READ(intel_dp-output_reg);
 
if (mode != DRM_MODE_DPMS_ON) {
+   ironlake_edp_backlight_off(intel_dp);
+   ironlake_edp_panel_off(intel_dp);
+
ironlake_edp_panel_vdd_on(intel_dp);
-   if (is_edp(intel_dp))
-   ironlake_edp_backlight_off(intel_dp);
intel_dp_sink_dpms(intel_dp, mode);
intel_dp_link_down(intel_dp);
-   ironlake_edp_panel_off(intel_dp);
-   if (is_edp(intel_dp)  !is_pch_edp(intel_dp))
-   ironlake_edp_pll_off(encoder);
ironlake_edp_panel_vdd_off(intel_dp, false);
+
+   if (is_cpu_edp(intel_dp))
+   ironlake_edp_pll_off(encoder);
} else {
+   if (is_cpu_edp(intel_dp))
+   ironlake_edp_pll_on(encoder);
+
ironlake_edp_panel_vdd_on(intel_dp);
intel_dp_sink_dpms(intel_dp, mode);
if (!(dp_reg  DP_PORT_EN)) {
@@ -1293,7 +1298,6 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
ironlake_edp_panel_on(intel_dp);
ironlake_edp_panel_vdd_off(intel_dp, true);
intel_dp_complete_link_train(intel_dp);
-   ironlake_edp_backlight_on(intel_dp);
} else
ironlake_edp_panel_vdd_off(intel_dp, false);
ironlake_edp_backlight_on(intel_dp);
-- 
1.7.7

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[PATCH 4/7] drm/i915: Let panel power sequencing hardware do its job

[Keith Packard]

The panel power sequencing hardware tracks the stages of panel power
sequencing and signals when the panel is completely on or off. Instead
of blindly assuming the panel timings will work, poll the panel power
status register until it shows the correct values.

Signed-off-by: Keith Packard kei...@keithp.com
---
 drivers/gpu/drm/i915/i915_reg.h |   17 -
 drivers/gpu/drm/i915/intel_dp.c |  138 +--
 2 files changed, 87 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416..275d149 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1553,12 +1553,21 @@
  */
 #define   PP_READY (1  30)
 #define   PP_SEQUENCE_NONE (0  28)
-#define   PP_SEQUENCE_ON   (1  28)
-#define   PP_SEQUENCE_OFF  (2  28)
-#define   PP_SEQUENCE_MASK 0x3000
+#define   PP_SEQUENCE_POWER_UP (1  28)
+#define   PP_SEQUENCE_POWER_DOWN (2  28)
+#define   PP_SEQUENCE_MASK (3  28)
+#define   PP_SEQUENCE_SHIFT28
 #define   PP_CYCLE_DELAY_ACTIVE(1  27)
-#define   PP_SEQUENCE_STATE_ON_IDLE (1  3)
 #define   PP_SEQUENCE_STATE_MASK 0x000f
+#define   PP_SEQUENCE_STATE_OFF_IDLE   (0x0  0)
+#define   PP_SEQUENCE_STATE_OFF_S0_1   (0x1  0)
+#define   PP_SEQUENCE_STATE_OFF_S0_2   (0x2  0)
+#define   PP_SEQUENCE_STATE_OFF_S0_3   (0x3  0)
+#define   PP_SEQUENCE_STATE_ON_IDLE(0x8  0)
+#define   PP_SEQUENCE_STATE_ON_S1_0(0x9  0)
+#define   PP_SEQUENCE_STATE_ON_S1_2(0xa  0)
+#define   PP_SEQUENCE_STATE_ON_S1_3(0xb  0)
+#define   PP_SEQUENCE_STATE_RESET  (0xf  0)
 #define PP_CONTROL 0x61204
 #define   POWER_TARGET_ON  (1  0)
 #define PP_ON_DELAYS   0x61208
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 185fae6..d6c6608 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -66,7 +66,6 @@ struct intel_dp {
struct drm_display_mode *panel_fixed_mode;  /* for eDP */
struct delayed_work panel_vdd_work;
bool want_panel_vdd;
-   unsigned long panel_off_jiffies;
 };
 
 /**
@@ -915,32 +914,56 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
}
 }
 
-static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+#define IDLE_ON_MASK   (PP_ON | PP_READY | PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_ON_VALUE  (PP_ON | PP_READY | PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_ON_IDLE)
+
+#define IDLE_OFF_MASK  (PP_ON | 0| PP_SEQUENCE_MASK | 0
 | PP_SEQUENCE_STATE_MASK)
+#define IDLE_OFF_VALUE (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+#define IDLE_CYCLE_MASK(PP_ON | 0| PP_SEQUENCE_MASK | 
PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
+#define IDLE_CYCLE_VALUE   (0 | 0| PP_SEQUENCE_NONE | 0
 | PP_SEQUENCE_STATE_OFF_IDLE)
+
+static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
+  u32 mask,
+  u32 value)
 {
-   unsigned long   off_time;
-   unsigned long   delay;
+   struct drm_device *dev = intel_dp-base.base.dev;
+   struct drm_i915_private *dev_priv = dev-dev_private;
 
-   DRM_DEBUG_KMS(Wait for panel power off time\n);
+   DRM_DEBUG_KMS(mask %08x value %08x status %08x control %08x\n,
+ mask, value,
+ I915_READ(PCH_PP_STATUS),
+ I915_READ(PCH_PP_CONTROL));
 
-   if (ironlake_edp_have_panel_power(intel_dp) ||
-   ironlake_edp_have_panel_vdd(intel_dp))
+   if (_wait_for((I915_READ(PCH_PP_STATUS)  mask) == value,
+ 5000,
+ 10))
{
-   DRM_DEBUG_KMS(Panel still on, no delay needed\n);
-   return;
+   DRM_ERROR(Panel status timeout: status %08x control %08x\n,
+ I915_READ(PCH_PP_STATUS),
+ I915_READ(PCH_PP_CONTROL));
}
+}
 
-   off_time = intel_dp-panel_off_jiffies + 
msecs_to_jiffies(intel_dp-panel_power_down_delay);
-   if (time_after(jiffies, off_time)) {
-   DRM_DEBUG_KMS(Time already passed);
-   return;
-   }
-   delay = jiffies_to_msecs(off_time - jiffies);
-   if (delay  intel_dp-panel_power_down_delay)
-   delay = intel_dp-panel_power_down_delay;
-   DRM_DEBUG_KMS(Waiting an additional %ld ms\n, delay);
-   msleep(delay);
+static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
+{
+   DRM_DEBUG_KMS(Wait for panel power on\n);
+   ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 }
 
+static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
+{
+   DRM_DEBUG_KMS(Wait for 

[PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

[Keith Packard]

PCH eDP has many of the same needs as regular PCH DP connections,
including the DP_CTl bit settings, the TRANS_DP_CTL register.

Signed-off-by: Keith Packard kei...@keithp.com
---
 drivers/gpu/drm/i915/intel_display.c |3 +-
 drivers/gpu/drm/i915/intel_dp.c  |  112 --
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9fa342e..53eb29e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2933,7 +2933,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 
/* For PCH DP, enable TRANS_DP_CTL */
if (HAS_PCH_CPT(dev) 
-   intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
+   (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
u32 bpc = (I915_READ(PIPECONF(pipe))  PIPE_BPC_MASK)  5;
reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c0c482..185fae6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct 
drm_display_mode *mode,
continue;
 
intel_dp = enc_to_intel_dp(encoder);
-   if (intel_dp-base.type == INTEL_OUTPUT_DISPLAYPORT) {
+   if (intel_dp-base.type == INTEL_OUTPUT_DISPLAYPORT || 
is_pch_edp(intel_dp)) {
lane_count = intel_dp-lane_count;
break;
-   } else if (is_edp(intel_dp)) {
+   } else if (is_cpu_edp(intel_dp)) {
lane_count = dev_priv-edp.lanes;
break;
}
@@ -808,6 +808,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
  struct drm_display_mode *adjusted_mode)
 {
struct drm_device *dev = encoder-dev;
+   struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_crtc *crtc = intel_dp-base.base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -820,18 +821,31 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
ironlake_edp_pll_off(encoder);
}
 
-   intel_dp-DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-   intel_dp-DP |= intel_dp-color_range;
+   /*
+* There are three kinds of DP registers:
+*
+*  IBX PCH
+*  CPU
+*  CPT PCH
+*
+* IBX PCH and CPU are the same for almost everything,
+* except that the CPU DP PLL is configured in this
+* register
+*
+* CPT PCH is quite different, having many bits moved
+* to the TRANS_DP_CTL register instead. That
+* configuration happens (oddly) in ironlake_pch_enable
+*/
 
-   if (adjusted_mode-flags  DRM_MODE_FLAG_PHSYNC)
-   intel_dp-DP |= DP_SYNC_HS_HIGH;
-   if (adjusted_mode-flags  DRM_MODE_FLAG_PVSYNC)
-   intel_dp-DP |= DP_SYNC_VS_HIGH;
+   /* Preserve the BIOS-computed detected bit. This is
+* supposed to be read-only.
+*/
+   intel_dp-DP = I915_READ(intel_dp-output_reg)  DP_DETECTED;
+   intel_dp-DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 
-   if (HAS_PCH_CPT(dev)  !is_cpu_edp(intel_dp))
-   intel_dp-DP |= DP_LINK_TRAIN_OFF_CPT;
-   else
-   intel_dp-DP |= DP_LINK_TRAIN_OFF;
+   /* Handle DP bits in common between all three register formats */
+
+   intel_dp-DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 
switch (intel_dp-lane_count) {
case 1:
@@ -850,32 +864,54 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct 
drm_display_mode *mode,
intel_dp-DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_write_eld(encoder, adjusted_mode);
}
-
memset(intel_dp-link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
intel_dp-link_configuration[0] = intel_dp-link_bw;
intel_dp-link_configuration[1] = intel_dp-lane_count;
intel_dp-link_configuration[8] = DP_SET_ANSI_8B10B;
-
/*
 * Check for DPCD version  1.1 and enhanced framing support
 */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11 
(intel_dp-dpcd[DP_MAX_LANE_COUNT]  DP_ENHANCED_FRAME_CAP)) {
intel_dp-link_configuration[1] |= 
DP_LANE_COUNT_ENHANCED_FRAME_EN;
-   intel_dp-DP |= DP_ENHANCED_FRAMING;
}
 
-   /* CPT DP's pipe select is decided in TRANS_DP_CTL */
-   if (intel_crtc-pipe == 1  !HAS_PCH_CPT(dev))
-   intel_dp-DP |= DP_PIPEB_SELECT;
+   /* Split out the IBX/CPU vs CPT settings */
 
-   if