[PATCH 00/83] AMD HSA kernel driver

2014-07-10 Thread Gabbay, Oded
On Thu, 2014-07-10 at 18:24 -0400, Jerome Glisse wrote:
> On Fri, Jul 11, 2014 at 12:45:27AM +0300, Oded Gabbay wrote:
> >  This patch set implements a Heterogeneous System Architecture 
> > (HSA) driver
> >  for radeon-family GPUs.
>  
> This is just quick comments on few things. Given size of this, people
> will need to have time to review things.
>  
> >  HSA allows different processor types (CPUs, DSPs, GPUs, etc..) to 
> > share
> >  system resources more effectively via HW features including 
> > shared pageable
> >  memory, userspace-accessible work queues, and platform-level 
> > atomics. In
> >  addition to the memory protection mechanisms in GPUVM and 
> > IOMMUv2, the Sea
> >  Islands family of GPUs also performs HW-level validation of 
> > commands passed
> >  in through the queues (aka rings).
> >  The code in this patch set is intended to serve both as a sample 
> > driver for
> >  other HSA-compatible hardware devices and as a production driver 
> > for
> >  radeon-family processors. The code is architected to support 
> > multiple CPUs
> >  each with connected GPUs, although the current implementation 
> > focuses on a
> >  single Kaveri/Berlin APU, and works alongside the existing radeon 
> > kernel
> >  graphics driver (kgd).
> >  AMD GPUs designed for use with HSA (Sea Islands and up) share 
> > some hardware
> >  functionality between HSA compute and regular gfx/compute (memory,
> >  interrupts, registers), while other functionality has been added
> >  specifically for HSA compute  (hw scheduler for virtualized 
> > compute rings).
> >  All shared hardware is owned by the radeon graphics driver, and 
> > an interface
> >  between kfd and kgd allows the kfd to make use of those shared 
> > resources,
> >  while HSA-specific functionality is managed directly by kfd by 
> > submitting
> >  packets into an HSA-specific command queue (the "HIQ").
> >  During kfd module initialization a char device node (/dev/kfd) is 
> > created
> >  (surviving until module exit), with ioctls for queue creation & 
> > management,
> >  and data structures are initialized for managing HSA device 
> > topology.
> >  The rest of the initialization is driven by calls from the radeon 
> > kgd at
> >  the following points :
> >  - radeon_init (kfd_init)
> >  - radeon_exit (kfd_fini)
> >  - radeon_driver_load_kms (kfd_device_probe, kfd_device_init)
> >  - radeon_driver_unload_kms (kfd_device_fini)
> >  During the probe and init processing per-device data structures 
> > are
> >  established which connect to the associated graphics kernel 
> > driver. This
> >  information is exposed to userspace via sysfs, along with a 
> > version number
> >  allowing userspace to determine if a topology change has occurred 
> > while it
> >  was reading from sysfs.
> >  The interface between kfd and kgd also allows the kfd to request 
> > buffer
> >  management services from kgd, and allows kgd to route interrupt 
> > requests to
> >  kfd code since the interrupt block is shared between regular
> >  graphics/compute and HSA compute subsystems in the GPU.
> >  The kfd code works with an open source usermode library 
> > ("libhsakmt") which
> >  is in the final stages of IP review and should be published in a 
> > separate
> >  repo over the next few days.
> >  The code operates in one of three modes, selectable via the 
> > sched_policy
> >  module parameter :
> >  - sched_policy=0 uses a hardware scheduler running in the MEC 
> > block within
> >  CP, and allows oversubscription (more queues than HW slots)
> >  - sched_policy=1 also uses HW scheduling but does not allow
> >  oversubscription, so create_queue requests fail when we run out 
> > of HW slots
> >  - sched_policy=2 does not use HW scheduling, so the driver 
> > manually assigns
> >  queues to HW slots by programming registers
> >  The "no HW scheduling" option is for debug & new hardware bringup 
> > only, so
> >  has less test coverage than the other options. Default in the 
> > current code
> >  is "HW scheduling without oversubscription" since that is where 
> > we have the
> >  most test coverage but we expect to change the default to "HW 
> > scheduling
> >  with oversubscription" after further testing. This effectively 
> > removes the
> >  HW limit on the number of work queues available to applications.
> >  Programs running on the GPU are associated with an address space 
> > through the
> >  VMID field, which is translated to a unique PASID at access time 
> > via a set
> >  of 16 VMID-to-PASID mapping registers. The available VMIDs 
> > (currently 16)
> >  are partitioned (under control of the radeon kgd) between current
> >  gfx/compute and HSA compute, with each getting 8 in the current 
> > code. The
> >  VMID-to-PASID mapping registers are updated by the HW scheduler 
> > when used,
> >  and by driver code if HW scheduling is not being used.
> >  The Sea Islands compute queues use a new "doorbell" mechanism 
> > instead of the
> >  earlier kernel-managed 

[PATCH RFA] drm: add of_graph endpoint helper to find possible CRTCs

2014-07-10 Thread Rob Clark
On Thu, Jul 10, 2014 at 2:01 PM, Russell King
 wrote:
> Add a helper to allow encoders to find their possible CRTCs from the
> OF graph without having to re-implement this functionality.  We add a
> device_node to drm_crtc which corresponds with the port node in the
> DT description of the CRTC device.
>
> We can then scan the DRM device list for CRTCs to find their index,
> matching the appropriate CRTC using the port device_node, thus building
> up the possible CRTC mask.
>
> Signed-off-by: Russell King 
> ---
>
> RFA = request for acks
>
> - Updated commentry in the drm_of_find_possible_crtcs() comment block to
> point at the description of the of_graph bindings.
> - Not updated for drm kerneldoc as I'm unable to build the documentation.

hmm, I wonder if kbuild robot builds docs?

Anyways, no worries.. I can add the entries in drm.tmpl once this
lands.. if I forget, someone remind me ;-)


Reviewed-by: Rob Clark 


>
>  drivers/gpu/drm/Makefile |  1 +
>  drivers/gpu/drm/drm_of.c | 67 
> 
>  include/drm/drm_crtc.h   |  2 ++
>  include/drm/drm_of.h | 18 +
>  4 files changed, 88 insertions(+)
>  create mode 100644 drivers/gpu/drm/drm_of.c
>  create mode 100644 include/drm/drm_of.h
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index dd2ba4269740..533d011eab3e 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -20,6 +20,7 @@ drm-$(CONFIG_COMPAT) += drm_ioc32.o
>  drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
>  drm-$(CONFIG_PCI) += ati_pcigart.o
>  drm-$(CONFIG_DRM_PANEL) += drm_panel.o
> +drm-$(CONFIG_OF) += drm_of.o
>
>  drm-usb-y   := drm_usb.o
>
> diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
> new file mode 100644
> index ..16150a00c237
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_of.c
> @@ -0,0 +1,67 @@
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> + * drm_crtc_port_mask - find the mask of a registered CRTC by port OF node
> + * @dev: DRM device
> + * @port: port OF node
> + *
> + * Given a port OF node, return the possible mask of the corresponding
> + * CRTC within a device's list of CRTCs.  Returns zero if not found.
> + */
> +static uint32_t drm_crtc_port_mask(struct drm_device *dev,
> +  struct device_node *port)
> +{
> +   unsigned int index = 0;
> +   struct drm_crtc *tmp;
> +
> +   list_for_each_entry(tmp, >mode_config.crtc_list, head) {
> +   if (tmp->port == port)
> +   return 1 << index;
> +
> +   index++;
> +   }
> +
> +   return 0;
> +}
> +
> +/**
> + * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
> + * @dev: DRM device
> + * @port: encoder port to scan for endpoints
> + *
> + * Scan all endpoints attached to a port, locate their attached CRTCs,
> + * and generate the DRM mask of CRTCs which may be attached to this
> + * encoder.
> + *
> + * See Documentation/devicetree/bindings/graph.txt for the bindings.
> + */
> +uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
> +   struct device_node *port)
> +{
> +   struct device_node *remote_port, *ep = NULL;
> +   uint32_t possible_crtcs = 0;
> +
> +   do {
> +   ep = of_graph_get_next_endpoint(port, ep);
> +   if (!ep)
> +   break;
> +
> +   remote_port = of_graph_get_remote_port(ep);
> +   if (!remote_port) {
> +   of_node_put(ep);
> +   return 0;
> +   }
> +
> +   possible_crtcs |= drm_crtc_port_mask(dev, remote_port);
> +
> +   of_node_put(remote_port);
> +   } while (1);
> +
> +   return possible_crtcs;
> +}
> +EXPORT_SYMBOL(drm_of_find_possible_crtcs);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 251b75e6bf7a..6a94909f1ca9 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -41,6 +41,7 @@ struct drm_framebuffer;
>  struct drm_object_properties;
>  struct drm_file;
>  struct drm_clip_rect;
> +struct device_node;
>
>  #define DRM_MODE_OBJECT_CRTC 0x
>  #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
> @@ -314,6 +315,7 @@ struct drm_crtc_funcs {
>   */
>  struct drm_crtc {
> struct drm_device *dev;
> +   struct device_node *port;
> struct list_head head;
>
> /**
> diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
> new file mode 100644
> index ..2441f7112074
> --- /dev/null
> +++ b/include/drm/drm_of.h
> @@ -0,0 +1,18 @@
> +#ifndef __DRM_OF_H__
> +#define __DRM_OF_H__
> +
> +struct drm_device;
> +struct device_node;
> +
> +#ifdef CONFIG_OF
> +extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
> +  struct 

[PATCH] modesetting: Support native primary plane rotation

2014-07-10 Thread Mark Kettenis
> From: Chris Wilson 
> Date: Wed,  9 Jul 2014 12:14:41 +0100
> 
> With the advent of universal drm planes and the introduction of generic
> plane properties for rotations, we can query and program the hardware
> for native rotation support.
> 
> NOTE: this depends upon the next release of libdrm to remove one
> opencoded define.
> 
> v2: Use enum to determine primary plane, suggested by Pekka Paalanen.
> Use libobj for replacement ffs(), suggested by walter harms
> v3: Support combinations of rotations and reflections
> Eliminate use of ffs() and so remove need for libobj

Surely that means...
>  
> +#ifndef HAVE_FFS
> +extern int ffs(unsigned int value);
> +#endif

This bit should be removed ad well?


[PATCH] modesetting: Support native primary plane rotation

2014-07-10 Thread Pekka Paalanen
On Wed, 9 Jul 2014 11:02:59 +0100
Chris Wilson  wrote:

> On Wed, Jul 09, 2014 at 12:57:12PM +0300, Pekka Paalanen wrote:
> > On Wed,  9 Jul 2014 09:19:08 +0100
> > Chris Wilson  wrote:
> > 
> > > With the advent of universal drm planes and the introduction of generic
> > > plane properties for rotations, we can query and program the hardware
> > > for native rotation support.
> > > 
> > > NOTE: this depends upon the next release of libdrm to remove one
> > > opencoded define.
> > > 
> > > v2: Use enum to determine primary plane, suggested by Pekka Paalanen.
> > > Use libobj for replacement ffs(), suggested by walter harms
> > > 
> > > Signed-off-by: Chris Wilson 
> > > Cc: Pekka Paalanen 
> > > Cc: walter harms 
> > 
> > My concerns have been addressed. On a second read, I found another
> > suspicious thing below.
> > 
> > > + if (strcmp(prop->name, "rotation") == 0) {
> > > + drmmode_crtc->rotation_prop_id = 
> > > proplist->props[j];
> > > + drmmode_crtc->current_rotation = 
> > > proplist->prop_values[j];
> > > + for (k = 0; k < prop->count_enums; k++) 
> > > {
> > > + int rr = -1;
> > > + if (strcmp(prop->enums[k].name, 
> > > "rotate-0") == 0)
> > > + rr = RR_Rotate_0;
> > > + else if 
> > > (strcmp(prop->enums[k].name, "rotate-90") == 0)
> > > + rr = RR_Rotate_90;
> > > + else if 
> > > (strcmp(prop->enums[k].name, "rotate-180") == 0)
> > > + rr = RR_Rotate_180;
> > > + else if 
> > > (strcmp(prop->enums[k].name, "rotate-270") == 0)
> > > + rr = RR_Rotate_270;
> > > + else if 
> > > (strcmp(prop->enums[k].name, "reflect-x") == 0)
> > > + rr = RR_Reflect_X;
> > > + else if 
> > > (strcmp(prop->enums[k].name, "reflect-y") == 0)
> > > + rr = RR_Reflect_Y;
> > > + if (rr != -1) {
> > > + 
> > > drmmode_crtc->map_rotations[rotation_index(rr)] = 1 << 
> > > prop->enums[k].value;
> > > + 
> > > drmmode_crtc->supported_rotations |= rr;
> > 
> > Comparing the above assignments to...
> > 
> > > +static Bool
> > > +rotation_set(xf86CrtcPtr crtc, unsigned rotation)
> > > +{
> > > + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> > > + drmmode_ptr drmmode = drmmode_crtc->drmmode;
> > > +
> > > + if (drmmode_crtc->current_rotation == rotation)
> > > + return TRUE;
> > > +
> > > + if ((drmmode_crtc->supported_rotations & rotation) == 0)
> > > + return FALSE;
> > > +
> > > + if (drmModeObjectSetProperty(drmmode->fd,
> > > +  drmmode_crtc->primary_plane_id,
> > > +  DRM_MODE_OBJECT_PLANE,
> > > +  drmmode_crtc->rotation_prop_id,
> > > +  
> > > drmmode_crtc->map_rotations[rotation_index(rotation)]))
> > 
> > ...the use here, it does not look like you are passing
> > prop->enums[k].value here. It is like you are missing ffs() here or
> > having a 1<< too much in the assignment.
> 
> It doesn't take the enum.value but 1 << enum.value.

Aah, it is not an 'enum', it is a 'bitmask'! Okay, I see it now, I
think.


Thanks,
pq


[Intel-gfx] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

2014-07-10 Thread Tian, Kevin
> From: Daniel Vetter
> Sent: Monday, July 07, 2014 11:40 AM
> 
> On Mon, Jul 07, 2014 at 07:58:30PM +0200, Paolo Bonzini wrote:
> > Il 07/07/2014 19:54, Daniel Vetter ha scritto:
> > >On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
> > >>Il 07/07/2014 16:49, Daniel Vetter ha scritto:
> > >>>So the correct fix to forward intel gpus to guests is indeed to somehow
> > >>>fake the pch pci ids since the driver really needs them. Gross design, 
> > >>>but
> > >>>that's how the hardware works.
> > >>
> > >>A way that could work for virtualization is this: if you find the card 
> > >>has a
> > >>magic subsystem vendor id, fetch the subsystem device id and use _that_
> as
> > >>the PCH device id.
> > >>
> > >>Would that work for you?
> > >
> > >I guess for quemu it also depends upon what windows does since we can't
> > >change that. If we care about that part. Another consideration is
> > >supporting older kernels, if that's possible at all.
> >
> > Yes, but right now it's more important to get something that's not too gross
> > for the future, for both Linux and Windows.  Hacks for existing guests can
> > be done separately, especially since they might differ between Linux (check
> > ISA bridge) and Windows (check 1f.0).
> 
> Well old Linux also checked 1f.0, so kinda the same really. As long as
> 1f.0 is an isa bridge. Wrt Windows I don't really expect them to change
> this (they're probably more focuesed on the windows hypervisor or whatever).

discussion is also on-going with Windows driver folks. Add Allen here.

> 
> In the end if the approach is ok for quemu and isn't much worse than what
> we currently have I don't mind at all about the i915.ko code. I just want
> to avoid flip-flopping around on the hack du jour like we seem to do just
> now.
> -Daniel

actually I'm curious whether it's still necessary to __detect__ PCH. Could
we assume a 1:1 mapping between GPU and PCH, e.g. BDW already hard
code the knowledge:

  } else if (IS_BROADWELL(dev)) {
  dev_priv->pch_type = PCH_LPT;
  dev_priv->pch_id =
  INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
  DRM_DEBUG_KMS("This is Broadwell, assuming "
"LynxPoint LP PCH\n");

Or if there is real usage on non-fixed mapping (not majority), could it be a 
better option to have fixed mapping as a fallback instead of leaving as 
PCH_NONE? Then even when Qemu doesn't provide a special tweaked PCH,
the majority case just works.

Thanks
Kevin


[Bug 81192] Garbled screen with VDPAU playback and h264

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81192

--- Comment #4 from Simon Gebler  ---
Oh, also.. nothing about that can be found in the Xorg logfile.
And I'll try to gather some output from mplayer from when the screen freezes,
if there will be anything, when I got some spare time later and feel like
crashing my xorg again

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[Bug 81192] Garbled screen with VDPAU playback and h264

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81192

--- Comment #3 from Simon Gebler  ---
Created attachment 102580
  --> https://bugs.freedesktop.org/attachment.cgi?id=102580=edit
crash log 2

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[Bug 81192] Garbled screen with VDPAU playback and h264

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81192

--- Comment #2 from Simon Gebler  ---
Created attachment 102579
  --> https://bugs.freedesktop.org/attachment.cgi?id=102579=edit
crash log

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[Bug 81192] Garbled screen with VDPAU playback and h264

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81192

--- Comment #1 from Simon Gebler  ---
Created attachment 102578
  --> https://bugs.freedesktop.org/attachment.cgi?id=102578=edit
vdpauinfo output

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[Bug 81192] New: Garbled screen with VDPAU playback and h264

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81192

  Priority: medium
Bug ID: 81192
  Assignee: dri-devel at lists.freedesktop.org
   Summary: Garbled screen with VDPAU playback and h264
  Severity: normal
Classification: Unclassified
OS: Linux (All)
  Reporter: sige at stripeyc.at
  Hardware: x86-64 (AMD64)
Status: NEW
   Version: unspecified
 Component: Drivers/Gallium/r600
   Product: Mesa

Created attachment 102577
  --> https://bugs.freedesktop.org/attachment.cgi?id=102577=edit
dmesg output

Whenever I try playing a h264 encoded movie, the system/X11 locks up completely
with 3 different symptoms.
X freezes, I might be able to move the mousecursor (which doesn't change), was
able to log in to the machine remotely and reboot it.
X freezes first, full screen is garbled just a few seconds later.
Additionally I might be able to move some square, which is likely the
"cursor".. garbled as well. I must be honest I didn't try logging in remotely
there yet, if the machine itself is still alive.

Machie is running:
Linux 3.15.4 from the repo and tried on a 3.16rc4 today (Installed that to test
against a kernel bug)
Xorg is 1.15.2
mesa is 10.2.3
mplayer is SVN-r37224

I tried a mpeg2 video and played it just fine
( mplayer -vo vdpau -vc ffmpeg12vdpau  )
I also got two h264 files and it freezes/garbles every time there

http://samples.mplayerhq.hu/V-codecs/h264/PAFF/Grey.ts
http://samples.mplayerhq.hu/V-codecs/h264/nature_704x576_25Hz_1500kbits.h264
mplayer -vo vdpau -vc ffh264vdpau 

It reliably just freezes the screen, with the mouse working for a while or
completely garbles it.
I also had an occurrence of the screen going garbled and then black, back to
the garbled screen. Three times or something. Maybe he tried resetting the GPU
or something; I don't know. Not sure if I can find any logs from that one.

Also: Haven't tried any other codecs yet, that might be supported.

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[PATCH 1/1] drm/tilcdc: Fix build breakage

2014-07-10 Thread Dave Airlie
On 10 July 2014 17:09, Daniel Vetter  wrote:
> On Thu, Jul 10, 2014 at 12:02:15PM +1000, Dave Airlie wrote:
>> On 9 July 2014 21:42, Sachin Kamat  wrote:
>> > Commit 34ea3d386347 ("drm: add register and unregister functions
>> > for connectors") probably missed out converting the
>> > drm_sysfs_connector_remove instances in the following files.
>> > Without this patch we get the following compilation error:
>> > ERROR: "drm_sysfs_connector_remove" [drivers/gpu/drm/tilcdc/tilcdc.ko] 
>> > undefined!
>> >
>> > Signed-off-by: Sachin Kamat 
>> > CC: Thomas Wood 
>> > CC: David Herrmann 
>> > CC: Daniel Vetter 
>> > ---
>> > Only compile tested.
>>
>> Oops, applied thanks,
>>
>> I did an arm build just on the drm dir, forgot to let it run to
>> completion over the whole tree.
>
> Yeah, my apologies for breaking things. Nowadays I rely on the 0-day
> builder for arm build testing, dunno why it didn't report this one here.
> Might be good to check with Wu Fengguang that your driver is included - he
> tends to catch other drm breakage on arm drivers well.

I just got the report now :-) after I fixed it!

Dave.


[PATCH RFA] drm: add of_graph endpoint helper to find possible CRTCs

2014-07-10 Thread Russell King
Add a helper to allow encoders to find their possible CRTCs from the
OF graph without having to re-implement this functionality.  We add a
device_node to drm_crtc which corresponds with the port node in the
DT description of the CRTC device.

We can then scan the DRM device list for CRTCs to find their index,
matching the appropriate CRTC using the port device_node, thus building
up the possible CRTC mask.

Signed-off-by: Russell King 
---

RFA = request for acks

- Updated commentry in the drm_of_find_possible_crtcs() comment block to
point at the description of the of_graph bindings.
- Not updated for drm kerneldoc as I'm unable to build the documentation.

 drivers/gpu/drm/Makefile |  1 +
 drivers/gpu/drm/drm_of.c | 67 
 include/drm/drm_crtc.h   |  2 ++
 include/drm/drm_of.h | 18 +
 4 files changed, 88 insertions(+)
 create mode 100644 drivers/gpu/drm/drm_of.c
 create mode 100644 include/drm/drm_of.h

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index dd2ba4269740..533d011eab3e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -20,6 +20,7 @@ drm-$(CONFIG_COMPAT) += drm_ioc32.o
 drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
 drm-$(CONFIG_PCI) += ati_pcigart.o
 drm-$(CONFIG_DRM_PANEL) += drm_panel.o
+drm-$(CONFIG_OF) += drm_of.o

 drm-usb-y   := drm_usb.o

diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
new file mode 100644
index ..16150a00c237
--- /dev/null
+++ b/drivers/gpu/drm/drm_of.c
@@ -0,0 +1,67 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * drm_crtc_port_mask - find the mask of a registered CRTC by port OF node
+ * @dev: DRM device
+ * @port: port OF node
+ *
+ * Given a port OF node, return the possible mask of the corresponding
+ * CRTC within a device's list of CRTCs.  Returns zero if not found.
+ */
+static uint32_t drm_crtc_port_mask(struct drm_device *dev,
+  struct device_node *port)
+{
+   unsigned int index = 0;
+   struct drm_crtc *tmp;
+
+   list_for_each_entry(tmp, >mode_config.crtc_list, head) {
+   if (tmp->port == port)
+   return 1 << index;
+
+   index++;
+   }
+
+   return 0;
+}
+
+/**
+ * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
+ * @dev: DRM device
+ * @port: encoder port to scan for endpoints
+ *
+ * Scan all endpoints attached to a port, locate their attached CRTCs,
+ * and generate the DRM mask of CRTCs which may be attached to this
+ * encoder.
+ *
+ * See Documentation/devicetree/bindings/graph.txt for the bindings.
+ */
+uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
+   struct device_node *port)
+{
+   struct device_node *remote_port, *ep = NULL;
+   uint32_t possible_crtcs = 0;
+
+   do {
+   ep = of_graph_get_next_endpoint(port, ep);
+   if (!ep)
+   break;
+
+   remote_port = of_graph_get_remote_port(ep);
+   if (!remote_port) {
+   of_node_put(ep);
+   return 0;
+   }
+
+   possible_crtcs |= drm_crtc_port_mask(dev, remote_port);
+
+   of_node_put(remote_port);
+   } while (1);
+
+   return possible_crtcs;
+}
+EXPORT_SYMBOL(drm_of_find_possible_crtcs);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 251b75e6bf7a..6a94909f1ca9 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -41,6 +41,7 @@ struct drm_framebuffer;
 struct drm_object_properties;
 struct drm_file;
 struct drm_clip_rect;
+struct device_node;

 #define DRM_MODE_OBJECT_CRTC 0x
 #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
@@ -314,6 +315,7 @@ struct drm_crtc_funcs {
  */
 struct drm_crtc {
struct drm_device *dev;
+   struct device_node *port;
struct list_head head;

/**
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
new file mode 100644
index ..2441f7112074
--- /dev/null
+++ b/include/drm/drm_of.h
@@ -0,0 +1,18 @@
+#ifndef __DRM_OF_H__
+#define __DRM_OF_H__
+
+struct drm_device;
+struct device_node;
+
+#ifdef CONFIG_OF
+extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
+  struct device_node *port);
+#else
+static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
+ struct device_node *port)
+{
+   return 0;
+}
+#endif
+
+#endif /* __DRM_OF_H__ */
-- 
1.8.3.1



[PATCH 00/83] AMD HSA kernel driver

2014-07-10 Thread Jerome Glisse
On Fri, Jul 11, 2014 at 12:45:27AM +0300, Oded Gabbay wrote:
> This patch set implements a Heterogeneous System Architecture (HSA) driver 
> for radeon-family GPUs. 

This is just quick comments on few things. Given size of this, people
will need to have time to review things.

> 
> HSA allows different processor types (CPUs, DSPs, GPUs, etc..) to share 
> system resources more effectively via HW features including shared pageable 
> memory, userspace-accessible work queues, and platform-level atomics. In 
> addition to the memory protection mechanisms in GPUVM and IOMMUv2, the Sea 
> Islands family of GPUs also performs HW-level validation of commands passed 
> in through the queues (aka rings).
> 
> The code in this patch set is intended to serve both as a sample driver for 
> other HSA-compatible hardware devices and as a production driver for 
> radeon-family processors. The code is architected to support multiple CPUs 
> each with connected GPUs, although the current implementation focuses on a 
> single Kaveri/Berlin APU, and works alongside the existing radeon kernel 
> graphics driver (kgd). 
> 
> AMD GPUs designed for use with HSA (Sea Islands and up) share some hardware 
> functionality between HSA compute and regular gfx/compute (memory, 
> interrupts, registers), while other functionality has been added 
> specifically for HSA compute  (hw scheduler for virtualized compute rings). 
> All shared hardware is owned by the radeon graphics driver, and an interface 
> between kfd and kgd allows the kfd to make use of those shared resources, 
> while HSA-specific functionality is managed directly by kfd by submitting 
> packets into an HSA-specific command queue (the "HIQ").
> 
> During kfd module initialization a char device node (/dev/kfd) is created 
> (surviving until module exit), with ioctls for queue creation & management, 
> and data structures are initialized for managing HSA device topology. 
> 
> The rest of the initialization is driven by calls from the radeon kgd at 
> the following points :
> 
> - radeon_init (kfd_init)
> - radeon_exit (kfd_fini)
> - radeon_driver_load_kms (kfd_device_probe, kfd_device_init)
> - radeon_driver_unload_kms (kfd_device_fini)
> 
> During the probe and init processing per-device data structures are 
> established which connect to the associated graphics kernel driver. This 
> information is exposed to userspace via sysfs, along with a version number 
> allowing userspace to determine if a topology change has occurred while it 
> was reading from sysfs. 
> 
> The interface between kfd and kgd also allows the kfd to request buffer 
> management services from kgd, and allows kgd to route interrupt requests to 
> kfd code since the interrupt block is shared between regular 
> graphics/compute and HSA compute subsystems in the GPU.
> 
> The kfd code works with an open source usermode library ("libhsakmt") which 
> is in the final stages of IP review and should be published in a separate 
> repo over the next few days. 
> 
> The code operates in one of three modes, selectable via the sched_policy 
> module parameter :
> 
> - sched_policy=0 uses a hardware scheduler running in the MEC block within 
> CP, and allows oversubscription (more queues than HW slots) 
> 
> - sched_policy=1 also uses HW scheduling but does not allow 
> oversubscription, so create_queue requests fail when we run out of HW slots 
> 
> - sched_policy=2 does not use HW scheduling, so the driver manually assigns 
> queues to HW slots by programming registers
> 
> The "no HW scheduling" option is for debug & new hardware bringup only, so 
> has less test coverage than the other options. Default in the current code 
> is "HW scheduling without oversubscription" since that is where we have the 
> most test coverage but we expect to change the default to "HW scheduling 
> with oversubscription" after further testing. This effectively removes the 
> HW limit on the number of work queues available to applications.
> 
> Programs running on the GPU are associated with an address space through the 
> VMID field, which is translated to a unique PASID at access time via a set 
> of 16 VMID-to-PASID mapping registers. The available VMIDs (currently 16) 
> are partitioned (under control of the radeon kgd) between current 
> gfx/compute and HSA compute, with each getting 8 in the current code. The 
> VMID-to-PASID mapping registers are updated by the HW scheduler when used, 
> and by driver code if HW scheduling is not being used.  
> 
> The Sea Islands compute queues use a new "doorbell" mechanism instead of the 
> earlier kernel-managed write pointer registers. Doorbells use a separate BAR 
> dedicated for this purpose, and pages within the doorbell aperture are 
> mapped to userspace (each page mapped to only one user address space). 
> Writes to the doorbell aperture are intercepted by GPU hardware, allowing 
> userspace code to safely manage work queues (rings) without requiring a 
> kernel call for every 

[pull] radeon drm-fixes-3.16

2014-07-10 Thread Alex Deucher
Hi Dave,

This new request drops the pageflipping fixes for now.  Just a few small
fixes for dpm, DP, and a fix for a hang on boot evergreen.

The following changes since commit 2db38e06ecda80063d748df7bd79b7186c8831e0:

  Merge tag 'drm-intel-fixes-2014-07-09' of 
git://anongit.freedesktop.org/drm-intel into drm-fixes (2014-07-10 10:10:06 
+1000)

are available in the git repository at:


  git://people.freedesktop.org/~agd5f/linux drm-fixes-3.16

for you to fetch changes up to 41959341ac7e33dd360c7a881d13566f9eca37b2:

  drm/radeon/dpm: Reenabling SS on Cayman (2014-07-10 17:01:30 -0400)


Alex Deucher (3):
  drm/radeon/dp: return -EIO for flags not zero case
  drm/radeon: fix typo in golden register setup on evergreen
  drm/radeon: fix typo in ci_stop_dpm()

Alexandre Demers (1):
  drm/radeon/dpm: Reenabling SS on Cayman

Christian K?nig (1):
  drm/radeon: only print meaningful VM faults

 drivers/gpu/drm/radeon/atombios_dp.c |  2 +-
 drivers/gpu/drm/radeon/ci_dpm.c  |  2 +-
 drivers/gpu/drm/radeon/cik.c |  6 --
 drivers/gpu/drm/radeon/evergreen.c   | 14 --
 drivers/gpu/drm/radeon/rv770_dpm.c   |  6 --
 drivers/gpu/drm/radeon/si.c  |  6 --
 6 files changed, 18 insertions(+), 18 deletions(-)


[Bug 80868] Support screen scaling modes for external monitors

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=80868

Alex Deucher  changed:

   What|Removed |Added

 Attachment #102491|0   |1
is obsolete||

--- Comment #13 from Alex Deucher  ---
Created attachment 102565
  --> https://bugs.freedesktop.org/attachment.cgi?id=102565=edit
better patch

This version handles the no modes case properly.

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[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=72921

Rpnpif  changed:

   What|Removed |Added

 CC||rpnpif at free.fr

--- Comment #32 from Rpnpif  ---
This patch (bapm=true) fixed all bug issue that I had from 3.13 with MSI
A78M-E35 motherboard with AMD APU A4-5300. My test are with 3.14.12 kernel and
radeon.dpm=1.

More ! "vblank_mode=1 glxgears" give two times more fps than with radeon.dpm=0.
Better temperature of the APU : cooler in idle mode and cool faster.

Succeed until now.

Thank you very much for your work.

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[Bug 73053] dpm hangs with BTC parts

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=73053

--- Comment #37 from Rpnpif  ---
(In reply to comment #36)
> You have an APU.  This bug is specifically about dpm on BTC discrete GPUs. 
> It sounds like you are seeing bug 72921.  Please try the patch on that bug.

You are right and the last patch of bug 72921 fixes my bug issue.
Thank you very much.

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[pull] radeon drm-fixes-3.16

2014-07-10 Thread Alex Deucher
Hi Dave,

Ignore this request for now.  Mario ran into some problems with
further pageflipping testing so I'll send a new request once we've
sorted that out.

Alex


On Thu, Jul 10, 2014 at 11:46 AM, Alex Deucher  wrote:
> Hi Dave,
>
> Mostly fixes to fallout from the pageflipping changes in 3.16.  The
> rest are dpm and display fixes and a boot hang fix.
>
> The following changes since commit 2db38e06ecda80063d748df7bd79b7186c8831e0:
>
>   Merge tag 'drm-intel-fixes-2014-07-09' of 
> git://anongit.freedesktop.org/drm-intel into drm-fixes (2014-07-10 10:10:06 
> +1000)
>
> are available in the git repository at:
>
>
>   git://people.freedesktop.org/~agd5f/linux drm-fixes-3.16
>
> for you to fetch changes up to cb2416af027a334ba62f49042386686fcf5b7425:
>
>   drm/radeon/dpm: Reenabling SS on Cayman (2014-07-10 09:31:38 -0400)
>
> 
> Alex Deucher (3):
>   drm/radeon/dp: return -EIO for flags not zero case
>   drm/radeon: fix typo in golden register setup on evergreen
>   drm/radeon: fix typo in ci_stop_dpm()
>
> Alexandre Demers (1):
>   drm/radeon/dpm: Reenabling SS on Cayman
>
> Christian K?nig (1):
>   drm/radeon: only print meaningful VM faults
>
> Michel D?nzer (3):
>   drm/radeon: Program page flips to execute in hblank instead of vblank
>   drm/radeon: Move pinning the BO back to radeon_crtc_page_flip()
>   drm/radeon: Complete page flip even if waiting on the BO fence fails
>
>  drivers/gpu/drm/radeon/atombios_crtc.c  |  28 ++--
>  drivers/gpu/drm/radeon/atombios_dp.c|   2 +-
>  drivers/gpu/drm/radeon/ci_dpm.c |   2 +-
>  drivers/gpu/drm/radeon/cik.c|  64 ++---
>  drivers/gpu/drm/radeon/evergreen.c  | 100 +++--
>  drivers/gpu/drm/radeon/r100.c   |  48 ++-
>  drivers/gpu/drm/radeon/r600.c   |  18 +--
>  drivers/gpu/drm/radeon/radeon.h |   5 +-
>  drivers/gpu/drm/radeon/radeon_asic.c|  22 ---
>  drivers/gpu/drm/radeon/radeon_asic.h|   4 -
>  drivers/gpu/drm/radeon/radeon_display.c | 243 
> +---
>  drivers/gpu/drm/radeon/radeon_mode.h|   3 +-
>  drivers/gpu/drm/radeon/rs600.c  |  28 +---
>  drivers/gpu/drm/radeon/rv770.c  |  24 +---
>  drivers/gpu/drm/radeon/rv770_dpm.c  |   6 -
>  drivers/gpu/drm/radeon/si.c |  58 ++--
>  16 files changed, 172 insertions(+), 483 deletions(-)


[PATCH 3/3] drm/gk20a: reclocking support

2014-07-10 Thread Alexandre Courbot
Add support for reclocking on GK20A, using a statically-defined pstates
table. The algorithms for calculating the coefficients and setting the
clocks are directly taken from the ChromeOS kernel.

Signed-off-by: Alexandre Courbot 
---
 drivers/gpu/drm/nouveau/Makefile   |   1 +
 drivers/gpu/drm/nouveau/core/engine/device/nve0.c  |   1 +
 .../gpu/drm/nouveau/core/include/subdev/clock.h|   1 +
 drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c  | 670 +
 4 files changed, 673 insertions(+)
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index a882ca0f3819..205d1ae7dd03 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -65,6 +65,7 @@ nouveau-y += core/subdev/clock/nva3.o
 nouveau-y += core/subdev/clock/nvaa.o
 nouveau-y += core/subdev/clock/nvc0.o
 nouveau-y += core/subdev/clock/nve0.o
+nouveau-y += core/subdev/clock/gk20a.o
 nouveau-y += core/subdev/clock/pllnv04.o
 nouveau-y += core/subdev/clock/pllnva3.o
 nouveau-y += core/subdev/devinit/base.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c 
b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index c75e9fc9b25f..a8b5184088b5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -158,6 +158,7 @@ nve0_identify(struct nouveau_device *device)
break;
case 0xea:
device->cname = "GK20A";
+   device->oclass[NVDEV_SUBDEV_CLOCK  ] = _clock_oclass;
device->oclass[NVDEV_SUBDEV_MC ] =  nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS] =  nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER  ] = _timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h 
b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index c0fe191c9787..9fed2834f25e 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -138,6 +138,7 @@ extern struct nouveau_oclass *nvaa_clock_oclass;
 extern struct nouveau_oclass nva3_clock_oclass;
 extern struct nouveau_oclass nvc0_clock_oclass;
 extern struct nouveau_oclass nve0_clock_oclass;
+extern struct nouveau_oclass gk20a_clock_oclass;

 int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
 int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c 
b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
new file mode 100644
index ..e175cfda0a48
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
+ *
+ */
+
+#define MHZ (1000 * 1000)
+
+#define MASK(w)((1 << w) - 1)
+
+#define SYS_GPCPLL_CFG_BASE0x00137000
+#define GPC_BCASE_GPCPLL_CFG_BASE  0x00132800
+
+#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
+#define GPCPLL_CFG_ENABLE  BIT(0)
+#define GPCPLL_CFG_IDDQBIT(1)
+#define GPCPLL_CFG_LOCK_DET_OFFBIT(4)
+#define GPCPLL_CFG_LOCKBIT(17)
+
+#define GPCPLL_COEFF   (SYS_GPCPLL_CFG_BASE + 4)
+#define GPCPLL_COEFF_M_SHIFT   0
+#define GPCPLL_COEFF_M_WIDTH   8
+#define GPCPLL_COEFF_N_SHIFT   8
+#define GPCPLL_COEFF_N_WIDTH   8
+#define GPCPLL_COEFF_P_SHIFT   16
+#define GPCPLL_COEFF_P_WIDTH   6
+
+#define GPCPLL_CFG2(SYS_GPCPLL_CFG_BASE + 0xc)
+#define GPCPLL_CFG2_SETUP2_SHIFT   16
+#define GPCPLL_CFG2_PLL_STEPA_SHIFT24
+
+#define GPCPLL_CFG3(SYS_GPCPLL_CFG_BASE + 0x18)
+#define GPCPLL_CFG3_PLL_STEPB_SHIFT16
+
+#define 

[PATCH 2/3] drm/nouveau/clk: support for non-BIOS pstates

2014-07-10 Thread Alexandre Courbot
Make nouveau_clock_create() take new two optional arguments: an array
of pstates and its size. When these are specified,
nouveau_clock_create() will use the provided pstates instead of
probing them using the BIOS.

This is useful for platforms which do not provide a BIOS, like Tegra.

Signed-off-by: Alexandre Courbot 
---
 drivers/gpu/drm/nouveau/core/include/subdev/clock.h |  8 +---
 drivers/gpu/drm/nouveau/core/subdev/clock/base.c| 16 
 drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c|  4 ++--
 drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c|  4 ++--
 drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c|  2 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c|  4 ++--
 drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c|  4 ++--
 drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c|  4 ++--
 drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c|  4 ++--
 9 files changed, 30 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h 
b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index c01e29c9f89a..c0fe191c9787 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -108,8 +108,9 @@ struct nouveau_clocks {
int mdiv;
 };

-#define nouveau_clock_create(p,e,o,i,r,d)  
\
-   nouveau_clock_create_((p), (e), (o), (i), (r), sizeof(**d), (void **)d)
+#define nouveau_clock_create(p,e,o,i,r,s,n,d)  
\
+   nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d),  \
+ (void **)d)
 #define nouveau_clock_destroy(p) ({
\
struct nouveau_clock *clk = (p);   \
_nouveau_clock_dtor(nv_object(clk));   \
@@ -123,7 +124,8 @@ struct nouveau_clocks {

 int  nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
   struct nouveau_oclass *,
-  struct nouveau_clocks *, bool, int, void **);
+  struct nouveau_clocks *, struct nouveau_pstate *,
+  int, bool, int, void **);
 void _nouveau_clock_dtor(struct nouveau_object *);
 int _nouveau_clock_init(struct nouveau_object *);
 #define _nouveau_clock_fini _nouveau_subdev_fini
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c 
b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index 63b314a033cb..e5798e74d616 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -464,6 +464,7 @@ nouveau_clock_create_(struct nouveau_object *parent,
  struct nouveau_object *engine,
  struct nouveau_oclass *oclass,
  struct nouveau_clocks *clocks,
+ struct nouveau_pstate *pstates, int nb_pstates,
  bool allow_reclock,
  int length, void **object)
 {
@@ -482,10 +483,17 @@ nouveau_clock_create_(struct nouveau_object *parent,
clk->domains = clocks;
clk->ustate = -1;

-   idx = 0;
-   do {
-   ret = nouveau_pstate_new(clk, idx++);
-   } while (ret == 0);
+   /* If no pstates are provided, try and fetch them from the BIOS */
+   if (!pstates) {
+   idx = 0;
+   do {
+   ret = nouveau_pstate_new(clk, idx++);
+   } while (ret == 0);
+   } else {
+   for (idx = 0; idx < nb_pstates; idx++)
+   list_add_tail([idx].head, >states);
+   clk->state_nr = nb_pstates;
+   }

clk->allow_reclock = allow_reclock;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c 
b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
index eb2d4425a49e..4c48232686be 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
@@ -82,8 +82,8 @@ nv04_clock_ctor(struct nouveau_object *parent, struct 
nouveau_object *engine,
struct nv04_clock_priv *priv;
int ret;

-   ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, false,
-  );
+   ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
+  false, );
*pobject = nv_object(priv);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c 
b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
index 8a9e16839791..08368fe97029 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
@@ -213,8 +213,8 @@ nv40_clock_ctor(struct nouveau_object *parent, struct 
nouveau_object *engine,
struct nv40_clock_priv *priv;
int ret;

-   ret 

[PATCH 1/3] drm/nouveau/clk: make therm and volt devices optional

2014-07-10 Thread Alexandre Courbot
Allow the clock subsystem to operate even if voltage and thermal devices
are not set for the device (for people with watercooling! ;))

Signed-off-by: Alexandre Courbot 
---
 drivers/gpu/drm/nouveau/core/subdev/clock/base.c | 36 +++-
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c 
b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index 22351f594d2a..63b314a033cb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -90,16 +90,20 @@ nouveau_cstate_prog(struct nouveau_clock *clk,
cstate = >base;
}

-   ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
-   if (ret && ret != -ENODEV) {
-   nv_error(clk, "failed to raise fan speed: %d\n", ret);
-   return ret;
+   if (ptherm) {
+   ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
+   if (ret && ret != -ENODEV) {
+   nv_error(clk, "failed to raise fan speed: %d\n", ret);
+   return ret;
+   }
}

-   ret = volt->set_id(volt, cstate->voltage, +1);
-   if (ret && ret != -ENODEV) {
-   nv_error(clk, "failed to raise voltage: %d\n", ret);
-   return ret;
+   if (volt) {
+   ret = volt->set_id(volt, cstate->voltage, +1);
+   if (ret && ret != -ENODEV) {
+   nv_error(clk, "failed to raise voltage: %d\n", ret);
+   return ret;
+   }
}

ret = clk->calc(clk, cstate);
@@ -108,13 +112,17 @@ nouveau_cstate_prog(struct nouveau_clock *clk,
clk->tidy(clk);
}

-   ret = volt->set_id(volt, cstate->voltage, -1);
-   if (ret && ret != -ENODEV)
-   nv_error(clk, "failed to lower voltage: %d\n", ret);
+   if (volt) {
+   ret = volt->set_id(volt, cstate->voltage, -1);
+   if (ret && ret != -ENODEV)
+   nv_error(clk, "failed to lower voltage: %d\n", ret);
+   }

-   ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
-   if (ret && ret != -ENODEV)
-   nv_error(clk, "failed to lower fan speed: %d\n", ret);
+   if (ptherm) {
+   ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
+   if (ret && ret != -ENODEV)
+   nv_error(clk, "failed to lower fan speed: %d\n", ret);
+   }

return 0;
 }
-- 
2.0.0



[PATCH 0/3] drm/gk20a: support for reclocking

2014-07-10 Thread Alexandre Courbot
This series adds support for reclocking on GK20A. The first two patches touch
the clock subsystem to allow GK20A to operate, by making the presence of the
thermal and voltage devices optional, and allowing pstates to be provided
directly instead of being probed using the BIOS (which Tegra does not have).

The last patch adds the GK20A clock device. Arguably the clock can be seen as a
stripped-down version of what is seen on NVE0, however instead of using NVE0
support has been written from scratch using the ChromeOS kernel as a basis.
There are several reasons for this:

- The ChromeOS driver uses a lookup table for the P coefficient which I could
  not find in the NVE0 driver,
- Some registers that NVE0 expects to find are not present on GK20A (e.g.
  0x137120 and 0x137140),
- Calculation of MNP is done differently from what is performed in
  nva3_pll_calc(), and it might be interesting to compare the two methods,
- All the same, the programming sequence is done differently in the ChromeOS
  driver and NVE0 could possibly benefit from it (?)

It would be interesting to try and merge both, but for now I prefer to have the
two coexisting to ensure proper operation on GK20A and besure I don't break
dGPU support. :)

Regarding the first patch, one might argue that I could as well add thermal
and voltage devices to GK20A. The reason this is not done is because these
currently depend heavily on the presence of a BIOS, and will require a rework
similar to that done in patch 2 for clocks. I would like to make sure this
approach is approved because applying it to other subdevs.

Alexandre Courbot (3):
  drm/nouveau/clk: make therm and volt devices optional
  drm/nouveau/clk: support for non-BIOS pstates
  drm/gk20a: reclocking support

 drivers/gpu/drm/nouveau/Makefile   |   1 +
 drivers/gpu/drm/nouveau/core/engine/device/nve0.c  |   1 +
 .../gpu/drm/nouveau/core/include/subdev/clock.h|   9 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/base.c   |  52 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c  | 670 +
 drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c   |   4 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c   |   4 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c   |   2 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c   |   4 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c   |   4 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c   |   4 +-
 drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c   |   4 +-
 12 files changed, 725 insertions(+), 34 deletions(-)
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c

-- 
2.0.0



[Bug 80868] Support screen scaling modes for external monitors

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=80868

--- Comment #12 from Alex Deucher  ---
(In reply to comment #11)
> Alex, this is great! It works perfectly for me. I tried all available modes.
> Thanks a lot.
> 
> A follow up question: Is this setting supposed to be reset on reboot or
> remembered? It is reset for me. If one would like to have this remembered,
> in which tool should one ask for such a feature (kernel, X, DE, somewhere
> else)? Thanks.

It's up to the desktop environment.  It should be saved as part of the display
configuration (e.g., along with display modes, orientations, etc., etc.).

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[Bug 80868] Support screen scaling modes for external monitors

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=80868

--- Comment #11 from Kamil P?ral  ---
Alex, this is great! It works perfectly for me. I tried all available modes.
Thanks a lot.

A follow up question: Is this setting supposed to be reset on reboot or
remembered? It is reset for me. If one would like to have this remembered, in
which tool should one ask for such a feature (kernel, X, DE, somewhere else)?
Thanks.

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[PATCH 04/83] drm/radeon: Add radeon <--> kfd interface

2014-07-10 Thread Joe Perches
On Fri, 2014-07-11 at 00:50 +0300, Oded Gabbay wrote:
> This patch adds the interface between the radeon driver and the kfd
> driver. The interface implementation is contained in
> radeon_kfd.c and radeon_kfd.h.
[]
>  include/linux/radeon_kfd.h  | 67 ++

Is there a good reason to put this file in include/linux?




[PATCH 28/83] mm: Change timing of notification to IOMMUs about a page to be invalidated

2014-07-10 Thread Hugh Dickins
On Fri, 11 Jul 2014, Joerg Roedel wrote:
> On Fri, Jul 11, 2014 at 12:53:26AM +0300, Oded Gabbay wrote:
> >  mm/rmap.c | 8 ++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/mm/rmap.c b/mm/rmap.c
> > index 196cd0c..73d4c3d 100644
> > --- a/mm/rmap.c
> > +++ b/mm/rmap.c
> > @@ -1231,13 +1231,17 @@ static int try_to_unmap_one(struct page *page, 
> > struct vm_area_struct *vma,
> > } else
> > dec_mm_counter(mm, MM_FILEPAGES);
> >  
> > +   pte_unmap_unlock(pte, ptl);
> > +
> > +   mmu_notifier_invalidate_page(vma, address, event);
> > +
> > page_remove_rmap(page);
> > page_cache_release(page);
> >  
> > +   return ret;
> > +
> >  out_unmap:
> > pte_unmap_unlock(pte, ptl);
> > -   if (ret != SWAP_FAIL && !(flags & TTU_MUNLOCK))
> > -   mmu_notifier_invalidate_page(vma, address, event);
> >  out:
> > return ret;
> 
> I think there is no bug. In that function the page is just unmapped,
> removed from the rmap (page_remove_rmap), and the LRU list
> (page_cache_release). The page itself is not released in this function,
> so the call mmu_notifier_invalidate_page() at the end is fine.

Agreed, nothing to fix here: the try_to_unmap() callers must hold
their own reference to the page.  If they did not, how could they
be sure that this is a page which is appropriate to unmap?

(Nit: we don't actually take a separate reference for the LRU list:
the page_cache_release above corresponds to the reference in the
pte which has just been removed.)

Hugh


[Bug 81045] [r600] Unreal Engine 4 demo crashed kernel

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81045

--- Comment #4 from Marek Zdunek  ---
Created attachment 102557
  --> https://bugs.freedesktop.org/attachment.cgi?id=102557=edit
xorg.log

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[Bug 81045] [r600] Unreal Engine 4 demo crashed kernel

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81045

--- Comment #3 from Marek Zdunek  ---
same here on Fedora 20

gpu HD 6850 BARTS
kernel  3.15.3-200.fc20.x86_64
mesa10.1.5-1.20140607.fc20 

instant gpu lockup after demo startup, only sounds playing

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[PATCH 28/83] mm: Change timing of notification to IOMMUs about a page to be invalidated

2014-07-10 Thread Andrew Morton
On Fri, 11 Jul 2014 00:53:26 +0300 Oded Gabbay  wrote:

> From: Andrew Lewycky 
> 
> This patch changes the location of the mmu_notifier_invalidate_page function
> call inside try_to_unmap_one. The mmu_notifier_invalidate_page function
> call tells the IOMMU that a pgae should be invalidated.
> 
> The location is changed from after releasing the physical page to
> before releasing the physical page.
> 
> This change should prevent the bug that would occur in the
> (rare) case where the GPU attempts to access a page while the CPU
> attempts to swap out that page (or discard it if it is not dirty).

um OK, but what is the effect on all the other
mmu_notifier_ops.invalidate_page() implementations?

Please spell this out in full detail within the changelog and be sure
to cc the affected maintainers.




[Nouveau] [PATCH v4 4/6] drm/nouveau: synchronize BOs when required

2014-07-10 Thread Daniel Vetter
On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote:
> On architectures for which access to GPU memory is non-coherent,
> caches need to be flushed and invalidated explicitly when BO control
> changes between CPU and GPU.
> 
> This patch adds buffer synchronization functions which invokes the
> correct API (PCI or DMA) to ensure synchronization is effective.
> 
> Based on the TTM DMA cache helper patches by Lucas Stach.
> 
> Signed-off-by: Lucas Stach 
> Signed-off-by: Alexandre Courbot 
> ---
>  drivers/gpu/drm/nouveau/nouveau_bo.c  | 56 
> +++
>  drivers/gpu/drm/nouveau/nouveau_bo.h  |  2 ++
>  drivers/gpu/drm/nouveau/nouveau_gem.c | 12 
>  3 files changed, 70 insertions(+)
> 
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
> b/drivers/gpu/drm/nouveau/nouveau_bo.c
> index 67e9e8e2e2ec..47e4e8886769 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -402,6 +402,60 @@ nouveau_bo_unmap(struct nouveau_bo *nvbo)
>   ttm_bo_kunmap(>kmap);
>  }
>  
> +void
> +nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
> +{
> + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
> + struct nouveau_device *device = nouveau_dev(drm->dev);
> + struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
> + int i;
> +
> + if (!ttm_dma)
> + return;
> +
> + if (nv_device_is_cpu_coherent(device) || nvbo->force_coherent)
> + return;

Is the is_cpu_coherent check really required? On coherent platforms the
sync_for_foo should be a noop. It's the dma api's job to encapsulate this
knowledge so that drivers can be blissfully ignorant. The explicit
is_coherent check makes this a bit leaky. And same comment that underlying
the bus-specifics dma-mapping functions are identical.
-Daniel

> +
> + if (nv_device_is_pci(device)) {
> + for (i = 0; i < ttm_dma->ttm.num_pages; i++)
> + pci_dma_sync_single_for_device(device->pdev,
> + ttm_dma->dma_address[i], PAGE_SIZE,
> + PCI_DMA_TODEVICE);
> + } else {
> + for (i = 0; i < ttm_dma->ttm.num_pages; i++)
> + dma_sync_single_for_device(nv_device_base(device),
> + ttm_dma->dma_address[i], PAGE_SIZE,
> + DMA_TO_DEVICE);
> + }
> +}
> +
> +void
> +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
> +{
> + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
> + struct nouveau_device *device = nouveau_dev(drm->dev);
> + struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
> + int i;
> +
> + if (!ttm_dma)
> + return;
> +
> + if (nv_device_is_cpu_coherent(device) || nvbo->force_coherent)
> + return;
> +
> + if (nv_device_is_pci(device)) {
> + for (i = 0; i < ttm_dma->ttm.num_pages; i++)
> + pci_dma_sync_single_for_cpu(device->pdev,
> + ttm_dma->dma_address[i], PAGE_SIZE,
> + PCI_DMA_FROMDEVICE);
> + } else {
> + for (i = 0; i < ttm_dma->ttm.num_pages; i++)
> + dma_sync_single_for_cpu(nv_device_base(device),
> + ttm_dma->dma_address[i], PAGE_SIZE,
> + DMA_FROM_DEVICE);
> + }
> +}
> +
>  int
>  nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
>   bool no_wait_gpu)
> @@ -418,6 +472,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool 
> interruptible,
>   if (!ttm)
>   return ret;
>  
> + nouveau_bo_sync_for_device(nvbo);
> +
>   device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev);
>   nv_wr32(device, 0x70004, 0x0001);
>   if (!nv_wait(device, 0x070004, 0x0001, 0x))
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h 
> b/drivers/gpu/drm/nouveau/nouveau_bo.h
> index ff17c1f432fc..fa42298d2dca 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.h
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
> @@ -81,6 +81,8 @@ void nouveau_bo_wr32(struct nouveau_bo *, unsigned index, 
> u32 val);
>  void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
>  int  nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
>bool no_wait_gpu);
> +void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo);
> +void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo);
>  
>  struct nouveau_vma *
>  nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
> diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c 
> b/drivers/gpu/drm/nouveau/nouveau_gem.c
> index c90c0dc0afe8..08829a720891 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_gem.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
> @@ -896,6 +896,7 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void 
> *data,
>   spin_lock(>bo.bdev->fence_lock);
>  

[Nouveau] [PATCH v4 2/6] drm/nouveau: map pages using DMA API on platform devices

2014-07-10 Thread Daniel Vetter
On Tue, Jul 08, 2014 at 05:25:57PM +0900, Alexandre Courbot wrote:
> page_to_phys() is not the correct way to obtain the DMA address of a
> buffer on a non-PCI system. Use the DMA API functions for this, which
> are portable and will allow us to use other DMA API functions for
> buffer synchronization.
> 
> Signed-off-by: Alexandre Courbot 
> ---
>  drivers/gpu/drm/nouveau/core/engine/device/base.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c 
> b/drivers/gpu/drm/nouveau/core/engine/device/base.c
> index 18c8c7245b73..e4e9e64988fe 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
> @@ -489,7 +489,10 @@ nv_device_map_page(struct nouveau_device *device, struct 
> page *page)
>   if (pci_dma_mapping_error(device->pdev, ret))
>   ret = 0;
>   } else {
> - ret = page_to_phys(page);
> + ret = dma_map_page(>platformdev->dev, page, 0,
> +PAGE_SIZE, DMA_BIDIRECTIONAL);
> + if (dma_mapping_error(>platformdev->dev, ret))
> + ret = 0;
>   }
>  
>   return ret;
> @@ -501,6 +504,9 @@ nv_device_unmap_page(struct nouveau_device *device, 
> dma_addr_t addr)
>   if (nv_device_is_pci(device))
>   pci_unmap_page(device->pdev, addr, PAGE_SIZE,
>  PCI_DMA_BIDIRECTIONAL);

pci_map/unmap alias to dma_unmap/map when called on the underlying struct
device embedded in pci_device (like for platform drivers). Dunno whether
it's worth to track a pointer to the struct device directly and always
call dma_unmap/map.

Just drive-by comment since I'm interested in how you solve this - i915
has similar fun with buffer sharing and coherent and non-coherent
platforms. Although we don't have fun with pci and non-pci based
platforms.
-Daniel

> + else
> + dma_unmap_page(>platformdev->dev, addr,
> +PAGE_SIZE, DMA_BIDIRECTIONAL);
>  }
>  
>  int
> -- 
> 2.0.0
> 
> ___
> Nouveau mailing list
> Nouveau at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/nouveau

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


[RESEND PATCH v3 06/11] drm: add DT bindings documentation for atmel-hlcdc-dc driver

2014-07-10 Thread Boris BREZILLON
Hi Laurent,

On Thu, 10 Jul 2014 13:16:21 +0200
Laurent Pinchart  wrote:

> Hi Boris,
> 
> Thank you for the patch.
> 
> On Monday 07 July 2014 18:42:59 Boris BREZILLON wrote:
> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> > at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> > controller device.
> > 
> > The HLCDC block provides a single RGB output port, and only supports LCD
> > panels connection to LCD panels for now.
> > 
> > The atmel,panel property link the HLCDC RGB output with the LCD panel
> > connected on this port (note that the HLCDC RGB connector implementation
> > makes use of the DRM panel framework).
> > 
> > Connection to other external devices (DRM bridges) might be added later by
> > mean of a new atmel,xxx (atmel,bridge) property.
> > 
> > Signed-off-by: Boris BREZILLON 
> > ---
> >  .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 +++
> >  1 file changed, 59 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> > b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt new file mode
> > 100644
> > index 000..594bdb2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> > @@ -0,0 +1,59 @@
> > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
> > +
> > +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
> > +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
> > +
> > +Required properties:
> > + - compatible: value should be one of the following:
> > +   "atmel,hlcdc-dc"
> > + - interrupts: the HLCDC interrupt definition
> > + - pinctrl-names: the pin control state names. Should contain "default",
> > +   "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
> > + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
> > +   names.
> 
> Do you need to switch between the different pinctrl configurations at 
> runtime, 
> or is the configuration selected from the panel type, which doesn't change ?

At the moment no, but if we ever need to support different devices on
the same RGB connector (actually Atmel's sama5d3xek boards have an
RGB to HDMI bridge connected on the same RGB connector) and these
devices do not support the same RGB mode (say your LCD panel supports
RGB888 and your RGB to HDMI bridge supports RGB555), then depending on
the output you select you'll have to change your pinctrl config at
runtime.

I'd say we could get rid of this runtime pinctrl config as a first step
if DT ABI stability was not required.
But it is, and I'd like to have a future proof binding to handle these
tricky cases when they occurs (if they ever do).

Anyway, I'm open to any other alternative that could let me add support
for this later on.

BTW, is there any reason for not defining an RGB connector type (I'm
currently defining HLCDC connector as an LVDS connector) ?

> 
> > + - atmel,panel: Should contain a phandle with 2 parameters.
> > +   The first cell is a phandle to a DRM panel device
> > +   The second cell encodes the RGB mode, which can take the following
> > values:
> > +   * 0: RGB444
> > +   * 1: RGB565
> > +   * 2: RGB666
> > +   * 3: RGB888
> > +   The third cell encodes specific flags describing LCD signals
> > configuration
> > +   (see Atmel's datasheet for a full description of these
> > fields):
> > +   * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
> > +   * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
> > +   * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
> > +   * bit 3: VSPDLYE: Vertical Synchronization Pulse End
> > +   * bit 4: DISPPOL: Display Signal Polarity
> > +   * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
> > +   * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
> > Configuration
> > +   * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
> > Configuration
> > +   * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time
> 
> If I'm not mistaken, those are HLCDC configuration values that depend on the 
> panel type and characteristics. Shouldn't they then be queries from the panel 
> through the drm_panel API at runtime instead of being specified in DT ? This 
> would likely require extending the drm_panel API.

HSPOL and VSPOL can be deduced from DRM_MODE_FLAG_[PN]HSYNC and
DRM_MODE_FLAG_[PN]VSYNC, I'm not sure for the other flags or the
GUARDTIME value.

Another question I had regarding these flags is whether they were LCD
panel specific or a mix of panel and board implementation.
Take the VSYNC HSYNC polarity, of course the LCD panel defines what it
expects in terms of polarity, but nothing prevents the HW designer from
inverting the VSYNC/HSYNC polarity (expect common sense :-)), right ?
A solution would be to override some drm_display_mode settings with
informations taken from the 

[PATCH 2/2] drm/radeon: add user pointer support v3

2014-07-10 Thread Christian König
From: Christian K?nig 

This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.

It imposes several restrictions upon the memory being mapped:

1. It must be page aligned (both start/end addresses, i.e ptr and size).

2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).

3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.

4. The BO is only mapped readonly for now, so no write support.

5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.

Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.

v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon.h|   4 ++
 drivers/gpu/drm/radeon/radeon_cs.c |  25 +++-
 drivers/gpu/drm/radeon/radeon_drv.c|   5 +-
 drivers/gpu/drm/radeon/radeon_gem.c|  67 +
 drivers/gpu/drm/radeon/radeon_kms.c|   1 +
 drivers/gpu/drm/radeon/radeon_object.c |   3 +
 drivers/gpu/drm/radeon/radeon_prime.c  |  10 +++
 drivers/gpu/drm/radeon/radeon_ttm.c| 107 -
 drivers/gpu/drm/radeon/radeon_vm.c |   3 +
 include/uapi/drm/radeon_drm.h  |  11 
 10 files changed, 232 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 86fdfa30..55c996e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2111,6 +2111,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void 
*data,
  struct drm_file *filp);
 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
+int radeon_gem_import_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *filp);
 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file_priv);
 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -2803,6 +2805,8 @@ extern void radeon_legacy_set_clock_gating(struct 
radeon_device *rdev, int enabl
 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int 
enable);
 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 
domain);
 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
+extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t userptr);
+extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc 
*mc, u64 base);
 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc 
*mc);
 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c 
b/drivers/gpu/drm/radeon/radeon_cs.c
index 71a1434..be65311 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -78,7 +78,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
struct radeon_cs_chunk *chunk;
struct radeon_cs_buckets buckets;
unsigned i, j;
-   bool duplicate;
+   bool duplicate, need_mmap_lock = false;
+   int r;

if (p->chunk_relocs_idx == -1) {
return 0;
@@ -164,6 +165,19 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser 
*p)
p->relocs[i].allowed_domains = domain;
}

+   if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
+   uint32_t domain = p->relocs[i].prefered_domains;
+   if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
+   DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
+ "allowed for userptr BOs\n");
+   return -EINVAL;
+   }
+   need_mmap_lock = true;
+   domain = RADEON_GEM_DOMAIN_GTT;
+   p->relocs[i].prefered_domains = domain;
+   p->relocs[i].allowed_domains = domain;
+   }
+
p->relocs[i].tv.bo = >relocs[i].robj->tbo;
p->relocs[i].handle = r->handle;

@@ -176,8 +190,15 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser 
*p)
if (p->cs_flags & RADEON_CS_USE_VM)
p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
  >validated);
+   if (need_mmap_lock)
+   down_read(>mm->mmap_sem);
+
+   r = radeon_bo_list_validate(p->rdev, >ticket, >validated, 
p->ring);

-   return radeon_bo_list_validate(p->rdev, >ticket, 

[PATCH 1/2] drm/radeon: add readonly flag to radeon_gart_set_page v2

2014-07-10 Thread Christian König
From: Christian K?nig 

v2: use flag instead of boolean

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/r100.c|  2 +-
 drivers/gpu/drm/radeon/r300.c|  8 ++--
 drivers/gpu/drm/radeon/radeon.h  | 12 +++-
 drivers/gpu/drm/radeon/radeon_asic.h |  8 
 drivers/gpu/drm/radeon/radeon_gart.c |  9 +
 drivers/gpu/drm/radeon/radeon_ttm.c  |  4 ++--
 drivers/gpu/drm/radeon/rs400.c   |  9 +++--
 drivers/gpu/drm/radeon/rs600.c   |  8 ++--
 8 files changed, 38 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index a6f7d61..fa71121d7 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -650,7 +650,7 @@ void r100_pci_gart_disable(struct radeon_device *rdev)
 }

 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
-   uint64_t addr)
+   uint64_t addr, uint32_t flags)
 {
u32 *gtt = rdev->gart.ptr;
gtt[i] = cpu_to_le32(lower_32_bits(addr));
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 8d14e66..b947f42 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -73,13 +73,17 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
 #define R300_PTE_READABLE  (1 << 3)

 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
- uint64_t addr)
+ uint64_t addr, uint32_t flags)
 {
void __iomem *ptr = rdev->gart.ptr;

addr = (lower_32_bits(addr) >> 8) |
   ((upper_32_bits(addr) & 0xff) << 24) |
-  R300_PTE_WRITEABLE | R300_PTE_READABLE;
+  R300_PTE_READABLE;
+
+   if (!(flags & RADEON_GART_PAGE_READONLY))
+   addr |= R300_PTE_WRITEABLE;
+
/* on x86 we want this to be CPU endian, on powerpc
 * on powerpc without HW swappers, it'll get swapped on way
 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c5318cac..86fdfa30 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -592,6 +592,8 @@ struct radeon_mc;
 #define RADEON_GPU_PAGE_SHIFT 12
 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & 
~RADEON_GPU_PAGE_MASK)

+#define RADEON_GART_PAGE_READONLY  1
+
 struct radeon_gart {
dma_addr_t  table_addr;
struct radeon_bo*robj;
@@ -616,7 +618,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, 
unsigned offset,
int pages);
 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 int pages, struct page **pagelist,
-dma_addr_t *dma_addr);
+dma_addr_t *dma_addr, uint32_t flags);


 /*
@@ -854,8 +856,8 @@ struct radeon_mec {
 #define R600_PTE_FRAG_256KB(6 << 7)

 /* flags used for GART page table entries on R600+ */
-#define R600_PTE_GART  ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
-   | R600_PTE_READABLE | R600_PTE_WRITEABLE)
+#define R600_PTE_GART  ( R600_PTE_VALID | R600_PTE_SYSTEM | \
+ R600_PTE_SNOOPED | R600_PTE_READABLE )

 struct radeon_vm_pt {
struct radeon_bo*bo;
@@ -1775,7 +1777,7 @@ struct radeon_asic {
struct {
void (*tlb_flush)(struct radeon_device *rdev);
void (*set_page)(struct radeon_device *rdev, unsigned i,
-uint64_t addr);
+uint64_t addr, uint32_t flags);
} gart;
struct {
int (*init)(struct radeon_device *rdev);
@@ -2703,7 +2705,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t 
v);
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), 
(state))
 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
-#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), 
(i), (p))
+#define radeon_gart_set_page(rdev, i, p, r) 
(rdev)->asic->gart.set_page((rdev), (i), (p), (r))
 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) 
((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), 
(flags)))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h 
b/drivers/gpu/drm/radeon/radeon_asic.h
index 7531b5e..f7d7c33 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -68,7 +68,7 @@ int r100_asic_reset(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
 void 

[PATCH v2 09/17] drm/radeon: use common fence implementation for fences

2014-07-10 Thread Alex Deucher
On Wed, Jul 9, 2014 at 9:23 AM, Maarten Lankhorst
 wrote:
> op 09-07-14 14:57, Deucher, Alexander schreef:
>>> 
>>> +static const char *radeon_fence_get_timeline_name(struct fence *f)
>>> +{
>>> +struct radeon_fence *fence = to_radeon_fence(f);
>>> +switch (fence->ring) {
>>> +case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
>>> +case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
>>> +case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
>>> +case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
>>> +case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
>>> +case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
>> Radeon supports vce rings on newer ascis.  Probably want to add the case for 
>> those here too.
>>
>> Alex
>>
> Indeed, how about this?

Looks good.  I'll let Christian comment on the rest of the changes.

Alex

> --8<---
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/radeon/radeon.h|  15 +--
>  drivers/gpu/drm/radeon/radeon_device.c |  60 -
>  drivers/gpu/drm/radeon/radeon_fence.c  | 225 
> +++--
>  3 files changed, 250 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 29d9cc04c04e..03a5567f2c2f 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -64,6 +64,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #include 
>  #include 
> @@ -116,9 +117,6 @@ extern int radeon_deep_color;
>  #define RADEONFB_CONN_LIMIT4
>  #define RADEON_BIOS_NUM_SCRATCH8
>
> -/* fence seq are set to this number when signaled */
> -#define RADEON_FENCE_SIGNALED_SEQ  0LL
> -
>  /* internal ring indices */
>  /* r1xx+ has gfx CP ring */
>  #define RADEON_RING_TYPE_GFX_INDEX 0
> @@ -350,12 +348,15 @@ struct radeon_fence_driver {
>  };
>
>  struct radeon_fence {
> +   struct fence base;
> +
> struct radeon_device*rdev;
> -   struct kref kref;
> /* protected by radeon_fence.lock */
> uint64_tseq;
> /* RB, DMA, etc. */
> unsignedring;
> +
> +   wait_queue_t fence_wake;
>  };
>
>  int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
> @@ -2268,6 +2269,7 @@ struct radeon_device {
> struct radeon_mman  mman;
> struct radeon_fence_driver  fence_drv[RADEON_NUM_RINGS];
> wait_queue_head_t   fence_queue;
> +   unsignedfence_context;
> struct mutexring_lock;
> struct radeon_ring  ring[RADEON_NUM_RINGS];
> boolib_pool_ready;
> @@ -2358,11 +2360,6 @@ u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 
> index);
>  void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
>
>  /*
> - * Cast helper
> - */
> -#define to_radeon_fence(p) ((struct radeon_fence *)(p))
> -
> -/*
>   * Registers read & write functions.
>   */
>  #define RREG8(reg) readb((rdev->rmmio) + (reg))
> diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
> b/drivers/gpu/drm/radeon/radeon_device.c
> index 03686fab842d..86699df7c8f3 100644
> --- a/drivers/gpu/drm/radeon/radeon_device.c
> +++ b/drivers/gpu/drm/radeon/radeon_device.c
> @@ -1213,6 +1213,7 @@ int radeon_device_init(struct radeon_device *rdev,
> for (i = 0; i < RADEON_NUM_RINGS; i++) {
> rdev->ring[i].idx = i;
> }
> +   rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
>
> DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 
> 0x%04X:0x%04X).\n",
> radeon_family_name[rdev->family], pdev->vendor, pdev->device,
> @@ -1607,6 +1608,54 @@ int radeon_resume_kms(struct drm_device *dev, bool 
> resume, bool fbcon)
> return 0;
>  }
>
> +static uint32_t radeon_gpu_mask_sw_irq(struct radeon_device *rdev)
> +{
> +   uint32_t mask = 0;
> +   int i;
> +
> +   if (!rdev->ddev->irq_enabled)
> +   return mask;
> +
> +   /*
> +* increase refcount on sw interrupts for all rings to stop
> +* enabling interrupts in radeon_fence_enable_signaling during
> +* gpu reset.
> +*/
> +
> +   for (i = 0; i < RADEON_NUM_RINGS; ++i) {
> +   if (!rdev->ring[i].ready)
> +   continue;
> +
> +   atomic_inc(>irq.ring_int[i]);
> +   mask |= 1 << i;
> +   }
> +   return mask;
> +}
> +
> +static void radeon_gpu_unmask_sw_irq(struct radeon_device *rdev, uint32_t 
> mask)
> +{
> +   unsigned long irqflags;
> +   int i;
> +
> +   if (!mask)
> +   return;
> +
> +   /*
> +* undo refcount increase, and reset irqs to correct value.
> +*/
> +
> +   for (i = 0; i < RADEON_NUM_RINGS; 

[Bug 73338] Fan speed in idle at 40% with radeonsi and at 18% with catalyst

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=73338

--- Comment #12 from Andr? Luz  ---
AMD Gigabyte 280X user here (Windforce3 model)
Fans at 40% speed for me, is very very loud. Using the 3.15 kernel in Fedora 20
with the radeonSI drivers, and the noise almost forces me to use the closed
source drivers. 

When I was back in Ubuntu and with fglrx, the fanspeed was working correctly,
it was very low (don't know how much, but maybe 10%).

When you install Windows for example and are using the WDDM drivers or default
ones, the fan speed stays around the same level (40%), which makes me believe
this is somewhat at driver level, and not Kernel.

Is there any way to reduce the speed manually, and increase it when the load
increases? (The fans ramp up with DPM already in 3.15)

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[PATCH] drm/radeon: add HDMI/DP sink description to ELD like data

2014-07-10 Thread Alex Deucher
On Wed, Jul 9, 2014 at 6:13 PM, Stefan Bruens
 wrote:
> Provide monitor name and product/manufacturer id to alsa hda driver. The 
> output
> matches the fglrx settings, short of the port_id. As the latter is not 
> standardized,
> leave it out for now.
>
> Corresponding alsa code is already in place.
>
> Signed-off-by: Stefan Br?ns 

Applied to my 3.17 tree.  thanks!

Alex

> ---
> The fglrx register settings where retrieved using Rafal Mileckis gdb script.
> After applying the patch fglrx and radeon register settings for sink info 
> match,
> short of the port_id.
>
> Regarding port id, see comment by Takashi Iwai, 14 Nov 2013:
> http://www.spinics.net/linux/fedora/alsa-user/msg12453.html
> and RFC by Stephen Warren (NVidia), 25 May 2011:
> http://lists.freedesktop.org/pipermail/xorg/2011-May/052893.html
>
>  drivers/gpu/drm/radeon/dce6_afmt.c  | 67 
> +
>  drivers/gpu/drm/radeon/evergreen_hdmi.c |  2 +
>  2 files changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c 
> b/drivers/gpu/drm/radeon/dce6_afmt.c
> index 0a65dc7..1adf95a 100644
> --- a/drivers/gpu/drm/radeon/dce6_afmt.c
> +++ b/drivers/gpu/drm/radeon/dce6_afmt.c
> @@ -273,6 +273,73 @@ void dce6_afmt_write_sad_regs(struct drm_encoder 
> *encoder)
> kfree(sads);
>  }
>
> +void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder)
> +{
> +   struct radeon_device *rdev = encoder->dev->dev_private;
> +   struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
> +   struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
> +   struct drm_connector *connector;
> +   u32 tmp = 0, offset;
> +   char description[18];
> +   uint8_t *eld;
> +
> +   if (!dig || !dig->afmt || !dig->afmt->pin)
> +   return;
> +
> +   offset = dig->afmt->pin->offset;
> +
> +   list_for_each_entry(connector, 
> >dev->mode_config.connector_list, head) {
> +   if (connector->encoder == encoder)
> +   break;
> +   }
> +
> +   if (!connector) {
> +   DRM_ERROR("Couldn't find encoder's connector\n");
> +   return;
> +   }
> +
> +   if (!connector->eld[0]) {
> +   DRM_ERROR("Connector has no ELD\n");
> +   return;
> +   }
> +
> +   eld = connector->eld;
> +
> +   tmp = MANUFACTURER_ID(eld[16]<<8 | eld[17]) | PRODUCT_ID(eld[18]<<8 | 
> eld[19]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0, tmp);
> +
> +   tmp = SINK_DESCRIPTION_LEN(strlen([20])) + 1;
> +   tmp = (tmp > 19) ? 19 : tmp;
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1, tmp);
> +
> +   strncpy(description, [20], 18);
> +
> +   tmp = PORT_ID0(0x1);
> +   //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2, tmp);
> +
> +   tmp = PORT_ID1(0x100);
> +   //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3, tmp);
> +
> +   tmp = DESCRIPTION0(description[0]) | DESCRIPTION1(description[1]) |
> + DESCRIPTION2(description[2]) | DESCRIPTION3(description[3]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4, tmp);
> +
> +   tmp = DESCRIPTION4(description[4]) | DESCRIPTION5(description[5]) |
> + DESCRIPTION6(description[6]) | DESCRIPTION7(description[7]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5, tmp);
> +
> +   tmp = DESCRIPTION8(description[8]) | DESCRIPTION9(description[9]) |
> + DESCRIPTION10(description[10]) | DESCRIPTION11(description[11]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6, tmp);
> +
> +   tmp = DESCRIPTION12(description[12]) | DESCRIPTION13(description[13]) 
> |
> + DESCRIPTION14(description[14]) | DESCRIPTION15(description[15]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7, tmp);
> +
> +   tmp = DESCRIPTION16(description[16]) | DESCRIPTION17(description[17]);
> +   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8, tmp);
> +}
> +
>  static int dce6_audio_chipset_supported(struct radeon_device *rdev)
>  {
> return !ASIC_IS_NODCE(rdev);
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 1ec0e6e..b04ec3b 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -37,6 +37,7 @@ extern void dce6_afmt_write_sad_regs(struct drm_encoder 
> *encoder);
>  extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
>  extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
>struct drm_display_mode *mode);
> +extern void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder);
>
>  /*
>   * update the N and CTS parameters for a given pixel clock rate
> @@ -425,6 +426,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, 
> struct 

[PATCH] drm/radeon: Inline r100_mm_rreg, -wreg, v3

2014-07-10 Thread Alex Deucher
On Thu, Jul 10, 2014 at 4:55 AM, Christian K?nig
 wrote:
> Am 10.07.2014 10:48, schrieb Lauri Kasanen:
>
>> On Sun, 20 Apr 2014 19:41:11 +0200
>> Christian K?nig  wrote:
>>
>>> Am 20.04.2014 19:29, schrieb Lauri Kasanen:

 This was originally un-inlined by Andi Kleen in 2011 citing size
 concerns.
 Indeed, a first attempt at inlining it grew radeon.ko by 7%.

 However, 2% of cpu is spent in this function. Simply inlining it gave 1%
 more fps
 in Urban Terror.

 v2: We know the minimum MMIO size. Adding it to the if allows the
 compiler to
 optimize the branch out, improving both performance and size.

 The v2 patch decreases radeon.ko size by 2%. I didn't re-benchmark, but
 common sense
 says perf is now more than 1% better.

 v3: Also change _wreg, make the threshold a define.

 Inlining _wreg increased the size a bit compared to v2, so now radeon.ko
 is only 1% smaller.

 Signed-off-by: Lauri Kasanen 
>>>
>>> Reviewed-by: Christian K?nig 
>>
>> Ping. Although reviewed in April, seems this wasn't applied to any tree?
>
>
> Sorry looks like I missed it. Alex can you pull that in your 3.17 branch?

Applied.  thanks.

Alex


[RESEND PATCH v3 06/11] drm: add DT bindings documentation for atmel-hlcdc-dc driver

2014-07-10 Thread Laurent Pinchart
Hi Boris,

Thank you for the patch.

On Monday 07 July 2014 18:42:59 Boris BREZILLON wrote:
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
> 
> The HLCDC block provides a single RGB output port, and only supports LCD
> panels connection to LCD panels for now.
> 
> The atmel,panel property link the HLCDC RGB output with the LCD panel
> connected on this port (note that the HLCDC RGB connector implementation
> makes use of the DRM panel framework).
> 
> Connection to other external devices (DRM bridges) might be added later by
> mean of a new atmel,xxx (atmel,bridge) property.
> 
> Signed-off-by: Boris BREZILLON 
> ---
>  .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 +++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> 
> diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt new file mode
> 100644
> index 000..594bdb2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> @@ -0,0 +1,59 @@
> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
> +
> +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
> +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
> +
> +Required properties:
> + - compatible: value should be one of the following:
> +   "atmel,hlcdc-dc"
> + - interrupts: the HLCDC interrupt definition
> + - pinctrl-names: the pin control state names. Should contain "default",
> +   "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
> + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
> +   names.

Do you need to switch between the different pinctrl configurations at runtime, 
or is the configuration selected from the panel type, which doesn't change ?

> + - atmel,panel: Should contain a phandle with 2 parameters.
> +   The first cell is a phandle to a DRM panel device
> +   The second cell encodes the RGB mode, which can take the following
> values:
> +   * 0: RGB444
> +   * 1: RGB565
> +   * 2: RGB666
> +   * 3: RGB888
> +   The third cell encodes specific flags describing LCD signals
> configuration
> +   (see Atmel's datasheet for a full description of these
> fields):
> +   * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
> +   * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
> +   * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
> +   * bit 3: VSPDLYE: Vertical Synchronization Pulse End
> +   * bit 4: DISPPOL: Display Signal Polarity
> +   * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
> +   * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
> Configuration
> +   * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
> Configuration
> +   * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time

If I'm not mistaken, those are HLCDC configuration values that depend on the 
panel type and characteristics. Shouldn't they then be queries from the panel 
through the drm_panel API at runtime instead of being specified in DT ? This 
would likely require extending the drm_panel API.

> +
> +Example:
> +
> + hlcdc: hlcdc at f003 {
> + compatible = "atmel,sama5d3-hlcdc";
> + reg = <0xf003 0x2000>;
> + clocks = <_clk>, <>, <>;
> + clock-names = "periph_clk","sys_clk", "slow_clk";
> + status = "disabled";
> +
> + hlcdc-display-controller {
> + compatible = "atmel,hlcdc-dc";
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + pinctrl-names = "default", "rgb-444", "rgb-565", 
> "rgb-666", 
"rgb-888";
> + pinctrl-0 = <_lcd_base>;
> + pinctrl-1 = <_lcd_base _lcd_rgb444>;
> + pinctrl-2 = <_lcd_base _lcd_rgb565>;
> + pinctrl-3 = <_lcd_base _lcd_rgb666>;
> + pinctrl-4 = <_lcd_base _lcd_rgb888>;
> + };
> +
> + hlcdc_pwm: hlcdc-pwm {
> + compatible = "atmel,hlcdc-pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <_lcd_pwm>;
> + #pwm-cells = <3>;
> + };
> + };

-- 
Regards,

Laurent Pinchart



[PATCH 2/2] drm/radeon: consolidate vga and dvi get_modes functions (v2)

2014-07-10 Thread Alex Deucher
They are identical.

v2: rebase

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 14 +-
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 88e3ffe..08a6fbd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1051,18 +1051,6 @@ static const struct drm_connector_funcs 
radeon_tv_connector_funcs = {
.set_property = radeon_connector_set_property,
 };

-static int radeon_dvi_get_modes(struct drm_connector *connector)
-{
-   struct radeon_connector *radeon_connector = 
to_radeon_connector(connector);
-   int ret;
-
-   ret = radeon_ddc_get_modes(radeon_connector);
-
-   radeon_get_native_mode(connector);
-
-   return ret;
-}
-
 static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector)
 {
struct drm_device *dev = connector->dev;
@@ -1365,7 +1353,7 @@ static int radeon_dvi_mode_valid(struct drm_connector 
*connector,
 }

 static const struct drm_connector_helper_funcs 
radeon_dvi_connector_helper_funcs = {
-   .get_modes = radeon_dvi_get_modes,
+   .get_modes = radeon_vga_get_modes,
.mode_valid = radeon_dvi_mode_valid,
.best_encoder = radeon_dvi_encoder,
 };
-- 
1.8.3.1



[PATCH 1/2] drm/radeon: enable display scaling on all connectors (v2)

2014-07-10 Thread Alex Deucher
This enables the display scaler on all connectors for r5xx
and newer asics.  Previously we only enabled the scaler for
fixed mode displays (eDP or LVDS) since they have to use the
scaler to support non-native modes.  Most other displays
are multi-sync or have a built in scaler to support non-native
modes.  The default scaling mode for non-fixed displays is
none which will use the scaler in the monitor.  Note that
we do not populate any fake modes like we do for fixed
displays so it will only use the modes in the edid.  For
other modes, you'll need to populate them manually.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=80868

v2: properly handle scaling with no modes defined

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_encoders.c |  10 +--
 drivers/gpu/drm/radeon/radeon_connectors.c | 106 -
 2 files changed, 95 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c 
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 2b29084..f27f0f7 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -327,12 +327,10 @@ static bool radeon_atom_mode_fixup(struct drm_encoder 
*encoder,
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay 
+ 2;

-   /* get the native mode for LVDS */
-   if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
+   /* get the native mode for scaling */
+   if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
radeon_panel_mode_fixup(encoder, adjusted_mode);
-
-   /* get the native mode for TV */
-   if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
+   } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
struct radeon_encoder_atom_dac *tv_dac = 
radeon_encoder->enc_priv;
if (tv_dac) {
if (tv_dac->tv_std == TV_STD_NTSC ||
@@ -342,6 +340,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder 
*encoder,
else
radeon_atom_get_tv_timings(rdev, 1, 
adjusted_mode);
}
+   } else if (radeon_encoder->rmx_type != RMX_OFF) {
+   radeon_panel_mode_fixup(encoder, adjusted_mode);
}

if (ASIC_IS_DCE3(rdev) &&
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 4483119..88e3ffe 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -285,6 +285,27 @@ static struct drm_encoder 
*radeon_best_single_encoder(struct drm_connector *conn
return NULL;
 }

+static void radeon_get_native_mode(struct drm_connector *connector)
+{
+   struct drm_encoder *encoder = radeon_best_single_encoder(connector);
+   struct radeon_encoder *radeon_encoder;
+
+   if (encoder == NULL)
+   return;
+
+   radeon_encoder = to_radeon_encoder(encoder);
+
+   if (!list_empty(>probed_modes)) {
+   struct drm_display_mode *preferred_mode =
+   list_first_entry(>probed_modes,
+struct drm_display_mode, head);
+
+   radeon_encoder->native_mode = *preferred_mode;
+   } else {
+   radeon_encoder->native_mode.clock = 0;
+   }
+}
+
 /*
  * radeon_connector_analog_encoder_conflict_solve
  * - search for other connectors sharing this encoder
@@ -585,6 +606,35 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
radeon_property_change_mode(_encoder->base);
}

+   if (property == dev->mode_config.scaling_mode_property) {
+   enum radeon_rmx_type rmx_type;
+
+   if (connector->encoder)
+   radeon_encoder = to_radeon_encoder(connector->encoder);
+   else {
+   struct drm_connector_helper_funcs *connector_funcs = 
connector->helper_private;
+   radeon_encoder = 
to_radeon_encoder(connector_funcs->best_encoder(connector));
+   }
+
+   switch (val) {
+   default:
+   case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
+   case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
+   case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
+   case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
+   }
+   if (radeon_encoder->rmx_type == rmx_type)
+   return 0;
+
+   if ((rmx_type != DRM_MODE_SCALE_NONE) &&
+   (radeon_encoder->native_mode.clock == 0))
+   return 0;
+
+   radeon_encoder->rmx_type = rmx_type;
+
+   radeon_property_change_mode(_encoder->base);
+   }
+
   

[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=72921

--- Comment #31 from Kertesz Laszlo  ---
I had some more reboots, some when the computer was idling. Now i reverted the
patch and rebuilt the kernel, let's see if it will help.

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[Bug 78661] GPU sometimes locks up after boot and/or resume

2014-07-10 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=78661

--- Comment #12 from Alex Deucher  ---
Make sure you power off completely before testing the new patch rather than
just a warm reboot to make sure the old register state is not retained.

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[PATCH 2/3] drm/radeon: add readonly flag to radeon_gart_set_page

2014-07-10 Thread Christian König
Am 09.07.2014 22:01, schrieb Alex Deucher:
> On Wed, Jul 9, 2014 at 2:15 PM, Christian K?nig  
> wrote:
>> [SNIP]
>
> I think it would be better to add a page_flags parameter rather than a
> boolean for each attribute.  At some point we may want write-only or
> non-snooped.
Yeah, I know. Just wanted to hack it down to get an opinion from Jerome 
on the other patch.

A cleaned up version will follow today,
Christian.



[Bug 73053] dpm hangs with BTC parts

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=73053

--- Comment #36 from Alex Deucher  ---
(In reply to comment #34)
> Hi,
> Same issue with my system on motherboard MSI A78M-E35 with AMD APU A4-5300.
> But my system reboots some 3 seconds after initramfs is loaded. So no Xorg
> and no logs.
> 

You have an APU.  This bug is specifically about dpm on BTC discrete GPUs.  It
sounds like you are seeing bug 72921.  Please try the patch on that bug.

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[PATCH 0/3] drm/gk20a: support for reclocking

2014-07-10 Thread Mikko Perttunen
Does GK20A itself have any kind of thermal protection capabilities? 
Upstream SOCTHERM support is not yet available (though I have a driver 
in my tree), so we are thinking of disabling CPU DVFS on boards that 
don't have always-on active cooling for now. Same might be necessary for 
GPU as well.

On 10/07/14 10:34, Alexandre Courbot wrote:
> This series adds support for reclocking on GK20A. The first two patches touch
> the clock subsystem to allow GK20A to operate, by making the presence of the
> thermal and voltage devices optional, and allowing pstates to be provided
> directly instead of being probed using the BIOS (which Tegra does not have).
>
> The last patch adds the GK20A clock device. Arguably the clock can be seen as 
> a
> stripped-down version of what is seen on NVE0, however instead of using NVE0
> support has been written from scratch using the ChromeOS kernel as a basis.
> There are several reasons for this:
>
> - The ChromeOS driver uses a lookup table for the P coefficient which I could
>not find in the NVE0 driver,
> - Some registers that NVE0 expects to find are not present on GK20A (e.g.
>0x137120 and 0x137140),
> - Calculation of MNP is done differently from what is performed in
>nva3_pll_calc(), and it might be interesting to compare the two methods,
> - All the same, the programming sequence is done differently in the ChromeOS
>driver and NVE0 could possibly benefit from it (?)
>
> It would be interesting to try and merge both, but for now I prefer to have 
> the
> two coexisting to ensure proper operation on GK20A and besure I don't break
> dGPU support. :)
>
> Regarding the first patch, one might argue that I could as well add thermal
> and voltage devices to GK20A. The reason this is not done is because these
> currently depend heavily on the presence of a BIOS, and will require a rework
> similar to that done in patch 2 for clocks. I would like to make sure this
> approach is approved because applying it to other subdevs.
>
> Alexandre Courbot (3):
>drm/nouveau/clk: make therm and volt devices optional
>drm/nouveau/clk: support for non-BIOS pstates
>drm/gk20a: reclocking support
>
>   drivers/gpu/drm/nouveau/Makefile   |   1 +
>   drivers/gpu/drm/nouveau/core/engine/device/nve0.c  |   1 +
>   .../gpu/drm/nouveau/core/include/subdev/clock.h|   9 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/base.c   |  52 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c  | 670 
> +
>   drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c   |   4 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c   |   4 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c   |   2 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c   |   4 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c   |   4 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c   |   4 +-
>   drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c   |   4 +-
>   12 files changed, 725 insertions(+), 34 deletions(-)
>   create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
>


[Bug 66963] Rv6xx dpm problems

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=66963

--- Comment #234 from Paul Bodenbenner  ---
Just want to note:
Still about every 10 time of booting or waking up from suspend an / the hard
freeze occurs with an up-to-date Arch Linux installation.

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[PATCH 0/3] drm/gk20a: support for reclocking

2014-07-10 Thread Peter De Schrijver
On Thu, Jul 10, 2014 at 09:34:34AM +0200, Alexandre Courbot wrote:
> This series adds support for reclocking on GK20A. The first two patches touch
> the clock subsystem to allow GK20A to operate, by making the presence of the
> thermal and voltage devices optional, and allowing pstates to be provided
> directly instead of being probed using the BIOS (which Tegra does not have).
> 
> The last patch adds the GK20A clock device. Arguably the clock can be seen as 
> a
> stripped-down version of what is seen on NVE0, however instead of using NVE0
> support has been written from scratch using the ChromeOS kernel as a basis.
> There are several reasons for this:
> 
> - The ChromeOS driver uses a lookup table for the P coefficient which I could
>   not find in the NVE0 driver,
> - Some registers that NVE0 expects to find are not present on GK20A (e.g.
>   0x137120 and 0x137140),
> - Calculation of MNP is done differently from what is performed in
>   nva3_pll_calc(), and it might be interesting to compare the two methods,
> - All the same, the programming sequence is done differently in the ChromeOS
>   driver and NVE0 could possibly benefit from it (?)
> 
> It would be interesting to try and merge both, but for now I prefer to have 
> the
> two coexisting to ensure proper operation on GK20A and besure I don't break
> dGPU support. :)
> 
> Regarding the first patch, one might argue that I could as well add thermal
> and voltage devices to GK20A. The reason this is not done is because these
> currently depend heavily on the presence of a BIOS, and will require a rework
> similar to that done in patch 2 for clocks. I would like to make sure this
> approach is approved because applying it to other subdevs.

I think this should use CCF so we can use pre and post rate change notifiers
to hookup vdd_gpu DVS.

Thanks,

Peter.


drm/vmwgfx: Fix compat shader namespace

2014-07-10 Thread Dan Carpenter
On Wed, Jul 09, 2014 at 11:31:45PM +0200, Thomas Hellstr?m wrote:
> >Speaking of verbose, all the likely/unlikely annotations should be
> >removed.
> 
> Is this your personal opinion or has there been some kind of kernel
> developer agreement not to add this annotation and remove it from
> the kernel tree? If not, I prefer to keep it.

It obviously makes the code less readable.  It makes a small speedup if
the code is called 1 times with the and the expected value is true
every time.  If more than 1 out of 1 values is unexpected then it is
a slow down.

There are two rules of thumb for likely/unlikely:

1) Don't use it in the drivers/ directory.
2) Or don't use it without benchmarking it.

These are general rules, not mine.

In the olden days we used to use it more often but then people did
benchmarking and likely/unlikely annotations didn't make a single
measurable difference on normal benchmarks at all.  Maybe on a micro
benchmark.  Also perhaps in those days people hadn't done branch
profiling so we were getting a lot of unexpected conditions and the slow
downs were canceling the speed ups.

regards,
dan carpenter



[Bug 73053] dpm hangs with BTC parts

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=73053

--- Comment #35 from Rpnpif  ---
(In reply to comment #34)

I have trying some minutes ago 3.14.12 kernel that have your patches included,
I think. But same issue : the system reboots early in the sequence boot.

Or my bug is different or it is the same and your patches does not fix it. Only
radeon.dpm=0 on the kernel command line fix it.

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[PATCH 1/1] drm/tilcdc: Fix build breakage

2014-07-10 Thread Thomas Wood
On 10 July 2014 10:16, Dave Airlie  wrote:
> On 10 July 2014 17:09, Daniel Vetter  wrote:
>> On Thu, Jul 10, 2014 at 12:02:15PM +1000, Dave Airlie wrote:
>>> On 9 July 2014 21:42, Sachin Kamat  wrote:
>>> > Commit 34ea3d386347 ("drm: add register and unregister functions
>>> > for connectors") probably missed out converting the
>>> > drm_sysfs_connector_remove instances in the following files.
>>> > Without this patch we get the following compilation error:
>>> > ERROR: "drm_sysfs_connector_remove" [drivers/gpu/drm/tilcdc/tilcdc.ko] 
>>> > undefined!
>>> >
>>> > Signed-off-by: Sachin Kamat 
>>> > CC: Thomas Wood 
>>> > CC: David Herrmann 
>>> > CC: Daniel Vetter 
>>> > ---
>>> > Only compile tested.
>>>
>>> Oops, applied thanks,
>>>
>>> I did an arm build just on the drm dir, forgot to let it run to
>>> completion over the whole tree.
>>
>> Yeah, my apologies for breaking things. Nowadays I rely on the 0-day
>> builder for arm build testing, dunno why it didn't report this one here.
>> Might be good to check with Wu Fengguang that your driver is included - he
>> tends to catch other drm breakage on arm drivers well.

It actually looks like the calls to drm_sysfs_connector_remove were
added after the patch to remove it was applied:

16dcbde drm/tilcdc: tfp410: fix dangling sysfs connector node
daa15b4 drm/tilcdc: slave: fix dangling sysfs connector node
e396900 drm/tilcdc: panel: fix dangling sysfs connector node

This probably explains why it wasn't reported from the builder on the
original patch.


>
> I just got the report now :-) after I fixed it!
>
> Dave.


[PATCH 1/1] drm/tilcdc: Fix build breakage

2014-07-10 Thread Dave Airlie
On 9 July 2014 21:42, Sachin Kamat  wrote:
> Commit 34ea3d386347 ("drm: add register and unregister functions
> for connectors") probably missed out converting the
> drm_sysfs_connector_remove instances in the following files.
> Without this patch we get the following compilation error:
> ERROR: "drm_sysfs_connector_remove" [drivers/gpu/drm/tilcdc/tilcdc.ko] 
> undefined!
>
> Signed-off-by: Sachin Kamat 
> CC: Thomas Wood 
> CC: David Herrmann 
> CC: Daniel Vetter 
> ---
> Only compile tested.

Oops, applied thanks,

I did an arm build just on the drm dir, forgot to let it run to
completion over the whole tree.

Dave.


[RFC] dma-buf: Implement test module

2014-07-10 Thread Thierry Reding
On Wed, Mar 26, 2014 at 09:32:47AM +0100, Thierry Reding wrote:
> On Tue, Mar 25, 2014 at 07:01:10PM +0100, Sam Ravnborg wrote:
> > > 
> > > There are two things that don't work too well with this. First this
> > > causes the build to break if the build machine doesn't have the new
> > > public header (include/uapi/linux/dma-buf.h) installed yet. So the only
> > > way to make this work would be by building the kernel once with SAMPLES
> > > disabled, install the headers and then build again with SAMPLES enabled.
> > > Which really isn't very nice.
> > > 
> > > One other option that I've tried is to modify the include path so that
> > > the test program would get the in-tree copy of the public header file,
> > > but that didn't build properly either because the header files aren't
> > > properly sanitized and therefore the compiler complains about it
> > > (include/uapi/linux/types.h).
> > > 
> > > One other disadvantage of carrying the sample program in the tree is
> > > that there's only infrastructure to build programs natively on the build
> > > machine. That's somewhat unfortunate because if you want to run the test
> > > program on a different architecture you have to either compile the
> > > kernel natively on that architecture (which isn't very practical on many
> > > embedded devices) or cross-compile manually.
> > > 
> > > I think a much nicer solution would be to add infrastructure to cross-
> > > compile these test programs, so that they end up being built for the
> > > same architecture as the kernel image (i.e. using CROSS_COMPILE).
> > > 
> > > Adding Michal and the linux-kbuild mailing list, perhaps this has been
> > > discussed before, or maybe somebody has a better idea on how to solve
> > > this.
> > I actually looked into this some time ago.
> > May try to dust off the patch.
> > IIRC the kernel provided headers were used for building - not the one 
> > installed on the machine.
> > And crosscompile were supported.
> 
> That sounds exactly like what I'd want for this. If you need any help,
> please let me know.

Did you have any time to look into dusting off the patch? If not I'll
gladly take whatever you have and dust it off myself.

Thierry
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[PATCH] drm/radeon: Inline r100_mm_rreg, -wreg, v3

2014-07-10 Thread Lauri Kasanen
On Sun, 20 Apr 2014 19:41:11 +0200
Christian K?nig  wrote:

> Am 20.04.2014 19:29, schrieb Lauri Kasanen:
> > This was originally un-inlined by Andi Kleen in 2011 citing size concerns.
> > Indeed, a first attempt at inlining it grew radeon.ko by 7%.
> >
> > However, 2% of cpu is spent in this function. Simply inlining it gave 1% 
> > more fps
> > in Urban Terror.
> >
> > v2: We know the minimum MMIO size. Adding it to the if allows the compiler 
> > to
> > optimize the branch out, improving both performance and size.
> >
> > The v2 patch decreases radeon.ko size by 2%. I didn't re-benchmark, but 
> > common sense
> > says perf is now more than 1% better.
> >
> > v3: Also change _wreg, make the threshold a define.
> >
> > Inlining _wreg increased the size a bit compared to v2, so now radeon.ko
> > is only 1% smaller.
> >
> > Signed-off-by: Lauri Kasanen 
> 
> Reviewed-by: Christian K?nig 

Ping. Although reviewed in April, seems this wasn't applied to any tree?

- Lauri


[pull] radeon drm-fixes-3.16

2014-07-10 Thread Alex Deucher
Hi Dave,

Mostly fixes to fallout from the pageflipping changes in 3.16.  The
rest are dpm and display fixes and a boot hang fix.

The following changes since commit 2db38e06ecda80063d748df7bd79b7186c8831e0:

  Merge tag 'drm-intel-fixes-2014-07-09' of 
git://anongit.freedesktop.org/drm-intel into drm-fixes (2014-07-10 10:10:06 
+1000)

are available in the git repository at:


  git://people.freedesktop.org/~agd5f/linux drm-fixes-3.16

for you to fetch changes up to cb2416af027a334ba62f49042386686fcf5b7425:

  drm/radeon/dpm: Reenabling SS on Cayman (2014-07-10 09:31:38 -0400)


Alex Deucher (3):
  drm/radeon/dp: return -EIO for flags not zero case
  drm/radeon: fix typo in golden register setup on evergreen
  drm/radeon: fix typo in ci_stop_dpm()

Alexandre Demers (1):
  drm/radeon/dpm: Reenabling SS on Cayman

Christian K?nig (1):
  drm/radeon: only print meaningful VM faults

Michel D?nzer (3):
  drm/radeon: Program page flips to execute in hblank instead of vblank
  drm/radeon: Move pinning the BO back to radeon_crtc_page_flip()
  drm/radeon: Complete page flip even if waiting on the BO fence fails

 drivers/gpu/drm/radeon/atombios_crtc.c  |  28 ++--
 drivers/gpu/drm/radeon/atombios_dp.c|   2 +-
 drivers/gpu/drm/radeon/ci_dpm.c |   2 +-
 drivers/gpu/drm/radeon/cik.c|  64 ++---
 drivers/gpu/drm/radeon/evergreen.c  | 100 +++--
 drivers/gpu/drm/radeon/r100.c   |  48 ++-
 drivers/gpu/drm/radeon/r600.c   |  18 +--
 drivers/gpu/drm/radeon/radeon.h |   5 +-
 drivers/gpu/drm/radeon/radeon_asic.c|  22 ---
 drivers/gpu/drm/radeon/radeon_asic.h|   4 -
 drivers/gpu/drm/radeon/radeon_display.c | 243 +---
 drivers/gpu/drm/radeon/radeon_mode.h|   3 +-
 drivers/gpu/drm/radeon/rs600.c  |  28 +---
 drivers/gpu/drm/radeon/rv770.c  |  24 +---
 drivers/gpu/drm/radeon/rv770_dpm.c  |   6 -
 drivers/gpu/drm/radeon/si.c |  58 ++--
 16 files changed, 172 insertions(+), 483 deletions(-)


[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

2014-07-10 Thread Inki Dae
On 2014? 07? 10? 10:20, Inki Dae wrote:
> On 2014? 07? 10? 10:06, YoungJun Cho wrote:
>> On 07/10/2014 12:22 AM, Thierry Reding wrote:
>>> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
 To support LCD I80 interface, the DSI host calls this function
 to notify the panel tearing effect synchronization signal to
 the CRTC device manager to trigger to transfer video image.

 Signed-off-by: YoungJun Cho 
 Acked-by: Inki Dae 
 Acked-by: Kyungmin Park 
 ---
   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
   include/drm/drm_mipi_dsi.h  |  7 +++
   2 files changed, 18 insertions(+)

 diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
 b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
 index dad543a..76e34ca 100644
 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
 +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
 @@ -24,6 +24,7 @@
   #include 
   #include 

 +#include "exynos_drm_crtc.h"
   #include "exynos_drm_drv.h"

   /* returns true iff both arguments logically differs */
 @@ -1041,10 +1042,20 @@ static ssize_t
 exynos_dsi_host_transfer(struct mipi_dsi_host *host,
   return (ret < 0) ? ret : xfer.rx_done;
   }

 +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
 +{
 +struct exynos_dsi *dsi = host_to_dsi(host);
 +struct drm_encoder *encoder = dsi->encoder;
 +
 +if (dsi->state & DSIM_STATE_ENABLED)
 +exynos_drm_crtc_te_handler(encoder->crtc);
 +}
 +
   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
   .attach = exynos_dsi_host_attach,
   .detach = exynos_dsi_host_detach,
   .transfer = exynos_dsi_host_transfer,
 +.pass_te = exynos_dsi_host_pass_te,
   };

   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
 diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
 index 944f33f..3f21bea 100644
 --- a/include/drm/drm_mipi_dsi.h
 +++ b/include/drm/drm_mipi_dsi.h
 @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of
 received bytes,
*   or error
 + * @pass_te: call the crtc te_handler() callback from DSI host.
 + * The panel generates tearing effect synchronization signal
 between
 + * MCU and FB to display video images. And the display
 controller
 + * should trigger to transfer video image at this signal. So
 the panel
 + * receives the TE IRQ, then calls this function to notify
 it to the
 + * display controller.
*/
   struct mipi_dsi_host_ops {
   int (*attach)(struct mipi_dsi_host *host,
 @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
 struct mipi_dsi_device *dsi);
   ssize_t (*transfer)(struct mipi_dsi_host *host,
   struct mipi_dsi_msg *msg);
 +void (*pass_te)(struct mipi_dsi_host *host);
>>>
>>> I've objected to this particular change before and that objection still
>>> stands. I don't see how this is related to DSI. It seems like an
>>> implementation detail of this particular setup and I think it should be
>>> handled differently (within the Exynos DSI controller implementation
>>> possibly).
>>>
>>
>> Okay, I understand what you mean.
>> As you know, this function is called by panel TE interrupt handler, so
>> it could be accessed by panel.
>> Do you have any good idea for panel to access exynos_drm_dsi directly
>> without mipi_dis_host_ops?
>>
> 
> Mr. Cho, let's just use notifier callback for the meantime: fimd driver
> registers a te handler to Exynos mipi dsi driver, and then Exynos mipi
> dsi driver calls the te handler when te interrupt occurs from Panel device.
> 

Again, there was my missing point. there wouldn't be way that Exynos
mipi dsi driver can receive te signal from panel without mipi_dsi_host_ops.

So let's use remote-endpoint property of DSI device node. DSI driver can
get te gpio from Panel node, and can register te irq handler in case of
i80 Panel. After that, te signal could be notified from te interrupt
handler of DSI driver to FIMD driver through notifier callback
registered already.

Thanks,
Inki Dae

> I think all we can consider for it is to use mipi_dsi_host_ops or core
> framework - connector/encoder and crtc. However, it seems that it's not
> really easy for we have a consensus with other maintainers until other
> i80 users appear and they need common something for it.
> 
> 
> Thanks,
> Inki Dae
> 
>> Thank you.
>> Best regards YJ
>>
>>> Laurent also asked you to split this up into two patches, one for the
>>> core part, the other for the Exynos driver parts, yet this patch
>>> contains both changes.
>>>
>>> Thierry
>>>
>>
>>
> 
> ___

[PATCH] drm/radeon: Inline r100_mm_rreg, -wreg, v3

2014-07-10 Thread Christian König
Am 10.07.2014 10:48, schrieb Lauri Kasanen:
> On Sun, 20 Apr 2014 19:41:11 +0200
> Christian K?nig  wrote:
>
>> Am 20.04.2014 19:29, schrieb Lauri Kasanen:
>>> This was originally un-inlined by Andi Kleen in 2011 citing size concerns.
>>> Indeed, a first attempt at inlining it grew radeon.ko by 7%.
>>>
>>> However, 2% of cpu is spent in this function. Simply inlining it gave 1% 
>>> more fps
>>> in Urban Terror.
>>>
>>> v2: We know the minimum MMIO size. Adding it to the if allows the compiler 
>>> to
>>> optimize the branch out, improving both performance and size.
>>>
>>> The v2 patch decreases radeon.ko size by 2%. I didn't re-benchmark, but 
>>> common sense
>>> says perf is now more than 1% better.
>>>
>>> v3: Also change _wreg, make the threshold a define.
>>>
>>> Inlining _wreg increased the size a bit compared to v2, so now radeon.ko
>>> is only 1% smaller.
>>>
>>> Signed-off-by: Lauri Kasanen 
>> Reviewed-by: Christian K?nig 
> Ping. Although reviewed in April, seems this wasn't applied to any tree?

Sorry looks like I missed it. Alex can you pull that in your 3.17 branch?

Thanks,
Christian.

>
> - Lauri



[PATCH 2/2] drm/radeon: add user pointer support v3

2014-07-10 Thread Jerome Glisse
On Thu, Jul 10, 2014 at 09:48:49AM -0400, Alex Deucher wrote:
> On Thu, Jul 10, 2014 at 8:33 AM, Christian K?nig
>  wrote:
> > From: Christian K?nig 
> >
> > This patch adds an IOCTL for turning a pointer supplied by
> > userspace into a buffer object.
> >
> > It imposes several restrictions upon the memory being mapped:
> >
> > 1. It must be page aligned (both start/end addresses, i.e ptr and size).
> >
> > 2. It must be normal system memory, not a pointer into another map of IO
> > space (e.g. it must not be a GTT mmapping of another object).
> >
> > 3. The BO is mapped into GTT, so the maximum amount of memory mapped at
> > all times is still the GTT limit.
> >
> > 4. The BO is only mapped readonly for now, so no write support.
> >
> > 5. List of backing pages is only acquired once, so they represent a
> > snapshot of the first use.
> >
> > Exporting and sharing as well as mapping of buffer objects created by
> > this function is forbidden and results in an -EPERM.
> >
> > v2: squash all previous changes into first public version
> > v3: fix tabs, map readonly, don't use MM callback any more
> >
> > Signed-off-by: Christian K?nig 
> 
> Reviewed-by: Alex Deucher 

Well i am not oppose to userptr even if i dislike it and this version
do not have the crazy mmu_notifier thing so.

Reviewed-by: J?r?me Glisse 

> 
> > ---
> >  drivers/gpu/drm/radeon/radeon.h|   4 ++
> >  drivers/gpu/drm/radeon/radeon_cs.c |  25 +++-
> >  drivers/gpu/drm/radeon/radeon_drv.c|   5 +-
> >  drivers/gpu/drm/radeon/radeon_gem.c|  67 +
> >  drivers/gpu/drm/radeon/radeon_kms.c|   1 +
> >  drivers/gpu/drm/radeon/radeon_object.c |   3 +
> >  drivers/gpu/drm/radeon/radeon_prime.c  |  10 +++
> >  drivers/gpu/drm/radeon/radeon_ttm.c| 107 
> > -
> >  drivers/gpu/drm/radeon/radeon_vm.c |   3 +
> >  include/uapi/drm/radeon_drm.h  |  11 
> >  10 files changed, 232 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon.h 
> > b/drivers/gpu/drm/radeon/radeon.h
> > index 86fdfa30..55c996e 100644
> > --- a/drivers/gpu/drm/radeon/radeon.h
> > +++ b/drivers/gpu/drm/radeon/radeon.h
> > @@ -2111,6 +2111,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, 
> > void *data,
> >   struct drm_file *filp);
> >  int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *filp);
> > +int radeon_gem_import_ioctl(struct drm_device *dev, void *data,
> > +   struct drm_file *filp);
> >  int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
> >  struct drm_file *file_priv);
> >  int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
> > @@ -2803,6 +2805,8 @@ extern void radeon_legacy_set_clock_gating(struct 
> > radeon_device *rdev, int enabl
> >  extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int 
> > enable);
> >  extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 
> > domain);
> >  extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
> > +extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t userptr);
> > +extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
> >  extern void radeon_vram_location(struct radeon_device *rdev, struct 
> > radeon_mc *mc, u64 base);
> >  extern void radeon_gtt_location(struct radeon_device *rdev, struct 
> > radeon_mc *mc);
> >  extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool 
> > fbcon);
> > diff --git a/drivers/gpu/drm/radeon/radeon_cs.c 
> > b/drivers/gpu/drm/radeon/radeon_cs.c
> > index 71a1434..be65311 100644
> > --- a/drivers/gpu/drm/radeon/radeon_cs.c
> > +++ b/drivers/gpu/drm/radeon/radeon_cs.c
> > @@ -78,7 +78,8 @@ static int radeon_cs_parser_relocs(struct 
> > radeon_cs_parser *p)
> > struct radeon_cs_chunk *chunk;
> > struct radeon_cs_buckets buckets;
> > unsigned i, j;
> > -   bool duplicate;
> > +   bool duplicate, need_mmap_lock = false;
> > +   int r;
> >
> > if (p->chunk_relocs_idx == -1) {
> > return 0;
> > @@ -164,6 +165,19 @@ static int radeon_cs_parser_relocs(struct 
> > radeon_cs_parser *p)
> > p->relocs[i].allowed_domains = domain;
> > }
> >
> > +   if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
> > +   uint32_t domain = p->relocs[i].prefered_domains;
> > +   if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
> > +   DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
> > + "allowed for userptr BOs\n");
> > +   return -EINVAL;
> > +   }
> > +   need_mmap_lock = true;
> > +   domain = RADEON_GEM_DOMAIN_GTT;
> > +   

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

2014-07-10 Thread Inki Dae
On 2014? 07? 10? 10:06, YoungJun Cho wrote:
> On 07/10/2014 12:22 AM, Thierry Reding wrote:
>> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>>> To support LCD I80 interface, the DSI host calls this function
>>> to notify the panel tearing effect synchronization signal to
>>> the CRTC device manager to trigger to transfer video image.
>>>
>>> Signed-off-by: YoungJun Cho 
>>> Acked-by: Inki Dae 
>>> Acked-by: Kyungmin Park 
>>> ---
>>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>>   include/drm/drm_mipi_dsi.h  |  7 +++
>>>   2 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> index dad543a..76e34ca 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> @@ -24,6 +24,7 @@
>>>   #include 
>>>   #include 
>>>
>>> +#include "exynos_drm_crtc.h"
>>>   #include "exynos_drm_drv.h"
>>>
>>>   /* returns true iff both arguments logically differs */
>>> @@ -1041,10 +1042,20 @@ static ssize_t
>>> exynos_dsi_host_transfer(struct mipi_dsi_host *host,
>>>   return (ret < 0) ? ret : xfer.rx_done;
>>>   }
>>>
>>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>>> +{
>>> +struct exynos_dsi *dsi = host_to_dsi(host);
>>> +struct drm_encoder *encoder = dsi->encoder;
>>> +
>>> +if (dsi->state & DSIM_STATE_ENABLED)
>>> +exynos_drm_crtc_te_handler(encoder->crtc);
>>> +}
>>> +
>>>   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>>   .attach = exynos_dsi_host_attach,
>>>   .detach = exynos_dsi_host_detach,
>>>   .transfer = exynos_dsi_host_transfer,
>>> +.pass_te = exynos_dsi_host_pass_te,
>>>   };
>>>
>>>   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>>> index 944f33f..3f21bea 100644
>>> --- a/include/drm/drm_mipi_dsi.h
>>> +++ b/include/drm/drm_mipi_dsi.h
>>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>>* @detach: detach DSI device from DSI host
>>>* @transfer: send and/or receive DSI packet, return number of
>>> received bytes,
>>>*   or error
>>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>>> + * The panel generates tearing effect synchronization signal
>>> between
>>> + * MCU and FB to display video images. And the display
>>> controller
>>> + * should trigger to transfer video image at this signal. So
>>> the panel
>>> + * receives the TE IRQ, then calls this function to notify
>>> it to the
>>> + * display controller.
>>>*/
>>>   struct mipi_dsi_host_ops {
>>>   int (*attach)(struct mipi_dsi_host *host,
>>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>> struct mipi_dsi_device *dsi);
>>>   ssize_t (*transfer)(struct mipi_dsi_host *host,
>>>   struct mipi_dsi_msg *msg);
>>> +void (*pass_te)(struct mipi_dsi_host *host);
>>
>> I've objected to this particular change before and that objection still
>> stands. I don't see how this is related to DSI. It seems like an
>> implementation detail of this particular setup and I think it should be
>> handled differently (within the Exynos DSI controller implementation
>> possibly).
>>
> 
> Okay, I understand what you mean.
> As you know, this function is called by panel TE interrupt handler, so
> it could be accessed by panel.
> Do you have any good idea for panel to access exynos_drm_dsi directly
> without mipi_dis_host_ops?
> 

Mr. Cho, let's just use notifier callback for the meantime: fimd driver
registers a te handler to Exynos mipi dsi driver, and then Exynos mipi
dsi driver calls the te handler when te interrupt occurs from Panel device.

I think all we can consider for it is to use mipi_dsi_host_ops or core
framework - connector/encoder and crtc. However, it seems that it's not
really easy for we have a consensus with other maintainers until other
i80 users appear and they need common something for it.


Thanks,
Inki Dae

> Thank you.
> Best regards YJ
> 
>> Laurent also asked you to split this up into two patches, one for the
>> core part, the other for the Exynos driver parts, yet this patch
>> contains both changes.
>>
>> Thierry
>>
> 
> 



[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

2014-07-10 Thread YoungJun Cho
On 07/10/2014 12:22 AM, Thierry Reding wrote:
> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>> To support LCD I80 interface, the DSI host calls this function
>> to notify the panel tearing effect synchronization signal to
>> the CRTC device manager to trigger to transfer video image.
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>   include/drm/drm_mipi_dsi.h  |  7 +++
>>   2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> index dad543a..76e34ca 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> @@ -24,6 +24,7 @@
>>   #include 
>>   #include 
>>
>> +#include "exynos_drm_crtc.h"
>>   #include "exynos_drm_drv.h"
>>
>>   /* returns true iff both arguments logically differs */
>> @@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
>> mipi_dsi_host *host,
>>  return (ret < 0) ? ret : xfer.rx_done;
>>   }
>>
>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>> +{
>> +struct exynos_dsi *dsi = host_to_dsi(host);
>> +struct drm_encoder *encoder = dsi->encoder;
>> +
>> +if (dsi->state & DSIM_STATE_ENABLED)
>> +exynos_drm_crtc_te_handler(encoder->crtc);
>> +}
>> +
>>   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>  .attach = exynos_dsi_host_attach,
>>  .detach = exynos_dsi_host_detach,
>>  .transfer = exynos_dsi_host_transfer,
>> +.pass_te = exynos_dsi_host_pass_te,
>>   };
>>
>>   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>> index 944f33f..3f21bea 100644
>> --- a/include/drm/drm_mipi_dsi.h
>> +++ b/include/drm/drm_mipi_dsi.h
>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>* @detach: detach DSI device from DSI host
>>* @transfer: send and/or receive DSI packet, return number of received 
>> bytes,
>>*   or error
>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>> + *   The panel generates tearing effect synchronization signal between
>> + *   MCU and FB to display video images. And the display controller
>> + *   should trigger to transfer video image at this signal. So the panel
>> + *   receives the TE IRQ, then calls this function to notify it to the
>> + *   display controller.
>>*/
>>   struct mipi_dsi_host_ops {
>>  int (*attach)(struct mipi_dsi_host *host,
>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>struct mipi_dsi_device *dsi);
>>  ssize_t (*transfer)(struct mipi_dsi_host *host,
>>  struct mipi_dsi_msg *msg);
>> +void (*pass_te)(struct mipi_dsi_host *host);
>
> I've objected to this particular change before and that objection still
> stands. I don't see how this is related to DSI. It seems like an
> implementation detail of this particular setup and I think it should be
> handled differently (within the Exynos DSI controller implementation
> possibly).
>

Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so 
it could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly 
without mipi_dis_host_ops?

Thank you.
Best regards YJ

> Laurent also asked you to split this up into two patches, one for the
> core part, the other for the Exynos driver parts, yet this patch
> contains both changes.
>
> Thierry
>



[PATCH] drm/crtc-helper: use drm_framebuffer flags

2014-07-10 Thread Fabien DESSENNE
Hi,
Can anyone review this patch ?
Thanks for your time.
Fabien

> -Original Message-
> From: Fabien DESSENNE [mailto:fabien.dessenne at st.com]
> Sent: mardi 1 juillet 2014 14:41
> To: dri-devel at lists.freedesktop.org
> Cc: Benjamin Gaignard; Vincent ABRIOU; Fabien DESSENNE
> Subject: [PATCH] drm/crtc-helper: use drm_framebuffer flags
> 
> The "flags" parameter of the DRM_IOCTL_MODE_ADDFB2 ioctl must be
> propagated and used by the driver.
> The only possible value of flags is DRM_MODE_FB_INTERLACED.
> 
> Signed-off-by: Fabien Dessenne 
> Reviewed-by: Benjamin GAIGNARD 
> ---
>  drivers/gpu/drm/drm_crtc_helper.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> b/drivers/gpu/drm/drm_crtc_helper.c
> index 23500c0..5974489 100644
> --- a/drivers/gpu/drm/drm_crtc_helper.c
> +++ b/drivers/gpu/drm/drm_crtc_helper.c
> @@ -966,6 +966,7 @@ int drm_helper_mode_fill_fb_struct(struct
> drm_framebuffer *fb,
>   drm_fb_get_bpp_depth(mode_cmd->pixel_format, >depth,
>   >bits_per_pixel);
>   fb->pixel_format = mode_cmd->pixel_format;
> + fb->flags = mode_cmd->flags;
> 
>   return 0;
>  }
> --
> 1.9.1



[PATCH 2/2] drm/radeon: add user pointer support v3

2014-07-10 Thread Alex Deucher
On Thu, Jul 10, 2014 at 8:33 AM, Christian K?nig
 wrote:
> From: Christian K?nig 
>
> This patch adds an IOCTL for turning a pointer supplied by
> userspace into a buffer object.
>
> It imposes several restrictions upon the memory being mapped:
>
> 1. It must be page aligned (both start/end addresses, i.e ptr and size).
>
> 2. It must be normal system memory, not a pointer into another map of IO
> space (e.g. it must not be a GTT mmapping of another object).
>
> 3. The BO is mapped into GTT, so the maximum amount of memory mapped at
> all times is still the GTT limit.
>
> 4. The BO is only mapped readonly for now, so no write support.
>
> 5. List of backing pages is only acquired once, so they represent a
> snapshot of the first use.
>
> Exporting and sharing as well as mapping of buffer objects created by
> this function is forbidden and results in an -EPERM.
>
> v2: squash all previous changes into first public version
> v3: fix tabs, map readonly, don't use MM callback any more
>
> Signed-off-by: Christian K?nig 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon.h|   4 ++
>  drivers/gpu/drm/radeon/radeon_cs.c |  25 +++-
>  drivers/gpu/drm/radeon/radeon_drv.c|   5 +-
>  drivers/gpu/drm/radeon/radeon_gem.c|  67 +
>  drivers/gpu/drm/radeon/radeon_kms.c|   1 +
>  drivers/gpu/drm/radeon/radeon_object.c |   3 +
>  drivers/gpu/drm/radeon/radeon_prime.c  |  10 +++
>  drivers/gpu/drm/radeon/radeon_ttm.c| 107 
> -
>  drivers/gpu/drm/radeon/radeon_vm.c |   3 +
>  include/uapi/drm/radeon_drm.h  |  11 
>  10 files changed, 232 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 86fdfa30..55c996e 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -2111,6 +2111,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void 
> *data,
>   struct drm_file *filp);
>  int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp);
> +int radeon_gem_import_ioctl(struct drm_device *dev, void *data,
> +   struct drm_file *filp);
>  int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
>  struct drm_file *file_priv);
>  int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
> @@ -2803,6 +2805,8 @@ extern void radeon_legacy_set_clock_gating(struct 
> radeon_device *rdev, int enabl
>  extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int 
> enable);
>  extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 
> domain);
>  extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
> +extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t userptr);
> +extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
>  extern void radeon_vram_location(struct radeon_device *rdev, struct 
> radeon_mc *mc, u64 base);
>  extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc 
> *mc);
>  extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool 
> fbcon);
> diff --git a/drivers/gpu/drm/radeon/radeon_cs.c 
> b/drivers/gpu/drm/radeon/radeon_cs.c
> index 71a1434..be65311 100644
> --- a/drivers/gpu/drm/radeon/radeon_cs.c
> +++ b/drivers/gpu/drm/radeon/radeon_cs.c
> @@ -78,7 +78,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser 
> *p)
> struct radeon_cs_chunk *chunk;
> struct radeon_cs_buckets buckets;
> unsigned i, j;
> -   bool duplicate;
> +   bool duplicate, need_mmap_lock = false;
> +   int r;
>
> if (p->chunk_relocs_idx == -1) {
> return 0;
> @@ -164,6 +165,19 @@ static int radeon_cs_parser_relocs(struct 
> radeon_cs_parser *p)
> p->relocs[i].allowed_domains = domain;
> }
>
> +   if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
> +   uint32_t domain = p->relocs[i].prefered_domains;
> +   if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
> +   DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
> + "allowed for userptr BOs\n");
> +   return -EINVAL;
> +   }
> +   need_mmap_lock = true;
> +   domain = RADEON_GEM_DOMAIN_GTT;
> +   p->relocs[i].prefered_domains = domain;
> +   p->relocs[i].allowed_domains = domain;
> +   }
> +
> p->relocs[i].tv.bo = >relocs[i].robj->tbo;
> p->relocs[i].handle = r->handle;
>
> @@ -176,8 +190,15 @@ static int radeon_cs_parser_relocs(struct 
> radeon_cs_parser *p)
> if (p->cs_flags & RADEON_CS_USE_VM)
> p->vm_bos = radeon_vm_get_bos(p->rdev, 

[PATCH 1/2] drm/radeon: add readonly flag to radeon_gart_set_page v2

2014-07-10 Thread Alex Deucher
On Thu, Jul 10, 2014 at 8:33 AM, Christian K?nig
 wrote:
> From: Christian K?nig 
>
> v2: use flag instead of boolean
>
> Signed-off-by: Christian K?nig 
> ---
>  drivers/gpu/drm/radeon/r100.c|  2 +-
>  drivers/gpu/drm/radeon/r300.c|  8 ++--
>  drivers/gpu/drm/radeon/radeon.h  | 12 +++-
>  drivers/gpu/drm/radeon/radeon_asic.h |  8 
>  drivers/gpu/drm/radeon/radeon_gart.c |  9 +
>  drivers/gpu/drm/radeon/radeon_ttm.c  |  4 ++--
>  drivers/gpu/drm/radeon/rs400.c   |  9 +++--
>  drivers/gpu/drm/radeon/rs600.c   |  8 ++--
>  8 files changed, 38 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index a6f7d61..fa71121d7 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -650,7 +650,7 @@ void r100_pci_gart_disable(struct radeon_device *rdev)
>  }
>
>  void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
> -   uint64_t addr)
> +   uint64_t addr, uint32_t flags)
>  {
> u32 *gtt = rdev->gart.ptr;
> gtt[i] = cpu_to_le32(lower_32_bits(addr));
> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
> index 8d14e66..b947f42 100644
> --- a/drivers/gpu/drm/radeon/r300.c
> +++ b/drivers/gpu/drm/radeon/r300.c
> @@ -73,13 +73,17 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
>  #define R300_PTE_READABLE  (1 << 3)
>
>  void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
> - uint64_t addr)
> + uint64_t addr, uint32_t flags)
>  {
> void __iomem *ptr = rdev->gart.ptr;
>
> addr = (lower_32_bits(addr) >> 8) |
>((upper_32_bits(addr) & 0xff) << 24) |
> -  R300_PTE_WRITEABLE | R300_PTE_READABLE;
> +  R300_PTE_READABLE;
> +
> +   if (!(flags & RADEON_GART_PAGE_READONLY))
> +   addr |= R300_PTE_WRITEABLE;
> +
> /* on x86 we want this to be CPU endian, on powerpc
>  * on powerpc without HW swappers, it'll get swapped on way
>  * into VRAM - so no need for cpu_to_le32 on VRAM tables */
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index c5318cac..86fdfa30 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -592,6 +592,8 @@ struct radeon_mc;
>  #define RADEON_GPU_PAGE_SHIFT 12
>  #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & 
> ~RADEON_GPU_PAGE_MASK)
>
> +#define RADEON_GART_PAGE_READONLY  1
> +
>  struct radeon_gart {
> dma_addr_t  table_addr;
> struct radeon_bo*robj;
> @@ -616,7 +618,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, 
> unsigned offset,
> int pages);
>  int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
>  int pages, struct page **pagelist,
> -dma_addr_t *dma_addr);
> +dma_addr_t *dma_addr, uint32_t flags);
>
>
>  /*
> @@ -854,8 +856,8 @@ struct radeon_mec {
>  #define R600_PTE_FRAG_256KB(6 << 7)
>
>  /* flags used for GART page table entries on R600+ */
> -#define R600_PTE_GART  ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED 
> \
> -   | R600_PTE_READABLE | R600_PTE_WRITEABLE)
> +#define R600_PTE_GART  ( R600_PTE_VALID | R600_PTE_SYSTEM | \
> + R600_PTE_SNOOPED | R600_PTE_READABLE )
>

This will disable the gart/GPUVM update optimization in most cases.
Might be better to just leave this define as is and use the individual
flags in the set_page() functions.  I realize this is just a proof of
concept.  Just pointing it out for future reference.

Alex

>  struct radeon_vm_pt {
> struct radeon_bo*bo;
> @@ -1775,7 +1777,7 @@ struct radeon_asic {
> struct {
> void (*tlb_flush)(struct radeon_device *rdev);
> void (*set_page)(struct radeon_device *rdev, unsigned i,
> -uint64_t addr);
> +uint64_t addr, uint32_t flags);
> } gart;
> struct {
> int (*init)(struct radeon_device *rdev);
> @@ -2703,7 +2705,7 @@ void radeon_ring_write(struct radeon_ring *ring, 
> uint32_t v);
>  #define radeon_vga_set_state(rdev, state) 
> (rdev)->asic->vga_set_state((rdev), (state))
>  #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
>  #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
> -#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), 
> (i), (p))
> +#define radeon_gart_set_page(rdev, i, p, r) 
> (rdev)->asic->gart.set_page((rdev), (i), (p), (r))
>  #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
>  #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
> 

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

2014-07-10 Thread Thierry Reding
 the same information, with reasonably low latency,
shall be transmitted from the display module to the host
processor when requested, using the bidirectional Data Lane.

My interpretation of that is that a DSI peripheral doesn't have a
dedicated TE signal. Now the panel that you want to support here seems
to have one, so I'm wondering if maybe it isn't a DSI panel at all but
rather DBI.

The specification goes into further detail about how to perform the TE
reporting in DSI. Essentially it consists of giving the peripheral
control of the bus via a BTA and then waiting for the peripheral to
report back with the TE event.

It would really help if somebody could find a datasheet for the panel so
that we don't have to keep guessing what the actual interface is and how
it's supposed to work.

Thierry
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[PATCH] exynos: Put a stop to the userptr heresy.

2014-07-10 Thread Daniel Vetter
On Thu, Jul 10, 2014 at 12:39:24AM +0900, Inki Dae wrote:
> On 2014? 07? 09? 18:23, Daniel Vetter wrote:
> > On Tue, Jul 8, 2014 at 6:20 PM, Inki Dae  wrote:
> >> 2014-07-08 22:37 GMT+09:00 Daniel Vetter :
> >>> On Wed, Jul 02, 2014 at 11:25:19AM -0400, Jerome Glisse wrote:
>  Anyway as this is upstream i guess you can keep it. This is just an 
>  horrible
>  API that allow to circumvant any limit set by memcg for page locking and 
>  all.
>  But anyway GPU driver never played in the same ballpark as other driver.
> >>>
> >>> I agree that exynos userptr as-is should be removed since as opposed to
> >>> the i915 implementation it doesn't play nice with the core mm
> >>
> >> Can you give me more details why you think so?
> > 
> >>From a very quick look there's two pieces:
> > - The implementation with the vma tricks looks _really_ scary. You'd
> > need to have Al Viro's opinion on it though.
> 
> You mean that it checks VM_DONTCOPY flag before copying vma? If so, I
> really forgot it.
> 
> > - If I'm reading the code correctly userspace can pin unlimted amounts
> > of memory, but I've gotten a bit lost in the code. In i915 we have
> 
> Not so. g2d driver is checking if user-requested buffer size is more
> than maximum capacity of g2d dma. So it can never pin unlimited amounts
> of memory.

Ah I didn't spot this check. I guess if the g2d dma size is a natural
limit then we're fine. Nowadays on recent i915 hw/sw we can use all of
system memory, so can't rely on some hw limit to limit the amount of
memory userspace can mlock. But if g2d has that (and there's enough memory
left for the kernel to not fall over) you should be fine.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


[PATCH 1/1] drm/tilcdc: Fix build breakage

2014-07-10 Thread Daniel Vetter
On Thu, Jul 10, 2014 at 12:02:15PM +1000, Dave Airlie wrote:
> On 9 July 2014 21:42, Sachin Kamat  wrote:
> > Commit 34ea3d386347 ("drm: add register and unregister functions
> > for connectors") probably missed out converting the
> > drm_sysfs_connector_remove instances in the following files.
> > Without this patch we get the following compilation error:
> > ERROR: "drm_sysfs_connector_remove" [drivers/gpu/drm/tilcdc/tilcdc.ko] 
> > undefined!
> >
> > Signed-off-by: Sachin Kamat 
> > CC: Thomas Wood 
> > CC: David Herrmann 
> > CC: Daniel Vetter 
> > ---
> > Only compile tested.
> 
> Oops, applied thanks,
> 
> I did an arm build just on the drm dir, forgot to let it run to
> completion over the whole tree.

Yeah, my apologies for breaking things. Nowadays I rely on the 0-day
builder for arm build testing, dunno why it didn't report this one here.
Might be good to check with Wu Fengguang that your driver is included - he
tends to catch other drm breakage on arm drivers well.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


[Bug 73053] dpm hangs with BTC parts

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=73053

Rpnpif  changed:

   What|Removed |Added

 CC||rpnpif at free.fr

--- Comment #34 from Rpnpif  ---
Hi,
Same issue with my system on motherboard MSI A78M-E35 with AMD APU A4-5300.
But my system reboots some 3 seconds after initramfs is loaded. So no Xorg and
no logs.

00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O
Memory Management Unit
Subsystem: Micro-Star International Co., Ltd. Device 7721
Flags: bus master, fast devsel, latency 0, IRQ 40
Capabilities: [40] Secure device 
Capabilities: [54] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [64] HyperTransport: MSI Mapping Enable+ Fixed+

00:01.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI Device
9993 (prog-if 00 [VGA controller])
Subsystem: Micro-Star International Co., Ltd. Device 7721
Flags: bus master, fast devsel, latency 0, IRQ 49
Memory at c000 (32-bit, prefetchable) [size=256M]
I/O ports at f000 [size=256]
Memory at feb0 (32-bit, non-prefetchable) [size=256K]
Expansion ROM at  [disabled]
Capabilities: [50] Power Management version 3
Capabilities: [58] Express Root Complex Integrated Endpoint, MSI 00
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 
Kernel driver in use: radeon

I wrote a bug issue on https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=748615
Same issue on linux 3.13 to 3.15.1.
radeon.dpm=0 fix it.

I does not yet try your last patch.

Regards.

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[Bug 80141] Fails to page flip multiple time, queue overflows waiting for one to finish that never does crashing entire system.

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=80141

--- Comment #19 from Aaron B  ---
Also a duplicate of the bug at
https://bugzilla.kernel.org/show_bug.cgi?id=79011. Sorry, marked it as the bug
from the forum I'm looking at, but didn't realize it encompassed multiple
bugzilla domains.

*** This bug has been marked as a duplicate of bug 79980 ***

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[Bug 79980] Random radeonsi crashes

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=79980

--- Comment #28 from Aaron B  ---
*** Bug 80141 has been marked as a duplicate of this bug. ***

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[Bug 80141] Fails to page flip multiple time, queue overflows waiting for one to finish that never does crashing entire system.

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=80141

--- Comment #18 from Aaron B  ---
Duplicate of 79980 as well.

*** This bug has been marked as a duplicate of bug 79011 ***

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[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

2014-07-10 Thread Inki Dae
On 2014? 07? 10? 00:22, Thierry Reding wrote:
> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>> To support LCD I80 interface, the DSI host calls this function
>> to notify the panel tearing effect synchronization signal to
>> the CRTC device manager to trigger to transfer video image.
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>  drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>  include/drm/drm_mipi_dsi.h  |  7 +++
>>  2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> index dad543a..76e34ca 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> @@ -24,6 +24,7 @@
>>  #include 
>>  #include 
>>  
>> +#include "exynos_drm_crtc.h"
>>  #include "exynos_drm_drv.h"
>>  
>>  /* returns true iff both arguments logically differs */
>> @@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
>> mipi_dsi_host *host,
>>  return (ret < 0) ? ret : xfer.rx_done;
>>  }
>>  
>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>> +{
>> +struct exynos_dsi *dsi = host_to_dsi(host);
>> +struct drm_encoder *encoder = dsi->encoder;
>> +
>> +if (dsi->state & DSIM_STATE_ENABLED)
>> +exynos_drm_crtc_te_handler(encoder->crtc);
>> +}
>> +
>>  static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>  .attach = exynos_dsi_host_attach,
>>  .detach = exynos_dsi_host_detach,
>>  .transfer = exynos_dsi_host_transfer,
>> +.pass_te = exynos_dsi_host_pass_te,
>>  };
>>  
>>  static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>> index 944f33f..3f21bea 100644
>> --- a/include/drm/drm_mipi_dsi.h
>> +++ b/include/drm/drm_mipi_dsi.h
>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>   * @detach: detach DSI device from DSI host
>>   * @transfer: send and/or receive DSI packet, return number of received 
>> bytes,
>>   *or error
>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>> + *   The panel generates tearing effect synchronization signal between
>> + *   MCU and FB to display video images. And the display controller
>> + *   should trigger to transfer video image at this signal. So the panel
>> + *   receives the TE IRQ, then calls this function to notify it to the
>> + *   display controller.
>>   */
>>  struct mipi_dsi_host_ops {
>>  int (*attach)(struct mipi_dsi_host *host,
>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>struct mipi_dsi_device *dsi);
>>  ssize_t (*transfer)(struct mipi_dsi_host *host,
>>  struct mipi_dsi_msg *msg);
>> +void (*pass_te)(struct mipi_dsi_host *host);
> 
> I've objected to this particular change before and that objection still
> stands. I don't see how this is related to DSI. It seems like an
> implementation detail of this particular setup and I think it should be
> handled differently (within the Exynos DSI controller implementation
> possibly).

I thought we had enough review but yes,  I missed it. It seems better to
handle pass_te callback within Exynos side as of now. That could cause
controversy. However, the obvious one is that te signal should be
notified to display controller driver somehow but there is no a good way
for it. Anyway, got it.  Reverted.

Thanks,
Inki Dae

> 
> Laurent also asked you to split this up into two patches, one for the
> core part, the other for the Exynos driver parts, yet this patch
> contains both changes.
> 
> Thierry
> 



[PATCH] exynos: Put a stop to the userptr heresy.

2014-07-10 Thread Inki Dae
On 2014? 07? 09? 18:23, Daniel Vetter wrote:
> On Tue, Jul 8, 2014 at 6:20 PM, Inki Dae  wrote:
>> 2014-07-08 22:37 GMT+09:00 Daniel Vetter :
>>> On Wed, Jul 02, 2014 at 11:25:19AM -0400, Jerome Glisse wrote:
 Anyway as this is upstream i guess you can keep it. This is just an 
 horrible
 API that allow to circumvant any limit set by memcg for page locking and 
 all.
 But anyway GPU driver never played in the same ballpark as other driver.
>>>
>>> I agree that exynos userptr as-is should be removed since as opposed to
>>> the i915 implementation it doesn't play nice with the core mm
>>
>> Can you give me more details why you think so?
> 
>>From a very quick look there's two pieces:
> - The implementation with the vma tricks looks _really_ scary. You'd
> need to have Al Viro's opinion on it though.

You mean that it checks VM_DONTCOPY flag before copying vma? If so, I
really forgot it.

> - If I'm reading the code correctly userspace can pin unlimted amounts
> of memory, but I've gotten a bit lost in the code. In i915 we have

Not so. g2d driver is checking if user-requested buffer size is more
than maximum capacity of g2d dma. So it can never pin unlimited amounts
of memory.

> shrinkers and mmu notifier to make sure that if the vm needs this
> memory again we'll make it available.

I am not familiar to mmu notifier. I will look into how i915 driver
handle it.

Thanks for comments,
Inki Dae

> -Daniel
> 



[PATCH] drm/radeon: add HDMI/DP sink description to ELD like data

2014-07-10 Thread Stefan Bruens
Provide monitor name and product/manufacturer id to alsa hda driver. The output
matches the fglrx settings, short of the port_id. As the latter is not 
standardized,
leave it out for now.

Corresponding alsa code is already in place.

Signed-off-by: Stefan Br?ns 
---
The fglrx register settings where retrieved using Rafal Mileckis gdb script.
After applying the patch fglrx and radeon register settings for sink info match,
short of the port_id.

Regarding port id, see comment by Takashi Iwai, 14 Nov 2013:
http://www.spinics.net/linux/fedora/alsa-user/msg12453.html
and RFC by Stephen Warren (NVidia), 25 May 2011:
http://lists.freedesktop.org/pipermail/xorg/2011-May/052893.html

 drivers/gpu/drm/radeon/dce6_afmt.c  | 67 +
 drivers/gpu/drm/radeon/evergreen_hdmi.c |  2 +
 2 files changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c 
b/drivers/gpu/drm/radeon/dce6_afmt.c
index 0a65dc7..1adf95a 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -273,6 +273,73 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
kfree(sads);
 }

+void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder)
+{
+   struct radeon_device *rdev = encoder->dev->dev_private;
+   struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+   struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+   struct drm_connector *connector;
+   u32 tmp = 0, offset;
+   char description[18];
+   uint8_t *eld;
+
+   if (!dig || !dig->afmt || !dig->afmt->pin)
+   return;
+
+   offset = dig->afmt->pin->offset;
+
+   list_for_each_entry(connector, 
>dev->mode_config.connector_list, head) {
+   if (connector->encoder == encoder)
+   break;
+   }
+
+   if (!connector) {
+   DRM_ERROR("Couldn't find encoder's connector\n");
+   return;
+   }
+
+   if (!connector->eld[0]) {
+   DRM_ERROR("Connector has no ELD\n");
+   return;
+   }
+
+   eld = connector->eld;
+
+   tmp = MANUFACTURER_ID(eld[16]<<8 | eld[17]) | PRODUCT_ID(eld[18]<<8 | 
eld[19]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0, tmp);
+
+   tmp = SINK_DESCRIPTION_LEN(strlen([20])) + 1;
+   tmp = (tmp > 19) ? 19 : tmp;
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1, tmp);
+
+   strncpy(description, [20], 18);
+
+   tmp = PORT_ID0(0x1);
+   //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2, tmp);
+
+   tmp = PORT_ID1(0x100);
+   //WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3, tmp);
+
+   tmp = DESCRIPTION0(description[0]) | DESCRIPTION1(description[1]) |
+ DESCRIPTION2(description[2]) | DESCRIPTION3(description[3]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4, tmp);
+
+   tmp = DESCRIPTION4(description[4]) | DESCRIPTION5(description[5]) |
+ DESCRIPTION6(description[6]) | DESCRIPTION7(description[7]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5, tmp);
+
+   tmp = DESCRIPTION8(description[8]) | DESCRIPTION9(description[9]) |
+ DESCRIPTION10(description[10]) | DESCRIPTION11(description[11]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6, tmp);
+
+   tmp = DESCRIPTION12(description[12]) | DESCRIPTION13(description[13]) |
+ DESCRIPTION14(description[14]) | DESCRIPTION15(description[15]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7, tmp);
+
+   tmp = DESCRIPTION16(description[16]) | DESCRIPTION17(description[17]);
+   WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8, tmp);
+}
+
 static int dce6_audio_chipset_supported(struct radeon_device *rdev)
 {
return !ASIC_IS_NODCE(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 1ec0e6e..b04ec3b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -37,6 +37,7 @@ extern void dce6_afmt_write_sad_regs(struct drm_encoder 
*encoder);
 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
 extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
   struct drm_display_mode *mode);
+extern void dce6_afmt_write_sinkinfo(struct drm_encoder *encoder);

 /*
  * update the N and CTS parameters for a given pixel clock rate
@@ -425,6 +426,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, 
struct drm_display_mode
dce6_afmt_select_pin(encoder);
dce6_afmt_write_sad_regs(encoder);
dce6_afmt_write_latency_fields(encoder, mode);
+   dce6_afmt_write_sinkinfo(encoder);
} else {
evergreen_hdmi_write_sad_regs(encoder);

[PATCH v5 00/14] drm/exynos: support LCD I80 interface display

2014-07-10 Thread Inki Dae
On 2014? 07? 08? 09:39, YoungJun Cho wrote:
> Hi,
> 
> This series adds LCD I80 interface display support for Exynos DRM driver.
> The FIMD(display controller) specification describes it as "LCD I80 interface"
> and the DSI specification describes it as "Command mode interface".
> 
> This is based on exynos-drm-next branch.

Thanks for contributions. Picked them up.

Thanks,
Inki Dae

> 
> The previous patches,
> RFC: http://www.spinics.net/lists/dri-devel/msg58898.html
> V1: http://www.spinics.net/lists/dri-devel/msg59291.html
> V2: http://www.spinics.net/lists/dri-devel/msg59867.html
> V3: http://www.spinics.net/lists/dri-devel/msg60708.html
> V4: http://www.spinics.net/lists/dri-devel/msg60943.html
> 
> Changelog v2:
> - Fixes typo and removes unnecessary error log (commented by Andrzej Hazda)
> - Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz)
> 
> Changelog v3:
> - Removes generic command mode and command mode display timing interface.
> - Moves I80 interface timings from panel DT to the FIMD(display controller) 
> DT.
> 
> Changelog v4:
> - Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because
>   it was already updated by linux-samsung-soc (commented by Vivek Gautam)
> 
> Changelog v5:
> - Fixes FIMD vidcon0 register relevant code
> - Fixes panel gamma table, disable sequence
> - Slitely updates for code cleanup
> 
> Patches 1 and 2 fix trivial bugs.
> 
> Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface.
> The MIPI DSI command mode based panel generates Tearing Effect synchronization
> signal between MCU and FB to display video image, and FIMD should trigger to
> transfer video image at this signal.
> So the panel should receive the TE IRQ and call TE handler chains to notify
> it to the FIMD.
> 
> Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver
> which is different from previous Exynos4 SoCs for some registers control.
> 
> Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED
> 5.7" LCD drm panel driver.
> 
> The ohters add DT property nodes to support MIPI DSI command mode.
> 
> I welcome any comments.
> 
> Thank you.
> Best regards YJ
> 
> YoungJun Cho (14):
>   drm/exynos: dsi: move the EoT packets configuration point
>   drm/exynos: use wait_event_timeout() for safety usage
>   ARM: dts: samsung-fimd: add LCD I80 interface specific properties
>   drm/exynos: add TE handler to support LCD I80 interface
>   drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
>   drm/exynos: fimd: support LCD I80 interface
>   ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
>   drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
>   ARM: dts: s6e3fa0: add DT bindings
>   drm/panel: add S6E3FA0 driver
>   ARM: dts: exynos4: add system register property
>   ARM: dts: exynos5: add system register property
>   ARM: dts: exynos5420: add mipi-phy node
>   ARM: dts: exynos5420: add dsi node
> 
>  .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |  46 ++
>  .../devicetree/bindings/video/exynos_dsim.txt  |   4 +-
>  .../devicetree/bindings/video/samsung-fimd.txt |  28 +
>  arch/arm/boot/dts/exynos4.dtsi |   1 +
>  arch/arm/boot/dts/exynos5.dtsi |   1 +
>  arch/arm/boot/dts/exynos5420.dtsi  |  20 +
>  drivers/gpu/drm/exynos/Kconfig |   1 +
>  drivers/gpu/drm/exynos/exynos_drm_crtc.c   |  15 +-
>  drivers/gpu/drm/exynos/exynos_drm_crtc.h   |   7 +
>  drivers/gpu/drm/exynos/exynos_drm_drv.h|   3 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c| 181 ++-
>  drivers/gpu/drm/exynos/exynos_drm_fimd.c   | 276 --
>  drivers/gpu/drm/panel/Kconfig  |   7 +
>  drivers/gpu/drm/panel/Makefile |   1 +
>  drivers/gpu/drm/panel/panel-s6e3fa0.c  | 569 
> +
>  include/drm/drm_mipi_dsi.h |   7 +
>  include/video/samsung_fimd.h   |   3 +-
>  17 files changed, 1098 insertions(+), 72 deletions(-)
>  create mode 100644 
> Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
>  create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
> 



[Bug 66067] Trine 2's fragment normal buffer is mixtextured on Radeon HD 6770 (Juniper)

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=66067

--- Comment #27 from smoki  ---
 Probably. Anyway with this patch somehow Unigine Sanctuary high shader is
affected, that huge performance drop happens only on Shaders:High setings, but
as i see performance is not reduced at all on Medium or Low shaders setting.

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[PATCH 00/12] drm/exynos/ipp: image post processing improvements, part three

2014-07-10 Thread Inki Dae
On 2014? 07? 03? 22:10, Andrzej Hajda wrote:
> This set of independent patches contains various improvement and fixes
> for exynos_drm ipp framework.
> The patchset is based on exynos-drm-next branch.
> 

Did you test ipp module using libdrm? If so, can you share the app? I
would try to test this patch series before merging them. Mainline libdrm
has no any ipp interfaces.

Thanks,
Inki Dae

> Regards
> Andrzej
> 
> 
> Andrzej Hajda (12):
>   drm/exynos/ipp: remove type casting
>   drm/exynos/ipp: remove unused field from exynos_drm_ipp_private
>   drm/exynos/ipp: remove struct exynos_drm_ipp_private
>   drm/exynos/ipp: correct address type
>   drm/exynos/ipp: remove temporary variable
>   drm/exynos/ipp: remove incorrect checks of list_first_entry result
>   drm/exynos/ipp: simplify memory check function
>   drm/exynos/ipp: remove useless registration checks
>   drm/exynos/ipp: simplify ipp_find_obj
>   drm/exynos/ipp: remove redundant messages
>   drm/exynos/ipp: simplify ipp_create_id
>   drm/exynos/ipp: simplify ipp_find_driver
> 
>  drivers/gpu/drm/exynos/exynos_drm_drv.h |   7 +-
>  drivers/gpu/drm/exynos/exynos_drm_ipp.c | 259 
> +---
>  drivers/gpu/drm/exynos/exynos_drm_ipp.h |   4 +-
>  3 files changed, 73 insertions(+), 197 deletions(-)
> 



[RFC] drm/exynos: abort commit when framebuffer is removed from plane

2014-07-10 Thread Inki Dae
On 2014? 07? 09? 20:06, Rahul Sharma wrote:
> On 8 July 2014 21:25, Inki Dae  wrote:
>> 2014-06-20 0:13 GMT+09:00 Rahul Sharma :
>>> This situation arises when userspace remove the frambuffer object
>>> and call setmode ioctl.
>>>
>>> drm_mode_rmfb --> drm_plane_force_disable --> plane->crtc = NULL;
>>> and
>>> drm_mode_setcrtc --> exynos_plane_commit --> passes plane->crtc to
>>> exynos_drm_crtc_plane_commit which is NULL.
>>
>> If user process requested drm_mode_rmfb with a fb_id, fb object to the
>> fb_id must be removed from crtc_idr table. So drm_mode_setcrtc should
>> be failed because there is no the fb object in the crtc_idr table
>> anymore.
>> I cannot understand how exynos_drm_crtc_plane_commit function could be
>> called. Can you give me more details?
> 
> Inki,
> 
> These logs should clarify more about the problem:

Thanks. And how can I reenact below problem? if we could reenact this
problem, we may find out fundamental problem and resolve it in more
generic. Can I get example code?

Thanks,
Inki Dae

> 
> localhost ~ # halt
> localhost ~ # [  130.570309] init: debugd main process (781) killed by
> TERM signal
> [  130.602453] init: lid_touchpad_helper main process (2100) killed by
> TERM signal
> [  131.374955] CPU: 2 PID: 834 Comm: X Tainted: GW 3.16.0-rc1+ 
> #623
> [  131.380558] [] (unwind_backtrace) from []
> (show_stack+0x20/0x24)
> [  131.388327] [] (show_stack) from []
> (dump_stack+0x7c/0x98)
> [  131.395522] [] (dump_stack) from []
> (exynos_drm_crtc_plane_commit+0x20/0x40)
> [  131.404263] [] (exynos_drm_crtc_plane_commit) from
> [] (exynos_plane_commit+0x24/0x28)
> [  131.413779] [] (exynos_plane_commit) from []
> (exynos_drm_crtc_commit+0x2c/0x54)
> [  131.422802] [] (exynos_drm_crtc_commit) from []
> (exynos_drm_crtc_mode_set_commit.isra.1+0x8c/0xa0)
> [  131.433468] [] (exynos_drm_crtc_mode_set_commit.isra.1)
> from [] (exynos_drm_crtc_page_flip+0x100/0x174)
> [  131.444587] [] (exynos_drm_crtc_page_flip) from
> [] (drm_mode_page_flip_ioctl+0x1f0/0x2b0)
> -->> [  131.454460] [] (drm_mode_page_flip_ioctl) from
> [] (drm_ioctl+0x270/0x44c)
> [  131.462966] [] (drm_ioctl) from []
> (do_vfs_ioctl+0x4e4/0x5a0)
> [  131.470397] [] (do_vfs_ioctl) from []
> (SyS_ioctl+0x5c/0x84)
> [  131.477728] [] (SyS_ioctl) from []
> (ret_fast_syscall+0x0/0x30)
> [  131.762797] CPU: 1 PID: 834 Comm: X Tainted: GW 3.16.0-rc1+ 
> #623
> [  131.768378] [] (unwind_backtrace) from []
> (show_stack+0x20/0x24)
> [  131.776151] [] (show_stack) from []
> (dump_stack+0x7c/0x98)
> [  131.783315] [] (dump_stack) from []
> (drm_plane_force_disable+0x5c/0x68)
> [  131.791658] [] (drm_plane_force_disable) from
> [] (drm_framebuffer_remove+0xe4/0x110)
> [  131.801070] [] (drm_framebuffer_remove) from []
> (drm_mode_rmfb+0xd4/0xfc)
> -->> [  131.809597] [] (drm_mode_rmfb) from []
> (drm_ioctl+0x270/0x44c)
> [  131.817135] [] (drm_ioctl) from []
> (do_vfs_ioctl+0x4e4/0x5a0)
> [  131.824609] [] (do_vfs_ioctl) from []
> (SyS_ioctl+0x5c/0x84)
> [  131.831884] [] (SyS_ioctl) from []
> (ret_fast_syscall+0x0/0x30)
> [  132.077803] CPU: 0 PID: 834 Comm: X Tainted: GW 3.16.0-rc1+ 
> #623
> [  132.083413] [] (unwind_backtrace) from []
> (show_stack+0x20/0x24)
> [  132.09] [] (show_stack) from []
> (dump_stack+0x7c/0x98)
> [  132.098343] [] (dump_stack) from []
> (exynos_drm_crtc_plane_commit+0x20/0x40)
> [  132.107098] [] (exynos_drm_crtc_plane_commit) from
> [] (exynos_plane_commit+0x24/0x28)
> [  132.116631] [] (exynos_plane_commit) from []
> (exynos_drm_crtc_commit+0x2c/0x54)
> [  132.125660] [] (exynos_drm_crtc_commit) from []
> (exynos_drm_crtc_mode_set_commit.isra.1+0x8c/0xa0)
> [  132.136330] [] (exynos_drm_crtc_mode_set_commit.isra.1)
> from [] (exynos_drm_crtc_mode_set_base+0x18/0x1c)
> [  132.147605] [] (exynos_drm_crtc_mode_set_base) from
> [] (drm_crtc_helper_set_config+0x828/0x8a4)
> [  132.158029] [] (drm_crtc_helper_set_config) from
> [] (drm_mode_set_config_internal+0x58/0xc0)
> [  132.168155] [] (drm_mode_set_config_internal) from
> [] (drm_mode_setcrtc+0x388/0x4ac)
> -->> [  132.177630] [] (drm_mode_setcrtc) from []
> (drm_ioctl+0x270/0x44c)
> [  132.185417] [] (drm_ioctl) from []
> (do_vfs_ioctl+0x4e4/0x5a0)
> [  132.192897] [] (do_vfs_ioctl) from []
> (SyS_ioctl+0x5c/0x84)
> [  132.200138] [] (SyS_ioctl) from []
> (ret_fast_syscall+0x0/0x30)
> [  132.207735] Unable to handle kernel NULL pointer dereference at
> virtual address 032c
> ..
> ..
> [  132.510786] ff80: b6ebdeb8 bee1d5e8 c06864a2 0036 c000e5a4
> ecf0e000  ecf0ffa8
> [  132.518941] ffa0: c000e380 c01130f4 b6ebdeb8 bee1d5e8 0005
> c06864a2 bee1d5e8 0001
> [  132.527095] ffc0: b6ebdeb8 bee1d5e8 c06864a2 0036 b85d4a74
> b8702a60  bee1d688
> [  132.535250] ffe0: b6a82f30 bee1d5cc b6a75cff b6bce50c 0010
> 0005 e1a0c00d e92dd800
> [  132.543408] [] (exynos_drm_crtc_plane_commit) from
> [] (exynos_plane_commit+0x24/0x28)
> [  132.552949] [] (exynos_plane_commit) from 

drm/vmwgfx: Fix compat shader namespace

2014-07-10 Thread Thomas Hellström

On 2014-07-09 14:48, Dan Carpenter wrote:
> Hello Thomas Hellstrom,
>
> The patch 18e4a4669c50: "drm/vmwgfx: Fix compat shader namespace"
> from Jun 9, 2014, leads to the following static checker warning:
>
>   drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c:477 vmw_cmd_res_reloc_add()
>   warn: missing error code here? 'kzalloc()' failed.
>
> drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
> 468
> 469  ret = vmw_resource_context_res_add(dev_priv, 
> sw_context, res);
> 470  if (unlikely(ret != 0))
> 471  goto out_err;
> 472  node->staged_bindings =
> 473  kzalloc(sizeof(*node->staged_bindings), 
> GFP_KERNEL);
> 474  if (node->staged_bindings == NULL) {
> 475  DRM_ERROR("Failed to allocate context 
> binding "
> 476"information.\n");
> 477  goto out_err;
>
> This should just be "return -ENOMEM;".  The goto is misleading because
> you expect it to do something useful.

Indeed. Thanks for pointing that out. Since this is old code being 
reorganized, the goto slipped through. The missing error code has been 
around for a while, though. I'll put together a patch for that.

>
> Soon checkpatch.pl will start complaining about the extra DRM_ERROR()
> because kzalloc() has a more useful printk builtin and this just wastes
> memory and makes the code more verbose.
Noted.

>
> Speaking of verbose, all the likely/unlikely annotations should be
> removed.

Is this your personal opinion or has there been some kind of kernel 
developer agreement not to add this annotation and remove it from the 
kernel tree? If not, I prefer to keep it.

>If the code were more readable then the missing error code
> would have been more noticeable.  This code is buggy because it is ugly;
> there is a direct cause effect relationship.
I think ugliness in this case is in the eye of the beholder. The bug 
likely entered long ago like these bugs tend to do because you're not 
100% focused when the code is written. I find this statement a bit 
incoherent because there's no branch prediction hint in the if statement 
preceding the bug and although the error message may be redundant in 
this case, I can't see why an error message would make the code ugly or 
be the cause of a bug.

>
> 478  }
> 479  INIT_LIST_HEAD(>staged_bindings->list);
> 480  }
> 481
> 482  if (p_val)
> 483  *p_val = node;
> 484
> 485  out_err:
> 486  return ret;
> 487  }
>
> regards,
> dan carpenter

Thanks,
Thomas


[Bug 78661] GPU sometimes locks up after boot and/or resume

2014-07-10 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=78661

--- Comment #11 from Nikolaus Waxweiler  ---
Created attachment 142621
  --> https://bugzilla.kernel.org/attachment.cgi?id=142621=edit
Got a temporary hang again on boot-up, managed to reboot...

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[Bug 66067] Trine 2's fragment normal buffer is mixtextured on Radeon HD 6770 (Juniper)

2014-07-10 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=66067

--- Comment #26 from Nicholas Miell  ---
(In reply to comment #25)
>  BTW just to be aware of i see some side effects of this patch, for example
> performance in Unigine Sanctuary goes down by ~40% for me :).

Probably because it adds a branch to every single sampler.

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