[PATCH 26/29] drm/exynos: atomic phase 1: add atomic_begin()/atomic_flush()
On 2014ë
12ì 18ì¼ 22:58, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Add CRTC callbacks .atomic_begin() .atomic_flush(). On exynos they
> unprotect the windows before the commit and protects it after based on
> a plane mask tha store which plane will be updated.
tha? Typo?
>
> For that we create two new exynos_crtc callbacks: .win_protect() and
> .win_unprotect(). The only driver that implement those now is FIMD.
>
> Signed-off-by: Gustavo Padovan
> ---
> drivers/gpu/drm/exynos/exynos_drm_crtc.c | 34 +++
> drivers/gpu/drm/exynos/exynos_drm_drv.h | 4 +++
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 56
> ++-
> drivers/gpu/drm/exynos/exynos_drm_plane.c | 4 +++
> 4 files changed, 82 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> index 74980c5..f231eb8 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> @@ -156,6 +156,38 @@ static void exynos_drm_crtc_disable(struct drm_crtc
> *crtc)
> }
> }
>
> +static void exynos_crtc_atomic_begin(struct drm_crtc *crtc)
> +{
> + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
> + struct drm_plane *plane;
> + int index = 0;
> +
Isn't drm_modest_lock_all(dev) required? Or is this function atomic
context? I didn't look into all codes yet so there may be my missing point.
> + list_for_each_entry(plane, >dev->mode_config.plane_list, head) {
> + if (exynos_crtc->ops->win_protect &&
> + exynos_crtc->plane_mask & (0x01 << index))
> + exynos_crtc->ops->win_protect(exynos_crtc, index);
> +
> + index++;
> + }
> +}
> +
> +static void exynos_crtc_atomic_flush(struct drm_crtc *crtc)
> +{
> + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
> + struct drm_plane *plane;
> + int index = 0;
> +
Ditto.
> + list_for_each_entry(plane, >dev->mode_config.plane_list, head) {
> + if (exynos_crtc->ops->win_unprotect &&
> + exynos_crtc->plane_mask & (0x01 << index))
> + exynos_crtc->ops->win_unprotect(exynos_crtc, index);
> +
> + index++;
> + }
> +
> + exynos_crtc->plane_mask = 0;
> +}
> +
> static struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = {
> .dpms = exynos_drm_crtc_dpms,
> .prepare= exynos_drm_crtc_prepare,
> @@ -164,6 +196,8 @@ static struct drm_crtc_helper_funcs
> exynos_crtc_helper_funcs = {
> .mode_set = exynos_drm_crtc_mode_set,
> .mode_set_base = exynos_drm_crtc_mode_set_base,
> .disable= exynos_drm_crtc_disable,
> + .atomic_begin = exynos_crtc_atomic_begin,
> + .atomic_flush = exynos_crtc_atomic_flush,
> };
>
> static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
> b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> index d490b49..1df769f 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> @@ -195,6 +195,8 @@ struct exynos_drm_crtc_ops {
> void (*win_enable)(struct exynos_drm_crtc *crtc, int zpos);
> void (*win_disable)(struct exynos_drm_crtc *crtc, int zpos);
> void (*te_handler)(struct exynos_drm_crtc *crtc);
> + void (*win_protect)(struct exynos_drm_crtc *crtc, int zpos);
> + void (*win_unprotect)(struct exynos_drm_crtc *crtc, int zpos);
> };
>
> enum exynos_crtc_mode {
> @@ -215,6 +217,7 @@ enum exynos_crtc_mode {
> * we can refer to the crtc to current hardware interrupt occurred through
> * this pipe value.
> * @dpms: store the crtc dpms value
> + * @plane_mask: store planes to be updated on atomic modesetting
> * @mode: store the crtc mode value
> * @ops: pointer to callbacks for exynos drm specific functionality
> * @ctx: A pointer to the crtc's implementation specific context
> @@ -224,6 +227,7 @@ struct exynos_drm_crtc {
> enum exynos_drm_output_type type;
> unsigned intpipe;
> unsigned intdpms;
> + unsigned intplane_mask;
> enum exynos_crtc_mode mode;
> wait_queue_head_t pending_flip_queue;
> atomic_tpending_flip;
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> index 0e01b17..4a5ef31 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> @@ -644,6 +644,16 @@ static void fimd_shadow_protect_win(struct fimd_context
> *ctx,
> {
> u32 reg, bits, val;
>
> + /*
> + * SHADOWCON/PRTCON register is used for enabling timing.
> + *
> + * for example, once only width value of a register is set,
> + * if the dma is started then fimd hardware could
[PATCH 25/29] drm/exynos: atomic phase 1: use drm_plane_helper_disable()
On 2014ë
12ì 18ì¼ 22:58, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> The atomic helper to disable planes also uses exynos_update_plane() to
> disable plane so we had to adapt it to both commit and disable planes.
>
> A check for NULL CRTC was added to exynos_plane_mode_set() since planes
> to be disabled have plane_state->crtc set to NULL.
>
> Also win_disable() callback uses plane->crtc as arg for the same reason.
>
> exynos_drm_fb_get_buf_cnt() needs a fb check too to avoid a null pointer.
>
> Signed-off-by: Gustavo Padovan
> ---
> drivers/gpu/drm/exynos/exynos_drm_fb.c| 2 +-
> drivers/gpu/drm/exynos/exynos_drm_plane.c | 24 ++--
> 2 files changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c
> b/drivers/gpu/drm/exynos/exynos_drm_fb.c
> index d346d1e..470456d 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
> @@ -136,7 +136,7 @@ unsigned int exynos_drm_fb_get_buf_cnt(struct
> drm_framebuffer *fb)
>
> exynos_fb = to_exynos_fb(fb);
>
> - return exynos_fb->buf_cnt;
> + return exynos_fb ? exynos_fb->buf_cnt : 0;
This change isn't related with this patch.
> }
>
> struct drm_framebuffer *
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
> b/drivers/gpu/drm/exynos/exynos_drm_plane.c
> index 1c67fbc..dfca218 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
> @@ -98,6 +98,9 @@ static void exynos_plane_mode_set(struct drm_plane *plane,
> struct drm_crtc *crtc
> unsigned int actual_w;
> unsigned int actual_h;
>
> + if (!crtc)
> + return;
Ditto.
> +
> actual_w = exynos_plane_get_size(crtc_x, crtc_w, crtc->mode.hdisplay);
> actual_h = exynos_plane_get_size(crtc_y, crtc_h, crtc->mode.vdisplay);
>
> @@ -140,8 +143,6 @@ static void exynos_plane_mode_set(struct drm_plane
> *plane, struct drm_crtc *crtc
> exynos_plane->crtc_x, exynos_plane->crtc_y,
> exynos_plane->crtc_width, exynos_plane->crtc_height);
>
> - plane->crtc = crtc;
> -
> if (exynos_crtc->ops->win_mode_set)
> exynos_crtc->ops->win_mode_set(exynos_crtc, exynos_plane);
> }
> @@ -179,15 +180,26 @@ exynos_update_plane(struct drm_plane *plane, struct
> drm_crtc *crtc,
>uint32_t src_x, uint32_t src_y,
>uint32_t src_w, uint32_t src_h)
> {
> - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
> struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
> + struct exynos_drm_crtc *exynos_crtc;
>
> exynos_plane_mode_set(plane, crtc, fb, crtc_x, crtc_y,
> crtc_w, crtc_h, src_x >> 16, src_y >> 16,
> src_w >> 16, src_h >> 16);
>
> - if (exynos_crtc->ops->win_commit)
> - exynos_crtc->ops->win_commit(exynos_crtc, exynos_plane->zpos);
> + if (fb) {
> + exynos_crtc = to_exynos_crtc(crtc);
> + if (exynos_crtc->ops->win_commit)
> + exynos_crtc->ops->win_commit(exynos_crtc,
> + exynos_plane->zpos);
> + } else {
> + exynos_crtc = to_exynos_crtc(plane->crtc);
> + if (exynos_crtc->ops->win_disable)
> + exynos_crtc->ops->win_disable(exynos_crtc,
> + exynos_plane->zpos);
> + }
> +
> + plane->crtc = crtc;
> }
>
> static int exynos_disable_plane(struct drm_plane *plane)
> @@ -224,7 +236,7 @@ static int exynos_plane_set_property(struct drm_plane
> *plane,
>
> static struct drm_plane_funcs exynos_plane_funcs = {
> .update_plane = drm_plane_helper_update,
> - .disable_plane = exynos_disable_plane,
> + .disable_plane = drm_plane_helper_disable,
> .destroy= exynos_plane_destroy,
> .set_property = exynos_plane_set_property,
> };
>
[PATCH 01/29] drm/exynos/fimd: only finish pageflip if START == START_S
On 2014ë
12ì 18ì¼ 22:58, Gustavo Padovan wrote:
> From: Daniel Kurtz
>
> A framebuffer gets committed to FIMD's default window like this:
> exynos_drm_crtc_update()
> exynos_plane_commit()
>fimd_win_commit()
>
> fimd_win_commit() programs BUF_START[0]. At each vblank, FIMD hardware
> copies the value from BUF_START to BUF_START_S (BUF_START's shadow
> register), starts scanning out from BUF_START_S, and asserts its irq.
>
> This irq is handled by fimd_irq_handler(), which calls
> exynos_drm_crtc_finish_pageflip() to free the old buffer that FIMD just
> finished scanning out, and potentially commit the next pending flip.
>
> There is a race, however, if fimd_win_commit() programs BUF_START(0)
> between the actual vblank irq, and its corresponding fimd_irq_handler().
>
> => FIMD vblank: BUF_START_S[0] := BUF_START[0], and irq asserted
> | => fimd_win_commit(0) writes new BUF_START[0]
> |exynos_drm_crtc_try_do_flip() marks exynos_fb as prepared
> => fimd_irq_handler()
> exynos_drm_crtc_finish_pageflip() sees prepared exynos_fb,
> and unmaps "old" fb
> ==> but, since BUF_START_S[0] still points to that "old" fb...
> ==> FIMD iommu fault
>
> This patch ensures that fimd_irq_handler() only calls
> exynos_drm_crtc_finish_pageflip() if any previously scheduled flip
> has really completed.
>
> This works because exynos_drm_crtc's flip fifo ensures that
> fimd_win_commit() is never called more than once per
> exynos_drm_crtc_finish_pageflip().
>
> Signed-off-by: Daniel Kurtz
> Reviewed-by: Sean Paul
> Signed-off-by: Gustavo Padovan
> ---
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 ++
> include/video/samsung_fimd.h | 1 +
> 2 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> index e5810d1..b379182 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> @@ -55,6 +55,7 @@
> #define VIDOSD_D(win)(VIDOSD_BASE + 0x0C + (win) * 16)
>
> #define VIDWx_BUF_START(win, buf)(VIDW_BUF_START(buf) + (win) * 8)
> +#define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
> #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
> #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
>
> @@ -1039,6 +1040,7 @@ static irqreturn_t fimd_irq_handler(int irq, void
> *dev_id)
> {
> struct fimd_context *ctx = (struct fimd_context *)dev_id;
> u32 val, clear_bit;
> + u32 start, start_s;
>
> val = readl(ctx->regs + VIDINTCON1);
>
> @@ -1050,15 +1052,31 @@ static irqreturn_t fimd_irq_handler(int irq, void
> *dev_id)
> if (ctx->pipe < 0 || !ctx->drm_dev)
> goto out;
>
> - if (ctx->i80_if) {
> + if (!ctx->i80_if)
> + drm_handle_vblank(ctx->drm_dev, ctx->pipe);
> +
> + /*
> + * Ensure finish_pageflip is called iff a pending flip has completed.
Maybe s/iff/if
> + * This works around a race between a page_flip request and the latency
> + * between vblank interrupt and this irq_handler:
> + * => FIMD vblank: BUF_START_S[0] := BUF_START[0], and asserts irq
> + * | => fimd_win_commit(0) writes new BUF_START[0]
> + * |exynos_drm_crtc_try_do_flip() marks exynos_fb as prepared
> + * => fimd_irq_handler()
> + * exynos_drm_crtc_finish_pageflip() sees prepared exynos_fb,
> + * and unmaps "old" fb
> + * ==> but, since BUF_START_S[0] still points to that "old" fb...
> + * ==> FIMD iommu fault
> + */
> + start = readl(ctx->regs + VIDWx_BUF_START(0, 0));
> + start_s = readl(ctx->regs + VIDWx_BUF_START_S(0, 0));
> + if (start == start_s)
> exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
As I already mentioned before, above codes should be called only in case
of RGB mode until checked for i80 mode. Have you ever tested above codes
on i80 mode?
And what if 'start_s' has a value different from one of 'start'? Is it
ok to skip finish_pageflip request this time? Shouldn't it ensure to
wait for that until 'start_s' has a value same as one of 'start'?
Thanks,
Inki Dae
>
> + if (ctx->i80_if) {
> /* Exits triggering mode */
> atomic_set(>triggering, 0);
> } else {
> - drm_handle_vblank(ctx->drm_dev, ctx->pipe);
> - exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
> -
> /* set wait vsync event to zero and wake up queue. */
> if (atomic_read(>wait_vsync_event)) {
> atomic_set(>wait_vsync_event, 0);
> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
> index a20e4a3..f81d081 100644
> --- a/include/video/samsung_fimd.h
> +++ b/include/video/samsung_fimd.h
> @@ -291,6 +291,7 @@
>
> /* Video buffer
[PATCH] drm: Move two seq_printf's outside of locked mutex
In drm_info.c: drm_bufs_info() and drm_vm_info() two seq_printf() was
done unnecessarily while locking a mutex. This patch flips the order of
the print and lock/unlock where applicable.
Signed-off-by: Jonas Lundqvist
---
drivers/gpu/drm/drm_info.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
index 51efebd..981afe7 100644
--- a/drivers/gpu/drm/drm_info.c
+++ b/drivers/gpu/drm/drm_info.c
@@ -81,11 +81,10 @@ int drm_vm_info(struct seq_file *m, void *data)
_DRM_SCATTER_GATHER and _DRM_CONSISTENT */
const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" };
const char *type;
- int i;
+ int i = 0;
- mutex_lock(>struct_mutex);
seq_printf(m, "slot offset size type flagsaddress
mtrr\n\n");
- i = 0;
+ mutex_lock(>struct_mutex);
list_for_each_entry(r_list, >maplist, head) {
map = r_list->map;
if (!map)
@@ -147,8 +146,8 @@ int drm_bufs_info(struct seq_file *m, void *data)
seq_printf(m, "\n");
seq_printf(m, " %d", dma->buflist[i]->list);
}
- seq_printf(m, "\n");
mutex_unlock(>struct_mutex);
+ seq_printf(m, "\n");
return 0;
}
--
2.1.4
[PULL] amdkfd-fixes
Hi Dave, A couple of bug fixes for 3.19-rc3, or for -rc4 if you decide to skip -rc3. Highlights: - Link order changes in drm/Makefile and drivers/Makefile to fix issue when amdkfd, radeon and amd_iommu_v2 are compiled inside the kernel image. - Consider kernel configuration (using #IFDEFs) when radeon initializes amdkfd, due to a specific configuration that makes symbol_request() return a non-NULL value when a symbol doesn't exists. Rusty Russel is helping me to find the root cause, but it may take a while because of year-end so I'm sending this as a band-aid solution. Other fixes include topology, pasid allocations and queues accounting. Thanks and a happy new year Oded The following changes since commit b7392d2247cfe6771f95d256374f1a8e6a6f48d6: Linux 3.19-rc2 (2014-12-28 16:49:37 -0800) are available in the git repository at: git://people.freedesktop.org/~gabbayo/linux tags/amdkfd-fixes-2014-12-30 for you to fetch changes up to 38c2adfb00db045a876dd667040abc01b788ad61: drm/radeon: Init amdkfd only if it was compiled (2014-12-29 14:46:00 +0200) Ben Goz (1): amdkfd: Fixing topology bug in building sysfs nodes Oded Gabbay (5): amdkfd: Fix accounting of device queues amdkfd: Remove duplicate include drivers: Move iommu/ before gpu/ in Makefile drm: Put amdkfd before radeon in drm Makefile drm/radeon: Init amdkfd only if it was compiled Sasha Levin (1): amdkfd: actually allocate longs for the pasid bitmask drivers/Makefile | 6 -- drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 13 +++-- drivers/gpu/drm/amd/amdkfd/kfd_pasid.c| 2 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- drivers/gpu/drm/radeon/radeon_kfd.c | 12 7 files changed, 30 insertions(+), 8 deletions(-)
[PATCH v8 0/2] ASoC: tda998x: add a codec to the HDMI transmitter
On Mon, Dec 29, 2014 at 07:37:21PM +0200, Jyri Sarha wrote: > On 12/29/2014 06:52 PM, Mark Brown wrote: > >So, I'm not seeing *any* interest here from any other HDMI users. This > >is a continuing theme with HDMI patches and is really very concerning, > >everyone appears to be working in their own bubbles coming up with their > >own things and ignoring everyone else's work - what little review I'm > I have not seen any significant new development since v7 of these patches. > My comments for v6 were mostly[1] addressed and I can live with these > changes, even develop this approach further if it gets merged. OK, so this sort of feedback is really useful - even a qualified Reviwed-by is useful. Total silence could mean anything. > However, as a general note I see a need for a generic ASoC hdmi codec > abstraction and I don't think this is generic enough. More of the audio > specific implementation and HDMI standard specific things should be pushed > away from the hdmi encoder driver (tda998x in this case) to the generic ASoC > side hdmi codec driver (or library). This is something I'm expecting, yes - what I don't have is a clear enough picture of how consistent the different hardware is in how it models these things. > [1] I personally do not like the hdmi_get_cdev() approach. I would rather go > with only a library for registering from ASoC codec component under the HDMI > encoder device or a completely separate device with only a reference to the > HDMI encoder. It does seem somewhat complicated, yes. I don't know if matches idioms for DRM somehow? -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: Digital signature URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/d14e34dd/attachment-0001.sig>
[Bug 83461] hdmi screen flicker/unusable
https://bugzilla.kernel.org/show_bug.cgi?id=83461 --- Comment #30 from Markus Gaugusch --- Additional info: With the (unmodified) patch applied, I get a message "Nonpreset Mode" displayed on my monitor when I turn it on. So I think the patch is not 100% correct ... -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 86635] Live for Speed and gallium nine, missing objects
https://bugs.freedesktop.org/show_bug.cgi?id=86635 --- Comment #6 from Balázs Vinarz --- after i updated the mesa package, every car has the normal color. thanks David, i think we can close the bug :) -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/f0c57cae/attachment.html>
[PATCH] drm: Move two seq_printf's outside of locked mutex
Jonas,
On Tue, Dec 30, 2014 at 10:54:26PM +0100, Jonas Lundqvist wrote:
> In drm_info.c: drm_bufs_info() and drm_vm_info() two seq_printf() was
> done unnecessarily while locking a mutex. This patch flips the order of
> the print and lock/unlock where applicable.
>
> Signed-off-by: Jonas Lundqvist
> ---
> drivers/gpu/drm/drm_info.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
> index 51efebd..981afe7 100644
> --- a/drivers/gpu/drm/drm_info.c
> +++ b/drivers/gpu/drm/drm_info.c
> @@ -81,11 +81,10 @@ int drm_vm_info(struct seq_file *m, void *data)
> _DRM_SCATTER_GATHER and _DRM_CONSISTENT */
> const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" };
> const char *type;
> - int i;
> + int i = 0;
>
> - mutex_lock(>struct_mutex);
> seq_printf(m, "slot offset size type flagsaddress
> mtrr\n\n");
> - i = 0;
> + mutex_lock(>struct_mutex);
> list_for_each_entry(r_list, >maplist, head) {
> map = r_list->map;
> if (!map)
> @@ -147,8 +146,8 @@ int drm_bufs_info(struct seq_file *m, void *data)
> seq_printf(m, "\n");
> seq_printf(m, " %d", dma->buflist[i]->list);
> }
> - seq_printf(m, "\n");
> mutex_unlock(>struct_mutex);
> + seq_printf(m, "\n");
> return 0;
> }
>
You changed 'i' but you didn't explain in your log message why you did this.
Does this change really improve anything? It may work the same with the
locks moved around. But if you look at the function as a whole, the
locks encapsulate the body of this function nicely. I like the original
design better.
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
--
- Jeremiah Mahler
[PULL] drm-intel-next-fixes
Hi Dave - I've had these since before -rc1, but they missed my last pull request. Real bug fixes and mostly cc: stable material. I'll keep sending pull requests regardless of any holidays you may have in case you have a window to pull. Happy new year, Jani. The following changes since commit 2c550183476dfa25641309ae9a28d30feed14379: drm/i915: Disable PSMI sleep messages on all rings around context switches (2014-12-16 15:07:53 +0200) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-fixes-2014-12-30 for you to fetch changes up to 5d77d9c5e177d2182df5d9fd61ba986facb64415: drm/i915: add missing rpm ref to i915_gem_pwrite_ioctl (2014-12-18 15:46:47 +0200) Imre Deak (1): drm/i915: add missing rpm ref to i915_gem_pwrite_ioctl Ville Syrjälä (3): drm/i915: Kill check_power_well() calls drm/i915: Don't call intel_prepare_page_flip() multiple times on gen2-4 Revert "drm/i915: Preserve VGACNTR bits from the BIOS" drivers/gpu/drm/i915/i915_drv.h | 2 -- drivers/gpu/drm/i915/i915_gem.c | 8 +++- drivers/gpu/drm/i915/i915_irq.c | 6 ++ drivers/gpu/drm/i915/intel_display.c| 8 +--- drivers/gpu/drm/i915/intel_runtime_pm.c | 27 --- 5 files changed, 10 insertions(+), 41 deletions(-) -- Jani Nikula, Intel Open Source Technology Center
[RFC 1/6] cec: add new driver for cec support.
On Tue, Dec 23, 2014 at 03:32:17PM +0100, Kamil Debski wrote: > +There are still a few todo's, the main one being the remote control support > +feature of CEC. I need to research if that should be implemented via the > +standard kernel remote control support. I guess a new rc driver type RC_DRIVER_CEC should be introduced (existing types are RC_DRIVER_IR_RAW and RC_DRIVER_SCANCODE). rc_register_device() should not register the sysfs attributes specific for IR, but register sysfs attributes for cec like a link to the device. In addition there should be a new rc_type protocol RC_TYPE_CEC; now rc_keydown_notimeout() can be called for each key press. I guess a new keymap should exist too. HTH Sean
[PATCH RFC v7 21/21] ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel
This patch adds support for Himax HX8369A panel. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the Himax HX8369A panel driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * Add the HIMAX prefix in the Kconfig name. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3e0e589..27db91b 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,6 +192,7 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_HIMAX_HX8369A=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -- 2.1.0
[PATCH RFC v7 20/21] ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller. The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm menuconfig and manually choose to build in the MIPI DSI host controller driver * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0dbd0c3..3e0e589 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -199,6 +199,7 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3=y CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_MIPI_DSI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -- 2.1.0
[PATCH RFC v7 19/21] ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging
The new imx_v6_v7_defconfig is generated in this way: * make ARCH=arm imx_v6_v7_defconfig * make ARCH=arm savedefconfig * cp defconfig arch/arm/configs/imx_v6_v7_defconfig Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. arch/arm/configs/imx_v6_v7_defconfig | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6790f1b..0dbd0c3 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -192,7 +192,13 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_IPUV3=y +CONFIG_DRM_IMX_HDMI=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -249,13 +255,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y -- 2.1.0
[PATCH RFC v7 18/21] ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Replace the bs[3:0]-gpios properties with the bs-gpios property.
This addresses Andrzej Hajda's comment.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* To address Thierry Reding's comments, remove several unnecessary
properties as they can be implied by the compatible string.
* Fix the compatible string.
* Remove the display-timings node from the panel node as it can be
implied by the compatible string as well.
* Remove the status property as it is unneeded.
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index baf2f00..4e3a666 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -482,6 +482,13 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
+
+ pinctrl_mipi_panel: mipipanelgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ >;
+ };
};
gpio_leds {
@@ -518,6 +525,19 @@
};
};
+_dsi {
+ status = "okay";
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ bs-gpios = <0>, <0>, < 14 GPIO_ACTIVE_HIGH>, <0>;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pcie>;
--
2.1.0
[PATCH RFC v7 17/21] ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v3->v4:
* None.
v2->v3:
* As suggested by Phillip Zabel, change the clocks and the clock-names
properties to use the pllref and core_cfg clocks only.
v1->v2:
* None.
arch/arm/boot/dts/imx6qdl.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 96bf2a0..7b1c313 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1006,7 +1006,13 @@
mipi_dsi: mipi at 021e {
#address-cells = <1>;
#size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_CORE_CFG>;
+ clock-names = "pllref", "core_cfg";
status = "disabled";
ports {
--
2.1.0
[PATCH RFC v7 16/21] drm: panel: Add support for Himax HX8369A MIPI DSI panel
This patch adds support for Himax HX8369A MIPI DSI panel.
Reviewed-by: Andrzej Hajda
Signed-off-by: Liu Ying
---
v6->v7:
* Address Andrzej Hajda's following comments.
* Simplify the return logic in hx8369a_dcs_write().
* Replace the macro hx8369a_dsi_init_helper() with a function array to improve
the code quality.
* Handle error cases during getting gpios in probe().
* Add 'Reviewed-by: Andrzej Hajda '.
v5->v6:
* Make the checkpatch.pl script be happier.
* Do not set the dsi channel number to be zero in probe(), because the MIPI DSI
bus driver would set it.
v4->v5:
* Address Andrzej Hajda's comments.
* Get the bs-gpios property instead of the bs[3:0]-gpios properties.
* Implement error propagation for panel register configurations.
* Other minor changes to improve the code quality.
v3->v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2->v3:
* Sort the included header files alphabetically.
v1->v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and driver name.
* Move the driver's Makefile entry place to sort the entries alphabetically.
* Reuse several standard DCS functions instead of inventing wheels.
* Move the panel resetting and power logics to the driver probe/remove stages.
This may simplify panel prepare/unprepare hooks. The power consumption should
not change a lot at DPMS since the panel enters sleep mode at that time.
* Add the module author.
* Other minor changes, such as coding style issues.
drivers/gpu/drm/panel/Kconfig | 5 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-himax-hx8369a.c | 614
3 files changed, 620 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 024e98e..81b0bf0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -16,6 +16,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes into a
low power state.
+config DRM_PANEL_HIMAX_HX8369A
+ tristate "Himax HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+
config DRM_PANEL_LD9040
tristate "LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d5dbe06 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HIMAX_HX8369A) += panel-himax-hx8369a.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8369a.c
b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
new file mode 100644
index 000..dd3b604
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
@@ -0,0 +1,614 @@
+/*
+ * Himax HX8369A panel driver.
+ *
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on Samsung s6e8aa0 panel driver.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define WRDISBV0x51
+#define WRCTRLD0x53
+#define WRCABC 0x55
+#define SETPOWER 0xb1
+#define SETDISP0xb2
+#define SETCYC 0xb4
+#define SETVCOM0xb6
+#define SETEXTC0xb9
+#define SETMIPI0xba
+#define SETPANEL 0xcc
+#define SETGIP 0xd5
+#define SETGAMMA 0xe0
+
+#define HX8369A_MIN_BRIGHTNESS 0x00
+#define HX8369A_MAX_BRIGHTNESS 0xff
+
+enum hx8369a_mpu_interface {
+ HX8369A_DBI_TYPE_A_8BIT,
+ HX8369A_DBI_TYPE_A_9BIT,
+ HX8369A_DBI_TYPE_A_16BIT,
+ HX8369A_DBI_TYPE_A_18BIT,
+ HX8369A_DBI_TYPE_B_8BIT,
+ HX8369A_DBI_TYPE_B_9BIT,
+ HX8369A_DBI_TYPE_B_16BIT,
+ HX8369A_DBI_TYPE_B_18BIT,
+ HX8369A_DSI_CMD_MODE,
+ HX8369A_DBI_TYPE_B_24BIT,
+ HX8369A_DSI_VIDEO_MODE,
+ HX8369A_MDDI,
+ HX8369A_DPI_DBI_TYPE_C_OPT1,
+ HX8369A_DPI_DBI_TYPE_C_OPT2,
+ HX8369A_DPI_DBI_TYPE_C_OPT3
+};
+
+enum hx8369a_resolution {
+ HX8369A_RES_480_864,
+ HX8369A_RES_480_854,
+ HX8369A_RES_480_800,
+ HX8369A_RES_480_640,
+ HX8369A_RES_360_640,
+ HX8369A_RES_480_720,
+};
+
+struct hx8369a_panel_desc {
+ const struct drm_display_mode *mode;
+
+ /* ms */
+ unsigned int
[PATCH RFC v7 15/21] Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver
This patch adds device tree bindings for Himax HX8369A DRM panel driver.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Merge the bs[3:0]-gpios properties into one property - bs-gpios.
This addresses Andrzej Hajda's comment.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/panel/himax,hx8369a.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/himax,hx8369a.txt
diff --git a/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
new file mode 100644
index 000..3a44b70
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/himax,hx8369a.txt
@@ -0,0 +1,39 @@
+Himax HX8369A WVGA 16.7M color TFT single chip driver with internal GRAM
+
+Himax HX8369A is a WVGA resolution driving controller.
+It is designed to provide a single chip solution that combines a source
+driver and power supply circuits to drive a TFT dot matrix LCD with
+480RGBx864 dots at the maximum.
+
+The HX8369A supports several interface modes, including MPU MIPI DBI Type
+A/B mode, MIPI DPI/DBI Type C mode, MIPI DSI video mode, MIPI DSI command
+mode and MDDI mode. The interface mode is selected by the external hardware
+pins BS[3:0].
+
+Currently, only the MIPI DSI video mode is supported.
+
+Required properties:
+ - compatible: should be a panel's compatible string
+ - reg: the virtual channel number of a DSI peripheral, as described in [1]
+ - reset-gpios: a GPIO spec for the reset pin, as described in [2]
+
+Optional properties:
+ - vdd1-supply: I/O and interface power supply
+ - vdd2-supply: analog power supply
+ - vdd3-supply: logic power supply
+ - dsi-vcc-supply: DSI and MDDI power supply
+ - vpp-supply: OTP programming voltage
+ - bs-gpios: a GPIO spec for the pins BS[3:0], as described in [2]
+
+[1] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[2] Documentation/devicetree/bindings/gpio/gpio.txt
+
+Example:
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_mipi_panel>;
+ reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ bs-gpios = <0>, <0>, < 14 GPIO_ACTIVE_HIGH>, <0>;
+ };
--
2.1.0
[PATCH RFC v7 14/21] drm: imx: Support Synopsys DesignWare MIPI DSI host controller
This patch adds support for Synopsys DesignWare MIPI DSI host controller
which is embedded in the i.MX6q/sdl SoCs.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* Make the checkpatch.pl script be happier.
v4->v5:
* None.
v3->v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2->v3:
* To address Andy Yan's comments, move the common Synopsys DesignWare MIPI DSI
host controller logic into it's drm/bridge driver and leave the i.MX specific
logic only.
v1->v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node in the panel
node.
* Update the DT documentation to state that the nodes which represent the
possible
DRM CRTCs the controller may connect with should be placed in the node
"ports".
* Remove the flag 'enabled' from the struct imx_mipi_dsi.
* Move the format_to_bpp() function in v1 to the common DRM MIPI DSI driver.
* Improve the way we wait for check status for DPHY and command packet
transfer.
* Improve the DPMS support for the encoder.
* Split the functions of ->host_attach() and ->mode_valid() clearly as
suggested by
Thierry Reding.
* Improve the logics in imx_mipi_dsi_dcs_long_write().
* Enable/disable the pllref_clk and pllref_gate_clk at the component
binding/unbinding
stages to help remove the flag 'enabled'.
* Update the module license to be "GPL".
* Other minor changes, such as coding style issues and macro naming issues.
drivers/gpu/drm/imx/Kconfig | 7 ++
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 ++
3 files changed, 238 insertions(+)
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 82fb758..c576f6b 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -51,3 +51,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX_MIPI_DSI
+ tristate "Freescale i.MX DRM MIPI DSI"
+ select DRM_DW_MIPI_DSI
+ depends on DRM_IMX
+ help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 582c438..f0dc278 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
obj-$(CONFIG_DRM_IMX_IPUV3)+= imx-ipuv3-crtc.o
obj-$(CONFIG_DRM_IMX_HDMI) += imx-hdmi.o
+obj-$(CONFIG_DRM_IMX_MIPI_DSI) += dw_mipi_dsi-imx.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
new file mode 100644
index 000..b2c96e2
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx.c
@@ -0,0 +1,230 @@
+/*
+ * i.MX drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "imx-drm.h"
+
+#define DRIVER_NAME"imx-mipi-dsi"
+
+struct imx_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+ regmap_update_bits(dsi->regmap, IOMUXC_GPR3,
+ IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+ ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+ .destroy = imx_drm_encoder_destroy,
+};
+
+static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void imx_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = V4L2_PIX_FMT_RGB24;
+
[PATCH RFC v7 13/21] Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver
This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI
driver.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless pllref_gate clock from the required clocks, clock-names
property.
v4->v5:
* None.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
new file mode 100644
index 000..75a7766
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt
@@ -0,0 +1,78 @@
+i.MX specific Device-Tree bindings for Synopsys DesignWare MIPI DSI host
controller
+
+MIPI DSI host controller
+
+
+The MIPI DSI host controller is a Synopsys DesignWare IP.
+The common device tree documentation for this controller can be found
+at [1].
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs.
+ - reg: Physical base address of the controller and length of memory
+ mapped region.
+ - interrupts: The controller's interrupt number to the CPU(s).
+ - gpr: Should be <>.
+ The phandle points to the iomuxc-gpr region containing the
+ multiplexer control register for the controller.
+ - clocks, clock-names: Phandles to the controller pllref and core_cfg clocks,
+ as described in [2] and [3].
+
+Required sub-nodes:
+ - ports: This node may contain up to four port nodes with endpoint
+ definitions as defined in [4], corresponding to the four inputs to
+ the controller multiplexer.
+ - A node to represent a DSI peripheral as described in [5].
+
+[1] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt.
+[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[3] Documentation/devicetree/bindings/clock/imx6q-clock.txt
+[4] Documentation/devicetree/bindings/media/video-interfaces.txt
+[5] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr at 020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi at 021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_CORE_CFG>;
+ clock-names = "pllref", "core_cfg";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.1.0
[PATCH RFC v7 12/21] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
This patch adds Synopsys DesignWare MIPI DSI host controller driver support. Currently, the driver supports the burst with sync pulses mode only. Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * Make the checkpatch.pl script be happier. v4->v5: * Remove 'dsi->panel = NULL;' in dw_mipi_dsi_host_detach() to address Andrzej Hajda's comment. v3->v4: * Move the relevant dt-bindings to a separate patch to address Stefan Wahren's comment. v2->v3: * Newly introduced in v3 to address Andy Yan's comment. This is based on the i.MX MIPI DSI driver in v2. To make the Synopsys DesignWare MIPI DSI host controller driver less platform-dependant, this patch places it at the drm/bridge directory as a DRM bridge driver. drivers/gpu/drm/bridge/Kconfig | 5 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 996 +++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1029 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 884923f..8180477 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -1,3 +1,8 @@ +config DRM_DW_MIPI_DSI + bool "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + config DRM_PTN3460 tristate "PTN3460 DP/LVDS bridge" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index b4733e1..b326ad5 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,3 +1,4 @@ ccflags-y := -Iinclude/drm +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_DRM_PTN3460) += ptn3460.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..2b54d44 --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,996 @@ +/* + * Synopsys DesignWare(DW) MIPI DSI Host Controller + * + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_CFG0x0c +#define EN18_LOOSELY BIT(10) +#define COLORM_ACTIVE_LOW BIT(9) +#define SHUTD_ACTIVE_LOW BIT(8) +#define HSYNC_ACTIVE_LOW BIT(7) +#define VSYNC_ACTIVE_LOW BIT(6) +#define DATAEN_ACTIVE_LOW BIT(5) +#define DPI_COLOR_CODING_16BIT_1 (0x0 << 2) +#define DPI_COLOR_CODING_16BIT_2 (0x1 << 2) +#define DPI_COLOR_CODING_16BIT_3 (0x2 << 2) +#define DPI_COLOR_CODING_18BIT_1 (0x3 << 2) +#define DPI_COLOR_CODING_18BIT_2 (0x4 << 2) +#define DPI_COLOR_CODING_24BIT (0x5 << 2) +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DBI_CFG0x10 +#define DSI_DBIS_CMDSIZE 0x14 + +#define DSI_PCKHDL_CFG 0x18 +#define GEN_VID_RX(vid)(((vid) & 0x3) << 5) +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTN_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_VID_MODE_CFG 0x1c +#define FRAME_BTA_ACK BIT(11) +#define EN_NULL_PKTBIT(10) +#define EN_NULL_PKT_MASK BIT(10) +#define EN_MULTI_PKT BIT(9) +#define ENABLE_LOW_POWER (0x3f << 3) +#define ENABLE_LOW_POWER_MASK (0x3f << 3) +#define VID_MODE_TYPE_NONBURST_SYNC_PULSES (0x0 << 1) +#define VID_MODE_TYPE_NONBURST_SYNC_EVENTS (0x1 << 1) +#define VID_MODE_TYPE_BURST_SYNC_PULSES(0x3 << 1) +#define VID_MODE_TYPE_MASK (0x3 << 1) +#define ENABLE_VIDEO_MODE BIT(0) +#define DISABLE_VIDEO_MODE 0 +#define
[PATCH RFC v7 11/21] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless input-port properties from the example port at 0 and port
at 1
nodes.
v4->v5:
* None.
v3->v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..f88a8d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,73 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The compatible string should be "fsl,imx6q-mipi-dsi" for
+ i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller pll reference and
+ core configuration clocks, as described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr at 020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi at 021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpr = <>;
+ clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_CORE_CFG>;
+ clock-names = "pllref", "core_cfg";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.1.0
[PATCH RFC v7 10/21] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.1.0
[PATCH RFC v7 09/21] ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripheral device. This patch moves the existing MIPI DSI ports into
a new 'ports' node so that the MIPI DSI bus driver may distinguish its
DSI peripheral device(s) from the existing ports.
Acked-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Add Philipp's Ack.
v1->v2:
* Newly added, as suggested by Thierry Reding.
arch/arm/boot/dts/imx6q.dtsi | 20 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 23 ++-
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646..9c0990b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -292,19 +292,21 @@
};
_dsi {
- port at 2 {
- reg = <2>;
+ ports {
+ port at 2 {
+ reg = <2>;
- mipi_mux_2: endpoint {
- remote-endpoint = <_di0_mipi>;
+ mipi_mux_2: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
};
- };
- port at 3 {
- reg = <3>;
+ port at 3 {
+ reg = <3>;
- mipi_mux_3: endpoint {
- remote-endpoint = <_di1_mipi>;
+ mipi_mux_3: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5..96bf2a0 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1009,19 +1009,24 @@
reg = <0x021e 0x4000>;
status = "disabled";
- port at 0 {
- reg = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
- mipi_mux_0: endpoint {
- remote-endpoint =
<_di0_mipi>;
+ mipi_mux_0: endpoint {
+ remote-endpoint =
<_di0_mipi>;
+ };
};
- };
- port at 1 {
- reg = <1>;
+ port at 1 {
+ reg = <1>;
- mipi_mux_1: endpoint {
- remote-endpoint =
<_di1_mipi>;
+ mipi_mux_1: endpoint {
+ remote-endpoint =
<_di1_mipi>;
+ };
};
};
};
--
2.1.0
[PATCH RFC v7 08/21] ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock. In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* Add two spaces in the clock driver to eliminate two errors reported by
the checkpatch.pl script.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 080d5b7..0f4d07c 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -418,6 +418,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1",
"ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1",
"ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx",
"hsi_tx_podf", base + 0x74, 16, _count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg",
"video_27m", base + 0x74, 16, _count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index 25625bf..dbc828c 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -249,6 +249,7 @@
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_VIDEO_27M 238
-#define IMX6QDL_CLK_END239
+#define IMX6QDL_CLK_MIPI_CORE_CFG 239
+#define IMX6QDL_CLK_END240
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
[PATCH RFC v7 07/21] ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a shared clock gate.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f19472a..080d5b7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
+static unsigned int share_count_mipi_core_cfg;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
@@ -416,7 +417,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0",
"ldb_di0_podf", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1",
"ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1",
"ipu2_di1_sel", base + 0x74, 10);
- clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx",
"hsi_tx_podf", base + 0x74, 16);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx",
"hsi_tx_podf", base + 0x74, 16, _count_mipi_core_cfg);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
--
2.1.0
[PATCH RFC v7 06/21] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
clock's parent should be the video_27m clock. The i.MX6DL reference manual
has the same statement. This patch changes the hdmi_isfr clock's parent
from the pll3_pfd1_540m clock to the video_27m clock.
Suggested-by: Philipp Zabel
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* Newly introduced in v3.
arch/arm/mach-imx/clk-imx6q.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 9470df3..f19472a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -401,7 +401,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core",
"gpu2d_core_podf", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core",
"gpu3d_core_podf", base + 0x6c, 26);
clk[IMX6QDL_CLK_HDMI_IAHB]= imx_clk_gate2("hdmi_iahb", "ahb",
base + 0x70, 0);
- clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2("hdmi_isfr",
"pll3_pfd1_540m",base + 0x70, 4);
+ clk[IMX6QDL_CLK_HDMI_ISFR]= imx_clk_gate2("hdmi_isfr",
"video_27m", base + 0x70, 4);
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1",
"ipg_per", base + 0x70, 6);
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2",
"ipg_per", base + 0x70, 8);
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3",
"ipg_per", base + 0x70, 10);
--
2.1.0
[PATCH RFC v7 05/21] ARM: imx6q: clk: Add the video_27m clock
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7..9470df3 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -246,6 +246,7 @@ static void __init imx6q_clocks_init(struct device_node
*ccm_node)
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m",
"pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm",
1, 2);
clk[IMX6QDL_CLK_GPT_3M]= imx_clk_fixed_factor("gpt_3m","osc",
1, 8);
+ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m",
"pll3_pfd1_540m", 1, 20);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi",
"mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi",
"mmdc_ch0_axi_podf", 1, 1);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h
b/include/dt-bindings/clock/imx6qdl-clock.h
index b690cdb..25625bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -248,6 +248,7 @@
#define IMX6QDL_PLL6_BYPASS235
#define IMX6QDL_PLL7_BYPASS236
#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_END238
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_END239
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.0
[PATCH RFC v7 04/21] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field shift bits. Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index ff44374..3b0bed4 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -207,6 +207,7 @@ #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) +#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) -- 2.1.0
[PATCH RFC v7 03/21] of: Add vendor prefix for Truly Semiconductors Limited
Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * None. v1->v2: * None. Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index f46adb2..0e67bad 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -158,6 +158,7 @@ tlm Trusted Logic Mobility toradexToradex AG toshibaToshiba Corporation toumaz Toumaz +truly Truly Semiconductors Limited usiUniversal Scientific Industrial Co., Ltd. v3 V3 Semiconductor variscite Variscite Ltd. -- 2.1.0
[PATCH RFC v7 02/21] of: Add vendor prefix for Himax Technologies Inc.
Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * Fix an ordering issue to address Stefan Wahren's comment. v2->v3: * None. v1->v2: * None. Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 78efebb..f46adb2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -67,6 +67,7 @@ gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. +himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hitHitachi Ltd. honeywell Honeywell -- 2.1.0
[PATCH RFC v7 01/21] clk: divider: Correct parent clk round rate if no bestdiv is normally found
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
---
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
drivers/clk/clk-divider.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b..f641d4b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(divider);
- *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
1);
+ *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ MULT_ROUND_UP(rate, bestdiv));
}
return bestdiv;
--
2.1.0
[PATCH RFC v7 00/21] Add support for i.MX MIPI DSI DRM driver
Hi, This version addresses some comments from Andrzej Hajda on v6. The comments are only for the Himax HX8369A DRM panel driver(PATCH 16/21). The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a i.MX MIPI DSI specific DRM driver. Currently, the MIPI DSI drivers only support the burst with sync pulse mode. This series also includes a DRM panel driver for the Truly TFT480800-16-E panel which is driven by the Himax HX8369A driver IC. The driver IC data sheet could be found at [1]. As mentioned by the data sheet, the driver IC supports several interface modes. Currently, the DRM panel driver only supports the MIPI DSI video mode. New interface modes could be added later(perhaps, just like the way the DRM simple panel driver supports both MIPI DSI interface panels and simple(parallel) interface panels). The MIPI DSI feature is tested on i.MX6Q SabreSD board and i.MX6DL SabreSD board. The MIPI DSI display could be enabled directly on i.MX6Q SabreSD board after applying this series, because the 26.4MHz pixel clock the panel requires could be derived from the IPU HSP clock(264MHz) with an integer divider. On i.MX6DL SabreSD board, we need to manually disable the LVDS and HDMI displays in the device tree blob, since the i.MX6DL IPU HSP clock is 198MHz at present, which makes the pixel clock share the PLL5 video clock source with the LVDS and HDMI, thus, the panel cannot get the pixel clock rate it wants. Patch 01/21 is needed to get a precise pixel clock rate(26.4MHz) from the PLL5 video clock. If we don't have this patch, the pixel clock rate is about 20MHz, which causes a horitonal shift on the display image. This series can be applied on the drm-next branch. [1] http://www.allshore.com/pdf/Himax_HX8369-A.pdf Liu Ying (21): clk: divider: Correct parent clk round rate if no bestdiv is normally found of: Add vendor prefix for Himax Technologies Inc. of: Add vendor prefix for Truly Semiconductors Limited ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: dts: imx6qdl: Move existing MIPI DSI ports into a new 'ports' node drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver drm: imx: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for Himax HX8369A DRM panel driver drm: panel: Add support for Himax HX8369A MIPI DSI panel ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller ARM: dts: imx6qdl-sabresd: Add support for TRULY TFT480800-16-E MIPI DSI panel ARM: imx_v6_v7_defconfig: Cleanup for imx drm being moved out of staging ARM: imx_v6_v7_defconfig: Add support for MIPI DSI host controller ARM: imx_v6_v7_defconfig: Add support for Himax HX8369A panel .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 73 ++ .../devicetree/bindings/drm/imx/mipi_dsi.txt | 78 ++ .../devicetree/bindings/panel/himax,hx8369a.txt| 39 + .../devicetree/bindings/vendor-prefixes.txt| 2 + arch/arm/boot/dts/imx6q.dtsi | 20 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 20 + arch/arm/boot/dts/imx6qdl.dtsi | 29 +- arch/arm/configs/imx_v6_v7_defconfig | 17 +- arch/arm/mach-imx/clk-imx6q.c | 7 +- drivers/clk/clk-divider.c | 3 +- drivers/gpu/drm/bridge/Kconfig | 5 + drivers/gpu/drm/bridge/Makefile| 1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 996 + drivers/gpu/drm/imx/Kconfig| 7 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 230 + drivers/gpu/drm/panel/Kconfig | 5 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-himax-hx8369a.c| 614 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/imx6qdl-clock.h | 4 +- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h| 1 + 23 files changed, 2164 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt create mode 100644
[PATCH RFC v6 16/21] drm: panel: Add support for Himax HX8369A MIPI DSI panel
On 12/29/2014 06:50 PM, Andrzej Hajda wrote:
> On 12/29/2014 11:07 AM, Liu Ying wrote:
>> On 12/29/2014 05:09 PM, Andrzej Hajda wrote:
>>> On 12/29/2014 07:39 AM, Liu Ying wrote:
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying
---
v5->v6:
* Make the checkpatch.pl script be happier.
* Do not set the dsi channel number to be zero in probe(), because the
MIPI DSI
bus driver would set it.
v4->v5:
* Address Andrzej Hajda's comments.
* Get the bs-gpios property instead of the bs[3:0]-gpios properties.
* Implement error propagation for panel register configurations.
* Other minor changes to improve the code quality.
v3->v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2->v3:
* Sort the included header files alphabetically.
v1->v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible
string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and driver
name.
* Move the driver's Makefile entry place to sort the entries
alphabetically.
* Reuse several standard DCS functions instead of inventing wheels.
* Move the panel resetting and power logics to the driver probe/remove
stages.
This may simplify panel prepare/unprepare hooks. The power
consumption should
not change a lot at DPMS since the panel enters sleep mode at that
time.
* Add the module author.
* Other minor changes, such as coding style issues.
drivers/gpu/drm/panel/Kconfig | 5 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-himax-hx8369a.c | 614
3 files changed, 620 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8369a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 024e98e..81b0bf0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -16,6 +16,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes
into a
low power state.
+config DRM_PANEL_HIMAX_HX8369A
+ tristate "Himax HX8369A panel"
+ depends on OF
+ select DRM_MIPI_DSI
+
config DRM_PANEL_LD9040
tristate "LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile
b/drivers/gpu/drm/panel/Makefile
index 4b2a043..d5dbe06 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HIMAX_HX8369A) += panel-himax-hx8369a.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
diff --git a/drivers/gpu/drm/panel/panel-himax-hx8369a.c
b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
new file mode 100644
index 000..eee36a7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-himax-hx8369a.c
@@ -0,0 +1,614 @@
+/*
+ * Himax HX8369A panel driver.
+ *
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on Samsung s6e8aa0 panel driver.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define WRDISBV 0x51
+#define WRCTRLD 0x53
+#define WRCABC0x55
+#define SETPOWER 0xb1
+#define SETDISP 0xb2
+#define SETCYC0xb4
+#define SETVCOM 0xb6
+#define SETEXTC 0xb9
+#define SETMIPI 0xba
+#define SETPANEL 0xcc
+#define SETGIP0xd5
+#define SETGAMMA 0xe0
+
+#define HX8369A_MIN_BRIGHTNESS0x00
+#define HX8369A_MAX_BRIGHTNESS0xff
+
+enum hx8369a_mpu_interface {
+ HX8369A_DBI_TYPE_A_8BIT,
+ HX8369A_DBI_TYPE_A_9BIT,
+ HX8369A_DBI_TYPE_A_16BIT,
+ HX8369A_DBI_TYPE_A_18BIT,
+ HX8369A_DBI_TYPE_B_8BIT,
+ HX8369A_DBI_TYPE_B_9BIT,
+ HX8369A_DBI_TYPE_B_16BIT,
+ HX8369A_DBI_TYPE_B_18BIT,
+ HX8369A_DSI_CMD_MODE,
+
[Bug 72710] rv635: resume from hibernation the second time fails
https://bugs.freedesktop.org/show_bug.cgi?id=72710 Harald Judt changed: What|Removed |Added Summary|rv635: resume fails |rv635: resume from ||hibernation the second time ||fails --- Comment #3 from Harald Judt --- Status update: After updating to 3.18.1 vanilla and booting with radeon.dpm=0, suspend/resume now works reliably. Hibernating/resuming still fails, but only and always on the second cycle, the first cycle seems to work fine now: 1) Boot with radeon.dpm=0 (radeon.dpm=1 seems to have its own stability troubles) 2) hibernate 3) resume 4) hibernate 5) resume => kernel panic after loading pages (counting from 0% to 100%). It seems the kernel panics when trying to switch back to the X screen. Unfortunately, I am for some reason no longer able to boot with a 3.6/3.7 kernel (maybe because of an udev problem), so I cannot bisect - and I am not sure any 3.6 kernels worked reliably before because I remember it had issues too. I've tried to suspend/resume between the hibernation cycles, but that does not change anything; hibernate/resume will still fail on the second resume attempt. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/25b2aefa/attachment-0001.html>
[Bug 64471] Radeon HD6570 lockup in Brütal Legend with HyperZ
https://bugs.freedesktop.org/show_bug.cgi?id=64471 --- Comment #29 from Clément Guérin --- Woops, sorry, this is out of place. Should I open another bug in the radeonsi section? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/c6dc7e97/attachment.html>
[Bug 85207] agd5f drm-next-3.19-wip + Unreal Elemental sometimes = list_add corruption/hung task
https://bugs.freedesktop.org/show_bug.cgi?id=85207 --- Comment #10 from Lorenzo Bona --- I found same issues here. [ 1384.901951] [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-512) [ 1453.198866] [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-512) [ 2215.773607] [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-512) [ 2351.238014] [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-512) [ 3877.903397] [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-512) Self compiled kernel from Linus git. 3.19-rc2+ right now. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/b99e02f2/attachment.html>
[Bug 87856] Driver load fails with no error on ppc64 host
https://bugs.freedesktop.org/show_bug.cgi?id=87856 65a changed: What|Removed |Added OS|All |Linux (All) -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/ec245d9b/attachment.html>
[Bug 87856] Driver load fails with no error on ppc64 host
https://bugs.freedesktop.org/show_bug.cgi?id=87856 65a changed: What|Removed |Added Hardware|Other |PowerPC -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/7593067d/attachment.html>
[Bug 87856] Driver load fails with no error on ppc64 host
https://bugs.freedesktop.org/show_bug.cgi?id=87856 Bug ID: 87856 Summary: Driver load fails with no error on ppc64 host Product: Mesa Version: 10.2 Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/r600 Assignee: dri-devel at lists.freedesktop.org Reporter: freedesktopbugs at 63bit.net Created attachment 111507 --> https://bugs.freedesktop.org/attachment.cgi?id=111507=edit Xorg log, dmesg | fgrep radeon, and glxinfo with LIBGL_DEBUG set I have a PowerPC G5 (ppc64 with 64-bit userland) with working KMS using a (ostensibly x86) Radeon HD4650. KMS is enabled and the kernel and Xorg parts of KMS/DRI2 appear to be attaching correctly. After X starts, running LIBGL_DEBUG=verbose glxinfo outputs the following: libGL: OpenDriver: trying /usr/lib64/dri/tls/r600_dri.so libGL: OpenDriver: trying /usr/lib64/dri/r600_dri.so libGL: driver does not expose __driDriverGetExtensions_r600(): /usr/lib64/dri/r600_dri.so: undefined symbol: __driDriverGetExtensions_r600 libGL: Can't open configuration file /root/.drirc: No such file or directory. libGL: Can't open configuration file /root/.drirc: No such file or directory. libGL error: failed to load driver: r600 libGL: OpenDriver: trying /usr/lib64/dri/tls/swrast_dri.so libGL: OpenDriver: trying /usr/lib64/dri/swrast_dri.so libGL: driver does not expose __driDriverGetExtensions_swrast(): /usr/lib64/dri/swrast_dri.so: undefined symbol: __driDriverGetExtensions_swrast libGL: Can't open configuration file /root/.drirc: No such file or directory. libGL: Can't open configuration file /root/.drirc: No such file or directory. libGL error: failed to load driver: swrast Error: couldn't find RGB GLX visual or fbconfig Error: couldn't find RGB GLX visual or fbconfig I am under the impression that the undefined symbol should not be causing problems after reading this bug: https://bugs.freedesktop.org/show_bug.cgi?id=72198 Nonetheless, glxgears will not run, and in general it appears mesa acceleration is not occurring. Mesa was compiled with support for llvm and the r600 generator. I am attaching various logs. I would be glad to test patches or hacks :) -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/07d9efc0/attachment.html>
[Bug 87278] Packet0 not allowed and GPU fault detected errors with Serious Engine games
https://bugs.freedesktop.org/show_bug.cgi?id=87278 --- Comment #14 from Alexandre Demers --- (In reply to Alexandre Demers from comment #13) > Created attachment 111430 [details] > VM faults and Packet0 error when quitting the current game > > on R9 270X with today's latest mesa, drm, ddx from git repositories and > kernel 3.19-rc1 Patch tested and I get the same error as before, as Christoph. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/e0a0f30e/attachment-0001.html>
[Bug 66963] Rv6xx dpm problems
https://bugs.freedesktop.org/show_bug.cgi?id=66963 --- Comment #250 from Kajzer --- With kernels 3.17 and 3.18 I have freezes when playing some games, those freezes can happen somewhere between 10 minutes and 1 hour. Freeze occur only in games. With kernel 3.16 everything is normal and there are no freezes. Latest patch (auto->high and radeon.dpm=1) is used in each of those kernels. Everything else is exactly the same, just booting with different kernel makes a difference. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20141230/ce77eb63/attachment.html>
