[Bug 94679] DAL DCE 10 missing CEA interlaced modes

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94679

Bug ID: 94679
   Summary: DAL  DCE 10 missing CEA interlaced modes
   Product: DRI
   Version: DRI git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: DRM/AMDgpu
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: adf.lists at gmail.com

I don't know if this is a bug or a feature request :-)

Testing R9285 Tonga + various agd5f DAL kernels I notice that the CEA
interlaced modes of my HDMI connected TV are missing.

With "normal" kernels they are listed and though not perfect (or not working at
all in the double clocked cases) I did use one of them sometimes as it let me
use my TVs de-interlacer.

fglrx has all interlaced modes working for my TV, so I was hopeful that DAL
would have also had them.

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/a95e35b9/attachment-0001.html>

[Bug 86351] HDMI audio garbled output on Radeon R9 280X

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=86351

--- Comment #23 from Andy Furniss  ---
I don't have a 270X anymore which I was using when first commenting in this
bug.

My current R9285 Tonga also has this issue and I've just tried setting 2048
(runtime) for prealloc and it doesn't help me.

I do think this is a sound driver issue though as pulse audio works, though it
was a different test = with fglrx the issue is also present when using alsa but
not pulse.

The difference seems to be that alsa direct uses

SND_PCM_ACCESS_RW_INTERLEAVED

and via pulse it uses

SND_PCM_ACCESS_MMAP_INTERLEAVED

-- 
You are receiving this mail because:
You are watching the assignee of the bug.

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94671

--- Comment #7 from Nicolai H�hnle  ---
Hi Jan! First, please try this patch which fixes a similar bug:
https://patchwork.freedesktop.org/patch/78118/

If that doesn't fix the problem: I'd appreciate if you could upload the
apitrace somewhere (Dropbox, Google Drive, etc.). A diff is not going to be
useful.

But first, try if the problem is already fixed with the patch above :)

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/0a726922/attachment.html>

[Bug 86351] HDMI audio garbled output on Radeon R9 280X

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=86351

--- Comment #22 from Alex Deucher  ---
This should be re-assigned to the audio driver then.

-- 
You are receiving this mail because:
You are watching the assignee of the bug.

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94671

--- Comment #6 from Jan Ziak <0xe2.0x9a.0x9b at gmail.com> ---
(In reply to Nicolai H�hnle from comment #5)
> Thank you for the report.
> 
> I suspect some of the BGR <-> RGB changes for shader image bitcasts are
> responsible. Could one of you please provide an apitrace that shows the
> problem? That would be very helpful.

Running Shadow of Mordor under apitrace 6.1 is very slow. I didn't run the
benchmark because the ingame menu screen wasn't responding. However, the menu
screen already has the blue-ish tint that shouldn't be there.

The trace is quite large: 392 MB uncompressed, 219 MB compressed with xz.

Do you still want the trace despite its size?

If not, do you want me to run apitrace on AMD's Opengl library and then perform
"apitrace diff ShadowOfMordor-radeonsi.trace ShadowOfMordor-amd.trace"?

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/41572634/attachment-0001.html>

[Bug 86351] HDMI audio garbled output on Radeon R9 280X

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=86351

--- Comment #21 from Christian Birchinger  ---
I was under the impression, that i already gave feedback about the
"Pre-allocated buffer size" value, but i guess i did not.

Anyway, a value of 2048 seems to fix the issue. I've tried normal stereo,
DTS and DolbyD and the sound was fine and without dropouts.

So for me, the issue is solved and comment #17 is probably right too.

-- 
You are receiving this mail because:
You are watching the assignee of the bug.

[PATCH] drm: Add support for EDID injection.

[Marius Vlad]

Allow the possibility to return an copy of the injected EDID when the connector
has been forced and an EDID has been specified over the debugfs interface.

Signed-off-by: Marius Vlad 
---
 drivers/gpu/drm/drm_edid.c | 23 ---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 414d7f6..239f9b1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1075,6 +1075,19 @@ static bool drm_edid_is_zero(const u8 *in_edid, int 
length)
return true;
 }

+static struct edid *
+drm_do_get_override_edid(struct drm_connector *connector)
+{
+   struct edid *edid = NULL;
+
+   if (connector->override_edid && connector->edid_blob_ptr->data) {
+   edid = kmemdup(connector->edid_blob_ptr->data,
+  connector->edid_blob_ptr->length, GFP_KERNEL);
+   }
+
+   return edid;
+}
+
 /**
  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
  * @raw_edid: pointer to raw EDID block
@@ -1385,10 +1398,14 @@ struct edid *drm_get_edid(struct drm_connector 
*connector,
 {
struct edid *edid;

-   if (!drm_probe_ddc(adapter))
-   return NULL;
+   if (!connector->override_edid) {
+   if (!drm_probe_ddc(adapter))
+   return NULL;
+   edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, 
adapter);
+   } else {
+   edid = drm_do_get_override_edid(connector);
+   }

-   edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
if (edid)
drm_get_displayid(connector, edid);
return edid;
-- 
2.5.0

[Bug 80419] XCOM: Enemy Unknown Causes lockup

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=80419

--- Comment #126 from Nicolai H�hnle  ---
That's interesting, because r600 is a different user space OpenGL driver. It
might be an interaction with the DDX or kernel though.

If you cannot ssh from a different computer, you can still recover the log from
e.g. /var/log/kern.log (the exact location may depend on the distribution).

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/0eb36752/attachment-0001.html>

[RFC 1/5] drm: Add DRM support for tiny LCD displays

[David Herrmann]

Hey

On Wed, Mar 16, 2016 at 2:34 PM, Noralf Trønnes  wrote:
> tinydrm provides a very simplified view of DRM for displays that has
> onboard video memory and is connected through a slow bus like SPI/I2C.
>
> Signed-off-by: Noralf Trønnes 
> ---
>  drivers/gpu/drm/Kconfig|   2 +
>  drivers/gpu/drm/Makefile   |   1 +
>  drivers/gpu/drm/tinydrm/Kconfig|  11 +
>  drivers/gpu/drm/tinydrm/Makefile   |   1 +
>  drivers/gpu/drm/tinydrm/core/Makefile  |   8 +
>  drivers/gpu/drm/tinydrm/core/internal.h|  43 +++
>  drivers/gpu/drm/tinydrm/core/tinydrm-core.c| 194 
>  drivers/gpu/drm/tinydrm/core/tinydrm-crtc.c| 203 
>  drivers/gpu/drm/tinydrm/core/tinydrm-deferred.c| 116 +++
>  drivers/gpu/drm/tinydrm/core/tinydrm-fbdev.c   | 345 
> +
>  drivers/gpu/drm/tinydrm/core/tinydrm-framebuffer.c | 112 +++
>  drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c |  97 ++
>  drivers/gpu/drm/tinydrm/core/tinydrm-plane.c   |  50 +++
>  include/drm/tinydrm/tinydrm.h  | 142 +
>  14 files changed, 1325 insertions(+)
>  create mode 100644 drivers/gpu/drm/tinydrm/Kconfig
>  create mode 100644 drivers/gpu/drm/tinydrm/Makefile
>  create mode 100644 drivers/gpu/drm/tinydrm/core/Makefile
>  create mode 100644 drivers/gpu/drm/tinydrm/core/internal.h
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-core.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-crtc.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-deferred.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-fbdev.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-framebuffer.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c
>  create mode 100644 drivers/gpu/drm/tinydrm/core/tinydrm-plane.c
>  create mode 100644 include/drm/tinydrm/tinydrm.h
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index c4bf9a1..3f8ede0 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -266,3 +266,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig"
>  source "drivers/gpu/drm/imx/Kconfig"
>
>  source "drivers/gpu/drm/vc4/Kconfig"
> +
> +source "drivers/gpu/drm/tinydrm/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 1e9ff4c..c7c5c16 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -75,3 +75,4 @@ obj-y += i2c/
>  obj-y  += panel/
>  obj-y  += bridge/
>  obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
> +obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
> diff --git a/drivers/gpu/drm/tinydrm/Kconfig b/drivers/gpu/drm/tinydrm/Kconfig
> new file mode 100644
> index 000..f290045
> --- /dev/null
> +++ b/drivers/gpu/drm/tinydrm/Kconfig
> @@ -0,0 +1,11 @@
> +menuconfig DRM_TINYDRM
> +   tristate "Support for small TFT LCD display modules"
> +   depends on DRM
> +   select DRM_KMS_HELPER
> +   select DRM_KMS_CMA_HELPER
> +   select DRM_GEM_CMA_HELPER
> +   select DRM_PANEL
> +   select VIDEOMODE_HELPERS
> +   help
> + Choose this option if you have a tinydrm supported display.
> + If M is selected the module will be called tinydrm.
> diff --git a/drivers/gpu/drm/tinydrm/Makefile 
> b/drivers/gpu/drm/tinydrm/Makefile
> new file mode 100644
> index 000..7476ed1
> --- /dev/null
> +++ b/drivers/gpu/drm/tinydrm/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_DRM_TINYDRM)  += core/
> diff --git a/drivers/gpu/drm/tinydrm/core/Makefile 
> b/drivers/gpu/drm/tinydrm/core/Makefile
> new file mode 100644
> index 000..03309f4
> --- /dev/null
> +++ b/drivers/gpu/drm/tinydrm/core/Makefile
> @@ -0,0 +1,8 @@
> +obj-$(CONFIG_DRM_TINYDRM)  += tinydrm.o
> +tinydrm-y  += tinydrm-core.o
> +tinydrm-y  += tinydrm-crtc.o
> +tinydrm-y  += tinydrm-framebuffer.o
> +tinydrm-y  += tinydrm-plane.o
> +tinydrm-y  += tinydrm-helpers.o
> +tinydrm-y  += tinydrm-deferred.o
> +tinydrm-$(CONFIG_DRM_KMS_FB_HELPER)+= tinydrm-fbdev.o
> diff --git a/drivers/gpu/drm/tinydrm/core/internal.h 
> b/drivers/gpu/drm/tinydrm/core/internal.h
> new file mode 100644
> index 000..a126658
> --- /dev/null
> +++ b/drivers/gpu/drm/tinydrm/core/internal.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2016 Noralf Trønnes
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +int tinydrm_crtc_create(struct tinydrm_device *tdev);
> +
> +static inline bool tinydrm_active(struct 

[RFC 1/5] drm: Add DRM support for tiny LCD displays

[Daniel Vetter]

On Wed, Mar 23, 2016 at 06:07:56PM +0100, Noralf Trønnes wrote:
> 
> Den 18.03.2016 18:47, skrev Daniel Vetter:
> >On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote:
> >>Den 16.03.2016 16:11, skrev Daniel Vetter:
> >>>On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote:
> tinydrm provides a very simplified view of DRM for displays that has
> onboard video memory and is connected through a slow bus like SPI/I2C.
> 
> Signed-off-by: Noralf Trønnes 
> >>>Yay, it finally happens! I already made a comment on the cover letter
> >>>about the fbdev stuff, I think that's the biggest part to split out from
> >>>tinydrm here. I'm not entirely sure a detailed code review makes sense
> >>>before that part is done (and hey we can start merging already), so just a
> >>>high level review for now:
> [...]
> >
> >>>In the case of tinydrm I think that means we should have a bunch of new
> >>>drm helpers, or extensions for existing ones:
> >>>- fbdev deferred io support using ->dirtyfb in drm_fb_helper.c.
> >>Are you thinking something like this?
> >>
> >>struct drm_fb_helper_funcs {
> >> int (*dirtyfb)(struct drm_fb_helper *fb_helper,
> >>struct drm_clip_rect *clip);
> >We already have a dirty_fb function in
> >dev->mode_config->funcs->dirty_fb(). This is the official interface native
> >drm/kms userspace is supposed to use to flush frontbuffer rendering. The
> >xfree86-video-modesetting driver uses it.
> 
> I couldn't find this dirty_fb() function, but I assume you mean
> drm_framebuffer_funcs.dirty().

Yup.

> >>};
> >>
> >>struct drm_fb_helper {
> >> spinlock_t dirty_lock;
> >> struct drm_clip_rect *dirty_clip;
> >>};
> >Yeah, this part is needed for the delayed work for the fbdev helper.
> 
> >struct work dirty_fb_work; is missing.
> 
> This confuses me.
> If we have this then there's no need for a fb->funcs->dirty() call,
> the driver can just add a work function here instead.
> 
> Possible fb dirty() call chain:
> Calls to drm_fb_helper_sys_* or mmap page writes will schedule
> fb_info->deferred_work. The worker func fb_deferred_io_work() calls
> fb_info->fbdefio->deferred_io().
> Then deferred_io() can call fb_helper->fb->funcs->dirty().
> 
> In my use-case this dirty() function would schedule a delayed_work to run
> immediately since it has already been deferred collecting changes.
> The regular drm side framebuffer dirty() collects damage and schedules
> the same worker to run deferred.
> 
> I don't see an easy way for a driver to set the dirty() function in
> drm_fb_cma_helper apart from doing this:
> 
>  struct drm_fbdev_cma {
>  struct drm_fb_helperfb_helper;
>  struct drm_fb_cma   *fb;
> +int (*dirty)(struct drm_framebuffer *framebuffer,
> + struct drm_file *file_priv, unsigned flags,
> + unsigned color, struct drm_clip_rect *clips,
> + unsigned num_clips);
>  };

Well my point is that drm core already has a canonical interface
(drm_framebuffer_funcs.dirty) to flush out rendering. And it's supposed to
be called from process context, and userspace is supposed to batch up
dirty updates.

What I'd like is that the fbdev emulation uses exactly that interface,
without requiring drivers to write any additional fbdev code (like qxl and
udl currently have). Since the drm_framebuffer_funcs.dirty is already
expected to run in process context I think the only bit we need is the
deferred_work you already added in fbdev, so that we can schedule the
driver's ->dirty() function.

There shouldn't be any need to have another ->dirty() function anywhere
else.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

[RFC 1/5] drm: Add DRM support for tiny LCD displays

[Noralf Trønnes]

Den 18.03.2016 18:47, skrev Daniel Vetter:
> On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote:
>> Den 16.03.2016 16:11, skrev Daniel Vetter:
>>> On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote:
 tinydrm provides a very simplified view of DRM for displays that has
 onboard video memory and is connected through a slow bus like SPI/I2C.

 Signed-off-by: Noralf Trønnes 
>>> Yay, it finally happens! I already made a comment on the cover letter
>>> about the fbdev stuff, I think that's the biggest part to split out from
>>> tinydrm here. I'm not entirely sure a detailed code review makes sense
>>> before that part is done (and hey we can start merging already), so just a
>>> high level review for now:
[...]
>
>>> In the case of tinydrm I think that means we should have a bunch of new
>>> drm helpers, or extensions for existing ones:
>>> - fbdev deferred io support using ->dirtyfb in drm_fb_helper.c.
>> Are you thinking something like this?
>>
>> struct drm_fb_helper_funcs {
>>  int (*dirtyfb)(struct drm_fb_helper *fb_helper,
>> struct drm_clip_rect *clip);
> We already have a dirty_fb function in
> dev->mode_config->funcs->dirty_fb(). This is the official interface native
> drm/kms userspace is supposed to use to flush frontbuffer rendering. The
> xfree86-video-modesetting driver uses it.

I couldn't find this dirty_fb() function, but I assume you mean
drm_framebuffer_funcs.dirty().

>> };
>>
>> struct drm_fb_helper {
>>  spinlock_t dirty_lock;
>>  struct drm_clip_rect *dirty_clip;
>> };
> Yeah, this part is needed for the delayed work for the fbdev helper.

> struct work dirty_fb_work; is missing.

This confuses me.
If we have this then there's no need for a fb->funcs->dirty() call,
the driver can just add a work function here instead.

Possible fb dirty() call chain:
Calls to drm_fb_helper_sys_* or mmap page writes will schedule
fb_info->deferred_work. The worker func fb_deferred_io_work() calls
fb_info->fbdefio->deferred_io().
Then deferred_io() can call fb_helper->fb->funcs->dirty().

In my use-case this dirty() function would schedule a delayed_work to run
immediately since it has already been deferred collecting changes.
The regular drm side framebuffer dirty() collects damage and schedules
the same worker to run deferred.

I don't see an easy way for a driver to set the dirty() function in
drm_fb_cma_helper apart from doing this:

  struct drm_fbdev_cma {
  struct drm_fb_helperfb_helper;
  struct drm_fb_cma   *fb;
+int (*dirty)(struct drm_framebuffer *framebuffer,
+ struct drm_file *file_priv, unsigned flags,
+ unsigned color, struct drm_clip_rect *clips,
+ unsigned num_clips);
  };


>> Initially I used drm_fb_cma_helper.c with some added deferred code.
>> This worked fine for fbcon, but the deferred mmap part didn't work well.
>> For instance when using fbtest, I got short random horizontal lines on the
>> display that didn't contain the latest pixels. I had to write several times
>> to /dev/fb1 to trigger a display update to get all the previous pixels to go
>> away and get the current image. Maybe it's some caching issue, I don't know.
>> The Raspberry Pi doesn't support 16-bit SPI, so tinydrm does a byte swap to
>> a new buffer before sending it using 8-bit.
>> Maybe I need to call some kind of DMA sync function?
> drm_fb_cma_helper is for creating drm_framebuffer backed by cma allocator
> objects. How you create drm_framebuffer is orthogonal to whether you have
> a ->dirty_fb hook (and hence needed defio support in fbdev) or not. E.g.
> maybe some SPI device has a dma engine, and hence you want to allocate
> drm_framebuffer using cma. On others with an i2c bus you want to just
> allocate kernel memory, since the cpu will copy the data anyway.
>
> That's why I think we need to make sure this split is still maintained.
>
>> The dumb buffer uses drm_gem_cma_dumb_create() which is backed by cma, and
>> that works just fine (I have only tested with David Herrmann's modeset[1]).
>> A similar byte swapping happens here.
>>
>> I also had to do this for the deferred io to work:
>>
>> info->fix.smem_start = __pa(info->screen_base);
>>
>> drm_fb_cma_helper assigns the dma address to smem_start, but at least on
>> the Raspberry Pi this bus address can't be used by deferred_io
>> (fb_deferred_io_fault()). And the ARM version of __pa states that it
>> shouldn't be used by drivers, so when my vmalloc version worked, I went
>> with that. But I see that there's a virt_to_phys() function that doesn't
>> have that statement about not being used by drivers, so maybe this isn't
>> a show stopper after all?
>>
>> Any thoughts on this problem? I would rather have a cma backed fbdev
>> framebuffer since that would give me the same type of memory both for
>> fbdev and DRM.
> Hm, tbh I have no clear idea who fbdev fb memory mapping workings. The
> above 

[PATCH v3 19/19] ARM: sun5i: chip: Enable the TV Encoder

[Maxime Ripard]

The CHIP has a composite output available muxed with the microphone in the
micro-jack plug.

Enable the composite output in its DTS.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts 
b/arch/arm/boot/dts/sun5i-r8-chip.dts
index f6898c6b84d4..a8d8b4582397 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -66,6 +66,10 @@
};
 };

+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -188,6 +192,14 @@
status = "okay";
 };

+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_b>;
-- 
2.7.3

[PATCH v3 18/19] ARM: sun5i: r8: Add display blocks to the DTSI

[Maxime Ripard]

The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.

Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it should be moved to sun5i.dtsi

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 137 
 1 file changed, 137 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 691d3de75b35..df20b3b3ecfb 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -57,4 +57,141 @@
status = "disabled";
};
};
+
+   soc at 01c0 {
+   tve0: tv-encoder at 01c0a000 {
+   compatible = "allwinner,sun4i-a10-tv-encoder";
+   reg = <0x01c0a000 0x1000>;
+   clocks = <_gates 34>;
+   resets = <_ch0_clk 0>;
+   status = "disabled";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tve0_in_tcon0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = <_out_tve0>;
+   };
+   };
+   };
+
+   tcon0: lcd-controller at 01c0c000 {
+   compatible = "allwinner,sun5i-a13-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = <44>;
+   resets = <_ch0_clk 1>;
+   reset-names = "lcd";
+   clocks = <_gates 36>,
+<_ch0_clk>,
+<_ch1_clk>;
+   clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+   clock-output-names = "tcon-pixel-clock";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon0_in: port at 0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   tcon0_in_be0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_tcon0>;
+   };
+   };
+
+   tcon0_out: port at 1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   tcon0_out_tve0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_tcon0>;
+   };
+   };
+   };
+   };
+
+   fe0: display-frontend at 01e0 {
+   compatible = "allwinner,sun5i-a13-display-frontend";
+   reg = <0x01e0 0x2>;
+   interrupts = <47>;
+   clocks = <_gates 46>, <_fe_clk>,
+<_gates 25>;
+   clock-names = "ahb", "mod",
+ "ram";
+   resets = <_fe_clk>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   fe0_out: port at 0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   fe0_out_be0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = <_in_fe0>;
+   };
+   };
+   };
+   };
+
+   be0: display-backend at 01e6 {
+   compatible = "allwinner,sun5i-a13-display-backend";
+   reg = <0x01e6 0x1>;
+   clocks = <_gates 44>, <_be_clk>,
+<_gates 26>;
+   clock-names = "ahb", "mod",
+  

[PATCH v3 17/19] drm: sun4i: tv: Add NTSC output standard

[Maxime Ripard]

Add the settings to support the NTSC standard.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 45 
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index ccf275a90132..bc047f923508 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -178,24 +178,69 @@ struct sun4i_tv {
struct sun4i_drv*drv;
 };

+struct video_levels ntsc_video_levels = {
+   .black = 282,   .blank = 240,
+};
+
 struct video_levels pal_video_levels = {
.black = 252,   .blank = 252,
 };

+struct burst_levels ntsc_burst_levels = {
+   .cb = 79,   .cr = 0,
+};
+
 struct burst_levels pal_burst_levels = {
.cb = 40,   .cr = 40,
 };

+struct color_gains ntsc_color_gains = {
+   .cb = 160,  .cr = 160,
+};
+
 struct color_gains pal_color_gains = {
.cb = 224,  .cr = 224,
 };

+struct resync_parameters ntsc_resync_parameters = {
+   .field = false, .line = 14, .pixel = 12,
+};
+
 struct resync_parameters pal_resync_parameters = {
.field = true,  .line = 13, .pixel = 12,
 };

 struct tv_mode tv_modes[] = {
{
+   .name   = "NTSC",
+   .mode   = SUN4I_TVE_CFG0_RES_480i,
+   .chroma_freq= 0x21f07c1f,
+   .yc_en  = true,
+   .dac3_en= true,
+   .dac_bit25_en   = true,
+
+   .back_porch = 118,
+   .front_porch= 32,
+   .line_number= 525,
+
+   .hdisplay   = 720,
+   .hfront_porch   = 18,
+   .hsync_len  = 2,
+   .hback_porch= 118,
+
+   .vdisplay   = 480,
+   .vfront_porch   = 26,
+   .vsync_len  = 2,
+   .vback_porch= 17,
+
+   .vblank_level   = 240,
+
+   .color_gains= _color_gains,
+   .burst_levels   = _burst_levels,
+   .video_levels   = _video_levels,
+   .resync_params  = _resync_parameters,
+   },
+   {
.name   = "PAL",
.mode   = SUN4I_TVE_CFG0_RES_576i,
.chroma_freq= 0x2a098acb,
-- 
2.7.3

[PATCH v3 16/19] drm: sun4i: tv: Add PAL output standard

[Maxime Ripard]

Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 78634dfc0f77..ccf275a90132 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -178,7 +178,49 @@ struct sun4i_tv {
struct sun4i_drv*drv;
 };

+struct video_levels pal_video_levels = {
+   .black = 252,   .blank = 252,
+};
+
+struct burst_levels pal_burst_levels = {
+   .cb = 40,   .cr = 40,
+};
+
+struct color_gains pal_color_gains = {
+   .cb = 224,  .cr = 224,
+};
+
+struct resync_parameters pal_resync_parameters = {
+   .field = true,  .line = 13, .pixel = 12,
+};
+
 struct tv_mode tv_modes[] = {
+   {
+   .name   = "PAL",
+   .mode   = SUN4I_TVE_CFG0_RES_576i,
+   .chroma_freq= 0x2a098acb,
+
+   .back_porch = 138,
+   .front_porch= 24,
+   .line_number= 625,
+
+   .hdisplay   = 720,
+   .hfront_porch   = 3,
+   .hsync_len  = 2,
+   .hback_porch= 139,
+
+   .vdisplay   = 576,
+   .vfront_porch   = 28,
+   .vsync_len  = 2,
+   .vback_porch= 19,
+
+   .vblank_level   = 252,
+
+   .color_gains= _color_gains,
+   .burst_levels   = _burst_levels,
+   .video_levels   = _video_levels,
+   .resync_params  = _resync_parameters,
+   },
 };

 static inline struct sun4i_tv *
-- 
2.7.3

[PATCH v3 15/19] drm: sun4i: Add composite output

[Maxime Ripard]

Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.

Add support for that TV encoder.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/Makefile   |   2 +
 drivers/gpu/drm/sun4i/sun4i_tv.c | 621 +++
 2 files changed, 623 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.c

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 830abb9b2b74..c93498f6a795 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -9,3 +9,5 @@ sun4i-tcon-y += sun4i_dotclock.o

 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
+
+obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
new file mode 100644
index ..78634dfc0f77
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -0,0 +1,621 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "sun4i_backend.h"
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+#define SUN4I_TVE_EN_REG   0x000
+#define SUN4I_TVE_EN_DAC_MAP_MASK  GENMASK(19, 4)
+#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
+#define SUN4I_TVE_EN_ENABLEBIT(0)
+
+#define SUN4I_TVE_CFG0_REG 0x004
+#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
+#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M   BIT(25)
+#define SUN4I_TVE_CFG0_CORE_CONTROL_54MBIT(24)
+#define SUN4I_TVE_CFG0_YC_EN   BIT(17)
+#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
+#define SUN4I_TVE_CFG0_RES(x)  ((x) & 0xf)
+#define SUN4I_TVE_CFG0_RES_480iSUN4I_TVE_CFG0_RES(0)
+#define SUN4I_TVE_CFG0_RES_576iSUN4I_TVE_CFG0_RES(1)
+
+#define SUN4I_TVE_DAC0_REG 0x008
+#define SUN4I_TVE_DAC0_CLOCK_INVERTBIT(24)
+#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
+#define SUN4I_TVE_DAC0_LUMA_0_4SUN4I_TVE_DAC0_LUMA(3)
+#define SUN4I_TVE_DAC0_CHROMA(x)   (((x) & 3) << 18)
+#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS  SUN4I_TVE_DAC0_INTERNAL_DAC(3)
+#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
+
+#define SUN4I_TVE_NOTCH_REG0x00c
+#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x)((4 - (x)) << (dac * 3))
+
+#define SUN4I_TVE_CHROMA_FREQ_REG  0x010
+
+#define SUN4I_TVE_PORCH_REG0x014
+#define SUN4I_TVE_PORCH_BACK(x)((x) << 16)
+#define SUN4I_TVE_PORCH_FRONT(x)   (x)
+
+#define SUN4I_TVE_LINE_REG 0x01c
+#define SUN4I_TVE_LINE_FIRST(x)((x) << 16)
+#define SUN4I_TVE_LINE_NUMBER(x)   (x)
+
+#define SUN4I_TVE_LEVEL_REG0x020
+#define SUN4I_TVE_LEVEL_BLANK(x)   ((x) << 16)
+#define SUN4I_TVE_LEVEL_BLACK(x)   (x)
+
+#define SUN4I_TVE_DAC1_REG 0x024
+#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x)   ((x) << (dac * 8))
+
+#define SUN4I_TVE_DETECT_STA_REG   0x038
+#define SUN4I_TVE_DETECT_STA_DAC(dac)  BIT((dac * 8))
+#define SUN4I_TVE_DETECT_STA_UNCONNECTED   0
+#define SUN4I_TVE_DETECT_STA_CONNECTED 1
+#define SUN4I_TVE_DETECT_STA_GROUND2
+
+#define SUN4I_TVE_CB_CR_LVL_REG0x10c
+#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x)((x) << 8)
+#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x)(x)
+
+#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
+#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x)   (x)
+
+#define SUN4I_TVE_BURST_WIDTH_REG  0x114
+#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
+#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x)   ((x) << 8)
+#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x)   (x)
+
+#define SUN4I_TVE_CB_CR_GAIN_REG   0x118
+#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
+#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
+
+#define SUN4I_TVE_SYNC_VBI_REG 0x11c
+#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
+#define SUN4I_TVE_SYNC_VBI_VBLANK(x)   (x)
+
+#define SUN4I_TVE_ACTIVE_LINE_REG  0x124
+#define SUN4I_TVE_ACTIVE_LINE(x)   

[PATCH v3 14/19] drm: sun4i: Add RGB output

[Maxime Ripard]

One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/Makefile |   1 +
 drivers/gpu/drm/sun4i/sun4i_drv.c  |   7 ++
 drivers/gpu/drm/sun4i/sun4i_rgb.c  | 234 +
 drivers/gpu/drm/sun4i/sun4i_rgb.h  |  18 +++
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  48 +++-
 drivers/gpu/drm/sun4i/sun4i_tcon.h |   2 +
 6 files changed, 309 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.h

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 6df3ef32732d..830abb9b2b74 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -2,6 +2,7 @@ sun4i-drm-y += sun4i_crtc.o
 sun4i-drm-y += sun4i_drv.o
 sun4i-drm-y += sun4i_framebuffer.o
 sun4i-drm-y += sun4i_layer.o
+sun4i-drm-y += sun4i_rgb.o

 sun4i-tcon-y += sun4i_tcon.o
 sun4i-tcon-y += sun4i_dotclock.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 5c64d2105dc7..5ba66ca5258b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -244,6 +244,13 @@ static int sun4i_drv_add_endpoints(struct device *dev,
}

for_each_available_child_of_node(port, ep) {
+   /*
+* If the node is a panel, don't register it into the
+* component framework
+*/
+   if (of_property_read_bool(ep, "allwinner,panel"))
+   continue;
+
remote = of_graph_get_remote_port_parent(ep);
if (!remote) {
DRM_DEBUG_DRIVER("Error retrieving the output node\n");
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c 
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
new file mode 100644
index ..dd0dcc6cdc26
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+struct sun4i_rgb {
+   struct drm_connectorconnector;
+   struct drm_encoder  encoder;
+
+   struct sun4i_drv*drv;
+};
+
+static inline struct sun4i_rgb *
+drm_connector_to_sun4i_rgb(struct drm_connector *connector)
+{
+   return container_of(connector, struct sun4i_rgb,
+   connector);
+}
+
+static inline struct sun4i_rgb *
+drm_encoder_to_sun4i_rgb(struct drm_encoder *encoder)
+{
+   return container_of(encoder, struct sun4i_rgb,
+   encoder);
+}
+
+static int sun4i_rgb_get_modes(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb =
+   drm_connector_to_sun4i_rgb(connector);
+   struct sun4i_drv *drv = rgb->drv;
+   struct sun4i_tcon *tcon = drv->tcon;
+
+   return drm_panel_get_modes(tcon->panel);
+}
+
+static int sun4i_rgb_mode_valid(struct drm_connector *connector,
+   struct drm_display_mode *mode)
+{
+   u32 hsync = mode->hsync_end - mode->hsync_start;
+   u32 vsync = mode->vsync_end - mode->vsync_start;
+
+   DRM_DEBUG_DRIVER("Validating modes...\n");
+
+   if ((hsync < 1) || (hsync > 0x3ff) ||
+   (mode->htotal < 1) || (mode->htotal > 0xfff))
+   return MODE_H_ILLEGAL;
+
+   DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
+
+   if ((vsync < 1) || (vsync > 0x3ff) ||
+   (mode->vtotal < 1) || (mode->vtotal > 0xfff))
+   return MODE_V_ILLEGAL;
+
+   DRM_DEBUG_DRIVER("Vertical parameters OK\n");
+
+   return MODE_OK;
+}
+
+static struct drm_encoder *
+sun4i_rgb_best_encoder(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb =
+   drm_connector_to_sun4i_rgb(connector);
+
+   return >encoder;
+}
+
+static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
+   .get_modes  = sun4i_rgb_get_modes,
+   .mode_valid = sun4i_rgb_mode_valid,
+   .best_encoder   = sun4i_rgb_best_encoder,
+};
+
+static enum drm_connector_status
+sun4i_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+   return connector_status_connected;
+}
+
+static void
+sun4i_rgb_connector_destroy(struct drm_connector *connector)
+{
+   struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
+   struct sun4i_drv *drv = rgb->drv;
+   struct sun4i_tcon *tcon = drv->tcon;
+
+   

[PATCH v3 13/19] drm: sun4i: Add DT bindings documentation

[Maxime Ripard]

The display pipeline of the Allwinner A10 is involving several loosely
coupled components.

Add a documentation for the bindings.

Signed-off-by: Maxime Ripard 
---
 .../bindings/display/sunxi/sun4i-drm.txt   | 254 +
 1 file changed, 254 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
new file mode 100644
index ..378edb919eae
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -0,0 +1,254 @@
+Allwinner A10 Display Pipeline
+==
+
+The Allwinner A10 Display pipeline is composed of several components
+that are going to be documented below:
+
+TV Encoder
+--
+
+The TV Encoder supports the composite and VGA output. It is one end of
+the pipeline.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
+ - reg: base address and size of memory-mapped region
+ - clocks: the clocks driving the TV encoder
+ - resets: phandle to the reset controller driving the encoder
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoint.
+
+TCON
+
+
+The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
+
+Required properties:
+ - compatible: value should be "allwinner,sun5i-a13-tcon".
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the TCON. Three are needed:
+   - 'ahb': the interface clocks
+   - 'tcon-ch0': The clock driving the TCON channel 0
+   - 'tcon-ch1': The clock driving the TCON channel 1
+ - resets: phandles to the reset controllers driving the encoder
+   - "lcd": the reset line for the TCON channel 0
+
+ - clock-names: the clock names mentioned above
+ - reset-names: the reset names mentioned above
+ - clock-output-names: Name of the pixel clock created
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoint, the second one the output
+
+Endpoints optional property:
+  - allwinner,panel: boolean to indicate that the endpoint is a panel
+
+
+Display Engine Backend
+--
+
+The display engine backend exposes layers and sprites to the
+system.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-backend
+  - reg: base address and size of the memory-mapped region.
+  - clocks: phandles to the clocks feeding the frontend and backend
+* ahb: the backend interface clock
+* mod: the backend module clock
+* ram: the backend DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the backend
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoints, the second one the output
+
+Display Engine Frontend
+---
+
+The display engine frontend does formats conversion, scaling,
+deinterlacing and color space conversion.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-frontend
+  - reg: base address and size of the memory-mapped region.
+  - interrupts: interrupt associated to this IP
+  - clocks: phandles to the clocks feeding the frontend and backend
+* ahb: the backend interface clock
+* mod: the backend module clock
+* ram: the backend DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the backend
+
+Display Engine Pipeline
+---
+
+The display engine pipeline (and its entry point, since it can be
+either directly the backend or the frontend) is represented as an
+extra node.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a13-display-engine
+  - allwinner,pipelines: list of phandle to the entry points of the
+pipelines (either to the frontend or backend)
+
+Example:
+
+panel: panel {
+   compatible = "olimex,lcd-olinuxino-43-ts";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port at 0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   panel_input: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = <_out_panel>;
+   };
+   };
+};
+
+tve0: tv-encoder at 01c0a000 {
+   compatible = "allwinner,sun4i-a10-tv-encoder";
+   reg = <0x01c0a000 0x1000>;
+   clocks = <_gates 34>;
+   resets = <_ch0_clk 0>;
+
+   port {
+   

[PATCH v3 12/19] drm: Add Allwinner A10 Display Engine support

[Maxime Ripard]

The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.

Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/Kconfig   |   2 +
 drivers/gpu/drm/Makefile  |   3 +-
 drivers/gpu/drm/sun4i/Kconfig |  14 +
 drivers/gpu/drm/sun4i/Makefile|  10 +
 drivers/gpu/drm/sun4i/sun4i_backend.c | 364 ++
 drivers/gpu/drm/sun4i/sun4i_backend.h | 165 ++
 drivers/gpu/drm/sun4i/sun4i_crtc.c| 120 
 drivers/gpu/drm/sun4i/sun4i_crtc.h|  30 ++
 drivers/gpu/drm/sun4i/sun4i_dotclock.c| 160 ++
 drivers/gpu/drm/sun4i/sun4i_dotclock.h|  21 ++
 drivers/gpu/drm/sun4i/sun4i_drv.c | 319 +++
 drivers/gpu/drm/sun4i/sun4i_drv.h |  30 ++
 drivers/gpu/drm/sun4i/sun4i_framebuffer.c |  54 
 drivers/gpu/drm/sun4i/sun4i_framebuffer.h |  19 ++
 drivers/gpu/drm/sun4i/sun4i_layer.c   | 161 ++
 drivers/gpu/drm/sun4i/sun4i_layer.h   |  30 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.c| 492 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.h| 184 +++
 18 files changed, 2177 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/Kconfig
 create mode 100644 drivers/gpu/drm/sun4i/Makefile
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_dotclock.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_dotclock.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f2a74d0b68ae..420779064e49 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -252,6 +252,8 @@ source "drivers/gpu/drm/rcar-du/Kconfig"

 source "drivers/gpu/drm/shmobile/Kconfig"

+source "drivers/gpu/drm/sun4i/Kconfig"
+
 source "drivers/gpu/drm/omapdrm/Kconfig"

 source "drivers/gpu/drm/tilcdc/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 6eb94fc561dc..e163fd3cd604 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -1,4 +1,4 @@
-#
+
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.

@@ -65,6 +65,7 @@ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/
 obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
 obj-y  += omapdrm/
+obj-$(CONFIG_DRM_SUN4I) += sun4i/
 obj-y  += tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
 obj-$(CONFIG_DRM_BOCHS) += bochs/
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
new file mode 100644
index ..99510e64e91a
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -0,0 +1,14 @@
+config DRM_SUN4I
+   tristate "DRM Support for Allwinner A10 Display Engine"
+   depends on DRM && ARM
+   depends on ARCH_SUNXI || COMPILE_TEST
+   select DRM_GEM_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_PANEL
+   select REGMAP_MMIO
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you have an Allwinner SoC with a
+ Display Engine. If M is selected the module will be called
+ sun4i-drm.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
new file mode 100644
index ..6df3ef32732d
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -0,0 +1,10 @@
+sun4i-drm-y += sun4i_crtc.o
+sun4i-drm-y += sun4i_drv.o
+sun4i-drm-y += sun4i_framebuffer.o
+sun4i-drm-y += sun4i_layer.o
+
+sun4i-tcon-y += sun4i_tcon.o
+sun4i-tcon-y += sun4i_dotclock.o
+
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
new file mode 100644
index ..f7a15c1a93bf
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it 

[PATCH v3 11/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS

[Maxime Ripard]

Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.

It is a 480x272 panel connected through a 24-bits RGB interface.

Signed-off-by: Maxime Ripard 
Acked-by: Rob Herring 
---
 .../display/panel/olimex,lcd-olinuxino-43-ts.txt   |  7 ++
 drivers/gpu/drm/panel/panel-simple.c   | 26 ++
 2 files changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
 
b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
new file mode 100644
index ..74540a090669
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
@@ -0,0 +1,7 @@
+Olimex 4.3" TFT LCD panel
+
+Required properties:
+- compatible: should be "olimex,lcd-olinuxino-43-ts"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index ceb20486dacf..f95abdbde147 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1084,6 +1084,29 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };

+static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+   .clock = 9000,
+   .hdisplay = 480,
+   .hsync_start = 480 + 5,
+   .hsync_end = 480 + 5 + 30,
+   .htotal = 480 + 5 + 30 + 10,
+   .vdisplay = 272,
+   .vsync_start = 272 + 8,
+   .vsync_end = 272 + 8 + 5,
+   .vtotal = 272 + 8 + 5 + 3,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+   .modes = _lcd_olinuxino_43ts_mode,
+   .num_modes = 1,
+   .size = {
+   .width = 105,
+   .height = 67,
+   },
+   .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
.clock = 25000,
.hdisplay = 480,
@@ -1329,6 +1352,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "okaya,rs800480t-7x0gp",
.data = _rs800480t_7x0gp,
}, {
+   .compatible = "olimex,lcd-olinuxino-43-ts",
+   .data = _lcd_olinuxino_43ts,
+   }, {
.compatible = "ortustech,com43h4m85ulc",
.data = _com43h4m85ulc,
}, {
-- 
2.7.3

[PATCH v3 10/19] drm: fb: Add seq_file definition

[Maxime Ripard]

Otherwise, building with DEBUG_FS enabled will trigger a build warning
because we're using a structure that has not been declared.

Signed-off-by: Maxime Ripard 
---
 include/drm/drm_fb_cma_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
index be62bd321e75..ae49c24fbf50 100644
--- a/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@ -24,6 +24,8 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct 
drm_framebuffer *fb,
unsigned int plane);

 #ifdef CONFIG_DEBUG_FS
+struct seq_file;
+
 int drm_fb_cma_debugfs_show(struct seq_file *m, void *arg);
 #endif

-- 
2.7.3

[PATCH v3 09/19] ARM: sun5i: Add TV encoder gate to the DTSI

[Maxime Ripard]

It turns out that the A13 / R8 also have a tve encoder block, and a gate
for it.

Add it to the DT.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d3d2b19c97f1..263d46dbc7e6 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -111,8 +111,8 @@
<10>, <13>,
<14>, <20>,
<21>, <22>,
-   <28>, <32>, <36>,
-   <40>, <44>,
+   <28>, <32>, <34>,
+   <36>, <40>, <44>,
<46>, <51>,
<52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
@@ -121,8 +121,8 @@
 "ahb_mmc2", "ahb_nand",
 "ahb_sdram", "ahb_spi0",
 "ahb_spi1", "ahb_spi2",
-"ahb_stimer", "ahb_ve", "ahb_lcd",
-"ahb_csi", "ahb_de_be",
+"ahb_stimer", "ahb_ve", "ahb_tve",
+"ahb_lcd", "ahb_csi", "ahb_de_be",
 "ahb_de_fe", "ahb_iep",
 "ahb_mali400";
};
-- 
2.7.3

[PATCH v3 08/19] ARM: sun5i: Add DRAM gates

[Maxime Ripard]

The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.

Enable it.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 22 +-
 arch/arm/boot/dts/sun5i-r8.dtsi  |  2 +-
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 9669b03f20f3..d3d2b19c97f1 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -62,7 +62,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <_gates 36>, <_gates 44>, <_be_clk>,
-<_ch0_clk>;
+<_ch0_clk>, <_gates 26>;
status = "disabled";
};
};
@@ -151,6 +151,26 @@
 "apb1_uart3";
};

+   dram_gates: clk at 01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun5i-a13-dram-gates-clk",
+"allwinner,sun4i-a10-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>,
+   <25>,
+   <26>,
+   <29>,
+   <31>;
+   clock-output-names = "dram_ve",
+"dram_csi",
+"dram_de_fe",
+"dram_de_be",
+"dram_ace",
+"dram_iep";
+   };
+
de_be_clk: clk at 01c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index b1e4e0170d51..691d3de75b35 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -53,7 +53,7 @@
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <_gates 34>, <_gates 36>,
 <_gates 44>, <_be_clk>,
-<_ch1_clk>;
+<_ch1_clk>, <_gates 26>;
status = "disabled";
};
};
-- 
2.7.3

[PATCH v3 07/19] ARM: sun5i: a13: Add display and TCON clocks

[Maxime Ripard]

Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.

Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a13.dtsi | 38 +-
 arch/arm/boot/dts/sun5i-r8.dtsi  |  5 +++--
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d910d3a6c41c..9669b03f20f3 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -61,7 +61,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>;
+   clocks = <_gates 36>, <_gates 44>, <_be_clk>,
+<_ch0_clk>;
status = "disabled";
};
};
@@ -149,6 +150,41 @@
 "apb1_i2c2", "apb1_uart1",
 "apb1_uart3";
};
+
+   de_be_clk: clk at 01c20104 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20104 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be";
+   };
+
+   de_fe_clk: clk at 01c2010c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c2010c 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe";
+   };
+
+   tcon_ch0_clk: clk at 01c20118 {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c20118 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon-ch0-sclk";
+   };
+
+   tcon_ch1_clk: clk at 01c2012c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+   reg = <0x01c2012c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon-ch1-sclk";
+   };
};

soc at 01c0 {
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 0ef865601ac9..b1e4e0170d51 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -51,8 +51,9 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
-   clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>;
+   clocks = <_gates 34>, <_gates 36>,
+<_gates 44>, <_be_clk>,
+<_ch1_clk>;
status = "disabled";
};
};
-- 
2.7.3

[PATCH v3 06/19] ARM: sun5i: dt: Add pll3 and pll7 clocks

[Maxime Ripard]

Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun5i.dtsi | 43 +++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 59a9426e3bd4..0840612b5ed6 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -88,6 +88,15 @@
clock-output-names = "osc24M";
};

+   osc3M: osc3M_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <8>;
+   clock-mult = <1>;
+   clocks = <>;
+   clock-output-names = "osc3M";
+   };
+
osc32k: clk at 0 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -112,6 +121,23 @@
 "pll2-4x", "pll2-8x";
};

+   pll3: clk at 01c20010 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-pll3-clk";
+   reg = <0x01c20010 0x4>;
+   clocks = <>;
+   clock-output-names = "pll3";
+   };
+
+   pll3x2: pll3x2_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <2>;
+   clocks = <>;
+   clock-output-names = "pll3-2x";
+   };
+
pll4: clk at 01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +162,23 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};

+   pll7: clk at 01c20030 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-pll3-clk";
+   reg = <0x01c20030 0x4>;
+   clocks = <>;
+   clock-output-names = "pll7";
+   };
+
+   pll7x2: pll7x2_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <2>;
+   clocks = <>;
+   clock-output-names = "pll7-2x";
+   };
+
/* dummy is 200M */
cpu: cpu at 01c20054 {
#clock-cells = <0>;
-- 
2.7.3

[PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible

[Maxime Ripard]

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 54192c1a98dc..e194cda2f469 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -66,6 +66,7 @@ Required properties:
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
+   "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
-- 
2.7.3

[PATCH v3 04/19] clk: sunxi: Add TCON channel1 clock

[Maxime Ripard]

The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.

It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).

Add a driver for the channel 1 clock.

Signed-off-by: Maxime Ripard 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c| 300 ++
 3 files changed, 302 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0e1e2c0eee61..54192c1a98dc 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -76,6 +76,7 @@ Required properties:
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
the A10
+   "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on 
the A10
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 244defcfa5db..39d2044a1f49 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
 obj-y += clk-sun4i-pll3.o
+obj-y += clk-sun4i-tcon-ch1.o
 obj-y += clk-sun8i-bus-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 
b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
new file mode 100644
index ..98a4582de56a
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TCON_CH1_SCLK2_PARENTS 4
+
+#define TCON_CH1_SCLK2_GATE_BITBIT(31)
+#define TCON_CH1_SCLK2_MUX_MASK3
+#define TCON_CH1_SCLK2_MUX_SHIFT   24
+#define TCON_CH1_SCLK2_DIV_MASK0xf
+#define TCON_CH1_SCLK2_DIV_SHIFT   0
+
+#define TCON_CH1_SCLK1_GATE_BITBIT(15)
+#define TCON_CH1_SCLK1_HALF_BITBIT(11)
+
+struct tcon_ch1_clk {
+   struct clk_hw   hw;
+   spinlock_t  lock;
+   void __iomem*reg;
+};
+
+#define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
+
+static void tcon_ch1_disable(struct clk_hw *hw)
+{
+   struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+   reg = readl(tclk->reg);
+   reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
+   writel(reg, tclk->reg);
+   spin_unlock_irqrestore(>lock, flags);
+}
+
+static int tcon_ch1_enable(struct clk_hw *hw)
+{
+   struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+   reg = readl(tclk->reg);
+   reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
+   writel(reg, tclk->reg);
+   spin_unlock_irqrestore(>lock, flags);
+
+   return 0;
+}
+
+static int tcon_ch1_is_enabled(struct clk_hw *hw)
+{
+   struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
+   u32 reg;
+
+   reg = readl(tclk->reg);
+   return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
+}
+
+static u8 tcon_ch1_get_parent(struct clk_hw *hw)
+{
+   struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
+   int num_parents = clk_hw_get_num_parents(hw);
+   u32 reg;
+
+   reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
+   reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
+
+   if (reg >= num_parents)
+   return -EINVAL;
+
+   return reg;
+}
+
+static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(>lock, flags);
+   reg = readl(tclk->reg);
+   reg &= ~(TCON_CH1_SCLK2_MUX_MASK << 

[PATCH v3 03/19] clk: sunxi: Add PLL3 clock

[Maxime Ripard]

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Acked-by: Rob Herring 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile|  1 +
 drivers/clk/sunxi/clk-sun4i-pll3.c| 98 +++
 3 files changed, 100 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 50e212bc8923..0e1e2c0eee61 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,6 +10,7 @@ Required properties:
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+   "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 37a6a642a037..244defcfa5db 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
+obj-y += clk-sun4i-pll3.o
 obj-y += clk-sun8i-bus-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c 
b/drivers/clk/sunxi/clk-sun4i-pll3.c
new file mode 100644
index ..f66267e77d9c
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-pll3.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SUN4I_A10_PLL3_GATE_BIT31
+#define SUN4I_A10_PLL3_DIV_WIDTH   7
+#define SUN4I_A10_PLL3_DIV_SHIFT   0
+
+static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
+
+static void __init sun4i_a10_pll3_setup(struct device_node *node)
+{
+   const char *clk_name = node->name, *parent;
+   struct clk_multiplier *mult;
+   struct clk_gate *gate;
+   struct resource res;
+   void __iomem *reg;
+   struct clk *clk;
+   int ret;
+
+   of_property_read_string(node, "clock-output-names", _name);
+   parent = of_clk_get_parent_name(node, 0);
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n", clk_name);
+   return;
+   }
+
+   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!gate)
+   goto err_unmap;
+
+   gate->reg = reg;
+   gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
+   gate->lock = _a10_pll3_lock;
+
+   mult = kzalloc(sizeof(*mult), GFP_KERNEL);
+   if (!mult)
+   goto err_free_gate;
+
+   mult->reg = reg;
+   mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
+   mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
+   mult->lock = _a10_pll3_lock;
+
+   clk = clk_register_composite(NULL, clk_name,
+, 1,
+NULL, NULL,
+>hw, _multiplier_ops,
+>hw, _gate_ops,
+0);
+   if (IS_ERR(clk)) {
+   pr_err("%s: Couldn't register the clock\n", clk_name);
+   goto err_free_mult;
+   }
+
+   ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   if (ret) {
+   pr_err("%s: Couldn't register DT provider\n",
+  clk_name);
+   goto err_clk_unregister;
+   }
+
+   return;
+
+err_clk_unregister:
+   clk_unregister_composite(clk);
+err_free_mult:
+   kfree(mult);
+err_free_gate:
+   kfree(gate);
+err_unmap:
+   iounmap(reg);
+   of_address_to_resource(node, 0, );
+   release_mem_region(res.start, resource_size());
+}
+
+CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
+  sun4i_a10_pll3_setup);
-- 
2.7.3

[PATCH v3 02/19] clk: sunxi: Add display and TCON0 clocks driver

[Maxime Ripard]

The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.

Add a driver to support both.

Signed-off-by: Maxime Ripard 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-sun4i-display.c | 262 ++
 3 files changed, 265 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 834436fbe83d..50e212bc8923 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -64,6 +64,7 @@ Required properties:
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
+   "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
@@ -73,6 +74,7 @@ Required properties:
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+   "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on 
the A10
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901d48e4..37a6a642a037 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += clk-a10-ve.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
+obj-y += clk-sun4i-display.o
 obj-y += clk-sun8i-bus-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
diff --git a/drivers/clk/sunxi/clk-sun4i-display.c 
b/drivers/clk/sunxi/clk-sun4i-display.c
new file mode 100644
index ..af7d1faebdec
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-display.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct sun4i_a10_display_clk_data {
+   boolhas_div;
+   u8  has_rst;
+   u8  parents;
+
+   u8  offset_en;
+   u8  offset_div;
+   u8  offset_mux;
+   u8  offset_rst;
+
+   u8  width_div;
+   u8  width_mux;
+};
+
+struct reset_data {
+   void __iomem*reg;
+   spinlock_t  *lock;
+   struct reset_controller_dev rcdev;
+   u8  offset;
+};
+
+static DEFINE_SPINLOCK(sun4i_a10_display_lock);
+
+static inline struct reset_data *rcdev_to_reset_data(struct 
reset_controller_dev *rcdev)
+{
+   return container_of(rcdev, struct reset_data, rcdev);
+};
+
+static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   struct reset_data *data = rcdev_to_reset_data(rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg & ~BIT(data->offset + id), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+   struct reset_data *data = rcdev_to_reset_data(rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg | BIT(data->offset + id), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
+   unsigned long id)
+{
+   struct reset_data *data = 

[PATCH v3 01/19] clk: composite: Add unregister function

[Maxime Ripard]

The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.

While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.

Add a clk_unregister_composite function to fix this.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/clk-composite.c  | 15 +++
 include/linux/clk-provider.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 1f903e1f86a2..b0f3b84ebd13 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -286,3 +286,18 @@ err:
kfree(composite);
return clk;
 }
+
+void clk_unregister_composite(struct clk *clk)
+{
+   struct clk_composite *composite;
+   struct clk_hw *hw;
+
+   hw = __clk_get_hw(clk);
+   if (!hw)
+   return;
+
+   composite = to_clk_composite(hw);
+
+   clk_unregister(clk);
+   kfree(composite);
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index da95258127aa..26a8c9b7be71 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -603,6 +603,7 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags);
+void clk_unregister_composite(struct clk *clk);

 /***
  * struct clk_gpio_gate - gpio gated clock
-- 
2.7.3

[PATCH v3 00/19] drm: Add Allwinner A10 display engine support

[Maxime Ripard]

Hi everyone,

The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.

Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
example), and the output availables will change too (HDMI, composite,
VGA on the A20, none of them on the A13).

On most featured SoCs, it looks like that:

++
|RAM |
++
  ||  ||
  v|  |v
++ |  | ++
|Frontend| |  | |Frontend|
++ |  | ++
|  |  | |
v  |  | v
++ |  | ++
|Backend |<+  +>|Backend |
++  ++
|   |
v   v
++  ++---> LVDS
|  TCON  |  |  TCON  |---> RGB
++  ++
   |   +---+   +---+  |
   |   |   |  |
   v   v   v  v
++  ++  ++---> VGA
| TV Encoder |  |HDMI|  | TV Encoder |---> Composite
++  ++  ++

The current code only assumes that there is a single instance of all
the controllers. It also supports only the RGB and Composite
interfaces.

Let me know what you think,
Maxime

Changes from v2:
  - Rebased on top of next-20160318

  - Dropped the generic clock regmap conversion and implemented a
custom clock for our pixel clock, backed by a regmap
  - Added the reset bits for the tcon channel 0 and display clocks
  - Used the new generic gates compatible for the DRAM gates
  - Few clock fixes (missing iounmap, return error checks, etc)
  - Found out that the TCON channel 1 clock was not operating properly
because of some weird rounding down and up between the various
generic clocks involved. Rewrote it using custom operations

  - Removed some TODO that were still there
  - Converted our panel DT description to the OF graph instead of a
custom property
  - Tested the driver on a setup where U-Boot was not initialising the
display, or initialising it on a different output, and fixed a
number of associated bugs (mostly related to missing
initialisation bits, missing reset handles, and so on)
  - Fixed the layer code that was assuming that the X and Y
coordinates were in pixels, leading to a miscalculation of the
buffer address when those coordinates where set.
  - Added the missing EXPORT_SYMBOL calls

  - Fixed our VBLANK interrupt code that was completely broken (and
not usable, which is why it was unnoticed)

Changes from v1:
  - Rebased on top of 4.4

  - Merged the clock drivers for the display and TCON channel 0 clocks
  - Replaced the container_of calls in the display reset clocks to an
inline function
  - Checked the return code of of_clk_parent_fill in the clocks
drivers
  - Checked the return code of of_clk_add_provider in the tcon-ch1 and
PLL3 clocks
  - Added missing clocks headers
  - Created a composite clock unregister function

  - Moved the binding documentation to
Documentation/devicetree/bindings/display
  - Added the clocks binding documentation
  - Added the Olimex vendor to the list of DT vendors
  - Moved to the OF graph representation and the component framework

  - Moved the reset cells count check into the reset framework to
avoid duplicating the code in every xlate implementation.
  - Made the reset_ops const

  - Reworked the DRM cmdline mode parsing code to allow named mode
  - Fixed the TV mode lookup when the mode name is not present (for
example because it was given by the userspace)

  - Made the driver outputs optional (to avoid crashing when a board
doesn't have either a panel or a composite output enabled)
  - Added multiple plane support with transparency
  - Moved the backend registers writes commit in the CRTC atomic_flush
callback
  - Removed the load / unload functions
  - Removed the enabled booleans in my private structure and removed
the implicit call to disable_unused_functions in the DRM core to
push it in the drivers.
  - Fixed a few bitmasks on some bitfields definition
  - Fixed the RGB connector mode validation that was not testing the
right values

Maxime Ripard (19):
  clk: composite: Add unregister function
  clk: sunxi: Add display and TCON0 clocks driver
  clk: sunxi: Add PLL3 clock
  clk: sunxi: Add TCON channel1 clock
  dt-bindings: clk: sun5i: add DRAM gates compatible
  ARM: sun5i: dt: Add pll3 and pll7 clocks
  ARM: sun5i: a13: 

[Bug 80419] XCOM: Enemy Unknown Causes lockup

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=80419

--- Comment #125 from Vladislav Kamenev  ---
How to get dmesg log during lockup?
Got this on r600 driver (AMD Radeon hd6650m TURKS)

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/aa726648/attachment.html>

[Bug 94667] Artifacts on applications on discrete

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94667

--- Comment #5 from Vladislav Kamenev  ---
Created attachment 122503
  --> https://bugs.freedesktop.org/attachment.cgi?id=122503=edit
Xorg.0.log

Logged into Steam.
Waited till artifacts appear.
Published log

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/e74cc4cd/attachment.html>

[Bug 94667] Artifacts on applications on discrete

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94667

--- Comment #4 from Vladislav Kamenev  ---
Created attachment 122502
  --> https://bugs.freedesktop.org/attachment.cgi?id=122502=edit
stderr of $ LIBGL_DEBUG=verbose DRI_PRIME=1 glxinfo 2> stderr

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/c77674be/attachment.html>

[Bug 94667] Artifacts on applications on discrete

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94667

--- Comment #3 from Vladislav Kamenev  ---
(In reply to Michel D�nzer from comment #2)
> Is this a duplicate of bug 94581?

Nope. That was my failure.
I used DRI3 instead of DRI2 at that time and managed to pass that problem.
Now i got artifacts without any feedback from kernel\xorg

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/27b9f200/attachment.html>

Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver]

[Thierry Reding]

On Wed, Mar 23, 2016 at 10:41:58AM +1000, Dave Airlie wrote:
> >
> >> So although it's small framework or just subdirectory, we would need
> >> someone who can manage the framework to avoid further confusion if
> >> necessary.
> >
> > So maybe it just doesn't need a maintainer, and maybe those the owner
> > of the bridge driver should be responsible for choosing the tree which
> > it's merged through along with updates.  That's how dw-hdmi has been
> > managed on the whole.
> >
> > It also means that the bridge driver maintainer is able to test changes
> > to the bridge driver, rather than having some over-arching bridge
> > subdirectory maintainer who doesn't have a clue whether the changes
> > work on the hardware.
> >
> > IMHO, having bridge driver authors/maintainers look after their own
> > code has many advantages.
> 
> The author just send me a pull request with acks from a git tree
> that hopefully both people agreed and tested from. No need to
> send this via another maintainer layer.

I have in the past "maintained" bridge drivers as part of the panel
tree, but I have no objections at all for this to go in via one of the
trees where it is used and can actually be tested.

Thierry
-- next part --
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/2b09a436/attachment.sig>

[PATCH] dma-buf: Update docs for SYNC ioctl

[David Herrmann]

Hi

On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson  
wrote:
> On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote:
>> My question was rather about why we do this? Semantics for EINTR are
>> well defined, and with SA_RESTART (default on linux) user-space can
>> ignore it. However, looping on EAGAIN is very uncommon, and it is not
>> at all clear why it is needed?
>>
>> Returning an error to user-space makes sense if user-space has a
>> reason to react to it. I fail to see how EAGAIN on a cache-flush/sync
>> operation helps user-space at all? As someone without insight into the
>> driver implementation, it is hard to tell why.. Any hints?
>
> The reason we return EAGAIN is to workaround a deadlock we face when
> blocking on the GPU holding the struct_mutex (inside the client's
> process), but the GPU is dead. As our locking is very, very coarse we
> cannot restart the GPU without acquiring the struct_mutex being held by
> the client so we wake the client up and tell them the resource they are
> waiting on (the flush of the object from the GPU into the CPU domain) is
> temporarily unavailable. If they try to immediately wait upon the ioctl
> again, they are blocked waiting for the reset to occur before they may
> complete their flush. There are a few other possible deadlocks that are
> also avoided with EAGAIN (again, the issue is more or less the lack of
> fine grained locking).

...so you hijacked EAGAIN for all DRM ioctls just for a driver
workaround? EAGAIN is universally used to signal the caller about a
blocking resource. It is very much linked to O_NONBLOCK. Why not use
EBUSY, ECANCELED, ECOMM, EDEADLOCK, EIO, EL3RST, ...

Anyhow, I guess that ship has sailed. But just mentioning EAGAIN in a
kernel-doc is way to vague for user-space to figure out they should
loop on it.

Thanks
David

[PATCH] adv7511: Set picture aspect ratio

[Jose Abreu]

As of current version the picture aspect ratio and active
aspect ratio are not being set when the video mode changes.
This patch fixes this problem by setting the picture aspect
ratio according to the current video mode and also sets the
active aspect ratio to be the same as picture aspect ratio.

Signed-off-by: Jose Abreu 
---
 drivers/gpu/drm/i2c/adv7511.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
index a02112b..c9aa83a 100644
--- a/drivers/gpu/drm/i2c/adv7511.c
+++ b/drivers/gpu/drm/i2c/adv7511.c
@@ -672,7 +672,7 @@ static void adv7511_encoder_mode_set(struct drm_encoder 
*encoder,
 struct drm_display_mode *adj_mode)
 {
struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
-   unsigned int low_refresh_rate;
+   unsigned int low_refresh_rate, picture_aspect;
unsigned int hsync_polarity = 0;
unsigned int vsync_polarity = 0;

@@ -754,6 +754,26 @@ static void adv7511_encoder_mode_set(struct drm_encoder 
*encoder,
regmap_update_bits(adv7511->regmap, 0x17,
0x60, (vsync_polarity << 6) | (hsync_polarity << 5));

+   switch (adj_mode->picture_aspect_ratio) {
+   case HDMI_PICTURE_ASPECT_NONE:
+   picture_aspect = 0x0;
+   break;
+   case HDMI_PICTURE_ASPECT_4_3:
+   picture_aspect = 0x1;
+   break;
+   case HDMI_PICTURE_ASPECT_16_9:
+   picture_aspect = 0x2;
+   break;
+   default:
+   picture_aspect = 0x3;
+   break;
+   }
+
+   regmap_update_bits(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME(1),
+   0x30, (picture_aspect << 4));
+   regmap_update_bits(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME(1),
+   0x0F, 0x08);
+
/*
 * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is
 * supposed to give better results.
-- 
1.9.1

[RFC 00/29] De-stage android's sync framework

[Tomeu Vizoso]

On 19 January 2016 at 17:12, John Harrison  wrote:
> On 19/01/2016 15:23, Gustavo Padovan wrote:
>>
>> Hi Daniel,
>>
>> 2016-01-19 Daniel Vetter :
>>
>>> On Fri, Jan 15, 2016 at 12:55:10PM -0200, Gustavo Padovan wrote:

 From: Gustavo Padovan 

 This patch series de-stage the sync framework, and in order to
 accomplish that
 a bunch of cleanups/improvements on the sync and fence were made.

 The sync framework contained some abstractions around struct fence and
 those
 were removed in the de-staging process among other changes:

 Userspace visible changes
 -

   * The sw_sync file was moved from /dev/sw_sync to
 /sync/sw_sync. No
   other change.

 Kernel API changes
 --

   * struct sync_timeline is now struct fence_timeline
   * sync_timeline_ops is now fence_timeline_ops and they now carry
 struct
   fence as parameter instead of struct sync_pt
   * a .cleanup() fence op was added to allow sync_fence to run a cleanup
 when
   the fence_timeline is destroyed
   * added fence_add_used_data() to pass a private point to struct fence.
 This
   pointer is sent back on the .cleanup op.
   * The sync timeline function were moved to be fence_timeline
 functions:
  - sync_timeline_create()   -> fence_timeline_create()
  - sync_timeline_get()  -> fence_timeline_get()
  - sync_timeline_put()  -> fence_timeline_put()
  - sync_timeline_destroy()  -> fence_timeline_destroy()
  - sync_timeline_signal()   -> fence_timeline_signal()

* sync_pt_create() was replaced be fence_create_on_timeline()

 Internal changes
 

   * fence_timeline_ops was removed in favor of direct use fence_ops
   * fence default functions were created for fence_ops
   * removed structs sync_pt, sw_sync_timeline and sw_sync_pt
>>>
>>> Bunch of fairly random comments all over:
>>>
>>> - include/uapi/linux/sw_sync.h imo should be dropped, it's just a private
>>>debugfs interface between fence fds and the testsuite. Since the plan
>>> is
>>>to have the testcases integrated into the kernel tree too we don't
>>> need
>>>a public header.
>>>
>>> - similar for include/linux/sw_sync.h Imo that should all be moved into
>>>sync_debug.c. Same for sw_sync.c, that should all land in sync_debug
>>>imo, and made optional with a Kconfig option. At least we should reuse
>>>CONFIG_DEBUGFS.
>>
>> These two items sounds reasonable to me.
>
>
> I have just posted our in-progress IGT for testing i915 syncs (with a CC of
> Gustavo). It uses the sw_sync mechanisms. Can you take a quick look and see
> if it is the kind of thing you would expect us to be doing? Or is it using
> interfaces that you are planning to remove and/or make kernel only?
>
> I'm not sure having a kernel only test is the best way to go. Having user
> land tests like IGT would be much more versatile.

Hi John,

I'm working on making the tests in igt useful for drivers other than
i915 and would love to have tests for the fence functionality. Have
you made any progress since you posted that RFC?

Thanks,

Tomeu

[RFC 6/6] drm/fence: support fence_collection on atomic commit

[Gustavo Padovan]

From: Gustavo Padovan 

Let atomic_commit() wait on a collection of fences before proceed with
the scanout.

Signed-off-by: Gustavo Padovan 
---
 drivers/gpu/drm/drm_atomic.c| 9 +
 drivers/gpu/drm/drm_atomic_helper.c | 9 +
 include/drm/drm_crtc.h  | 2 +-
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8bc364c..28a65d1 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 

 /**
  * drm_atomic_state_default_release -
@@ -795,6 +796,14 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
return -EINVAL;
}

+#ifdef CONFIG_SYNC_FILE
+   if (state->fence_fd >= 0) {
+   state->fences = sync_file_fences_get(state->fence_fd);
+   if (!state->fences)
+   return -EINVAL;
+   }
+#endif
+
return 0;
 }

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 4f91f84..a6e34b6 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -977,14 +977,12 @@ static void wait_for_fences(struct drm_device *dev,
int i;

for_each_plane_in_state(state, plane, plane_state, i) {
-   if (!plane->state->fence)
+   if (!plane->state->fences)
continue;

WARN_ON(!plane->state->fb);

-   fence_wait(plane->state->fence, false);
-   fence_put(plane->state->fence);
-   plane->state->fence = NULL;
+   fence_collection_wait(plane->state->fences);
}
 }

@@ -2654,6 +2652,9 @@ void __drm_atomic_helper_plane_destroy_state(struct 
drm_plane *plane,
 {
if (state->fb)
drm_framebuffer_unreference(state->fb);
+
+   if (state->fences)
+   fence_collection_put(state->fences);
 }
 EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index a8f6ec0..c221c28 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1257,7 +1257,7 @@ struct drm_plane_state {

struct drm_crtc *crtc;   /* do not write directly, use 
drm_atomic_set_crtc_for_plane() */
struct drm_framebuffer *fb;  /* do not write directly, use 
drm_atomic_set_fb_for_plane() */
-   struct fence *fence;
+   struct fence_collection *fences;
int fence_fd;

/* Signed dest location allows it to be partially off screen */
-- 
2.5.0

[RFC 5/6] dma-buf/fence: add fence_collection_wait()

[Gustavo Padovan]

From: Gustavo Padovan 

Iterate over the array of fences and wait for all of the to finish.

Signed-off-by: Gustavo Padovan 
---
 drivers/dma-buf/fence.c | 16 
 include/linux/fence.h   |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/dma-buf/fence.c b/drivers/dma-buf/fence.c
index a3fe3e7..31e554b 100644
--- a/drivers/dma-buf/fence.c
+++ b/drivers/dma-buf/fence.c
@@ -532,6 +532,22 @@ fence_init(struct fence *fence, const struct fence_ops 
*ops,
 EXPORT_SYMBOL(fence_init);

 /**
+ * fence_collection_wait - Wait for collection of fences to signal
+ * @collection:[in]the collection to wait on
+ *
+ * This functions simplifies the waiting process when one needs to
+ * wait for many fences at the same time.
+ */
+void fence_collection_wait(struct fence_collection *collection)
+{
+   int i;
+
+   for (i = 0 ; i < collection->num_fences ; i++)
+   fence_wait(collection->fences[i], false);
+}
+EXPORT_SYMBOL(fence_collection_wait);
+
+/**
  * fence_collection_put - put all the fences in a collection
  * @collection:[in]the collection to put fences
  *
diff --git a/include/linux/fence.h b/include/linux/fence.h
index 3f871b0..52f1aea 100644
--- a/include/linux/fence.h
+++ b/include/linux/fence.h
@@ -244,6 +244,7 @@ int fence_add_callback(struct fence *fence, struct fence_cb 
*cb,
 bool fence_remove_callback(struct fence *fence, struct fence_cb *cb);
 void fence_enable_sw_signaling(struct fence *fence);

+void fence_collection_wait(struct fence_collection *collection);
 void fence_collection_put(struct fence_collection *collection);

 /**
-- 
2.5.0

[RFC 4/6] dma-buf/fence: add fence_collection_put()

[Gustavo Padovan]

From: Gustavo Padovan 

Put fence_collection data. For that calls fence_put() on all fences
and the user put callback.

Signed-off-by: Gustavo Padovan 
---
 drivers/dma-buf/fence.c | 17 +
 include/linux/fence.h   |  2 ++
 2 files changed, 19 insertions(+)

diff --git a/drivers/dma-buf/fence.c b/drivers/dma-buf/fence.c
index 7b05dbe..a3fe3e7 100644
--- a/drivers/dma-buf/fence.c
+++ b/drivers/dma-buf/fence.c
@@ -530,3 +530,20 @@ fence_init(struct fence *fence, const struct fence_ops 
*ops,
trace_fence_init(fence);
 }
 EXPORT_SYMBOL(fence_init);
+
+/**
+ * fence_collection_put - put all the fences in a collection
+ * @collection:[in]the collection to put fences
+ *
+ * This functions unrefs all fences in the collection.
+ */
+void fence_collection_put(struct fence_collection *collection)
+{
+   int i;
+
+   for (i = 0 ; i < collection->num_fences ; i++)
+   fence_put(collection->fences[i]);
+
+   collection->func(collection->user_data);
+}
+EXPORT_SYMBOL(fence_collection_put);
diff --git a/include/linux/fence.h b/include/linux/fence.h
index 3d1151f..3f871b0 100644
--- a/include/linux/fence.h
+++ b/include/linux/fence.h
@@ -244,6 +244,8 @@ int fence_add_callback(struct fence *fence, struct fence_cb 
*cb,
 bool fence_remove_callback(struct fence *fence, struct fence_cb *cb);
 void fence_enable_sw_signaling(struct fence *fence);

+void fence_collection_put(struct fence_collection *collection);
+
 /**
  * fence_is_signaled_locked - Return an indication if the fence is signaled 
yet.
  * @fence: [in]the fence to check
-- 
2.5.0

[RFC 2/6] dma-buf/fence: add struct fence_collection

[Gustavo Padovan]

From: Gustavo Padovan 

The struct aggregates fences that we need to wait on before proceed with
some specific operation. In DRM, for example, we may wait for a group of
fences to signal before we scanout the buffers related to those fences.

Signed-off-by: Gustavo Padovan 
---
 include/linux/fence.h | 16 
 1 file changed, 16 insertions(+)

diff --git a/include/linux/fence.h b/include/linux/fence.h
index 605bd88..3d1151f 100644
--- a/include/linux/fence.h
+++ b/include/linux/fence.h
@@ -104,6 +104,22 @@ struct fence_cb {
fence_func_t func;
 };

+typedef void (*collection_put_func_t)(void *data);
+
+/**
+ * struct fence_collection - aggregate fences together
+ * @num_fences: number of fence in the collection.
+ * @user_data: user data.
+ * @func: user callback to put user data.
+ * @fences: array of @num_fences fences.
+ */
+struct fence_collection {
+   int num_fences;
+   void *user_data;
+   collection_put_func_t func;
+   struct fence *fences[];
+};
+
 /**
  * struct fence_ops - operations implemented for fence
  * @get_driver_name: returns the driver name.
-- 
2.5.0

[RFC 1/6] drm/fence: add FENCE_FD property to planes

[Gustavo Padovan]

From: Gustavo Padovan 

FENCE_FD can now be set by the user during an atomic IOCTL, it
will be used by atomic_commit to wait until the sync_file is signalled,
i.e., the framebuffer is ready for scanout.

Signed-off-by: Gustavo Padovan 
---
 drivers/gpu/drm/drm_atomic.c| 4 
 drivers/gpu/drm/drm_atomic_helper.c | 1 +
 drivers/gpu/drm/drm_crtc.c  | 7 +++
 include/drm/drm_crtc.h  | 3 +++
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8fb469c..8bc364c 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -609,6 +609,8 @@ int drm_atomic_plane_set_property(struct drm_plane *plane,
drm_atomic_set_fb_for_plane(state, fb);
if (fb)
drm_framebuffer_unreference(fb);
+   } else if (property == config->prop_fence_fd) {
+   state->fence_fd = val;
} else if (property == config->prop_crtc_id) {
struct drm_crtc *crtc = drm_crtc_find(dev, val);
return drm_atomic_set_crtc_for_plane(state, crtc);
@@ -666,6 +668,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,

if (property == config->prop_fb_id) {
*val = (state->fb) ? state->fb->base.id : 0;
+   } else if (property == config->prop_fence_fd) {
+   *val = state->fence_fd;
} else if (property == config->prop_crtc_id) {
*val = (state->crtc) ? state->crtc->base.id : 0;
} else if (property == config->prop_crtc_x) {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 2b430b0..4f91f84 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2594,6 +2594,7 @@ void drm_atomic_helper_plane_reset(struct drm_plane 
*plane)
if (plane->state) {
plane->state->plane = plane;
plane->state->rotation = BIT(DRM_ROTATE_0);
+   plane->state->fence_fd = -1;
}
 }
 EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 65258ac..165f199 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1291,6 +1291,7 @@ int drm_universal_plane_init(struct drm_device *dev, 
struct drm_plane *plane,

if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
drm_object_attach_property(>base, config->prop_fb_id, 0);
+   drm_object_attach_property(>base, config->prop_fence_fd, 
-1);
drm_object_attach_property(>base, config->prop_crtc_id, 
0);
drm_object_attach_property(>base, config->prop_crtc_x, 
0);
drm_object_attach_property(>base, config->prop_crtc_y, 
0);
@@ -1546,6 +1547,12 @@ static int drm_mode_create_standard_properties(struct 
drm_device *dev)
return -ENOMEM;
dev->mode_config.prop_fb_id = prop;

+   prop = drm_property_create_signed_range(dev, DRM_MODE_PROP_ATOMIC,
+   "FENCE_FD", -1, INT_MAX);
+   if (!prop)
+   return -ENOMEM;
+   dev->mode_config.prop_fence_fd = prop;
+
prop = drm_property_create_object(dev, DRM_MODE_PROP_ATOMIC,
"CRTC_ID", DRM_MODE_OBJECT_CRTC);
if (!prop)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8c7fb3d..a8f6ec0 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1239,6 +1239,7 @@ struct drm_connector {
  * @crtc: currently bound CRTC, NULL if disabled
  * @fb: currently bound framebuffer
  * @fence: optional fence to wait for before scanning out @fb
+ * @fence_fd: fd representing the sync_fence
  * @crtc_x: left position of visible portion of plane on crtc
  * @crtc_y: upper position of visible portion of plane on crtc
  * @crtc_w: width of visible portion of plane on crtc
@@ -1257,6 +1258,7 @@ struct drm_plane_state {
struct drm_crtc *crtc;   /* do not write directly, use 
drm_atomic_set_crtc_for_plane() */
struct drm_framebuffer *fb;  /* do not write directly, use 
drm_atomic_set_fb_for_plane() */
struct fence *fence;
+   int fence_fd;

/* Signed dest location allows it to be partially off screen */
int32_t crtc_x, crtc_y;
@@ -2098,6 +2100,7 @@ struct drm_mode_config {
struct drm_property *prop_crtc_w;
struct drm_property *prop_crtc_h;
struct drm_property *prop_fb_id;
+   struct drm_property *prop_fence_fd;
struct drm_property *prop_crtc_id;
struct drm_property *prop_active;
struct drm_property *prop_mode_id;
-- 
2.5.0

[RFC 0/6] drm/fences: add in-fences to DRM

[Gustavo Padovan]

From: Gustavo Padovan 

Hi,

This is a first proposal to discuss the addition of in-fences support
to DRM. It adds a new struct to fence.c to abstract the use of sync_file
in DRM drivers. The new struct fence_collection contains a array with all
fences that a atomic commit needs to wait on

/**
 * struct fence_collection - aggregate fences together
 * @num_fences: number of fence in the collection.
 * @user_data: user data.
 * @func: user callback to put user data.
 * @fences: array of @num_fences fences.
 */
struct fence_collection {
   int num_fences;
   void *user_data;
   collection_put_func_t func;
   struct fence *fences[];
};


The fence_collection is allocated and filled by sync_file_fences_get() and
atomic_commit helpers can use fence_collection_wait() to wait the fences to
signal.

These patches depends on the sync ABI rework:

https://www.spinics.net/lists/dri-devel/msg102795.html

and the patch to de-stage the sync framework:

https://www.spinics.net/lists/dri-devel/msg102799.html


I also hacked together some sync support into modetest for testing:

https://git.collabora.com/cgit/user/padovan/libdrm.git/log/?h=atomic


Gustavo


Gustavo Padovan (6):
  drm/fence: add FENCE_FD property to planes
  dma-buf/fence: add struct fence_collection
  dma-buf/sync_file: add sync_file_fences_get()
  dma-buf/fence: add fence_collection_put()
  dma-buf/fence: add fence_collection_wait()
  drm/fence: support fence_collection on atomic commit

 drivers/dma-buf/fence.c | 33 +
 drivers/dma-buf/sync_file.c | 36 
 drivers/gpu/drm/drm_atomic.c| 13 +
 drivers/gpu/drm/drm_atomic_helper.c | 10 ++
 drivers/gpu/drm/drm_crtc.c  |  7 +++
 include/drm/drm_crtc.h  |  5 -
 include/linux/fence.h   | 19 +++
 include/linux/sync_file.h   |  8 
 8 files changed, 126 insertions(+), 5 deletions(-)

-- 
2.5.0

[PATCH] dma-buf: Update docs for SYNC ioctl

[Chris Wilson]

On Wed, Mar 23, 2016 at 04:32:59PM +0100, David Herrmann wrote:
> Hi
> 
> On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson  
> wrote:
> > On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote:
> >> My question was rather about why we do this? Semantics for EINTR are
> >> well defined, and with SA_RESTART (default on linux) user-space can
> >> ignore it. However, looping on EAGAIN is very uncommon, and it is not
> >> at all clear why it is needed?
> >>
> >> Returning an error to user-space makes sense if user-space has a
> >> reason to react to it. I fail to see how EAGAIN on a cache-flush/sync
> >> operation helps user-space at all? As someone without insight into the
> >> driver implementation, it is hard to tell why.. Any hints?
> >
> > The reason we return EAGAIN is to workaround a deadlock we face when
> > blocking on the GPU holding the struct_mutex (inside the client's
> > process), but the GPU is dead. As our locking is very, very coarse we
> > cannot restart the GPU without acquiring the struct_mutex being held by
> > the client so we wake the client up and tell them the resource they are
> > waiting on (the flush of the object from the GPU into the CPU domain) is
> > temporarily unavailable. If they try to immediately wait upon the ioctl
> > again, they are blocked waiting for the reset to occur before they may
> > complete their flush. There are a few other possible deadlocks that are
> > also avoided with EAGAIN (again, the issue is more or less the lack of
> > fine grained locking).
> 
> ...so you hijacked EAGAIN for all DRM ioctls just for a driver
> workaround?

No, we utilized the fact that EAGAIN was already enshrined by libdrm as
the defacto mechanism for repeating the ioctl in order to repeat the
ioctl for a driver workaround.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH v3 1/2 RESEND] drm/dp_helper: add workarounds from intel_dp_dpcd_read_wake()

[Lyude]

Some sinks need some time during the process of resuming the system from
sleep before they're ready to handle transactions. While it would be
nice if they responded with NACKs in these scenarios, this isn't always
the case as a few sinks will just timeout on all of the transactions
they receive.

This patch was originally intended to be a workaround for a very
mysterious bug on the T560, where any monitors connected to the dock
would fail to turn back on after resume. When resuming the laptop, it
appears that there's a short period of time where we're unable to
complete any aux transactions, as they all immediately timeout. The only
machine I'm able to reproduce this on is the T560 as other production
Skylake models seem to be fine. The period during which AUX transactions
fail appears to be around 22ms long. AFAIK, the dock for the T560 never
actually turns off, the only difference is that it's in SST mode at the
start of the resume process, so it's unclear as to why it would need so
much time to come back up.

There's been a discussion on this issue going on for a while on the
intel-gfx mailing list about this that has, in addition to including
developers from Intel, also had the correspondence of one of the
hardware engineers for Intel:

http://www.spinics.net/lists/intel-gfx/msg88831.html
http://www.spinics.net/lists/intel-gfx/msg88410.html

We've already looked into a couple of possible explanations for the
problem:

- Calling intel_dp_mst_resume() before right fix.
  intel_runtime_pm_enable_interrupts(). This was the first fix I tried,
  and while it worked it definitely wasn't the right fix. This worked
  because DP aux transactions don't actually require interrupts to work:

static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
struct intel_digital_port *intel_dig_port = 
dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
uint32_t status;
bool done;

#define C (((status = I915_READ_NOTRACE(ch_ctl)) & 
DP_AUX_CH_CTL_SEND_BUSY) == 0)
if (has_aux_irq)
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  msecs_to_jiffies_timeout(10));
else
done = wait_for_atomic(C, 10) == 0;
if (!done)
DRM_ERROR("dp aux hw did not signal timeout (has irq: 
%i)!\n",
  has_aux_irq);
#undef C

return status;
}

  When there's no interrupts enabled, we end up timing out on the
  wait_event_timeout() call, which causes us to check the DP status
  register once to see if the transaction was successful or not. Since
  this adds a 10ms delay to each aux transaction, it ends up adding a
  long enough delay to the resume process for aux transactions to become
  functional again. This gave us the illusion that enabling interrupts
  had something to do with making things work again, and put me on the
  wrong track for a while.

- Interrupts occurring when we try to perform the aux transactions
  required to put the dock back into MST mode. This isn't the problem,
  as the only interrupts I've observed that come during this timeout
  period are from the snd_hda_intel driver, and disabling that driver
  doesn't appear to change the behavior at all.

- Skylake's PSR block causing issues by performing aux transactions
  while we try to bring the dock out of MST mode. Disabling PSR through
  i915's command line options doesn't seem to change the behavior
  either, nor does preventing the DMC firmware from being loaded.

Since this investigation went on for about 2 weeks, we decided it would
be better for the time being to just workaround this issue until we find
a better fix. This patch adds some behavior we want in
drm_dp_dpcd_access() anyway, since DP aux transactions aren't exactly
robust and this will probably fix quite a few other issues with DP MST
hardware not responding in time. Plus, this is something we already do
in the i915 driver with intel_dp_dpcd_read_wake(), except that that
function is somewhat of a hack and DRM helpers can't make use of it.

Changes since v2
- Reworked the patch again to incorporate all of the behavior of
  intel_dp_dpcd_read_wake() into drm_dp_dpcd_read() and
  drm_dp_dpcd_access()

Changes since v1

- Patch has been reworked to take the retry logic out of
  intel_dp_mst_resume() and into drm_dp_dpcd_access(), based off a
  suggestion from Daniel Vetter

- Commit message is much longer and gives a better description of the
  issue this was originally intended to workaround.

Signed-off-by: Lyude 
---
Left some rebase ditritus 

[PATCH v3 1/2] drm/dp_helper: add workarounds from intel_dp_dpcd_read_wake()

[Lyude]

Some sinks need some time during the process of resuming the system from
sleep before they're ready to handle transactions. While it would be
nice if they responded with NACKs in these scenarios, this isn't always
the case as a few sinks will just timeout on all of the transactions
they receive.

This patch was originally intended to be a workaround for a very
mysterious bug on the T560, where any monitors connected to the dock
would fail to turn back on after resume. When resuming the laptop, it
appears that there's a short period of time where we're unable to
complete any aux transactions, as they all immediately timeout. The only
machine I'm able to reproduce this on is the T560 as other production
Skylake models seem to be fine. The period during which AUX transactions
fail appears to be around 22ms long. AFAIK, the dock for the T560 never
actually turns off, the only difference is that it's in SST mode at the
start of the resume process, so it's unclear as to why it would need so
much time to come back up.

There's been a discussion on this issue going on for a while on the
intel-gfx mailing list about this that has, in addition to including
developers from Intel, also had the correspondence of one of the
hardware engineers for Intel:

http://www.spinics.net/lists/intel-gfx/msg88831.html
http://www.spinics.net/lists/intel-gfx/msg88410.html

We've already looked into a couple of possible explanations for the
problem:

- Calling intel_dp_mst_resume() before right fix.
  intel_runtime_pm_enable_interrupts(). This was the first fix I tried,
  and while it worked it definitely wasn't the right fix. This worked
  because DP aux transactions don't actually require interrupts to work:

static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
struct intel_digital_port *intel_dig_port = 
dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
uint32_t status;
bool done;

#define C (((status = I915_READ_NOTRACE(ch_ctl)) & 
DP_AUX_CH_CTL_SEND_BUSY) == 0)
if (has_aux_irq)
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  msecs_to_jiffies_timeout(10));
else
done = wait_for_atomic(C, 10) == 0;
if (!done)
DRM_ERROR("dp aux hw did not signal timeout (has irq: 
%i)!\n",
  has_aux_irq);
#undef C

return status;
}

  When there's no interrupts enabled, we end up timing out on the
  wait_event_timeout() call, which causes us to check the DP status
  register once to see if the transaction was successful or not. Since
  this adds a 10ms delay to each aux transaction, it ends up adding a
  long enough delay to the resume process for aux transactions to become
  functional again. This gave us the illusion that enabling interrupts
  had something to do with making things work again, and put me on the
  wrong track for a while.

- Interrupts occurring when we try to perform the aux transactions
  required to put the dock back into MST mode. This isn't the problem,
  as the only interrupts I've observed that come during this timeout
  period are from the snd_hda_intel driver, and disabling that driver
  doesn't appear to change the behavior at all.

- Skylake's PSR block causing issues by performing aux transactions
  while we try to bring the dock out of MST mode. Disabling PSR through
  i915's command line options doesn't seem to change the behavior
  either, nor does preventing the DMC firmware from being loaded.

Since this investigation went on for about 2 weeks, we decided it would
be better for the time being to just workaround this issue until we find
a better fix. This patch adds some behavior we want in
drm_dp_dpcd_access() anyway, since DP aux transactions aren't exactly
robust and this will probably fix quite a few other issues with DP MST
hardware not responding in time. Plus, this is something we already do
in the i915 driver with intel_dp_dpcd_read_wake(), except that that
function is somewhat of a hack and DRM helpers can't make use of it.

Changes since v2
- Reworked the patch again to incorporate all of the behavior of
  intel_dp_dpcd_read_wake() into drm_dp_dpcd_read() and
  drm_dp_dpcd_access()

Changes since v1

- Patch has been reworked to take the retry logic out of
  intel_dp_mst_resume() and into drm_dp_dpcd_access(), based off a
  suggestion from Daniel Vetter

- Commit message is much longer and gives a better description of the
  issue this was originally intended to workaround.

Signed-off-by: Lyude 

squash! drm/dp_helper: retry 

[PATCH 02/23] ARM: dts: n950: add display support

[Sebastian Reichel]

Hi,

On Wed, Mar 23, 2016 at 02:40:53PM +0200, Jani Nikula wrote:
> On Thu, 17 Mar 2016, Sebastian Reichel  wrote:
> > On Thu, Mar 17, 2016 at 02:14:26PM +0200, Laurent Pinchart wrote:
> >> [...]
> >> > +
> >> > +/* panel is 480x464 with top and bottom 5 lines not 
> >> > visible */
> >> 
> >> I assume you mean 480x864 ?
> >
> > Yes, nice catch. Basically the screen is 480x864, but only
> > 480x854 are visible.
> 
> It's been a while, but I thought the full 480x864 was actually usable
> and visible.

I tried that first and the first few lines were missing. The stock
kernel also uses only 854px:

https://github.com/nemomobile/kernel-adaptation-n950-n9/blob/mer-n9-2.6.32-20121301/arch/arm/mach-omap2/board-rm680-video.c

(search for partial_area)

-- Sebastian
-- next part --
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/f6490bea/attachment-0001.sig>

[PATCH 02/23] ARM: dts: n950: add display support

[Jani Nikula]

On Thu, 17 Mar 2016, Sebastian Reichel  wrote:
> On Thu, Mar 17, 2016 at 02:14:26PM +0200, Laurent Pinchart wrote:
>> [...]
>> > +
>> > +  /* panel is 480x464 with top and bottom 5 lines not visible */
>> 
>> I assume you mean 480x864 ?
>
> Yes, nice catch. Basically the screen is 480x864, but only
> 480x854 are visible.

It's been a while, but I thought the full 480x864 was actually usable
and visible.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center

[PATCH 6/6] drm/exynos: convert clock_enable crtc callback to pipeline clock

[Andrzej Hajda]

clock_enable callback is used only by FIMD->DP pipeline. Similar but more
universal functionality provides pipeline clock.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_dp_core.c  |  8 ++--
 drivers/gpu/drm/exynos/exynos_drm_drv.h  |  5 -
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 27 +--
 3 files changed, 15 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index cff8dc7..ebb96eb 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1054,7 +1054,6 @@ static int exynos_dp_bridge_attach(struct drm_bridge 
*bridge)
 static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
struct exynos_dp_device *dp = bridge->driver_private;
-   struct exynos_drm_crtc *crtc = dp_to_crtc(dp);

if (dp->dpms_mode == DRM_MODE_DPMS_ON)
return;
@@ -1068,8 +1067,7 @@ static void exynos_dp_bridge_enable(struct drm_bridge 
*bridge)
}
}

-   if (crtc->ops->clock_enable)
-   crtc->ops->clock_enable(dp_to_crtc(dp), true);
+   exynos_drm_pipe_clk_enable(dp_to_crtc(dp), true);

phy_power_on(dp->phy);
exynos_dp_init_dp(dp);
@@ -1082,7 +1080,6 @@ static void exynos_dp_bridge_enable(struct drm_bridge 
*bridge)
 static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
struct exynos_dp_device *dp = bridge->driver_private;
-   struct exynos_drm_crtc *crtc = dp_to_crtc(dp);

if (dp->dpms_mode != DRM_MODE_DPMS_ON)
return;
@@ -1098,8 +1095,7 @@ static void exynos_dp_bridge_disable(struct drm_bridge 
*bridge)
flush_work(>hotplug_work);
phy_power_off(dp->phy);

-   if (crtc->ops->clock_enable)
-   crtc->ops->clock_enable(dp_to_crtc(dp), false);
+   exynos_drm_pipe_clk_enable(dp_to_crtc(dp), false);

if (dp->panel) {
if (drm_panel_unprepare(dp->panel))
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 6ee0b20..1542910 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -129,10 +129,6 @@ struct exynos_drm_plane_config {
  * @disable_plane: disable hardware specific overlay.
  * @te_handler: trigger to transfer video image at the tearing effect
  * synchronization signal if there is a page flip request.
- * @clock_enable: optional function enabling/disabling display domain clock,
- * called from exynos-dp driver before powering up (with
- * 'enable' argument as true) and after powering down (with
- * 'enable' as false).
  */
 struct exynos_drm_crtc;
 struct exynos_drm_crtc_ops {
@@ -151,7 +147,6 @@ struct exynos_drm_crtc_ops {
  struct exynos_drm_plane *plane);
void (*atomic_flush)(struct exynos_drm_crtc *crtc);
void (*te_handler)(struct exynos_drm_crtc *crtc);
-   void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
 };

 struct exynos_drm_clk {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 51d484a..004bf57 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -102,6 +102,7 @@ struct fimd_driver_data {
unsigned int has_vidoutcon:1;
unsigned int has_vtsel:1;
unsigned int has_mic_bypass:1;
+   unsigned int has_dp_clk:1;
 };

 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -145,6 +146,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = {
.has_shadowcon = 1,
.has_vidoutcon = 1,
.has_vtsel = 1,
+   .has_dp_clk = 1,
 };

 static struct fimd_driver_data exynos5420_fimd_driver_data = {
@@ -157,6 +159,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data 
= {
.has_vidoutcon = 1,
.has_vtsel = 1,
.has_mic_bypass = 1,
+   .has_dp_clk = 1,
 };

 struct fimd_context {
@@ -184,6 +187,7 @@ struct fimd_context {

struct fimd_driver_data *driver_data;
struct drm_encoder *encoder;
+   struct exynos_drm_clk   dp_clk;
 };

 static const struct of_device_id fimd_driver_dt_match[] = {
@@ -878,21 +882,12 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc)
drm_crtc_handle_vblank(>crtc->base);
 }

-static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
+static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 {
-   struct fimd_context *ctx = crtc->ctx;
-   u32 val;
-
-   /*
-* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
-* clock. On these SoCs the bootloader may enable it but any
-* power domain off/on will reset it to disable state.
-*/
-   if (ctx->driver_data != _fimd_driver_data ||
-   ctx->driver_data != _fimd_driver_data)
-  

[PATCH 5/6] drm/exynos/mixer: enable HDMI-PHY before configuring MIXER

[Andrzej Hajda]

According to documentation HDMI-PHY must be on prior to MIXER configuration.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c 
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 0a5a600..27f36c0 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -1065,6 +1065,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)

pm_runtime_get_sync(ctx->dev);

+   exynos_drm_pipe_clk_enable(crtc, true);
+
mixer_vsync_set_update(ctx, false);

mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
@@ -1094,6 +1096,8 @@ static void mixer_disable(struct exynos_drm_crtc *crtc)
for (i = 0; i < MIXER_WIN_NR; i++)
mixer_disable_plane(crtc, >planes[i]);

+   exynos_drm_pipe_clk_enable(crtc, false);
+
pm_runtime_put(ctx->dev);

clear_bit(MXR_BIT_POWERED, >flags);
-- 
1.9.1

[PATCH 4/6] drm/exynos/decon5433: enable HDMI-PHY before configuring DECON

[Andrzej Hajda]

According to documentation and tests HDMI-PHY must be on prior
to MIXER configuration.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index c8c921c..26b582c 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -393,6 +393,8 @@ static void decon_enable(struct exynos_drm_crtc *crtc)

pm_runtime_get_sync(ctx->dev);

+   exynos_drm_pipe_clk_enable(crtc, true);
+
set_bit(BIT_CLKS_ENABLED, >flags);

decon_swreset(ctx);
@@ -424,6 +426,8 @@ static void decon_disable(struct exynos_drm_crtc *crtc)

clear_bit(BIT_CLKS_ENABLED, >flags);

+   exynos_drm_pipe_clk_enable(crtc, false);
+
pm_runtime_put_sync(ctx->dev);

set_bit(BIT_SUSPENDED, >flags);
-- 
1.9.1

[PATCH 3/6] drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock

[Andrzej Hajda]

HDMI-PHY clock should be accessible from other components in the pipeline.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 67 ++--
 1 file changed, 48 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 49a5902..0d1c2f0 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -146,6 +146,7 @@ struct hdmi_context {
struct clk  **clk_muxes;
struct regulator_bulk_data  regul_bulk[ARRAY_SIZE(supply)];
struct regulator*reg_hdmi_en;
+   struct exynos_drm_clk   phy_clk;
 };

 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
@@ -1448,7 +1449,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)

 static void hdmi_conf_apply(struct hdmi_context *hdata)
 {
-   hdmiphy_conf_apply(hdata);
hdmi_start(hdata, false);
hdmi_conf_init(hdata);
hdmi_audio_init(hdata);
@@ -1481,10 +1481,8 @@ static void hdmi_set_refclk(struct hdmi_context *hdata, 
bool on)
   SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
 }

-static void hdmi_enable(struct drm_encoder *encoder)
+static void hdmiphy_enable(struct hdmi_context *hdata)
 {
-   struct hdmi_context *hdata = encoder_to_hdmi(encoder);
-
if (hdata->powered)
return;

@@ -1500,11 +1498,40 @@ static void hdmi_enable(struct drm_encoder *encoder)

hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);

-   hdmi_conf_apply(hdata);
+   hdmiphy_conf_apply(hdata);

hdata->powered = true;
 }

+static void hdmiphy_disable(struct hdmi_context *hdata)
+{
+   if (!hdata->powered)
+   return;
+
+   hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
+
+   hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
+
+   hdmi_set_refclk(hdata, false);
+
+   regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
+   PMU_HDMI_PHY_ENABLE_BIT, 0);
+
+   regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
+
+   pm_runtime_put_sync(hdata->dev);
+
+   hdata->powered = false;
+}
+
+static void hdmi_enable(struct drm_encoder *encoder)
+{
+   struct hdmi_context *hdata = encoder_to_hdmi(encoder);
+
+   hdmiphy_enable(hdata);
+   hdmi_conf_apply(hdata);
+}
+
 static void hdmi_disable(struct drm_encoder *encoder)
 {
struct hdmi_context *hdata = encoder_to_hdmi(encoder);
@@ -1528,22 +1555,9 @@ static void hdmi_disable(struct drm_encoder *encoder)
if (funcs && funcs->disable)
(*funcs->disable)(crtc);

-   hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
-
cancel_delayed_work(>hotplug_work);

-   hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
-
-   hdmi_set_refclk(hdata, false);
-
-   regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
-   PMU_HDMI_PHY_ENABLE_BIT, 0);
-
-   regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
-
-   pm_runtime_put_sync(hdata->dev);
-
-   hdata->powered = false;
+   hdmiphy_disable(hdata);
 }

 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs 
= {
@@ -1627,6 +1641,17 @@ static int hdmi_clk_init(struct hdmi_context *hdata)
return hdmi_clks_get(hdata, _data->clk_muxes, hdata->clk_muxes);
 }

+static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
+{
+   struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
+ phy_clk);
+
+   if (enable)
+   hdmiphy_enable(hdata);
+   else
+   hdmiphy_disable(hdata);
+}
+
 static int hdmi_resources_init(struct hdmi_context *hdata)
 {
struct device *dev = hdata->dev;
@@ -1710,6 +1735,10 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
if (pipe < 0)
return pipe;

+   hdata->phy_clk.enable = hdmiphy_clk_enable;
+
+   exynos_drm_crtc_from_pipe(drm_dev, pipe)->pipe_clk = >phy_clk;
+
encoder->possible_crtcs = 1 << pipe;

DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-- 
1.9.1

[PATCH 2/6] drm/exynos: add support for pipeline clock to the framework

[Andrzej Hajda]

Components belonging to the same pipeline often requires
synchronized clocks. Such clocks are sometimes provided
by external clock controller, but they can be also provided by
pipeline components. In latter case there should be a way
to access them from another component belonging to the same pipeline.
This is the case of:
- DECON,FIMD -> HDMI and HDMI-PHY clock,
- FIMD -> DP and DP clock in FIMD.
The latter case has been solved by clock_enable callback
in exynos_drm_crtc_ops. This solutin will not work with
HDMI path as in this case clock is provided by encoder.

This patch provides more generic solution allowing to register
pipeline clock during initialization in exynos_drm_crtc structure.
This way the clock will be easily accessible from both components.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_drv.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index fcea940..6ee0b20 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -154,6 +154,10 @@ struct exynos_drm_crtc_ops {
void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
 };

+struct exynos_drm_clk {
+   void (*enable)(struct exynos_drm_clk *clk, bool enable);
+};
+
 /*
  * Exynos specific crtc structure.
  *
@@ -182,8 +186,16 @@ struct exynos_drm_crtc {
atomic_tpending_update;
const struct exynos_drm_crtc_ops*ops;
void*ctx;
+   struct exynos_drm_clk   *pipe_clk;
 };

+static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc,
+ bool enable)
+{
+   if (crtc->pipe_clk)
+   crtc->pipe_clk->enable(crtc->pipe_clk, enable);
+}
+
 struct exynos_drm_g2d_private {
struct device   *dev;
struct list_headinuse_cmdlist;
-- 
1.9.1

[PATCH 1/6] drm/exynos: add helper to get crtc from pipe

[Andrzej Hajda]

The helper abstracts out conversion from pipeline
to crtc. Currently it is used in two places, but
there will be more uses in next patches.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 10 --
 drivers/gpu/drm/exynos/exynos_drm_drv.h  |  8 
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e36579c..50dd33d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -157,9 +157,8 @@ err_crtc:

 int exynos_drm_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe)
 {
-   struct exynos_drm_private *private = dev->dev_private;
-   struct exynos_drm_crtc *exynos_crtc =
-   to_exynos_crtc(private->crtc[pipe]);
+   struct exynos_drm_crtc *exynos_crtc = exynos_drm_crtc_from_pipe(dev,
+   pipe);

if (exynos_crtc->ops->enable_vblank)
return exynos_crtc->ops->enable_vblank(exynos_crtc);
@@ -169,9 +168,8 @@ int exynos_drm_crtc_enable_vblank(struct drm_device *dev, 
unsigned int pipe)

 void exynos_drm_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe)
 {
-   struct exynos_drm_private *private = dev->dev_private;
-   struct exynos_drm_crtc *exynos_crtc =
-   to_exynos_crtc(private->crtc[pipe]);
+   struct exynos_drm_crtc *exynos_crtc = exynos_drm_crtc_from_pipe(dev,
+   pipe);

if (exynos_crtc->ops->disable_vblank)
exynos_crtc->ops->disable_vblank(exynos_crtc);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 3f170ce..fcea940 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -232,6 +232,14 @@ struct exynos_drm_private {
wait_queue_head_t   wait;
 };

+static inline struct exynos_drm_crtc *
+exynos_drm_crtc_from_pipe(struct drm_device *dev, int pipe)
+{
+   struct exynos_drm_private *private = dev->dev_private;
+
+   return to_exynos_crtc(private->crtc[pipe]);
+}
+
 static inline struct device *to_dma_dev(struct drm_device *dev)
 {
struct exynos_drm_private *priv = dev->dev_private;
-- 
1.9.1

[PATCH 0/6] drm/exynos: add pipeline clock support

[Andrzej Hajda]

Hi Inki,

In case of some pipielines there is need to set clock in one component
by driver of another component, for example:
1. Decon and Mixer driver must enable HDMI-PHY clock before configuration.
2. DP driver must enable DP clock provided by FIMD.

This set of patches provide more generic solution for such problem
than currently present clock_enable callback. More details in particular
patches. The patchset is based on recently sent patchset with HDMI/DECON
path fixes[1].

[1]: http://permalink.gmane.org/gmane.comp.video.dri.devel/149714

Regards
Andrzej


Andrzej Hajda (6):
  drm/exynos: add helper to get crtc from pipe
  drm/exynos: add support for pipeline clock to the framework
  drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock
  drm/exynos/decon5433: enable HDMI-PHY before configuring DECON
  drm/exynos/mixer: enable HDMI-PHY before configuring MIXER
  drm/exynos: convert clock_enable crtc callback to pipeline clock

 drivers/gpu/drm/exynos/exynos5433_drm_decon.c |  4 ++
 drivers/gpu/drm/exynos/exynos_dp_core.c   |  8 +---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c  | 10 ++--
 drivers/gpu/drm/exynos/exynos_drm_drv.h   | 25 --
 drivers/gpu/drm/exynos/exynos_drm_fimd.c  | 27 ++-
 drivers/gpu/drm/exynos/exynos_hdmi.c  | 67 +++
 drivers/gpu/drm/exynos/exynos_mixer.c |  4 ++
 7 files changed, 95 insertions(+), 50 deletions(-)

-- 
1.9.1

[PATCH 7/7] drm/exynos/decon5433: do not protect window in plane disable

[Andrzej Hajda]

decon_atomic_begin and decon_atomic_flush protects all windows already.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 120efd8..c8c921c 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -329,12 +329,7 @@ static void decon_disable_plane(struct exynos_drm_crtc 
*crtc,
if (test_bit(BIT_SUSPENDED, >flags))
return;

-   decon_shadow_protect_win(ctx, win, true);
-
-   /* window disable */
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
-
-   decon_shadow_protect_win(ctx, win, false);
 }

 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
-- 
1.9.1

[PATCH 6/7] drm/exynos/decon5433: reset decon on start

[Andrzej Hajda]

Resetting IP at starting ensures that DECON will be in known state
regardless of changes by bootloader.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 7fec656..120efd8 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -400,6 +400,8 @@ static void decon_enable(struct exynos_drm_crtc *crtc)

set_bit(BIT_CLKS_ENABLED, >flags);

+   decon_swreset(ctx);
+
/* if vblank was enabled status, enable it again. */
if (test_and_clear_bit(BIT_IRQS_ENABLED, >flags))
decon_enable_vblank(ctx->crtc);
-- 
1.9.1

[PATCH 5/7] drm/exynos/decon5433: fix DECON standalone update

[Andrzej Hajda]

DECON should be updated after un-protecting windows and after changing
output parameters, otherwise image is not displayed in case of HDMI path.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index ab9154e..7fec656 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -191,6 +191,8 @@ static void decon_commit(struct exynos_drm_crtc *crtc)

/* enable output and display signal */
decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
+
+   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 }

 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
@@ -316,9 +318,6 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,

/* window enable */
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
-
-   /* standalone update */
-   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 }

 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
@@ -336,9 +335,6 @@ static void decon_disable_plane(struct exynos_drm_crtc 
*crtc,
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);

decon_shadow_protect_win(ctx, win, false);
-
-   /* standalone update */
-   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 }

 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
@@ -352,6 +348,9 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
for (i = ctx->first_win; i < WINDOWS_NR; i++)
decon_shadow_protect_win(ctx, i, false);

+   /* standalone update */
+   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
+
if (ctx->out_type == IFTYPE_I80)
set_bit(BIT_WIN_UPDATED, >flags);
 }
@@ -463,8 +462,10 @@ static void decon_clear_channels(struct exynos_drm_crtc 
*crtc)
decon_shadow_protect_win(ctx, win, true);
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
decon_shadow_protect_win(ctx, win, false);
-   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
}
+
+   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
+
/* TODO: wait for possible vsync */
msleep(50);

-- 
1.9.1

[PATCH 4/7] drm/exynos/hdmi: remove registry dump

[Andrzej Hajda]

HDMI registry dump unnecessary spoils console and is not very helpful.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 263 ---
 1 file changed, 263 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 6faa104..49a5902 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -716,268 +716,6 @@ static int hdmiphy_reg_write_buf(struct hdmi_context 
*hdata,
}
 }

-static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
-{
-#define DUMPREG(reg_id) \
-   DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
-   readl(hdata->regs + reg_id))
-   DRM_DEBUG_KMS("%s:  CONTROL REGISTERS \n", prefix);
-   DUMPREG(HDMI_INTC_FLAG);
-   DUMPREG(HDMI_INTC_CON);
-   DUMPREG(HDMI_HPD_STATUS);
-   DUMPREG(HDMI_V13_PHY_RSTOUT);
-   DUMPREG(HDMI_V13_PHY_VPLL);
-   DUMPREG(HDMI_V13_PHY_CMU);
-   DUMPREG(HDMI_V13_CORE_RSTOUT);
-
-   DRM_DEBUG_KMS("%s:  CORE REGISTERS \n", prefix);
-   DUMPREG(HDMI_CON_0);
-   DUMPREG(HDMI_CON_1);
-   DUMPREG(HDMI_CON_2);
-   DUMPREG(HDMI_SYS_STATUS);
-   DUMPREG(HDMI_V13_PHY_STATUS);
-   DUMPREG(HDMI_STATUS_EN);
-   DUMPREG(HDMI_HPD);
-   DUMPREG(HDMI_MODE_SEL);
-   DUMPREG(HDMI_V13_HPD_GEN);
-   DUMPREG(HDMI_V13_DC_CONTROL);
-   DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
-
-   DRM_DEBUG_KMS("%s:  CORE SYNC REGISTERS \n", prefix);
-   DUMPREG(HDMI_H_BLANK_0);
-   DUMPREG(HDMI_H_BLANK_1);
-   DUMPREG(HDMI_V13_V_BLANK_0);
-   DUMPREG(HDMI_V13_V_BLANK_1);
-   DUMPREG(HDMI_V13_V_BLANK_2);
-   DUMPREG(HDMI_V13_H_V_LINE_0);
-   DUMPREG(HDMI_V13_H_V_LINE_1);
-   DUMPREG(HDMI_V13_H_V_LINE_2);
-   DUMPREG(HDMI_VSYNC_POL);
-   DUMPREG(HDMI_INT_PRO_MODE);
-   DUMPREG(HDMI_V13_V_BLANK_F_0);
-   DUMPREG(HDMI_V13_V_BLANK_F_1);
-   DUMPREG(HDMI_V13_V_BLANK_F_2);
-   DUMPREG(HDMI_V13_H_SYNC_GEN_0);
-   DUMPREG(HDMI_V13_H_SYNC_GEN_1);
-   DUMPREG(HDMI_V13_H_SYNC_GEN_2);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
-   DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
-
-   DRM_DEBUG_KMS("%s:  TG REGISTERS \n", prefix);
-   DUMPREG(HDMI_TG_CMD);
-   DUMPREG(HDMI_TG_H_FSZ_L);
-   DUMPREG(HDMI_TG_H_FSZ_H);
-   DUMPREG(HDMI_TG_HACT_ST_L);
-   DUMPREG(HDMI_TG_HACT_ST_H);
-   DUMPREG(HDMI_TG_HACT_SZ_L);
-   DUMPREG(HDMI_TG_HACT_SZ_H);
-   DUMPREG(HDMI_TG_V_FSZ_L);
-   DUMPREG(HDMI_TG_V_FSZ_H);
-   DUMPREG(HDMI_TG_VSYNC_L);
-   DUMPREG(HDMI_TG_VSYNC_H);
-   DUMPREG(HDMI_TG_VSYNC2_L);
-   DUMPREG(HDMI_TG_VSYNC2_H);
-   DUMPREG(HDMI_TG_VACT_ST_L);
-   DUMPREG(HDMI_TG_VACT_ST_H);
-   DUMPREG(HDMI_TG_VACT_SZ_L);
-   DUMPREG(HDMI_TG_VACT_SZ_H);
-   DUMPREG(HDMI_TG_FIELD_CHG_L);
-   DUMPREG(HDMI_TG_FIELD_CHG_H);
-   DUMPREG(HDMI_TG_VACT_ST2_L);
-   DUMPREG(HDMI_TG_VACT_ST2_H);
-   DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
-   DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
-   DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
-   DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
-   DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
-   DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
-   DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
-   DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
-#undef DUMPREG
-}
-
-static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
-{
-   int i;
-
-#define DUMPREG(reg_id) \
-   DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
-   readl(hdata->regs + reg_id))
-
-   DRM_DEBUG_KMS("%s:  CONTROL REGISTERS \n", prefix);
-   DUMPREG(HDMI_INTC_CON);
-   DUMPREG(HDMI_INTC_FLAG);
-   DUMPREG(HDMI_HPD_STATUS);
-   DUMPREG(HDMI_INTC_CON_1);
-   DUMPREG(HDMI_INTC_FLAG_1);
-   DUMPREG(HDMI_PHY_STATUS_0);
-   DUMPREG(HDMI_PHY_STATUS_PLL);
-   DUMPREG(HDMI_PHY_CON_0);
-   DUMPREG(HDMI_V14_PHY_RSTOUT);
-   DUMPREG(HDMI_PHY_VPLL);
-   DUMPREG(HDMI_PHY_CMU);
-   DUMPREG(HDMI_CORE_RSTOUT);
-
-   DRM_DEBUG_KMS("%s:  CORE REGISTERS \n", prefix);
-   DUMPREG(HDMI_CON_0);
-   DUMPREG(HDMI_CON_1);
-   DUMPREG(HDMI_CON_2);
-   DUMPREG(HDMI_SYS_STATUS);
-   DUMPREG(HDMI_PHY_STATUS_0);
-   DUMPREG(HDMI_STATUS_EN);
-   DUMPREG(HDMI_HPD);
-   DUMPREG(HDMI_MODE_SEL);
-   DUMPREG(HDMI_ENC_EN);
-   DUMPREG(HDMI_DC_CONTROL);
-   DUMPREG(HDMI_VIDEO_PATTERN_GEN);
-
-   DRM_DEBUG_KMS("%s:  CORE SYNC REGISTERS \n", prefix);
-   DUMPREG(HDMI_H_BLANK_0);
-   DUMPREG(HDMI_H_BLANK_1);
-   DUMPREG(HDMI_V2_BLANK_0);
-   

[PATCH 3/7] drm/exynos/hdmi: add core reset code

[Andrzej Hajda]

To ensure HDMI-PHY reprogramming will not affect
HDMI the latter should be reset.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 16951f3..6faa104 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1662,6 +1662,10 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)

 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
 {
+   hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1);
+   usleep_range(1, 12000);
+   hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1);
+   usleep_range(1, 12000);
hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
usleep_range(1, 12000);
hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
-- 
1.9.1

[PATCH 2/7] drm/exynos/hdmi: add PHY power off signal handling

[Andrzej Hajda]

HDMI-PHY power off bit defaults to 0 in older HDMI versions.
In case of Exynos5433 it defaults to 1. To make code
consistent across all versions this bit is always unset/set in
power on/off sequences.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5c7dbfc..16951f3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1757,6 +1757,8 @@ static void hdmi_enable(struct drm_encoder *encoder)

hdmi_set_refclk(hdata, true);

+   hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
+
hdmi_conf_apply(hdata);

hdata->powered = true;
@@ -1789,6 +1791,8 @@ static void hdmi_disable(struct drm_encoder *encoder)

cancel_delayed_work(>hotplug_work);

+   hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
+
hdmi_set_refclk(hdata, false);

regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
-- 
1.9.1

[PATCH 1/7] drm/exynos/hdmi: fix PHY configuration sequence

[Andrzej Hajda]

Proper PHY configuration should be as follow:
1. set HDMI clock parents to OSCCLK.
2. reconfigure PHY.
3. set HDMI clock parents to PHY.
4. wait for PLL stabilization.

The patch fixes it and consolidates the code.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 839ad70..5c7dbfc 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1657,15 +1657,11 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)
else
hdmi_v14_mode_apply(hdata);

-   hdmiphy_wait_for_pll(hdata);
-   hdmi_clk_set_parents(hdata, true);
hdmi_start(hdata, true);
 }

 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
 {
-   hdmi_clk_set_parents(hdata, false);
-
hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
usleep_range(1, 12000);
hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
@@ -1683,29 +1679,33 @@ static void hdmiphy_enable_mode_set(struct hdmi_context 
*hdata, bool enable)
 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
 {
int ret;
-   int i;
+   const u8 *phy_conf;

-   i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
-   if (i < 0) {
+   ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
+   if (ret < 0) {
DRM_ERROR("failed to find hdmiphy conf\n");
return;
}
+   phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
+
+   hdmi_clk_set_parents(hdata, false);
+
+   hdmiphy_conf_reset(hdata);

hdmiphy_enable_mode_set(hdata, true);
-   ret = hdmiphy_reg_write_buf(hdata, 0,
-   hdata->drv_data->phy_confs.data[i].conf, 32);
+   ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
if (ret) {
DRM_ERROR("failed to configure hdmiphy\n");
return;
}
hdmiphy_enable_mode_set(hdata, false);
-
+   hdmi_clk_set_parents(hdata, true);
usleep_range(1, 12000);
+   hdmiphy_wait_for_pll(hdata);
 }

 static void hdmi_conf_apply(struct hdmi_context *hdata)
 {
-   hdmiphy_conf_reset(hdata);
hdmiphy_conf_apply(hdata);
hdmi_start(hdata, false);
hdmi_conf_init(hdata);
-- 
1.9.1

[PATCH 0/7] drm/exynos: HDMI and DECON fixes and enhancements

[Andrzej Hajda]

Hi Inki,

This set of patches provides set of different fixes and enhancements
for DECON -> HDMI path. It is based on:
- my HDMI patches which are not yet merged[1], could you look at them
  by the way, they were posted about 5 months ago :)
- IOMMU patches by Marek (for some mysterious reason HDMI path on 5433
  works only with IOMMU enabled),
- latest exynos-drm-next patches.

[1]: http://permalink.gmane.org/gmane.comp.video.dri.devel/140109

Regards
Andrzej


Andrzej Hajda (7):
  drm/exynos/hdmi: fix PHY configuration sequence
  drm/exynos/hdmi: add PHY power off signal handling
  drm/exynos/hdmi: add core reset code
  drm/exynos/hdmi: remove registry dump
  drm/exynos/decon5433: fix DECON standalone update
  drm/exynos/decon5433: reset decon on start
  drm/exynos/decon5433: do not protect window in plane disable

 drivers/gpu/drm/exynos/exynos5433_drm_decon.c |  22 +-
 drivers/gpu/drm/exynos/exynos_hdmi.c  | 293 ++
 2 files changed, 29 insertions(+), 286 deletions(-)

-- 
1.9.1

[Bug 94671] [radeonsi] Blue-ish textures in Shadow of Mordor

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94671

--- Comment #5 from Nicolai H�hnle  ---
Thank you for the report.

I suspect some of the BGR <-> RGB changes for shader image bitcasts are
responsible. Could one of you please provide an apitrace that shows the
problem? That would be very helpful.

-- 
You are receiving this mail because:
You are the assignee for the bug.
-- next part --
An HTML attachment was scrubbed...
URL: 
<https://lists.freedesktop.org/archives/dri-devel/attachments/20160323/32c7a5f3/attachment-0001.html>

[PATCH v2 13/18] mm/compaction: support non-lru movable page migration

[Joonsoo Kim]

On Tue, Mar 22, 2016 at 11:55:45PM +0900, Minchan Kim wrote:
> On Tue, Mar 22, 2016 at 02:50:37PM +0900, Joonsoo Kim wrote:
> > On Mon, Mar 21, 2016 at 03:31:02PM +0900, Minchan Kim wrote:
> > > We have allowed migration for only LRU pages until now and it was
> > > enough to make high-order pages. But recently, embedded system(e.g.,
> > > webOS, android) uses lots of non-movable pages(e.g., zram, GPU memory)
> > > so we have seen several reports about troubles of small high-order
> > > allocation. For fixing the problem, there were several efforts
> > > (e,g,. enhance compaction algorithm, SLUB fallback to 0-order page,
> > > reserved memory, vmalloc and so on) but if there are lots of
> > > non-movable pages in system, their solutions are void in the long run.
> > > 
> > > So, this patch is to support facility to change non-movable pages
> > > with movable. For the feature, this patch introduces functions related
> > > to migration to address_space_operations as well as some page flags.
> > > 
> > > Basically, this patch supports two page-flags and two functions related
> > > to page migration. The flag and page->mapping stability are protected
> > > by PG_lock.
> > > 
> > >   PG_movable
> > >   PG_isolated
> > > 
> > >   bool (*isolate_page) (struct page *, isolate_mode_t);
> > >   void (*putback_page) (struct page *);
> > > 
> > > Duty of subsystem want to make their pages as migratable are
> > > as follows:
> > > 
> > > 1. It should register address_space to page->mapping then mark
> > > the page as PG_movable via __SetPageMovable.
> > > 
> > > 2. It should mark the page as PG_isolated via SetPageIsolated
> > > if isolation is sucessful and return true.
> > > 
> > > 3. If migration is successful, it should clear PG_isolated and
> > > PG_movable of the page for free preparation then release the
> > > reference of the page to free.
> > > 
> > > 4. If migration fails, putback function of subsystem should
> > > clear PG_isolated via ClearPageIsolated.
> > 
> > I think that this feature needs a separate document to describe
> > requirement of each step in more detail. For example, #1 can be
> > possible without holding a lock? I'm not sure because you lock
> > the page when implementing zsmalloc page migration in 15th patch.
> 
> Yes, we needs PG_lock because install page->mapping and PG_movable
> should be atomic and PG_lock protects it.
> 
> Better interface might be
> 
> void __SetPageMovable(struct page *page, sruct address_space *mapping);
> 
> > 
> > #3 also need more explanation. Before release, we need to
> > unregister address_space. I guess that it needs to be done
> > in migratepage() but there is no explanation.
> 
> Okay, we can unregister address_space in __ClearPageMovable.
> I will change it.
> 
> > 
> > > 
> > > Cc: Vlastimil Babka 
> > > Cc: Mel Gorman 
> > > Cc: Hugh Dickins 
> > > Cc: dri-devel at lists.freedesktop.org
> > > Cc: virtualization at lists.linux-foundation.org
> > > Signed-off-by: Gioh Kim 
> > > Signed-off-by: Minchan Kim 
> > > ---
> > >  Documentation/filesystems/Locking  |   4 +
> > >  Documentation/filesystems/vfs.txt  |   5 ++
> > >  fs/proc/page.c |   3 +
> > >  include/linux/fs.h |   2 +
> > >  include/linux/migrate.h|   2 +
> > >  include/linux/page-flags.h |  29 
> > >  include/uapi/linux/kernel-page-flags.h |   1 +
> > >  mm/compaction.c|  14 +++-
> > >  mm/migrate.c   | 132 
> > > +
> > >  9 files changed, 177 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/Documentation/filesystems/Locking 
> > > b/Documentation/filesystems/Locking
> > > index 619af9bfdcb3..0bb79560abb3 100644
> > > --- a/Documentation/filesystems/Locking
> > > +++ b/Documentation/filesystems/Locking
> > > @@ -195,7 +195,9 @@ unlocks and drops the reference.
> > >   int (*releasepage) (struct page *, int);
> > >   void (*freepage)(struct page *);
> > >   int (*direct_IO)(struct kiocb *, struct iov_iter *iter, loff_t offset);
> > > + bool (*isolate_page) (struct page *, isolate_mode_t);
> > >   int (*migratepage)(struct address_space *, struct page *, struct page 
> > > *);
> > > + void (*putback_page) (struct page *);
> > >   int (*launder_page)(struct page *);
> > >   int (*is_partially_uptodate)(struct page *, unsigned long, unsigned 
> > > long);
> > >   int (*error_remove_page)(struct address_space *, struct page *);
> > > @@ -219,7 +221,9 @@ invalidatepage:   yes
> > >  releasepage: yes
> > >  freepage:yes
> > >  direct_IO:
> > > +isolate_page:yes
> > >  migratepage: yes (both)
> > > +putback_page:yes
> > >  launder_page:yes
> > >  is_partially_uptodate:   yes
> > >  error_remove_page:   yes
> > > diff --git a/Documentation/filesystems/vfs.txt 
> > > b/Documentation/filesystems/vfs.txt
> > > index b02a7d598258..4c1b6c3b4bc8 

[Bug 115141] radeon kernel module hangs suspend

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=115141

Alex Deucher  changed:

   What|Removed |Added

 CC||alexdeucher at gmail.com

--- Comment #3 from Alex Deucher  ---
Can you bisect?

-- 
You are receiving this mail because:
You are watching the assignee of the bug.

[PATCH 52/52] drm/amd/dal: Enable Polaris support in the Kconfig

[Alex Deucher]

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/dal/Kconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
index b108756..939d5c6 100644
--- a/drivers/gpu/drm/amd/dal/Kconfig
+++ b/drivers/gpu/drm/amd/dal/Kconfig
@@ -46,6 +46,16 @@ config DRM_AMD_DAL_DCE11_0
 CZ family
 for display engine

+config DRM_AMD_DAL_DCE11_2
+bool "Polaris11 family"
+depends on DRM_AMD_DAL
+   select DRM_AMD_DAL_DCE11_0
+help
+ Choose this option
+if you want to have
+BF family
+for display engine.
+
 config DEBUG_KERNEL_DAL
 bool "Enable kgdb break in DAL"
 depends on DRM_AMD_DAL
-- 
2.5.0

[PATCH 51/52] drm/amdgpu: add dal support for polaris

[Alex Deucher]

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/vi.c| 79 ++
 2 files changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5857f71..926b933 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1404,9 +1404,11 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device 
*adev)
case CHIP_HAWAII:
return amdgpu_dal != 0;
 #endif
-#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#if defined(CONFIG_DRM_AMD_DAL) && (defined(CONFIG_DRM_AMD_DAL_DCE11_0) || 
defined(CONFIG_DRM_AMD_DAL_DCE11_2))
case CHIP_CARRIZO:
case CHIP_STONEY:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS10:
return amdgpu_dal != 0;
 #endif
 #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 6192ec7..119a52b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1144,6 +1144,75 @@ static const struct amdgpu_ip_block_version 
cz_ip_blocks_dal[] =
 #endif
 };

+static const struct amdgpu_ip_block_version polaris11_ip_blocks_dal[] =
+{
+   /* ORDER MATTERS! */
+   {
+   .type = AMD_IP_BLOCK_TYPE_COMMON,
+   .major = 2,
+   .minor = 0,
+   .rev = 0,
+   .funcs = _common_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_GMC,
+   .major = 8,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _v8_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_IH,
+   .major = 3,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _ih_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_SMC,
+   .major = 7,
+   .minor = 2,
+   .rev = 0,
+   /* To Do */
+   .funcs = _pp_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_DCE,
+   .major = 11,
+   .minor = 2,
+   .rev = 0,
+   .funcs = _dm_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_GFX,
+   .major = 8,
+   .minor = 0,
+   .rev = 0,
+   .funcs = _v8_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_SDMA,
+   .major = 3,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _v3_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_UVD,
+   .major = 6,
+   .minor = 3,
+   .rev = 0,
+   .funcs = _v6_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_VCE,
+   .major = 3,
+   .minor = 4,
+   .rev = 0,
+   .funcs = _v3_0_ip_funcs,
+   },
+};
+
 static const struct amdgpu_ip_block_version tonga_ip_blocks_dal[] =
 {
/* ORDER MATTERS! */
@@ -1318,8 +1387,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
+#if defined(CONFIG_DRM_AMD_DAL)
+   if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
+   adev->ip_blocks = polaris11_ip_blocks_dal;
+   adev->num_ip_blocks = 
ARRAY_SIZE(polaris11_ip_blocks_dal);
+   } else {
+   adev->ip_blocks = polaris11_ip_blocks;
+   adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
+   }
+#else
adev->ip_blocks = polaris11_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
+#endif
break;
case CHIP_CARRIZO:
case CHIP_STONEY:
-- 
2.5.0

[PATCH 50/52] drm/amd/dal/dm: add polaris support

[Alex Deucher]

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index 1564485..5b3edb8 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -1007,6 +1007,10 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device 
*adev)
case CHIP_FIJI:
case CHIP_CARRIZO:
case CHIP_STONEY:
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS10:
+#endif
if (dce110_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
return -1;
@@ -1308,6 +1312,22 @@ static int dm_early_init(void *handle)
if (adev->mode_info.funcs == NULL)
adev->mode_info.funcs = _dce_v11_0_display_funcs;
break;
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
+   case CHIP_POLARIS11:
+   adev->mode_info.num_crtc = 5;
+   adev->mode_info.num_hpd = 5;
+   adev->mode_info.num_dig = 5;
+   if (adev->mode_info.funcs == NULL)
+   adev->mode_info.funcs = _dce_v11_0_display_funcs;
+   break;
+   case CHIP_POLARIS10:
+   adev->mode_info.num_crtc = 6;
+   adev->mode_info.num_hpd = 6;
+   adev->mode_info.num_dig = 6;
+   if (adev->mode_info.funcs == NULL)
+   adev->mode_info.funcs = _dce_v11_0_display_funcs;
+   break;
+#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;
-- 
2.5.0

[PATCH 49/52] drm/amd/dal: add core support for Polaris family (v2)

[Alex Deucher]

This adds core dc support for polaris 10 and 11.

v2: add missing files

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/dal/dc/Makefile|4 +
 drivers/gpu/drm/amd/dal/dc/adapter/Makefile|4 +
 .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   12 +
 .../adapter/dce112/hw_ctx_adapter_service_dce112.c |  302 +++
 .../adapter/dce112/hw_ctx_adapter_service_dce112.h |   39 +
 .../gpu/drm/amd/dal/dc/asic_capability/Makefile|9 +
 .../amd/dal/dc/asic_capability/asic_capability.c   |   15 +-
 .../dc/asic_capability/polaris10_asic_capability.c |  146 ++
 .../dc/asic_capability/polaris10_asic_capability.h |   36 +
 drivers/gpu/drm/amd/dal/dc/audio/Makefile  |8 +
 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c  |9 +
 .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c |  451 +
 .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h |   40 +
 .../amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c  | 1923 
 .../amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h  |   47 +
 drivers/gpu/drm/amd/dal/dc/bios/Makefile   |9 +
 .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |6 +
 .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |4 +
 drivers/gpu/drm/amd/dal/dc/bios/command_table.c|   78 +-
 .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |6 +
 .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |3 +
 .../dal/dc/bios/dce112/bios_parser_helper_dce112.c |  480 +
 .../dal/dc/bios/dce112/bios_parser_helper_dce112.h |   34 +
 .../dc/bios/dce112/command_table_helper_dce112.c   |  417 +
 .../dc/bios/dce112/command_table_helper_dce112.h   |   34 +
 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |  206 +++
 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |7 +
 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c  |   22 +-
 .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c|1 +
 .../amd/dal/dc/dce110/dce110_timing_generator.c|2 +-
 drivers/gpu/drm/amd/dal/dc/dce112/Makefile |   10 +
 .../drm/amd/dal/dc/dce112/dce112_clock_source.c|  266 +++
 .../drm/amd/dal/dc/dce112/dce112_clock_source.h|   52 +
 .../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c  |  883 +
 .../gpu/drm/amd/dal/dc/dce112/dce112_compressor.h  |   84 +
 .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c|  178 ++
 .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.h|   36 +
 .../drm/amd/dal/dc/dce112/dce112_link_encoder.c|  116 ++
 .../drm/amd/dal/dc/dce112/dce112_link_encoder.h|   41 +
 .../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c   |  455 +
 .../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h   |   38 +
 .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c| 1404 ++
 .../gpu/drm/amd/dal/dc/dce112/dce112_resource.h|   42 +
 drivers/gpu/drm/amd/dal/dc/dm_services_types.h |5 +
 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c   |3 +
 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c |3 +
 drivers/gpu/drm/amd/dal/dc/gpu/Makefile|8 +
 .../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c |   89 +
 .../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h |   33 +
 .../amd/dal/dc/gpu/dce112/display_clock_dce112.c   |  964 ++
 .../amd/dal/dc/gpu/dce112/display_clock_dce112.h   |   54 +
 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c |5 +-
 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |4 +-
 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c   |4 +
 drivers/gpu/drm/amd/dal/include/dal_asic_id.h  |   14 +
 drivers/gpu/drm/amd/dal/include/dal_types.h|3 +
 .../drm/amd/dal/include/display_clock_interface.h  |6 +
 57 files changed, 9146 insertions(+), 8 deletions(-)
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.c
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.h
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
 create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
 create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.c
 create mode 100644 
drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.h
 create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/Makefile
 create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
 create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.h
 create mode 100644 

[PATCH 48/52] drm/amdgpu: add polaris10/11 smc fw declaration

[Alex Deucher]

From: Flora Cui 

Signed-off-by: Flora Cui 
Reviewed-by: Rex Zhu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 6efd459..6192ec7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -79,6 +79,11 @@
 #include "amdgpu_dm.h"
 #include "amdgpu_powerplay.h"

+MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
+
 /*
  * Indirect registers accessor
  */
-- 
2.5.0

[PATCH 47/52] drm/amd/powerplay: Disable Spread Spectrum on DPM 0 on baffin as SPLL Shut Down feature is enabled.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Acked-by: Flora Cui 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 6 ++
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index b77d7aa..715bc3d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -1248,6 +1248,9 @@ static int polaris10_populate_all_graphic_levels(struct 
pp_hwmgr *hwmgr)
if (i > 1)
levels[i].DeepSleepDivId = 0;
}
+   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_SPLLShutdownSupport))
+   data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;

data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
data->smc_state_table.GraphicsDpmLevelCount =
@@ -2602,6 +2605,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr 
*hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);

+   if (hwmgr->chip_id == CHIP_POLARIS11)
+   phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_SPLLShutdownSupport);
return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 040d3f7..56f712c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -211,6 +211,7 @@ enum phm_platform_caps {
PHM_PlatformCaps_ClockStretcher,
PHM_PlatformCaps_TablelessHardwareInterface,
PHM_PlatformCaps_EnableDriverEVV,
+   PHM_PlatformCaps_SPLLShutdownSupport,
PHM_PlatformCaps_Max
 };

-- 
2.5.0

[PATCH 46/52] drm/amd/powerplay: enable set lowest mclk clock on baffin.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 446ed72..b77d7aa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3136,7 +3136,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr 
*hwmgr)
(1 << level));

}
-/* uvd is enabled, can't set mclk low right now
+
if (!data->mclk_dpm_key_disabled) {
if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr,
@@ -3146,7 +3146,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr 
*hwmgr)
(1 << level));
}
}
-*/
+
if (!data->pcie_dpm_key_disabled) {
if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr,
-- 
2.5.0

[PATCH 45/52] drm/amd/powrplay: fix issue that get wrong enable flag.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index d08f739..446ed72 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3960,14 +3960,11 @@ static int polaris10_trim_single_dpm_states(struct 
pp_hwmgr *hwmgr,
uint32_t low_limit, uint32_t high_limit)
 {
uint32_t i;
-   struct polaris10_hwmgr *data = (struct polaris10_hwmgr 
*)(hwmgr->backend);

for (i = 0; i < dpm_table->count; i++) {
if ((dpm_table->dpm_levels[i].value < low_limit)
|| (dpm_table->dpm_levels[i].value > high_limit))
dpm_table->dpm_levels[i].enabled = false;
-   else if (((1 << i) & data->disable_dpm_mask) == 0)
-   dpm_table->dpm_levels[i].enabled = false;
else
dpm_table->dpm_levels[i].enabled = true;
}
-- 
2.5.0

[PATCH 44/52] drm/amd/powerplay: fix mclk in high clock for baffin

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index ac40599..d08f739 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -1377,13 +1377,14 @@ static int polaris10_populate_all_memory_levels(struct 
pp_hwmgr *hwmgr)
result = polaris10_populate_single_memory_level(hwmgr,
dpm_table->mclk_table.dpm_levels[i].value,
[i]);
+   if (i == dpm_table->mclk_table.count - 1) {
+   levels[i].DisplayWatermark = 
PPSMC_DISPLAY_WATERMARK_HIGH;
+   levels[i].EnabledForActivity = 1;
+   }
if (result)
return result;
}

-   /* Only enable level 0 for now. */
-   levels[0].EnabledForActivity = 1;
-
/* in order to prevent MC activity from stutter mode to push DPM up.
 * the UVD change complements this by putting the MCLK in
 * a higher state by default such that we are not effected by
@@ -1396,9 +1397,6 @@ static int polaris10_populate_all_memory_levels(struct 
pp_hwmgr *hwmgr)
(uint8_t)dpm_table->mclk_table.count;
data->dpm_level_enable_mask.mclk_dpm_enable_mask =

phm_get_dpm_level_enable_mask_value(_table->mclk_table);
-   /* set highest level watermark to high */
-   levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
-   PPSMC_DISPLAY_WATERMARK_HIGH;

/* level count will send to smc once at init smc table and never change 
*/
result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t 
*)levels,
-- 
2.5.0

[PATCH 43/52] drm/amd/powerplay: print gpu loading and uvd/vce power gate enablement for polaris10/11.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 5080d67..ac40599 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3646,7 +3646,9 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr 
*hwmgr,
 static void
 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file 
*m)
 {
-   uint32_t sclk, mclk;
+   uint32_t sclk, mclk, activity_percent;
+   uint32_t offset;
+   struct polaris10_hwmgr *data = (struct polaris10_hwmgr 
*)(hwmgr->backend);

smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);

@@ -3657,6 +3659,17 @@ polaris10_print_current_perforce_level(struct pp_hwmgr 
*hwmgr, struct seq_file *
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
mclk / 100, sclk / 100);
+
+   offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, 
AverageGraphicsActivity);
+   activity_percent = cgs_read_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset);
+   activity_percent += 0x80;
+   activity_percent >>= 8;
+
+   seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : 
activity_percent);
+
+   seq_printf(m, "uvd%sabled\n", data->uvd_power_gated ? "dis" : "en");
+
+   seq_printf(m, "vce%sabled\n", data->vce_power_gated ? "dis" : "en");
 }

 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr 
*hwmgr, const void *input)
-- 
2.5.0

[PATCH 41/52] drm/amdgpu: add ELM/BAF pci ids

[Alex Deucher]

From: Flora Cui 

Signed-off-by: Flora Cui 
Reviewed-by: Alex Deucher 
Reviewed-by: Jammy Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 5bff00e..4c4eb4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -281,6 +281,16 @@ static struct pci_device_id pciidlist[] = {
{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
/* stoney */
{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
+   /* Baffin */
+   {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
+   /* Ellesmere */
+   {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
+   {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},

{0, 0, 0}
 };
-- 
2.5.0

[PATCH 40/52] drm/amdgpu: update the core VI support for ELM/BAF

[Alex Deucher]

From: Flora Cui 

Signed-off-by: Flora Cui 
Reviewed-by: Jammy Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +
 drivers/gpu/drm/amd/amdgpu/vi.c| 87 ++
 2 files changed, 89 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e0c2e99..79a3e32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1152,6 +1152,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
case CHIP_TOPAZ:
case CHIP_TONGA:
case CHIP_FIJI:
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
case CHIP_CARRIZO:
case CHIP_STONEY:
if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == 
CHIP_STONEY)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 328707c..f554c7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -277,6 +277,8 @@ static void vi_init_golden_registers(struct amdgpu_device 
*adev)
 stoney_mgcg_cgcg_init,
 (const 
u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
break;
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
default:
break;
}
@@ -538,6 +540,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 
se_num,
break;
case CHIP_FIJI:
case CHIP_TONGA:
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
case CHIP_CARRIZO:
case CHIP_STONEY:
asic_register_table = cz_allowed_read_registers;
@@ -908,6 +912,74 @@ static const struct amdgpu_ip_block_version 
fiji_ip_blocks[] =
},
 };

+static const struct amdgpu_ip_block_version baffin_ip_blocks[] =
+{
+   /* ORDER MATTERS! */
+   {
+   .type = AMD_IP_BLOCK_TYPE_COMMON,
+   .major = 2,
+   .minor = 0,
+   .rev = 0,
+   .funcs = _common_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_GMC,
+   .major = 8,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _v8_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_IH,
+   .major = 3,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _ih_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_SMC,
+   .major = 7,
+   .minor = 2,
+   .rev = 0,
+   .funcs = _pp_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_DCE,
+   .major = 11,
+   .minor = 2,
+   .rev = 0,
+   .funcs = _v11_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_GFX,
+   .major = 8,
+   .minor = 0,
+   .rev = 0,
+   .funcs = _v8_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_SDMA,
+   .major = 3,
+   .minor = 1,
+   .rev = 0,
+   .funcs = _v3_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_UVD,
+   .major = 6,
+   .minor = 3,
+   .rev = 0,
+   .funcs = _v6_0_ip_funcs,
+   },
+   {
+   .type = AMD_IP_BLOCK_TYPE_VCE,
+   .major = 3,
+   .minor = 4,
+   .rev = 0,
+   .funcs = _v3_0_ip_funcs,
+   },
+};
+
 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
 {
/* ORDER MATTERS! */
@@ -1239,6 +1311,11 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
 #endif
break;
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
+   adev->ip_blocks = baffin_ip_blocks;
+   adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks);
+   break;
case CHIP_CARRIZO:
case CHIP_STONEY:
 #if defined(CONFIG_DRM_AMD_DAL)
@@ -1335,6 +1412,16 @@ static int vi_common_early_init(void *handle)
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14;
break;
+   case CHIP_BAFFIN:
+   adev->cg_flags = 0;
+   adev->pg_flags = 0;
+   adev->external_rev_id = adev->rev_id + 0x5A;
+   break;
+   case CHIP_ELLESMERE:
+   adev->cg_flags = 0;
+   adev->pg_flags = 0;
+   adev->external_rev_id = adev->rev_id + 0x50;
+   break;
case CHIP_CARRIZO:
case CHIP_STONEY:
adev->cg_flags = 0;
-- 
2.5.0

[PATCH 39/52] drm/amdgpu: ungate SMC clockgating first before suspend

[Alex Deucher]

From: Flora Cui 

46c34bcb6a15dd85329a39a5e72c62108626acdc put all block’s clockgating
support in SMC. The sequence in suspend routine should be adjusted
accordingly, otherwise it causes asic hang.

Signed-off-by: Flora Cui 
Reviewed-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5ed7baf..e0c2e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1340,14 +1340,23 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
 {
int i, r;

+   /* ungate SMC block first */
+   r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
+AMD_CG_STATE_UNGATE);
+   if (r) {
+   DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
+   }
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_block_status[i].valid)
continue;
/* ungate blocks so that suspend can properly shut them down */
-   r = adev->ip_blocks[i].funcs->set_clockgating_state((void 
*)adev,
-   
AMD_CG_STATE_UNGATE);
-   if (r) {
-   DRM_ERROR("set_clockgating_state(ungate) %d failed 
%d\n", i, r);
+   if (i != AMD_IP_BLOCK_TYPE_SMC) {
+   r = 
adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
+   
AMD_CG_STATE_UNGATE);
+   if (r) {
+   DRM_ERROR("set_clockgating_state(ungate) %d 
failed %d\n", i, r);
+   }
}
/* XXX handle errors */
r = adev->ip_blocks[i].funcs->suspend(adev);
-- 
2.5.0

[PATCH 38/52] drm/amd/amdgpu: add power gating init for Baffin

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index faa0682..9618014 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1091,9 +1091,14 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device 
*adev,
PACKET3_SET_CONTEXT_REG_START);
switch (adev->asic_type) {
case CHIP_TONGA:
+   case CHIP_ELLESMERE:
buffer[count++] = cpu_to_le32(0x1612);
buffer[count++] = cpu_to_le32(0x002A);
break;
+   case CHIP_BAFFIN:
+   buffer[count++] = cpu_to_le32(0x1612);
+   buffer[count++] = cpu_to_le32(0x);
+   break;
case CHIP_FIJI:
buffer[count++] = cpu_to_le32(0x3a00161a);
buffer[count++] = cpu_to_le32(0x002e);
@@ -3652,6 +3657,37 @@ static void gfx_v8_0_enable_save_restore_machine(struct 
amdgpu_device *adev)
WREG32(mmRLC_SRM_CNTL, data);
 }

+static void baffin_init_power_gating(struct amdgpu_device *adev)
+{
+   uint32_t data;
+
+   if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
+   AMD_PG_SUPPORT_GFX_SMG |
+   AMD_PG_SUPPORT_GFX_DMG)) {
+   data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
+   data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
+   data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
+   WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
+
+   data = 0;
+   data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
+   data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
+   data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
+   data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
+   WREG32(mmRLC_PG_DELAY, data);
+
+   data = RREG32(mmRLC_PG_DELAY_2);
+   data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
+   data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
+   WREG32(mmRLC_PG_DELAY_2, data);
+
+   data = RREG32(mmRLC_AUTO_PG_CTRL);
+   data &= 
~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
+   data |= (0x55f0 << 
RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
+   WREG32(mmRLC_AUTO_PG_CTRL, data);
+   }
+}
+
 static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
 {
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -3663,6 +3699,9 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
gfx_v8_0_init_csb(adev);
gfx_v8_0_init_save_restore_list(adev);
gfx_v8_0_enable_save_restore_machine(adev);
+
+   if (adev->asic_type == CHIP_BAFFIN)
+   baffin_init_power_gating(adev);
}
 }

-- 
2.5.0

[PATCH 37/52] drm/amd/amdgpu: add power gating initialization support for GFX8.0

[Alex Deucher]

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  14 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 353 +-
 2 files changed, 364 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64dcf58..e46dbc0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1054,6 +1054,20 @@ struct amdgpu_rlc {
uint64_tcp_table_gpu_addr;
volatile uint32_t   *cp_table_ptr;
u32 cp_table_size;
+
+   /* for firmware data */
+   u32 save_and_restore_offset;
+   u32 clear_state_descriptor_offset;
+   u32 avail_scratch_ram_locations;
+   u32 reg_restore_list_size;
+   u32 reg_list_format_start;
+   u32 reg_list_format_separate_start;
+   u32 starting_offsets_start;
+   u32 reg_list_format_size_bytes;
+   u32 reg_list_size_bytes;
+
+   u32 *register_list_format;
+   u32 *register_restore;
 };

 struct amdgpu_mec {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index f9d17e7..faa0682 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -86,6 +86,8 @@ enum {
BPM_REG_FGCG_MAX
 };

+#define RLC_FormatDirectRegListLength14
+
 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
@@ -632,6 +634,7 @@ static const u32 stoney_mgcg_cgcg_init[] =
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
+static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);

 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
@@ -837,6 +840,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device 
*adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
const struct gfx_firmware_header_v1_0 *cp_hdr;
+   const struct rlc_firmware_header_v2_0 *rlc_hdr;
+   unsigned int *tmp = NULL, i;

DRM_DEBUG("\n");

@@ -904,9 +909,49 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device 
*adev)
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
-   cp_hdr = (const struct gfx_firmware_header_v1_0 
*)adev->gfx.rlc_fw->data;
-   adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
-   adev->gfx.rlc_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);
+   rlc_hdr = (const struct rlc_firmware_header_v2_0 
*)adev->gfx.rlc_fw->data;
+   adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+   adev->gfx.rlc_feature_version = 
le32_to_cpu(rlc_hdr->ucode_feature_version);
+
+   adev->gfx.rlc.save_and_restore_offset =
+   le32_to_cpu(rlc_hdr->save_and_restore_offset);
+   adev->gfx.rlc.clear_state_descriptor_offset =
+   le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
+   adev->gfx.rlc.avail_scratch_ram_locations =
+   le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
+   adev->gfx.rlc.reg_restore_list_size =
+   le32_to_cpu(rlc_hdr->reg_restore_list_size);
+   adev->gfx.rlc.reg_list_format_start =
+   le32_to_cpu(rlc_hdr->reg_list_format_start);
+   adev->gfx.rlc.reg_list_format_separate_start =
+   le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
+   adev->gfx.rlc.starting_offsets_start =
+   le32_to_cpu(rlc_hdr->starting_offsets_start);
+   adev->gfx.rlc.reg_list_format_size_bytes =
+   le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
+   adev->gfx.rlc.reg_list_size_bytes =
+   le32_to_cpu(rlc_hdr->reg_list_size_bytes);
+
+   adev->gfx.rlc.register_list_format =
+   kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
+   adev->gfx.rlc.reg_list_size_bytes, 
GFP_KERNEL);
+
+   if (!adev->gfx.rlc.register_list_format) {
+   err = -ENOMEM;
+   goto out;
+   }
+
+   tmp = (unsigned int *)((uint64_t)rlc_hdr +
+   
le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
+   for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
+   adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
+
+   adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
+
+   tmp = (unsigned int *)((uint64_t)rlc_hdr +
+   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
+   for (i = 0 ; i < 

[PATCH 36/52] drm/amd/powerplay: add default clockgating handling

[Alex Deucher]

From: Flora Cui 

This is to workaround regression introduced in
46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a
final fix.

Signed-off-by: Flora Cui 
Reviewed-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 94b7809..32a6a6f 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -188,10 +188,12 @@ static int pp_set_clockgating_state(void *handle,

hwmgr = ((struct pp_instance *)handle)->hwmgr;

-   if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-   hwmgr->hwmgr_func->update_clock_gatings == NULL)
+   if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
return -EINVAL;

+   if (hwmgr->hwmgr_func->update_clock_gatings == NULL)
+   return 0;
+
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
-- 
2.5.0

[PATCH 35/52] drm/amd/amdgpu: add medium grain powergating support for Baffin

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 95 +++
 1 file changed, 95 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6f31fc7..f9d17e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4392,6 +4392,9 @@ static int gfx_v8_0_hw_fini(void *handle)
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_cp_compute_fini(adev);

+   amdgpu_set_powergating_state(adev,
+   AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
+
return 0;
 }

@@ -4819,12 +4822,104 @@ static int gfx_v8_0_late_init(void *handle)
if (r)
return r;

+   amdgpu_set_powergating_state(adev,
+   AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
+
return 0;
 }

+static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device 
*adev,
+   bool enable)
+{
+   uint32_t data, temp;
+
+   /* Send msg to SMU via Powerplay */
+   amdgpu_set_powergating_state(adev,
+   AMD_IP_BLOCK_TYPE_SMC,
+   enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
+
+   if (enable) {
+   /* Enable static MGPG */
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   } else {
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   }
+}
+
+static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device 
*adev,
+   bool enable)
+{
+   uint32_t data, temp;
+
+   if (enable) {
+   /* Enable dynamic MGPG */
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   } else {
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   }
+}
+
+static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
+   bool enable)
+{
+   uint32_t data, temp;
+
+   if (enable) {
+   /* Enable quick PG */
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data |= 0x10;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   } else {
+   temp = data = RREG32(mmRLC_PG_CNTL);
+   data &= ~0x10;
+
+   if (temp != data)
+   WREG32(mmRLC_PG_CNTL, data);
+   }
+}
+
 static int gfx_v8_0_set_powergating_state(void *handle,
  enum amd_powergating_state state)
 {
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+   return 0;
+
+   switch (adev->asic_type) {
+   case CHIP_BAFFIN:
+   if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)
+   baffin_enable_gfx_static_mg_power_gating(adev,
+   state == AMD_PG_STATE_GATE ? true : 
false);
+   else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)
+   baffin_enable_gfx_dynamic_mg_power_gating(adev,
+   state == AMD_PG_STATE_GATE ? true : 
false);
+   else
+   baffin_enable_gfx_quick_mg_power_gating(adev,
+   state == AMD_PG_STATE_GATE ? true : 
false);
+   break;
+   default:
+   break;
+   }
+
return 0;
 }

-- 
2.5.0

[PATCH 34/52] drm/amd/powerplay: add GFX per cu powergating for Baffin

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
---
 .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 28 ++
 .../powerplay/hwmgr/ellesmere_clockpowergating.h   |  1 +
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  5 
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
index a94f6a8..93db824 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
@@ -398,3 +398,31 @@ int ellesmere_phm_update_clock_gatings(struct pp_hwmgr 
*hwmgr,

return 0;
 }
+
+/* This function is for Baffin only for now,
+ * Powerplay will only control the static per CU Power Gating.
+ * Dynamic per CU Power Gating will be done in gfx.
+ */
+int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool 
enable)
+{
+   struct cgs_system_info sys_info = {0};
+   uint32_t active_cus;
+   int result;
+
+   sys_info.size = sizeof(struct cgs_system_info);
+   sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
+
+   result = cgs_query_system_info(hwmgr->device, _info);
+
+   if (result)
+   return -EINVAL;
+   else
+   active_cus = sys_info.value;
+
+   if (enable)
+   return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
+   else
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_GFX_CU_PG_DISABLE);
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
index a90577e..b403e11 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
@@ -35,5 +35,6 @@ int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool 
bgate);
 int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
 int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id);
+int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool 
enable);

 #endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
index c87d5ef..152d77d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
@@ -4687,6 +4687,11 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs 
= {
.register_internal_thermal_interrupt = 
ellesmere_register_internal_thermal_interrupt,
.check_smc_update_required_for_display_configuration = 
ellesmere_check_smc_update_required_for_display_configuration,
.check_states_equal = ellesmere_check_states_equal,
+   .get_pp_table = ellesmere_get_pp_table,
+   .set_pp_table = ellesmere_set_pp_table,
+   .force_clock_level = ellesmere_force_clock_level,
+   .print_clock_levels = ellesmere_print_clock_levels,
+   .enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating,
 };

 int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
2.5.0

[PATCH 33/52] drm/amd/powerplay: add GFX per cu powergating support through SMU/powerplay

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 ++-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |  1 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9c742e0..94b7809 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -267,7 +267,20 @@ static int pp_set_clockgating_state(void *handle,
 static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
 {
-   return 0;
+   struct pp_hwmgr  *hwmgr;
+
+   if (handle == NULL)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
+   hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL)
+   return -EINVAL;
+
+   /* Enable/disable GFX per cu powergating through SMU */
+   return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
+   state == AMD_PG_STATE_GATE ? true : false);
 }

 static int pp_suspend(void *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 928f5a7..d098afb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -337,6 +337,7 @@ struct pp_hwmgr_func {
int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t 
size);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type 
type, int level);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type 
type, char *buf);
+   int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 };

 struct pp_table_func {
-- 
2.5.0

[PATCH 32/52] drm/amd/amdgpu: add query GFX cu info in CGS query system info

[Alex Deucher]

Needed for per CU powergating.

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 5 +
 drivers/gpu/drm/amd/include/cgs_common.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index bd4571c..08c1e6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -791,6 +791,7 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
struct cgs_system_info *sys_info)
 {
CGS_FUNC_ADEV;
+   struct amdgpu_cu_info cu_info;

if (NULL == sys_info)
return -ENODEV;
@@ -814,6 +815,10 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
case CGS_SYSTEM_INFO_PG_FLAGS:
sys_info->value = adev->pg_flags;
break;
+   case CGS_SYSTEM_INFO_GFX_CU_INFO:
+   amdgpu_asic_get_cu_info(adev, _info);
+   sys_info->value = cu_info.number;
+   break;
default:
return -ENODEV;
}
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
b/drivers/gpu/drm/amd/include/cgs_common.h
index 2cd427a..58c0cef 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -112,6 +112,7 @@ enum cgs_system_info_id {
CGS_SYSTEM_INFO_PCIE_MLW,
CGS_SYSTEM_INFO_CG_FLAGS,
CGS_SYSTEM_INFO_PG_FLAGS,
+   CGS_SYSTEM_INFO_GFX_CU_INFO,
CGS_SYSTEM_INFO_ID_MAXIMUM,
 };

-- 
2.5.0

[PATCH 31/52] drm/amd/powerplay: add GFX/SYS clockgating support for ELM/BAF

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
---
 .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 247 +
 .../powerplay/hwmgr/ellesmere_clockpowergating.h   |   2 +
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |   1 +
 3 files changed, 250 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
index 0dee0df..a94f6a8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
@@ -151,3 +151,250 @@ int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, 
bool bgate)
return 0;
 }

+int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
+   const uint32_t *msg_id)
+{
+   PPSMC_Msg msg;
+   uint32_t value;
+
+   switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
+   case PP_GROUP_GFX:
+   switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
+   case PP_BLOCK_GFX_CG:
+   if (PP_STATE_SUPPORT_CG & *msg_id) {
+   msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) 
?
+   
PPSMC_MSG_EnableClockGatingFeature :
+   
PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_CGCG_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+   if (PP_STATE_SUPPORT_LS & *msg_id) {
+   msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
+   ? PPSMC_MSG_EnableClockGatingFeature
+   : PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_CGLS_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+   break;
+
+   case PP_BLOCK_GFX_3D:
+   if (PP_STATE_SUPPORT_CG & *msg_id) {
+   msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) 
?
+   
PPSMC_MSG_EnableClockGatingFeature :
+   
PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_3DCG_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+
+   if  (PP_STATE_SUPPORT_LS & *msg_id) {
+   msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
+   
PPSMC_MSG_EnableClockGatingFeature :
+   
PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_3DLS_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+   break;
+
+   case PP_BLOCK_GFX_RLC:
+   if (PP_STATE_SUPPORT_LS & *msg_id) {
+   msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
+   
PPSMC_MSG_EnableClockGatingFeature :
+   
PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_RLC_LS_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+   break;
+
+   case PP_BLOCK_GFX_CP:
+   if (PP_STATE_SUPPORT_LS & *msg_id) {
+   msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
+   
PPSMC_MSG_EnableClockGatingFeature :
+   
PPSMC_MSG_DisableClockGatingFeature;
+   value = CG_GFX_CP_LS_MASK;
+
+   if (smum_send_msg_to_smc_with_parameter(
+   hwmgr->smumgr, msg, value))
+   return -1;
+   }
+ 

[PATCH 30/52] drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay

[Alex Deucher]

From: Eric Huang 

Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 81 +++
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  3 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9d22900..9c742e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -180,6 +180,87 @@ static void pp_print_status(void *handle)
 static int pp_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
 {
+   struct pp_hwmgr  *hwmgr;
+   uint32_t msg_id, pp_state;
+
+   if (handle == NULL)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
+   hwmgr->hwmgr_func->update_clock_gatings == NULL)
+   return -EINVAL;
+
+   if (state == AMD_CG_STATE_UNGATE)
+   pp_state = 0;
+   else
+   pp_state = PP_STATE_CG | PP_STATE_LS;
+
+   /* Enable/disable GFX blocks clock gating through SMU */
+   msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+   PP_BLOCK_GFX_CG,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+   PP_BLOCK_GFX_3D,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+   PP_BLOCK_GFX_RLC,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+   PP_BLOCK_GFX_CP,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
+   PP_BLOCK_GFX_MG,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+
+   /* Enable/disable System blocks clock gating through SMU */
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_BIF,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_BIF,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_MC,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_ROM,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_DRM,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_HDP,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+   msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+   PP_BLOCK_SYS_SDMA,
+   PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
+   pp_state);
+   hwmgr->hwmgr_func->update_clock_gatings(hwmgr, _id);
+
return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h 
b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 7255f7d..e5f2ee7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -289,6 +289,9 @@ struct pp_states_info {

 #define PP_BLOCK_GFX_CG 0x01
 #define PP_BLOCK_GFX_MG 0x02
+#define PP_BLOCK_GFX_3D 0x04
+#define PP_BLOCK_GFX_RLC0x08
+#define PP_BLOCK_GFX_CP 0x10
 #define PP_BLOCK_SYS_BIF0x01
 #define PP_BLOCK_SYS_MC 0x02
 #define PP_BLOCK_SYS_ROM0x04
-- 
2.5.0

[PATCH 29/52] drm/amd/powerplay: update baffin & ellesmere smc_sk firmware.

[Alex Deucher]

From: yanyang1 

sync the code form catalyst CL:#1230866.

Signed-off-by: yanyang1 
Rviewed-by: Alex Deucher 
---
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  51 ++-
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |   1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h|   2 +
 .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h|  14 +++
 .../amd/powerplay/hwmgr/tonga_processpptables.c| 101 +++--
 .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c|  28 --
 .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h|   2 +
 7 files changed, 162 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
index 62f0f36..043aefa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
@@ -222,6 +222,22 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr 
*hwmgr)
" found a available voltage in VDDC DPM Table \n");
 }

+/**
+* Enable voltage control
+*
+* @parampHwMgr  the address of the powerplay hardware manager.
+* @return   always PP_Result_OK
+*/
+int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
+{
+   PP_ASSERT_WITH_CODE(
+   (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, 
PPSMC_MSG_Voltage_Cntl_Enable) == 0),
+   "Failed to enable voltage DPM during DPM Start Function!",
+   return 1;
+   );
+
+   return 0;
+}

 /**
 * Checks if we want to support voltage control
@@ -586,6 +602,10 @@ static int ellesmere_setup_default_pcie_table(struct 
pp_hwmgr *hwmgr)

pcie_table->entries[i].lane_width));
}
data->dpm_table.pcie_speed_table.count = max_entry - 1;
+
+   /* Setup BIF_SCLK levels */
+   for (i = 0; i < max_entry; i++)
+   data->bif_sclk_table[i] = 
pcie_table->entries[i].pcie_sclk;
} else {
/* Hardcode Pcie Table */
phm_setup_pcie_table_entry(>dpm_table.pcie_speed_table, 0,
@@ -938,9 +958,13 @@ static int ellesmere_calculate_sclk_params(struct pp_hwmgr 
*hwmgr,
sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
sclk_setting->PllRange = dividers.ucSclkPllRange;
+   sclk_setting->Sclk_slew_rate = 0x400;
+   sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
+   sclk_setting->Pcc_down_slew_rate = 0x;
sclk_setting->SSc_En = dividers.ucSscEnable;
sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
+   sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
return result;
}

@@ -1174,8 +1198,12 @@ static int 
ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
+   CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
+   CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
+   CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
+   CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
return 0;
 }

@@ -1458,8 +1486,12 @@ static int ellesmere_populate_smc_acpi_level(struct 
pp_hwmgr *hwmgr,
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
+   
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
+   
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
+   
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
+   
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);

if (!data->mclk_dpm_key_disabled) {
/* Get MinVoltage and Frequency from DPM0, already converted to 
SMC_UL */
@@ -1966,6 +1998,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr 
*hwmgr)
const struct ellesmere_ulv_parm *ulv = &(data->ulv);
uint8_t i;
struct pp_atomctrl_gpio_pin_assignment gpio_pin;
+   pp_atomctrl_clock_dividers_vi dividers;

[PATCH 28/52] drm/amd/powerplay: Add smc_sk firmware to baffin & ellesmere.

[Alex Deucher]

From: yanyang1 

update relational h files.

Signed-off-by: yanyang1 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h|  1 +
 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h| 10 --
 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h |  1 +
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h 
b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
index c24a81e..880152c 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
@@ -44,6 +44,7 @@
 #define UCODE_ID_IH_REG_RESTORE   11
 #define UCODE_ID_VBIOS12
 #define UCODE_ID_MISC_METADATA13
+#define UCODE_ID_SMU_SK  14
 #define UCODE_ID_RLC_SCRATCH  32
 #define UCODE_ID_RLC_SRM_ARAM 33
 #define UCODE_ID_RLC_SRM_DRAM 34
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
index 733fa37..f816262 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
@@ -71,8 +71,12 @@ struct SMU_SclkSetting {
uint16_tPcc_fcw_int;
uint8_t PllRange;
uint8_t SSc_En;
+   uint16_tSclk_slew_rate;
+   uint16_tPcc_up_slew_rate;
+   uint16_tPcc_down_slew_rate;
uint16_tFcw1_int;
uint16_tFcw1_frac;
+   uint16_tSclk_ss_slew_rate;
 };
 typedef struct SMU_SclkSetting SMU_SclkSetting;

@@ -120,7 +124,8 @@ struct SMU74_Discrete_Ulv {
uint16_tVddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
-   uint32_tReserved;
+   uint16_tBifSclkDfs;
+   uint16_tReserved;
 };

 typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
@@ -155,7 +160,8 @@ struct SMU74_Discrete_LinkLevel {
uint8_t SPC;
uint32_tDownThreshold;
uint32_tUpThreshold;
-   uint32_tReserved;
+   uint16_tBifSclkDfs;
+   uint16_tReserved;
 };

 typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
index c24a81e..880152c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
@@ -44,6 +44,7 @@
 #define UCODE_ID_IH_REG_RESTORE   11
 #define UCODE_ID_VBIOS12
 #define UCODE_ID_MISC_METADATA13
+#define UCODE_ID_SMU_SK  14
 #define UCODE_ID_RLC_SCRATCH  32
 #define UCODE_ID_RLC_SRM_ARAM 33
 #define UCODE_ID_RLC_SRM_DRAM 34
-- 
2.5.0

[PATCH 27/52] drm/amd/amdgpu: Add smc_sk firmware in baffin & ellesmere.

[Alex Deucher]

From: yanyang1 

add CGS_UCODE_ID_SMU_SK.

Signed-off-by: yanyang1 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 12 +---
 drivers/gpu/drm/amd/include/cgs_common.h |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 477beae..bd4571c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -702,7 +702,7 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
 {
CGS_FUNC_ADEV;

-   if (CGS_UCODE_ID_SMU != type) {
+   if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
uint64_t gpu_addr;
uint32_t data_size;
const struct gfx_firmware_header_v1_0 *header;
@@ -743,10 +743,16 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
strcpy(fw_name, "amdgpu/fiji_smc.bin");
break;
case CHIP_BAFFIN:
-   strcpy(fw_name, "amdgpu/baffin_smc.bin");
+   if (type == CGS_UCODE_ID_SMU)
+   strcpy(fw_name, "amdgpu/baffin_smc.bin");
+   else if (type == CGS_UCODE_ID_SMU_SK)
+   strcpy(fw_name, "amdgpu/baffin_smc_sk.bin");
break;
case CHIP_ELLESMERE:
-   strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
+   if (type == CGS_UCODE_ID_SMU)
+   strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
+   else if (type == CGS_UCODE_ID_SMU_SK)
+   strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin");
break;
default:
DRM_ERROR("SMC firmware not supported\n");
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
b/drivers/gpu/drm/amd/include/cgs_common.h
index aec38fc..2cd427a 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -92,6 +92,7 @@ enum cgs_voltage_planes {
  */
 enum cgs_ucode_id {
CGS_UCODE_ID_SMU = 0,
+   CGS_UCODE_ID_SMU_SK,
CGS_UCODE_ID_SDMA0,
CGS_UCODE_ID_SDMA1,
CGS_UCODE_ID_CP_CE,
-- 
2.5.0

[PATCH 26/52] drm/amd/powerplay: add UVD DPM and powergating support for elm/baf

[Alex Deucher]

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |   3 +-
 .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 153 +
 .../powerplay/hwmgr/ellesmere_clockpowergating.h   |  37 +
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  91 +++-
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |   4 +
 5 files changed, 282 insertions(+), 6 deletions(-)
 create mode 100644 
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
 create mode 100644 
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index f13327d..5437ec0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -9,7 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
fiji_clockpowergating.o fiji_thermal.o \
-  ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o
+  ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \
+  ellesmere_clockpowergating.o

 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
new file mode 100644
index 000..0dee0df
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "ellesmere_clockpowergating.h"
+
+int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cf_want_uvd_power_gating(hwmgr))
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_UVDPowerOFF);
+   return 0;
+}
+
+int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cf_want_uvd_power_gating(hwmgr)) {
+   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDynamicPowerGating)) {
+   return 
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_UVDPowerON, 1);
+   } else {
+   return 
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_UVDPowerON, 0);
+   }
+   }
+
+   return 0;
+}
+
+int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cf_want_vce_power_gating(hwmgr))
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_VCEPowerOFF);
+   return 0;
+}
+
+int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cf_want_vce_power_gating(hwmgr))
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_VCEPowerON);
+   return 0;
+}
+
+int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_SamuPowerGating))
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_SAMPowerOFF);
+   return 0;
+}
+
+int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
+{
+   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_SamuPowerGating))
+   return smum_send_msg_to_smc(hwmgr->smumgr,
+   PPSMC_MSG_SAMPowerON);
+   return 0;
+}
+
+int 

[PATCH 25/52] drm/amd/powerplay: add thermal control for elm/baf

[Alex Deucher]

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |   2 +-
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  39 +-
 .../drm/amd/powerplay/hwmgr/ellesmere_thermal.c| 711 +
 .../drm/amd/powerplay/hwmgr/ellesmere_thermal.h|  62 ++
 4 files changed, 801 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 2982d5c..f13327d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -9,7 +9,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
fiji_clockpowergating.o fiji_thermal.o \
-  ellesmere_hwmgr.o ellesmere_powertune.o
+  ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o

 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
index 10e8e87..3ef8d3c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
@@ -57,6 +57,8 @@
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"

+#include "ellesmere_thermal.h"
+
 #define MC_CG_ARB_FREQ_F0   0x0a
 #define MC_CG_ARB_FREQ_F1   0x0b
 #define MC_CG_ARB_FREQ_F2   0x0c
@@ -4198,8 +4200,14 @@ static int ellesmere_set_power_state_tasks(struct 
pp_hwmgr *hwmgr, const void *i

 static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t 
us_max_fan_pwm)
 {
+   hwmgr->thermal_controller.
+   advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;

+   if (phm_is_hw_access_blocked(hwmgr))
return 0;
+
+   return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
 }

 int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool 
has_display)
@@ -4290,9 +4298,16 @@ int ellesmere_display_configuration_changed_task(struct 
pp_hwmgr *hwmgr)
 * @paramusMaxFanRpm:  max operating fan RPM value.
 * @return   The response that came from the SMC.
 */
-static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t 
us_max_fan_pwm)
+static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t 
us_max_fan_rpm)
 {
-   return 0;
+   hwmgr->thermal_controller.
+   advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
+
+   if (phm_is_hw_access_blocked(hwmgr))
+   return 0;
+
+   return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }

 int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
@@ -4529,15 +4544,15 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs 
= {
.display_config_changed = ellesmere_display_configuration_changed_task,
.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
.set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output,
-   .get_temperature = NULL,
-   .stop_thermal_controller = NULL,
-   .get_fan_speed_info = NULL,
-   .get_fan_speed_percent = NULL,
-   .set_fan_speed_percent = NULL,
-   .reset_fan_speed_to_default = NULL,
-   .get_fan_speed_rpm = NULL,
-   .set_fan_speed_rpm = NULL,
-   .uninitialize_thermal_controller = NULL,
+   .get_temperature = ellesmere_thermal_get_temperature,
+   .stop_thermal_controller = ellesmere_thermal_stop_thermal_controller,
+   .get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info,
+   .get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent,
+   .set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent,
+   .reset_fan_speed_to_default = 
ellesmere_fan_ctrl_reset_fan_speed_to_default,
+   .get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm,
+   .set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm,
+   .uninitialize_thermal_controller = 
ellesmere_thermal_ctrl_uninitialize_thermal_controller,
.register_internal_thermal_interrupt = 
ellesmere_register_internal_thermal_interrupt,
.check_smc_update_required_for_display_configuration = 
ellesmere_check_smc_update_required_for_display_configuration,
.check_states_equal = ellesmere_check_states_equal,
@@ -4554,7 +4569,7 @@ int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data;
hwmgr->hwmgr_func = _hwmgr_funcs;
hwmgr->pptable_func = 

[PATCH 24/52] drm/amd/powerplay: enable powerplay for baffin.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 3cb6d6c..261748c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -101,6 +101,8 @@ static int amdgpu_pp_early_init(void *handle)
switch (adev->asic_type) {
case CHIP_TONGA:
case CHIP_FIJI:
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
break;
case CHIP_CARRIZO:
-- 
2.5.0

[PATCH 23/52] drm/amd/powerplay: init hwmgr for ELM/BAF

[Alex Deucher]

From: Rex Zhu 

Reviewed-by: Alex Deucher 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 5fb98aa..2c68199 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -34,6 +34,7 @@
 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);

 int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
 {
@@ -67,6 +68,10 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct 
pp_instance *handle)
case CHIP_FIJI:
fiji_hwmgr_init(hwmgr);
break;
+   case CHIP_BAFFIN:
+   case CHIP_ELLESMERE:
+   ellesemere_hwmgr_init(hwmgr);
+   break;
default:
return -EINVAL;
}
-- 
2.5.0

[PATCH 22/52] drm/amd/powerplay: enable dpm for baffin.

[Alex Deucher]

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |3 +-
 .../amd/powerplay/hwmgr/ellesmere_dyn_defaults.h   |   62 +
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  | 4560 
 .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |  349 ++
 .../drm/amd/powerplay/hwmgr/ellesmere_powertune.c  |  396 ++
 .../drm/amd/powerplay/hwmgr/ellesmere_powertune.h  |   70 +
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  111 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h   |   40 +-
 8 files changed, 5581 insertions(+), 10 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index b664e34..2982d5c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -8,7 +8,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
   tonga_processpptables.o ppatomctrl.o \
tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
-   fiji_clockpowergating.o fiji_thermal.o
+   fiji_clockpowergating.o fiji_thermal.o \
+  ellesmere_hwmgr.o ellesmere_powertune.o

 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
new file mode 100644
index 000..ba1187c
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef ELLESMERE_DYN_DEFAULTS_H
+#define ELLESMERE_DYN_DEFAULTS_H
+
+
+enum Ellesmeredpm_TrendDetection {
+   EllesmereAdpm_TrendDetection_AUTO,
+   EllesmereAdpm_TrendDetection_UP,
+   EllesmereAdpm_TrendDetection_DOWN
+};
+typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;
+
+/*  We need to fill in the default values */
+
+
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0  0x3FFFC102
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1  0x000400
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2  0xC00080
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3  0xC00200
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4  0xC01680
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5  0xC00033
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6  0xC00033
+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7  0x3FFFC000
+
+
+#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT0x200
+#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT0
+#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT0x00C8
+#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT0x200
+#define PPELLESMERE_REFERENCEDIVIDER_DFLT  4
+
+#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT 1687
+
+#define PPELLESMERE_CGULVPARAMETER_DFLT0x00040035
+#define PPELLESMERE_CGULVCONTROL_DFLT  0x7450
+#define PPELLESMERE_TARGETACTIVITY_DFLT 50
+#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT10
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
new file mode 100644
index 000..10e8e87
--- /dev/null
+++ 

[PATCH 21/52] drm/amd/powerplay: add smu support for ellesmere/baffin

[Alex Deucher]

From: rezhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Jammy Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|  11 +-
 drivers/gpu/drm/amd/powerplay/smumgr/Makefile  |   2 +-
 .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c| 969 +
 .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h|  66 ++
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c  |   5 +
 5 files changed, 1050 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 7a4b101..477beae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -681,9 +681,10 @@ static uint32_t fw_type_convert(void *cgs_device, uint32_t 
fw_type)
result = AMDGPU_UCODE_ID_CP_MEC1;
break;
case CGS_UCODE_ID_CP_MEC_JT2:
-   if (adev->asic_type == CHIP_TONGA)
+   if (adev->asic_type == CHIP_TONGA || adev->asic_type == 
CHIP_BAFFIN
+ || adev->asic_type == CHIP_ELLESMERE)
result = AMDGPU_UCODE_ID_CP_MEC2;
-   else if (adev->asic_type == CHIP_CARRIZO)
+   else
result = AMDGPU_UCODE_ID_CP_MEC1;
break;
case CGS_UCODE_ID_RLC_G:
@@ -741,6 +742,12 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
case CHIP_FIJI:
strcpy(fw_name, "amdgpu/fiji_smc.bin");
break;
+   case CHIP_BAFFIN:
+   strcpy(fw_name, "amdgpu/baffin_smc.bin");
+   break;
+   case CHIP_ELLESMERE:
+   strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
+   break;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
index 6c4ef13..4f751e5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the 'smu manager' sub-component of powerplay.
 # It provides the smu management services for the driver.

-SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o
+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o

 AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
new file mode 100644
index 000..f57ba12
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
@@ -0,0 +1,969 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "smumgr.h"
+#include "smu74.h"
+#include "smu_ucode_xfer_vi.h"
+#include "ellesmere_smumgr.h"
+#include "smu74_discrete.h"
+#include "smu/smu_7_1_3_d.h"
+#include "smu/smu_7_1_3_sh_mask.h"
+#include "gmc/gmc_8_1_d.h"
+#include "gmc/gmc_8_1_sh_mask.h"
+#include "oss/oss_3_0_d.h"
+#include "gca/gfx_8_0_d.h"
+#include "bif/bif_5_0_d.h"
+#include "bif/bif_5_0_sh_mask.h"
+#include "ellesmere_pwrvirus.h"
+#include "ppatomctrl.h"
+#include "pp_debug.h"
+#include "cgs_common.h"
+
+#define ELLESMERE_SMC_SIZE 0x2
+#define VOLTAGE_SCALE 4
+
+/* Microcode file is stored in this buffer */
+#define BUFFER_SIZE 8
+#define MAX_STRING_SIZE 15
+#define BUFFER_SIZETWO  131072  /* 128 *1024 */
+
+#define SMC_RAM_END 0x4
+
+SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
+   /*  Min  pcie   DeepSleep Activity  CgSpll  

[PATCH 20/52] drm/amd/powerplay: add header files for ellesmere smu manager.

[Alex Deucher]

From: rezhu 

Signed-off-by: Rex Zhu 
---
 .../gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h|   401 +
 .../gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h | 10088 +++
 drivers/gpu/drm/amd/powerplay/inc/smu74.h  |   774 ++
 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h |   780 ++
 4 files changed, 12043 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu74.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
new file mode 100644
index 000..18fe230
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef ELLESMERE_PP_SMC_H
+#define ELLESMERE_PP_SMC_H
+
+
+#pragma pack(push, 1)
+
+
+#define PPSMC_SWSTATE_FLAG_DC   0x01
+#define PPSMC_SWSTATE_FLAG_UVD  0x02
+#define PPSMC_SWSTATE_FLAG_VCE  0x04
+
+#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
+#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
+#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
+
+#define PPSMC_SYSTEMFLAG_GPIO_DC0x01
+#define PPSMC_SYSTEMFLAG_STEPVDDC   0x02
+#define PPSMC_SYSTEMFLAG_GDDR5  0x04
+
+#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP   0x08
+
+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT  0x10
+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG   0x20
+
+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK  0x07
+#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
+
+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
+
+
+#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
+#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
+#define PPSMC_DPM2FLAGS_OCP 0x04
+
+
+#define PPSMC_DISPLAY_WATERMARK_LOW 0
+#define PPSMC_DISPLAY_WATERMARK_HIGH1
+
+
+#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP0x01
+#define PPSMC_STATEFLAG_POWERBOOST 0x02
+#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
+#define PPSMC_STATEFLAG_POWERSHIFT 0x08
+#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
+#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
+#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
+
+
+#define FDO_MODE_HARDWARE 0
+#define FDO_MODE_PIECE_WISE_LINEAR 1
+
+enum FAN_CONTROL {
+   FAN_CONTROL_FUZZY,
+   FAN_CONTROL_TABLE
+};
+
+
+#define PPSMC_Result_OK ((uint16_t)0x01)
+#define PPSMC_Result_NoMore ((uint16_t)0x02)
+
+#define PPSMC_Result_NotNow ((uint16_t)0x03)
+#define PPSMC_Result_Failed ((uint16_t)0xFF)
+#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
+#define PPSMC_Result_UnknownVT  ((uint16_t)0xFD)
+
+typedef uint16_t PPSMC_Result;
+
+#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
+
+
+#define PPSMC_MSG_Halt  ((uint16_t)0x10)
+#define PPSMC_MSG_Resume((uint16_t)0x11)
+#define PPSMC_MSG_EnableDPMLevel((uint16_t)0x12)
+#define PPSMC_MSG_ZeroLevelsDisabled((uint16_t)0x13)
+#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
+#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
+#define PPSMC_MSG_EnableThermalInterrupt((uint16_t)0x16)
+#define PPSMC_MSG_RunningOnAC   ((uint16_t)0x17)
+#define PPSMC_MSG_LevelUp   ((uint16_t)0x18)
+#define PPSMC_MSG_LevelDown