[PATCH V3 5/5] dts/imx6q-b850v3: Use GE B850v3 LVDS/DP++ Bridge

2016-07-31 Thread Peter Senna Tschudin 
Configures the GE B850v3 LVDS/DP++ bridge on the dts file.

Cc: Javier Martinez Canillas 
Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Signed-off-by: Peter Senna Tschudin 
---
Unchanged from V2.

Changes from V1:
 - Replaced '_' by '-' in node names or compatible strings
 - Added missing @73 to b850v3-lvds-dp-bridge

 arch/arm/boot/dts/imx6q-b850v3.dts | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts 
b/arch/arm/boot/dts/imx6q-b850v3.dts
index 88a70de..10dfc3b 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -77,6 +77,13 @@
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
+
+   port at 4 {
+   reg = <4>;
+   lvds0_out: endpoint {
+   remote-endpoint = <_lvds_dp_bridge_in>;
+   };
+   };
};
 };

@@ -147,3 +154,26 @@
reg = <0x4a>;
};
 };
+
+_i2c2 {
+   status = "okay";
+   clock-frequency = <10>;
+
+   b850v3-lvds-dp-bridge at 73 {
+   compatible = "ge,b850v3-lvds-dp";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <0x73>;
+   interrupt-parent = <>;
+   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+   edid-reg = <0x72>;
+
+   port {
+   b850v3_lvds_dp_bridge_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+};
-- 
2.5.5

[PATCH V3 4/5] drm/bridge: Add driver for GE B850v3 LVDS/DP++ Bridge

2016-07-31 Thread Peter Senna Tschudin 
Add a driver that create a drm_bridge and a drm_connector for the LVDS
to DP++ display bridge of the GE B850v3.

There are two physical bridges on the video signal pipeline: a
STDP4028(LVDS to DP) and a STDP2690(DP to DP++).  The hardware and
firmware made it complicated for this binding to comprise two device
tree nodes, as the design goal is to configure both bridges based on
the LVDS signal, which leave the driver powerless to control the video
processing pipeline. The two bridges behaves as a single bridge, and
the driver is only needed for telling the host about EDID / HPD, and
for giving the host powers to ack interrupts. The video signal pipeline
is as follows:

  Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

Cc: Daniel Vetter 
Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
CC: David Airlie 
CC: Thierry Reding 
CC: Thierry Reding 
Signed-off-by: Peter Senna Tschudin 
---
 - Made it atomic to be applied on next-20160729 on top of Liu Ying changes
   that made imx-ldb atomic.

Changes from V1:
 - New commit message
 - Removed 3 empty entry points
 - Removed memory leak from ge_b850v3_lvds_dp_get_modes()
 - Added a lock for mode setting
 - Removed a few blank lines
 - Changed the order at Makefile and Kconfig

 MAINTAINERS|   8 +
 drivers/gpu/drm/bridge/Kconfig |  11 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c | 397 +
 4 files changed, 417 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c

diff --git a/MAINTAINERS b/MAINTAINERS
index aaf36c0..ec52e17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5139,6 +5139,14 @@ W:   https://linuxtv.org
 S: Maintained
 F: drivers/media/radio/radio-gemtek*

+GENERAL ELECTRIC B850V3 LVDS/DP++ BRIDGE
+M: Peter Senna Tschudin 
+M: Martin Donnelly 
+M: Martyn Welch 
+S: Maintained
+F: drivers/gpu/drm/bridge/ge_b850v3_dp2.c
+F: Documentation/devicetree/bindings/ge/b850v3_dp2_bridge.txt
+
 GENERIC GPIO I2C DRIVER
 M: Haavard Skinnemoen 
 S: Supported
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index b590e67..b4b70fb 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -32,6 +32,17 @@ config DRM_DW_HDMI_AHB_AUDIO
  Designware HDMI block.  This is used in conjunction with
  the i.MX6 HDMI driver.

+config DRM_GE_B850V3_LVDS_DP
+   tristate "GE B850v3 LVDS to DP++ display bridge"
+   depends on OF
+   select DRM_KMS_HELPER
+   select DRM_PANEL
+   ---help---
+  This is a driver for the display bridge of
+  GE B850v3 that convert dual channel LVDS
+  to DP++. This is used with the i.MX6 imx-ldb
+  driver.
+
 config DRM_NXP_PTN3460
tristate "NXP PTN3460 DP/LVDS bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index efdb07e..b9606f3 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,6 +3,7 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
+obj-$(CONFIG_DRM_GE_B850V3_LVDS_DP) += ge_b850v3_lvds_dp.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_SII902X) += sii902x.o
diff --git a/drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c 
b/drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c
new file mode 100644
index 000..eee8eac
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c
@@ -0,0 +1,397 @@
+/*
+ * Driver for GE B850v3 DP display bridge
+
+ * Copyright (c) 2016, Collabora Ltd.
+ * Copyright (c) 2016, General Electric Company
+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+
+ * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
+ * display bridge of the GE B850v3. There are two physical bridges on the video
+ * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). However
+ * the physical bridges are automatically configured by the input video signal,
+ * and the driver has no access to the video processing pipeline. The driver is
+ * only needed to read EDID from the STDP2690 and to handle HPD events from

[PATCH V3 3/5] Documentation/devicetree/bindings: b850v3_lvds_dp

2016-07-31 Thread Peter Senna Tschudin 
Devicetree bindings documentation for the GE B850v3 LVDS/DP++
display bridge.

Cc: Javier Martinez Canillas 
Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Signed-off-by: Peter Senna Tschudin 
---
Unchanged from V2.

Changes from V1:
 - Replaced '_' by '-' in node names or compatible strings
 - Added missing @73 to the example

 .../devicetree/bindings/ge/b850v3-lvds-dp.txt  | 37 ++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt

diff --git a/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt 
b/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
new file mode 100644
index 000..f05c3e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
@@ -0,0 +1,37 @@
+Driver for GE B850v3 LVDS/DP++ display bridge
+
+Required properties:
+  - compatible : should be "ge,b850v3-lvds-dp".
+  - reg : should contain the address used to ack the interrupts.
+  - interrupt-parent : phandle of the interrupt controller that services
+interrupts to the device
+  - interrupts : one interrupt should be described here, as in
+<0 IRQ_TYPE_LEVEL_HIGH>.
+  - edid-reg : should contain the address used to read edid information
+  - port : should describe the video signal connection between the host
+and the bridge.
+
+Example:
+
+_i2c2 {
+   status = "okay";
+   clock-frequency = <10>;
+
+   b850v3-lvds-dp-bridge at 73  {
+   compatible = "ge,b850v3-lvds-dp";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <0x73>;
+   interrupt-parent = <>;
+   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+   edid-reg = <0x72>;
+
+   port {
+   b850v3_dp_bridge_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+};
-- 
2.5.5

[PATCH V3 2/5] dts/imx6q-b850v3: Configure IPU assignment order

2016-07-31 Thread Peter Senna Tschudin 
As the IPU has combined limitations across multiple crtcs, and as that
can't be communicated to userspace at the moment, reorder the crtcs to
allow support to two Full-HD monitors by avoiding assigning two
monitors to a single IPU.

Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Signed-off-by: Peter Senna Tschudin 
---
Unchanged from V2.

Changes from V1:
 - New commit message

 arch/arm/boot/dts/imx6q-b850v3.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts 
b/arch/arm/boot/dts/imx6q-b850v3.dts
index 167f744..88a70de 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -51,6 +51,11 @@
chosen {
stdout-path = 
};
+
+   display-subsystem {
+   compatible = "fsl,imx-display-subsystem";
+   ports = <_di0>, <_di0>, <_di1>, <_di1>;
+   };
 };

  {
-- 
2.5.5

[PATCH V3 1/5] drm/imx-ldb: Add support to drm-bridge

2016-07-31 Thread Peter Senna Tschudin 
Add support to attach a drm_bridge to imx-ldb in addition to
existing support to attach a LVDS panel.

This patch does a simple code refactoring by moving code
from for_each_child_of_node iterator to a new function named
imx_ldb_panel_ddc(). This was necessary to allow the panel ddc
code to run only when the imx_ldb is not attached to a bridge.

Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Cc: David Airlie 
Cc: Thierry Reding 
Cc: Thierry Reding 
Signed-off-by: Peter Senna Tschudin 
---
Changes from V2:
 - Updated to be aplied on top of Liu Ying changes that made imx-ldb atomic.
 - Tested on next-20160729.

Changes from V1:
 - Reanmed ext_bridge to bridge
 - Removed empty entry point imx_ldb_encoder_enable()
 - Adapted the code to apply to the latest linux next: next-20160609

 drivers/gpu/drm/imx/imx-ldb.c | 111 ++
 1 file changed, 70 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 5d2831d..ebe9abd 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -57,7 +57,11 @@ struct imx_ldb_channel {
struct imx_ldb *ldb;
struct drm_connector connector;
struct drm_encoder encoder;
+
+   /* Defines what is connected to the ldb, only one at a time */
struct drm_panel *panel;
+   struct drm_bridge *bridge;
+
struct device_node *child;
struct i2c_adapter *ddc;
int chno;
@@ -469,19 +473,28 @@ static int imx_ldb_register(struct drm_device *drm,
drm_encoder_init(drm, encoder, _ldb_encoder_funcs,
 DRM_MODE_ENCODER_LVDS, NULL);

-   drm_connector_helper_add(_ldb_ch->connector,
-   _ldb_connector_helper_funcs);
-   drm_connector_init(drm, _ldb_ch->connector,
-  _ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
-
if (imx_ldb_ch->panel) {
+   drm_connector_helper_add(_ldb_ch->connector,
+   _ldb_connector_helper_funcs);
+   drm_connector_init(drm, _ldb_ch->connector,
+   _ldb_connector_funcs,
+   DRM_MODE_CONNECTOR_LVDS);
ret = drm_panel_attach(imx_ldb_ch->panel,
-  _ldb_ch->connector);
+   _ldb_ch->connector);
if (ret)
return ret;
}

-   drm_mode_connector_attach_encoder(_ldb_ch->connector, encoder);
+   if (imx_ldb_ch->bridge) {
+   imx_ldb_ch->bridge->encoder = encoder;
+
+   imx_ldb_ch->encoder.bridge = imx_ldb_ch->bridge;
+   ret = drm_bridge_attach(drm, imx_ldb_ch->bridge);
+   if (ret) {
+   DRM_ERROR("Failed to initialize bridge with drm\n");
+   return ret;
+   }
+   }

return 0;
 }
@@ -551,6 +564,45 @@ static const struct of_device_id imx_ldb_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);

+static int imx_ldb_panel_ddc(struct device *dev,
+   struct imx_ldb_channel *channel, struct device_node *child)
+{
+   struct device_node *ddc_node;
+   const u8 *edidp;
+   int ret;
+
+   ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
+   if (ddc_node) {
+   channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
+   of_node_put(ddc_node);
+   if (!channel->ddc) {
+   dev_warn(dev, "failed to get ddc i2c adapter\n");
+   return -EPROBE_DEFER;
+   }
+   }
+
+   if (!channel->ddc) {
+   /* if no DDC available, fallback to hardcoded EDID */
+   dev_dbg(dev, "no ddc available\n");
+
+   edidp = of_get_property(child, "edid",
+   >edid_len);
+   if (edidp) {
+   channel->edid = kmemdup(edidp,
+   channel->edid_len,
+   GFP_KERNEL);
+   } else if (!channel->panel) {
+   /* fallback to display-timings node */
+   ret = of_get_drm_display_mode(child,
+ >mode,
+ OF_USE_NATIVE_MODE);
+   if (!ret)
+   channel->mode_valid = 1;
+   }
+   }
+   return 0;
+}
+
 static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 {
struct drm_device *drm = data;
@@ -558,7 +610,6 @@ static int imx_ldb_bind(struct device *dev, struct device 
*master, void *data)
const struct of_device_id *of_id =
of_match_device(imx_ldb_dt_ids, dev);
struct device_node *child;
-

[PATCH V3 0/5] Add driver for GE B850v3 LVDS/DP++ Bridge

2016-07-31 Thread Peter Senna Tschudin 
The series adds a driver that creates a drm_bridge and a drm_connector for the
LVDS to DP++ display bridge of the GE B850v3.

There are two physical bridges on the video signal pipeline: a STDP4028(LVDS to
DP) and a STDP2690(DP to DP++).  The hardware and firmware made it complicated
for this binding to comprise two device tree nodes, as the design goal is to
configure both bridges based on the LVDS signal, which leave the driver
powerless to control the video processing pipeline. The two bridges behaves as
a single bridge, and the driver is only needed for telling the host about EDID /
HPD, and for giving the host powers to ack interrupts. The video signal
pipeline is as follows:

  Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

The patches from the series:
 [1/5] Change the imx-ldb driver to allow attaching a bridge and not only a LVDS
   panel.

 [2/5] Configure the mapping between IPUs and external displays on the dts file
   of the B850v3. Needed to support two simultaneos Full-HD monitors.

 [3/5] Devicetree documentation for the GE B850v3 LVDS/DP++ Bridge

 [4/5] Add the driver, make changes to MAINTAINERS, Kconfig and Makefile

 [5/5] Make the changes to the B850v3 dts file to enable the GE B850v3
   LVDS/DP++ Bridge.

Peter Senna Tschudin (5):
  drm/imx-ldb: Add support to drm-bridge
  dts/imx6q-b850v3: Configure IPU assignment order
  Documentation/devicetree/bindings: b850v3_lvds_dp
  drm/bridge: Add driver for GE B850v3 LVDS/DP++ Bridge
  dts/imx6q-b850v3: Use GE B850v3 LVDS/DP++ Bridge

 .../devicetree/bindings/ge/b850v3-lvds-dp.txt  |  37 ++
 MAINTAINERS|   8 +
 arch/arm/boot/dts/imx6q-b850v3.dts |  35 ++
 drivers/gpu/drm/bridge/Kconfig |  11 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c | 397 +
 drivers/gpu/drm/imx/imx-ldb.c  | 111 +++---
 7 files changed, 559 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
 create mode 100644 drivers/gpu/drm/bridge/ge_b850v3_lvds_dp.c

-- 
2.5.5

[Bug 97022] Garbage in windows while running a game windowed

2016-07-31 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=97022

--- Comment #11 from Chernovsky Oleg  ---
No, I was asking Michael actually, but thanks for explanation, it guves a clue.

Regression is a situation when something was working before update and stopped
afterwards. So in your case in Mesa 11 it worked and broke in Mesa 12. Most
likely something was broken between releases, that's why Michael asked for
bisect.

-- 
You are receiving this mail because:
You are the assignee for the bug.
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[RESEND] [PATCH v9 4/4] drm/panel: Add JDI LT070ME05000 WUXGA DSI Panel

2016-07-31 Thread Vinay Simha BN 
Add support for the JDI LT070ME05000 WUXGA DSI panel used in
Nexus 7 2013 devices.

Programming sequence for the panel is was originally found in the
android-msm-flo-3.4-lollipop-release branch from:
https://android.googlesource.com/kernel/msm.git

And video mode setting is from dsi-panel-jdi-dualmipi1-video.dtsi
file in:
git://codeaurora.org/kernel/msm-3.10.git  LNX.LA.3.6_rb1.27

Cc: Archit Taneja 
Cc: Rob Clark 
Cc: Sumit Semwal 
Cc: John Stultz 
Cc: Emil Velikov 
Cc: Thierry Reding 
Cc: David Airlie 
Signed-off-by: Sumit Semwal 
Signed-off-by: John Stultz 
Signed-off-by: Vinay Simha BN 
Tested-by: John Stultz 
Reviewed-by: Emil Velikov 

---
v1:
 * sumit ported to drm/panel framework, john cherry-picked to mainline,
   folded down other fixes from Vinay and Archit, vinay removed interface
   setting cmd mode, video mode panel selected

v2:
 * incorporated code reviews from theiry, archit
   code style, alphabetical soring in Makefile, Kconfig, regulator_bulk,
   arrays of u8, generic helper function, documentation bindings,

v3:
 * dcs backlight support added
 * tested this panel driver in nexus7 2013 device

v4:
 * backlight interface added in the panel driver
 * incorporated width_mm and height_mm suggested by rob herring

v5:
 * theirry review comments incorporated
   panel model naming consistent, alphabetical soring in Kconfig
   Makefile, MAX_BRIGHTNESS dropped, regulator_names, parameterize
   panel width and height, descprition for control display, cabc
   and interface setting, temporary variable removed, consistent
   error reporting and commit message
 * removed tear on/off, scanline, since these are required only
   for command mode panels

v6:
 * emil review comments incorporated
   PANEL_NUM_REGULATORS dropped, return ret added at necessary
   places, if checks dropped for backlight and gpios

v7:
 * emil review comments incorporated
   added ARRAY_SIZE in struct, regulator_bulk_disable in poweroff,
   gpios checks dropped.
   some returns cannot be dropped, since drm panel framework return
   type required.

v8:
 * emil review commnets incorporated for jdi_panel_unprepare,
   dropped the returns (ref: panel-sharp-lq101r1sx01.c) and
   for jdi_panel_prepare(panel_on) it does not return prematurely
   and goes to poweroff if not success
 * few dev_err's for panel_init

v9:
 * function drm_panel_create_dsi_backlight made as static
---
 drivers/gpu/drm/panel/Kconfig  |  11 +
 drivers/gpu/drm/panel/Makefile |   1 +
 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c | 518 +
 3 files changed, 530 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 1500ab9..62aba97 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -18,6 +18,17 @@ config DRM_PANEL_SIMPLE
  that it can be automatically turned off when the panel goes into a
  low power state.

+config DRM_PANEL_JDI_LT070ME05000
+   tristate "JDI LT070ME05000 WUXGA DSI panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to enable support for JDI DSI video mode
+ panel as found in Google Nexus 7 (2013) devices.
+ The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses
+ 24 bit per pixel.
+
 config DRM_PANEL_SAMSUNG_LD9040
tristate "Samsung LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index f277eed..a5c7ec0 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
 obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
 obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += 
panel-panasonic-vvx10f034n00.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c 
b/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c
new file mode 100644
index 000..517fa89
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c
@@ -0,0 +1,518 @@
+/*
+ * Copyright (C) 2016 InforceComputing
+ * Author: Vinay Simha BN 
+ *
+ * Copyright (C) 2016 Linaro Ltd
+ * Author: Sumit Semwal 
+ *
+ * From internet archives, the panel for Nexus 7 2nd Gen, 2013 model is a
+ * JDI model LT070ME05000, and its data sheet is at:
+ * http://panelone.net/en/7-0-inch/JDI_LT070ME05000_7.0_inch-datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of

[RESEND] [PATCH v3 3/4] drm/dsi: Implement dcs set/get display brightness

2016-07-31 Thread Vinay Simha BN 
Provide a small convenience wrapper that set/get the
display brightness value

Cc: John Stultz 
Cc: Sumit Semwal 
Cc: Archit Taneja 
Cc: Rob Clark 
Cc: Jani Nikula 
Cc: Thierry Reding 
Cc: Emil Velikov 
Signed-off-by: Vinay Simha BN 
Reviewed-by: Emil Velikov 

---
v1:
 *tested in nexus7 2nd gen.

v2:
 * implemented jani review comments
   -functions name mapped accordingly
   -bl value increased from 0xff to 0x
   -backlight interface will be handled in panel driver,
so it is moved from the mipi_dsi helper function

v3:
 * emil review comments
   (err < 0) supposed to be (err <= 0)
---
 drivers/gpu/drm/drm_mipi_dsi.c | 49 ++
 include/drm/drm_mipi_dsi.h |  4 
 2 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index af0d471..43aa743 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -1041,6 +1041,55 @@ int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device 
*dsi, u8 format)
 }
 EXPORT_SYMBOL(mipi_dsi_dcs_set_pixel_format);

+/**
+ * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value
+ * of the display
+ * @dsi: DSI peripheral device
+ * @brightness: brightness value
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi,
+   u16 *brightness)
+{
+   ssize_t err;
+
+   err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
+   brightness, sizeof(*brightness));
+   if (err <= 0) {
+   if (err == 0)
+   err = -ENODATA;
+
+   return err;
+   }
+
+   return 0;
+}
+EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness);
+
+/**
+ * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of
+ * the display
+ * @dsi: DSI peripheral device
+ * @brightness: brightness value
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi,
+   u16 brightness)
+{
+   ssize_t err;
+   u8 bl_value[2] = { brightness & 0xff, brightness >> 8 };
+
+   err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
+bl_value, sizeof(bl_value));
+   if (err < 0)
+   return err;
+
+   return 0;
+}
+EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness);
+
 static int mipi_dsi_drv_probe(struct device *dev)
 {
struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver);
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 47ac925..404c373 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -270,6 +270,10 @@ int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi);
 int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
 enum mipi_dsi_dcs_tear_mode mode);
 int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format);
+int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi,
+   u16 *brightness);
+int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi,
+   u16 brightness);

 /**
  * struct mipi_dsi_driver - DSI driver
-- 
2.1.2

[RESEND] [PATCH v2 2/4] dt-bindings: Add jdi lt070me05000 panel bindings

2016-07-31 Thread Vinay Simha BN 
Add documentation for lt070me05000 panel

Cc: Archit Taneja 
Cc: John Stultz 
Cc: Thierry Reding 
Cc: Sumit Semwal 
Signed-off-by: Vinay Simha BN 
Acked-by: Rob Herring 

---
v2:
 * incorporated rob herring and thierry reviews
   gpio to gpios, gpio to regulator using fixed regulators
   and pwm backlight is removed, since it is controlled by
   dcs commands
---
 .../bindings/display/panel/jdi,lt070me05000.txt| 57 ++
 1 file changed, 57 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt 
b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt
new file mode 100644
index 000..613b76f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt
@@ -0,0 +1,57 @@
+JDI model LT070ME05000 1200x1920 7" DSI Panel
+
+Required properties:
+- compatible: should be "jdi,lt070me05000"
+- vddp-supply: phandle of the regulator that provides the supply voltage
+  Power IC supply (3-5V)
+- dcdc_en-supply: phandle of the regulator that provides the supply voltage
+  Power IC supply enable, High active
+- vcc-supply: phandle of the regulator that provides the supply voltage
+  IOVCC , power supply for LCM (1.8V)
+- reset-gpios: phandle of gpio for reset line
+  This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
+  XRES, Reset, Low active
+- enable-gpios: phandle of gpio for enable line
+  LED_EN, LED backlight enable, High active
+
+Example:
+
+   vcc_1p8v: regulator-fixed at 2 {
+   compatible = "regulator-fixed";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc_1p8v";
+   regulator-type = "voltage";
+   startup-delay-us = <0>;
+   gpio = <_gpio 23 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-boot-on;
+   };
+
+   tlmm_pinmux: pinctrl at 80 {
+
+   dsi_panel_pinctrl: dsi-panel-pinctrl {
+   mux {
+   pins = "gpio54";
+   function = "gpio";
+   bias-pull-up;
+   drive-strength = <8>;
+   };
+   };
+   };
+
+   dsi0: qcom,mdss_dsi at 470 {
+   panel at 0 {
+   compatible = "jdi,lt070me05000";
+   reg = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_panel_pinctrl>;
+
+   vddp-supply = <_l17>;
+   dcdc_en-supply = <_lvs7>;
+   vcc-supply = <_1p8v>;
+
+   reset-gpios = <_pinmux 54 0>;
+   enable-gpios = <_gpio 36 GPIO_ACTIVE_HIGH>;
+   };
+   };
-- 
2.1.2

[Bug 97055] Black screens on A10-8780P (Carrizo) + R7 M260/M265 (Topaz) Combo

2016-07-31 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=97055

--- Comment #2 from Thomas J. Moore  ---
Still broken in 4.7.0, in case that wasn't obvious.  In related news, took me
20 minutes of blind reboots to get this piece of crap running this afternoon
(came up after "only" 4 boots this morning).  Now it seems to like going black
in X shortly after starting, even with power management turned off.  Thermal
issues?  Not likely, since the machine runs hot during use and doesn't flake
out, but who knows?  Defective hardware?  Not likely, since efifb works
perfectly every time (but I do want to occasionally do things that are not
affected by the limitations of efifb).  Given the complete lack of
documentation for just about anything power related, both hardware and software
(how about that incredibly useful barely English documentation "select this
option will enable AMD powerplay component." for the "Enable AMD powerplay
component" compile-time option?  Good thing everybody knows exactly what AMD
powerplay is, and how it differs from all the other undocumented power
management options), I can't exactly fix this myself.

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[Bug 97157] MST displays fail to wake

2016-07-31 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=97157

Bug ID: 97157
   Summary: MST displays fail to wake
   Product: DRI
   Version: XOrg git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: DRM/Radeon
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: dan.doel at gmail.com

Created attachment 125450
  --> https://bugs.freedesktop.org/attachment.cgi?id=125450=edit
dmesg output

Since moving to kernel 4.6, I've been having regular problems with my MST
monitors failing to wake after being put to sleep. This only seems to occur
after the machine has been on for a sufficient amount of time, but I usually
experience it within a day of booting, and typically after the displays have
been powered off for an extended period of time.

There are two MST monitors, but typically only one fails to wake. Also, it is
more often that the secondary display is the one that fails. However, I have
had the primary display fail to come back (while the secondary one succeeds),
and I have had both fail to come back as well.

Sometimes, only a complete power off is able to make the monitors wake up; a
reboot is not always sufficient.

The dmesg displays some errors, and I've poked around a bit. It seems likely
that this is related to commit f3d58dccdbf9f8c0a229d555d4b295d52e743039, which
was first included in 4.6. This commit basically causes dpms to work at all
with MST monitors; before it was a no-op that didn't actually put the monitors
into power saving. That doesn't help narrow the problem down much, though,
since a significant portion of the mst dpms code probably wasn't being
exercised before that.

Also, it seems notable that the error message (which seems more like a debug
message) in the STANDBY/SUSPEND/OFF case keeps reporting higher numbers, as
though it keeps going through the ON case, which increments the variable, but
not making it through the portion of the OFF case that decrements the variable.

I'll attach dmesg journal output that might be relevant. I believe the
error/debug messages timestamped 'Jul 31 11:03:49' correspond to the first time
one of the displays failed to wake up. I tried various ways of toggling the
dpms off and on after that, so those are the subsequent error messages in the
log.

As far as specs go, I have:
  Radeon HD7870 (Pitcairn)
  Kernel 4.6.4 (4.6.3 also affected)
  2 UP2414Q mst displays
  xorg-server 1.18.4
  Modesetting driver

Let me know if there's any more information I can try to provide.

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[PATCH] drm: Don't prepare or cleanup unchanging frame buffers [v2]

2016-07-31 Thread kbuild test robot 
Hi,

[auto build test WARNING on v4.7-rc7]
[cannot apply to drm/drm-next next-20160729]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Keith-Packard/drm-Don-t-prepare-or-cleanup-unchanging-frame-buffers-v2/20160731-161116
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_irq.c:2722: warning: No description found for 
parameter 'fmt'
   include/drm/drm_crtc.h:374: warning: No description found for parameter 
'mode_blob'
   include/drm/drm_crtc.h:789: warning: No description found for parameter 
'name'
   include/drm/drm_crtc.h:1248: warning: No description found for parameter 
'connector_id'
   include/drm/drm_crtc.h:1248: warning: No description found for parameter 
'tile_blob_ptr'
   include/drm/drm_crtc.h:1287: warning: No description found for parameter 
'rotation'
   include/drm/drm_crtc.h:1550: warning: No description found for parameter 
'name'
   include/drm/drm_crtc.h:1550: warning: No description found for parameter 
'mutex'
>> include/drm/drm_crtc.h:1550: warning: No description found for parameter 
>> 'prepared'
   include/drm/drm_crtc.h:1550: warning: No description found for parameter 
'helper_private'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tile_idr'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'connector_ida'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'delayed_event'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'edid_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'dpms_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'path_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tile_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'plane_type_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'rotation_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_src_x'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_src_y'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_src_w'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_src_h'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_crtc_x'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_crtc_y'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_crtc_w'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_crtc_h'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_fb_id'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_crtc_id'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_active'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'prop_mode_id'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'dvi_i_subconnector_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'dvi_i_select_subconnector_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_subconnector_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_select_subconnector_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_mode_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_left_margin_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_right_margin_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_top_margin_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_bottom_margin_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_brightness_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_contrast_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_flicker_reduction_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_overscan_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_saturation_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'tv_hue_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'scaling_mode_property'
   include/drm/drm_crtc.h:2186: warning: No description found for parameter 
'aspect_ratio_property'
   incl

[PATCH v3 00/12] IPUv3 prep for i.MX5/6 v4l2 staging drivers, v3

2016-07-31 Thread Steve Longerbeam 
On 07/31/2016 12:42 PM, Steve Longerbeam wrote:
> In this version:
>
> - API changes to ipu-vdi.c in "gpu: ipu-v3: Add Video Deinterlacer unit".
> - "gpu: ipu-v3: Add FSU channel linking support" is new but based on
>   previous patch "gpu: ipu-v3: Add IDMA channel linking support".
>
> No other changes from previous version.

Actually one other change from previous version:

- removed the patch "gpu: ipu-v3: Add ipu_set_vdi_src_mux()".

Steve

> Steve Longerbeam (12):
>   gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
>   gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
>   gpu: ipu-v3: Add ipu_get_num()
>   gpu: ipu-v3: Add VDI input IDMAC channels
>   gpu: ipu-v3: set correct full sensor frame for PAL/NTSC
>   gpu: ipu-v3: Fix CSI data format for 16-bit media bus formats
>   gpu: ipu-v3: Fix IRT usage
>   gpu: ipu-v3: rename CSI client device
>   gpu: ipu-v3: Add Video Deinterlacer unit
>   gpu: ipu-v3: Add FSU channel linking support
>   gpu: ipu-ic: Add complete image conversion support with tiling
>   gpu: ipu-ic: allow multiple handles to ic
>
>  drivers/gpu/ipu-v3/Makefile |2 +-
>  drivers/gpu/ipu-v3/ipu-common.c |  154 +++-
>  drivers/gpu/ipu-v3/ipu-cpmem.c  |   13 +
>  drivers/gpu/ipu-v3/ipu-csi.c|   26 +-
>  drivers/gpu/ipu-v3/ipu-ic.c | 1756 
> ++-
>  drivers/gpu/ipu-v3/ipu-prv.h|   34 +
>  drivers/gpu/ipu-v3/ipu-vdi.c|  254 ++
>  include/video/imx-ipu-v3.h  |   99 ++-
>  8 files changed, 2278 insertions(+), 60 deletions(-)
>  create mode 100644 drivers/gpu/ipu-v3/ipu-vdi.c
>

[PATCH v3 12/12] gpu: ipu-ic: allow multiple handles to ic

2016-07-31 Thread Steve Longerbeam 
The image converter kernel API supports conversion contexts and
job queues, so we should allow more than one handle to the IC, so
that multiple users can add jobs to the queue.

Note however that users that control the IC manually (that do not
use the image converter APIs but setup the IC task by hand via calls
to ipu_ic_task_enable(), ipu_ic_enable(), etc.) must still be careful not
to share the IC handle with other threads. At this point, the only user
that still controls the IC manually is the i.mx capture driver. In that
case the capture driver only allows one open context to get a handle
to the IC at a time, so we should be ok there.

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-ic.c | 25 +
 1 file changed, 1 insertion(+), 24 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
index 5471b72..cc0780b 100644
--- a/drivers/gpu/ipu-v3/ipu-ic.c
+++ b/drivers/gpu/ipu-v3/ipu-ic.c
@@ -342,7 +342,6 @@ struct ipu_ic {
enum ipu_color_space out_cs;
bool graphics;
bool rotation;
-   bool in_use;

struct image_converter cvt;

@@ -2367,38 +2366,16 @@ EXPORT_SYMBOL_GPL(ipu_ic_disable);
 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task)
 {
struct ipu_ic_priv *priv = ipu->ic_priv;
-   unsigned long flags;
-   struct ipu_ic *ic, *ret;

if (task >= IC_NUM_TASKS)
return ERR_PTR(-EINVAL);

-   ic = >task[task];
-
-   spin_lock_irqsave(>lock, flags);
-
-   if (ic->in_use) {
-   ret = ERR_PTR(-EBUSY);
-   goto unlock;
-   }
-
-   ic->in_use = true;
-   ret = ic;
-
-unlock:
-   spin_unlock_irqrestore(>lock, flags);
-   return ret;
+   return >task[task];
 }
 EXPORT_SYMBOL_GPL(ipu_ic_get);

 void ipu_ic_put(struct ipu_ic *ic)
 {
-   struct ipu_ic_priv *priv = ic->priv;
-   unsigned long flags;
-
-   spin_lock_irqsave(>lock, flags);
-   ic->in_use = false;
-   spin_unlock_irqrestore(>lock, flags);
 }
 EXPORT_SYMBOL_GPL(ipu_ic_put);

-- 
1.9.1

[PATCH v3 11/12] gpu: ipu-ic: Add complete image conversion support with tiling

2016-07-31 Thread Steve Longerbeam 
This patch implements complete image conversion support to ipu-ic,
with tiling to support scaling to and from images up to 4096x4096.
Image rotation is also supported.

The internal API is subsystem agnostic (no V4L2 dependency except
for the use of V4L2 fourcc pixel formats).

Callers prepare for image conversion by calling
ipu_image_convert_prepare(), which initializes the parameters of
the conversion. The caller passes in the ipu_ic task to use for
the conversion, the input and output image formats, a rotation mode,
and a completion callback and completion context pointer:

struct image_converter_ctx *
ipu_image_convert_prepare(struct ipu_ic *ic,
  struct ipu_image *in, struct ipu_image *out,
  enum ipu_rotate_mode rot_mode,
  image_converter_cb_t complete,
  void *complete_context);

The caller is given a new conversion context that must be passed to
the further APIs:

struct image_converter_run *
ipu_image_convert_run(struct image_converter_ctx *ctx,
  dma_addr_t in_phys, dma_addr_t out_phys);

This queues a new image conversion request to a run queue, and
starts the conversion immediately if the run queue is empty. Only
the physaddr's of the input and output image buffers are needed,
since the conversion context was created previously with
ipu_image_convert_prepare(). Returns a new run object pointer. When
the conversion completes, the run pointer is returned to the
completion callback.

void image_convert_abort(struct image_converter_ctx *ctx);

This will abort any active or pending conversions for this context.
Any currently active or pending runs belonging to this context are
returned via the completion callback with an error status.

void ipu_image_convert_unprepare(struct image_converter_ctx *ctx);

Unprepares the conversion context. Any active or pending runs will
be aborted by calling image_convert_abort().

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-ic.c | 1691 ++-
 include/video/imx-ipu-v3.h  |   57 +-
 2 files changed, 1736 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
index 1a37afc..5471b72 100644
--- a/drivers/gpu/ipu-v3/ipu-ic.c
+++ b/drivers/gpu/ipu-v3/ipu-ic.c
@@ -17,6 +17,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include "ipu-prv.h"

 /* IC Register Offsets */
@@ -82,6 +84,40 @@
 #define IC_IDMAC_3_PP_WIDTH_MASK(0x3ff << 20)
 #define IC_IDMAC_3_PP_WIDTH_OFFSET  20

+/*
+ * The IC Resizer has a restriction that the output frame from the
+ * resizer must be 1024 or less in both width (pixels) and height
+ * (lines).
+ *
+ * The image conversion support attempts to split up a conversion when
+ * the desired output (converted) frame resolution exceeds the IC resizer
+ * limit of 1024 in either dimension.
+ *
+ * If either dimension of the output frame exceeds the limit, the
+ * dimension is split into 1, 2, or 4 equal stripes, for a maximum
+ * of 4*4 or 16 tiles. A conversion is then carried out for each
+ * tile (but taking care to pass the full frame stride length to
+ * the DMA channel's parameter memory!). IDMA double-buffering is used
+ * to convert each tile back-to-back when possible (see note below
+ * when double_buffering boolean is set).
+ *
+ * Note that the input frame must be split up into the same number
+ * of tiles as the output frame.
+ */
+#define MAX_STRIPES_W4
+#define MAX_STRIPES_H4
+#define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H)
+
+#define MIN_W 128
+#define MIN_H 128
+#define MAX_W 4096
+#define MAX_H 4096
+
+enum image_convert_type {
+   IMAGE_CONVERT_IN = 0,
+   IMAGE_CONVERT_OUT,
+};
+
 struct ic_task_regoffs {
u32 rsc;
u32 tpmem_csc[2];
@@ -96,6 +132,16 @@ struct ic_task_bitfields {
u32 ic_cmb_galpha_bit;
 };

+struct ic_task_channels {
+   int in;
+   int out;
+   int rot_in;
+   int rot_out;
+   int vdi_in_p;
+   int vdi_in;
+   int vdi_in_n;
+};
+
 static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = {
[IC_TASK_ENCODER] = {
.rsc = IC_PRP_ENC_RSC,
@@ -138,12 +184,159 @@ static const struct ic_task_bitfields 
ic_task_bit[IC_NUM_TASKS] = {
},
 };

+static const struct ic_task_channels ic_task_ch[IC_NUM_TASKS] = {
+   [IC_TASK_ENCODER] = {
+   .out = IPUV3_CHANNEL_IC_PRP_ENC_MEM,
+   .rot_in = IPUV3_CHANNEL_MEM_ROT_ENC,
+   .rot_out = IPUV3_CHANNEL_ROT_ENC_MEM,
+   },
+   [IC_TASK_VIEWFINDER] = {
+   .in = IPUV3_CHANNEL_MEM_IC_PRP_VF,
+   .out = IPUV3_CHANNEL_IC_PRP_VF_MEM,
+   .rot_in = IPUV3_CHANNEL_MEM_ROT_VF,
+   .rot_out = IPUV3_CHANNEL_ROT_VF_MEM,
+   .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV,
+   .vdi_in =

[PATCH v3 10/12] gpu: ipu-v3: Add FSU channel linking support

2016-07-31 Thread Steve Longerbeam 
Adds functions to link and unlink source channels to sink
channels in the FSU:

int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);

The channels numbers are usually IDMAC channels, but they can also be
channels that do not transfer data to or from memory. The following
convenience functions can be used in place of ipu_fsu_link/unlink()
when both source and sink channels are IDMAC channels:

int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -> IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM  -> IPUV3_CHANNEL_MEM_ROT_PP
IPUV3_CHANNEL_CSI_DIRECT -> IPUV3_CHANNEL_CSI_VDI_PREV

More links can be added to the fsu_link_info[] array.

Signed-off-by: Steve Longerbeam 
---
 drivers/gpu/ipu-v3/ipu-common.c | 131 
 drivers/gpu/ipu-v3/ipu-prv.h|  27 +
 include/video/imx-ipu-v3.h  |  13 
 3 files changed, 171 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 9d3584b..891cbef 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -730,6 +730,137 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, 
bool vdi)
 }
 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);

+
+/* Frame Synchronization Unit Channel Linking */
+
+struct fsu_link_reg_info {
+   int chno;
+   u32 reg;
+   u32 mask;
+   u32 val;
+};
+
+struct fsu_link_info {
+   struct fsu_link_reg_info src;
+   struct fsu_link_reg_info sink;
+};
+
+static const struct fsu_link_info fsu_link_info[] = {
+   {
+   .src  = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
+ FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC 
},
+   .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
+ FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC 
},
+   }, {
+   .src =  { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
+ FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
+   .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
+ FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
+   }, {
+   .src =  { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
+ FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
+   .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
+ FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
+   }, {
+   .src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
+   .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
+ FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
+   },
+};
+
+static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
+   if (src == fsu_link_info[i].src.chno &&
+   sink == fsu_link_info[i].sink.chno)
+   return _link_info[i];
+   }
+
+   return NULL;
+}
+
+/*
+ * Links a source channel to a sink channel in the FSU.
+ */
+int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
+{
+   const struct fsu_link_info *link;
+   u32 src_reg, sink_reg;
+   unsigned long flags;
+
+   link = find_fsu_link_info(src_ch, sink_ch);
+   if (!link)
+   return -EINVAL;
+
+   spin_lock_irqsave(>lock, flags);
+
+   if (link->src.mask) {
+   src_reg = ipu_cm_read(ipu, link->src.reg);
+   src_reg &= ~link->src.mask;
+   src_reg |= link->src.val;
+   ipu_cm_write(ipu, src_reg, link->src.reg);
+   }
+
+   if (link->sink.mask) {
+   sink_reg = ipu_cm_read(ipu, link->sink.reg);
+   sink_reg &= ~link->sink.mask;
+   sink_reg |= link->sink.val;
+   ipu_cm_write(ipu, sink_reg, link->sink.reg);
+   }
+
+   spin_unlock_irqrestore(>lock, flags);
+   return 0;
+}
+EXPORT_SYMBOL_GPL(ipu_fsu_link);
+
+/*
+ * Unlinks source and sink channels in the FSU.
+ */
+int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
+{
+   const struct fsu_link_info *link;
+   u32 src_reg, sink_reg;
+   unsigned long flags;
+
+   link = find_fsu_link_info(src_ch, sink_ch);
+   if (!link)
+   return -EINVAL;
+
+   spin_lock_irqsave(>lock, flags);
+
+   if (link->src.mask) {
+   src_reg = ipu_cm_read(ipu, link->src.reg);
+   src_reg &= ~link->src.mask;
+   ipu_cm_write(ipu, src_reg, link->src.reg);
+   }
+
+   if (link->sink.mask) {
+   sink_reg =

[PATCH v3 09/12] gpu: ipu-v3: Add Video Deinterlacer unit

2016-07-31 Thread Steve Longerbeam 
Adds the Video Deinterlacer (VDIC) unit.

Signed-off-by: Steve Longerbeam 

---

v3:
- renamed and exported ipu_vdi_set_top_field_man() to
  ipu_vdi_set_field_order(). Args include std and field to determine
  correct field order.
- exported ipu_vdi_set_motion().
- ipu_vdi_setup() does not need to call ipu_vdi_set_top_field_man() or
  ipu_vdi_set_motion(), since latter are exported. This simplifies args.
- removed ipu_vdi_toggle_top_field_man().
- removed ipu_vdi_set_src().

v2:
- removed include of module.h
- corrected V4L2 field type checks
- cleaned up use_count decrement in ipu_vdi_disable()
---
 drivers/gpu/ipu-v3/Makefile |   2 +-
 drivers/gpu/ipu-v3/ipu-common.c |  11 ++
 drivers/gpu/ipu-v3/ipu-prv.h|   6 +
 drivers/gpu/ipu-v3/ipu-vdi.c| 254 
 include/video/imx-ipu-v3.h  |  23 
 5 files changed, 295 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/ipu-v3/ipu-vdi.c

diff --git a/drivers/gpu/ipu-v3/Makefile b/drivers/gpu/ipu-v3/Makefile
index 107ec23..aeba9dc 100644
--- a/drivers/gpu/ipu-v3/Makefile
+++ b/drivers/gpu/ipu-v3/Makefile
@@ -1,4 +1,4 @@
 obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o

 imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
-   ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-smfc.o
+   ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-smfc.o ipu-vdi.o
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index d230988..9d3584b 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -839,6 +839,14 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
goto err_ic;
}

+   ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
+  IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
+  IPU_CONF_IC_INPUT);
+   if (ret) {
+   unit = "vdi";
+   goto err_vdi;
+   }
+
ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
  IPU_CONF_DI0_EN, ipu_clk);
if (ret) {
@@ -893,6 +901,8 @@ err_dc:
 err_di_1:
ipu_di_exit(ipu, 0);
 err_di_0:
+   ipu_vdi_exit(ipu);
+err_vdi:
ipu_ic_exit(ipu);
 err_ic:
ipu_csi_exit(ipu, 1);
@@ -977,6 +987,7 @@ static void ipu_submodules_exit(struct ipu_soc *ipu)
ipu_dc_exit(ipu);
ipu_di_exit(ipu, 1);
ipu_di_exit(ipu, 0);
+   ipu_vdi_exit(ipu);
ipu_ic_exit(ipu);
ipu_csi_exit(ipu, 1);
ipu_csi_exit(ipu, 0);
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index fd47f8f..02057d8 100644
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -138,6 +138,7 @@ struct ipu_dc_priv;
 struct ipu_dmfc_priv;
 struct ipu_di;
 struct ipu_ic_priv;
+struct ipu_vdi;
 struct ipu_smfc_priv;

 struct ipu_devtype;
@@ -170,6 +171,7 @@ struct ipu_soc {
struct ipu_di   *di_priv[2];
struct ipu_csi  *csi_priv[2];
struct ipu_ic_priv  *ic_priv;
+   struct ipu_vdi  *vdi_priv;
struct ipu_smfc_priv*smfc_priv;
 };

@@ -200,6 +202,10 @@ int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, unsigned long tpmem_base);
 void ipu_ic_exit(struct ipu_soc *ipu);

+int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
+unsigned long base, u32 module);
+void ipu_vdi_exit(struct ipu_soc *ipu);
+
 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
unsigned long base, u32 module, struct clk *ipu_clk);
 void ipu_di_exit(struct ipu_soc *ipu, int id);
diff --git a/drivers/gpu/ipu-v3/ipu-vdi.c b/drivers/gpu/ipu-v3/ipu-vdi.c
new file mode 100644
index 000..abd080c
--- /dev/null
+++ b/drivers/gpu/ipu-v3/ipu-vdi.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2012-2016 Mentor Graphics Inc.
+ * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ipu-prv.h"
+
+struct ipu_vdi {
+   void __iomem *base;
+   u32 module;
+   spinlock_t lock;
+   int use_count;
+   struct ipu_soc *ipu;
+};
+
+
+/* VDI Register Offsets */
+#define VDI_FSIZE 0x
+#define VDI_C 0x0004
+
+/* VDI Register Fields */
+#define VDI_C_CH_420 (0 << 1)
+#define VDI_C_CH_422 (1 << 1)
+#define VDI_C_MOT_SEL_MASK

[PATCH v3 08/12] gpu: ipu-v3: rename CSI client device

2016-07-31 Thread Steve Longerbeam 
Rename the CSI client device in the client_reg[] table to
"imx-ipuv3-csi".

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index d697cd5..d230988 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1010,14 +1010,14 @@ static struct ipu_platform_reg client_reg[] = {
.dma[0] = IPUV3_CHANNEL_CSI0,
.dma[1] = -EINVAL,
},
-   .name = "imx-ipuv3-camera",
+   .name = "imx-ipuv3-csi",
}, {
.pdata = {
.csi = 1,
.dma[0] = IPUV3_CHANNEL_CSI1,
.dma[1] = -EINVAL,
},
-   .name = "imx-ipuv3-camera",
+   .name = "imx-ipuv3-csi",
}, {
.pdata = {
.di = 0,
-- 
1.9.1

[PATCH v3 07/12] gpu: ipu-v3: Fix IRT usage

2016-07-31 Thread Steve Longerbeam 
There can be multiple IC tasks using the IRT, so the IRT needs
a separate use counter. Create a private ipu_irt_enable() to
enable the IRT module when any IC task requires rotation, and
ipu_irt_disable() when a task no longer needs the IRT.

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2:
- cleaned up irt_use_count decrement in ipu_irt_disable()
---
 drivers/gpu/ipu-v3/ipu-ic.c | 40 +++-
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
index 1dcb96c..1a37afc 100644
--- a/drivers/gpu/ipu-v3/ipu-ic.c
+++ b/drivers/gpu/ipu-v3/ipu-ic.c
@@ -160,6 +160,7 @@ struct ipu_ic_priv {
spinlock_t lock;
struct ipu_soc *ipu;
int use_count;
+   int irt_use_count;
struct ipu_ic task[IC_NUM_TASKS];
 };

@@ -379,8 +380,6 @@ void ipu_ic_task_disable(struct ipu_ic *ic)

ipu_ic_write(ic, ic_conf, IC_CONF);

-   ic->rotation = ic->graphics = false;
-
spin_unlock_irqrestore(>lock, flags);
 }
 EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
@@ -629,22 +628,41 @@ unlock:
 }
 EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);

+static void ipu_irt_enable(struct ipu_ic *ic)
+{
+   struct ipu_ic_priv *priv = ic->priv;
+
+   if (!priv->irt_use_count)
+   ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN);
+
+   priv->irt_use_count++;
+}
+
+static void ipu_irt_disable(struct ipu_ic *ic)
+{
+   struct ipu_ic_priv *priv = ic->priv;
+
+   if (priv->irt_use_count) {
+   if (!--priv->irt_use_count)
+   ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN);
+   }
+}
+
 int ipu_ic_enable(struct ipu_ic *ic)
 {
struct ipu_ic_priv *priv = ic->priv;
unsigned long flags;
-   u32 module = IPU_CONF_IC_EN;

spin_lock_irqsave(>lock, flags);

-   if (ic->rotation)
-   module |= IPU_CONF_ROT_EN;
-
if (!priv->use_count)
-   ipu_module_enable(priv->ipu, module);
+   ipu_module_enable(priv->ipu, IPU_CONF_IC_EN);

priv->use_count++;

+   if (ic->rotation)
+   ipu_irt_enable(ic);
+
spin_unlock_irqrestore(>lock, flags);

return 0;
@@ -655,18 +673,22 @@ int ipu_ic_disable(struct ipu_ic *ic)
 {
struct ipu_ic_priv *priv = ic->priv;
unsigned long flags;
-   u32 module = IPU_CONF_IC_EN | IPU_CONF_ROT_EN;

spin_lock_irqsave(>lock, flags);

priv->use_count--;

if (!priv->use_count)
-   ipu_module_disable(priv->ipu, module);
+   ipu_module_disable(priv->ipu, IPU_CONF_IC_EN);

if (priv->use_count < 0)
priv->use_count = 0;

+   if (ic->rotation)
+   ipu_irt_disable(ic);
+
+   ic->rotation = ic->graphics = false;
+
spin_unlock_irqrestore(>lock, flags);

return 0;
-- 
1.9.1

[PATCH v3 06/12] gpu: ipu-v3: Fix CSI data format for 16-bit media bus formats

2016-07-31 Thread Steve Longerbeam 
The CSI data format was being programmed incorrectly for the
1x16 media bus formats. The CSI data format for 16-bit must
be bayer/generic (CSI_SENS_CONF_DATA_FMT_BAYER).

Suggested-by: Carsten Resch 
Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-csi.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 641ed76..d6e5ded 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -258,12 +258,8 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config 
*cfg, u32 mbus_code)
cfg->data_width = IPU_CSI_DATA_WIDTH_8;
break;
case MEDIA_BUS_FMT_UYVY8_1X16:
-   cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
-   cfg->mipi_dt = MIPI_DT_YUV422;
-   cfg->data_width = IPU_CSI_DATA_WIDTH_16;
-   break;
case MEDIA_BUS_FMT_YUYV8_1X16:
-   cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
+   cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
cfg->mipi_dt = MIPI_DT_YUV422;
cfg->data_width = IPU_CSI_DATA_WIDTH_16;
break;
-- 
1.9.1

[PATCH v3 05/12] gpu: ipu-v3: set correct full sensor frame for PAL/NTSC

2016-07-31 Thread Steve Longerbeam 
Set the sensor full frame based on whether the passed in mbus_fmt
is 720x480 (NTSC) or 720x576 (PAL).

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-csi.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 06631ac..641ed76 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -365,10 +365,14 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
 {
struct ipu_csi_bus_config cfg;
unsigned long flags;
-   u32 data = 0;
+   u32 width, height, data = 0;

fill_csi_bus_cfg(, mbus_cfg, mbus_fmt);

+   /* set default sensor frame width and height */
+   width = mbus_fmt->width;
+   height = mbus_fmt->height;
+
/* Set the CSI_SENS_CONF register remaining fields */
data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
@@ -386,11 +390,6 @@ int ipu_csi_init_interface(struct ipu_csi *csi,

ipu_csi_write(csi, data, CSI_SENS_CONF);

-   /* Setup sensor frame size */
-   ipu_csi_write(csi,
- (mbus_fmt->width - 1) | ((mbus_fmt->height - 1) << 16),
- CSI_SENS_FRM_SIZE);
-
/* Set CCIR registers */

switch (cfg.clk_mode) {
@@ -408,11 +407,12 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
 */
+   height = 625; /* framelines for PAL */
+
ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
  CSI_CCIR_CODE_1);
ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
ipu_csi_write(csi, 0xFF, CSI_CCIR_CODE_3);
-
} else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
/*
 * NTSC case
@@ -422,6 +422,8 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
 */
+   height = 525; /* framelines for NTSC */
+
ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
  CSI_CCIR_CODE_1);
ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
@@ -447,6 +449,10 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
break;
}

+   /* Setup sensor frame size */
+   ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
+ CSI_SENS_FRM_SIZE);
+
dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
ipu_csi_read(csi, CSI_SENS_CONF));
dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
-- 
1.9.1

[PATCH v3 04/12] gpu: ipu-v3: Add VDI input IDMAC channels

2016-07-31 Thread Steve Longerbeam 
Adds the VDIC field input IDMAC channels. These channels
transfer fields F(n-1), F(n), and F(N+1) from memory to
the VDIC (channels 8, 9, 10 respectively).

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2:
- made the channel names more descriptive: "_PREV" instead of "_P", etc.
---
 include/video/imx-ipu-v3.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index ef54634..c4ccc79 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -97,6 +97,9 @@ enum ipu_channel_irq {
 #define IPUV3_CHANNEL_CSI2  2
 #define IPUV3_CHANNEL_CSI3  3
 #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
+#define IPUV3_CHANNEL_MEM_VDI_PREV  8
+#define IPUV3_CHANNEL_MEM_VDI_CUR   9
+#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
 #define IPUV3_CHANNEL_MEM_IC_PP11
 #define IPUV3_CHANNEL_MEM_IC_PRP_VF12
 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF  14
-- 
1.9.1

[PATCH v3 03/12] gpu: ipu-v3: Add ipu_get_num()

2016-07-31 Thread Steve Longerbeam 
Adds of-alias id to ipu_soc and retrieve with ipu_get_num().

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-common.c | 8 
 drivers/gpu/ipu-v3/ipu-prv.h| 1 +
 include/video/imx-ipu-v3.h  | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 99dcacf..d697cd5 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -45,6 +45,12 @@ static inline void ipu_cm_write(struct ipu_soc *ipu, u32 
value, unsigned offset)
writel(value, ipu->cm_reg + offset);
 }

+int ipu_get_num(struct ipu_soc *ipu)
+{
+   return ipu->id;
+}
+EXPORT_SYMBOL_GPL(ipu_get_num);
+
 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
 {
u32 val;
@@ -1209,6 +1215,7 @@ static int ipu_probe(struct platform_device *pdev)
 {
const struct of_device_id *of_id =
of_match_device(imx_ipu_dt_ids, >dev);
+   struct device_node *np = pdev->dev.of_node;
struct ipu_soc *ipu;
struct resource *res;
unsigned long ipu_base;
@@ -1237,6 +1244,7 @@ static int ipu_probe(struct platform_device *pdev)
ipu->channel[i].ipu = ipu;
ipu->devtype = devtype;
ipu->ipu_type = devtype->type;
+   ipu->id = of_alias_get_id(np, "ipu");

spin_lock_init(>lock);
mutex_init(>channel_lock);
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index bfb1e8a..fd47f8f 100644
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -152,6 +152,7 @@ struct ipu_soc {
void __iomem*cm_reg;
void __iomem*idmac_reg;

+   int id;
int usecount;

struct clk  *clk;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 8c4312d..ef54634 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -138,6 +138,7 @@ int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct 
ipuv3_channel *channel,
 /*
  * IPU Common functions
  */
+int ipu_get_num(struct ipu_soc *ipu);
 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
 void ipu_dump(struct ipu_soc *ipu);
-- 
1.9.1

[PATCH v3 02/12] gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()

2016-07-31 Thread Steve Longerbeam 
Adds ipu_cpmem_get_burstsize().

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-cpmem.c | 6 ++
 include/video/imx-ipu-v3.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index a36c35e..fcb7dc8 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -275,6 +275,12 @@ void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);

+int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch)
+{
+   return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1;
+}
+EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize);
+
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
 {
ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 69c8658..8c4312d 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -187,6 +187,7 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int 
bufnum, dma_addr_t buf);
 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
+int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
-- 
1.9.1

[PATCH v3 01/12] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

2016-07-31 Thread Steve Longerbeam 
Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.

Signed-off-by: Steve Longerbeam 

---

v3: no changes
v2: no changes
---
 drivers/gpu/ipu-v3/ipu-cpmem.c | 7 +++
 include/video/imx-ipu-v3.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 6494a4d..a36c35e 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -253,6 +253,13 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int 
bufnum, dma_addr_t buf)
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);

+void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
+{
+   ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
+   ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
+}
+EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
+
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
 {
ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 7adeaae..69c8658 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -184,6 +184,7 @@ void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int 
xres, int yres);
 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t 
buf);
+void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
-- 
1.9.1

[PATCH v3 00/12] IPUv3 prep for i.MX5/6 v4l2 staging drivers, v3

2016-07-31 Thread Steve Longerbeam 
In this version:

- API changes to ipu-vdi.c in "gpu: ipu-v3: Add Video Deinterlacer unit".
- "gpu: ipu-v3: Add FSU channel linking support" is new but based on
  previous patch "gpu: ipu-v3: Add IDMA channel linking support".

No other changes from previous version.

Steve Longerbeam (12):
  gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
  gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
  gpu: ipu-v3: Add ipu_get_num()
  gpu: ipu-v3: Add VDI input IDMAC channels
  gpu: ipu-v3: set correct full sensor frame for PAL/NTSC
  gpu: ipu-v3: Fix CSI data format for 16-bit media bus formats
  gpu: ipu-v3: Fix IRT usage
  gpu: ipu-v3: rename CSI client device
  gpu: ipu-v3: Add Video Deinterlacer unit
  gpu: ipu-v3: Add FSU channel linking support
  gpu: ipu-ic: Add complete image conversion support with tiling
  gpu: ipu-ic: allow multiple handles to ic

 drivers/gpu/ipu-v3/Makefile |2 +-
 drivers/gpu/ipu-v3/ipu-common.c |  154 +++-
 drivers/gpu/ipu-v3/ipu-cpmem.c  |   13 +
 drivers/gpu/ipu-v3/ipu-csi.c|   26 +-
 drivers/gpu/ipu-v3/ipu-ic.c | 1756 ++-
 drivers/gpu/ipu-v3/ipu-prv.h|   34 +
 drivers/gpu/ipu-v3/ipu-vdi.c|  254 ++
 include/video/imx-ipu-v3.h  |   99 ++-
 8 files changed, 2278 insertions(+), 60 deletions(-)
 create mode 100644 drivers/gpu/ipu-v3/ipu-vdi.c

-- 
1.9.1

[PATCH] drm: Don't prepare or cleanup unchanging frame buffers [v2]

2016-07-31 Thread Keith Packard 
When reconfiguring a plane position (as in moving the cursor), the
frame buffer for the cursor isn't changing, so don't call the prepare
or cleanup driver functions.

This avoids making cursor position updates block on all pending rendering.

v2: Track which planes have been prepared to know which to
cleanup. Otherwise, failure paths and success paths would need
different tests in the cleanup code as the plane state points to
different places in the two cases.

cc: dri-devel at lists.freedesktop.org
cc: David Airlie 
Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/drm_atomic_helper.c | 23 +--
 include/drm/drm_crtc.h  |  1 +
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index ddfa0d1..f7f3a51 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1246,18 +1246,20 @@ EXPORT_SYMBOL(drm_atomic_helper_commit);
  * Returns:
  * 0 on success, negative error code on failure.
  */
+
 int drm_atomic_helper_prepare_planes(struct drm_device *dev,
 struct drm_atomic_state *state)
 {
-   int nplanes = dev->mode_config.num_total_plane;
+   struct drm_plane *plane;
+   struct drm_plane_state *plane_state;
int ret, i;

-   for (i = 0; i < nplanes; i++) {
+   for_each_plane_in_state(state, plane, plane_state, i) {
const struct drm_plane_helper_funcs *funcs;
-   struct drm_plane *plane = state->planes[i];
-   struct drm_plane_state *plane_state = state->plane_states[i];

-   if (!plane)
+   plane->prepared = false;
+
+   if (plane->state->fb == plane_state->fb)
continue;

funcs = plane->helper_private;
@@ -1267,24 +1269,22 @@ int drm_atomic_helper_prepare_planes(struct drm_device 
*dev,
if (ret)
goto fail;
}
+   plane->prepared = true;
}

return 0;

 fail:
-   for (i--; i >= 0; i--) {
+   for_each_plane_in_state(state, plane, plane_state, i) {
const struct drm_plane_helper_funcs *funcs;
-   struct drm_plane *plane = state->planes[i];
-   struct drm_plane_state *plane_state = state->plane_states[i];

-   if (!plane)
+   if (!plane->prepared)
continue;

funcs = plane->helper_private;

if (funcs->cleanup_fb)
funcs->cleanup_fb(plane, plane_state);
-
}

return ret;
@@ -1527,6 +1527,9 @@ void drm_atomic_helper_cleanup_planes(struct drm_device 
*dev,
for_each_plane_in_state(old_state, plane, plane_state, i) {
const struct drm_plane_helper_funcs *funcs;

+   if (!plane->prepared)
+   continue;
+
funcs = plane->helper_private;

if (funcs->cleanup_fb)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index d1559cd..08b2033 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1531,6 +1531,7 @@ struct drm_plane {
uint32_t *format_types;
unsigned int format_count;
bool format_default;
+   bool prepared;

struct drm_crtc *crtc;
struct drm_framebuffer *fb;
-- 
2.8.1

[PATCH] drm/i915: cleanup_plane_fb: also drop reference to current state wait_req

2016-07-31 Thread Keith Packard 
There are two paths into intel_cleanup_plane_fb, the normal completion
path and the failure path.

In the failure case, intel_cleanup_plane_fb is called before
drm_atomic_helper_swap_state, so any wait_req reference made in
intel_prepare_plane_fb will be in old_intel_state->wait_req.

In the normal completion path, drm_atomic_helper_swap_state has
already been called, so the plane state holding the just-used wait_req
will not be in old_intel_state->wait_req, rather it will be in the
state associated with the plane itself.

Clearing this reference ensures that the wait_req will be freed as
soon as it the related mode setting operation is complete, rather than
waiting for some future mode setting operation to eventually
dereference it.

The existing dereference of old_intel_state->wait_req is still
required as that will hold the wait_req when the mode setting
operation fails.

cc: Daniel Vetter 
cc: David Airlie 
cc: intel-gfx at lists.freedesktop.org
cc: dri-devel at lists.freedesktop.org
Signed-off-by: Keith Packard 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3074c56..dbabaf3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13924,6 +13924,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
struct drm_device *dev = plane->dev;
struct intel_plane *intel_plane = to_intel_plane(plane);
struct intel_plane_state *old_intel_state;
+   struct intel_plane_state *intel_state = 
to_intel_plane_state(plane->state);
struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);

@@ -13941,6 +13942,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
(obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);

+   i915_gem_request_assign(_state->wait_req, NULL);
i915_gem_request_assign(_intel_state->wait_req, NULL);
 }

-- 
2.8.1