[Bug 109138] [KBL-G][GL-CTS]KHR-GL31.texture_size_promotion.functional test failed
https://bugs.freedesktop.org/show_bug.cgi?id=109138 Hai changed: What|Removed |Added Hardware|Other |x86-64 (AMD64) -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 106175] amdgpu.dc=1 shows performance issues with Xorg compositors when moving windows
https://bugs.freedesktop.org/show_bug.cgi?id=106175 --- Comment #79 from bmil...@gmail.com --- any chance to backport the last version of the patch to 4.20? -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 17/18] drm/mediatek: add ovl0/ovl0_2l usecase
On Mon, Dec 24, 2018 at 6:52 PM Yongqiang Niu
wrote:
>
> This patch add ovl0/ovl0_2l usecase
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 38
> ++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index a5af4be..25cf063 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -283,6 +283,15 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
> + enum mtk_ddp_comp_id prev = DDP_COMPONENT_ID_MAX;
> +
> + if (i > 0) {
> + struct mtk_ddp_comp *comp_prev;
> +
> + comp_prev = mtk_crtc->ddp_comp[i - 1];
> + prev = comp_prev->id;
Just
if (i > 0)
prev = mtk_crtc->ddp_comp[i - 1]->id;
else
prev = DDP_COMPONENT_ID_MAX;
> + }
> + mtk_ddp_comp_connect(comp, prev);
>
> mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
> mtk_ddp_comp_start(comp);
> @@ -292,10 +301,19 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> for (i = 0; i < mtk_crtc->layer_nr; i++) {
> struct drm_plane *plane = _crtc->planes[i];
> struct mtk_plane_state *plane_state;
> + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
> + unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp);
> + unsigned int local_layer = 0;
No need to init to 0.
>
> plane_state = to_mtk_plane_state(plane->state);
> - mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i,
> - plane_state);
> +
> + if (i >= comp_layer_nr) {
> + comp = mtk_crtc->ddp_comp[1];
> + local_layer = i - comp_layer_nr;
> + } else {
> + local_layer = i;
> + }
> + mtk_ddp_comp_layer_config(comp, local_layer, plane_state);
> }
>
> return 0;
> @@ -340,6 +358,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> struct mtk_crtc_state *state =
> to_mtk_crtc_state(mtk_crtc->base.state);
> struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
> unsigned int i;
> + unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp);
> + unsigned int local_layer = 0;
ditto, don't init to 0.
>
> /*
> * TODO: instead of updating the registers here, we should prepare
> @@ -362,7 +382,15 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> plane_state = to_mtk_plane_state(plane->state);
>
> if (plane_state->pending.config) {
> - mtk_ddp_comp_layer_config(comp, i,
> plane_state);
> + if (i >= comp_layer_nr) {
> + comp = mtk_crtc->ddp_comp[1];
> + local_layer = i - comp_layer_nr;
> + } else {
> + local_layer = i;
> + }
> +
> + mtk_ddp_comp_layer_config(comp, local_layer,
> + plane_state);
> plane_state->pending.config = false;
> }
> }
> @@ -604,6 +632,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> }
>
> mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
> + if (mtk_crtc->ddp_comp_nr > 1 &&
> + mtk_ddp_comp_get_type(mtk_crtc->ddp_comp[1]->id) == MTK_DISP_OVL)
> + mtk_crtc->layer_nr +=
> + mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[1]);
> mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr,
> sizeof(struct drm_plane),
> GFP_KERNEL);
> --
> 1.8.1.1.dirty
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Re: [PATCH 16/18] drm/mediatek: add function mtk_ddp_comp_get_type
On Mon, Dec 24, 2018 at 6:53 PM Yongqiang Niu
wrote:
>
> This patch add function mtk_ddp_comp_get_type
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 1c0f9cc..71b565c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -350,6 +350,16 @@ int mtk_ddp_comp_get_id(struct device_node *node,
> return -EINVAL;
> }
>
> +enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id)
> +{
> + enum mtk_ddp_comp_type comp_type = MTK_DDP_COMP_TYPE_MAX;
> +
> + if (comp_id < DDP_COMPONENT_ID_MAX)
> + comp_type = mtk_ddp_matches[comp_id].type;
return mtk_ddp_matches[comp_id].type
> +
> + return comp_type;
return MTK_DDP_COMP_TYPE_MAX
> +}
> +
> int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
> const struct mtk_ddp_comp_funcs *funcs)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index b908172..599e293 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -198,5 +198,6 @@ void mtk_ddp_write_mask(unsigned int value,
> struct mtk_ddp_comp *comp,
> unsigned int offset,
> unsigned int mask);
> +enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
>
> #endif /* MTK_DRM_DDP_COMP_H */
> --
> 1.8.1.1.dirty
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Re: [PATCH 10/18] drm/mediatek: add gmc_bits for ovl private data
On Mon, Dec 24, 2018 at 6:53 PM Yongqiang Niu
wrote:
>
> This patch add gmc_bits for ovl private data
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +--
> 1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 28d1911..afb313c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -39,7 +39,9 @@
> #define DISP_REG_OVL_ADDR_MT8173 0x0f40
> #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 *
> (n))
>
> -#defineOVL_RDMA_MEM_GMC0x40402020
> +#define GMC_THRESHOLD_BITS 16
> +#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
> +#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
>
> #define OVL_CON_BYTE_SWAP BIT(24)
> #define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
> @@ -57,6 +59,7 @@
>
> struct mtk_disp_ovl_data {
> unsigned int addr;
> + unsigned int gmc_bits;
> bool fmt_rgb565_is_0;
> };
>
> @@ -140,9 +143,23 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp
> *comp)
> static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
> {
> unsigned int reg;
> + unsigned int gmc_thrshd_l;
> + unsigned int gmc_thrshd_h;
> + unsigned int gmc_value;
> + struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
>
> writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
> - writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
> +
> + gmc_thrshd_l = GMC_THRESHOLD_LOW >>
> + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
> + gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
> + (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
> + if (ovl->data->gmc_bits == 10)
> + gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
I don't really get what this does, but is it intentional that you
don't use gmc_thrshd_l here?
Also, if you only ever use 8 or 10 bits gmc, maybe it's easier to
hard-code the 2 values?
if (ovl->data->gmc_bits == 10)
gmc_value = OVL_RDMA_MEM_GMC_10BIT;
else
gmc_value = OVL_RDMA_MEM_GMC_8BIT; //0x40402020
> + else
> + gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
> + gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
> + writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
>
> reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
> reg = reg | BIT(idx);
> @@ -324,11 +341,13 @@ static int mtk_disp_ovl_remove(struct platform_device
> *pdev)
>
> static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT2701,
> + .gmc_bits = 8,
> .fmt_rgb565_is_0 = false,
> };
>
> static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
> .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 8,
> .fmt_rgb565_is_0 = true,
> };
>
> --
> 1.8.1.1.dirty
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Re: [PATCH 03/18] drm/mediatek: redefine mtk_ddp_sout_sel
On Mon, Dec 24, 2018 at 6:52 PM Yongqiang Niu
wrote:
>
> This patch redefine mtk_ddp_sout_sel
Can you describe a bit more why you are making this change?
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 32
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index adb37e4..592f852 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -405,21 +405,27 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id
> cur,
> return value;
> }
>
> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> -enum mtk_ddp_comp_id cur,
> -enum mtk_ddp_comp_id next)
> +static unsigned int mtk_ddp_sout_sel(void __iomem *config_regs,
You don't use config_regs anymore, drop it.
> +enum mtk_ddp_comp_id cur,
> +enum mtk_ddp_comp_id next,
> +unsigned int *addr)
> {
> + unsigned int value;
> +
> if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> + *addr = DISP_REG_CONFIG_OUT_SEL;
> + value = BLS_TO_DSI_RDMA1_TO_DPI1;
You can directly return BLS_TO_DSI_RDMA1_TO_DPI1.
> } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> - config_regs + DISP_REG_CONFIG_OUT_SEL);
> - writel_relaxed(DSI_SEL_IN_RDMA,
> - config_regs + DISP_REG_CONFIG_DSI_SEL);
> - writel_relaxed(DPI_SEL_IN_BLS,
> - config_regs + DISP_REG_CONFIG_DPI_SEL);
> + *addr = DISP_REG_CONFIG_OUT_SEL;
> + value = BLS_TO_DPI_RDMA1_TO_DSI;
I (kind of) understand the change above, as you still end up writing
BLS_TO_DSI_RDMA1_TO_DPI1 in DISP_REG_CONFIG_OUT_SEL.
This changes the behaviour, as now you only write
BLS_TO_DPI_RDMA1_TO_DSI to DISP_REG_CONFIG_OUT_SEL, but the previous
revision of the code would also write to DISP_REG_CONFIG_DSI_SEL and
DISP_REG_CONFIG_DPI_SEL. Why?
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> + *addr = DISP_REG_CONFIG_DSI_SEL;
> + value = DSI_SEL_IN_RDMA;
> + } else {
> + value = 0;
> }
> +
> + return value;
> }
>
> void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> @@ -434,7 +440,9 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> writel_relaxed(reg, config_regs + addr);
> }
>
> - mtk_ddp_sout_sel(config_regs, cur, next);
> + value = mtk_ddp_sout_sel(cur, next, );
> + if (value)
> + writel_relaxed(value, config_regs + addr);
Why this change? I don't see mtk_ddp_sout_sel being used later in the
series, so I'm not sure why we don't directly write the value into the
register.
> value = mtk_ddp_sel_in(cur, next, );
> if (value) {
> --
> 1.8.1.1.dirty
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[Bug 109140] [KBL-G][GL] KHR-GL43.compute_shader.max test failed
https://bugs.freedesktop.org/show_bug.cgi?id=109140 Bug ID: 109140 Summary: [KBL-G][GL] KHR-GL43.compute_shader.max test failed Product: DRI Version: XOrg git Hardware: Other OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: hai@intel.com When Use Kaby Lake-g(AMD Vega M GPU) to do the OpenGL CTS test, the case " KHR-GL43.compute_shader.max" will fail. KHR-GL44.compute_shader.max and KHR-GL45.compute_shader.max also failed Following is the environtment PlatformKabyLake-G CPU Intel (R) Core (TM) i7-8809G CPU @3.10GHz GPU AMD(Radeon RX Vega M GH Graphics); Memory 16G OS Ubutu18.04 Kernel 4.19.0 Mesa: mesa 18.3.0 (https://mesa.freedesktop.org/archive/mesa-18.3.0.tar.gz) VK-GL-CTS version https://github.com/KhronosGroup/VK-GL-CTS commit 54e546a1a0a6fa412ea4c3e3081bbc9518928a6e How to reproduce run command: $ ./glcts -n KHR-GL43.compute_shader.max Writing test log into TestResults.qpa dEQP Core git-54e546a1a0a6fa412ea4c3e3081bbc9518928a6e (0x54e546a1) starting.. target implementation = 'Default' Test case 'KHR-GL43.compute_shader.max'.. Fail (Fail) DONE! Test run totals: Passed: 0/1 (0.0%) Failed: 1/1 (100.0%) Not supported: 0/1 (0.0%) Warnings: 0/1 (0.0%) -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 107978] [amdgpu] Switching to tty fails with DisplayPort 1.2 monitor going to sleep (REG_WAIT timeout / dce110_stream_encoder_dp_blank)
https://bugs.freedesktop.org/show_bug.cgi?id=107978 --- Comment #37 from Shmerl --- I wonder if it's some kind of distro specific race condition that happens during boot. Happens to me in Debian testing (you can try reproducing it there). -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 109135] R9 390 hangs at boot with DPM/DC enabled for kernels 4.19.x and above, says KMS not supported
https://bugs.freedesktop.org/show_bug.cgi?id=109135 toma678 changed: What|Removed |Added CC||gta...@gmail.com --- Comment #3 from toma678 --- Created attachment 142880 --> https://bugs.freedesktop.org/attachment.cgi?id=142880=edit Kernel Log From Crash on R9 390 > 4.19 Added kernel log from crash. Error affects 4.19 and 4.20. Runs fine with same settings on 4.18. Line #925 looks like first error, with further errors on #943 and #944 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 0/9] Use vm_insert_range
Having discussed with Matthew offlist, I think we've come to the
following conclusion - there's a number of drivers that buggily
ignore vm_pgoff.
So, what I proposed is:
static int __vm_insert_range(struct vm_struct *vma, struct page *pages,
size_t num, unsigned long offset)
{
unsigned long count = vma_pages(vma);
unsigned long uaddr = vma->vm_start;
int ret;
/* Fail if the user requested offset is beyond the end of the object */
if (offset > num)
return -ENXIO;
/* Fail if the user requested size exceeds available object size */
if (count > num - offset)
return -ENXIO;
/* Never exceed the number of pages that the user requested */
for (i = 0; i < count; i++) {
ret = vm_insert_page(vma, uaddr, pages[offset + i]);
if (ret < 0)
return ret;
uaddr += PAGE_SIZE;
}
return 0;
}
/*
* Maps an object consisting of `num' `pages', catering for the user's
* requested vm_pgoff
*/
int vm_insert_range(struct vm_struct *vma, struct page *pages, size_t num)
{
return __vm_insert_range(vma, pages, num, vma->vm_pgoff);
}
/*
* Maps a set of pages, always starting at page[0]
*/
int vm_insert_range_buggy(struct vm_struct *vma, struct page *pages, size_t num)
{
return __vm_insert_range(vma, pages, num, 0);
}
With this, drivers such as iommu/dma-iommu.c can be converted thusly:
int iommu_dma_mmap(struct page **pages, size_t size, struct vm_area_struct
*vma+)
{
- unsigned long uaddr = vma->vm_start;
- unsigned int i, count = PAGE_ALIGN(size) >> PAGE_SHIFT;
- int ret = -ENXIO;
-
- for (i = vma->vm_pgoff; i < count && uaddr < vma->vm_end; i++) {
- ret = vm_insert_page(vma, uaddr, pages[i]);
- if (ret)
- break;
- uaddr += PAGE_SIZE;
- }
- return ret;
+ return vm_insert_range(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
}
and drivers such as firewire/core-iso.c:
int fw_iso_buffer_map_vma(struct fw_iso_buffer *buffer,
struct vm_area_struct *vma)
{
- unsigned long uaddr;
- int i, err;
-
- uaddr = vma->vm_start;
- for (i = 0; i < buffer->page_count; i++) {
- err = vm_insert_page(vma, uaddr, buffer->pages[i]);
- if (err)
- return err;
-
- uaddr += PAGE_SIZE;
- }
-
- return 0;
+ return vm_insert_range_buggy(vma, buffer->pages, buffer->page_count);
}
and this gives us something to grep for to find these buggy drivers.
Now, this may not look exactly equivalent, but if you look at
fw_device_op_mmap(), buffer->page_count is basically vma_pages(vma)
at this point, which means this should be equivalent.
We _could_ then at a later date "fix" these drivers to behave according
to the normal vm_pgoff offsetting simply by removing the _buggy suffix
on the function name... and if that causes regressions, it gives us an
easy way to revert (as long as vm_insert_range_buggy() remains
available.)
In the case of firewire/core-iso.c, it currently ignores the mmap offset
entirely, so making the above suggested change would be tantamount to
causing it to return -ENXIO for any non-zero mmap offset.
IMHO, this approach is way simpler, and easier to get it correct at
each call site, rather than the current approach which seems to be
error-prone.
--
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Re: [PATCH] drm/fb-helper: fix leaks in error path of drm_fb_helper_fbdev_setup
On Mon, Dec 24, 2018 at 03:52:55PM +0100, Noralf Trønnes wrote:
>
>
> Den 24.12.2018 00.10, skrev Peter Wu:
> > On Sun, Dec 23, 2018 at 02:55:52PM +0100, Noralf Trønnes wrote:
> > >
> > >
> > > Den 23.12.2018 01.55, skrev Peter Wu:
> > > > After drm_fb_helper_fbdev_setup calls drm_fb_helper_init,
> > > > "dev->fb_helper" will be initialized (and thus drm_fb_helper_fini will
> > > > have some effect). After that, drm_fb_helper_initial_config is called
> > > > which may call the "fb_probe" driver callback.
> > > >
> > > > This driver callback may call drm_fb_helper_defio_init (as is done by
> > > > drm_fb_helper_generic_probe) or set a framebuffer (as is done by bochs)
> > > > as documented. These are normally cleaned up on exit by
> > > > drm_fb_helper_fbdev_teardown which also calls drm_fb_helper_fini.
> > > >
> > > > If an error occurs after "fb_probe", but before setup is complete, then
> > > > calling just drm_fb_helper_fini will leak resources. This was triggered
> > > > by df2052cc922 ("bochs: convert to drm_fb_helper_fbdev_setup/teardown"):
> > > >
> > > > [ 50.008030] bochsdrmfb: enable CONFIG_FB_LITTLE_ENDIAN to
> > > > support this framebuffer
> > > > [ 50.009436] bochs-drm :00:02.0:
> > > > [drm:drm_fb_helper_fbdev_setup] *ERROR* fbdev: Failed to set
> > > > configuration (ret=-38)
> > > > [ 50.011456] [drm] Initialized bochs-drm 1.0.0 20130925 for
> > > > :00:02.0 on minor 2
> > > > [ 50.013604] WARNING: CPU: 1 PID: 1 at
> > > > drivers/gpu/drm/drm_mode_config.c:477
> > > > drm_mode_config_cleanup+0x280/0x2a0
> > > > [ 50.016175] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G
> > > > T 4.20.0-rc7 #1
> > > > [ 50.017732] EIP: drm_mode_config_cleanup+0x280/0x2a0
> > > > ...
> > > > [ 50.023155] Call Trace:
> > > > [ 50.023155] ? bochs_kms_fini+0x1e/0x30
> > > > [ 50.023155] ? bochs_unload+0x18/0x40
> > > >
> > > > This can be reproduced with QEMU and CONFIG_FB_LITTLE_ENDIAN=n.
> > > >
> > > > Link: https://lkml.kernel.org/r/20181221083226.GI23332@shao2-debian
> > > > Link: https://lkml.kernel.org/r/20181223004315.GA11455@al
> > > > Fixes: 8741216396b2 ("drm/fb-helper: Add
> > > > drm_fb_helper_fbdev_setup/teardown()")
> > > > Reported-by: kernel test robot
> > > > Cc: Noralf Trønnes
> > > > Signed-off-by: Peter Wu
> > > > ---
> > > >drivers/gpu/drm/drm_fb_helper.c | 2 +-
> > > >1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_fb_helper.c
> > > > b/drivers/gpu/drm/drm_fb_helper.c
> > > > index 9d64f874f965..432e0f3b9267 100644
> > > > --- a/drivers/gpu/drm/drm_fb_helper.c
> > > > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > > > @@ -2860,7 +2860,7 @@ int drm_fb_helper_fbdev_setup(struct drm_device
> > > > *dev,
> > > > return 0;
> > > >err_drm_fb_helper_fini:
> > > > - drm_fb_helper_fini(fb_helper);
> > > > + drm_fb_helper_fbdev_teardown(dev);
> > >
> > > This change will break the error path for drm_fbdev_generic_setup()
> > > because drm_fb_helper_generic_probe() cleans up on error but doesn't
> > > clear drm_fb_helper->fb resulting in a double drm_framebuffer_remove().
> >
> > This should probably considered a bug of drm_fb_helper_generic_probe.
> > Ownership of fb_helper should remain with the caller. The caller can
> > detect an error and act accordingly.
> >
> > > My assumption has been that the drm_fb_helper_funcs->fb_probe callback
> > > cleans up its resources on error. Clearly this is not the case for bochs,
> > > so
> > > my take on this is that bochsfb_create() needs to clean up on error.
> >
> > That assumption still holds for bochs. The problem is this sequence:
> > - drm_fb_helper_fbdev_setup is called.
> > - fb_probe succeeds (this is crucial).
> > - register_framebuffer fails.
> > - error path of setup is triggered.
> >
> > As fb_helper is fully setup by drivers, the drm_fb_helper core should
> > fully deallocate it again on the error path or else a leak occurs.
> >
> > > Gerd has a patchset that switches bochs over to the generic fbdev
> > > emulation, but ofc that doesn't help with 4.20:
> > > https://patchwork.freedesktop.org/series/54269/
> >
> > And that does not help with other users of the drm_fb_helper who use
> > functions like drm_fb_helper_defio_init. They will likely run in the
> > same problem.
> >
> > I don't have a way to test tinydrm or other drivers, but if you force
> > register_framebuffer to fail, you should be able to reproduce the
> > problem with drm_fb_helper_generic_probe.
> >
>
> Now I understand. I have looked at the drivers that use drm_fb_helper
> and no one seem to handle the case where register_framebuffer() is
> failing.
>
> Here's what drivers do when drm_fb_helper_initial_config() fails:
>
> Doesn't check:
> amdgpu
> virtio
>
> Calls drm_fb_helper_fini():
> armada
> ast
> exynos
> gma500
> hisilicon
> mgag200
> msm
> nouveau
> omap
> radeon
>
Re: [PATCH] drm/fb-helper: fix leaks in error path of drm_fb_helper_fbdev_setup
Den 24.12.2018 00.10, skrev Peter Wu:
On Sun, Dec 23, 2018 at 02:55:52PM +0100, Noralf Trønnes wrote:
Den 23.12.2018 01.55, skrev Peter Wu:
After drm_fb_helper_fbdev_setup calls drm_fb_helper_init,
"dev->fb_helper" will be initialized (and thus drm_fb_helper_fini will
have some effect). After that, drm_fb_helper_initial_config is called
which may call the "fb_probe" driver callback.
This driver callback may call drm_fb_helper_defio_init (as is done by
drm_fb_helper_generic_probe) or set a framebuffer (as is done by bochs)
as documented. These are normally cleaned up on exit by
drm_fb_helper_fbdev_teardown which also calls drm_fb_helper_fini.
If an error occurs after "fb_probe", but before setup is complete, then
calling just drm_fb_helper_fini will leak resources. This was triggered
by df2052cc922 ("bochs: convert to drm_fb_helper_fbdev_setup/teardown"):
[ 50.008030] bochsdrmfb: enable CONFIG_FB_LITTLE_ENDIAN to support this
framebuffer
[ 50.009436] bochs-drm :00:02.0: [drm:drm_fb_helper_fbdev_setup]
*ERROR* fbdev: Failed to set configuration (ret=-38)
[ 50.011456] [drm] Initialized bochs-drm 1.0.0 20130925 for
:00:02.0 on minor 2
[ 50.013604] WARNING: CPU: 1 PID: 1 at
drivers/gpu/drm/drm_mode_config.c:477 drm_mode_config_cleanup+0x280/0x2a0
[ 50.016175] CPU: 1 PID: 1 Comm: swapper/0 Tainted: GT
4.20.0-rc7 #1
[ 50.017732] EIP: drm_mode_config_cleanup+0x280/0x2a0
...
[ 50.023155] Call Trace:
[ 50.023155] ? bochs_kms_fini+0x1e/0x30
[ 50.023155] ? bochs_unload+0x18/0x40
This can be reproduced with QEMU and CONFIG_FB_LITTLE_ENDIAN=n.
Link: https://lkml.kernel.org/r/20181221083226.GI23332@shao2-debian
Link: https://lkml.kernel.org/r/20181223004315.GA11455@al
Fixes: 8741216396b2 ("drm/fb-helper: Add drm_fb_helper_fbdev_setup/teardown()")
Reported-by: kernel test robot
Cc: Noralf Trønnes
Signed-off-by: Peter Wu
---
drivers/gpu/drm/drm_fb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 9d64f874f965..432e0f3b9267 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2860,7 +2860,7 @@ int drm_fb_helper_fbdev_setup(struct drm_device *dev,
return 0;
err_drm_fb_helper_fini:
- drm_fb_helper_fini(fb_helper);
+ drm_fb_helper_fbdev_teardown(dev);
This change will break the error path for drm_fbdev_generic_setup()
because drm_fb_helper_generic_probe() cleans up on error but doesn't
clear drm_fb_helper->fb resulting in a double drm_framebuffer_remove().
This should probably considered a bug of drm_fb_helper_generic_probe.
Ownership of fb_helper should remain with the caller. The caller can
detect an error and act accordingly.
My assumption has been that the drm_fb_helper_funcs->fb_probe callback
cleans up its resources on error. Clearly this is not the case for bochs, so
my take on this is that bochsfb_create() needs to clean up on error.
That assumption still holds for bochs. The problem is this sequence:
- drm_fb_helper_fbdev_setup is called.
- fb_probe succeeds (this is crucial).
- register_framebuffer fails.
- error path of setup is triggered.
As fb_helper is fully setup by drivers, the drm_fb_helper core should
fully deallocate it again on the error path or else a leak occurs.
Gerd has a patchset that switches bochs over to the generic fbdev
emulation, but ofc that doesn't help with 4.20:
https://patchwork.freedesktop.org/series/54269/
And that does not help with other users of the drm_fb_helper who use
functions like drm_fb_helper_defio_init. They will likely run in the
same problem.
I don't have a way to test tinydrm or other drivers, but if you force
register_framebuffer to fail, you should be able to reproduce the
problem with drm_fb_helper_generic_probe.
Now I understand. I have looked at the drivers that use drm_fb_helper
and no one seem to handle the case where register_framebuffer() is
failing.
Here's what drivers do when drm_fb_helper_initial_config() fails:
Doesn't check:
amdgpu
virtio
Calls drm_fb_helper_fini():
armada
ast
exynos
gma500
hisilicon
mgag200
msm
nouveau
omap
radeon
rockchip
tegra
udl
bochs - Uses drm_fb_helper_fbdev_setup()
qxl - Uses drm_fb_helper_fbdev_setup()
vboxvideo - Uses drm_fb_helper_fbdev_setup()
Might clean up, not sure:
cirrus
Looks suspicious:
i915
I looked at bochs before it switched to drm_fb_helper_fbdev_setup() and
it also just called drm_fb_helper_fini().
It looks like you've uncovered something no one has though about (or
not implemented at least).
It's not just the framebuffer that's not destroyed, the buffer object
is also leaked. drm_mode_config_cleanup() yells about the framebuffer
(and frees it), but says nothing about the buffer object. It might be
that it can't even be made to detect that since some drivers do special
stuff for the fbdev buffer.
I'll pick up on
[Bug 102322] System crashes after "[drm] IP block:gmc_v8_0 is hung!" / [drm] IP block:sdma_v3_0 is hung!
https://bugs.freedesktop.org/show_bug.cgi?id=102322 --- Comment #75 from dwagner --- Audio is unrelated to this bug. In my reproduction scripts, I do not output any audio at all. The video-at-3-fps replay that I use for reproduction seems to just trigger a certain pattern of the memory- and shader-clocks getting increased/decreased (with dynamic power management being enabled) that makes the occurrence of this bug likely. Any other GPU-usage pattern that triggers a lot of memory/shader clock changes seems to also increase the crash likelihood - manual use of some web-browser where GPU load spikes are caused a few times per second seems to be also a scenario where this bug is triggered now and then. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 202043] amdgpu: Vega 56 SCLK drops to 700 Mhz when undervolting
https://bugzilla.kernel.org/show_bug.cgi?id=202043 fin4...@hotmail.com changed: What|Removed |Added CC||fin4...@hotmail.com --- Comment #2 from fin4...@hotmail.com --- Have amdgpu.ppfeaturemask=0x in the kernel command line. -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 9/9] MAINTAINERS: Add maintainer for arm komeda driver
On Mon, Dec 24, 2018 at 1:33 PM Liviu Dudau wrote: > > On Fri, Dec 21, 2018 at 10:01:06AM +, james qian wang (Arm Technology > China) wrote: > > v2: Adjusted the position of KOMEDA by alphabetical order > > > > Signed-off-by: James (Qian) Wang > > Acked-by: Liviu Dudau > > Best regards, > Liviu > > > --- > > MAINTAINERS | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 254b7b267731..e48c2e5fd29f 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1124,6 +1124,15 @@ S: Supported > > F: drivers/gpu/drm/arm/hdlcd_* > > F: Documentation/devicetree/bindings/display/arm,hdlcd.txt > > > > +ARM KOMEDA DRM-KMS DRIVER > > +M: James (Qian) Wang > > +M: Mali DP Maintainers > > +S: Supported > > +F: drivers/gpu/drm/arm/display/include/ > > +F: drivers/gpu/drm/arm/display/komeda/ > > +F: Documentation/devicetree/bindings/display/arm/arm,komeda.txt > > +F: Documentation/gpu/komeda-kms.rst Mentioning the git tree would be good. And I guess you'll do some kind of group maintainership? Probably still good if you send out a dedicated/topic pull request for this new driver, but from then on it's all in the same git repo. -Daniel > > + > > ARM MALI-DP DRM DRIVER > > M: Liviu Dudau > > M: Brian Starkey > > -- > > 2.17.1 > > > > -- > > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --- > ¯\_(ツ)_/¯ -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 102322] System crashes after "[drm] IP block:gmc_v8_0 is hung!" / [drm] IP block:sdma_v3_0 is hung!
https://bugs.freedesktop.org/show_bug.cgi?id=102322 --- Comment #74 from fin4...@hotmail.com --- The Firefox browser requires the pulseaudio driver. Use the Alsa audio and the chrome/chromium browser. Disable hardware acceleration in browser settings. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 8/9] drm/doc: Add initial komeda driver documentation
On Fri, Dec 21, 2018 at 10:00:49AM +, james qian wang (Arm Technology China) wrote: > v2: Some editing changes according to Randy Dunlap's comments > > Signed-off-by: James (Qian) Wang Reviewed-by: Liviu Dudau > --- > Documentation/gpu/drivers.rst| 1 + > Documentation/gpu/komeda-kms.rst | 488 +++ > 2 files changed, 489 insertions(+) > create mode 100644 Documentation/gpu/komeda-kms.rst > > diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst > index 7c1672118a73..978e6da9bbff 100644 > --- a/Documentation/gpu/drivers.rst > +++ b/Documentation/gpu/drivers.rst > @@ -17,6 +17,7 @@ GPU Driver Documentation > vkms > bridge/dw-hdmi > xen-front > + komeda-kms > > .. only:: subproject and html > > diff --git a/Documentation/gpu/komeda-kms.rst > b/Documentation/gpu/komeda-kms.rst > new file mode 100644 > index ..b08da1cffecc > --- /dev/null > +++ b/Documentation/gpu/komeda-kms.rst > @@ -0,0 +1,488 @@ > +.. SPDX-License-Identifier: GPL-2.0 > + > +== > + drm/komeda Arm display driver > +== > + > +The drm/komeda driver supports the Arm display processor D71 and later > products, > +this document gives a brief overview of driver design: how it works and why > +design it like that. > + > +Overview of D71 like display IPs > + > + > +From D71, Arm display IP begins to adopt a flexible and modularized > +architecture. A display pipeline is made up of multiple individual and > +functional pipeline stages called components, and every component has some > +specific capabilities that can give the flowed pipeline pixel data a > +particular processing. > + > +Typical D71 components: > + > +Layer > +- > +Layer is the first pipeline stage, which prepares the pixel data for the next > +stage. It fetches the pixel from memory, decodes it if it's AFBC, rotates the > +source image, unpacks or converts YUV pixels to the device internal RGB > pixels, > +then adjusts the color_space of pixels if needed. > + > +Scaler > +-- > +As its name suggests, scaler takes responsibility for scaling, and D71 also > +supports image enhancements by scaler. > +The usage of scaler is very flexible and can be connected to layer output > +for layer scaling, or connected to compositor and scale the whole display > +frame and then feed the output data into wb_layer which will then write it > +into memory. > + > +Compositor (compiz) > +--- > +Compositor blends multiple layers or pixel data flows into one single display > +frame. its output frame can be fed into post image processor for showing it > on > +the monitor or fed into wb_layer and written to memory at the same time. > +user can also insert a scaler between compositor and wb_layer to down scale > +the display frame first and and then write to memory. > + > +Writeback Layer (wb_layer) > +-- > +Writeback layer does the opposite things of Layer, which connects to compiz > +and writes the composition result to memory. > + > +Post image processor (improc) > +- > +Post image processor adjusts frame data like gamma and color space to fit the > +requirements of the monitor. > + > +Timing controller (timing_ctrlr) > + > +Final stage of display pipeline, Timing controller is not for the pixel > +handling, but only for controlling the display timing. > + > +Merger > +-- > +D71 scaler mostly only has the half horizontal input/output capabilities > +compared with Layer, like if Layer supports 4K input size, the scaler only > can > +support 2K input/output in the same time. To achieve the ful frame scaling, > D71 > +introduces Layer Split, which splits the whole image to two half parts and > feeds > +them to two Layers A and B, and does the scaling independently. After scaling > +the result need to be fed to merger to merge two part images together, and > then > +output merged result to compiz. > + > +Splitter > + > +Similar to Layer Split, but Splitter is used for writeback, which splits the > +compiz result to two parts and then feed them to two scalers. > + > +Possible D71 Pipeline usage > +=== > + > +Benefitting from the modularized architecture, D71 pipelines can be easily > +adjusted to fit different usages. And D71 has two pipelines, which support > two > +types of working mode: > + > +- Dual display mode > +Two pipelines work independently and separately to drive two display > outputs. > + > +- Single display mode > +Two pipelines work together to drive only one display output. > + > +On this mode, pipeline_B doesn't work indenpendently, but outputs its > +composition result into pipeline_A, and its pixel timing also derived > from > +pipeline_A.timing_ctrlr. The pipeline_B works just like a "slave" of > +pipeline_A(master) > + > +Single
Re: [PATCH v3 9/9] MAINTAINERS: Add maintainer for arm komeda driver
On Fri, Dec 21, 2018 at 10:01:06AM +, james qian wang (Arm Technology China) wrote: > v2: Adjusted the position of KOMEDA by alphabetical order > > Signed-off-by: James (Qian) Wang Acked-by: Liviu Dudau Best regards, Liviu > --- > MAINTAINERS | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 254b7b267731..e48c2e5fd29f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1124,6 +1124,15 @@ S: Supported > F: drivers/gpu/drm/arm/hdlcd_* > F: Documentation/devicetree/bindings/display/arm,hdlcd.txt > > +ARM KOMEDA DRM-KMS DRIVER > +M: James (Qian) Wang > +M: Mali DP Maintainers > +S: Supported > +F: drivers/gpu/drm/arm/display/include/ > +F: drivers/gpu/drm/arm/display/komeda/ > +F: Documentation/devicetree/bindings/display/arm/arm,komeda.txt > +F: Documentation/gpu/komeda-kms.rst > + > ARM MALI-DP DRM DRIVER > M: Liviu Dudau > M: Brian Starkey > -- > 2.17.1 > -- | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --- ¯\_(ツ)_/¯ ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 7/9] drm/komeda: Attach komeda_dev to DRM-KMS
On Fri, Dec 21, 2018 at 10:00:33AM +, james qian wang (Arm Technology
China) wrote:
> Add komeda_kms abstracton to attach komeda_dev to DRM-KMS
> CRTC: according to the komeda_pipeline
> PLANE: according to komeda_layer (layer input pipeline)
> PRIVATE_OBJS: komeda_pipeline/component all will be treat as private_objs
>
> komeda_kms is for connecting DRM-KMS and komeda_dev, like reporting the
> kms object properties according to the komeda_dev, and pass/convert KMS's
> requirement to komeda_dev.
>
> Changes in v3:
> - Fixed style problem found by checkpatch.pl --strict.
>
> Changes in v2:
> - Unified abbreviation of "pipeline" to "pipe".
>
> Signed-off-by: James (Qian) Wang
> ---
> drivers/gpu/drm/arm/display/komeda/Makefile | 6 +-
> .../gpu/drm/arm/display/komeda/komeda_crtc.c | 106 +++
> .../gpu/drm/arm/display/komeda/komeda_drv.c | 19 +-
> .../gpu/drm/arm/display/komeda/komeda_kms.c | 169 ++
> .../gpu/drm/arm/display/komeda/komeda_kms.h | 113
> .../drm/arm/display/komeda/komeda_pipeline.h | 3 +
> .../gpu/drm/arm/display/komeda/komeda_plane.c | 109 +++
> .../arm/display/komeda/komeda_private_obj.c | 88 +
> 8 files changed, 608 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_kms.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_kms.h
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_plane.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index 25beae900ed2..1b875e5dc0f6 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -9,7 +9,11 @@ komeda-y := \
> komeda_dev.o \
> komeda_format_caps.o \
> komeda_pipeline.o \
> - komeda_framebuffer.o
> + komeda_framebuffer.o \
> + komeda_kms.o \
> + komeda_crtc.o \
> + komeda_plane.o \
> + komeda_private_obj.o
>
> komeda-y += \
> d71/d71_dev.o
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> new file mode 100644
> index ..5bb5a55f6b31
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
> + * Author: James.Qian.Wang
> + *
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "komeda_dev.h"
> +#include "komeda_kms.h"
> +
> +struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
> +};
> +
> +static const struct drm_crtc_funcs komeda_crtc_funcs = {
> +};
> +
> +int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
> +struct komeda_dev *mdev)
> +{
> + struct komeda_crtc *crtc;
> + struct komeda_pipeline *master;
> + char str[16];
> + int i;
> +
> + kms->n_crtcs = 0;
> +
> + for (i = 0; i < mdev->n_pipelines; i++) {
> + crtc = >crtcs[kms->n_crtcs];
> + master = mdev->pipelines[i];
> +
> + crtc->master = master;
> + crtc->slave = NULL;
> +
> + if (crtc->slave)
> + sprintf(str, "pipe-%d", crtc->slave->id);
> + else
> + sprintf(str, "None");
> +
> + DRM_INFO("crtc%d: master(pipe-%d) slave(%s) output: %s.\n",
> + kms->n_crtcs, master->id, str,
> + master->of_output_dev ?
> + master->of_output_dev->full_name : "None");
> +
> + kms->n_crtcs++;
> + }
> +
> + return 0;
> +}
> +
> +static struct drm_plane *
> +get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc)
> +{
> + struct komeda_plane *kplane;
> + struct drm_plane *plane;
> +
> + drm_for_each_plane(plane, >base) {
> + if (plane->type != DRM_PLANE_TYPE_PRIMARY)
> + continue;
> +
> + kplane = to_kplane(plane);
> + /* only master can be primary */
> + if (kplane->layer->base.pipeline == crtc->master)
> + return plane;
> + }
> +
> + return NULL;
> +}
> +
> +static int komeda_crtc_add(struct komeda_kms_dev *kms,
> +struct komeda_crtc *kcrtc)
> +{
> + struct drm_crtc *crtc = >base;
> + int err;
> +
> + err = drm_crtc_init_with_planes(>base, crtc,
> + get_crtc_primary(kms, kcrtc), NULL,
> + _crtc_funcs, NULL);
> + if (err)
> + return err;
> +
> + drm_crtc_helper_add(crtc, _crtc_helper_funcs);
> + drm_crtc_vblank_reset(crtc);
> +
> + crtc->port =
[PATCH] drm/vc4: Allow fb modifiers early enough to fill IN_FORMATS property
The KMS mode_config elements are currently configured in vc4_kms_load,
that is called after all components are binded (component_bind_all).
However, the CRTC component (for the Pixel Valve) needs to access the
allow_fb_modifiers element at bind time, when initializing its planes
through drm_universal_plane_init.
This helpers checks allow_fb_modifiers to decide whether to fill the
IN_FORMATS property. Because allow_fb_modifiers is still set to false
at this point, the property is never filled and userspace cannot
retrieve the combination of supported formats and modifiers.
Fix this by setting allow_fb_modifiers right after calling
drm_mode_config_init (which initializes the structure), before binding
the components of the driver.
Fixes: 423ad7b3cbd1 ("drm/vc4: Advertise supported modifiers for planes")
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/vc4/vc4_drv.c | 1 +
drivers/gpu/drm/vc4/vc4_kms.c | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 7195a0bcceb3..5c24f80dd34e 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -273,6 +273,7 @@ static int vc4_drm_bind(struct device *dev)
goto dev_put;
drm_mode_config_init(drm);
+ drm->mode_config.allow_fb_modifiers = true;
vc4_gem_init(drm);
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index b0cbb869f659..b70931fd8cf0 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -530,7 +530,6 @@ int vc4_kms_load(struct drm_device *dev)
dev->mode_config.funcs = _mode_funcs;
dev->mode_config.preferred_depth = 24;
dev->mode_config.async_page_flip = true;
- dev->mode_config.allow_fb_modifiers = true;
drm_modeset_lock_init(>ctm_state_lock);
--
2.20.1
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Re: [PATCH] drm: Block fb changes for async plane updates
On Fri, Dec 21, 2018 at 09:33:24AM -0500, Nicholas Kazlauskas wrote: > The behavior of drm_atomic_helper_cleanup_planes differs depending on > whether the commit was an asynchronous update or not. > > For a typical (non-async) atomic commit prepare_fb is called on the > new_plane_state and cleanup_fb is called on the old_plane_state. > > However, async commits are performed in place and don't swap the state > for the plane. The call to prepare_fb happens on the new_plane_state > and the call to cleanup_fb is also called on the new_plane_state in > this case (since the state hasn't swapped). > > This behavior can lead to use-after-free or unpin of an active fb. > > Consider the following sequence of events for interleaving fbs: > > - Async update, fb1 prepare, fb1 cleanup_fb > - Async update, fb2 prepare, fb2 cleanup_fb > - Non-async update, fb1 prepare, fb2 cleanup_fb > - Async update, fb2 cleanup_fb -> double cleanup, use-after-free I think I see your bug, but I'm completely lost in your description above. I think this is ok as a short-term gap, but imo better if it's a separate if condition with a FIXME comment. Long-term we want to fix this, and I think simplest way to do that is if we expect drivers to store the old fb in the new_plane_state (and check that with a WARN_ON like the others). I think that should work. We probably also need some locking on top, to prevent races with the cleanup_fb calls done by non-blocking commits, to make sure those clean up the right fb. -Daniel > This situation has been observed in practice for a double buffered > cursor when closing an X client. The non-async update occurs because > the new_plane_state->crtc != old_plane_state->crtc which forces the > non-async path to occur. > > The simplest fix for this is to block fb updates in > drm_atomic_helper_async_check. This guarantees that the framebuffer > will have previously been prepared and any subsequent async updates > will always call prepare and cleanup_fb like the non-async atomic > commit path would. > > Cc: Michel Dänzer > Cc: Daniel Vetter > Cc: Andrey Grodzovsky > Cc: Harry Wentland > Signed-off-by: Nicholas Kazlauskas > --- > drivers/gpu/drm/drm_atomic_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c > b/drivers/gpu/drm/drm_atomic_helper.c > index 54e2ae614dcc..d2f80bf14f86 100644 > --- a/drivers/gpu/drm/drm_atomic_helper.c > +++ b/drivers/gpu/drm/drm_atomic_helper.c > @@ -1599,7 +1599,8 @@ int drm_atomic_helper_async_check(struct drm_device > *dev, > return -EINVAL; > > if (!new_plane_state->crtc || > - old_plane_state->crtc != new_plane_state->crtc) > + old_plane_state->crtc != new_plane_state->crtc || > + old_plane_state->fb != new_plane_state->fb) > return -EINVAL; > > funcs = plane->helper_private; > -- > 2.17.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 6/9] drm/komeda: Add komeda_framebuffer
On Fri, Dec 21, 2018 at 10:00:17AM +, james qian wang (Arm Technology
China) wrote:
> komeda_framebuffer is for extending drm_framebuffer to add komeda own
> attributes and komeda specific fb handling.
>
> Changes in v3:
> - Fixed style problem found by checkpatch.pl --strict.
>
> Signed-off-by: James (Qian) Wang
> ---
> drivers/gpu/drm/arm/display/komeda/Makefile | 3 +-
> .../arm/display/komeda/komeda_framebuffer.c | 165 ++
> .../arm/display/komeda/komeda_framebuffer.h | 31
> 3 files changed, 198 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index 394fc2aa434a..25beae900ed2 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -8,7 +8,8 @@ komeda-y := \
> komeda_drv.o \
> komeda_dev.o \
> komeda_format_caps.o \
> - komeda_pipeline.o
> + komeda_pipeline.o \
> + komeda_framebuffer.o
>
> komeda-y += \
> d71/d71_dev.o
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> new file mode 100644
> index ..4ddd5314ca23
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c
> @@ -0,0 +1,165 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
> + * Author: James.Qian.Wang
> + *
> + */
> +#include
> +#include
> +#include
> +#include
> +#include "komeda_framebuffer.h"
> +#include "komeda_dev.h"
> +
> +static void komeda_fb_destroy(struct drm_framebuffer *fb)
> +{
> + struct komeda_fb *kfb = to_kfb(fb);
> + u32 i;
> +
> + for (i = 0; i < fb->format->num_planes; i++)
> + drm_gem_object_put_unlocked(fb->obj[i]);
> +
> + drm_framebuffer_cleanup(fb);
> + kfree(kfb);
> +}
> +
> +static int komeda_fb_create_handle(struct drm_framebuffer *fb,
> +struct drm_file *file, u32 *handle)
> +{
> + return drm_gem_handle_create(file, fb->obj[0], handle);
> +}
> +
> +static const struct drm_framebuffer_funcs komeda_fb_funcs = {
> + .destroy= komeda_fb_destroy,
> + .create_handle = komeda_fb_create_handle,
> +};
> +
> +static int
> +komeda_fb_none_afbc_size_check(struct komeda_dev *mdev, struct komeda_fb
> *kfb,
> +struct drm_file *file,
> +const struct drm_mode_fb_cmd2 *mode_cmd)
Not sure what _none stands for here, but otherwise:
Acked-by: Liviu Dudau
Best regards,
Liviu
> +{
> + struct drm_framebuffer *fb = >base;
> + struct drm_gem_object *obj;
> + u32 min_size = 0;
> + u32 i;
> +
> + for (i = 0; i < fb->format->num_planes; i++) {
> + obj = drm_gem_object_lookup(file, mode_cmd->handles[i]);
> + if (!obj) {
> + DRM_DEBUG_KMS("Failed to lookup GEM object\n");
> + fb->obj[i] = NULL;
> +
> + return -ENOENT;
> + }
> +
> + kfb->aligned_w = fb->width / (i ? fb->format->hsub : 1);
> + kfb->aligned_h = fb->height / (i ? fb->format->vsub : 1);
> +
> + if (fb->pitches[i] % mdev->chip.bus_width) {
> + DRM_DEBUG_KMS("Pitch[%d]: 0x%x doesn't align to 0x%x\n",
> + i, fb->pitches[i], mdev->chip.bus_width);
> + drm_gem_object_put_unlocked(obj);
> + fb->obj[i] = NULL;
> +
> + return -EINVAL;
> + }
> +
> + min_size = ((kfb->aligned_h / kfb->format_caps->tile_size - 1)
> + * fb->pitches[i])
> + + (kfb->aligned_w * fb->format->cpp[i]
> +* kfb->format_caps->tile_size)
> + + fb->offsets[i];
> +
> + if (obj->size < min_size) {
> + DRM_DEBUG_KMS("Fail to check none afbc fb size.\n");
> + drm_gem_object_put_unlocked(obj);
> + fb->obj[i] = NULL;
> +
> + return -EINVAL;
> + }
> +
> + fb->obj[i] = obj;
> + }
> +
> + if (fb->format->num_planes == 3) {
> + if (fb->pitches[1] != fb->pitches[2]) {
> + DRM_DEBUG_KMS("The pitch[1] and [2] are not same\n");
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +struct drm_framebuffer *
> +komeda_fb_create(struct drm_device *dev, struct drm_file *file,
> + const struct drm_mode_fb_cmd2 *mode_cmd)
> +{
> + struct komeda_dev *mdev = dev->dev_private;
> + struct komeda_fb *kfb;
> + int ret = 0, i;
> +
> +
[radeon-alex:amd-staging-drm-next 597/638] drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_timing_generator.c:97: undefined reference to `__udivdi3'
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: d9c54d61df327dc93374b718d7941a09e02e32e1
commit: 1d752442f3d6275b40bace55d022e792167f7fca [597/638] drm/amd/display: Use
100 Hz precision for pipe pixel clocks
config: i386-randconfig-n0-12220509 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
git checkout 1d752442f3d6275b40bace55d022e792167f7fca
# save the attached .config to linux build tree
make ARCH=i386
Note: the radeon-alex/amd-staging-drm-next HEAD
d9c54d61df327dc93374b718d7941a09e02e32e1 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.o: In function
`amdgpu_dm_do_flip':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4615: undefined
reference to `__udivdi3'
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.o: In function
`program_pix_dur':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_timing_generator.c:97:
>> undefined reference to `__udivdi3'
vim +97 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_timing_generator.c
86
87 static void program_pix_dur(struct timing_generator *tg, uint32_t
pix_clk_100hz)
88 {
89 uint64_t pix_dur;
90 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
91 +
DCE110TG_FROM_TG(tg)->offsets.dmif;
92 uint32_t value = dm_read_reg(tg->ctx, addr);
93
94 if (pix_clk_100hz == 0)
95 return;
96
> 97 pix_dur = 100ull / pix_clk_100hz;
98
99 set_reg_field_value(
100 value,
101 pix_dur,
102 DPG_PIPE_ARBITRATION_CONTROL1,
103 PIXEL_DURATION);
104
105 dm_write_reg(tg->ctx, addr, value);
106 }
107
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [PATCH v3 5/9] drm/komeda: Add komeda_format_caps for format handling
On Fri, Dec 21, 2018 at 10:00:01AM +, james qian wang (Arm Technology
China) wrote:
> komeda_format_caps is for describing ARM display specific features and
> limitations of a specific format, and format_caps will be linked into
> _framebuffer like a extension of _format_info.
> And komed_format_caps_table will be initialized before the enum_resources,
> since the layer features description depend on this format_caps table, so
> we'd better initialize the table first.
>
> Changes in v3:
> - Fixed style problem found by checkpatch.pl --strict.
>
> Signed-off-by: James (Qian) Wang
Acked-by: Liviu Dudau
Best regards,
Liviu
> ---
> drivers/gpu/drm/arm/display/komeda/Makefile | 1 +
> .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 78
> .../gpu/drm/arm/display/komeda/komeda_dev.c | 2 +
> .../gpu/drm/arm/display/komeda/komeda_dev.h | 11 ++-
> .../arm/display/komeda/komeda_format_caps.c | 75
> .../arm/display/komeda/komeda_format_caps.h | 89 +++
> .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> 7 files changed, 256 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_format_caps.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index c03d6876ef75..394fc2aa434a 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -7,6 +7,7 @@ ccflags-y := \
> komeda-y := \
> komeda_drv.o \
> komeda_dev.o \
> + komeda_format_caps.o \
> komeda_pipeline.o
>
> komeda-y += \
> diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> index af3dabb499cd..edbf9daa1545 100644
> --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> @@ -13,7 +13,85 @@ static int d71_enum_resources(struct komeda_dev *mdev)
> return -1;
> }
>
> +#define __HW_ID(__group, __format) \
> + __group) & 0x7) << 3) | ((__format) & 0x7))
> +
> +#define RICH KOMEDA_FMT_RICH_LAYER
> +#define SIMPLE KOMEDA_FMT_SIMPLE_LAYER
> +#define RICH_SIMPLE (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_SIMPLE_LAYER)
> +#define RICH_WB (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_WB_LAYER)
> +#define RICH_SIMPLE_WB (RICH_SIMPLE | KOMEDA_FMT_WB_LAYER)
> +
> +#define Rot_0DRM_MODE_ROTATE_0
> +#define Flip_H_V (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | Rot_0)
> +#define Rot_ALL_H_V (DRM_MODE_ROTATE_MASK | Flip_H_V)
> +
> +#define LYT_NM BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16)
> +#define LYT_WB BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
> +#define LYT_NM_WB(LYT_NM | LYT_WB)
> +
> +#define AFB_TH AFBC(_TILED | _SPARSE)
> +#define AFB_TH_SC_YTRAFBC(_TILED | _SC | _SPARSE | _YTR)
> +#define AFB_TH_SC_YTR_BS AFBC(_TILED | _SC | _SPARSE | _YTR | _SPLIT)
> +
> +static struct komeda_format_caps d71_format_caps_table[] = {
> + /* HW_ID|fourcc| tile_sz | layer_types | rots
>| afbc_layouts | afbc_features */
> + /* ABGR_2101010*/
> + {__HW_ID(0, 0), DRM_FORMAT_ARGB2101010, 1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1, RICH_SIMPLE,
> Rot_ALL_H_V,LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
> + {__HW_ID(0, 2), DRM_FORMAT_RGBA1010102, 1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(0, 3), DRM_FORMAT_BGRA1010102, 1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + /* ABGR_*/
> + {__HW_ID(1, 0), DRM_FORMAT_ARGB,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(1, 1), DRM_FORMAT_ABGR,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(1, 1), DRM_FORMAT_ABGR,1, RICH_SIMPLE,
> Rot_ALL_H_V,LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
> + {__HW_ID(1, 2), DRM_FORMAT_RGBA,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(1, 3), DRM_FORMAT_BGRA,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + /* XBGB_ */
> + {__HW_ID(2, 0), DRM_FORMAT_XRGB,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(2, 1), DRM_FORMAT_XBGR,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(2, 2), DRM_FORMAT_RGBX,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + {__HW_ID(2, 3), DRM_FORMAT_BGRX,1, RICH_SIMPLE_WB,
> Flip_H_V, 0, 0},
> + /* BGR_888 */ /* none-afbc RGB888 doesn't support rotation and flip */
> + {__HW_ID(3, 0),
Re: [PATCH v3 4/9] drm/komeda: Add DT parsing
On Fri, Dec 21, 2018 at 09:59:44AM +, james qian wang (Arm Technology
China) wrote:
> Parse DT and initialize corresponding dev/pipeline attributes.
>
> Changes in v3:
> - Fixed style problem found by checkpatch.pl --strict.
>
> Changes in v2:
> - Unified abbreviation of "pipeline" to "pipe".
>
> Signed-off-by: James (Qian) Wang
Acked-by: Liviu Dudau
Best regards,
Liviu
> ---
> .../gpu/drm/arm/display/komeda/komeda_dev.c | 76 +++
> .../gpu/drm/arm/display/komeda/komeda_dev.h | 3 +
> .../drm/arm/display/komeda/komeda_pipeline.c | 4 +
> .../drm/arm/display/komeda/komeda_pipeline.h | 7 ++
> 4 files changed, 90 insertions(+)
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
> b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
> index 887a17005367..d0cc4f758077 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
> @@ -12,6 +12,76 @@
> #include
> #include "komeda_dev.h"
>
> +static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node
> *np)
> +{
> + struct komeda_pipeline *pipe;
> + struct clk *clk;
> + u32 pipe_id;
> + int ret = 0;
> +
> + ret = of_property_read_u32(np, "reg", _id);
> + if (ret != 0 || pipe_id >= mdev->n_pipelines)
> + return -EINVAL;
> +
> + pipe = mdev->pipelines[pipe_id];
> +
> + clk = of_clk_get_by_name(np, "aclk");
> + if (IS_ERR(clk)) {
> + DRM_ERROR("get aclk for pipeline %d failed!\n", pipe_id);
> + return PTR_ERR(clk);
> + }
> + pipe->aclk = clk;
> +
> + clk = of_clk_get_by_name(np, "pxclk");
> + if (IS_ERR(clk)) {
> + DRM_ERROR("get pxclk for pipeline %d failed!\n", pipe_id);
> + return PTR_ERR(clk);
> + }
> + pipe->pxlclk = clk;
> +
> + /* enum ports */
> + pipe->of_output_dev =
> + of_graph_get_remote_node(np, KOMEDA_OF_PORT_OUTPUT, 0);
> + pipe->of_output_port =
> + of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT);
> +
> + pipe->of_node = np;
> +
> + return 0;
> +}
> +
> +static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct device_node *child, *np = dev->of_node;
> + struct clk *clk;
> + int ret;
> +
> + clk = devm_clk_get(dev, "mclk");
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + mdev->mclk = clk;
> + mdev->irq = platform_get_irq(pdev, 0);
> + if (mdev->irq < 0) {
> + DRM_ERROR("could not get IRQ number.\n");
> + return mdev->irq;
> + }
> +
> + for_each_available_child_of_node(np, child) {
> + if (of_node_cmp(child->name, "pipeline") == 0) {
> + ret = komeda_parse_pipe_dt(mdev, child);
> + if (ret) {
> + DRM_ERROR("parse pipeline dt error!\n");
> + of_node_put(child);
> + break;
> + }
> + }
> + }
> +
> + return ret;
> +}
> +
> struct komeda_dev *komeda_dev_create(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> @@ -74,6 +144,12 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
> goto err_cleanup;
> }
>
> + err = komeda_parse_dt(dev, mdev);
> + if (err) {
> + DRM_ERROR("parse device tree failed.\n");
> + goto err_cleanup;
> + }
> +
> return mdev;
>
> err_cleanup:
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> index 680e3e2cf100..4a27a44e2ec6 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> @@ -72,6 +72,9 @@ struct komeda_dev {
> /** @mck: HW main engine clk */
> struct clk *mclk;
>
> + /** @irq: irq number */
> + u32 irq;
> +
> int n_pipelines;
> struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
> b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
> index 9293598b0533..e731b2a85c3a 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
> @@ -55,6 +55,10 @@ void komeda_pipeline_destroy(struct komeda_dev *mdev,
> clk_put(pipe->pxlclk);
> clk_put(pipe->aclk);
>
> + of_node_put(pipe->of_output_dev);
> + of_node_put(pipe->of_output_port);
> + of_node_put(pipe->of_node);
> +
> devm_kfree(mdev->dev, pipe);
> }
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> index 2174796d47c5..d1e0c1140273 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> +++
Re: [PATCH v3 3/9] drm/komeda: Build komeda to be a platform module
On Fri, Dec 21, 2018 at 09:59:28AM +, james qian wang (Arm Technology
China) wrote:
> Implement a simple wrapper for platform module to build komeda to module,
> Also add a very simple D71 layer code to show how to discover a product.
> Komeda driver direct bind the product ENTRY function xxx_identity to DT
> compatible name like:
>
> d71_product = {
> .product_id = MALIDP_D71_PRODUCT_ID,
> .identify = d71_identify,
> },
>
> const struct of_device_id komeda_of_match[] = {
> { .compatible = "arm,mali-d71", .data = _product, },
> {},
> };
>
> Then when linux found a matched DT node and call driver to probe, we can
> easily get the of data, and call into the product to do the identify:
>
> komeda_bind()
> {
> ...
> product = of_device_get_match_data(dev);
>
> product->identify();
> ...
> }
>
> Changes in v3:
> - Fixed style problem found by checkpatch.pl --strict.
>
> Signed-off-by: James (Qian) Wang
Acked-by: Liviu Dudau
Best regards,
Liviu
> ---
> .../gpu/drm/arm/display/include/malidp_io.h | 42 ++
> drivers/gpu/drm/arm/display/komeda/Makefile | 6 +-
> .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 33 +
> .../gpu/drm/arm/display/komeda/komeda_dev.h | 3 +
> .../gpu/drm/arm/display/komeda/komeda_drv.c | 132 ++
> 5 files changed, 215 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/arm/display/include/malidp_io.h
> create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_drv.c
>
> diff --git a/drivers/gpu/drm/arm/display/include/malidp_io.h
> b/drivers/gpu/drm/arm/display/include/malidp_io.h
> new file mode 100644
> index ..4fb3caf864ce
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/display/include/malidp_io.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
> + * Author: James.Qian.Wang
> + *
> + */
> +#ifndef _MALIDP_IO_H_
> +#define _MALIDP_IO_H_
> +
> +#include
> +
> +static inline u32
> +malidp_read32(u32 __iomem *base, u32 offset)
> +{
> + return readl((base + (offset >> 2)));
> +}
> +
> +static inline void
> +malidp_write32(u32 __iomem *base, u32 offset, u32 v)
> +{
> + writel(v, (base + (offset >> 2)));
> +}
> +
> +static inline void
> +malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v)
> +{
> + u32 tmp = malidp_read32(base, offset);
> +
> + tmp &= (~m);
> + malidp_write32(base, offset, v | tmp);
> +}
> +
> +static inline void
> +malidp_write_group(u32 __iomem *base, u32 offset, int num, const u32 *values)
> +{
> + int i;
> +
> + for (i = 0; i < num; i++)
> + malidp_write32(base, offset + i * 4, values[i]);
> +}
> +
> +#endif /*_MALIDP_IO_H_*/
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index 5b44e36509b1..c03d6876ef75 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -5,7 +5,11 @@ ccflags-y := \
> -I$(src)
>
> komeda-y := \
> + komeda_drv.o \
> komeda_dev.o \
> - komeda_pipeline.o \
> + komeda_pipeline.o
> +
> +komeda-y += \
> + d71/d71_dev.o
>
> obj-$(CONFIG_DRM_KOMEDA) += komeda.o
> diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> new file mode 100644
> index ..af3dabb499cd
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
> + * Author: James.Qian.Wang
> + *
> + */
> +#include "malidp_io.h"
> +#include "komeda_dev.h"
> +
> +static int d71_enum_resources(struct komeda_dev *mdev)
> +{
> + /* TODO add enum resources */
> + return -1;
> +}
> +
> +static struct komeda_dev_funcs d71_chip_funcs = {
> + .enum_resources = d71_enum_resources,
> + .cleanup= NULL,
> +};
> +
> +#define GLB_ARCH_ID 0x000
> +#define GLB_CORE_ID 0x004
> +#define GLB_CORE_INFO0x008
> +
> +struct komeda_dev_funcs *
> +d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
> +{
> + chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
> + chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
> + chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
> +
> + return _chip_funcs;
> +}
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> index ad8fa160eff9..680e3e2cf100 100644
> --- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> +++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
> @@ -92,6 +92,9 @@ komeda_product_match(struct komeda_dev *mdev, u32 target)
> return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
> }
>
> +struct
Re: [PATCH v3 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71
On Fri, Dec 21, 2018 at 09:59:12AM +, james qian wang (Arm Technology
China) wrote:
> Add DT bindings documentation for the ARM display processor D71 and later
> IPs.
>
> Signed-off-by: James (Qian) Wang
>
> Changes in v3:
> - Deleted unnecessary property: interrupt-names.
> - Dropped 'ports' and moving 'port' up a level.
> ---
> .../bindings/display/arm/arm,komeda.txt | 79 +++
> 1 file changed, 79 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/arm/arm,komeda.txt
>
> diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
> b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
> new file mode 100644
> index ..b4e450243c7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
> @@ -0,0 +1,79 @@
> +Device Tree bindings for ARM Komeda display driver
> +
> +Required properties:
> +- compatible: Should be "arm,mali-d71"
> +- reg: Physical base address and length of the registers in the system
> +- interrupts: the interrupt line number of the device in the system
> +- clocks: A list of phandle + clock-specifier pairs, one for each entry
> +in 'clock-names'
> +- clock-names: A list of clock names. It should contain:
> + - "mclk": for the main processor clock
> + - "pclk": for the APB interface clock
> +- #address-cells: Must be 1
> +- #size-cells: Must be 0
> +
> +Required properties for sub-node: pipeline@nq
> +Each device contains one or two pipeline sub-nodes (at least one), each
> +pipeline node should provide properties:
> +- reg: Zero-indexed identifier for the pipeline
> +- clocks: A list of phandle + clock-specifier pairs, one for each entry
> +in 'clock-names'
> +- clock-names: should contain:
> + - "pxclk": pixel clock
> + - "aclk": AXI interface clock
> +
> +- port: each pipeline connect to an encoder input port. The connection is
> +modeled using the OF graph bindings specified in
> +Documentation/devicetree/bindings/graph.txt
> +
> +Optional properties:
> + - memory-region: phandle to a node describing memory (see
> +Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
> +to be used for the framebuffer; if not present, the framebuffer may
> +be located anywhere in memory.
> +
> +Example:
> +/ {
> + ...
> +
> + dp0: display@c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "arm,mali-d71";
> + reg = <0xc0 0x2>;
> + interrupts = <0 168 4>;
> + clocks = <_mclk>, <_aclk>;
> + clock-names = "mclk", "pclk";
> +
> + dp0_pipe0: pipeline@0 {
> + clocks = <>, <_aclk>;
> + clock-names = "pxclk", "aclk";
> + reg = <0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
These are undocumented and not necessary anyway, as the pipelines will
inherit display's attributes.
> +
> + port@0 {
> + dp0_pipe0_out: endpoint {
> + remote-endpoint = <_dvi0_in>;
> + };
> + };
> + };
> +
> + dp0_pipe1: pipeline@1 {
> + clocks = <>, <_aclk>;
> + clock-names = "pxclk", "aclk";
> + reg = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
same here.
> +
> + port@0 {
> + dp0_pipe1_out: endpoint {
> + remote-endpoint = <_dvi1_in>;
> + };
> + };
> + };
> + };
> + ...
> +};
> --
> 2.17.1
>
With these changes:
Reviewed-by: Liviu Dudau
Best regards,
Liviu
--
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---
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Re: [PATCH v3 1/9] drm/komeda: komeda_dev/pipeline/component definition and initialzation
On Fri, Dec 21, 2018 at 09:58:55AM +, james qian wang (Arm Technology China) wrote: > 1. Added a brief definition of komeda_dev/pipeline/component, this change >didn't add the detailed component features and capabilities, which will >be added in the following changes. > 2. Corresponding resources discovery and initialzation functions. > > Signed-off-by: James (Qian) Wang > > Changes in v3: > - Fixed style problem found by checkpatch.pl --strict. > > Changes in v2: > - Unified abbreviation of "pipeline" to "pipe". > --- > drivers/gpu/drm/arm/Kconfig | 2 + > drivers/gpu/drm/arm/Makefile | 1 + > drivers/gpu/drm/arm/display/Kbuild| 3 + > drivers/gpu/drm/arm/display/Kconfig | 14 + > .../drm/arm/display/include/malidp_product.h | 23 ++ > .../drm/arm/display/include/malidp_utils.h| 16 + > drivers/gpu/drm/arm/display/komeda/Makefile | 11 + > .../gpu/drm/arm/display/komeda/komeda_dev.c | 117 ++ > .../gpu/drm/arm/display/komeda/komeda_dev.h | 98 + > .../drm/arm/display/komeda/komeda_pipeline.c | 198 ++ > .../drm/arm/display/komeda/komeda_pipeline.h | 350 ++ > 11 files changed, 833 insertions(+) > create mode 100644 drivers/gpu/drm/arm/display/Kbuild > create mode 100644 drivers/gpu/drm/arm/display/Kconfig > create mode 100644 drivers/gpu/drm/arm/display/include/malidp_product.h > create mode 100644 drivers/gpu/drm/arm/display/include/malidp_utils.h > create mode 100644 drivers/gpu/drm/arm/display/komeda/Makefile > create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_dev.c > create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_dev.h > create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c > create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h > > diff --git a/drivers/gpu/drm/arm/Kconfig b/drivers/gpu/drm/arm/Kconfig > index f9f7761cb2f4..a204103b3efb 100644 > --- a/drivers/gpu/drm/arm/Kconfig > +++ b/drivers/gpu/drm/arm/Kconfig > @@ -37,4 +37,6 @@ config DRM_MALI_DISPLAY > > If compiled as a module it will be called mali-dp. > > +source "drivers/gpu/drm/arm/display/Kconfig" > + > endmenu > diff --git a/drivers/gpu/drm/arm/Makefile b/drivers/gpu/drm/arm/Makefile > index 3bf31d1a4722..120bef801fcf 100644 > --- a/drivers/gpu/drm/arm/Makefile > +++ b/drivers/gpu/drm/arm/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_DRM_HDLCD) += hdlcd.o > mali-dp-y := malidp_drv.o malidp_hw.o malidp_planes.o malidp_crtc.o > mali-dp-y += malidp_mw.o > obj-$(CONFIG_DRM_MALI_DISPLAY) += mali-dp.o > +obj-$(CONFIG_DRM_KOMEDA) += display/ > diff --git a/drivers/gpu/drm/arm/display/Kbuild > b/drivers/gpu/drm/arm/display/Kbuild > new file mode 100644 > index ..382f1ca831e4 > --- /dev/null > +++ b/drivers/gpu/drm/arm/display/Kbuild > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +obj-$(CONFIG_DRM_KOMEDA) += komeda/ > diff --git a/drivers/gpu/drm/arm/display/Kconfig > b/drivers/gpu/drm/arm/display/Kconfig > new file mode 100644 > index ..cec0639e3aa1 > --- /dev/null > +++ b/drivers/gpu/drm/arm/display/Kconfig > @@ -0,0 +1,14 @@ > +# SPDX-License-Identifier: GPL-2.0 > +config DRM_KOMEDA > + tristate "ARM Komeda display driver" > + depends on DRM && OF > + depends on COMMON_CLK > + select DRM_KMS_HELPER > + select DRM_KMS_CMA_HELPER > + select DRM_GEM_CMA_HELPER > + select VIDEOMODE_HELPERS > + help > + Choose this option if you want to compile the ARM Komeda display > + Processor driver. It supports the D71 variants of the hardware. > + > + If compiled as a module it will be called komeda. > diff --git a/drivers/gpu/drm/arm/display/include/malidp_product.h > b/drivers/gpu/drm/arm/display/include/malidp_product.h > new file mode 100644 > index ..b35fc5db866b > --- /dev/null > +++ b/drivers/gpu/drm/arm/display/include/malidp_product.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * (C) COPYRIGHT 2018 ARM Limited. All rights reserved. > + * Author: James.Qian.Wang > + * > + */ > +#ifndef _MALIDP_PRODUCT_H_ > +#define _MALIDP_PRODUCT_H_ > + > +/* Product identification */ > +#define MALIDP_CORE_ID(__product, __major, __minor, __status) \ > + __product) & 0x) << 16) | (((__major) & 0xF) << 12) | \ > + (((__minor) & 0xF) << 8) | ((__status) & 0xFF)) > + > +#define MALIDP_CORE_ID_PRODUCT_ID(__core_id) ((__u32)(__core_id) >> 16) > +#define MALIDP_CORE_ID_MAJOR(__core_id) (((__u32)(__core_id) >> 12) & > 0xF) > +#define MALIDP_CORE_ID_MINOR(__core_id) (((__u32)(__core_id) >> 8) & > 0xF) > +#define MALIDP_CORE_ID_STATUS(__core_id) (((__u32)(__core_id)) & 0xFF) > + > +/* Mali-display product IDs */ > +#define MALIDP_D71_PRODUCT_ID 0x0071 > + > +#endif /* _MALIDP_PRODUCT_H_ */ > diff --git a/drivers/gpu/drm/arm/display/include/malidp_utils.h >
[Bug 201539] AMDGPU R9 390 automatic fan speed control in Linux 4.19/4.20
https://bugzilla.kernel.org/show_bug.cgi?id=201539 --- Comment #9 from Jan Ziak (http://atom-symbol.net) (0xe2.0x9a.0...@gmail.com) --- Linux 4.20 behaves the same as Linux 4.19. -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 201539] AMDGPU R9 390 automatic fan speed control in Linux 4.19/4.20
https://bugzilla.kernel.org/show_bug.cgi?id=201539 Jan Ziak (http://atom-symbol.net) (0xe2.0x9a.0...@gmail.com) changed: What|Removed |Added Summary|AMDGPU R9 390 automatic fan |AMDGPU R9 390 automatic fan |speed control in Linux 4.19 |speed control in Linux ||4.19/4.20 -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 201273] Fatal error during GPU init amdgpu RX560
https://bugzilla.kernel.org/show_bug.cgi?id=201273 --- Comment #27 from quirin.blae...@freenet.de --- Bug is still alive. amd-staging-drm-next d9c54d61df327dc93374b718d7941a09e02e32e1 -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 16/18] drm/mediatek: add function mtk_ddp_comp_get_type
___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH][next] drm: fix null pointer dereference on null state pointer
On Sat, Dec 22, 2018 at 01:00:46PM +, Colin King wrote:
> From: Colin Ian King
>
> In the case where state cannot be allocated, the current exit path via
> label 'out' will dereference the null state pointer when calling
> drm_atomic_state_put. Fix this by adding a new error exit label and
> jumping to this to avoid the drm_atomic_state_put.
>
> Detected by CoverityScan, CID#1476034 ("Dereference after null check")
>
> Fixes: b9fc5e01d1ce ("drm: Add helper to implement legacy dirtyfb")
> Signed-off-by: Colin Ian King
Looks correct to me, merged into drm-misc-next-fixes for 4.21.
Thanks, Daniel
> ---
> drivers/gpu/drm/drm_damage_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_damage_helper.c
> b/drivers/gpu/drm/drm_damage_helper.c
> index d2a1c7372f36..31032407254d 100644
> --- a/drivers/gpu/drm/drm_damage_helper.c
> +++ b/drivers/gpu/drm/drm_damage_helper.c
> @@ -178,7 +178,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb,
> state = drm_atomic_state_alloc(fb->dev);
> if (!state) {
> ret = -ENOMEM;
> - goto out;
> + goto out_drop_locks;
> }
> state->acquire_ctx =
>
> @@ -238,6 +238,7 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb,
> kfree(rects);
> drm_atomic_state_put(state);
>
> +out_drop_locks:
> drm_modeset_drop_locks();
> drm_modeset_acquire_fini();
>
> --
> 2.19.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 08/18] drm/mediatek: add component OVL1_2L
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[PATCH 11/18] drm/medaitek: add layer_nr for ovl private data
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[PATCH 10/18] drm/mediatek: add gmc_bits for ovl private data
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[PATCH 09/18] drm/mediatek: add component DITHER
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[PATCH v4 1/2] drm/amd: validate user pitch alignment
Userspace may request pitch alignment that is not supported by GPU.
Some requests 32, but GPU ignores it and uses default 64 when cpp is
4. If GEM object is allocated based on the smaller alignment, GPU
DMA will go out of bound.
For GPU that does frame buffer compression, DMA writing out of bound
memory will cause memory corruption.
Cc: sta...@vger.kernel.org # v4.2+
Signed-off-by: Yu Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 686a26de50f9..af0626a2b528 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -527,6 +527,15 @@ amdgpu_display_user_framebuffer_create(struct drm_device
*dev,
struct drm_gem_object *obj;
struct amdgpu_framebuffer *amdgpu_fb;
int ret;
+ struct amdgpu_device *adev = dev->dev_private;
+ int cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
+ int pitch = amdgpu_align_pitch(adev, mode_cmd->width, cpp, false);
+
+ if (mode_cmd->pitches[0] != pitch) {
+ DRM_DEBUG_KMS("Invalid pitch: expecting %d but got %d\n",
+ pitch, mode_cmd->pitches[0]);
+ return ERR_PTR(-EINVAL);
+ }
obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
if (obj == NULL) {
--
2.20.1.415.g653613c723-goog
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[PATCH] staging: android: ion: move map_kernel to ion_dma_buf_kmap
Now, as Google's user guide, if userspace need clean ION buffer's
cache, they should call ioctl(fd, DMA_BUF_IOCTL_SYNC, sync). Then
we found that ion_dma_buf_begin_cpu_access/ion_dma_buf_end_cpu_access
will do ION buffer's map_kernel, it's not necessary. And if usersapce
only need clean cache, they will call ion_dma_buf_end_cpu_access by
dmabuf's ioctl, ION buffer's kmap_cnt will be wrong value -1, then
driver could not get right kernel vaddr by dma_buf_kmap.
Signed-off-by: Qing Xia
---
drivers/staging/android/ion/ion.c | 46 ++-
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/staging/android/ion/ion.c
index 9907332..f7e2812 100644
--- a/drivers/staging/android/ion/ion.c
+++ b/drivers/staging/android/ion/ion.c
@@ -303,45 +303,47 @@ static void ion_dma_buf_release(struct dma_buf *dmabuf)
static void *ion_dma_buf_kmap(struct dma_buf *dmabuf, unsigned long offset)
{
struct ion_buffer *buffer = dmabuf->priv;
+ void *vaddr;
- return buffer->vaddr + offset * PAGE_SIZE;
+ if (buffer->heap->ops->map_kernel) {
+ mutex_lock(>lock);
+ vaddr = ion_buffer_kmap_get(buffer);
+ mutex_unlock(>lock);
+ if (IS_ERR(vaddr))
+ return vaddr;
+
+ return vaddr + offset * PAGE_SIZE;
+ }
+
+ return NULL;
}
static void ion_dma_buf_kunmap(struct dma_buf *dmabuf, unsigned long offset,
void *ptr)
{
+ struct ion_buffer *buffer = dmabuf->priv;
+
+ if (buffer->heap->ops->map_kernel) {
+ mutex_lock(>lock);
+ ion_buffer_kmap_put(buffer);
+ mutex_unlock(>lock);
+ }
}
static int ion_dma_buf_begin_cpu_access(struct dma_buf *dmabuf,
enum dma_data_direction direction)
{
struct ion_buffer *buffer = dmabuf->priv;
- void *vaddr;
struct ion_dma_buf_attachment *a;
- int ret = 0;
-
- /*
-* TODO: Move this elsewhere because we don't always need a vaddr
-*/
- if (buffer->heap->ops->map_kernel) {
- mutex_lock(>lock);
- vaddr = ion_buffer_kmap_get(buffer);
- if (IS_ERR(vaddr)) {
- ret = PTR_ERR(vaddr);
- goto unlock;
- }
- mutex_unlock(>lock);
- }
mutex_lock(>lock);
list_for_each_entry(a, >attachments, list) {
dma_sync_sg_for_cpu(a->dev, a->table->sgl, a->table->nents,
direction);
}
-
-unlock:
mutex_unlock(>lock);
- return ret;
+
+ return 0;
}
static int ion_dma_buf_end_cpu_access(struct dma_buf *dmabuf,
@@ -350,12 +352,6 @@ static int ion_dma_buf_end_cpu_access(struct dma_buf
*dmabuf,
struct ion_buffer *buffer = dmabuf->priv;
struct ion_dma_buf_attachment *a;
- if (buffer->heap->ops->map_kernel) {
- mutex_lock(>lock);
- ion_buffer_kmap_put(buffer);
- mutex_unlock(>lock);
- }
-
mutex_lock(>lock);
list_for_each_entry(a, >attachments, list) {
dma_sync_sg_for_device(a->dev, a->table->sgl, a->table->nents,
--
2.7.3
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[PATCH 14/18] drm/mediatek: add connect function for ovl
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[PATCH 15/18] drm/mediatek: add RDMA1 fifo size into RDMA private data
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[PATCH 00/18] add drm support for MT8183
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[PATCH 07/18] drm/mediatek: add commponent OVL0_2L
___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/3] drm/amd: validate user pitch alignment
On Fri, Dec 21, 2018 at 10:07:26AM +0100, Michel Dänzer wrote: > On 2018-12-21 4:10 a.m., Yu Zhao wrote: > > Userspace may request pitch alignment that is not supported by GPU. > > Some requests 32, but GPU ignores it and uses default 64 when cpp is > > 4. If GEM object is allocated based on the smaller alignment, GPU > > DMA will go out of bound. > > > > For GPU that does frame buffer compression, DMA writing out of bound > > memory will cause memory corruption. > > > > Signed-off-by: Yu Zhao > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c > > index e309d26170db..755daa332f8a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c > > @@ -527,6 +527,15 @@ amdgpu_display_user_framebuffer_create(struct > > drm_device *dev, > > struct drm_gem_object *obj; > > struct amdgpu_framebuffer *amdgpu_fb; > > int ret; > > + struct amdgpu_device *adev = dev->dev_private; > > + int cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); > > + int pitch = amdgpu_align_pitch(adev, mode_cmd->width, cpp, false); > > Also, this needs to use mode_cmd->pitches[0] instead of mode_cmd->width, > otherwise it'll spuriously fail for larger but well-aligned pitches. Actually mode_cmd->pitches[0] is aligned mode_cmd->width multiplied by cpp. So we can't just use mode_cmd->pitches[0]. And I'm not sure if the hardware works with larger alignment (it certainly ignores smaller alignment). ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 12/18] drm/mediatek: add function to connect module with it's previous one
___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 2/2] drm/amd: validate user GEM object size
When creating frame buffer, userspace may request to attach to a
previously allocated GEM object that is smaller than what GPU
requires. Validation must be done to prevent out-of-bound DMA,
which could not only corrupt memory but also reveal sensitive data.
This fix is not done in a common code path because individual
driver might have different requirement.
Cc: sta...@vger.kernel.org # v4.2+
Signed-off-by: Yu Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index af0626a2b528..9aa23cb20873 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -527,6 +527,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device
*dev,
struct drm_gem_object *obj;
struct amdgpu_framebuffer *amdgpu_fb;
int ret;
+ int height;
struct amdgpu_device *adev = dev->dev_private;
int cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
int pitch = amdgpu_align_pitch(adev, mode_cmd->width, cpp, false);
@@ -550,6 +551,13 @@ amdgpu_display_user_framebuffer_create(struct drm_device
*dev,
return ERR_PTR(-EINVAL);
}
+ height = ALIGN(mode_cmd->height, 8);
+ if (obj->size < pitch * height) {
+ DRM_DEBUG_KMS("Invalid GEM size: expecting >= %d but got %zu\n",
+ pitch * height, obj->size);
+ return ERR_PTR(-EINVAL);
+ }
+
amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
if (amdgpu_fb == NULL) {
drm_gem_object_put_unlocked(obj);
--
2.20.1.415.g653613c723-goog
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[PATCH 18/18] drm/mediatek: add support for mediatek SOC MT8183
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[PATCH 04/18] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 06/18] drm/mediatek: add mmsys private data for ddp path config
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[PATCH 03/18] drm/mediatek: redefine mtk_ddp_sout_sel
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[PATCH 02/18] drm/mediatek: add mutex mod and sof into ddp private data
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[PATCH 01/18] drm/mediatek: update dt-bindings for mt8183
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RE: [PATCH] staging: android: ion: add buffer flag update ioctl
Hi laura:
>-Original Message-
>From: Laura Abbott [mailto:labb...@redhat.com]
>Sent: Friday, December 21, 2018 4:50 AM
>To: Zengtao (B) ; sumit.sem...@linaro.org
>Cc: Greg Kroah-Hartman ; Arve Hjønnevåg
>; Todd Kjos ; Martijn Coenen
>; Joel Fernandes ;
>de...@driverdev.osuosl.org; dri-devel@lists.freedesktop.org;
>linaro-mm-...@lists.linaro.org; linux-ker...@vger.kernel.org
>Subject: Re: [PATCH] staging: android: ion: add buffer flag update ioctl
>
>On 12/19/18 5:39 PM, Zengtao (B) wrote:
>> Hi laura:
>>
>>> -Original Message-
>>> From: Laura Abbott [mailto:labb...@redhat.com]
>>> Sent: Thursday, December 20, 2018 2:10 AM
>>> To: Zengtao (B) ;
>sumit.sem...@linaro.org
>>> Cc: Greg Kroah-Hartman ; Arve
>Hjønnevåg
>>> ; Todd Kjos ; Martijn
>Coenen
>>> ; Joel Fernandes ;
>>> de...@driverdev.osuosl.org; dri-devel@lists.freedesktop.org;
>>> linaro-mm-...@lists.linaro.org; linux-ker...@vger.kernel.org
>>> Subject: Re: [PATCH] staging: android: ion: add buffer flag update
>>> ioctl
>>>
>>> On 12/19/18 9:19 AM, Zeng Tao wrote:
In some usecases, the buffer cached attribute is not determined at
allocation time, it's determined just before the real cpu mapping.
And from the memory view of point, a buffer should not have the
>>> cached
attribute util is really mapped by the cpu. So in this patch, we
introduced the new ioctl command to target the requirement.
>>>
>>> This is racy and error prone. Can you explain more what problem you
>>> are trying to solve?
>>
>> My use case is like this:
>> 1. There are two process A and B, A takes case of ion buffer allocation,
>and
>> pass the buffer fd to B, then B maps and uses it.
>> 2. Process B need to map the buffer with different cached attribute
>> for different use case, for example, if the buffer is used for pure
>> software algorithm, then we need to map it as cached, otherwise
>> non-cached, and B needs to deal with both cases.
>> And unfortunately the mmap syscall takes no cached flags and we can't
>> decide the cache attribute when we are doing the mmap, so I introduce
>> new the ioctl even though I think the solution is not as good.
>>
>>
>
>Thanks for the explanation, this was about the use case I expected.
>I'm pretty sure I had this exact problem once upon a time and we didn't
>come up with a solution. I'd still like to get rid of uncached buffers in
>general and just use cached buffers (see
>http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2018-N
>ovember/128842.html)
>What's your usecase for uncached buffers?
Some buffers are only used by HW, in this case, we tend to use uncached buffers.
But sometimes the SW need to read few buffer contents for debug purpose and
no synchronization is needed.
>
>>>
Signed-off-by: Zeng Tao
---
drivers/staging/android/ion/ion-ioctl.c | 4
drivers/staging/android/ion/ion.c | 17
>+
drivers/staging/android/ion/ion.h | 1 +
drivers/staging/android/uapi/ion.h | 22
>>> ++
4 files changed, 44 insertions(+)
diff --git a/drivers/staging/android/ion/ion-ioctl.c
b/drivers/staging/android/ion/ion-ioctl.c
index a8d3cc4..60bb702 100644
--- a/drivers/staging/android/ion/ion-ioctl.c
+++ b/drivers/staging/android/ion/ion-ioctl.c
@@ -12,6 +12,7 @@
union ion_ioctl_arg {
struct ion_allocation_data allocation;
+ struct ion_buffer_flag_data update;
struct ion_heap_query query;
};
@@ -83,6 +84,9 @@ long ion_ioctl(struct file *filp, unsigned int
cmd, unsigned long arg)
break;
}
+ case ION_IOC_BUFFER_UPDATE:
+ ret = ion_buffer_update(data.update.fd, data.update.flags);
+ break;
case ION_IOC_HEAP_QUERY:
ret = ion_query_heaps();
break;
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/staging/android/ion/ion.c
index 9907332..f1404dc 100644
--- a/drivers/staging/android/ion/ion.c
+++ b/drivers/staging/android/ion/ion.c
@@ -436,6 +436,23 @@ int ion_alloc(size_t len, unsigned int
>>> heap_id_mask, unsigned int flags)
return fd;
}
+int ion_buffer_update(unsigned int fd, unsigned int flags) {
+ struct dma_buf *dmabuf;
+ struct ion_buffer *buffer;
+
+ dmabuf = dma_buf_get(fd);
+
+ if (!dmabuf)
+ return -EINVAL;
+
+ buffer = dmabuf->priv;
+ buffer->flags = flags;
+ dma_buf_put(dmabuf);
+
+ return 0;
+}
+
int ion_query_heaps(struct ion_heap_query *query)
{
struct ion_device *dev = internal_dev; diff --git
a/drivers/staging/android/ion/ion.h
b/drivers/staging/android/ion/ion.h
index c006fc1..99bf9ab 100644
---
Re: [PATCH] drm: Put damage blob when destroy plane state
On Fri, Dec 21, 2018 at 8:56 PM Thomas Hellstrom wrote: > > Reviewed-by: Thomas Hellstrom > > Daniel, Dave, could you help try to get this patch in -next before the > merge window. Otherwise people will start to experience random kernel > crashes. I figure we don't want to wait until first -fixes pull with > this. Afaiui this will only blow up with new userspace on new kernels, that doesn't feel like rushing an updated -next out the door material to me. More concerning is why this fell through the cracks: - We have an igt, do those testcases not hit this bug? - Were the tests not run before you've sent out the pull? - The merged version doesn't seem to match any of the versions I've found on dri-devel, I guess should have been resend when there was conflicts? - Some other crack in the matrix? > Thanks, > Thomas > > > On Fri, 2018-12-21 at 11:35 -0800, Deepak Rawat wrote: > > Somehow the code to put the damage blob on destroy plane state and > > set > > the blob to NULL when duplicate plane state was not merged. May be > > because the files are refactored since the patch was written. With > > this > > fix add those. > > > > Cc: Daniel Vetter > > Signed-off-by: Deepak Rawat Needs a Fixes: tag referencing the broken commit, pls remember to add these anytime you fix an issue with a commit. I'll add that and push it to drm-misc-next-fixes. Thanks, Daniel > > --- > > drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c > > b/drivers/gpu/drm/drm_atomic_state_helper.c > > index 3ba996069d69..709355c6bac6 100644 > > --- a/drivers/gpu/drm/drm_atomic_state_helper.c > > +++ b/drivers/gpu/drm/drm_atomic_state_helper.c > > @@ -241,6 +241,7 @@ void > > __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, > > > > state->fence = NULL; > > state->commit = NULL; > > + state->fb_damage_clips = NULL; > > } > > EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); > > > > @@ -285,6 +286,8 @@ void > > __drm_atomic_helper_plane_destroy_state(struct drm_plane_state > > *state) > > > > if (state->commit) > > drm_crtc_commit_put(state->commit); > > + > > + drm_property_blob_put(state->fb_damage_clips); > > } > > EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); > > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Expose more EDID fields to userspace
On Sun, Dec 23, 2018 at 09:16:13AM +, Simon Ser wrote:
> Hi all,
>
> Right now, the kernel parses EDIDs and exposes some of the data to
> userspace. For instance, drmModeConnector has mm{Width,Height} and
> subpixel.
>
> Generally, userspace also has another EDID parser. For instance,
> wlroots uses it just to get the make/model/serial. I've talked about
> this at XDC 2018, and someone mentioned it could be a good idea to
> de-duplicate the work.
Could have been me ...
> Would it be reasonable to expose those as DRM connector properties?
Yes, very much. Aside from the kernel-side implementation all we need is
the userspace per
https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html#open-source-userspace-requirements
Important: Don't merge the userspace side into your main branch before
it's all reviewed.
And ideally some igts (we have infrastructure to inject edids and hence
can check that the right stuff comes back):
https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html#testing-and-validation
Cheers, Daniel
>
> Thanks,
> --
> Simon Ser
> https://emersion.fr
>
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--
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http://blog.ffwll.ch
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Re: [PATCH] dma-buf: Change to use DEFINE_SHOW_ATTRIBUTE macro
On Fri, Nov 30, 2018 at 11:11:01AM -0500, Yangtao Li wrote:
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Yangtao Li
Sorry, fell through the cracks, applied for 4.22, thanks for your patch.
For next time around pls ping again after 1-2 weeks already, instead of
1-2 months.
Thanks, Daniel
> ---
> drivers/dma-buf/dma-buf.c| 12 +---
> drivers/dma-buf/sync_debug.c | 16 +++-
> 2 files changed, 4 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index 02f7f9a89979..7c858020d14b 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -1093,17 +1093,7 @@ static int dma_buf_debug_show(struct seq_file *s, void
> *unused)
> return 0;
> }
>
> -static int dma_buf_debug_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, dma_buf_debug_show, NULL);
> -}
> -
> -static const struct file_operations dma_buf_debug_fops = {
> - .open = dma_buf_debug_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release= single_release,
> -};
> +DEFINE_SHOW_ATTRIBUTE(dma_buf_debug);
>
> static struct dentry *dma_buf_debugfs_dir;
>
> diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c
> index c4c8ecb24aa9..c0abf37df88b 100644
> --- a/drivers/dma-buf/sync_debug.c
> +++ b/drivers/dma-buf/sync_debug.c
> @@ -147,7 +147,7 @@ static void sync_print_sync_file(struct seq_file *s,
> }
> }
>
> -static int sync_debugfs_show(struct seq_file *s, void *unused)
> +static int sync_info_debugfs_show(struct seq_file *s, void *unused)
> {
> struct list_head *pos;
>
> @@ -178,17 +178,7 @@ static int sync_debugfs_show(struct seq_file *s, void
> *unused)
> return 0;
> }
>
> -static int sync_info_debugfs_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, sync_debugfs_show, inode->i_private);
> -}
> -
> -static const struct file_operations sync_info_debugfs_fops = {
> - .open = sync_info_debugfs_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release= single_release,
> -};
> +DEFINE_SHOW_ATTRIBUTE(sync_info_debugfs);
>
> static __init int sync_debugfs_init(void)
> {
> @@ -218,7 +208,7 @@ void sync_dump(void)
> };
> int i;
>
> - sync_debugfs_show(, NULL);
> + sync_info_debugfs_show(, NULL);
>
> for (i = 0; i < s.count; i += DUMP_CHUNK) {
> if ((s.count - i) > DUMP_CHUNK) {
> --
> 2.17.0
>
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--
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http://blog.ffwll.ch
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drm-misc-next vs. drm-misc-next-fixes
Hi all,
Lukas mentioned that there's a few patches in drm-misc-next that
should be in drm-misc-next-fixes. I found only the following two:
70bce993a7aa ("drm/bochs: add edid present check")
2312f9842854 ("drm/v3d: fix broken build")
Others look like fixes for issues in drm-misc-next itself. I guess
good time to remind committers about where to put bugfixes around the
merge window:
https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-misc.html#where-do-i-apply-my-patch
Misplaced patches need to be cherry-picked over (with cherry-pick -x).
Also I guess the drm-misc-next-fixes maintainers should occasionally
check for misplaced patches, should probably add this here:
https://drm.pages.freedesktop.org/maintainer-tools/maintainer-drm-misc.html#maintainer-s-duties
Cheers, Daniel
--
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: DDI: call intel_psr_ and _edp_drrs_enable() on pipe updates (v2)
On Fri, Dec 21, 2018 at 8:42 PM Dhinakaran Pandiyan
wrote:
>
> On Thu, 2018-12-20 at 15:13 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-12-20 at 09:10 -0800, Rodrigo Vivi wrote:
> > > On Thu, Dec 20, 2018 at 02:21:20PM +0100, Hans de Goede wrote:
> > > > Call intel_psr_enable() and intel_edp_drrs_enable() on pipe
> > > > updates
> > > > to make
> > > > sure that we enable PSR / DRRS (when applicable) on fastsets.
> >
> > I am probably missing something, doesn't intel_pipe_config_compare()
> > need to check for pipe_config->has_psr? And also read the hardware
> > PSR
> > state at boot?
> Answering my own question here, pipe_config_compare() returns true
> lacking a comparison for ->has_psr. And we assume the bios does not
> enable PSR, so no need to read the hardware state.
pipe_config_compare is also a validation tool, ensuring that all the
various fastboot (and other modeset) transitions work. Not reading out
& not comparing state reduces validation coverage. Some exceptions
apply, but generally they should be justified with other test
coverage, not with "it works without that". Everything is supposed to
work without the validation tools/tests :-)
-Daniel
> > > >
> > > > Note calling these functions when PSR / DRRS has already been
> > > > enabled is a
> > > > no-op, so it is safe to do this on every encoder->update_pipe
> > > > callback.
> > > >
> > > > Changes in v2:
> > > > -Merge the patches adding the intel_psr_enable() and
> > > > intel_edp_drrs_enable()
> > > > calls into a single patch
> > > >
> > > > Reviewed-by: Maarten Lankhorst > > > >
> > > > Signed-off-by: Hans de Goede
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: José Roberto de Souza
> > >
> > > Acked-by: Rodrigo Vivi
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_ddi.c | 19 +++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index e3cc19e19199..fdf57f451b72 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -3537,6 +3537,24 @@ static void intel_disable_ddi(struct
> > > > intel_encoder *encoder,
> > > > intel_disable_ddi_dp(encoder, old_crtc_state,
> > > > old_conn_state);
> > > > }
> > > >
> > > > +static void intel_ddi_update_pipe_dp(struct intel_encoder
> > > > *encoder,
> > > > + const struct intel_crtc_state
> > > > *crtc_state,
> > > > + const struct drm_connector_state
> > > > *conn_state)
> > > > +{
> > > > + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> > > > +
> > > > + intel_psr_enable(intel_dp, crtc_state);
> > > > + intel_edp_drrs_enable(intel_dp, crtc_state);
> > > > +}
> > > > +
> > > > +static void intel_ddi_update_pipe(struct intel_encoder *encoder,
> > > > + const struct intel_crtc_state
> > > > *crtc_state,
> > > > + const struct drm_connector_state
> > > > *conn_state)
> > > > +{
> > > > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> >
> > We could restrict this to eDP outputs as both PSR and DRRS are eDP
> > features.
> >
> > > > + intel_ddi_update_pipe_dp(encoder, crtc_state,
> > > > conn_state);
> > > > +}
> > > > +
> > > > static void intel_ddi_set_fia_lane_count(struct intel_encoder
> > > > *encoder,
> > > >const struct intel_crtc_state
> > > > *pipe_config,
> > > >enum port port)
> > > > @@ -4169,6 +4187,7 @@ void intel_ddi_init(struct drm_i915_private
> > > > *dev_priv, enum port port)
> > > > intel_encoder->pre_enable = intel_ddi_pre_enable;
> > > > intel_encoder->disable = intel_disable_ddi;
> > > > intel_encoder->post_disable = intel_ddi_post_disable;
> > > > + intel_encoder->update_pipe = intel_ddi_update_pipe;
> > > > intel_encoder->get_hw_state = intel_ddi_get_hw_state;
> > > > intel_encoder->get_config = intel_ddi_get_config;
> > > > intel_encoder->suspend = intel_ddi_encoder_suspend;
> > > > --
> > > > 2.20.1
> > > >
>
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Re: [PATCH] drm/i915/psr: simplify enable_psr handling
On Fri, Dec 21, 2018 at 8:53 PM Ross Zwisler wrote:
>
> On Fri, Dec 21, 2018 at 11:23:07AM -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-12-21 at 10:23 -0700, Ross Zwisler wrote:
> > > The following commit:
> > >
> > > commit 2bdd045e3a30 ("drm/i915/psr: Check if VBT says PSR can be
> > > enabled.")
> > >
> > > added some code with no usable functionality. Regardless of how the
> > > psr
> > > default is set up in the BDB_DRIVER_FEATURES section, if the
> > > enable_psr
> > > module parameter isn't specified it defaults to 0.
> > Right, that was intentional and the commit message even makes a note of
> > it
> > " Note: The feature currently remains disabled by default for all
> > platforms irrespective of what VBT says."
> >
> >
> > Anyway, we've enabled the feature by default now and the current code
> > should take into account the VBT flag if the module parameter is left
> > to a default value. Please check git://anongit.freedesktop.org/drm-tip
> > drm-tip.
>
> Fair enough. It's a bad pattern to introduce dead code as a placeholder for
> some future work, though. This code has been in the tree for three major
> kernel releases (v4.{18,19,20}) without providing any useful functionality.
Getting PSR enabled by default on at least a few platforms took years.
Insisting that we do not ever merge such code also doesn't work.
-Daniel
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Re: [PATCH] drm/etnaviv: fix some off by one bugs
On Fri, Dec 21, 2018 at 9:24 PM Dan Carpenter wrote:
>
> I don't think anyone responded to this one?
Maybe time to move etnaviv into drm-misc so that there's a notch more
redundancy in maintainers? Lucas, Christian, others?
-Daniel
>
> regards,
> dan carpenter
>
> On Fri, Jul 13, 2018 at 06:00:18PM +0300, Dan Carpenter wrote:
> > The ->nr_signal is the supposed to be the number of elements in the
> > ->signal array. There was one place where it was 5 but it was supposed
> > to be 4. That looks like a copy and paste bug. There were also two
> > checks that were off by one.
> >
> > Fixes: 9e2c2e273012 ("drm/etnaviv: add infrastructure to query perf
> > counter")
> > Signed-off-by: Dan Carpenter
> > ---
> > Not tested.
> >
> > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> > b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> > index 9980d81a26e3..4227a4006c34 100644
> > --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> > +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> > @@ -113,7 +113,7 @@ static const struct etnaviv_pm_domain doms_3d[] = {
> > .name = "PE",
> > .profile_read = VIVS_MC_PROFILE_PE_READ,
> > .profile_config = VIVS_MC_PROFILE_CONFIG0,
> > - .nr_signals = 5,
> > + .nr_signals = 4,
> > .signal = (const struct etnaviv_pm_signal[]) {
> > {
> > "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
> > @@ -435,7 +435,7 @@ int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
> >
> > dom = meta->domains + signal->domain;
> >
> > - if (signal->iter > dom->nr_signals)
> > + if (signal->iter >= dom->nr_signals)
> > return -EINVAL;
> >
> > sig = >signal[signal->iter];
> > @@ -461,7 +461,7 @@ int etnaviv_pm_req_validate(const struct
> > drm_etnaviv_gem_submit_pmr *r,
> >
> > dom = meta->domains + r->domain;
> >
> > - if (r->signal > dom->nr_signals)
> > + if (r->signal >= dom->nr_signals)
> > return -EINVAL;
> >
> > return 0;
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Re: [PATCH v2 03/11] vga-switcheroo: make PCI dependency explicit
On Sun, Dec 23, 2018 at 6:15 PM Lukas Wunner wrote:
>
> On Sun, Dec 23, 2018 at 02:00:15AM +0300, Sinan Kaya wrote:
> > On Sat, Dec 22, 2018 at 7:40 PM Lukas Wunner wrote:
> > > On Sat, Dec 22, 2018 at 09:07:12AM +, Sinan Kaya wrote:
> > > > This driver depends on the PCI infrastructure but the dependency has not
> > > > been explicitly called out.
> > > >
> > > > Signed-off-by: Sinan Kaya
> > > > Reviewed-by: Lukas Wunner
> > >
> > > This series doesn't have a cover letter so it's unclear to me through
> > > which tree it's supposed to go in? Each patch through the individual
> > > subsystem tree or all through the same tree? If the former I guess I
> > > could push this to drm-misc...
> >
> > Feel free to apply individual patches independently. Let me know which
> > one you applied so that I can drop them on the next rev.
>
> I've realized only now that this patch fixes fallout of commit
> 5d32a66541c4 ("PCI/ACPI: Allow ACPI to be built without CONFIG_PCI set")
> which is part of Rafael's acpi pull for v4.21.
>
> Usually such fixes go through the same tree as the offending commit,
> so I'd expect Raphael to pick up the whole series and forward it to
> Linus in the second half of the merge window. I'm not sure if that's
> how it'll play out though given the holidays.
Yeah, best to get this merged through the tree that broke things.
Acked-by: Daniel Vetter for that.
> Additionally, drm-misc is currently in a somewhat confusing state:
> Normally fixes targeting v4.21 should have been applied to
> drm-misc-next-fixes for the last 2 weeks, yet no new commits have
> been applied to that branch since December 5, but plenty of stuff
> that should have been applied (various fixes and a MAINTAINERS change)
> went to drm-misc-next instead. So it looks like a lot of folks picked
> the wrong branch and drm-misc-next is now a mix of v4.22 features and
> v4.21 fixes. I think I should rather not add to this mess before a
> drm-misc maintainer has had a chance to sort it out.
If a patch has been misplaced the only way to fix it is to cherry-pick
it over. Hence no need to wait for maintainers to sort out anything if
you have patches for drm-misc-next-fixes, you can't make it worse :-)
> I'll be sure to keep an eye on this though. The fallout addressed by
> the patch is mostly confined to randconfigs I think, so waiting a few
> more days probably won't hurt much.
Agreed.
-Daniel
>
> Thanks,
>
> Lukas
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[PATCH 10/11] drm/komeda: Add sysfs attribute: core_id and config_id
Add two sysfs node: core_id, config_id, user can read them to fetch the
HW product information.
Signed-off-by: James (Qian) Wang
---
.../drm/arm/display/include/malidp_product.h | 12 +
.../gpu/drm/arm/display/komeda/komeda_dev.c | 48 +++
.../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
.../gpu/drm/arm/display/komeda/komeda_drv.c | 9 +++-
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/include/malidp_product.h
b/drivers/gpu/drm/arm/display/include/malidp_product.h
index b35fc5db866b..1053b11352eb 100644
--- a/drivers/gpu/drm/arm/display/include/malidp_product.h
+++ b/drivers/gpu/drm/arm/display/include/malidp_product.h
@@ -20,4 +20,16 @@
/* Mali-display product IDs */
#define MALIDP_D71_PRODUCT_ID 0x0071
+union komeda_config_id {
+ struct {
+ __u32 max_line_sz:16,
+ n_pipelines:2,
+ n_scalers:2, /* number of scalers per pipeline */
+ n_layers:3, /* number of layers per pipeline */
+ n_richs:3, /* number of rich layers per pipeline */
+ reserved_bits:6;
+ };
+ __u32 value;
+};
+
#endif /* _MALIDP_PRODUCT_H_ */
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
index 811f3617e893..8a0a78e1d1ff 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
@@ -56,6 +56,46 @@ static void komeda_debugfs_init(struct komeda_dev *mdev)
mdev, _register_fops);
}
+static ssize_t
+core_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct komeda_dev *mdev = dev_to_mdev(dev);
+
+ return snprintf(buf, PAGE_SIZE, "0x%08x\n", mdev->chip.core_id);
+}
+static DEVICE_ATTR_RO(core_id);
+
+static ssize_t
+config_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct komeda_dev *mdev = dev_to_mdev(dev);
+ struct komeda_pipeline *pipe = mdev->pipelines[0];
+ union komeda_config_id config_id = {0,};
+ int i;
+
+ config_id.max_line_sz = pipe->layers[0]->hsize_in.end;
+ config_id.n_pipelines = mdev->n_pipelines;
+ config_id.n_scalers = pipe->n_scalers;
+ config_id.n_layers = pipe->n_layers;
+ config_id.n_richs = 0;
+ for (i = 0; i < pipe->n_layers; i++) {
+ if (pipe->layers[i]->layer_type == KOMEDA_FMT_RICH_LAYER)
+ config_id.n_richs++;
+ }
+ return snprintf(buf, PAGE_SIZE, "0x%08x\n", config_id.value);
+}
+static DEVICE_ATTR_RO(config_id);
+
+static struct attribute *komeda_sysfs_entries[] = {
+ _attr_core_id.attr,
+ _attr_config_id.attr,
+ NULL,
+};
+
+static struct attribute_group komeda_sysfs_attr_group = {
+ .attrs = komeda_sysfs_entries,
+};
+
static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node
*np)
{
struct komeda_pipeline *pipe;
@@ -204,6 +244,12 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
goto err_cleanup;
}
+ err = sysfs_create_group(>kobj, _sysfs_attr_group);
+ if (err) {
+ DRM_ERROR("create sysfs group failed.\n");
+ goto err_cleanup;
+ }
+
#ifdef CONFIG_DEBUG_FS
komeda_debugfs_init(mdev);
#endif
@@ -221,6 +267,8 @@ void komeda_dev_destroy(struct komeda_dev *mdev)
struct komeda_dev_funcs *funcs = mdev->funcs;
int i;
+ sysfs_remove_group(>kobj, _sysfs_attr_group);
+
#ifdef CONFIG_DEBUG_FS
debugfs_remove_recursive(mdev->debugfs_root);
#endif
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
index 2beaa0d49c34..f237cd027717 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
@@ -191,4 +191,6 @@ d71_identify(u32 __iomem *reg, struct komeda_chip_info
*chip);
struct komeda_dev *komeda_dev_create(struct device *dev);
void komeda_dev_destroy(struct komeda_dev *mdev);
+struct komeda_dev *dev_to_mdev(struct device *dev);
+
#endif /*_KOMEDA_DEV_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
index d421d13e9742..ff7a095cf2aa 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
@@ -17,6 +17,13 @@ struct komeda_drv {
struct komeda_kms_dev *kms;
};
+struct komeda_dev *dev_to_mdev(struct device *dev)
+{
+ struct komeda_drv *mdrv = dev_get_drvdata(dev);
+
+ return mdrv ? mdrv->mdev : NULL;
+}
+
static void komeda_unbind(struct device *dev)
{
struct komeda_drv *mdrv = dev_get_drvdata(dev);
@@ -29,7 +36,7 @@ static void komeda_unbind(struct device *dev)
komeda_dev_destroy(mdrv->mdev);
[PATCH 11/11] drm/komeda: Expose bus_width to Komeda-CORE
CHIP set bus_width according to the HW configuration, and CORE will use
it as buffer alignment.
Signed-off-by: James (Qian) Wang
---
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c | 1 +
drivers/gpu/drm/arm/display/komeda/komeda_kms.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
index 31680bc0ccba..b5d7edf0870b 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
@@ -512,6 +512,7 @@ d71_identify(u32 __iomem *reg_base, struct komeda_chip_info
*chip)
chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
+ chip->bus_width = D71_BUS_WIDTH_16_BYTES;
return _chip_funcs;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
index ae97db7e447e..9ca24990495f 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
@@ -21,10 +21,10 @@ static int komeda_gem_cma_dumb_create(struct drm_file *file,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
- u32 alignment = 16; /* TODO get alignment from dev */
+ struct komeda_dev *mdev = dev->dev_private;
+ u32 pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
- args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8),
- alignment);
+ args->pitch = ALIGN(pitch, mdev->chip.bus_width);
return drm_gem_cma_dumb_create_internal(file, dev, args);
}
--
2.17.1
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[PATCH 09/11] drm/komeda: Add komeda_kms_check
Implement komeda_kms_check to add all affected_planes (even unchanged) to
drm_atomic_state. since komeda need to re-calculate the resources
assumption in every commit.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_kms.c | 30 ++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
index 210e5c05bf49..ae97db7e447e 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
@@ -95,9 +95,37 @@ static const struct drm_mode_config_helper_funcs
komeda_mode_config_helpers = {
.atomic_commit_tail = komeda_kms_commit_tail,
};
+static int komeda_kms_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_st, *new_crtc_st;
+ int i, err;
+
+ err = drm_atomic_helper_check_modeset(dev, state);
+ if (err)
+ return err;
+
+ /* komeda need to re-calculate resource assumption in every commit
+* so need to add all affected_planes (even unchanged) to
+* drm_atomic_state.
+*/
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_st, new_crtc_st, i)
{
+ err = drm_atomic_add_affected_planes(state, crtc);
+ if (err)
+ return err;
+ }
+
+ err = drm_atomic_helper_check_planes(dev, state);
+ if (err)
+ return err;
+
+ return 0;
+}
+
static const struct drm_mode_config_funcs komeda_mode_config_funcs = {
.fb_create = komeda_fb_create,
- .atomic_check = NULL,/*komeda_kms_check*/
+ .atomic_check = komeda_kms_check,
.atomic_commit = drm_atomic_helper_commit,
};
--
2.17.1
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[PATCH 06/11] drm/komeda: Add komeda_crtc_atomic_enable/disable
Pass enable/disable command to komeda and adjust komeda hardware for
enable/disable a display instance.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 102 +-
.../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
.../drm/arm/display/komeda/komeda_pipeline.h | 4 +
.../display/komeda/komeda_pipeline_state.c| 32 ++
4 files changed, 138 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 9c176ea59303..c76cd75a0100 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -157,9 +157,28 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
if (events & KOMEDA_EVENT_EOW)
DRM_INFO("EOW.\n");
- /* will handle it with crtc->flush */
- if (events & KOMEDA_EVENT_FLIP)
- DRM_INFO("FLIP Done.\n");
+ if (events & KOMEDA_EVENT_FLIP) {
+ unsigned long flags;
+ struct drm_pending_vblank_event *event;
+
+ spin_lock_irqsave(>dev->event_lock, flags);
+ if (kcrtc->disable_done) {
+ complete_all(kcrtc->disable_done);
+ kcrtc->disable_done = NULL;
+ } else if (crtc->state->event) {
+ event = crtc->state->event;
+ /*
+* Consume event before notifying drm core that flip
+* happened.
+*/
+ crtc->state->event = NULL;
+ drm_crtc_send_vblank_event(crtc, event);
+ } else {
+ DRM_WARN("CRTC[%d]: FLIP happen but no pending
commit.\n",
+drm_crtc_index(>base));
+ }
+ spin_unlock_irqrestore(>dev->event_lock, flags);
+ }
}
static void
@@ -183,6 +202,81 @@ komeda_crtc_do_flush(struct drm_crtc *crtc,
mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes);
}
+static void
+komeda_crtc_atomic_enable(struct drm_crtc *crtc,
+ struct drm_crtc_state *old)
+{
+ komeda_crtc_prepare(to_kcrtc(crtc));
+ drm_crtc_vblank_on(crtc);
+ komeda_crtc_do_flush(crtc, old);
+}
+
+static void
+komeda_crtc_atomic_disable(struct drm_crtc *crtc,
+ struct drm_crtc_state *old)
+{
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+ struct komeda_crtc_state *old_st = to_kcrtc_st(old);
+ struct komeda_dev *mdev = crtc->dev->dev_private;
+ struct komeda_pipeline *master = kcrtc->master;
+ struct completion *disable_done = >state->commit->flip_done;
+ struct completion temp;
+ int timeout;
+
+ DRM_DEBUG_ATOMIC("CRTC%d_DISABLE: active_pipes: 0x%x, affected:
0x%x.\n",
+drm_crtc_index(crtc),
+old_st->active_pipes, old_st->affected_pipes);
+
+ if (has_bit(master->id, old_st->active_pipes))
+ komeda_pipeline_disable(master, old->state);
+
+ /* crtc_disable has two scenarios according to the state->active switch.
+* 1. active -> inactive
+*this commit is a disable commit. and the commit will be finished
+*or done after the disable operation. on this case we can directly
+*use the crtc->state->event to tracking the HW disable operation.
+* 2. active -> active
+*the crtc->commit is not for disable, but a modeset operation when
+*crtc is active, such commit actually has been completed by 3
+*DRM operations:
+*crtc_disable, update_planes(crtc_flush), crtc_enable
+*so on this case the crtc->commit is for the whole process.
+*we can not use it for tracing the disable, we need a temporary
+*flip_done for tracing the disable. and crtc->state->event for
+*the crtc_enable operation.
+*That's also the reason why skip modeset commit in
+*komeda_crtc_atomic_flush()
+*/
+ if (crtc->state->active) {
+ struct komeda_pipeline_state *pipe_st;
+ /* clear the old active_comps to zero */
+ pipe_st = komeda_pipeline_get_old_state(master, old->state);
+ pipe_st->active_comps = 0;
+
+ init_completion();
+ kcrtc->disable_done =
+ disable_done =
+ }
+
+ mdev->funcs->flush(mdev, master->id, 0);
+
+ /* wait the disable take affect.*/
+ timeout = wait_for_completion_timeout(disable_done, HZ);
+ if (timeout == 0) {
+ DRM_ERROR("disable pipeline%d timeout.\n", kcrtc->master->id);
+ if (crtc->state->active) {
+ unsigned long flags;
+
+
[PATCH 07/11] drm/komeda: Add komeda_crtc_vblank_enable/disable
Add a new komeda_dev_func->on_off_vblank to enable/disable HW vblank event
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/d71/d71_dev.c | 10 ++
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 19 +++
.../gpu/drm/arm/display/komeda/komeda_dev.h | 3 +++
3 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
index 39b3c84cf483..31680bc0ccba 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
@@ -241,6 +241,15 @@ static int d71_disable_irq(struct komeda_dev *mdev)
return 0;
}
+static void d71_on_off_vblank(struct komeda_dev *mdev, int master_pipe, bool
on)
+{
+ struct d71_dev *d71 = mdev->chip_data;
+ struct d71_pipeline *pipe = d71->pipes[master_pipe];
+
+ malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
+ DOU_IRQ_PL0, on ? DOU_IRQ_PL0 : 0);
+}
+
static int to_d71_opmode(int core_mode)
{
switch (core_mode) {
@@ -492,6 +501,7 @@ static struct komeda_dev_funcs d71_chip_funcs = {
.irq_handler= d71_irq_handler,
.enable_irq = d71_enable_irq,
.disable_irq= d71_disable_irq,
+ .on_off_vblank = d71_on_off_vblank,
.change_opmode = d71_change_opmode,
.flush = d71_flush,
};
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index c76cd75a0100..6d9fb4626ba5 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -347,7 +347,26 @@ struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
.mode_fixup = komeda_crtc_mode_fixup,
};
+static int komeda_crtc_vblank_enable(struct drm_crtc *crtc)
+{
+ struct komeda_dev *mdev = crtc->dev->dev_private;
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+
+ mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, true);
+ return 0;
+}
+
+static void komeda_crtc_vblank_disable(struct drm_crtc *crtc)
+{
+ struct komeda_dev *mdev = crtc->dev->dev_private;
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+
+ mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false);
+}
+
static const struct drm_crtc_funcs komeda_crtc_funcs = {
+ .enable_vblank = komeda_crtc_vblank_enable,
+ .disable_vblank = komeda_crtc_vblank_disable,
};
int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
index 18dd82b09340..2beaa0d49c34 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
@@ -103,6 +103,9 @@ struct komeda_dev_funcs {
int (*enable_irq)(struct komeda_dev *mdev);
/** @disable_irq: disable irq */
int (*disable_irq)(struct komeda_dev *mdev);
+ /** @on_off_vblank: notify HW to on/off vblank */
+ void (*on_off_vblank)(struct komeda_dev *mdev,
+ int master_pipe, bool on);
/** @dump_register: Optional, dump registers to seq_file */
void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 08/11] drm/komeda: Add komeda_crtc_funcs
Added functions:
- komeda_crtc_reset
- komeda_crtc_vblank_enable
- komeda_crtc_vblank_disable
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 6d9fb4626ba5..cc7f67fb08fd 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -347,6 +347,47 @@ struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
.mode_fixup = komeda_crtc_mode_fixup,
};
+static void komeda_crtc_reset(struct drm_crtc *crtc)
+{
+ struct komeda_crtc_state *state;
+
+ if (crtc->state)
+ __drm_atomic_helper_crtc_destroy_state(crtc->state);
+
+ kfree(to_kcrtc_st(crtc->state));
+ crtc->state = NULL;
+
+ state = kzalloc(sizeof(*state), GFP_KERNEL);
+ if (state) {
+ crtc->state = >base;
+ crtc->state->crtc = crtc;
+ }
+}
+
+static struct drm_crtc_state *
+komeda_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
+{
+ struct komeda_crtc_state *old = to_kcrtc_st(crtc->state);
+ struct komeda_crtc_state *new;
+
+ new = kzalloc(sizeof(*new), GFP_KERNEL);
+ if (!new)
+ return NULL;
+
+ __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
+
+ new->affected_pipes = old->active_pipes;
+
+ return >base;
+}
+
+static void komeda_crtc_atomic_destroy_state(struct drm_crtc *crtc,
+struct drm_crtc_state *state)
+{
+ __drm_atomic_helper_crtc_destroy_state(state);
+ kfree(to_kcrtc_st(state));
+}
+
static int komeda_crtc_vblank_enable(struct drm_crtc *crtc)
{
struct komeda_dev *mdev = crtc->dev->dev_private;
@@ -365,6 +406,13 @@ static void komeda_crtc_vblank_disable(struct drm_crtc
*crtc)
}
static const struct drm_crtc_funcs komeda_crtc_funcs = {
+ .gamma_set = drm_atomic_helper_legacy_gamma_set,
+ .destroy= drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = komeda_crtc_reset,
+ .atomic_duplicate_state = komeda_crtc_atomic_duplicate_state,
+ .atomic_destroy_state = komeda_crtc_atomic_destroy_state,
.enable_vblank = komeda_crtc_vblank_enable,
.disable_vblank = komeda_crtc_vblank_disable,
};
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 03/11] drm/komeda: Add komeda_crtc_atomic_flush
A komeda flush is comprised two steps:
1. update pipeline/component state to HW.
2. call dev_func->flush to notify HW to kickoff the update.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/d71/d71_dev.c | 11 ++
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 33 +
.../gpu/drm/arm/display/komeda/komeda_dev.h | 3 ++
.../drm/arm/display/komeda/komeda_pipeline.h | 5 +++
.../display/komeda/komeda_pipeline_state.c| 37 +++
5 files changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
index 895603695d79..ecbcf26e8ad6 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
@@ -241,6 +241,16 @@ static int d71_disable_irq(struct komeda_dev *mdev)
return 0;
}
+static void d71_flush(struct komeda_dev *mdev,
+ int master_pipe, u32 active_pipes)
+{
+ struct d71_dev *d71 = mdev->chip_data;
+ u32 reg_offset = (master_pipe == 0) ?
+GCU_CONFIG_VALID0 : GCU_CONFIG_VALID1;
+
+ malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);
+}
+
static int d71_reset(struct d71_dev *d71)
{
u32 __iomem *gcu = d71->gcu_addr;
@@ -451,6 +461,7 @@ static struct komeda_dev_funcs d71_chip_funcs = {
.irq_handler= d71_irq_handler,
.enable_irq = d71_enable_irq,
.disable_irq= d71_disable_irq,
+ .flush = d71_flush,
};
struct komeda_dev_funcs *
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index f84024aae155..b4640971e47e 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -58,8 +58,41 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
DRM_INFO("FLIP Done.\n");
}
+static void
+komeda_crtc_do_flush(struct drm_crtc *crtc,
+struct drm_crtc_state *old)
+{
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+ struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc->state);
+ struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
+ struct komeda_pipeline *master = kcrtc->master;
+
+ DRM_DEBUG_ATOMIC("CRTC%d_FLUSH: active_pipes: 0x%x, affected: 0x%x.\n",
+drm_crtc_index(crtc),
+kcrtc_st->active_pipes, kcrtc_st->affected_pipes);
+
+ /* step 1: update the pipeline/component state to HW */
+ if (has_bit(master->id, kcrtc_st->affected_pipes))
+ komeda_pipeline_update(master, old->state);
+
+ /* step 2: notify the HW to kickoff the update */
+ mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes);
+}
+
+static void
+komeda_crtc_atomic_flush(struct drm_crtc *crtc,
+struct drm_crtc_state *old)
+{
+ /* commit with modeset will be handled in enable/disable */
+ if (drm_atomic_crtc_needs_modeset(crtc->state))
+ return;
+
+ komeda_crtc_do_flush(crtc, old);
+}
+
struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
.atomic_check = komeda_crtc_atomic_check,
+ .atomic_flush = komeda_crtc_atomic_flush,
};
static const struct drm_crtc_funcs komeda_crtc_funcs = {
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
index 5f96d2f57c4e..686ce97ce30f 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.h
@@ -106,6 +106,9 @@ struct komeda_dev_funcs {
/** @dump_register: Optional, dump registers to seq_file */
void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
+ /** @flush: Notify the HW to flush or kickoff the update */
+ void (*flush)(struct komeda_dev *mdev,
+ int master_pipe, u32 active_pipes);
};
/**
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index 9a17d0152021..9a96ee906a36 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -421,4 +421,9 @@ int komeda_build_display_data_flow(struct komeda_crtc
*kcrtc,
int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe,
struct komeda_crtc_state *kcrtc_st);
+void komeda_pipeline_disable(struct komeda_pipeline *pipe,
+struct drm_atomic_state *old_state);
+void komeda_pipeline_update(struct komeda_pipeline *pipe,
+ struct drm_atomic_state *old_state);
+
#endif /* _KOMEDA_PIPELINE_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 920d2b40e9cc..19d8ed904bf7
[PATCH 02/11] drm/komeda: Add komeda_release_unclaimed_resources
Komeda driver treats KMS-CRTC/PLANE as user which will acquire pipeline
resources, but we still need to release the unclaimed resources.
crtc_atomic_check is the final check stage, so beside build a display data
pipeline according the crtc_state, but still needs to release/disable the
unclaimed pipeline resources.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 27 +
.../drm/arm/display/komeda/komeda_pipeline.h | 3 +
.../display/komeda/komeda_pipeline_state.c| 58 +++
3 files changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index c896e46203ed..f84024aae155 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -14,6 +14,32 @@
#include "komeda_dev.h"
#include "komeda_kms.h"
+/* crtc_atomic_check is the final check stage, so beside build a display data
+ * pipeline according the crtc_state, but still needs to release/disable the
+ * unclaimed pipeline resources.
+ */
+static int
+komeda_crtc_atomic_check(struct drm_crtc *crtc,
+struct drm_crtc_state *state)
+{
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+ struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state);
+ int err;
+
+ if (state->active) {
+ err = komeda_build_display_data_flow(kcrtc, kcrtc_st);
+ if (err)
+ return err;
+ }
+
+ /* release unclaimed pipeline resources */
+ err = komeda_release_unclaimed_resources(kcrtc->master, kcrtc_st);
+ if (err)
+ return err;
+
+ return 0;
+}
+
void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
struct komeda_events *evts)
{
@@ -33,6 +59,7 @@ void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
}
struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
+ .atomic_check = komeda_crtc_atomic_check,
};
static const struct drm_crtc_funcs komeda_crtc_funcs = {
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index bc4ed1513348..9a17d0152021 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -418,4 +418,7 @@ int komeda_build_layer_data_flow(struct komeda_layer *layer,
int komeda_build_display_data_flow(struct komeda_crtc *kcrtc,
struct komeda_crtc_state *kcrtc_st);
+int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe,
+ struct komeda_crtc_state *kcrtc_st);
+
#endif /* _KOMEDA_PIPELINE_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 05386e9d1749..920d2b40e9cc 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -42,6 +42,18 @@ komeda_pipeline_get_state(struct komeda_pipeline *pipe,
return priv_to_pipe_st(priv_st);
}
+struct komeda_pipeline_state *
+komeda_pipeline_get_new_state(struct komeda_pipeline *pipe,
+ struct drm_atomic_state *state)
+{
+ struct drm_private_state *priv_st;
+
+ priv_st = drm_atomic_get_new_private_obj_state(state, >obj);
+ if (priv_st)
+ return priv_to_pipe_st(priv_st);
+ return NULL;
+}
+
/* Assign a pipeline crtc */
struct komeda_pipeline_state *
komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe,
@@ -478,3 +490,49 @@ int komeda_build_display_data_flow(struct komeda_crtc
*kcrtc,
return 0;
}
+
+void komeda_pipeline_unbound_components(struct komeda_pipeline *pipe,
+ struct komeda_pipeline_state *new)
+{
+ struct drm_atomic_state *drm_st = new->obj.state;
+ struct komeda_pipeline_state *old = priv_to_pipe_st(pipe->obj.state);
+ struct komeda_component_state *c_st;
+ struct komeda_component *c;
+ u32 disabling_comps, id;
+
+ WARN_ON(!old);
+
+ disabling_comps = (~new->active_comps) & old->active_comps;
+
+ /* unbound all disabling component */
+ dp_for_each_set_bit(id, disabling_comps) {
+ c = komeda_pipeline_get_component(pipe, id);
+ c_st = komeda_component_get_state_and_set_user(c,
+ drm_st, NULL, new->crtc);
+ WARN_ON(IS_ERR(c_st));
+ }
+}
+
+/* release unclaimed pipeline resource */
+int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe,
+ struct komeda_crtc_state *kcrtc_st)
+{
+ struct drm_atomic_state *drm_st = kcrtc_st->base.state;
+ struct komeda_pipeline_state *st;
+
+ /* ignore the pipeline which is
[PATCH 05/11] drm/komeda: Add komeda_crtc_prepare/unprepare
These two function will be used by komeda_crtc_enable/disable to do some
prepartion works when enable/disable a crtc. like enable a crtc:
1. Adjust display operation mode.
2. Enable/prepare needed clk.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/d71/d71_dev.c | 32 ++
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 104 ++
.../gpu/drm/arm/display/komeda/komeda_dev.c | 2 +
.../gpu/drm/arm/display/komeda/komeda_dev.h | 27 +
4 files changed, 165 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
index ecbcf26e8ad6..39b3c84cf483 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
@@ -241,6 +241,37 @@ static int d71_disable_irq(struct komeda_dev *mdev)
return 0;
}
+static int to_d71_opmode(int core_mode)
+{
+ switch (core_mode) {
+ case KOMEDA_MODE_DISP0:
+ return DO0_ACTIVE_MODE;
+ case KOMEDA_MODE_DISP1:
+ return DO1_ACTIVE_MODE;
+ case KOMEDA_MODE_DUAL_DISP:
+ return DO01_ACTIVE_MODE;
+ case KOMEDA_MODE_INACTIVE:
+ return INACTIVE_MODE;
+ default:
+ WARN(1, "Unknown operation mode");
+ return INACTIVE_MODE;
+ }
+}
+
+static int d71_change_opmode(struct komeda_dev *mdev, int new_mode)
+{
+ struct d71_dev *d71 = mdev->chip_data;
+ u32 opmode = to_d71_opmode(new_mode);
+ int ret;
+
+ malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode);
+
+ ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7)
== opmode),
+ 100, 1000, 1);
+
+ return ret > 0 ? 0 : -ETIMEDOUT;
+}
+
static void d71_flush(struct komeda_dev *mdev,
int master_pipe, u32 active_pipes)
{
@@ -461,6 +492,7 @@ static struct komeda_dev_funcs d71_chip_funcs = {
.irq_handler= d71_irq_handler,
.enable_irq = d71_enable_irq,
.disable_irq= d71_disable_irq,
+ .change_opmode = d71_change_opmode,
.flush = d71_flush,
};
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index 05bdff137e50..9c176ea59303 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -40,6 +40,110 @@ komeda_crtc_atomic_check(struct drm_crtc *crtc,
return 0;
}
+u32 komeda_calc_mclk(struct komeda_crtc_state *kcrtc_st)
+{
+ unsigned long mclk = kcrtc_st->base.adjusted_mode.clock * 1000;
+
+ return mclk;
+}
+
+/* For active a crtc, mainly need two parts of preparation
+ * 1. adjust display operation mode.
+ * 2. enable needed clk
+ */
+static int
+komeda_crtc_prepare(struct komeda_crtc *kcrtc)
+{
+ struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
+ struct komeda_pipeline *master = kcrtc->master;
+ struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state);
+ unsigned long pxlclk_rate = kcrtc_st->base.adjusted_mode.clock * 1000;
+ u32 new_mode;
+ int err;
+
+ mutex_lock(>lock);
+
+ new_mode = mdev->dpmode | BIT(master->id);
+ if (WARN_ON(new_mode == mdev->dpmode)) {
+ err = 0;
+ goto unlock;
+ }
+
+ err = mdev->funcs->change_opmode(mdev, new_mode);
+ if (err) {
+ DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,",
+ mdev->dpmode, new_mode);
+ goto unlock;
+ }
+
+ mdev->dpmode = new_mode;
+ /* Only need to enable mclk on single display mode, but no need to
+* enable mclk it on dual display mode, since the dual mode always
+* switch from single display mode, the mclk already enabled, no need
+* to enable it again.
+*/
+ if (new_mode != KOMEDA_MODE_DUAL_DISP) {
+ err = clk_set_rate(mdev->mclk, komeda_calc_mclk(kcrtc_st));
+ if (err)
+ DRM_ERROR("failed to set mclk.\n");
+ err = clk_prepare_enable(mdev->mclk);
+ if (err)
+ DRM_ERROR("failed to enable mclk.\n");
+ }
+
+ err = clk_prepare_enable(master->aclk);
+ if (err)
+ DRM_ERROR("failed to enable axi clk for pipe%d.\n", master->id);
+ err = clk_set_rate(master->pxlclk, pxlclk_rate);
+ if (err)
+ DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id);
+ err = clk_prepare_enable(master->pxlclk);
+ if (err)
+ DRM_ERROR("failed to enable pxl clk for pipe%d.\n", master->id);
+
+unlock:
+ mutex_unlock(>lock);
+
+ return err;
+}
+
+static int
+komeda_crtc_unprepare(struct komeda_crtc *kcrtc)
+{
+ struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
+ struct
[PATCH 01/11] drm/komeda: Add komeda_build_display_data_flow
This function builds a display output pipeline according to crtc_state.
And this change only added single pipeline support, the dual pipeline with
slave enabled data flow support will be added in the following change.
Signed-off-by: James (Qian) Wang
---
.../drm/arm/display/komeda/komeda_pipeline.h | 3 +
.../display/komeda/komeda_pipeline_state.c| 72 +++
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index c78edfc6ed5b..bc4ed1513348 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -408,11 +408,14 @@ void komeda_component_destroy(struct komeda_dev *mdev,
struct komeda_plane_state;
struct komeda_crtc_state;
+struct komeda_crtc;
int komeda_build_layer_data_flow(struct komeda_layer *layer,
struct komeda_component_output *dflow,
struct komeda_plane_state *kplane_st,
struct komeda_crtc_state *kcrtc_st,
struct komeda_layer_viewport *vp);
+int komeda_build_display_data_flow(struct komeda_crtc *kcrtc,
+ struct komeda_crtc_state *kcrtc_st);
#endif /* _KOMEDA_PIPELINE_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index b98163211cfd..05386e9d1749 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -380,6 +380,51 @@ int komeda_compiz_validate(struct komeda_compiz *compiz,
return 0;
}
+int komeda_improc_validate(struct komeda_improc *improc,
+ struct komeda_component_output *input,
+ struct komeda_component_output *slave_in,
+ struct komeda_crtc_state *kcrtc_st)
+{
+ struct drm_crtc *crtc = kcrtc_st->base.crtc;
+ struct komeda_component_state *c_st;
+ struct komeda_improc_state *st;
+
+ c_st = komeda_component_get_state_and_set_user(>base,
+ kcrtc_st->base.state, crtc, crtc);
+ if (IS_ERR(c_st))
+ return PTR_ERR(c_st);
+
+ st = to_improc_st(c_st);
+
+ pipeline_composition_size(kcrtc_st, >hsize, >vsize);
+
+ komeda_component_add_input(>base, input, 0);
+ komeda_component_set_output(input, >base, 0);
+
+ return 0;
+}
+
+int komeda_timing_ctrlr_validate(struct komeda_timing_ctrlr *ctrlr,
+struct komeda_component_output *input,
+struct komeda_crtc_state *kcrtc_st)
+{
+ struct drm_crtc *crtc = kcrtc_st->base.crtc;
+ struct komeda_timing_ctrlr_state *st;
+ struct komeda_component_state *c_st;
+
+ c_st = komeda_component_get_state_and_set_user(>base,
+ kcrtc_st->base.state, crtc, crtc);
+ if (IS_ERR(c_st))
+ return PTR_ERR(c_st);
+
+ st = to_ctrlr_st(c_st);
+
+ komeda_component_add_input(>base, input, 0);
+ komeda_component_set_output(input, >base, 0);
+
+ return 0;
+}
+
int komeda_build_layer_data_flow(struct komeda_layer *layer,
struct komeda_component_output *dflow,
struct komeda_plane_state *kplane_st,
@@ -406,3 +451,30 @@ int komeda_build_layer_data_flow(struct komeda_layer
*layer,
return err;
}
+
+/* build display output data flow, the data path is:
+ * compiz -> improc -> timing_ctrlr
+ */
+int komeda_build_display_data_flow(struct komeda_crtc *kcrtc,
+ struct komeda_crtc_state *kcrtc_st)
+{
+ struct komeda_pipeline *master = kcrtc->master;
+ struct komeda_component_output m_dflow; /* master data flow */
+ int err;
+
+ memset(_dflow, 0, sizeof(m_dflow));
+
+ err = komeda_compiz_validate(master->compiz, _dflow, kcrtc_st, NULL);
+ if (err)
+ return err;
+
+ err = komeda_improc_validate(master->improc, _dflow, NULL, kcrtc_st);
+ if (err)
+ return err;
+
+ err = komeda_timing_ctrlr_validate(master->ctrlr, _dflow, kcrtc_st);
+ if (err)
+ return err;
+
+ return 0;
+}
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 04/11] drm/komeda: Add komeda_crtc_mode_valid/fixup
komeda_crtc_mode_valid compares the input mode->clk with main engine clk
and AXI clk, and reject the mode if the required pixel clk can not be
satisfied by main engine clk and AXI-clk.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
index b4640971e47e..05bdff137e50 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -90,9 +90,61 @@ komeda_crtc_atomic_flush(struct drm_crtc *crtc,
komeda_crtc_do_flush(crtc, old);
}
+static enum drm_mode_status
+komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
+{
+ struct komeda_dev *mdev = crtc->dev->dev_private;
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+ struct komeda_pipeline *master = kcrtc->master;
+ long mode_clk, pxlclk;
+
+ if (m->flags & DRM_MODE_FLAG_INTERLACE)
+ return MODE_NO_INTERLACE;
+
+ /* main clock/AXI clk must be faster than pxlclk*/
+ mode_clk = m->clock * 1000;
+ pxlclk = clk_round_rate(master->pxlclk, mode_clk);
+ if (pxlclk != mode_clk) {
+ DRM_DEBUG_ATOMIC("pxlclk doesn't support %ld Hz\n", mode_clk);
+
+ return MODE_NOCLOCK;
+ }
+
+ if (clk_round_rate(mdev->mclk, mode_clk) < pxlclk) {
+ DRM_DEBUG_ATOMIC("mclk can't satisfy the requirement of %s-clk:
%ld.\n",
+m->name, pxlclk);
+
+ return MODE_CLOCK_HIGH;
+ }
+
+ if (clk_round_rate(master->aclk, mode_clk) < pxlclk) {
+ DRM_DEBUG_ATOMIC("aclk can't satisfy the requirement of %s-clk:
%ld.\n",
+m->name, pxlclk);
+
+ return MODE_CLOCK_HIGH;
+ }
+
+ return MODE_OK;
+}
+
+static bool komeda_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *m,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct komeda_crtc *kcrtc = to_kcrtc(crtc);
+ struct komeda_pipeline *master = kcrtc->master;
+ long mode_clk = m->clock * 1000;
+
+ adjusted_mode->clock = clk_round_rate(master->pxlclk, mode_clk) / 1000;
+
+ return true;
+}
+
struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
.atomic_check = komeda_crtc_atomic_check,
.atomic_flush = komeda_crtc_atomic_flush,
+ .mode_valid = komeda_crtc_mode_valid,
+ .mode_fixup = komeda_crtc_mode_fixup,
};
static const struct drm_crtc_funcs komeda_crtc_funcs = {
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 00/11] Implement komeda DRM-Crtc
This is the 4th patchset for komeda-driver, with this patchset the driver can bring up and enable the D71 support with basic features. This patchset implemented komeda_crtc/crtc_helper functions for DRM-crtc. James (Qian) Wang (11): drm/komeda: Add komeda_build_display_data_flow drm/komeda: Add komeda_release_unclaimed_resources drm/komeda: Add komeda_crtc_atomic_flush drm/komeda: Add komeda_crtc_mode_valid/fixup drm/komeda: Add komeda_crtc_prepare/unprepare drm/komeda: Add komeda_crtc_atomic_enable/disable drm/komeda: Add komeda_crtc_vblank_enable/disable drm/komeda: Add komeda_crtc_funcs drm/komeda: Add komeda_kms_check drm/komeda: Add sysfs attribute: core_id and config_id drm/komeda: Expose bus_width to Komeda-CORE .../drm/arm/display/include/malidp_product.h | 12 + .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 54 +++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 385 +- .../gpu/drm/arm/display/komeda/komeda_dev.c | 50 +++ .../gpu/drm/arm/display/komeda/komeda_dev.h | 35 ++ .../gpu/drm/arm/display/komeda/komeda_drv.c | 9 +- .../gpu/drm/arm/display/komeda/komeda_kms.c | 36 +- .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 + .../drm/arm/display/komeda/komeda_pipeline.h | 15 + .../display/komeda/komeda_pipeline_state.c| 199 + 10 files changed, 790 insertions(+), 8 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 5/5] drm/komeda: Add komeda_plane/plane_helper_funcs
Per komeda design KMS-plane maps to komeda layer input pipeline.
komeda_plane_atomic_check is for building a komeda layer input pipeline.
And KMS-plane is only a user of komeda resources. so there is no real HW
update for plane, but all HW update will be handled in crtc->flush.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_plane.c | 129 ++
1 file changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
index 0a4953a9a909..522b0600 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
@@ -10,7 +10,83 @@
#include "komeda_dev.h"
#include "komeda_kms.h"
+int komeda_prepare_viewport(struct drm_plane_state *st,
+ struct komeda_layer_viewport *view)
+{
+ struct drm_framebuffer *fb = st->fb;
+
+ memset(view, 0, sizeof(*view));
+
+ view->blending_zorder = st->zpos;
+
+ /* if format doesn't have alpha, fix blend mode to PIXEL_NONE */
+ view->pixel_blend_mode = fb->format->has_alpha ?
+ st->pixel_blend_mode : DRM_MODE_BLEND_PIXEL_NONE;
+ view->layer_alpha = st->alpha >> 8;
+
+ view->out_x = st->crtc_x;
+ view->out_y = st->crtc_y;
+ view->out_w = st->crtc_w;
+ view->out_h = st->crtc_h;
+
+ view->in_x = st->src_x >> 16;
+ view->in_y = st->src_y >> 16;
+ view->in_w = st->src_w >> 16;
+ view->in_h = st->src_h >> 16;
+
+ return 0;
+}
+
+int komeda_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct komeda_plane *kplane = to_kplane(plane);
+ struct komeda_plane_state *kplane_st = to_kplane_st(state);
+ struct komeda_layer *layer = kplane->layer;
+ struct drm_crtc_state *crtc_st;
+ struct komeda_crtc *kcrtc;
+ struct komeda_crtc_state *kcrtc_st;
+ struct komeda_layer_viewport view;
+ struct komeda_component_output dflow;
+ int err;
+
+ if (!state->crtc || !state->fb)
+ return 0;
+
+ crtc_st = drm_atomic_get_crtc_state(state->state, state->crtc);
+ if (!crtc_st->enable) {
+ DRM_DEBUG_ATOMIC("Cannot update plane on a disabled CRTC.\n");
+ return -EINVAL;
+ }
+
+ /* crtc is inactive, skip the resource assignment */
+ if (!crtc_st->active)
+ return 0;
+
+ kcrtc = to_kcrtc(state->crtc);
+ kcrtc_st = to_kcrtc_st(crtc_st);
+
+ err = komeda_prepare_viewport(state, );
+ if (err)
+ return err;
+
+ err = komeda_build_layer_data_flow(layer, ,
+ kplane_st, kcrtc_st, );
+
+ return err;
+}
+
+/* plane doesn't represent a real HW, so there is no HW update for plane.
+ * komeda handles all the HW update in crtc->atomic_flush
+ */
+void komeda_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+}
+
static const struct drm_plane_helper_funcs komeda_plane_helper_funcs = {
+ .atomic_check = komeda_plane_atomic_check,
+ .atomic_update = komeda_plane_atomic_update,
};
static void komeda_plane_destroy(struct drm_plane *plane)
@@ -20,7 +96,60 @@ static void komeda_plane_destroy(struct drm_plane *plane)
kfree(to_kplane(plane));
}
+static void komeda_plane_reset(struct drm_plane *plane)
+{
+ struct komeda_plane_state *state;
+ struct komeda_plane *kplane = to_kplane(plane);
+
+ if (plane->state)
+ __drm_atomic_helper_plane_destroy_state(plane->state);
+
+ kfree(plane->state);
+ plane->state = NULL;
+
+ state = kzalloc(sizeof(*state), GFP_KERNEL);
+ if (state) {
+ state->base.rotation = DRM_MODE_ROTATE_0;
+ state->base.pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
+ state->base.alpha = DRM_BLEND_ALPHA_OPAQUE;
+ state->base.zpos = kplane->layer->base.id;
+ plane->state = >base;
+ plane->state->plane = plane;
+ }
+}
+
+static struct drm_plane_state *
+komeda_plane_atomic_duplicate_state(struct drm_plane *plane)
+{
+ struct komeda_plane_state *new;
+
+ if (WARN_ON(!plane->state))
+ return NULL;
+
+ new = kzalloc(sizeof(*new), GFP_KERNEL);
+ if (!new)
+ return NULL;
+
+ __drm_atomic_helper_plane_duplicate_state(plane, >base);
+
+ return >base;
+}
+
+static void
+komeda_plane_atomic_destroy_state(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ __drm_atomic_helper_plane_destroy_state(state);
+ kfree(to_kplane_st(state));
+}
+
static const struct drm_plane_funcs komeda_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane
[PATCH 2/5] drm/komeda: Add komeda_pipeline/component_get_state_and_set_user
get_state_and_set_user packed get_state and set_user into one function,
which get pipeline/component state for a specific pipeline/component, if
success set the user to it.
Signed-off-by: James (Qian) Wang
---
drivers/gpu/drm/arm/display/komeda/Makefile | 1 +
.../drm/arm/display/komeda/komeda_pipeline.c | 2 +
.../drm/arm/display/komeda/komeda_pipeline.h | 7 +
.../display/komeda/komeda_pipeline_state.c| 148 ++
4 files changed, 158 insertions(+)
create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
b/drivers/gpu/drm/arm/display/komeda/Makefile
index d593125236ae..62bd1bff66a3 100644
--- a/drivers/gpu/drm/arm/display/komeda/Makefile
+++ b/drivers/gpu/drm/arm/display/komeda/Makefile
@@ -9,6 +9,7 @@ komeda-y := \
komeda_dev.o \
komeda_format_caps.o \
komeda_pipeline.o \
+ komeda_pipeline_state.o \
komeda_framebuffer.o \
komeda_kms.o \
komeda_crtc.o \
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
index 611e8c53e248..1c9205d0e61b 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
@@ -34,6 +34,8 @@ komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
pipe->id = mdev->n_pipelines;
pipe->funcs = funcs;
+ drm_modeset_lock_init(>mutex);
+
mdev->pipelines[mdev->n_pipelines] = pipe;
mdev->n_pipelines++;
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index 4f98fdb21557..201fcf074fa1 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -295,6 +295,13 @@ struct komeda_pipeline_funcs {
struct komeda_pipeline {
/** @obj: link pipeline as private obj of drm_atomic_state */
struct drm_private_obj obj;
+
+ /**
+* @mutex:
+*
+* protects pipeline_state, since pipeline can be shared between crtcs
+*/
+ struct drm_modeset_lock mutex;
/** @mdev: the parent komeda_dev */
struct komeda_dev *mdev;
/** @pxlclk: pixel clock */
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
new file mode 100644
index ..7ce006b9e5f7
--- /dev/null
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
+ * Author: James.Qian.Wang
+ *
+ */
+#include
+#include "komeda_dev.h"
+#include "komeda_kms.h"
+#include "komeda_pipeline.h"
+
+static inline bool is_switching_user(void *old, void *new)
+{
+ if (!old || !new)
+ return false;
+
+ return old != new;
+}
+
+struct komeda_pipeline_state *
+komeda_pipeline_get_state(struct komeda_pipeline *pipe,
+ struct drm_atomic_state *state)
+{
+ struct drm_private_state *priv_st;
+ int err;
+
+ WARN_ON(!state->acquire_ctx);
+
+ priv_st = drm_atomic_get_new_private_obj_state(state, >obj);
+ if (priv_st)
+ return priv_to_pipe_st(priv_st);
+
+ err = drm_modeset_lock(>mutex, state->acquire_ctx);
+ if (err)
+ return ERR_PTR(err);
+
+ priv_st = drm_atomic_get_private_obj_state(state, >obj);
+ if (IS_ERR(priv_st))
+ return ERR_CAST(priv_st);
+
+ return priv_to_pipe_st(priv_st);
+}
+
+/* Assign a pipeline crtc */
+struct komeda_pipeline_state *
+komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe,
+ struct drm_atomic_state *state,
+ struct drm_crtc *crtc)
+{
+ struct komeda_pipeline_state *st;
+
+ st = komeda_pipeline_get_state(pipe, state);
+ if (IS_ERR(st))
+ return st;
+
+ if (is_switching_user(crtc, st->crtc)) {
+ DRM_DEBUG_ATOMIC("CRTC%d required pipeline%d is busy.\n",
+drm_crtc_index(crtc), pipe->id);
+ return ERR_PTR(-EBUSY);
+ }
+
+ /* pipeline only can be disabled when the it is free or unused */
+ if (!crtc && st->active_comps) {
+ DRM_DEBUG_ATOMIC("Disabling a busy pipeline:%d.\n", pipe->id);
+ return ERR_PTR(-EBUSY);
+ }
+
+ st->crtc = crtc;
+
+ if (crtc) {
+ struct komeda_crtc_state *kcrtc_st;
+
+ kcrtc_st = to_kcrtc_st(drm_atomic_get_new_crtc_state(state,
+crtc));
+
+ kcrtc_st->active_pipes |= BIT(pipe->id);
+ kcrtc_st->affected_pipes |= BIT(pipe->id);
+ }
+ return
[PATCH 4/5] drm/komeda: Add komeda_build_layer_data_flow
build_layer_data_flow builds a input pipeline according to plane_state.
and in this initial stage only added this simplest pipeline usage:
Layer -> compiz
The scaler and layer_split will be added in the future.
Signed-off-by: James (Qian) Wang
---
.../drm/arm/display/komeda/komeda_pipeline.h | 24 ++
.../display/komeda/komeda_pipeline_state.c| 260 ++
2 files changed, 284 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index 201fcf074fa1..c78edfc6ed5b 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -280,6 +280,21 @@ struct komeda_timing_ctrlr_state {
struct komeda_component_state base;
};
+/* Why define A separated structure but not use plane_state directly ?
+ * 1. Komeda supports layer_split which means a plane_state can be split and
+ *handled by two layers, one layer only handle half of plane image.
+ * 2. Fix up the user properties according to HW's capabilities, like user
+ *set rotation to R180, but HW only supports REFLECT_X+Y. the rot here is
+ *after drm_rotation_simplify()
+ */
+struct komeda_layer_viewport {
+ u16 in_x, in_y, in_w, in_h;
+ u32 out_x, out_y, out_w, out_h;
+ u32 rot;
+ int blending_zorder;
+ u8 pixel_blend_mode, layer_alpha;
+};
+
/** struct komeda_pipeline_funcs */
struct komeda_pipeline_funcs {
/* dump_register: Optional, dump registers to seq_file */
@@ -391,4 +406,13 @@ komeda_component_add(struct komeda_pipeline *pipe,
void komeda_component_destroy(struct komeda_dev *mdev,
struct komeda_component *c);
+struct komeda_plane_state;
+struct komeda_crtc_state;
+
+int komeda_build_layer_data_flow(struct komeda_layer *layer,
+struct komeda_component_output *dflow,
+struct komeda_plane_state *kplane_st,
+struct komeda_crtc_state *kcrtc_st,
+struct komeda_layer_viewport *vp);
+
#endif /* _KOMEDA_PIPELINE_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 7ce006b9e5f7..b98163211cfd 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -8,6 +8,7 @@
#include "komeda_dev.h"
#include "komeda_kms.h"
#include "komeda_pipeline.h"
+#include "komeda_framebuffer.h"
static inline bool is_switching_user(void *old, void *new)
{
@@ -89,6 +90,18 @@ komeda_component_get_state(struct komeda_component *c,
>obj));
}
+static struct komeda_component_state *
+komeda_component_get_old_state(struct komeda_component *c,
+ struct drm_atomic_state *state)
+{
+ struct drm_private_state *priv_st;
+
+ priv_st = drm_atomic_get_old_private_obj_state(state, >obj);
+ if (priv_st)
+ return priv_to_comp_st(priv_st);
+ return NULL;
+}
+
/**
* komeda_component_get_state_and_set_user()
*
@@ -146,3 +159,250 @@ komeda_component_get_state_and_set_user(struct
komeda_component *c,
return st;
}
+
+static void
+komeda_component_add_input(struct komeda_component_state *state,
+ struct komeda_component_output *input,
+ int idx)
+{
+ struct komeda_component *c = state->component;
+
+ WARN_ON((idx < 0 || idx >= c->max_active_inputs));
+
+ /* since the inputs[i] is only valid when it is active. So if a input[i]
+* is a newly enabled input which switches from disable to enable, then
+* the old inputs[i] is undefined (NOT zeroed), we can not rely on
+* memcmp, but directly mark it changed
+*/
+ if (!has_bit(idx, state->affected_inputs) ||
+ memcmp(>inputs[idx], input, sizeof(*input))) {
+ memcpy(>inputs[idx], input, sizeof(*input));
+ state->changed_active_inputs |= BIT(idx);
+ }
+ state->active_inputs |= BIT(idx);
+ state->affected_inputs |= BIT(idx);
+}
+
+static int
+komeda_component_check_input(struct komeda_component_state *state,
+struct komeda_component_output *input,
+int idx)
+{
+ struct komeda_component *c = state->component;
+
+ if ((idx < 0) || (idx >= c->max_active_inputs)) {
+ DRM_DEBUG_ATOMIC("%s invalid input id: %d.\n", c->name, idx);
+ return -EINVAL;
+ }
+
+ if (has_bit(idx, state->active_inputs)) {
+ DRM_DEBUG_ATOMIC("%s required input_id: %d has been occupied
already.\n",
+c->name, idx);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
[PATCH 3/5] drm/arm/komeda: Initialize komeda component as drm private object
Initialize koemda_layer, komeda_compiz, komeda_improc and
komeda_timing_ctrlr as drm private object, then track komeda private
component state by drm_atomic_state.
Signed-off-by: James (Qian) Wang
---
.../arm/display/komeda/komeda_private_obj.c | 200 +-
1 file changed, 198 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
b/drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
index 9edfd6ab0c12..c5b42fc4f904 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
@@ -7,6 +7,184 @@
#include "komeda_dev.h"
#include "komeda_kms.h"
+static void
+komeda_component_state_reset(struct komeda_component_state *st)
+{
+ st->binding_user = NULL;
+ st->affected_inputs = st->active_inputs;
+ st->active_inputs = 0;
+ st->changed_active_inputs = 0;
+}
+
+static struct drm_private_state *
+komeda_layer_atomic_duplicate_state(struct drm_private_obj *obj)
+{
+ struct komeda_layer_state *st;
+
+ st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return NULL;
+
+ komeda_component_state_reset(>base);
+ __drm_atomic_helper_private_obj_duplicate_state(obj, >base.obj);
+
+ return >base.obj;
+}
+
+static void
+komeda_layer_atomic_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+ struct komeda_layer_state *st = to_layer_st(priv_to_comp_st(state));
+
+ kfree(st);
+}
+
+static const struct drm_private_state_funcs komeda_layer_obj_funcs = {
+ .atomic_duplicate_state = komeda_layer_atomic_duplicate_state,
+ .atomic_destroy_state = komeda_layer_atomic_destroy_state,
+};
+
+static int komeda_layer_obj_add(struct komeda_layer *layer)
+{
+ struct komeda_layer_state *st;
+
+ st = kzalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ st->base.component = >base;
+ drm_atomic_private_obj_init(>base.obj, >base.obj,
+ _layer_obj_funcs);
+ return 0;
+}
+
+static struct drm_private_state *
+komeda_compiz_atomic_duplicate_state(struct drm_private_obj *obj)
+{
+ struct komeda_compiz_state *st;
+
+ st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return NULL;
+
+ komeda_component_state_reset(>base);
+ __drm_atomic_helper_private_obj_duplicate_state(obj, >base.obj);
+
+ return >base.obj;
+}
+
+static void
+komeda_compiz_atomic_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+ kfree(to_compiz_st(priv_to_comp_st(state)));
+}
+
+static const struct drm_private_state_funcs komeda_compiz_obj_funcs = {
+ .atomic_duplicate_state = komeda_compiz_atomic_duplicate_state,
+ .atomic_destroy_state = komeda_compiz_atomic_destroy_state,
+};
+
+static int komeda_compiz_obj_add(struct komeda_compiz *compiz)
+{
+ struct komeda_compiz_state *st;
+
+ st = kzalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ st->base.component = >base;
+ drm_atomic_private_obj_init(>base.obj, >base.obj,
+ _compiz_obj_funcs);
+
+ return 0;
+}
+
+static struct drm_private_state *
+komeda_improc_atomic_duplicate_state(struct drm_private_obj *obj)
+{
+ struct komeda_improc_state *st;
+
+ st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return NULL;
+
+ komeda_component_state_reset(>base);
+ __drm_atomic_helper_private_obj_duplicate_state(obj, >base.obj);
+
+ return >base.obj;
+}
+
+static void
+komeda_improc_atomic_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+ kfree(to_improc_st(priv_to_comp_st(state)));
+}
+
+static const struct drm_private_state_funcs komeda_improc_obj_funcs = {
+ .atomic_duplicate_state = komeda_improc_atomic_duplicate_state,
+ .atomic_destroy_state = komeda_improc_atomic_destroy_state,
+};
+
+static int komeda_improc_obj_add(struct komeda_improc *improc)
+{
+ struct komeda_improc_state *st;
+
+ st = kzalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ st->base.component = >base;
+ drm_atomic_private_obj_init(>base.obj, >base.obj,
+ _improc_obj_funcs);
+
+ return 0;
+}
+
+static struct drm_private_state *
+komeda_timing_ctrlr_atomic_duplicate_state(struct drm_private_obj *obj)
+{
+ struct komeda_timing_ctrlr_state *st;
+
+ st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return NULL;
+
+ komeda_component_state_reset(>base);
+ __drm_atomic_helper_private_obj_duplicate_state(obj, >base.obj);
+
+
[PATCH 1/5] drm: Add drm_atomic_get_old/new_private_obj_state
This pair of functions return the old/new private object state for the
given private_obj, or NULL if the private_obj is not part of the global
atomic state.
Reviewed-by: Alexandru Gheorghe
Signed-off-by: James (Qian) Wang
---
drivers/gpu/drm/drm_atomic.c | 45 +++-
include/drm/drm_atomic.h | 6 +
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 9ac26437051b..6ff29f3862fc 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -764,6 +764,50 @@ drm_atomic_get_private_obj_state(struct drm_atomic_state
*state,
}
EXPORT_SYMBOL(drm_atomic_get_private_obj_state);
+/**
+ * drm_atomic_get_old_private_obj_state
+ * @state: global atomic state object
+ * @obj: private_obj to grab
+ *
+ * This function returns the old private object state for the given
private_obj,
+ * or NULL if the private_obj is not part of the global atomic state.
+ */
+struct drm_private_state *
+drm_atomic_get_old_private_obj_state(struct drm_atomic_state *state,
+struct drm_private_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_private_objs; i++)
+ if (obj == state->private_objs[i].ptr)
+ return state->private_objs[i].old_state;
+
+ return NULL;
+}
+EXPORT_SYMBOL(drm_atomic_get_old_private_obj_state);
+
+/**
+ * drm_atomic_get_new_private_obj_state
+ * @state: global atomic state object
+ * @obj: private_obj to grab
+ *
+ * This function returns the new private object state for the given
private_obj,
+ * or NULL if the private_obj is not part of the global atomic state.
+ */
+struct drm_private_state *
+drm_atomic_get_new_private_obj_state(struct drm_atomic_state *state,
+struct drm_private_obj *obj)
+{
+ int i;
+
+ for (i = 0; i < state->num_private_objs; i++)
+ if (obj == state->private_objs[i].ptr)
+ return state->private_objs[i].new_state;
+
+ return NULL;
+}
+EXPORT_SYMBOL(drm_atomic_get_new_private_obj_state);
+
/**
* drm_atomic_get_connector_state - get connector state
* @state: global atomic state object
@@ -1203,4 +1247,3 @@ int drm_atomic_debugfs_init(struct drm_minor *minor)
minor->debugfs_root, minor);
}
#endif
-
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index f9b35834c45d..beb7b7fb6067 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -408,6 +408,12 @@ void drm_atomic_private_obj_fini(struct drm_private_obj
*obj);
struct drm_private_state * __must_check
drm_atomic_get_private_obj_state(struct drm_atomic_state *state,
struct drm_private_obj *obj);
+struct drm_private_state *
+drm_atomic_get_old_private_obj_state(struct drm_atomic_state *state,
+struct drm_private_obj *obj);
+struct drm_private_state *
+drm_atomic_get_new_private_obj_state(struct drm_atomic_state *state,
+struct drm_private_obj *obj);
/**
* drm_atomic_get_existing_crtc_state - get crtc state, if it exists
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 0/5] Implement komeda DRM-Plane
This is the 3rd patchset for the komeda driver. This patchset implemented plane/plane_helper functions for DRM-Plane. per the komeda driver design, A DRM-plane maps to komeda layer input pipeline, so the plane->atomic_check will build a layer input pipeline according to the plane_state. and with this build function the plane_state will be covert to komeda private component states to represent the real HW configuration. Beside that also added some basic functions for operating the komeda private object. James (Qian) Wang (5): drm: Add drm_atomic_get_old/new_private_obj_state drm/komeda: Add komeda_pipeline/component_get_state_and_set_user drm/arm/komeda: Initialize komeda component as drm private object drm/komeda: Add komeda_build_layer_data_flow drm/komeda: Add komeda_plane/plane_helper_funcs drivers/gpu/drm/arm/display/komeda/Makefile | 1 + .../drm/arm/display/komeda/komeda_pipeline.c | 2 + .../drm/arm/display/komeda/komeda_pipeline.h | 31 ++ .../display/komeda/komeda_pipeline_state.c| 408 ++ .../gpu/drm/arm/display/komeda/komeda_plane.c | 129 ++ .../arm/display/komeda/komeda_private_obj.c | 200 - drivers/gpu/drm/drm_atomic.c | 45 +- include/drm/drm_atomic.h | 6 + 8 files changed, 819 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 7/7] drm/komeda: Add debugfs node "register" for register dump
Add a debugfs node "register" and entry function dump_register to
dev/pipeline/component to register dump, then user can read
"/sys/kernel/debug/komeda/register" to get the register values via these
chip function.
Signed-off-by: James (Qian) Wang
---
.../arm/display/komeda/d71/d71_component.c| 205 ++
.../gpu/drm/arm/display/komeda/komeda_dev.c | 52 +
.../gpu/drm/arm/display/komeda/komeda_dev.h | 5 +
.../drm/arm/display/komeda/komeda_pipeline.c | 20 ++
.../drm/arm/display/komeda/komeda_pipeline.h | 3 +
5 files changed, 285 insertions(+)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
index 811634ec1193..5b2265bd3a40 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -69,6 +69,42 @@ static u32 get_valid_inputs(struct block_header *blk)
return valid_inputs;
}
+static void get_values_from_reg(void __iomem *reg, u32 offset,
+ u32 count, u32 *val)
+{
+ u32 i, addr;
+
+ for (i = 0; i < count; i++) {
+ addr = offset + (i << 2);
+ /* 0xA4 is WO register */
+ if (addr != 0xA4)
+ val[i] = malidp_read32(reg, addr);
+ else
+ val[i] = 0xDEADDEAD;
+ }
+}
+
+static void dump_block_header(struct seq_file *sf, void __iomem *reg)
+{
+ struct block_header hdr;
+ u32 i, n_input, n_output;
+
+ d71_read_block_header(reg, );
+ seq_printf(sf, "BLOCK_INFO:\t\t0x%X\n", hdr.block_info);
+ seq_printf(sf, "PIPELINE_INFO:\t\t0x%X\n", hdr.pipeline_info);
+
+ n_output = PIPELINE_INFO_N_OUTPUTS(hdr.pipeline_info);
+ n_input = PIPELINE_INFO_N_VALID_INPUTS(hdr.pipeline_info);
+
+ for (i = 0; i < n_input; i++)
+ seq_printf(sf, "VALID_INPUT_ID%u:\t0x%X\n",
+ i, hdr.input_ids[i]);
+
+ for (i = 0; i < n_output; i++)
+ seq_printf(sf, "OUTPUT_ID%u:\t\t0x%X\n",
+ i, hdr.output_ids[i]);
+}
+
static u32 to_rot_ctrl(u32 rot)
{
u32 lr_ctrl = 0;
@@ -142,9 +178,76 @@ static void d71_layer_update(struct komeda_component *c,
malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl);
}
+static void d71_layer_dump(struct komeda_component *c, struct seq_file *sf)
+{
+ u32 v[15], i;
+ bool rich, rgb2rgb;
+ char *prefix;
+
+ get_values_from_reg(c->reg, LAYER_INFO, 1, [14]);
+ if (v[14] & 0x1) {
+ rich = true;
+ prefix = "LR_";
+ } else {
+ rich = false;
+ prefix = "LS_";
+ }
+
+ rgb2rgb = !!(v[14] & L_INFO_CM);
+
+ dump_block_header(sf, c->reg);
+
+ seq_printf(sf, "%sLAYER_INFO:\t\t0x%X\n", prefix, v[14]);
+
+ get_values_from_reg(c->reg, 0xD0, 1, v);
+ seq_printf(sf, "%sCONTROL:\t\t0x%X\n", prefix, v[0]);
+ if (rich) {
+ get_values_from_reg(c->reg, 0xD4, 1, v);
+ seq_printf(sf, "LR_RICH_CONTROL:\t0x%X\n", v[0]);
+ }
+ get_values_from_reg(c->reg, 0xD8, 4, v);
+ seq_printf(sf, "%sFORMAT:\t\t0x%X\n", prefix, v[0]);
+ seq_printf(sf, "%sIT_COEFFTAB:\t\t0x%X\n", prefix, v[1]);
+ seq_printf(sf, "%sIN_SIZE:\t\t0x%X\n", prefix, v[2]);
+ seq_printf(sf, "%sPALPHA:\t\t0x%X\n", prefix, v[3]);
+
+ get_values_from_reg(c->reg, 0x100, 3, v);
+ seq_printf(sf, "%sP0_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
+ seq_printf(sf, "%sP0_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
+ seq_printf(sf, "%sP0_STRIDE:\t\t0x%X\n", prefix, v[2]);
+
+ get_values_from_reg(c->reg, 0x110, 2, v);
+ seq_printf(sf, "%sP1_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
+ seq_printf(sf, "%sP1_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
+ if (rich) {
+ get_values_from_reg(c->reg, 0x118, 1, v);
+ seq_printf(sf, "LR_P1_STRIDE:\t\t0x%X\n", v[0]);
+
+ get_values_from_reg(c->reg, 0x120, 2, v);
+ seq_printf(sf, "LR_P2_PTR_LOW:\t\t0x%X\n", v[0]);
+ seq_printf(sf, "LR_P2_PTR_HIGH:\t\t0x%X\n", v[1]);
+
+ get_values_from_reg(c->reg, 0x130, 12, v);
+ for (i = 0; i < 12; i++)
+ seq_printf(sf, "LR_YUV_RGB_COEFF%u:\t0x%X\n", i, v[i]);
+ }
+
+ if (rgb2rgb) {
+ get_values_from_reg(c->reg, LAYER_RGB_RGB_COEFF0, 12, v);
+ for (i = 0; i < 12; i++)
+ seq_printf(sf, "LS_RGB_RGB_COEFF%u:\t0x%X\n", i, v[i]);
+ }
+
+ get_values_from_reg(c->reg, 0x160, 3, v);
+ seq_printf(sf, "%sAD_CONTROL:\t\t0x%X\n", prefix, v[0]);
+ seq_printf(sf, "%sAD_H_CROP:\t\t0x%X\n", prefix, v[1]);
+ seq_printf(sf, "%sAD_V_CROP:\t\t0x%X\n", prefix, v[2]);
+}
+
struct komeda_component_funcs d71_layer_funcs = {
.update
[PATCH 6/7] drm/komeda: Add irq handling
1. Added irq_handler/irq_enable/irq_disable to komeda_dev_func, then the
Komeda-CORE can control the HW irq via these chip function.
2. Install irq and register irq_handler to system by DRM, so once the IRQ
coming, the handling sequence is:
komeda_kms_irq_handler(int irq, void *data)
/* step 1. call into the CHIP to recognize event */
mdev->funcs->irq_handler(mdev, );
/* step 2. notify the crtc to handle the events */
for (i = 0; i < kms->n_crtcs; i++)
komeda_crtc_handle_event(>crtcs[i], );
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/d71/d71_dev.c | 237 ++
.../gpu/drm/arm/display/komeda/komeda_crtc.c | 18 ++
.../gpu/drm/arm/display/komeda/komeda_dev.h | 43
.../gpu/drm/arm/display/komeda/komeda_kms.c | 35 ++-
.../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
5 files changed, 335 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
index 3c10e1fe5bd0..895603695d79 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
@@ -7,6 +7,240 @@
#include "d71_dev.h"
#include "malidp_io.h"
+static u64 get_lpu_event(struct d71_pipeline *d71_pipeline)
+{
+ u32 __iomem *reg = d71_pipeline->lpu_addr;
+ u32 status, raw_status;
+ u64 evts = 0ULL;
+
+ raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
+ if (raw_status & LPU_IRQ_IBSY)
+ evts |= KOMEDA_EVENT_IBSY;
+ if (raw_status & LPU_IRQ_EOW)
+ evts |= KOMEDA_EVENT_EOW;
+
+ if (raw_status & (LPU_IRQ_ERR | LPU_IRQ_IBSY)) {
+ u32 restore = 0, tbu_status;
+ /* Check error of LPU status */
+ status = malidp_read32(reg, BLK_STATUS);
+ if (status & LPU_STATUS_AXIE) {
+ restore |= LPU_STATUS_AXIE;
+ evts |= KOMEDA_ERR_AXIE;
+ }
+ if (status & LPU_STATUS_ACE0) {
+ restore |= LPU_STATUS_ACE0;
+ evts |= KOMEDA_ERR_ACE0;
+ }
+ if (status & LPU_STATUS_ACE1) {
+ restore |= LPU_STATUS_ACE1;
+ evts |= KOMEDA_ERR_ACE1;
+ }
+ if (status & LPU_STATUS_ACE2) {
+ restore |= LPU_STATUS_ACE2;
+ evts |= KOMEDA_ERR_ACE2;
+ }
+ if (status & LPU_STATUS_ACE3) {
+ restore |= LPU_STATUS_ACE3;
+ evts |= KOMEDA_ERR_ACE3;
+ }
+ if (restore != 0)
+ malidp_write32_mask(reg, BLK_STATUS, restore, 0);
+
+ restore = 0;
+ /* Check errors of TBU status */
+ tbu_status = malidp_read32(reg, LPU_TBU_STATUS);
+ if (tbu_status & LPU_TBU_STATUS_TCF) {
+ restore |= LPU_TBU_STATUS_TCF;
+ evts |= KOMEDA_ERR_TCF;
+ }
+ if (tbu_status & LPU_TBU_STATUS_TTNG) {
+ restore |= LPU_TBU_STATUS_TTNG;
+ evts |= KOMEDA_ERR_TTNG;
+ }
+ if (tbu_status & LPU_TBU_STATUS_TITR) {
+ restore |= LPU_TBU_STATUS_TITR;
+ evts |= KOMEDA_ERR_TITR;
+ }
+ if (tbu_status & LPU_TBU_STATUS_TEMR) {
+ restore |= LPU_TBU_STATUS_TEMR;
+ evts |= KOMEDA_ERR_TEMR;
+ }
+ if (tbu_status & LPU_TBU_STATUS_TTF) {
+ restore |= LPU_TBU_STATUS_TTF;
+ evts |= KOMEDA_ERR_TTF;
+ }
+ if (restore != 0)
+ malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0);
+ }
+
+ malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
+ return evts;
+}
+
+static u64 get_cu_event(struct d71_pipeline *d71_pipeline)
+{
+ u32 __iomem *reg = d71_pipeline->cu_addr;
+ u32 status, raw_status;
+ u64 evts = 0ULL;
+
+ raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
+ if (raw_status & CU_IRQ_OVR)
+ evts |= KOMEDA_EVENT_OVR;
+
+ if (raw_status & (CU_IRQ_ERR | CU_IRQ_OVR)) {
+ status = malidp_read32(reg, BLK_STATUS) & 0x7FFF;
+ if (status & CU_STATUS_CPE)
+ evts |= KOMEDA_ERR_CPE;
+ if (status & CU_STATUS_ZME)
+ evts |= KOMEDA_ERR_ZME;
+ if (status & CU_STATUS_CFGE)
+ evts |= KOMEDA_ERR_CFGE;
+ if (status)
+ malidp_write32_mask(reg, BLK_STATUS, status, 0);
+ }
+
+ malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
+
+ return evts;
+}
+
+static u64
[PATCH 5/7] drm/komeda: Add komeda_assemble_pipelines
komeda_accemble_pipelines is for:
1. Verifing the component->supported_inputs according to the
pipeline->avail_components.
2. Generating component->supported_outputs.
Signed-off-by: James (Qian) Wang
---
.../gpu/drm/arm/display/komeda/komeda_dev.c | 6 ++
.../drm/arm/display/komeda/komeda_pipeline.c | 75 +++
.../drm/arm/display/komeda/komeda_pipeline.h | 2 +-
3 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
index 2f8f4685eb62..ccadd6c23915 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
@@ -152,6 +152,12 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
goto err_cleanup;
}
+ err = komeda_assemble_pipelines(mdev);
+ if (err) {
+ DRM_ERROR("assemble display pipelines failed.\n");
+ goto err_cleanup;
+ }
+
return mdev;
err_cleanup:
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
index 65b35495d3b7..d0f2d556fc6a 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
@@ -200,3 +200,78 @@ void komeda_component_destroy(struct komeda_dev *mdev,
{
devm_kfree(mdev->dev, c);
}
+
+static void komeda_component_dump(struct komeda_component *c)
+{
+ if (!c)
+ return;
+
+ DRM_INFO(" %s: ID %d-0x%08lx.\n",
+c->name, c->id, BIT(c->id));
+ DRM_INFO(" max_active_inputs:%d, supported_inputs:
0x%08x.\n",
+c->max_active_inputs, c->supported_inputs);
+ DRM_INFO(" max_active_outputs:%d, supported_outputs:
0x%08x.\n",
+c->max_active_outputs, c->supported_outputs);
+}
+
+static void komeda_pipeline_dump(struct komeda_pipeline *pipe)
+{
+ struct komeda_component *c;
+ int id;
+
+ DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s\n",
+pipe->id, pipe->n_layers, pipe->n_scalers,
+pipe->of_output_dev ? pipe->of_output_dev->full_name : "none");
+
+ dp_for_each_set_bit(id, pipe->avail_comps) {
+ c = komeda_pipeline_get_component(pipe, id);
+
+ komeda_component_dump(c);
+ }
+}
+
+static void komeda_component_verify_inputs(struct komeda_component *c)
+{
+ struct komeda_pipeline *pipe = c->pipeline;
+ struct komeda_component *input;
+ int id;
+
+ dp_for_each_set_bit(id, c->supported_inputs) {
+ input = komeda_pipeline_get_component(pipe, id);
+ if (!input) {
+ c->supported_inputs &= ~(BIT(id));
+ DRM_WARN("Can not find input(ID-%d) for component:
%s.\n",
+id, c->name);
+ continue;
+ }
+
+ input->supported_outputs |= BIT(c->id);
+ }
+}
+
+static void komeda_pipeline_assemble(struct komeda_pipeline *pipe)
+{
+ struct komeda_component *c;
+ int id;
+
+ dp_for_each_set_bit(id, pipe->avail_comps) {
+ c = komeda_pipeline_get_component(pipe, id);
+
+ komeda_component_verify_inputs(c);
+ }
+}
+
+int komeda_assemble_pipelines(struct komeda_dev *mdev)
+{
+ struct komeda_pipeline *pipe;
+ int i;
+
+ for (i = 0; i < mdev->n_pipelines; i++) {
+ pipe = mdev->pipelines[i];
+
+ komeda_pipeline_assemble(pipe);
+ komeda_pipeline_dump(pipe);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index b2bd6ab282cb..df82f986f9c9 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -365,7 +365,7 @@ komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
struct komeda_pipeline_funcs *funcs);
void komeda_pipeline_destroy(struct komeda_dev *mdev,
struct komeda_pipeline *pipe);
-
+int komeda_assemble_pipelines(struct komeda_dev *mdev);
struct komeda_component *
komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id);
--
2.17.1
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4/7] drm/komeda: Add D71 improc and timing_ctrlr
Add and initialize improc and timing_ctrlr according to D71 capablitites
Signed-off-by: James (Qian) Wang
---
.../arm/display/komeda/d71/d71_component.c| 108 +-
.../gpu/drm/arm/display/komeda/komeda_kms.h | 2 +
.../drm/arm/display/komeda/komeda_pipeline.h | 7 ++
3 files changed, 115 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
index 5458df726b08..811634ec1193 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -285,18 +285,122 @@ static int d71_compiz_init(struct d71_dev *d71,
return 0;
}
+static void d71_improc_update(struct komeda_component *c,
+ struct komeda_component_state *state)
+{
+ struct komeda_improc_state *st = to_improc_st(state);
+ u32 __iomem *reg = c->reg;
+ u32 index, input_hw_id;
+
+ for_each_changed_input(state, index) {
+ input_hw_id = state->active_inputs & BIT(index) ?
+ to_d71_input_id(>inputs[index]) : 0;
+ malidp_write32(reg, BLK_INPUT_ID0 + index * 4, input_hw_id);
+ }
+
+ malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
+}
+
+struct komeda_component_funcs d71_improc_funcs = {
+ .update = d71_improc_update,
+ .disable= d71_component_disable,
+};
+
static int d71_improc_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
- DRM_INFO("Detect D71_improc.\n");
+ struct komeda_component *c;
+ struct komeda_improc *improc;
+ u32 blk_id = BLOCK_INFO_BLK_ID(blk->block_info);
+ u32 value;
+
+ c = komeda_component_add(>pipes[blk_id]->base, sizeof(*improc),
+KOMEDA_COMPONENT_IPS0 + blk_id,
+BLOCK_INFO_INPUT_ID(blk->block_info),
+_improc_funcs, IPS_NUM_INPUT_IDS,
+get_valid_inputs(blk),
+IPS_NUM_OUTPUT_IDS, reg, "DOU%d_IPS", blk_id);
+ if (!c) {
+ DRM_ERROR("Failed to add improc component\n");
+ return -EINVAL;
+ }
+
+ improc = to_improc(c);
+ improc->supported_color_depths = BIT(8) | BIT(10);
+ improc->supported_color_formats = DRM_COLOR_FORMAT_RGB444 |
+ DRM_COLOR_FORMAT_YCRCB444 |
+ DRM_COLOR_FORMAT_YCRCB422;
+ value = malidp_read32(reg, BLK_INFO);
+ if (value & IPS_INFO_CHD420)
+ improc->supported_color_formats |= DRM_COLOR_FORMAT_YCRCB420;
+
+ improc->supports_csc = true;
+ improc->supports_gamma = true;
return 0;
}
+static void d71_timing_ctrlr_disable(struct komeda_component *c)
+{
+ malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0);
+}
+
+static void d71_timing_ctrlr_update(struct komeda_component *c,
+ struct komeda_component_state *state)
+{
+ struct drm_crtc_state *crtc_st = state->crtc->state;
+ u32 __iomem *reg = c->reg;
+ struct videomode vm;
+ u32 value;
+
+ drm_display_mode_to_videomode(_st->adjusted_mode, );
+
+ malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(vm.hactive, vm.vactive));
+ malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(vm.hfront_porch,
+ vm.hback_porch));
+ malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vm.vfront_porch,
+ vm.vback_porch));
+
+ value = BS_SYNC_VSW(vm.vsync_len) | BS_SYNC_HSW(vm.hsync_len);
+ value |= vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? BS_SYNC_VSP : 0;
+ value |= vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? BS_SYNC_HSP : 0;
+ malidp_write32(reg, BS_SYNC, value);
+
+ malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1);
+ malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
+
+ /* configure bs control register */
+ value = BS_CTRL_EN | BS_CTRL_VM;
+
+ malidp_write32(reg, BLK_CONTROL, value);
+}
+
+struct komeda_component_funcs d71_timing_ctrlr_funcs = {
+ .update = d71_timing_ctrlr_update,
+ .disable= d71_timing_ctrlr_disable,
+};
+
static int d71_timing_ctrlr_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
- DRM_INFO("Detect D71_timing_ctrlr.\n");
+ struct komeda_component *c;
+ struct komeda_timing_ctrlr *ctrlr;
+ u32 blk_id = BLOCK_INFO_BLK_ID(blk->block_info);
+
+ c = komeda_component_add(>pipes[blk_id]->base, sizeof(*ctrlr),
+KOMEDA_COMPONENT_TIMING_CTRLR,
+
[PATCH 3/7] arm/komeda: Add d71 compiz component
Implement d71_compiz_init and add compiz component to komeda-CORE
Signed-off-by: James (Qian) Wang
---
.../arm/display/komeda/d71/d71_component.c| 95 ++-
.../drm/arm/display/komeda/komeda_pipeline.h | 26 +++--
2 files changed, 113 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
index 0e8ae7b00d14..5458df726b08 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -96,6 +96,14 @@ static u32 to_rot_ctrl(u32 rot)
return lr_ctrl;
}
+static inline u32
+to_d71_input_id(struct komeda_component_output *output)
+{
+ struct komeda_component *comp = output->component;
+
+ return comp ? (comp->hw_id + output->output_port) : 0;
+}
+
static void d71_layer_disable(struct komeda_component *c)
{
malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0);
@@ -184,10 +192,95 @@ static int d71_wb_layer_init(struct d71_dev *d71,
return 0;
}
+static void d71_component_disable(struct komeda_component *c)
+{
+ u32 __iomem *reg = c->reg;
+ u32 i;
+
+ malidp_write32(reg, BLK_CONTROL, 0);
+
+ for (i = 0; i < c->max_active_inputs; i++)
+ malidp_write32(reg, BLK_INPUT_ID0 + (i << 2), 0);
+}
+
+static void compiz_enable_input(u32 __iomem *id_reg,
+ u32 __iomem *cfg_reg,
+ u32 input_hw_id,
+ struct komeda_compiz_input_cfg *cin)
+{
+ u32 ctrl = CU_INPUT_CTRL_EN;
+ u8 blend = cin->pixel_blend_mode;
+
+ if (blend == DRM_MODE_BLEND_PIXEL_NONE)
+ ctrl |= CU_INPUT_CTRL_PAD;
+ else if (blend == DRM_MODE_BLEND_PREMULTI)
+ ctrl |= CU_INPUT_CTRL_PMUL;
+
+ ctrl |= CU_INPUT_CTRL_ALPHA(cin->layer_alpha);
+
+ malidp_write32(id_reg, BLK_INPUT_ID0, input_hw_id);
+
+ malidp_write32(cfg_reg, CU_INPUT0_SIZE,
+ HV_SIZE(cin->hsize, cin->vsize));
+ malidp_write32(cfg_reg, CU_INPUT0_OFFSET,
+ HV_OFFSET(cin->hoffset, cin->voffset));
+ malidp_write32(cfg_reg, CU_INPUT0_CONTROL, ctrl);
+}
+
+static void d71_compiz_update(struct komeda_component *c,
+ struct komeda_component_state *state)
+{
+ struct komeda_compiz_state *st = to_compiz_st(state);
+ u32 __iomem *reg = c->reg;
+ u32 __iomem *id_reg, *cfg_reg;
+ u32 index, input_hw_id;
+
+ for_each_changed_input(state, index) {
+ id_reg = reg + index;
+ cfg_reg = reg + index * CU_PER_INPUT_REGS;
+ input_hw_id = to_d71_input_id(>inputs[index]);
+ if (state->active_inputs & BIT(index)) {
+ compiz_enable_input(id_reg, cfg_reg,
+ input_hw_id, >cins[index]);
+ } else {
+ malidp_write32(id_reg, BLK_INPUT_ID0, 0);
+ malidp_write32(cfg_reg, CU_INPUT0_CONTROL, 0);
+ }
+ }
+
+ malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
+}
+
+struct komeda_component_funcs d71_compiz_funcs = {
+ .update = d71_compiz_update,
+ .disable= d71_component_disable,
+};
+
static int d71_compiz_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
- DRM_INFO("Detect D71_compiz.\n");
+ struct komeda_component *c;
+ struct komeda_compiz *compiz;
+ u32 blk_id = BLOCK_INFO_BLK_ID(blk->block_info);
+ u32 pipe_id, comp_id;
+
+ get_resources_id(blk->block_info, _id, _id);
+
+ c = komeda_component_add(>pipes[pipe_id]->base, sizeof(*compiz),
+comp_id,
+BLOCK_INFO_INPUT_ID(blk->block_info),
+_compiz_funcs,
+CU_NUM_INPUT_IDS, get_valid_inputs(blk),
+CU_NUM_OUTPUT_IDS, reg,
+"CU%d", blk_id);
+
+ if (!c)
+ return -1;
+
+ compiz = to_compiz(c);
+
+ set_range(>hsize, D71_MIN_LINE_SIZE, d71->max_line_size);
+ set_range(>vsize, D71_MIN_VERTICAL_SIZE, d71->max_vsize);
return 0;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index b8cf502982fb..22baeb5e1b61 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -206,6 +206,10 @@ static inline u16 component_changed_inputs(struct
komeda_component_state *st)
return component_disabling_inputs(st) | st->changed_active_inputs;
}
+#define for_each_changed_input(st, i) \
+ for ((i) = 0; (i) < (st)->component->max_active_inputs; (i)++) \
+
[PATCH 1/7] drm/komeda: Add d71_enum_resources and d71_cleanup
D71 consists of a number of Register Blocks, every Block controls a
specific HW function, every block has a common block_header to represent
its type and pipeline information.
GCU (Global Control Unit) is the first Block which describe the global
information of D71 HW, Like number of block contained and the number of
pipeline supported.
So the d71_enum_resources parsed GCU and create pipeline according
the GCU configuration, and then iterate and detect the blocks that
indicated by the GCU and block_header.
And this change also added two struct d71_dev/d71_pipeline to extend
komeda_dev/komeda_pipeline to add some d71 only members.
Signed-off-by: James (Qian) Wang
---
.../drm/arm/display/include/malidp_utils.h| 12 +
drivers/gpu/drm/arm/display/komeda/Makefile | 3 +-
.../arm/display/komeda/d71/d71_component.c| 120
.../gpu/drm/arm/display/komeda/d71/d71_dev.c | 130 -
.../gpu/drm/arm/display/komeda/d71/d71_dev.h | 50 ++
.../gpu/drm/arm/display/komeda/d71/d71_regs.h | 530 ++
6 files changed, 837 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h
create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
diff --git a/drivers/gpu/drm/arm/display/include/malidp_utils.h
b/drivers/gpu/drm/arm/display/include/malidp_utils.h
index 63cc47cefcf8..b7bf8db39a64 100644
--- a/drivers/gpu/drm/arm/display/include/malidp_utils.h
+++ b/drivers/gpu/drm/arm/display/include/malidp_utils.h
@@ -13,4 +13,16 @@
#define dp_for_each_set_bit(bit, mask) \
for_each_set_bit((bit), ((unsigned long *)&(mask)), sizeof(mask) * 8)
+#define dp_wait_cond(__cond, __tries, __min_range, __max_range)\
+({ \
+ int num_tries = __tries;\
+ while (!__cond && (num_tries > 0)) {\
+ usleep_range(__min_range, __max_range); \
+ if (__cond) \
+ break; \
+ num_tries--;\
+ } \
+ num_tries; \
+})
+
#endif /* _MALIDP_UTILS_ */
diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
b/drivers/gpu/drm/arm/display/komeda/Makefile
index 1b875e5dc0f6..d593125236ae 100644
--- a/drivers/gpu/drm/arm/display/komeda/Makefile
+++ b/drivers/gpu/drm/arm/display/komeda/Makefile
@@ -16,6 +16,7 @@ komeda-y := \
komeda_private_obj.o
komeda-y += \
- d71/d71_dev.o
+ d71/d71_dev.o \
+ d71/d71_component.o
obj-$(CONFIG_DRM_KOMEDA) += komeda.o
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
new file mode 100644
index ..a43a2410159f
--- /dev/null
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
+ * Author: James.Qian.Wang
+ *
+ */
+#include "d71_dev.h"
+#include "komeda_kms.h"
+#include "malidp_io.h"
+
+static int d71_layer_init(struct d71_dev *d71,
+ struct block_header *blk, u32 __iomem *reg)
+{
+ DRM_INFO("Detect D71_Layer.\n");
+
+ return 0;
+}
+
+static int d71_wb_layer_init(struct d71_dev *d71,
+struct block_header *blk, u32 __iomem *reg)
+{
+ DRM_INFO("Detect D71_Wb_Layer.\n");
+
+ return 0;
+}
+
+static int d71_compiz_init(struct d71_dev *d71,
+ struct block_header *blk, u32 __iomem *reg)
+{
+ DRM_INFO("Detect D71_compiz.\n");
+
+ return 0;
+}
+
+static int d71_improc_init(struct d71_dev *d71,
+ struct block_header *blk, u32 __iomem *reg)
+{
+ DRM_INFO("Detect D71_improc.\n");
+
+ return 0;
+}
+
+static int d71_timing_ctrlr_init(struct d71_dev *d71,
+struct block_header *blk, u32 __iomem *reg)
+{
+ DRM_INFO("Detect D71_timing_ctrlr.\n");
+
+ return 0;
+}
+
+int d71_probe_block(struct d71_dev *d71,
+ struct block_header *blk, u32 __iomem *reg)
+{
+ struct d71_pipeline *pipe;
+ int blk_id = BLOCK_INFO_BLK_ID(blk->block_info);
+
+ int err = 0;
+
+ switch (BLOCK_INFO_BLK_TYPE(blk->block_info)) {
+ case D71_BLK_TYPE_GCU:
+ break;
+
+ case D71_BLK_TYPE_LPU:
+ pipe = d71->pipes[blk_id];
+ pipe->lpu_addr = reg;
+ break;
+
+ case D71_BLK_TYPE_LPU_LAYER:
+ err = d71_layer_init(d71, blk, reg);
+ break;
+
+ case D71_BLK_TYPE_LPU_WB_LAYER:
+ err = d71_wb_layer_init(d71, blk, reg);
+ break;
+
+ case D71_BLK_TYPE_CU:
+ pipe
[PATCH 2/7] drm/komeda: Add d71 layer
1. Add detailed layer/layer_state definitions
2. Add d71_layer_init to report layer features and capabilities according
to D71 layer block.
3. Add d71_layer_updat/disable
Signed-off-by: James (Qian) Wang
---
.../drm/arm/display/include/malidp_utils.h| 17 ++
.../arm/display/komeda/d71/d71_component.c| 162 +-
.../drm/arm/display/komeda/komeda_pipeline.c | 2 +-
.../drm/arm/display/komeda/komeda_pipeline.h | 10 +-
4 files changed, 186 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/include/malidp_utils.h
b/drivers/gpu/drm/arm/display/include/malidp_utils.h
index b7bf8db39a64..e97df5fbc9ea 100644
--- a/drivers/gpu/drm/arm/display/include/malidp_utils.h
+++ b/drivers/gpu/drm/arm/display/include/malidp_utils.h
@@ -25,4 +25,21 @@
num_tries; \
})
+/* the restriction of range is [start, end] */
+struct malidp_range {
+ u32 start;
+ u32 end;
+};
+
+static inline void set_range(struct malidp_range *rg, u32 start, u32 end)
+{
+ rg->start = start;
+ rg->end = end;
+}
+
+static inline bool in_range(struct malidp_range *rg, u32 v)
+{
+ return (v >= rg->start) && (v <= rg->end);
+}
+
#endif /* _MALIDP_UTILS_ */
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
index a43a2410159f..0e8ae7b00d14 100644
--- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
+++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
@@ -7,11 +7,171 @@
#include "d71_dev.h"
#include "komeda_kms.h"
#include "malidp_io.h"
+#include "komeda_framebuffer.h"
+
+static void get_resources_id(u32 hw_id, u32 *pipe_id, u32 *comp_id)
+{
+ u32 id = BLOCK_INFO_BLK_ID(hw_id);
+ u32 pipe = id;
+
+ switch (BLOCK_INFO_BLK_TYPE(hw_id)) {
+ case D71_BLK_TYPE_LPU_WB_LAYER:
+ id = KOMEDA_COMPONENT_WB_LAYER;
+ break;
+ case D71_BLK_TYPE_CU_SPLITTER:
+ id = KOMEDA_COMPONENT_SPLITTER;
+ break;
+ case D71_BLK_TYPE_CU_SCALER:
+ pipe = id / D71_PIPELINE_MAX_SCALERS;
+ id %= D71_PIPELINE_MAX_SCALERS;
+ id += KOMEDA_COMPONENT_SCALER0;
+ break;
+ case D71_BLK_TYPE_CU:
+ id += KOMEDA_COMPONENT_COMPIZ0;
+ break;
+ case D71_BLK_TYPE_LPU_LAYER:
+ pipe = id / D71_PIPELINE_MAX_LAYERS;
+ id %= D71_PIPELINE_MAX_LAYERS;
+ id += KOMEDA_COMPONENT_LAYER0;
+ break;
+ case D71_BLK_TYPE_DOU_IPS:
+ id += KOMEDA_COMPONENT_IPS0;
+ break;
+ case D71_BLK_TYPE_CU_MERGER:
+ id = KOMEDA_COMPONENT_MERGER;
+ break;
+ case D71_BLK_TYPE_DOU:
+ id = KOMEDA_COMPONENT_TIMING_CTRLR;
+ break;
+ default:
+ id = 0x;
+ }
+
+ if (comp_id)
+ *comp_id = id;
+
+ if (pipe_id)
+ *pipe_id = pipe;
+}
+
+static u32 get_valid_inputs(struct block_header *blk)
+{
+ u32 valid_inputs = 0, comp_id;
+ int i;
+
+ for (i = 0; i < PIPELINE_INFO_N_VALID_INPUTS(blk->pipeline_info); i++) {
+ get_resources_id(blk->input_ids[i], NULL, _id);
+ if (comp_id == 0x)
+ continue;
+ valid_inputs |= BIT(comp_id);
+ }
+
+ return valid_inputs;
+}
+
+static u32 to_rot_ctrl(u32 rot)
+{
+ u32 lr_ctrl = 0;
+
+ switch (rot & DRM_MODE_ROTATE_MASK) {
+ case DRM_MODE_ROTATE_0:
+ lr_ctrl |= L_ROT(L_ROT_R0);
+ break;
+ case DRM_MODE_ROTATE_90:
+ lr_ctrl |= L_ROT(L_ROT_R90);
+ break;
+ case DRM_MODE_ROTATE_180:
+ lr_ctrl |= L_ROT(L_ROT_R180);
+ break;
+ case DRM_MODE_ROTATE_270:
+ lr_ctrl |= L_ROT(L_ROT_R270);
+ break;
+ }
+
+ if (rot & DRM_MODE_REFLECT_X)
+ lr_ctrl |= L_HFLIP;
+ if (rot & DRM_MODE_REFLECT_Y)
+ lr_ctrl |= L_VFLIP;
+
+ return lr_ctrl;
+}
+
+static void d71_layer_disable(struct komeda_component *c)
+{
+ malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0);
+}
+
+static void d71_layer_update(struct komeda_component *c,
+struct komeda_component_state *state)
+{
+ struct komeda_layer_state *st = to_layer_st(state);
+ struct drm_plane_state *plane_st = state->plane->state;
+ struct drm_framebuffer *fb = plane_st->fb;
+ struct komeda_fb *kfb = to_kfb(fb);
+ u32 __iomem *reg = c->reg;
+ u32 ctrl_mask = L_EN | L_ROT(L_ROT_R270) | L_HFLIP | L_VFLIP | L_TBU_EN;
+ u32 ctrl = L_EN | to_rot_ctrl(st->rot);
+ int i;
+
+ for (i = 0; i < fb->format->num_planes; i++) {
+ malidp_write32(reg,
+
[PATCH 0/7] D71 pipeline/component descovery and initialization
This is the 2nd patchset for komeda-driver. These patches focus on CHIP(D71) Layer for pipeline/component descovery and initialization. All basic and essential display component: layer, compiz, improc, timing-ctrlr and irq handling have been added, other component support: scaler, wb_layer, merger, splitter will be added in the future. James (Qian) Wang (7): drm/komeda: Add d71_enum_resources and d71_cleanup drm/komeda: Add d71 layer arm/komeda: Add d71 compiz component drm/komeda: Add D71 improc and timing_ctrlr drm/komeda: Add komeda_assemble_pipelines drm/komeda: Add irq handling drm/komeda: Add debugfs node "register" for register dump .../drm/arm/display/include/malidp_utils.h| 29 + drivers/gpu/drm/arm/display/komeda/Makefile | 3 +- .../arm/display/komeda/d71/d71_component.c| 682 ++ .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 367 +- .../gpu/drm/arm/display/komeda/d71/d71_dev.h | 50 ++ .../gpu/drm/arm/display/komeda/d71/d71_regs.h | 530 ++ .../gpu/drm/arm/display/komeda/komeda_crtc.c | 18 + .../gpu/drm/arm/display/komeda/komeda_dev.c | 58 ++ .../gpu/drm/arm/display/komeda/komeda_dev.h | 48 ++ .../gpu/drm/arm/display/komeda/komeda_kms.c | 35 +- .../gpu/drm/arm/display/komeda/komeda_kms.h | 5 + .../drm/arm/display/komeda/komeda_pipeline.c | 97 ++- .../drm/arm/display/komeda/komeda_pipeline.h | 48 +- 13 files changed, 1949 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h create mode 100644 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
