[PATCH v2] drm/ast: Disable fast reset after DRAM initial
[Bug][AST2500]
V1:
When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization
have to be achieved by VGA driver with P2A (PCI to AHB) enabling.
However, HW suggests disable Fast reset mode after DRAM initializaton,
because fast reset mode is mainly designed for ARM ICE debugger.
Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be
first enabled to avoid system deadlock before disable fast reset mode.
V2:
Use to_pci_dev() to get revision of PCI configuration.
Signed-off-by: KuoHsiang Chou
---
drivers/gpu/drm/ast/ast_drv.h | 1 +
drivers/gpu/drm/ast/ast_main.c | 5 +++
drivers/gpu/drm/ast/ast_post.c | 71 +-
3 files changed, 51 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index da6dfb677540..a2cf5fef2399 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -320,6 +320,7 @@ bool ast_is_vga_enabled(struct drm_device *dev);
void ast_post_gpu(struct drm_device *dev);
u32 ast_mindwm(struct ast_private *ast, u32 r);
void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
+void ast_patch_ahb_2500(struct ast_private *ast);
/* ast dp501 */
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 3775fe26f792..0e4dfcc25623 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -69,6 +69,7 @@ static void ast_detect_config_mode(struct drm_device *dev,
u32 *scu_rev)
{
struct device_node *np = dev->pdev->dev.of_node;
struct ast_private *ast = to_ast_private(dev);
+ struct pci_dev *pdev = to_pci_dev(dev->dev);
uint32_t data, jregd0, jregd1;
/* Defaults */
@@ -96,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev,
u32 *scu_rev)
jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
+ /* Patch AST2500 */
+ if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0))
+ ast_patch_ahb_2500(ast);
+
/* Double check it's actually working */
data = ast_read32(ast, 0xf004);
if (data != 0x) {
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 8902c2f84bf9..1f0007daa005 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -2026,6 +2026,33 @@ static bool ast_dram_init_2500(struct ast_private *ast)
return true;
}
+void ast_patch_ahb_2500(struct ast_private *ast)
+{
+ u32 data;
+
+patch_ahb_lock:
+ /* Clear bus lock condition */
+ ast_moutdwm(ast, 0x1e60, 0xAEED1A03);
+ ast_moutdwm(ast, 0x1e600084, 0x0001);
+ ast_moutdwm(ast, 0x1e600088, 0x);
+ ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
+ data = ast_mindwm(ast, 0x1e6e2070);
+ if (data & 0x0800) {/*
check fast reset */
+
+ ast_moutdwm(ast, 0x1E785004, 0x0010);
+ ast_moutdwm(ast, 0x1E785008, 0x4755);
+ ast_moutdwm(ast, 0x1E78500c, 0x0033);
+ udelay(1000);
+ }
+ ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
+ do {
+ data = ast_mindwm(ast, 0x1e6e2000);
+ if (data == 0x)
+ goto patch_ahb_lock;
+ } while (data != 1);
+ ast_moutdwm(ast, 0x1e6e207c, 0x0800); /* clear fast reset */
+}
+
void ast_post_chip_2500(struct drm_device *dev)
{
struct ast_private *ast = to_ast_private(dev);
@@ -2033,39 +2060,31 @@ void ast_post_chip_2500(struct drm_device *dev)
u8 reg;
reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
- if ((reg & 0x80) == 0) {/* vga only */
+ if ((reg & 0xC0) == 0) {/* vga only */
/* Clear bus lock condition */
- ast_moutdwm(ast, 0x1e60, 0xAEED1A03);
- ast_moutdwm(ast, 0x1e600084, 0x0001);
- ast_moutdwm(ast, 0x1e600088, 0x);
- ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
- ast_write32(ast, 0xf004, 0x1e6e);
- ast_write32(ast, 0xf000, 0x1);
- ast_write32(ast, 0x12000, 0x1688a8a8);
- while (ast_read32(ast, 0x12000) != 0x1)
- ;
-
- ast_write32(ast, 0x1, 0xfc600309);
- while (ast_read32(ast, 0x1) != 0x1)
- ;
+ ast_patch_ahb_2500(ast);
+
+ /* Disable watchdog */
+ ast_moutdwm(ast, 0x1E78502C, 0x);
+ ast_moutdwm(ast, 0x1E78504C, 0x);
+
[PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..ecf249a58435
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+ opp-microvolt = <668750>,
+ <75>;
+ };
+
+ opp-60500 {
+ opp-hz = /bits/ 64 <60500>;
+ opp-hz-real = /bits/ 64 <60500>,
+/bits/ 64 <60500>;
+ opp-microvolt = <681250>,
+
[PATCH v3] drm/sun4i: tcon: fix inverted DCLK polarity
From: Giulio Benetti
During commit 88bc4178568b ("drm: Use new
DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
macros have been changed to avoid ambiguity but just because of this
ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning
_SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but
instead of swapping phase values, let's adopt an easier approach Maxime
suggested:
It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to
invert DCLK polarity and this makes things really easier than before. So
let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as
bit 26 and activating according to bus_flags the same way it is done for
all the other signals polarity.
Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE
flags")
Suggested-by: Maxime Ripard
Signed-off-by: Giulio Benetti
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +---
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index eaaf5d70e352..30171ccd87e5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon
*tcon,
if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
- /*
-* On A20 and similar SoCs, the only way to achieve Positive Edge
-* (Rising Edge), is setting dclk clock phase to 2/3(240°).
-* By default TCON works in Negative Edge(Falling Edge),
-* this is why phase is set to 0 in that case.
-* Unfortunately there's no way to logically invert dclk through
-* IO_POL register.
-* The only acceptable way to work, triple checked with scope,
-* is using clock phase set to 0° for Negative Edge and set to 240°
-* for Positive Edge.
-* On A33 and similar SoCs there would be a 90° phase option,
-* but it divides also dclk by 2.
-* Following code is a way to avoid quirks all around TCON
-* and DOTCLOCK drivers.
-*/
if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
- clk_set_phase(tcon->dclk, 240);
-
- if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
- clk_set_phase(tcon->dclk, 0);
+ val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE;
regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index cfbf4e6c1679..0ce71d10a31b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -113,6 +113,7 @@
#define SUN4I_TCON0_IO_POL_REG 0x88
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
+#define SUN4I_TCON0_IO_POL_DCLK_POSITIVE BIT(26)
#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [patch 02/30] genirq: Move status flag checks to core
On Sun, Dec 27 2020 at 11:20, Guenter Roeck wrote: > On Thu, Dec 10, 2020 at 08:25:38PM +0100, Thomas Gleixner wrote: > Yes, but that means that irq_check_status_bit() may be called from modules, > but it is not exported, resulting in build errors such as the following. > > arm64:allmodconfig: > > ERROR: modpost: "irq_check_status_bit" [drivers/perf/arm_spe_pmu.ko] > undefined! Duh. Yes, that lacks an export obviously. Thanks, tglx ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 12/15] drm/vc4: hdmi: Don't register the CEC adapter if there's no interrupts
We introduced the BCM2711 support to the vc4 HDMI controller with 5.10,
but this was lacking any of the interrupts of the CEC controller so we
have to deal with the backward compatibility.
Do so by simply ignoring the CEC setup if the DT doesn't have the
interrupts property.
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5a606b6f2917..eee9751009c2 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1667,9 +1667,15 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
{
struct cec_connector_info conn_info;
struct platform_device *pdev = vc4_hdmi->pdev;
+ struct device *dev = >dev;
u32 value;
int ret;
+ if (!of_find_property(dev->of_node, "interrupts", NULL)) {
+ dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
+ return 0;
+ }
+
vc4_hdmi->cec_adap = cec_allocate_adapter(_hdmi_cec_adap_ops,
vc4_hdmi, "vc4",
CEC_CAP_DEFAULTS |
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling
On 1/11/21 6:20 PM, Maxime Ripard wrote: On Fri, Jan 08, 2021 at 03:34:52PM +0100, Giulio Benetti wrote: Hi, On 1/8/21 10:23 AM, Maxime Ripard wrote: Hi, Thanks for those patches On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote: From: Giulio Benetti It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes thing really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to bus_flags the same way is done for all the other signals. Cc: Maxime Ripard Suggested-by would be nice here :) Ok, didn't know about this tag Signed-off-by: Giulio Benetti --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +--- drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 52598bb0fb0b..30171ccd87e5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; - /* -* On A20 and similar SoCs, the only way to achieve Positive Edge -* (Rising Edge), is setting dclk clock phase to 2/3(240°). -* By default TCON works in Negative Edge(Falling Edge), -* this is why phase is set to 0 in that case. -* Unfortunately there's no way to logically invert dclk through -* IO_POL register. -* The only acceptable way to work, triple checked with scope, -* is using clock phase set to 0° for Negative Edge and set to 240° -* for Positive Edge. -* On A33 and similar SoCs there would be a 90° phase option, -* but it divides also dclk by 2. -* Following code is a way to avoid quirks all around TCON -* and DOTCLOCK drivers. -*/ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 0); - - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 240); + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE; I'm not really sure why we need the first patch of this series here? The idea was to have 2 for testing, 1st one is already applicable, while the other must be tested, but I can send only one with no problem. That patch only seem to undo what you did in patch 1 No, it doesn't, the 2nd one change the way it achieve the same thing, because the 1st swap DCLK phase, while the 2nd uses the IO_POL bit to set IO polarity according to bus_flags. It makes sense for testing, but I'm not sure we want to carry it into the history. Can you squash them both into the same patch? Sure, I'm going to send V3 then. Thank you Best regards -- Giulio Benetti Benetti Engineering sas ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 02/15] drm/vc4: hdmi: Move hdmi reset to bind
From: Dom Cobley
The hdmi reset got moved to a later point in the commit 9045e91a476b
("drm/vc4: hdmi: Add reset callback").
However, the reset now occurs after vc4_hdmi_cec_init and so tramples
the setup of registers like HDMI_CEC_CNTRL_1
This only affects pi0-3 as on pi4 the cec registers are in a separate
block
Fixes: 9045e91a476b ("drm/vc4: hdmi: Add reset callback")
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 2e5449b25ce4..cb4594e7df6f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -779,9 +779,6 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct
drm_encoder *encoder,
return;
}
- if (vc4_hdmi->variant->reset)
- vc4_hdmi->variant->reset(vc4_hdmi);
-
if (vc4_hdmi->variant->phy_init)
vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
@@ -1874,6 +1871,9 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
vc4_hdmi->disable_wifi_frequencies =
of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
+ if (vc4_hdmi->variant->reset)
+ vc4_hdmi->variant->reset(vc4_hdmi);
+
pm_runtime_enable(dev);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx
Hi Jordan, On 2021-01-11 21:41, Jordan Crouse wrote: On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote: Hi Rob, On 2021-01-08 22:16, Rob Clark wrote: >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan > wrote: >> >>On 2021-01-08 19:09, Konrad Dybcio wrote: Konrad, can you please test this below change without your change? >>> >>> This brings no difference, a BUG still happens. We're still calling >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 >>> into an A640.. >>> >>> Also, relying on disabling LLCC in the config is out of question as it >>> makes the arm32 kernel not compile with DRM/MSM and it just removes >>> the functionality on devices with a6xx.. (unless somebody removes the >>> dependency on it, which in my opinion is even worse and will cause >>> more problems for developers!). >>> >> >>Disabling LLCC is not the suggestion, I was under the impression that >>was the cause here for the smmu bug. Anyways, the check for llc slice >>in case llcc is disabled is not correct as well. I will send a patch for >>that as well. >> >>> The bigger question is how and why did that piece of code ever make it >>> to adreno_gpu.c and not a6xx_gpu.c? >>> >> >>My mistake, I will move it. > >Thanks, since we don't have kernel-CI coverage for gpu, and there >probably isn't one person who has all the different devices supported >(or enough hours in the day to test them all), it is probably >better/safer to keep things in the backend code that is specific to a >given generation. > Agreed, I will post this change soon and will introduce some feature check as well because we will need it for iommu prot flag as per discussion here - https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/ >>> To solve it in a cleaner way I propose to move it to an a6xx-specific >>> file, or if it's going to be used with next-gen GPUs, perhaps manage >>> calling of this code via an adreno quirk/feature in adreno_device.c. >>> Now that I think about it, A5xx GPMU en/disable could probably managed >>> like that, instead of using tons of if-statements for each GPU model >>> that has it.. >>> >>> While we're at it, do ALL (and I truly do mean ALL, including the >>> low-end ones, this will be important later on) A6xx GPUs make use of >>> that feature? >>> >> >>I do not have a list of all A6XX GPUs with me currently, but from what >>I know, A618, A630, A640, A650 has the support. >> > >From the PoV of bringing up new a6xx, we should probably consider that >some of them may not *yet* have LLCC enabled. I have an 8cx laptop >and once I find time to get the display working, the next step would >be bringing up a680.. and I'd probably like to start without LLCC.. > Right, once I move the LLCC code to a6xx specific address space creation, without LLCC slices for GPU specified in qcom llcc driver, we will not be using it. Right. The problem here was that we were assuming an a6xx container in generic code. Testing the existence of LLCC or not is a different problem but it is my understanding that if we set the attribute without LLCC enabled it just gets ignored. Is that correct Sai? Yes that is correct, I just confirmed now with LLCC team. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 15/15] ARM: dts: bcm2711: Add the CEC interrupt controller
The CEC and hotplug interrupts go through an interrupt controller shared
between the two HDMI controllers.
Let's add that interrupt controller and the interrupts for both HDMI
controllers
Reviewed-by: Florian Fainelli
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 8bb46ae76a92..06b15797ec11 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -316,6 +316,14 @@ bsc_intr: interrupt-controller@7ef00040 {
#interrupt-cells = <1>;
};
+ aon_intr: interrupt-controller@7ef00100 {
+ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+ reg = <0x7ef00100 0x30>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
hdmi0: hdmi@7ef00700 {
compatible = "brcm,bcm2711-hdmi0";
reg = <0x7ef00700 0x300>,
@@ -338,6 +346,11 @@ hdmi0: hdmi@7ef00700 {
"hd";
clock-names = "hdmi", "bvb", "audio", "cec";
resets = < 0>;
+ interrupt-parent = <_intr>;
+ interrupts = <0>, <1>, <2>,
+<3>, <4>, <5>;
+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
+ "wakeup", "hpd-connected",
"hpd-removed";
ddc = <>;
dmas = < 10>;
dma-names = "audio-rx";
@@ -377,6 +390,11 @@ hdmi1: hdmi@7ef05700 {
ddc = <>;
clock-names = "hdmi", "bvb", "audio", "cec";
resets = < 1>;
+ interrupt-parent = <_intr>;
+ interrupts = <8>, <7>, <6>,
+<9>, <10>, <11>;
+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
+ "wakeup", "hpd-connected",
"hpd-removed";
dmas = < 17>;
dma-names = "audio-rx";
status = "disabled";
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 04/15] drm/vc4: hdmi: Fix up CEC registers
From: Dom Cobley
The commit 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout
abstraction") forgot one CEC register, and made a copy and paste mistake
for another one. Fix those mistakes.
Fixes: 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout abstraction")
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
index 401863cb8c98..e1b58eac766f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
@@ -29,6 +29,7 @@ enum vc4_hdmi_field {
HDMI_CEC_CPU_MASK_SET,
HDMI_CEC_CPU_MASK_STATUS,
HDMI_CEC_CPU_STATUS,
+ HDMI_CEC_CPU_SET,
/*
* Transmit data, first byte is low byte of the 32-bit reg.
@@ -199,9 +200,10 @@ static const struct vc4_hdmi_register __maybe_unused
vc4_hdmi_fields[] = {
VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
+ VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
- VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c),
+ VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
};
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] drm: Introduce a drm_crtc_commit_wait helper
There's currently four users of the same logic to wait for a commit to
be flipped: three for the CRTCs, connectors and planes in
drm_atomic_helper_wait_for_dependencies, and one in vc4.
Let's consolidate this a bit to avoid any code duplication.
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Added a note in struct drm_crtc_commit documentation to look at the
new function
---
drivers/gpu/drm/drm_atomic.c| 39 ++
drivers/gpu/drm/drm_atomic_helper.c | 61 +
drivers/gpu/drm/vc4/vc4_kms.c | 17 ++--
include/drm/drm_atomic.h| 4 ++
4 files changed, 56 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index dda60051854b..b1efa9322be2 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -52,6 +52,45 @@ void __drm_crtc_commit_free(struct kref *kref)
}
EXPORT_SYMBOL(__drm_crtc_commit_free);
+/**
+ * drm_crtc_commit_wait - Waits for a commit to complete
+ * @commit: _crtc_commit to wait for
+ *
+ * Waits for a given _crtc_commit to be programmed into the
+ * hardware and flipped to.
+ *
+ * Returns:
+ *
+ * 0 on success, a negative error code otherwise.
+ */
+int drm_crtc_commit_wait(struct drm_crtc_commit *commit)
+{
+ unsigned long timeout = 10 * HZ;
+ int ret;
+
+ if (!commit)
+ return 0;
+
+ ret = wait_for_completion_timeout(>hw_done, timeout);
+ if (!ret) {
+ DRM_ERROR("hw_done timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /*
+* Currently no support for overwriting flips, hence
+* stall for previous one to execute completely.
+*/
+ ret = wait_for_completion_timeout(>flip_done, timeout);
+ if (!ret) {
+ DRM_ERROR("flip_done timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_crtc_commit_wait);
+
/**
* drm_atomic_state_default_release -
* release memory initialized by drm_atomic_state_init
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index a84dc427cf82..9fa3f97223a1 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2202,70 +2202,27 @@ void drm_atomic_helper_wait_for_dependencies(struct
drm_atomic_state *old_state)
struct drm_plane_state *old_plane_state;
struct drm_connector *conn;
struct drm_connector_state *old_conn_state;
- struct drm_crtc_commit *commit;
int i;
long ret;
for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
- commit = old_crtc_state->commit;
-
- if (!commit)
- continue;
-
- ret = wait_for_completion_timeout(>hw_done,
- 10*HZ);
- if (ret == 0)
- DRM_ERROR("[CRTC:%d:%s] hw_done timed out\n",
- crtc->base.id, crtc->name);
-
- /* Currently no support for overwriting flips, hence
-* stall for previous one to execute completely. */
- ret = wait_for_completion_timeout(>flip_done,
- 10*HZ);
- if (ret == 0)
- DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
+ ret = drm_crtc_commit_wait(old_crtc_state->commit);
+ if (ret)
+ DRM_ERROR("[CRTC:%d:%s] commit wait timed out\n",
crtc->base.id, crtc->name);
}
for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
- commit = old_conn_state->commit;
-
- if (!commit)
- continue;
-
- ret = wait_for_completion_timeout(>hw_done,
- 10*HZ);
- if (ret == 0)
- DRM_ERROR("[CONNECTOR:%d:%s] hw_done timed out\n",
- conn->base.id, conn->name);
-
- /* Currently no support for overwriting flips, hence
-* stall for previous one to execute completely. */
- ret = wait_for_completion_timeout(>flip_done,
- 10*HZ);
- if (ret == 0)
- DRM_ERROR("[CONNECTOR:%d:%s] flip_done timed out\n",
+ ret = drm_crtc_commit_wait(old_conn_state->commit);
+ if (ret)
+ DRM_ERROR("[CONNECTOR:%d:%s] commit wait timed out\n",
conn->base.id, conn->name);
}
for_each_old_plane_in_state(old_state, plane, old_plane_state, i) {
- commit = old_plane_state->commit;
-
- if (!commit)
-
Re: [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling
On Fri, Jan 08, 2021 at 03:34:52PM +0100, Giulio Benetti wrote: > Hi, > > On 1/8/21 10:23 AM, Maxime Ripard wrote: > > Hi, > > > > Thanks for those patches > > > > On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote: > > > From: Giulio Benetti > > > > > > It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is > > > dedicated to invert DCLK polarity and this makes thing really easier than > > > before. So let's handle DCLK polarity by adding > > > SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to > > > bus_flags the same way is done for all the other signals. > > > > > > Cc: Maxime Ripard > > > > Suggested-by would be nice here :) > > Ok, didn't know about this tag > > > > Signed-off-by: Giulio Benetti > > > --- > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +--- > > > drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + > > > 2 files changed, 2 insertions(+), 19 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > index 52598bb0fb0b..30171ccd87e5 100644 > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct > > > sun4i_tcon *tcon, > > > if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) > > > val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; > > > - /* > > > - * On A20 and similar SoCs, the only way to achieve Positive Edge > > > - * (Rising Edge), is setting dclk clock phase to 2/3(240°). > > > - * By default TCON works in Negative Edge(Falling Edge), > > > - * this is why phase is set to 0 in that case. > > > - * Unfortunately there's no way to logically invert dclk through > > > - * IO_POL register. > > > - * The only acceptable way to work, triple checked with scope, > > > - * is using clock phase set to 0° for Negative Edge and set to 240° > > > - * for Positive Edge. > > > - * On A33 and similar SoCs there would be a 90° phase option, > > > - * but it divides also dclk by 2. > > > - * Following code is a way to avoid quirks all around TCON > > > - * and DOTCLOCK drivers. > > > - */ > > > if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) > > > - clk_set_phase(tcon->dclk, 0); > > > - > > > - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) > > > - clk_set_phase(tcon->dclk, 240); > > > + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE; > > > > I'm not really sure why we need the first patch of this series here? > > The idea was to have 2 for testing, 1st one is already applicable, while the > other must be tested, but I can send only one with no problem. > > > That patch only seem to undo what you did in patch 1 > > No, it doesn't, the 2nd one change the way it achieve the same thing, > because the 1st swap DCLK phase, while the 2nd uses the IO_POL bit to set IO > polarity according to bus_flags. It makes sense for testing, but I'm not sure we want to carry it into the history. Can you squash them both into the same patch? Thanks! Maxime signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: Removes invalid function return value comment information
Signed-off-by: Zhaoge Zhang
---
drivers/gpu/drm/drm_file.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index b50380f..8548e8b 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -240,9 +240,6 @@ static void drm_events_release(struct drm_file *file_priv)
* before calling this.
*
* If NULL is passed, this is a no-op.
- *
- * RETURNS:
- * 0 on success, or error code on failure.
*/
void drm_file_free(struct drm_file *file)
{
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers
Use the newly introduced IOMMU_LLC page protection flag to map
GPU buffers. This will make sure that proper stage-1 PTE
attributes are set for GPU buffers to use system cache. This
also introduces MMU_FEATURE_USE_LLC features bit to check for
GPUs supporting LLC and set them in the target specific address
space creation, in this case we set them for A6XX GPUs.
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
drivers/gpu/drm/msm/msm_iommu.c | 3 +++
drivers/gpu/drm/msm/msm_mmu.h | 4
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 3c7ad51732bb..23da21b6f0ff 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1266,6 +1266,9 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct
platform_device *pdev)
return ERR_CAST(mmu);
}
+ if (!IS_ERR_OR_NULL(a6xx_gpu->llc_slice))
+ mmu->features |= MMU_FEATURE_USE_LLC;
+
/*
* Use the aperture start or SZ_16M, whichever is greater. This will
* ensure that we align with the allocated pagetable range while still
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 22ac7c692a81..a329f9836422 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -235,6 +235,9 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
if (iova & BIT_ULL(48))
iova |= GENMASK_ULL(63, 49);
+ if (mmu->features & MMU_FEATURE_USE_LLC)
+ prot |= IOMMU_LLC;
+
ret = iommu_map_sgtable(iommu->domain, iova, sgt, prot);
WARN_ON(!ret);
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
index 61ade89d9e48..efcd1939c98e 100644
--- a/drivers/gpu/drm/msm/msm_mmu.h
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -23,12 +23,16 @@ enum msm_mmu_type {
MSM_MMU_IOMMU_PAGETABLE,
};
+/* MMU features */
+#define MMU_FEATURE_USE_LLCBIT(0)
+
struct msm_mmu {
const struct msm_mmu_funcs *funcs;
struct device *dev;
int (*handler)(void *arg, unsigned long iova, int flags);
void *arg;
enum msm_mmu_type type;
+ u32 features;
};
static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/3] iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag
Add a new page protection flag IOMMU_LLC which can be used by non-coherent masters to set cacheable memory attributes for an outer level of cache called as last-level cache or system cache. Initial user of this page protection flag is the adreno gpu and then can later be used by other clients such as video where this can be used for per-buffer based mapping. Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/io-pgtable-arm.c | 3 +++ include/linux/iommu.h | 6 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 7439ee7fdcdb..ebe653ef601b 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -415,6 +415,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, else if (prot & IOMMU_CACHE) pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE << ARM_LPAE_PTE_ATTRINDX_SHIFT); + else if (prot & IOMMU_LLC) + pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE + << ARM_LPAE_PTE_ATTRINDX_SHIFT); } if (prot & IOMMU_CACHE) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ffaa389ea128..1f82057df531 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -31,6 +31,12 @@ * if the IOMMU page table format is equivalent. */ #define IOMMU_PRIV (1 << 5) +/* + * Non-coherent masters can use this page protection flag to set cacheable + * memory attributes for only a transparent outer level of cache, also known as + * the last-level or system cache. + */ +#define IOMMU_LLC (1 << 6) struct iommu_ops; struct iommu_group; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v16 0/4] RDMA: Add dma-buf support
On Mon, Jan 11, 2021 at 03:24:18PM +, Xiong, Jianxin wrote: > Jason, will this series be able to get into 5.12? I was going to ask you where things are after the break? Did everyone agree the userspace stuff is OK now? Is Edward OK with the pyverbs changes, etc Jason ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 172
2 files changed, 179 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..9abba13df68e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,178 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+ /bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+
Re: [PATCH 2/2] drm/msm/dp: unplug interrupt missed after irq_hpd handler
Quoting Kuogee Hsieh (2021-01-07 12:30:25)
> There is HPD unplug interrupts missed at scenario of an irq_hpd
> followed by unplug interrupts with around 10 ms in between.
> Since both AUX_SW_RESET and DP_SW_RESET clear pending HPD interrupts,
> irq_hpd handler should not issues either aux or sw reset to avoid
> following unplug interrupt be cleared accidentally.
So the problem is that we're resetting the DP aux phy in the middle of
the HPD state machine transitioning states?
>
> Signed-off-by: Kuogee Hsieh
> ---
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
> b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 44f0c57..9c0ce98 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -190,6 +190,18 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog
> *dp_catalog)
> return 0;
> }
>
> +/**
> + * dp_catalog_aux_reset() - reset AUX controller
> + *
> + * @aux: DP catalog structure
> + *
> + * return: void
> + *
> + * This function reset AUX controller
> + *
> + * NOTE: reset AUX controller will also clear any pending HPD related
> interrupts
> + *
> + */
> void dp_catalog_aux_reset(struct dp_catalog *dp_catalog)
> {
> u32 aux_ctrl;
> @@ -483,6 +495,18 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog
> *dp_catalog,
> return 0;
> }
>
> +/**
> + * dp_catalog_ctrl_reset() - reset DP controller
> + *
> + * @aux: DP catalog structure
It's called dp_catalog though.
> + *
> + * return: void
> + *
> + * This function reset DP controller
resets the
> + *
> + * NOTE: reset DP controller will also clear any pending HPD related
> interrupts
> + *
> + */
> void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog)
> {
> u32 sw_reset;
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index e3462f5..f96c415 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -1296,7 +1296,8 @@ static int dp_ctrl_setup_main_link(struct
> dp_ctrl_private *ctrl,
> * transitioned to PUSH_IDLE. In order to start transmitting
> * a link training pattern, we have to first do soft reset.
> */
> - dp_catalog_ctrl_reset(ctrl->catalog);
> + if (*training_step != DP_TRAINING_NONE)
Can we check for the positive value instead? i.e.
DP_TRAINING_1/DP_TRAINING_2
> + dp_catalog_ctrl_reset(ctrl->catalog);
>
> ret = dp_ctrl_link_train(ctrl, cr, training_step);
>
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 03/15] drm/vc4: hdmi: Fix register offset with longer CEC messages
From: Dom Cobley
The code prior to 311e305fdb4e ("drm/vc4: hdmi: Implement a register
layout abstraction") was relying on the fact that the register offset
was incremented by 4 for each readl call. That worked since the register
width is 4 bytes.
However, since that commit the HDMI_READ macro is now taking an enum,
and the offset doesn't increment by 4 but 1 now. Divide the index by 4
to fix this.
Fixes: 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout abstraction")
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index cb4594e7df6f..7945dbcee78c 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1443,13 +1443,20 @@ static irqreturn_t vc4_cec_irq_handler_thread(int irq,
void *priv)
static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
{
+ struct drm_device *dev = vc4_hdmi->connector.dev;
struct cec_msg *msg = _hdmi->cec_rx_msg;
unsigned int i;
msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
+
+ if (msg->len > 16) {
+ drm_err(dev, "Attempting to read too much data (%d)\n",
msg->len);
+ return;
+ }
+
for (i = 0; i < msg->len; i += 4) {
- u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i);
+ u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
msg->msg[i] = val & 0xff;
msg->msg[i + 1] = (val >> 8) & 0xff;
@@ -1542,11 +1549,17 @@ static int vc4_hdmi_cec_adap_transmit(struct
cec_adapter *adap, u8 attempts,
u32 signal_free_time, struct cec_msg *msg)
{
struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
+ struct drm_device *dev = vc4_hdmi->connector.dev;
u32 val;
unsigned int i;
+ if (msg->len > 16) {
+ drm_err(dev, "Attempting to transmit too much data (%d)\n",
msg->len);
+ return -ENOMEM;
+ }
+
for (i = 0; i < msg->len; i += 4)
- HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i,
+ HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
(msg->msg[i]) |
(msg->msg[i + 1] << 8) |
(msg->msg[i + 2] << 16) |
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 13/15] dt-binding: display: bcm2711-hdmi: Add CEC and hotplug interrupts
The CEC and hotplug interrupts were missing when that binding was introduced, let's add them in now that we've figured out how it works. Signed-off-by: Maxime Ripard --- .../bindings/display/brcm,bcm2711-hdmi.yaml | 20 ++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml index 7ce06f9f9f8e..6e8ac910bdd8 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml @@ -53,6 +53,24 @@ properties: - const: audio - const: cec + interrupts: +items: + - description: CEC TX interrupt + - description: CEC RX interrupt + - description: CEC stuck at low interrupt + - description: Wake-up interrupt + - description: Hotplug connected interrupt + - description: Hotplug removed interrupt + + interrupt-names: +items: + - const: cec-tx + - const: cec-rx + - const: cec-low + - const: wakeup + - const: hpd-connected + - const: hpd-removed + ddc: allOf: - $ref: /schemas/types.yaml#/definitions/phandle @@ -90,7 +108,7 @@ required: - resets - ddc -additionalProperties: false +unevaluatedProperties: false examples: - | -- 2.29.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 05/15] drm/vc4: hdmi: Restore cec physical address on reconnect
From: Dom Cobley
Currently we call cec_phys_addr_invalidate on a hotplug deassert.
That may be due to a TV power cycling, or an AVR being switched
on (and switching edid).
This makes CEC unusable since our controller wouldn't have a physical
address anymore.
Set it back up again on the hotplug assert.
Fixes: 15b4511a4af6 ("drm/vc4: add HDMI CEC support")
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 7945dbcee78c..c3a301396aad 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -136,20 +136,32 @@ static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
+ bool connected = false;
if (vc4_hdmi->hpd_gpio) {
if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
vc4_hdmi->hpd_active_low)
- return connector_status_connected;
- cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
- return connector_status_disconnected;
+ connected = true;
+ } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
+ connected = true;
+ } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
+ connected = true;
}
- if (drm_probe_ddc(vc4_hdmi->ddc))
- return connector_status_connected;
+ if (connected) {
+ if (connector->status != connector_status_connected) {
+ struct edid *edid = drm_get_edid(connector,
vc4_hdmi->ddc);
+
+ if (edid) {
+ cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap,
edid);
+ vc4_hdmi->encoder.hdmi_monitor =
drm_detect_hdmi_monitor(edid);
+ kfree(edid);
+ }
+ }
- if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
return connector_status_connected;
+ }
+
cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
return connector_status_disconnected;
}
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 08/15] drm/vc4: hdmi: Introduce a CEC clock
While the BCM2835 had the CEC clock derived from the HSM clock, the
BCM2711 has a dedicated parent clock for it.
Let's introduce a separate clock for it so that we can handle both
cases.
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 9 -
drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 0627b8db32f6..7b5c92df8f1b 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -145,7 +145,7 @@ static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi
*vc4_hdmi)
* Set the clock divider: the hsm_clock rate and this divider
* setting will give a 40 kHz CEC clock.
*/
- clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
+ clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
}
@@ -1752,6 +1752,7 @@ static int vc4_hdmi_init_resources(struct vc4_hdmi
*vc4_hdmi)
return PTR_ERR(vc4_hdmi->hsm_clock);
}
vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
+ vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
return 0;
}
@@ -1845,6 +1846,12 @@ static int vc5_hdmi_init_resources(struct vc4_hdmi
*vc4_hdmi)
return PTR_ERR(vc4_hdmi->audio_clock);
}
+ vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
+ if (IS_ERR(vc4_hdmi->cec_clock)) {
+ DRM_ERROR("Failed to get CEC clock\n");
+ return PTR_ERR(vc4_hdmi->cec_clock);
+ }
+
vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
if (IS_ERR(vc4_hdmi->reset)) {
DRM_ERROR("Failed to get HDMI reset line\n");
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 4c8994cfd932..6966db1a0957 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -155,6 +155,7 @@ struct vc4_hdmi {
bool cec_tx_ok;
bool cec_irq_was_rx;
+ struct clk *cec_clock;
struct clk *pixel_clock;
struct clk *hsm_clock;
struct clk *audio_clock;
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 09/15] drm/vc4: hdmi: Split the interrupt handlers
The BCM2711 has two different interrupt sources to transmit and receive
CEC messages, provided through an external interrupt chip shared between
the two HDMI interrupt controllers.
The rest of the CEC controller is identical though so we need to change
a bit the code organisation to share the code as much as possible, yet
still allowing to register independant handlers.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 86 +-
1 file changed, 65 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 7b5c92df8f1b..12ca5f3084af 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1454,15 +1454,22 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi
*vc4_hdmi)
}
#ifdef CONFIG_DRM_VC4_HDMI_CEC
-static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
+static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
{
struct vc4_hdmi *vc4_hdmi = priv;
- if (vc4_hdmi->cec_irq_was_rx) {
- if (vc4_hdmi->cec_rx_msg.len)
- cec_received_msg(vc4_hdmi->cec_adap,
-_hdmi->cec_rx_msg);
- } else if (vc4_hdmi->cec_tx_ok) {
+ if (vc4_hdmi->cec_rx_msg.len)
+ cec_received_msg(vc4_hdmi->cec_adap,
+_hdmi->cec_rx_msg);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
+{
+ struct vc4_hdmi *vc4_hdmi = priv;
+
+ if (vc4_hdmi->cec_tx_ok) {
cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
0, 0, 0, 0);
} else {
@@ -1476,6 +1483,19 @@ static irqreturn_t vc4_cec_irq_handler_thread(int irq,
void *priv)
return IRQ_HANDLED;
}
+static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
+{
+ struct vc4_hdmi *vc4_hdmi = priv;
+ irqreturn_t ret;
+
+ if (vc4_hdmi->cec_irq_was_rx)
+ ret = vc4_cec_irq_handler_rx_thread(irq, priv);
+ else
+ ret = vc4_cec_irq_handler_tx_thread(irq, priv);
+
+ return ret;
+}
+
static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
{
struct drm_device *dev = vc4_hdmi->connector.dev;
@@ -1500,31 +1520,55 @@ static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi,
u32 cntrl1)
}
}
+static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
+{
+ struct vc4_hdmi *vc4_hdmi = priv;
+ u32 cntrl1;
+
+ cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
+ vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
+ cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
+ HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
+
+ return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
+{
+ struct vc4_hdmi *vc4_hdmi = priv;
+ u32 cntrl1;
+
+ vc4_hdmi->cec_rx_msg.len = 0;
+ cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
+ vc4_cec_read_msg(vc4_hdmi, cntrl1);
+ cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
+ HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
+ cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
+
+ HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
+
+ return IRQ_WAKE_THREAD;
+}
+
static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
{
struct vc4_hdmi *vc4_hdmi = priv;
u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
- u32 cntrl1, cntrl5;
+ irqreturn_t ret;
+ u32 cntrl5;
if (!(stat & VC4_HDMI_CPU_CEC))
return IRQ_NONE;
- vc4_hdmi->cec_rx_msg.len = 0;
- cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
+
cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
- if (vc4_hdmi->cec_irq_was_rx) {
- vc4_cec_read_msg(vc4_hdmi, cntrl1);
- cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
- HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
- cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
- } else {
- vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
- cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
- }
- HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
+ if (vc4_hdmi->cec_irq_was_rx)
+ ret = vc4_cec_irq_handler_rx_bare(irq, priv);
+ else
+ ret = vc4_cec_irq_handler_tx_bare(irq, priv);
+
HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
-
- return IRQ_WAKE_THREAD;
+ return ret;
}
static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 06/15] drm/vc4: hdmi: Compute the CEC clock divider from the clock rate
The CEC clock divider needs to output a frequency of 40kHz from the HSM
rate on the BCM2835. The driver used to have a fixed frequency for it,
but that changed for the BCM2711 and we now need to compute it
dynamically to maintain the proper rate.
Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel
rate")
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c3a301396aad..50008513edfc 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1598,6 +1598,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
{
struct cec_connector_info conn_info;
struct platform_device *pdev = vc4_hdmi->pdev;
+ u16 clk_cnt;
u32 value;
int ret;
@@ -1623,8 +1624,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
* divider: the hsm_clock rate and this divider setting will
* give a 40 kHz CEC clock.
*/
+ clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
value |= VC4_HDMI_CEC_ADDR_MASK |
-(4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+(clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
ret = devm_request_threaded_irq(>dev, platform_get_irq(pdev, 0),
vc4_cec_irq_handler,
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type setting required for the non-coherent masters to use
system cache. Now that system cache support for GPU is added, we will
need to set the right PTE attribute for GPU buffers to be sys cached.
Without this, the system cache lines are not allocated for GPU.
So the patches in this series introduces a new prot flag IOMMU_LLC,
renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC
and makes GPU the user of this protection flag.
The series slightly depends on following 2 patches posted earlier and
is based on msm-next branch:
* https://lore.kernel.org/patchwork/patch/1363008/
* https://lore.kernel.org/patchwork/patch/1363010/
Sai Prakash Ranjan (3):
iommu/io-pgtable: Rename last-level cache quirk to
IO_PGTABLE_QUIRK_PTW_LLC
iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag
drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 3 +++
drivers/gpu/drm/msm/msm_mmu.h | 4
drivers/iommu/io-pgtable-arm.c | 9 ++---
include/linux/io-pgtable.h | 6 +++---
include/linux/iommu.h | 6 ++
7 files changed, 26 insertions(+), 7 deletions(-)
base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH -next] drm/amd/display: tweak the kerneldoc for active_vblank_irq_count
Commit 71338cb4a7c2 ("drm/amd/display: enable idle optimizations for linux
(MALL stutter)") adds active_vblank_irq_count to amdgpu_display_manager
in ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h.
The kerneldoc is incorrectly formatted, and make htmldocs warns:
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:
340: warning: Incorrect use of kernel-doc format: *
@active_vblank_irq_count
379: warning: Function parameter or member 'active_vblank_irq_count' not
described in 'amdgpu_display_manager'
Tweak the kerneldoc for active_vblank_irq_count.
Signed-off-by: Lukas Bulwahn
---
applies on amdgpu's -next and next-20210111
Bhawanpreet, Nick, please review and ack.
Alex, Christian, please pick on top of the commit above.
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index f084e2fc9569..5ee1b766884e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -337,7 +337,7 @@ struct amdgpu_display_manager {
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
/**
-* @active_vblank_irq_count
+* @active_vblank_irq_count:
*
* number of currently active vblank irqs
*/
--
2.17.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 00/15] drm/vc4: hdmi: Add CEC support for the BCM2711
Hi, Here's a series introducing the CEC support for the BCM2711 found on the RaspberryPi4. The BCM2711 HDMI controller uses a similar layout for the CEC registers, the main difference being that the interrupt handling part is now shared between both HDMI controllers. This series is mainly about fixing a couple of bugs, reworking the driver to support having two different interrupts, one for each direction, provided by an external irqchip, and enables the irqchip driver for the controller we have. This has been tested on an RPi3 and RPi4, but requires the latest firmware. It's is based on the 10 and 12 bpc series. Here is the cec-compliance output: pi@raspberrypi:~$ cec-ctl --tuner -p 1.0.0.0 The CEC adapter doesn't allow setting the physical address manually, ignore this option. Driver Info: Driver Name: vc4_hdmi Adapter Name : vc4 Capabilities : 0x010e Logical Addresses Transmit Passthrough Driver version : 5.10.0 Available Logical Addresses: 1 Physical Address : 1.0.0.0 Logical Address Mask : 0x0008 CEC Version: 2.0 Vendor ID : 0x000c03 (HDMI) OSD Name : Tuner Logical Addresses : 1 (Allow RC Passthrough) Logical Address : 3 (Tuner 1) Primary Device Type: Tuner Logical Address Type : Tuner All Device Types : Tuner RC TV Profile : None Device Features: None pi@raspberrypi:~$ cec-compliance cec-compliance SHA : not available Driver Info: Driver Name: vc4_hdmi Adapter Name : vc4 Capabilities : 0x010e Logical Addresses Transmit Passthrough Driver version : 5.10.0 Available Logical Addresses: 1 Physical Address : 1.0.0.0 Logical Address Mask : 0x0008 CEC Version: 2.0 Vendor ID : 0x000c03 (HDMI) OSD Name : Tuner Logical Addresses : 1 (Allow RC Passthrough) Logical Address : 3 (Tuner 1) Primary Device Type: Tuner Logical Address Type : Tuner All Device Types : Tuner RC TV Profile : None Device Features: None Compliance test for device /dev/cec0: The test results mean the following: OK Supported correctly by the device. OK (Not Supported) Not supported and not mandatory for the device. OK (Presumed) Presumably supported. Manually check to confirm. OK (Unexpected) Supported correctly but is not expected to be supported for this device. OK (Refused)Supported by the device, but was refused. FAILFailed and was expected to be supported by this device. Find remote devices: Polling: OK Network topology: System Information for device 0 (TV) from device 3 (Tuner 1): CEC Version: 2.0 Physical Address : 0.0.0.0 Primary Device Type: TV Vendor ID : 0x000c03 OSD Name : 'TV ' Power Status : Tx, OK, Rx, OK, Feature Abort Total: 1, Succeeded: 1, Failed: 0, Warnings: 0 pi@raspberrypi:~$ cec-ctl -d1 --tuner -p 1.0.0.0 The CEC adapter doesn't allow setting the physical address manually, ignore this option. Driver Info: Driver Name: vc4_hdmi Adapter Name : vc4 Capabilities : 0x010e Logical Addresses Transmit Passthrough Driver version : 5.10.0 Available Logical Addresses: 1 Physical Address : 1.0.0.0 Logical Address Mask : 0x0008 CEC Version: 2.0 Vendor ID : 0x000c03 (HDMI) OSD Name : Tuner Logical Addresses : 1 (Allow RC Passthrough) Logical Address : 3 (Tuner 1) Primary Device Type: Tuner Logical Address Type : Tuner All Device Types : Tuner RC TV Profile : None Device Features: None pi@raspberrypi:~$ cec-compliance -d1 cec-compliance SHA : not available Driver Info: Driver Name: vc4_hdmi Adapter Name : vc4 Capabilities : 0x010e
[PATCH v2 11/15] drm/vc4: hdmi: Remove cec_available flag
From: Dom Cobley
Now that our HDMI controller supports CEC for the BCM2711, let's remove
that flag.
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ---
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index d116ecfd8cf7..5a606b6f2917 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1670,9 +1670,6 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
u32 value;
int ret;
- if (!vc4_hdmi->variant->cec_available)
- return 0;
-
vc4_hdmi->cec_adap = cec_allocate_adapter(_hdmi_cec_adap_ops,
vc4_hdmi, "vc4",
CEC_CAP_DEFAULTS |
@@ -2086,7 +2083,6 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.debugfs_name = "hdmi_regs",
.card_name = "vc4-hdmi",
.max_pixel_clock= 16200,
- .cec_available = true,
.registers = vc4_hdmi_fields,
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index d71f6ed321bf..3cebd1fd00fc 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -42,9 +42,6 @@ struct vc4_hdmi_variant {
/* Filename to expose the registers in debugfs */
const char *debugfs_name;
- /* Set to true when the CEC support is available */
- bool cec_available;
-
/* Maximum pixel clock supported by the controller (in Hz) */
unsigned long long max_pixel_clock;
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 14/15] ARM: dts: bcm2711: Add the BSC interrupt controller
The BSC controllers used for the HDMI DDC have an interrupt controller
shared between both instances. Let's add it to avoid polling.
Reviewed-by: Florian Fainelli
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 4847dd305317..8bb46ae76a92 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -308,6 +308,14 @@ dvp: clock@7ef0 {
#reset-cells = <1>;
};
+ bsc_intr: interrupt-controller@7ef00040 {
+ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+ reg = <0x7ef00040 0x30>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
hdmi0: hdmi@7ef00700 {
compatible = "brcm,bcm2711-hdmi0";
reg = <0x7ef00700 0x300>,
@@ -341,6 +349,8 @@ ddc0: i2c@7ef04500 {
reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
+ interrupt-parent = <_intr>;
+ interrupts = <0>;
status = "disabled";
};
@@ -377,6 +387,8 @@ ddc1: i2c@7ef09500 {
reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
+ interrupt-parent = <_intr>;
+ interrupts = <1>;
status = "disabled";
};
};
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [patch V3 13/37] mips/mm/highmem: Switch to generic kmap atomic
On 2021-01-09 01:33:52 [+0100], Thomas Bogendoerfer wrote:
> On Sat, Jan 09, 2021 at 12:58:05AM +0100, Thomas Bogendoerfer wrote:
> > On Fri, Jan 08, 2021 at 08:20:43PM +, Paul Cercueil wrote:
> > > Hi Thomas,
> > >
> > > 5.11 does not boot anymore on Ingenic SoCs, I bisected it to this commit.
> > >
> > > Any idea what could be happening?
> >
> > not yet, kernel crash log of a Malta QEMU is below.
>
> update:
>
> This dirty hack lets the Malta QEMU boot again:
>
> diff --git a/mm/highmem.c b/mm/highmem.c
> index c3a9ea7875ef..190cdda1149d 100644
> --- a/mm/highmem.c
> +++ b/mm/highmem.c
> @@ -515,7 +515,7 @@ void *__kmap_local_pfn_prot(unsigned long pfn, pgprot_t
> prot)
> vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
> BUG_ON(!pte_none(*(kmap_pte - idx)));
> pteval = pfn_pte(pfn, prot);
> - set_pte_at(_mm, vaddr, kmap_pte - idx, pteval);
> + set_pte(kmap_pte - idx, pteval);
> arch_kmap_local_post_map(vaddr, pteval);
> current->kmap_ctrl.pteval[kmap_local_idx()] = pteval;
> preempt_enable();
>
> set_pte_at() tries to update cache and could do an kmap_atomic() there.
So the old implementation used set_pte() while the new one uses
set_pte_at().
> Not sure, if this is allowed at this point.
The problem is the recursion
kmap_atomic() -> __update_cache() -> kmap_atomic()
and kmap_local_idx_push() runs out if index space before stack space.
I'm not sure if the __update_cache() worked for highmem. It has been
added for that in commit
f4281bba81810 ("MIPS: Handle highmem pages in __update_cache")
but it assumes that the address returned by kmap_atomic() is the same or
related enough for flush_data_cache_page() to work.
> Thomas.
>
Sebastian
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH -next] phy: mediatek: Mark mtk_mipi_tx_driver with static keyword
Fix the following sparse warning:
drivers/phy/mediatek/phy-mtk-mipi-dsi.c:237:24: warning: symbol
'mtk_mipi_tx_driver' was not declared. Should it be static?
Signed-off-by: Zou Wei
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
index 18c4812..eeb357b 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
@@ -234,7 +234,7 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
{ },
};
-struct platform_driver mtk_mipi_tx_driver = {
+static struct platform_driver mtk_mipi_tx_driver = {
.probe = mtk_mipi_tx_probe,
.remove = mtk_mipi_tx_remove,
.driver = {
--
2.6.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/3] iommu/io-pgtable: Rename last-level cache quirk to IO_PGTABLE_QUIRK_PTW_LLC
Rename last-level cache quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to
IO_PGTABLE_QUIRK_PTW_LLC which is used to set the required TCR
attributes for non-coherent page table walker to be more generic
and in sync with the upcoming page protection flag IOMMU_LLC.
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/iommu/io-pgtable-arm.c | 6 +++---
include/linux/io-pgtable.h | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0f184c3dd9d9..82b5e4969195 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -190,7 +190,7 @@ void adreno_set_llc_attributes(struct iommu_domain *iommu)
{
struct io_pgtable_domain_attr pgtbl_cfg;
- pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
+ pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_PTW_LLC;
iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, _cfg);
}
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 7c9ea9d7874a..7439ee7fdcdb 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -762,7 +762,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg,
void *cookie)
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NON_STRICT |
IO_PGTABLE_QUIRK_ARM_TTBR1 |
- IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
+ IO_PGTABLE_QUIRK_PTW_LLC))
return NULL;
data = arm_lpae_alloc_pgtable(cfg);
@@ -774,12 +774,12 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg,
void *cookie)
tcr->sh = ARM_LPAE_TCR_SH_IS;
tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)
+ if (cfg->quirks & IO_PGTABLE_QUIRK_PTW_LLC)
goto out_free_data;
} else {
tcr->sh = ARM_LPAE_TCR_SH_OS;
tcr->irgn = ARM_LPAE_TCR_RGN_NC;
- if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
+ if (!(cfg->quirks & IO_PGTABLE_QUIRK_PTW_LLC))
tcr->orgn = ARM_LPAE_TCR_RGN_NC;
else
tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index fb4d5a763e0c..6f996a817441 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -87,8 +87,8 @@ struct io_pgtable_cfg {
* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
* for use in the upper half of a split address space.
*
-* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
-* attributes set in the TCR for a non-coherent page-table walker.
+* IO_PGTABLE_QUIRK_PTW_LLC: Override the outer-cacheability attributes
+* set in the TCR for a non-coherent page-table walker.
*/
#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -96,7 +96,7 @@ struct io_pgtable_cfg {
#define IO_PGTABLE_QUIRK_ARM_MTK_EXTBIT(3)
#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
+ #define IO_PGTABLE_QUIRK_PTW_LLCBIT(6)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned intias;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: Fix macro name DRM_MODE_PROP_OBJECT in code comment
Signed-off-by: Zhaoge Zhang
---
include/drm/drm_property.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
index 4a0a80d..bbf5c1fd 100644
--- a/include/drm/drm_property.h
+++ b/include/drm/drm_property.h
@@ -114,7 +114,7 @@ struct drm_property {
* by the property. Bitmask properties are created using
* drm_property_create_bitmask().
*
-* DRM_MODE_PROB_OBJECT
+* DRM_MODE_PROP_OBJECT
* Object properties are used to link modeset objects. This is used
* extensively in the atomic support to create the display pipeline,
* by linking _framebuffer to _plane, _plane to
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: arc: Use simple encoder
The arc driver uses empty implementations for its encoders. Replace
the code with the generic simple encoder.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/arc/arcpgu_hdmi.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/arc/arcpgu_hdmi.c
b/drivers/gpu/drm/arc/arcpgu_hdmi.c
index 5283993..71ef75f 100644
--- a/drivers/gpu/drm/arc/arcpgu_hdmi.c
+++ b/drivers/gpu/drm/arc/arcpgu_hdmi.c
@@ -9,13 +9,10 @@
#include
#include
#include
+#include
#include "arcpgu.h"
-static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = {
- .destroy = drm_encoder_cleanup,
-};
-
int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np)
{
struct drm_encoder *encoder;
@@ -34,8 +31,7 @@ int arcpgu_drm_hdmi_init(struct drm_device *drm, struct
device_node *np)
encoder->possible_crtcs = 1;
encoder->possible_clones = 0;
- ret = drm_encoder_init(drm, encoder, _drm_encoder_funcs,
- DRM_MODE_ENCODER_TMDS, NULL);
+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
if (ret)
return ret;
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 01/15] ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835
@Maxime it seems you forgot to CC me on the series :) On Mon, 2021-01-11 at 08:54 -0800, Florian Fainelli wrote: > > On 1/11/2021 6:22 AM, Maxime Ripard wrote: > > The BCM2711 has a number of instances of interrupt controllers handled > > by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). > > > > Let's select that driver as part of the ARCH_BCM2835 Kconfig option. > > > > Signed-off-by: Maxime Ripard > > Acked-by: Florian Fainelli > > Nicolas, I suppose you will be taking patches 1 and 14, 15 through the > SoC pull request, right? Yes, that's about right. But I think it'd be nice to wait a bit to see if RobH has something to say. Regards, Nicolas signature.asc Description: This is a digitally signed message part ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] drm/msm/dp: postpone irq_hpd event during connection pending state
Quoting Kuogee Hsieh (2021-01-07 12:30:24)
> irq_hpd event can only be executed at connected state. Therefore
> irq_hpd event should be postponed if it happened at connection
> pending state. This patch also make sure both link rate and lane
Why does it happen at connection pending state?
> are valid before start link training.
Can this part about link rate and lane being valid be split off into
another patch?
>
> Signed-off-by: Kuogee Hsieh
> ---
Any fixes tag?
> drivers/gpu/drm/msm/dp/dp_display.c | 7 +++
> drivers/gpu/drm/msm/dp/dp_panel.c | 12 +---
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 6e971d5..3bc7ed2 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -693,6 +693,13 @@ static int dp_irq_hpd_handle(struct dp_display_private
> *dp, u32 data)
> return 0;
> }
>
> + if (state == ST_CONNECT_PENDING) {
> + /* wait until ST_CONNECTED */
> + dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */
> + mutex_unlock(>event_mutex);
> + return 0;
> + }
> +
> ret = dp_display_usbpd_attention_cb(>pdev->dev);
> if (ret == -ECONNRESET) { /* cable unplugged */
> dp->core_initialized = false;
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 01/15] ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835
On 1/11/2021 6:22 AM, Maxime Ripard wrote: > The BCM2711 has a number of instances of interrupt controllers handled > by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). > > Let's select that driver as part of the ARCH_BCM2835 Kconfig option. > > Signed-off-by: Maxime Ripard Acked-by: Florian Fainelli Nicolas, I suppose you will be taking patches 1 and 14, 15 through the SoC pull request, right? -- Florian ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 10/15] drm/vc4: hdmi: Support BCM2711 CEC interrupt setup
The HDMI controller found in the BCM2711 has an external interrupt
controller for the CEC and hotplug interrupt shared between the two
instances.
Let's add a variant flag to register a single interrupt handler and
deals with the interrupt handler setup, or two interrupt handlers
relying on an external irqchip.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 42 ++
drivers/gpu/drm/vc4/vc4_hdmi.h | 7 ++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 12ca5f3084af..d116ecfd8cf7 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1605,9 +1605,11 @@ static int vc4_hdmi_cec_adap_enable(struct cec_adapter
*adap, bool enable)
((3600 / usecs) <<
VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
((3500 / usecs) <<
VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
- HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
+ if (!vc4_hdmi->variant->external_irq_controller)
+ HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
} else {
- HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
+ if (!vc4_hdmi->variant->external_irq_controller)
+ HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
}
@@ -1682,8 +1684,6 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
cec_fill_conn_info_from_drm(_info, _hdmi->connector);
cec_s_conn_info(vc4_hdmi->cec_adap, _info);
- HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0x);
-
value = HDMI_READ(HDMI_CEC_CNTRL_1);
/* Set the logical address to Unregistered */
value |= VC4_HDMI_CEC_ADDR_MASK;
@@ -1691,12 +1691,32 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
vc4_hdmi_cec_update_clk_div(vc4_hdmi);
- ret = devm_request_threaded_irq(>dev, platform_get_irq(pdev, 0),
- vc4_cec_irq_handler,
- vc4_cec_irq_handler_thread, 0,
- "vc4 hdmi cec", vc4_hdmi);
- if (ret)
- goto err_delete_cec_adap;
+ if (vc4_hdmi->variant->external_irq_controller) {
+ ret = devm_request_threaded_irq(>dev,
+ platform_get_irq_byname(pdev,
"cec-rx"),
+ vc4_cec_irq_handler_rx_bare,
+ vc4_cec_irq_handler_rx_thread,
0,
+ "vc4 hdmi cec rx", vc4_hdmi);
+ if (ret)
+ goto err_delete_cec_adap;
+
+ ret = devm_request_threaded_irq(>dev,
+ platform_get_irq_byname(pdev,
"cec-tx"),
+ vc4_cec_irq_handler_tx_bare,
+ vc4_cec_irq_handler_tx_thread,
0,
+ "vc4 hdmi cec tx", vc4_hdmi);
+ if (ret)
+ goto err_delete_cec_adap;
+ } else {
+ HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0x);
+
+ ret = devm_request_threaded_irq(>dev,
platform_get_irq(pdev, 0),
+ vc4_cec_irq_handler,
+ vc4_cec_irq_handler_thread, 0,
+ "vc4 hdmi cec", vc4_hdmi);
+ if (ret)
+ goto err_delete_cec_adap;
+ }
ret = cec_register_adapter(vc4_hdmi->cec_adap, >dev);
if (ret < 0)
@@ -2095,6 +2115,7 @@ static const struct vc4_hdmi_variant
bcm2711_hdmi0_variant = {
PHY_LANE_CK,
},
.unsupported_odd_h_timings = true,
+ .external_irq_controller= true,
.init_resources = vc5_hdmi_init_resources,
.csc_setup = vc5_hdmi_csc_setup,
@@ -2121,6 +2142,7 @@ static const struct vc4_hdmi_variant
bcm2711_hdmi1_variant = {
PHY_LANE_2,
},
.unsupported_odd_h_timings = true,
+ .external_irq_controller= true,
.init_resources = vc5_hdmi_init_resources,
.csc_setup = vc5_hdmi_csc_setup,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 6966db1a0957..d71f6ed321bf 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -64,6 +64,13 @@ struct vc4_hdmi_variant {
/* The BCM2711 cannot deal with odd horizontal pixel timings */
bool unsupported_odd_h_timings;
+ /*
+* The
[PATCH v2 01/15] ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835
The BCM2711 has a number of instances of interrupt controllers handled by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). Let's select that driver as part of the ARCH_BCM2835 Kconfig option. Signed-off-by: Maxime Ripard --- arch/arm/mach-bcm/Kconfig| 1 + arch/arm64/Kconfig.platforms | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index ae790908fc74..c9b24ecb56c6 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -161,6 +161,7 @@ config ARCH_BCM2835 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER + select BRCMSTB_L2_IRQ select PINCTRL select PINCTRL_BCM2835 select MFD_CORE diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 5c4ac1c9f4e0..2c5620822895 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -39,6 +39,7 @@ config ARCH_BCM2835 select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select BRCMSTB_L2_IRQ help This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. -- 2.29.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 07/15] drm/vc4: hdmi: Update the CEC clock divider on HSM rate change
As part of the enable sequence we might change the HSM clock rate if the
pixel rate is different than the one we were already dealing with.
On the BCM2835 however, the CEC clock derives from the HSM clock so any
rate change will need to be reflected in the CEC clock divider to output
40kHz.
Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel
rate")
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 39 +-
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 50008513edfc..0627b8db32f6 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -132,6 +132,27 @@ static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
}
+#ifdef CONFIG_DRM_VC4_HDMI_CEC
+static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
+{
+ u16 clk_cnt;
+ u32 value;
+
+ value = HDMI_READ(HDMI_CEC_CNTRL_1);
+ value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
+
+ /*
+* Set the clock divider: the hsm_clock rate and this divider
+* setting will give a 40 kHz CEC clock.
+*/
+ clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
+ value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
+ HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
+}
+#else
+static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
+#endif
+
static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
@@ -770,6 +791,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct
drm_encoder *encoder,
return;
}
+ vc4_hdmi_cec_update_clk_div(vc4_hdmi);
+
/*
* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
* at 300MHz.
@@ -1598,7 +1621,6 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
{
struct cec_connector_info conn_info;
struct platform_device *pdev = vc4_hdmi->pdev;
- u16 clk_cnt;
u32 value;
int ret;
@@ -1617,17 +1639,14 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
cec_s_conn_info(vc4_hdmi->cec_adap, _info);
HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0x);
+
value = HDMI_READ(HDMI_CEC_CNTRL_1);
- value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
- /*
-* Set the logical address to Unregistered and set the clock
-* divider: the hsm_clock rate and this divider setting will
-* give a 40 kHz CEC clock.
-*/
- clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
- value |= VC4_HDMI_CEC_ADDR_MASK |
-(clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+ /* Set the logical address to Unregistered */
+ value |= VC4_HDMI_CEC_ADDR_MASK;
HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
+
+ vc4_hdmi_cec_update_clk_div(vc4_hdmi);
+
ret = devm_request_threaded_irq(>dev, platform_get_irq(pdev, 0),
vc4_cec_irq_handler,
vc4_cec_irq_handler_thread, 0,
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 05/15] drm/vc4: hdmi: Restore cec physical address on reconnect
Hi Dave,
Thanks for your review
On Fri, Dec 18, 2020 at 02:45:54PM +, Dave Stevenson wrote:
> On Fri, 18 Dec 2020 at 14:21, Dave Stevenson
> wrote:
> >
> > Hi Maxime & Dom
> >
> > On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> > >
> > > From: Dom Cobley
> > >
> > > Currently we call cec_phys_addr_invalidate on a hotplug deassert.
> > > That may be due to a TV power cycling, or an AVR being switched
> > > on (and switching edid).
> > >
> > > This makes CEC unusable since our controller wouldn't have a physical
> > > address anymore.
> > >
> > > Set it back up again on the hotplug assert.
> > >
> > > Fixes: 15b4511a4af6 ("drm/vc4: add HDMI CEC support")
> > > Signed-off-by: Dom Cobley
> > > Signed-off-by: Maxime Ripard
> > > ---
> > > drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +
> > > 1 file changed, 17 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c
> > > b/drivers/gpu/drm/vc4/vc4_hdmi.c
> > > index 28b78ea885ea..eff3bac562c6 100644
> > > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> > > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> > > @@ -136,20 +136,29 @@ static enum drm_connector_status
> > > vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
> > > {
> > > struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
> > > + bool connected = false;
> > >
> > > if (vc4_hdmi->hpd_gpio) {
> > > if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
> > > vc4_hdmi->hpd_active_low)
> > > - return connector_status_connected;
> > > - cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
> > > - return connector_status_disconnected;
> > > - }
> > > -
> > > - if (drm_probe_ddc(vc4_hdmi->ddc))
> > > - return connector_status_connected;
> > > -
> > > + connected = true;
> > > + } else if (drm_probe_ddc(vc4_hdmi->ddc))
> > > + connected = true;
> > > if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
> >
> > This needs to become an "else if(...".
> > It used to be that all the other paths would return, so were mutually
> > exclusive to this. Now they set a thing and keep going we need to
> > avoid reading the register should there be a HPD gpio or the ddc probe
> > succeeds.
> > Memory says that otherwise Pi3 always reports connected.
> >
> > I fixed this in a downstream patch already -
> > https://github.com/raspberrypi/linux/commit/d345caec1e9b2317b9cd7eb5b92ae453a0d3e98c
> >
> > Otherwise fine.
> >
> > Dave
> >
> > > + connected = true;
> > > + if (connected) {
> > > + if (connector->status != connector_status_connected) {
> > > + struct edid *edid = drm_get_edid(connector,
> > > vc4_hdmi->ddc);
> > > +
> > > + if (edid) {
> > > +
> > > cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
> > > + vc4_hdmi->encoder.hdmi_monitor =
> > > drm_detect_hdmi_monitor(edid);
> > > +
> > > drm_connector_update_edid_property(connector, edid);
>
> Actually looking at this again in the context of the other changes, do
> we need to call drm_connector_update_edid_property() here?
>
> We've just called drm_get_edid() to get the edid, and that calls
> drm_connector_update_edid_property() as well [1]
Yeah, you're right I'll drop it
> Updating vc4_hdmi->encoder.hdmi_monitor may be necessary. It's
> otherwise done in vc4_hdmi_connector_get_modes, which I sort of expect
> to be called almost immediately by the framework when connector_detect
> returns "connected". I haven't checked if that is guaranteed though.
>
> vc4_hdmi_connector_get_modes also includes a manual call to
> drm_connector_update_edid_property after having just called
> drm_get_edid, so that one feels redundant too.
.get_modes is called in drm_helper_probe_single_connector_modes, which
is usually the helper set in .fill_modes. .fill_modes seems to only be
called when either DRM_IOCTL_MODE_GETCONNECTOR is called, or when the
connector status is forced through sysfs, so it doesn't look like it's
done automatically.
I'm not sure we need to set hdmi_monitor though, it's only used to
configure the display related side, and that can't happen without
get_modes being called.
Maxime
signature.asc
Description: PGP signature
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 11/13] drm/vboxvideo: Use drm_gem_vram_vmap_local() in cursor update
Hi
Am 11.01.21 um 18:06 schrieb Daniel Vetter:
On Fri, Jan 08, 2021 at 10:43:38AM +0100, Thomas Zimmermann wrote:
Cursor updates in vboxvideo require a short-term mapping of the
source BO. Use drm_gem_vram_vmap_local() and avoid the pinning
operations.
Signed-off-by: Thomas Zimmermann
All these drivers patches break the dma_resv_lock vs
dma_fence_begin/end_signalling nesting rules, so this doesn't work.
Generally this is what the prepare/cleanup_fb hooks are for, that's where
mappings (including vmaps) are meant to be set up, permanently.
I'm kinda not clear on why we need all these changes, I thought the
locking problem is just in the fb helper paths, because it's outside of
the atomic path and could conflict with an atomic update at the same time?
So only that one should get the vmap_local treatment, everything else
should keep the normal vmap treatment.
Kind of responding to all your comment on the driver changes:
These drivers only require short-term mappings, so using vmap_local
would be the natural choice. For SHMEM helpers, it's mostly a cosmetic
thing. For VRAM helpers, I was hoping to remove the vmap/vunmap helpers
entirely. One cannot really map the BOs for the long-term, so not having
the helpers at all would make sense.
But reading all your comments on the driver patches, I'd rather not
update the drivers here but later convert them to use
prepare_fb/cleanup_fb in the correct way.
Best regards
Thomas
-Daniel
---
drivers/gpu/drm/vboxvideo/vbox_mode.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_mode.c
b/drivers/gpu/drm/vboxvideo/vbox_mode.c
index dbc0dd53c69e..215b37c78c10 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_mode.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c
@@ -381,7 +381,8 @@ static void vbox_cursor_atomic_update(struct drm_plane
*plane,
container_of(plane->dev, struct vbox_private, ddev);
struct vbox_crtc *vbox_crtc = to_vbox_crtc(plane->state->crtc);
struct drm_framebuffer *fb = plane->state->fb;
- struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(fb->obj[0]);
+ struct drm_gem_object *obj = fb->obj[0];
+ struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(obj);
u32 width = plane->state->crtc_w;
u32 height = plane->state->crtc_h;
size_t data_size, mask_size;
@@ -401,11 +402,12 @@ static void vbox_cursor_atomic_update(struct drm_plane
*plane,
vbox_crtc->cursor_enabled = true;
- ret = drm_gem_vram_vmap(gbo, );
+ ret = dma_resv_lock(obj->resv, NULL);
+ if (ret)
+ return;
+ ret = drm_gem_vram_vmap_local(gbo, );
if (ret) {
- /*
-* BUG: we should have pinned the BO in prepare_fb().
-*/
+ dma_resv_unlock(obj->resv);
mutex_unlock(>hw_mutex);
DRM_WARN("Could not map cursor bo, skipping update\n");
return;
@@ -421,7 +423,8 @@ static void vbox_cursor_atomic_update(struct drm_plane
*plane,
data_size = width * height * 4 + mask_size;
copy_cursor_image(src, vbox->cursor_data, width, height, mask_size);
- drm_gem_vram_vunmap(gbo, );
+ drm_gem_vram_vunmap_local(gbo, );
+ dma_resv_unlock(obj->resv);
flags = VBOX_MOUSE_POINTER_VISIBLE | VBOX_MOUSE_POINTER_SHAPE |
VBOX_MOUSE_POINTER_ALPHA;
--
2.29.2
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
OpenPGP_signature
Description: OpenPGP digital signature
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] drm/radeon: stop re-init the TTM page pool
Am 11.01.21 um 17:17 schrieb Daniel Vetter:
On Mon, Jan 11, 2021 at 11:16:13AM +0100, Christian König wrote:
Am 08.01.21 um 16:53 schrieb Daniel Vetter:
On Fri, Jan 8, 2021 at 3:36 PM Christian König wrote:
Am 08.01.21 um 15:31 schrieb Daniel Vetter:
On Thu, Jan 07, 2021 at 09:08:29PM +0100, Christian König wrote:
Am 07.01.21 um 19:07 schrieb Daniel Vetter:
On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
Drivers are not supposed to init the page pool directly any more.
Signed-off-by: Christian König
Please include reported-by credits and link to the bug reports on
lore.kernel.org when merging this. Also I guess this should have a Fixes:
line?
I'm not aware of a bug report, but the reported-by/Fixes lines are indeed
missing.
This one here:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2F20201231104020.GA4504%40zn.tnic%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7Cff77249040634cf2750308d8b64c616d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459786459556204%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=m8tjDXFtsEwtcv9byq5r1sbUuqb8q%2BAn63r4aKMpcaM%3Dreserved=0
Or did I get confused, and the above is yet another bug?
Yeah, but that was just reported by mail. The bug tracker I've saw was
opened after the patch was already pushed.
Still good to give reported-by credits for mailing list reports and
link to lore.kernel.org for the report, that's not just useful for
bugzilla reports.
That's indeed true, but I was distracted by the fact that drm-misc-fixes
wasn't up to date :)
Going to add that earlier next time.
BTW: Any idea why dim add-link doesn't work?
Hm we occasionally have fun with email parsing (it's hard) and especially
python changes in how encodings are handled differently between python2
and python3. If you have a specific example I can try and take a look why
it doesn't work.
It just looks up and doesn't seem to do anything. I'm not familiar with
python so I can just describe the symptoms.
I meant tell me which mail (patchwork or lore) and I'll try to
reproduce and see what's maybe up.
It doesn't seem to work in general. E.g. any patch I try I just don't get
any progress in over 10 Minutes.
Maybe some server is not responding?
Uh dim add-link pretty similar to dim apply-patch, it takes the mbox on
stdin and does only local git stuff with it.
AH! Since it was getting a branch parameter I was assuming that it looks
at patches on that branch!
Thanks for the explanation,
Christian.
-Daniel
Christian.
-Daniel
Christian.
-Daniel
And maybe some words on how/why stuff blows up.
Just a typo. I've forgot to remove two lines in radeon while rebasing and
still had the symbols exported so never noticed this.
Christian.
-Daniel
---
drivers/gpu/drm/radeon/radeon_ttm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index d4328ff57757..35b715f82ed8 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -729,9 +729,6 @@ int radeon_ttm_init(struct radeon_device *rdev)
}
rdev->mman.initialized = true;
- ttm_pool_init(>mman.bdev.pool, rdev->dev, rdev->need_swiotlb,
-dma_addressing_limited(>pdev->dev));
-
r = radeon_ttm_init_vram(rdev);
if (r) {
DRM_ERROR("Failed initializing VRAM heap.\n");
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-develdata=04%7C01%7Cchristian.koenig%40amd.com%7Cff77249040634cf2750308d8b64c616d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459786459556204%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=nBl4CRoSoA3t%2Bd4sZ4My4L27GiCiJwRenoILGU9LbO4%3Dreserved=0
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 01/13] dma-buf: Add vmap_local and vnumap_local operations
Hi
Am 08.01.21 um 17:12 schrieb Ruhl, Michael J:
-Original Message-
From: dri-devel On Behalf Of
Thomas Zimmermann
Sent: Friday, January 8, 2021 4:43 AM
To: sumit.sem...@linaro.org; christian.koe...@amd.com;
airl...@redhat.com; dan...@ffwll.ch; maarten.lankho...@linux.intel.com;
mrip...@kernel.org; kra...@redhat.com; hdego...@redhat.com;
s...@poorly.run; e...@anholt.net; s...@ravnborg.org
Cc: Daniel Vetter ; dri-devel@lists.freedesktop.org;
virtualizat...@lists.linux-foundation.org; linaro-mm-...@lists.linaro.org;
Thomas Zimmermann ; linux-
me...@vger.kernel.org
Subject: [PATCH v4 01/13] dma-buf: Add vmap_local and vnumap_local
operations
The existing dma-buf calls dma_buf_vmap() and dma_buf_vunmap() are
allowed to pin the buffer or acquire the buffer's reservation object
lock.
This is a problem for callers that only require a short-term mapping
of the buffer without the pinning, or callers that have special locking
requirements. These may suffer from unnecessary overhead or interfere
with regular pin operations.
The new interfaces dma_buf_vmap_local(), dma_buf_vunmapo_local(), and
their rsp callbacks in struct dma_buf_ops provide an alternative without
pinning or reservation locking. Callers are responsible for these
operations.
v4:
* update documentation (Daniel)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
Suggested-by: Daniel Vetter
---
drivers/dma-buf/dma-buf.c | 81
+++
include/linux/dma-buf.h | 34
2 files changed, 115 insertions(+)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index b8465243eca2..01f9c74d97fa 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -1295,6 +1295,87 @@ void dma_buf_vunmap(struct dma_buf *dmabuf,
struct dma_buf_map *map)
}
EXPORT_SYMBOL_GPL(dma_buf_vunmap);
+/**
+ * dma_buf_vmap_local - Create virtual mapping for the buffer object into
kernel
+ * address space.
+ * @dmabuf:[in]buffer to vmap
+ * @map: [out] returns the vmap pointer
+ *
+ * Unlike dma_buf_vmap() this is a short term mapping and will not pin
+ * the buffer. The struct dma_resv for the @dmabuf must be locked until
+ * dma_buf_vunmap_local() is called.
+ *
+ * Returns:
+ * 0 on success, or a negative errno code otherwise.
+ */
+int dma_buf_vmap_local(struct dma_buf *dmabuf, struct dma_buf_map
*map)
+{
+ struct dma_buf_map ptr;
+ int ret = 0;
+
+ dma_buf_map_clear(map);
+
+ if (WARN_ON(!dmabuf))
+ return -EINVAL;
+
+ dma_resv_assert_held(dmabuf->resv);
+
+ if (!dmabuf->ops->vmap_local)
+ return -EINVAL;
You are clearing the map, and then doing the above checks.
Is it ok to change the map info and then exit on error?
In vmap_local map argument returns the mapping's address. Callers are
expected to check the return code. But I would expect a careless caller
to not check, or check for map being cleared. Clearing it here first is
the save thing to do.
Best regards
Thomas
Mike
+ mutex_lock(>lock);
+ if (dmabuf->vmapping_counter) {
+ dmabuf->vmapping_counter++;
+ BUG_ON(dma_buf_map_is_null(>vmap_ptr));
+ *map = dmabuf->vmap_ptr;
+ goto out_unlock;
+ }
+
+ BUG_ON(dma_buf_map_is_set(>vmap_ptr));
+
+ ret = dmabuf->ops->vmap_local(dmabuf, );
+ if (WARN_ON_ONCE(ret))
+ goto out_unlock;
+
+ dmabuf->vmap_ptr = ptr;
+ dmabuf->vmapping_counter = 1;
+
+ *map = dmabuf->vmap_ptr;
+
+out_unlock:
+ mutex_unlock(>lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(dma_buf_vmap_local);
+
+/**
+ * dma_buf_vunmap_local - Unmap a vmap obtained by
dma_buf_vmap_local.
+ * @dmabuf:[in]buffer to vunmap
+ * @map: [in]vmap pointer to vunmap
+ *
+ * Release a mapping established with dma_buf_vmap_local().
+ */
+void dma_buf_vunmap_local(struct dma_buf *dmabuf, struct
dma_buf_map *map)
+{
+ if (WARN_ON(!dmabuf))
+ return;
+
+ dma_resv_assert_held(dmabuf->resv);
+
+ BUG_ON(dma_buf_map_is_null(>vmap_ptr));
+ BUG_ON(dmabuf->vmapping_counter == 0);
+ BUG_ON(!dma_buf_map_is_equal(>vmap_ptr, map));
+
+ mutex_lock(>lock);
+ if (--dmabuf->vmapping_counter == 0) {
+ if (dmabuf->ops->vunmap_local)
+ dmabuf->ops->vunmap_local(dmabuf, map);
+ dma_buf_map_clear(>vmap_ptr);
+ }
+ mutex_unlock(>lock);
+}
+EXPORT_SYMBOL_GPL(dma_buf_vunmap_local);
+
#ifdef CONFIG_DEBUG_FS
static int dma_buf_debug_show(struct seq_file *s, void *unused)
{
diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
index 628681bf6c99..aeed754b5467 100644
--- a/include/linux/dma-buf.h
+++ b/include/linux/dma-buf.h
@@ -264,6 +264,38 @@ struct dma_buf_ops {
int (*vmap)(struct dma_buf *dmabuf, struct dma_buf_map *map);
void (*vunmap)(struct dma_buf *dmabuf, struct
RE: [PATCH 2/2] drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT interrupt work
[AMD Official Use Only - Internal Distribution Only]
Any comment?
-Original Message-
From: Xiaogang.Chen
Sent: Monday, January 4, 2021 12:02 AM
To: amd-...@lists.freedesktop.org; Wentland, Harry ;
dri-devel@lists.freedesktop.org; airl...@linux.ie
Cc: Chen, Xiaogang
Subject: [PATCH 2/2] drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT
interrupt work
From: Xiaogang Chen
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT interrupt(hpd, hpd_rx) by using
work queue and uses single work_struct. If previous interrupt has not been
handled new interrupts(same type) will be discarded and driver just sends
"amdgpu_dm_irq_schedule_work FAILED" message out.
If some important hpd, hpd_rx related interrupts are missed by driver the hot
(un)plug devices may cause system hang or unstable, such as system resumes from
S3 sleep with mst device connected.
This patch dynamically allocates new amdgpu_dm_irq_handler_data for new
interrupts if previous INTERRUPT_LOW_IRQ_CONTEXT interrupt work has not been
handled. So the new interrupt works can be queued to the same workqueue_struct,
instead discard the new interrupts.
All allocated amdgpu_dm_irq_handler_data are put into a single linked list and
will be reused after.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 14 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 114 ++---
2 files changed, 80 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index c9d82b9..730e540 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -69,18 +69,6 @@ struct common_irq_params { };
/**
- * struct irq_list_head - Linked-list for low context IRQ handlers.
- *
- * @head: The list_head within handler_data
- * @work: A work_struct containing the deferred handler work
- */
-struct irq_list_head {
- struct list_head head;
- /* In case this interrupt needs post-processing, 'work' will be queued*/
- struct work_struct work;
-};
-
-/**
* struct dm_compressor_info - Buffer info used by frame buffer compression
* @cpu_addr: MMIO cpu addr
* @bo_ptr: Pointer to the buffer object @@ -270,7 +258,7 @@ struct
amdgpu_display_manager {
* Note that handlers are called in the same order as they were
* registered (FIFO).
*/
- struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
+ struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
/**
* @irq_handler_list_high_tab:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 3577785..ada344a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -82,6 +82,7 @@ struct amdgpu_dm_irq_handler_data {
struct amdgpu_display_manager *dm;
/* DAL irq source which registered for this interrupt. */
enum dc_irq_source irq_source;
+ struct work_struct work;
};
#define DM_IRQ_TABLE_LOCK(adev, flags) \ @@ -111,20 +112,10 @@ static void
init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
*/
static void dm_irq_work_func(struct work_struct *work) {
- struct irq_list_head *irq_list_head =
- container_of(work, struct irq_list_head, work);
- struct list_head *handler_list = _list_head->head;
- struct amdgpu_dm_irq_handler_data *handler_data;
-
- list_for_each_entry(handler_data, handler_list, list) {
- DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
- handler_data->irq_source);
+ struct amdgpu_dm_irq_handler_data *handler_data =
+container_of(work, struct amdgpu_dm_irq_handler_data, work);
- DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
- handler_data->irq_source);
-
- handler_data->handler(handler_data->handler_arg);
- }
+ handler_data->handler(handler_data->handler_arg);
/* Call a DAL subcomponent which registered for interrupt notification
* at INTERRUPT_LOW_IRQ_CONTEXT.
@@ -156,7 +147,7 @@ static struct list_head *remove_irq_handler(struct
amdgpu_device *adev,
break;
case INTERRUPT_LOW_IRQ_CONTEXT:
default:
- hnd_list = >dm.irq_handler_list_low_tab[irq_source].head;
+ hnd_list = >dm.irq_handler_list_low_tab[irq_source];
break;
}
@@ -287,7 +278,8 @@ void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device
*adev,
break;
case INTERRUPT_LOW_IRQ_CONTEXT:
default:
- hnd_list = >dm.irq_handler_list_low_tab[irq_source].head;
+ hnd_list = >dm.irq_handler_list_low_tab[irq_source];
+
RE: [PATCH 1/2] drm: distinguish return value of drm_dp_check_and_send_link_address.
[AMD Official Use Only - Internal Distribution Only] Any comment? -Original Message- From: Xiaogang.Chen Sent: Monday, January 4, 2021 12:02 AM To: amd-...@lists.freedesktop.org; Wentland, Harry ; dri-devel@lists.freedesktop.org; airl...@linux.ie Cc: Chen, Xiaogang Subject: [PATCH 1/2] drm: distinguish return value of drm_dp_check_and_send_link_address. From: Xiaogang Chen drm_dp_check_and_send_link_address discovers MST device topology. It can return both positive and negative values. When it returns positive values there is no error found. If it returns negative values there is error found, such as get NAK , timeout, etc. Following drm_kms_helper_hotplug_event should be called when drm_dp_check_and_send_link_address returns positive value. Signed-off-by: Xiaogang Chen --- drivers/gpu/drm/drm_dp_mst_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 17dbed0..3ef5206 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -2650,7 +2650,7 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) drm_dp_mst_topology_put_mstb(mstb); mutex_unlock(>probe_lock); - if (ret) + if (ret > 0) drm_kms_helper_hotplug_event(dev); } -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v9 14/19] drm/i915/hdcp: MST streams support in hdcp port_data
On Mon, 2021-01-11 at 13:41 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> Security f/w doesn't have any provision to mark the stream_type
> for each stream separately, it just take single input of
> stream_type while authenticating the port and applies the
> same stream_type to all streams. So driver mark each stream_type
> with common highest supported content type for all streams
> in DP MST Topology.
>
> Security f/w supports RepeaterAuthStreamManage msg and m'
> validation only once during port authentication and encryption.
> Though it is not compulsory, security fw should support dynamic
> update of content_type and should support RepeaterAuthStreamManage
> msg and m' validation whenever required.
>
> v2:
> - Init the hdcp port data k for HDMI/DP SST stream.
> v3:
> - Cosmetic changes. [Uma]
> v4:
> - 's/port_auth/hdcp_port_auth'. [Ram]
> - Commit log improvement.
> v5:
> - Comment and commit log improvement. [Ram]
> v6:
> - Check first connector connected status before intel_encoder_is_mst
> to avoid any NULL pointer dereference.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Reviewed-by: Ramalingam C
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 113 +++-
> --
> 2 files changed, 102 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b74c10c8b01c..b37a02a73de6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1502,10 +1502,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, hdcp_port_data
> */
> + /* protects num_hdcp_streams reference count, hdcp_port_data
> and hdcp_auth_status */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port
> */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool hdcp_auth_status;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data hdcp_port_data;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2bec26123a05..bd87694def74 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,74 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector)
> +{
> + /* For HDMI this is forced to be 0x0. For DP SST also this is
> 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +/*
> + * intel_hdcp_required_content_stream selects the most highest
> common possible HDCP
> + * content_type for all streams in DP MST topology because security
> f/w doesn't
> + * have any provision to mark content_type for each stream
> separately, it marks
> + * all available streams with the content_type proivided at the time
> of port
> + * authentication. This may prohibit the userspace to use type1
> content on
> + * HDCP 2.2 capable sink because of other sink are not capable of
> HDCP 2.2 in
> + * DP MST topology. Though it is not compulsory, security fw should
> change its
> + * policy to mark different content_types for different streams.
> + */
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port-
> >base.base.dev);
> + struct hdcp_port_data *data = _port->hdcp_port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->hdcp_auth_status)
> + return 0;
> +
> + drm_connector_list_iter_begin(>drm, _iter);
> + for_each_intel_connector_iter(connector, _iter) {
> + if (connector->base.status ==
> connector_status_disconnected)
> + continue;
> +
> + if
> (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (!enforce_type0 &&
> !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id =
> intel_conn_to_vcpi(connector);
> + data->k++;
> +
> +
Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
Hi Rob,
On Mon, Jan 11, 2021 at 05:12:58PM -0600, Rob Herring wrote:
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74
> > .../display/rockchip/rockchip,dw-hdmi.yaml| 158 ++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644
> > Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644
> > Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..
> > ---
> > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have
> > two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C
> > master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff98 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff98 0x2>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <>;
> > - rockchip,grf = <>;
> > - interrupts = ;
> > - clocks = < PCLK_HDMI_CTRL>, < SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > new file mode 100644
> > index ..d3b2f87f152a
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier:
Re: [PATCH] drm/bridge: nwl-dsi: Avoid potential multiplication overflow on 32-bit
Hi Geert, Thank you for the patch. On Mon, Jan 11, 2021 at 01:57:02PM +0100, Geert Uytterhoeven wrote: > As nwl_dsi.lanes is u32, and NSEC_PER_SEC is 10L, the second > multiplication in > > dsi->lanes * 8 * NSEC_PER_SEC > > will overflow on a 32-bit platform. Fix this by making the constant > unsigned long long, forcing 64-bit arithmetic. > > While iMX8 is arm64, this driver is currently used on 64-bit platforms > only, where long is 64-bit, so this cannot happen. But the issue may > start to happen when the driver is reused for a 32-bit SoC, or when code > is copied for a new driver. > > Signed-off-by: Geert Uytterhoeven > --- > Compile-tested only. > --- > drivers/gpu/drm/bridge/nwl-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c > b/drivers/gpu/drm/bridge/nwl-dsi.c > index 66b67402f1acd57d..a8da3081efdcc84e 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -195,7 +195,7 @@ static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long > ps) > u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); > > return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, > - dsi->lanes * 8 * NSEC_PER_SEC); > + dsi->lanes * 8ULL * NSEC_PER_SEC); I wonder if we could get rid of a whole class of bugs by turning NSEC_PER_SEC into a ULL, but I suppose there are valid cases where a 32-bit integer is enough. Reviewed-by: Laurent Pinchart How did you come across this by the way ? > } > > /* -- Regards, Laurent Pinchart ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 08/15] drm/mediatek: check if fb is null
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:48寫道：
>
> It's possible that state->base.fb is null. Add a check before access its
> format.
Applied to mediatek-drm-next [1], thanks.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has
> no alpha)
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 4934bee..8e7f494 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp
> *comp, unsigned int idx,
> }
>
> con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb->format->has_alpha)
> + if (state->base.fb && state->base.fb->format->has_alpha)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> --
> 1.8.1.1.dirty
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:44寫道：
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Could you describe more information? Without this patch, what would happen?
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index b47c238..4934bee 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -23,6 +23,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> #define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_LAYER_SMI_ID_ENBIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> unsigned int gmc_bits;
> unsigned int layer_nr;
> bool fmt_rgb565_is_0;
> + bool smi_id_en;
> };
>
> /**
> @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp
> *comp)
>
> static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> {
> + struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> +
> writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> +
> + if(ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
I think this setting should before write 1 to DISP_REG_OVL_EN.
> + }
> }
>
> static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
Should clear DISP_REG_OVL_DATAPATH_CON when stop?
Regards,
Chun-Kuang.
> --
> 1.8.1.1.dirty
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 06/15] drm/mediatek: add component RDMA4
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component RDMA4
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index bc6b10a..fc01fea 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -392,6 +392,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
> [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
> [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
> + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL },
> [DDP_COMPONENT_UFOE]= { MTK_DISP_UFOE, 0, _ufoe },
> [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> --
> 1.8.1.1.dirty
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 05/15] drm/mediatek: add component POSTMASK
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component POSTMASK,
This patch has conflicts with the series "Decouple Mediatek DRM sub
driver" [1] which has been applied to mediatek-drm-next, so please
rebase this patch onto mediatek-drm-next.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=399915
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160
> +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 168 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 17a08e2..ce5ad59 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 000..736224c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,160 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_ENBIT(0)
> +#define DISP_POSTMASK_CFG 0x0020
> +#define POSTMASK_RELAY_MODEBIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct mtk_ddp_comp ddp_comp;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
> +static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp
> *comp)
> +{
> + return container_of(comp, struct mtk_disp_postmask, ddp_comp);
> +}
> +
> +static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
> +}
> +
> +static void mtk_postmask_start(struct mtk_ddp_comp *comp)
> +{
> + writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + int ret;
> +
> + ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
> + if (ret < 0) {
> + dev_err(dev, "Failed to register component %pOF: %d\n",
> + dev->of_node, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_disp_postmask_unbind(struct device *dev, struct device
> *master,
> + void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> +
> + mtk_ddp_comp_unregister(drm_dev, >ddp_comp);
> +}
> +
> +static const struct component_ops mtk_disp_postmask_component_ops = {
> + .bind = mtk_disp_postmask_bind,
> + .unbind = mtk_disp_postmask_unbind,
> +};
> +
> +static int mtk_disp_postmask_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + struct mtk_disp_postmask *priv;
> + int comp_id;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return
Re: [PATCH v3, 04/15] drm/mediatek: add component OVL_2L2
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component OVL_2L2
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 81ed076..a715127 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, NULL },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, NULL },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, NULL },
> [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM, 2, NULL },
> --
> 1.8.1.1.dirty
> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 03/15] arm64: dts: mt8192: add display node
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月11日 週一 下午3:48寫道：
>
> add display node
>
> Signed-off-by: Yongqiang Niu
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134
> +++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024..dcf9fdf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -15,6 +15,11 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl2-2l2 = _2l2;
> + rdma4 =
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -508,5 +513,134 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + mmsys: syscon@1400 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x1400 0 0x1000>;
> + //mboxes = < 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + // < 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + //mediatek,gce-client-reg = < SUBSYS_1400 0
> 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> +mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = ;
> + //clocks = < CLK_MM_DISP_MUTEX0>;
> + //mediatek,gce-events =
> ,
> + //
> ;
> + };
> +
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = ;
> + //clocks = < CLK_MM_DISP_OVL0>;
> + //iommus = < M4U_PORT_L0_OVL_RDMA0>;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
I think you should not mark these property.
Regards,
Chun-Kuang.
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0x5000 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = ;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> + //clocks = < CLK_MM_DISP_OVL0_2L>;
> + //iommus = < M4U_PORT_L1_OVL_2L_RDMA0>;
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0x6000 0x1000>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = ;
> + //clocks = < CLK_MM_DISP_RDMA0>;
> + //iommus = < M4U_PORT_L0_DISP_RDMA0>;
> + //mediatek,larb = <>;
> + //mediatek,rdma-fifo-size = <5120>;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0x7000 0x1000>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> +"mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = ;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> + //clocks = < CLK_MM_DISP_COLOR0>;
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0x9000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = ;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> + //clocks = < CLK_MM_DISP_CCORR0>;
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0xa000 0x1000>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = ;
> + //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> + //clocks = < CLK_MM_DISP_AAL0>;
> + //mediatek,gce-client-reg = < SUBSYS_1400
> 0xb000 0x1000>;
> + };
> +
> + gamma0: gamma@1400c000 {
Re: [PATCH v3, 02/15] dt-bindings: mediatek: add description for mt8192 display
Hi, Yongqiang: Yongqiang Niu 於 2021年1月11日 週一 下午3:48寫道： > > add description for mt8192 display Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu > Reviewed-by: Chun-Kuang Hu > Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index 9d9ab65..b47e1a0 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -44,7 +44,7 @@ Required properties (all function blocks): > "mediatek,-dpi" - DPI controller, see > mediatek,dpi.txt > "mediatek,-disp-mutex"- display mutex > "mediatek,-disp-od" - overdrive > - the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183. > + the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and > mt8192. > - reg: Physical base address and length of the function block register space > - interrupts: The interrupt signal from the function block (required, except > for >merge and split function blocks). > -- > 1.8.1.1.dirty > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3, 01/15] dt-bindings: mediatek: add description for postmask
Yongqiang Niu 於 2021年1月11日 週一 下午3:44寫道： > > add description for postmask > postmask is used control round corner for display frame After changing to 'used to control', Reviewed-by: Chun-Kuang Hu > > Signed-off-by: Yongqiang Niu > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index c562cda..9d9ab65 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -37,6 +37,7 @@ Required properties (all function blocks): > "mediatek,-disp-aal" - adaptive ambient light > controller > "mediatek,-disp-gamma"- gamma correction > "mediatek,-disp-merge"- merge streams from two RDMA > sources > + "mediatek,-disp-postmask" - control round corner for > display frame > "mediatek,-disp-split"- split stream to two encoders > "mediatek,-disp-ufoe" - data compression engine > "mediatek,-dsi" - DSI controller, see > mediatek,dsi.txt > -- > 1.8.1.1.dirty > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> Convert the Rockchip HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart
> ---
> Changes since v2:
>
> - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> bounces
>
> Changes since v1:
>
> - Drop pinctrl-0 and pinctrl-1
> - Use unevaluatedProperties instead of additionalProperties
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Tidy up clock names
> ---
> .../display/rockchip/dw_hdmi-rockchip.txt | 74
> .../display/rockchip/rockchip,dw-hdmi.yaml| 158 ++
> 2 files changed, 158 insertions(+), 74 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> create mode 100644
> Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> deleted file mode 100644
> index 3d32ce137e7f..
> --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -Rockchip DWC HDMI TX Encoder
> -
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible: should be one of the following:
> - "rockchip,rk3228-dw-hdmi"
> - "rockchip,rk3288-dw-hdmi"
> - "rockchip,rk3328-dw-hdmi"
> - "rockchip,rk3399-dw-hdmi"
> -- reg: See dw_hdmi.txt.
> -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> - corresponding to the video input of the controller. The port shall have two
> - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> -
> -Optional properties
> -
> -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C
> master
> - or the functionally-reduced I2C master contained in the DWC HDMI. When
> - connected to a system I2C master this property contains a phandle to that
> - I2C master controller.
> -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> -- clock-names: May contain "grf", power for grf io.
> -- clock-names: May contain "vpll", external clock for some hdmi phy.
> -- phys: from general PHY binding: the phandle for the PHY device.
> -- phy-names: Should be "hdmi" if phys references an external phy.
> -
> -Optional pinctrl entry:
> -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> - i2c timeout. It's intended that this unwedge pinctrl entry will
> - cause the SDA line to be driven low to work around a hardware
> - errata.
> -
> -Example:
> -
> -hdmi: hdmi@ff98 {
> - compatible = "rockchip,rk3288-dw-hdmi";
> - reg = <0xff98 0x2>;
> - reg-io-width = <4>;
> - ddc-i2c-bus = <>;
> - rockchip,grf = <>;
> - interrupts = ;
> - clocks = < PCLK_HDMI_CTRL>, < SCLK_HDMI_HDCP>;
> - clock-names = "iahb", "isfr";
> - ports {
> - hdmi_in: port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - hdmi_in_vopb: endpoint@0 {
> - reg = <0>;
> - remote-endpoint = <_out_hdmi>;
> - };
> - hdmi_in_vopl: endpoint@1 {
> - reg = <1>;
> - remote-endpoint = <_out_hdmi>;
> - };
> - };
> - };
> -};
> diff --git
> a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> new file mode 100644
> index ..d3b2f87f152a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DWC HDMI TX Encoder
> +
> +maintainers:
> + - Mark Yao
> +
>
Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
Hi Rob,
On Mon, Jan 11, 2021 at 05:01:36PM -0600, Rob Herring wrote:
> On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> > Hi Rob,
> >
> > Given that the maintainers property is mandatory in the schema, what's
> > the procedure when no maintainer steps up for a converter YAML binding ?
>
> Delete it if no one cares...
>
> Typically we just put a subsystem or platform maintainer.
Do you mean dropping dw_hdmi-rockchip.txt completely, even if it's in
use by a driver ?
> > On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > > Convert the Rockchip HDMI TX text binding to YAML.
> > >
> > > Signed-off-by: Laurent Pinchart
> > >
> > > ---
> > > Changes since v2:
> > >
> > > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > > bounces
> > >
> > > Changes since v1:
> > >
> > > - Drop pinctrl-0 and pinctrl-1
> > > - Use unevaluatedProperties instead of additionalProperties
> > > - Drop reg and interrupts as they're checked in the base schema
> > > - Rebase on top of OF graph schema, dropped redundant properties
> > > - Fix identation for enum entries
> > > - Tidy up clock names
> > > ---
> > > .../display/rockchip/dw_hdmi-rockchip.txt | 74
> > > .../display/rockchip/rockchip,dw-hdmi.yaml| 158 ++
> > > 2 files changed, 158 insertions(+), 74 deletions(-)
> > > delete mode 100644
> > > Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > create mode 100644
> > > Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > deleted file mode 100644
> > > index 3d32ce137e7f..
> > > ---
> > > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > > +++ /dev/null
> > > @@ -1,74 +0,0 @@
> > > -Rockchip DWC HDMI TX Encoder
> > > -
> > > -
> > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > -with a companion PHY IP.
> > > -
> > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > > -following device-specific properties.
> > > -
> > > -
> > > -Required properties:
> > > -
> > > -- compatible: should be one of the following:
> > > - "rockchip,rk3228-dw-hdmi"
> > > - "rockchip,rk3288-dw-hdmi"
> > > - "rockchip,rk3328-dw-hdmi"
> > > - "rockchip,rk3399-dw-hdmi"
> > > -- reg: See dw_hdmi.txt.
> > > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > > -- interrupts: HDMI interrupt number
> > > -- clocks: See dw_hdmi.txt.
> > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered > > > 0
> > > - corresponding to the video input of the controller. The port shall
> > > have two
> > > - endpoints, numbered 0 and 1, connected respectively to the vopb and
> > > vopl.
> > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > > -
> > > -Optional properties
> > > -
> > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C
> > > master
> > > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > > - connected to a system I2C master this property contains a phandle to
> > > that
> > > - I2C master controller.
> > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > > -- clock-names: May contain "grf", power for grf io.
> > > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > > -- phys: from general PHY binding: the phandle for the PHY device.
> > > -- phy-names: Should be "hdmi" if phys references an external phy.
> > > -
> > > -Optional pinctrl entry:
> > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > > - cause the SDA line to be driven low to work around a hardware
> > > - errata.
> > > -
> > > -Example:
> > > -
> > > -hdmi: hdmi@ff98 {
> > > - compatible = "rockchip,rk3288-dw-hdmi";
> > > - reg = <0xff98 0x2>;
> > > - reg-io-width = <4>;
> > > - ddc-i2c-bus = <>;
> > > - rockchip,grf = <>;
> > > - interrupts = ;
> > > - clocks = < PCLK_HDMI_CTRL>, < SCLK_HDMI_HDCP>;
> > > - clock-names = "iahb", "isfr";
> > > - ports {
> > > - hdmi_in: port {
> > > - #address-cells = <1>;
> > > - #size-cells = <0>;
> > > - hdmi_in_vopb: endpoint@0 {
> > > - reg = <0>;
> > > - remote-endpoint = <_out_hdmi>;
> > > - };
> > >
Re: [PATCH v3 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML
On Wed, Jan 06, 2021 at 05:17:55PM +0200, Laurent Pinchart wrote:
> Hi Rob,
>
> Given that the maintainers property is mandatory in the schema, what's
> the procedure when no maintainer steps up for a converter YAML binding ?
Delete it if no one cares...
Typically we just put a subsystem or platform maintainer.
>
> On Tue, Jan 05, 2021 at 08:08:16AM +0200, Laurent Pinchart wrote:
> > Convert the Rockchip HDMI TX text binding to YAML.
> >
> > Signed-off-by: Laurent Pinchart
> > ---
> > Changes since v2:
> >
> > - Use Mark's @gmail.com e-mail address as the @rock-chips.com address
> > bounces
> >
> > Changes since v1:
> >
> > - Drop pinctrl-0 and pinctrl-1
> > - Use unevaluatedProperties instead of additionalProperties
> > - Drop reg and interrupts as they're checked in the base schema
> > - Rebase on top of OF graph schema, dropped redundant properties
> > - Fix identation for enum entries
> > - Tidy up clock names
> > ---
> > .../display/rockchip/dw_hdmi-rockchip.txt | 74
> > .../display/rockchip/rockchip,dw-hdmi.yaml| 158 ++
> > 2 files changed, 158 insertions(+), 74 deletions(-)
> > delete mode 100644
> > Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > create mode 100644
> > Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > deleted file mode 100644
> > index 3d32ce137e7f..
> > ---
> > a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
> > +++ /dev/null
> > @@ -1,74 +0,0 @@
> > -Rockchip DWC HDMI TX Encoder
> > -
> > -
> > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > -with a companion PHY IP.
> > -
> > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > -following device-specific properties.
> > -
> > -
> > -Required properties:
> > -
> > -- compatible: should be one of the following:
> > - "rockchip,rk3228-dw-hdmi"
> > - "rockchip,rk3288-dw-hdmi"
> > - "rockchip,rk3328-dw-hdmi"
> > - "rockchip,rk3399-dw-hdmi"
> > -- reg: See dw_hdmi.txt.
> > -- reg-io-width: See dw_hdmi.txt. Shall be 4.
> > -- interrupts: HDMI interrupt number
> > -- clocks: See dw_hdmi.txt.
> > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
> > - corresponding to the video input of the controller. The port shall have
> > two
> > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
> > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
> > -
> > -Optional properties
> > -
> > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C
> > master
> > - or the functionally-reduced I2C master contained in the DWC HDMI. When
> > - connected to a system I2C master this property contains a phandle to that
> > - I2C master controller.
> > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
> > -- clock-names: May contain "cec" as defined in dw_hdmi.txt.
> > -- clock-names: May contain "grf", power for grf io.
> > -- clock-names: May contain "vpll", external clock for some hdmi phy.
> > -- phys: from general PHY binding: the phandle for the PHY device.
> > -- phy-names: Should be "hdmi" if phys references an external phy.
> > -
> > -Optional pinctrl entry:
> > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
> > - will switch to the unwedge pinctrl state for 10ms if it ever gets an
> > - i2c timeout. It's intended that this unwedge pinctrl entry will
> > - cause the SDA line to be driven low to work around a hardware
> > - errata.
> > -
> > -Example:
> > -
> > -hdmi: hdmi@ff98 {
> > - compatible = "rockchip,rk3288-dw-hdmi";
> > - reg = <0xff98 0x2>;
> > - reg-io-width = <4>;
> > - ddc-i2c-bus = <>;
> > - rockchip,grf = <>;
> > - interrupts = ;
> > - clocks = < PCLK_HDMI_CTRL>, < SCLK_HDMI_HDCP>;
> > - clock-names = "iahb", "isfr";
> > - ports {
> > - hdmi_in: port {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - hdmi_in_vopb: endpoint@0 {
> > - reg = <0>;
> > - remote-endpoint = <_out_hdmi>;
> > - };
> > - hdmi_in_vopl: endpoint@1 {
> > - reg = <1>;
> > - remote-endpoint = <_out_hdmi>;
> > - };
> > - };
> > - };
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> >
Re: [PATCH v3 3/6] dt-bindings: display: imx: hdmi: Convert binding to YAML
On Tue, Jan 05, 2021 at 08:08:15AM +0200, Laurent Pinchart wrote:
> Convert the i.MX6 HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart
> ---
> Changes since v1:
>
> - Only specify maxItems for clocks
> - Drop reg and interrupts as they're checked in the base schema
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> - Drop clock-names items, use maxItems only
> ---
> .../bindings/display/imx/fsl,imx6-hdmi.yaml | 130 ++
> .../devicetree/bindings/display/imx/hdmi.txt | 65 -
> 2 files changed, 130 insertions(+), 65 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/imx/hdmi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> new file mode 100644
> index ..f9b131bb3339
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 DWC HDMI TX Encoder
> +
> +maintainers:
> + - Philipp Zabel
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> + with a companion PHY IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> +enum:
> + - fsl,imx6dl-hdmi
> + - fsl,imx6q-hdmi
> +
> + reg-io-width:
> +const: 1
> +
> + clocks:
> +maxItems: 2
> +
> + clock-names:
> +maxItems: 2
> +
> + ddc-i2c-bus:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description:
> + The HDMI DDC bus can be connected to either a system I2C master or the
> + functionally-reduced I2C master contained in the DWC HDMI. When
> connected
> + to a system I2C master this property contains a phandle to that I2C
> + master controller.
This should be deprecated as it should be in the connector node. But
that's a separate issue.
> +
> + gpr:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description:
> + phandle to the iomuxc-gpr region containing the HDMI multiplexer
> control
> + register.
> +
> + ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +description: |
> + This device has four video ports, corresponding to the four inputs of
> the
> + HDMI multiplexer. Each port shall have a single endpoint.
> +
> +properties:
> + port@0:
> +$ref: /schemas/graph.yaml#/$defs/port-base
> +unevaluatedProperties: false
> +description: First input of the HDMI multiplexer
muxing should have been endpoints rather than ports...
Anyways, same 'port' issues here. With those fixes:
Reviewed-by: Rob Herring
> +
> + port@1:
> +$ref: /schemas/graph.yaml#/$defs/port-base
> +unevaluatedProperties: false
> +description: Second input of the HDMI multiplexer
> +
> + port@2:
> +$ref: /schemas/graph.yaml#/$defs/port-base
> +unevaluatedProperties: false
> +description: Third input of the HDMI multiplexer
> +
> + port@3:
> +$ref: /schemas/graph.yaml#/$defs/port-base
> +unevaluatedProperties: false
> +description: Fourth input of the HDMI multiplexer
> +
> +anyOf:
> + - required:
> + - port@0
> + - required:
> + - port@1
> + - required:
> + - port@2
> + - required:
> + - port@3
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - gpr
> + - interrupts
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +
> +hdmi: hdmi@12 {
> +reg = <0x0012 0x9000>;
> +interrupts = <0 115 0x04>;
> +gpr = <>;
> +clocks = < IMX6QDL_CLK_HDMI_IAHB>,
> + < IMX6QDL_CLK_HDMI_ISFR>;
> +clock-names = "iahb", "isfr";
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +
> +hdmi_mux_0: endpoint {
> +remote-endpoint = <_di0_hdmi>;
> +};
> +};
> +
> +port@1 {
> +reg = <1>;
> +
> +hdmi_mux_1: endpoint {
> +remote-endpoint = <_di1_hdmi>;
> +};
> +};
> +};
> +};
> +
> +...
> diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt
> b/Documentation/devicetree/bindings/display/imx/hdmi.txt
> deleted file mode 100644
> index 6d021e71c9cf..
> ---
Re: [PATCH v8] backlight: lms283gf05: Convert to GPIO descriptors
On Mon, Jan 11, 2021 at 10:40:46PM +0100, Linus Walleij wrote: > Mark, can I have your ACK for deleting > include/linux/spi/lms283gf05.h > As part of this patch sets? Acked-by: Mark Brown signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 2/6] dt-bindings: display: bridge: renesas,dw-hdmi: Convert binding to YAML
On Tue, Jan 05, 2021 at 08:08:14AM +0200, Laurent Pinchart wrote:
> Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
>
> Signed-off-by: Laurent Pinchart
> ---
> Changes since v2:
>
> - Update MAINTAINERS
>
> Changes since v1:
>
> - Drop the part numbers in comments, only keep the SoC names
> - Use unevaluatedProperties instead of additionalProperties
> - Only specify maxItems for clocks and clock-names
> - Drop reg, interrupts, #address-cells and #size-cells as they're
> checked in the base schema
> - Use one size and address cell in example
> - Rebase on top of OF graph schema, dropped redundant properties
> - Fix identation for enum entries
> ---
> .../display/bridge/renesas,dw-hdmi.txt| 88
> .../display/bridge/renesas,dw-hdmi.yaml | 128 ++
> MAINTAINERS | 2 +-
> 3 files changed, 129 insertions(+), 89 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> deleted file mode 100644
> index 3f6072651182..
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -Renesas Gen3 DWC HDMI TX Encoder
> -
> -
> -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> -with a companion PHY IP.
> -
> -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> -following device-specific properties.
> -
> -
> -Required properties:
> -
> -- compatible : Shall contain one or more of
> - - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
> - - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
> - - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
> - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
> - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
> - - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
> - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
> - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
> - HDMI TX
> -
> -When compatible with generic versions, nodes must list the SoC-specific
> -version corresponding to the platform first, followed by the
> -family-specific version.
> -
> -- reg: See dw_hdmi.txt.
> -- interrupts: HDMI interrupt number
> -- clocks: See dw_hdmi.txt.
> -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
> -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
> - corresponding to the video input of the controller and one port numbered 1
> - corresponding to its HDMI output, and one port numbered 2 corresponding to
> - sound input of the controller. Each port shall have a single endpoint.
> -
> -Optional properties:
> -
> -- power-domains: Shall reference the power domain that contains the DWC HDMI,
> - if any.
> -
> -
> -Example:
> -
> - hdmi0: hdmi@fead {
> - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
> - reg = <0 0xfead 0 0x1>;
> - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = < CPG_CORE R8A7795_CLK_S0D4>, < CPG_MOD 729>;
> - clock-names = "iahb", "isfr";
> - power-domains = < R8A7795_PD_ALWAYS_ON>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - port@0 {
> - reg = <0>;
> - dw_hdmi0_in: endpoint {
> - remote-endpoint = <_out_hdmi0>;
> - };
> - };
> - port@1 {
> - reg = <1>;
> - rcar_dw_hdmi0_out: endpoint {
> - remote-endpoint = <_con>;
> - };
> - };
> - port@2 {
> - reg = <2>;
> - rcar_dw_hdmi0_sound_in: endpoint {
> - remote-endpoint = <_sound_out>;
> - };
> - };
> - };
> - };
> -
> - hdmi0-out {
> - compatible = "hdmi-connector";
> - label = "HDMI0 OUT";
> - type = "a";
> -
> - port {
> - hdmi0_con: endpoint {
> - remote-endpoint = <_dw_hdmi0_out>;
> -
Re: [PATCH v3 1/6] dt-bindings: display: bridge: Add YAML schema for Synopsys DW-HDMI
On Tue, Jan 05, 2021 at 08:08:13AM +0200, Laurent Pinchart wrote: > Add a .yaml schema containing the common properties for the Synopsys > DesignWare HDMI TX controller. This isn't a full device tree binding > specification, but is meant to be referenced by platform-specific > bindings for the IP core. > > Signed-off-by: Laurent Pinchart > --- > Changes since v1: > > - Add default to reg-io-width property > - Add additionalProperties > - Rebase on top of OF graph schema, dropped redundant properties > - Drop cec clock as it's device-specific > - Increase max clocks to 5 to accommodate the Rockchip DW-HDMI > --- > .../display/bridge/synopsys,dw-hdmi.yaml | 58 +++ > 1 file changed, 58 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml > b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml > new file mode 100644 > index ..96c4bc06dbe7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Common Properties for Synopsys DesignWare HDMI TX Controller > + > +maintainers: > + - Laurent Pinchart > + > +description: | > + This document defines device tree properties for the Synopsys DesignWare > HDMI > + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device > tree > + binding specification by itself but is meant to be referenced by device > tree > + bindings for the platform-specific integrations of the DWC HDMI TX. > + > + When referenced from platform device tree bindings the properties defined > in > + this document are defined as follows. The platform device tree bindings are > + responsible for defining whether each property is required or optional. > + > +properties: > + reg: > +maxItems: 1 > + > + reg-io-width: > +description: > + Width (in bytes) of the registers specified by the reg property. > +allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [1, 4] > +default: 1 > + > + clocks: > +minItems: 2 > +maxItems: 5 > +items: > + - description: The bus clock for either AHB and APB > + - description: The internal register configuration clock > +additionalItems: true > + > + clock-names: > +minItems: 2 > +maxItems: 5 > +items: > + - const: iahb > + - const: isfr > +additionalItems: true > + > + interrupts: > +maxItems: 1 > + > + ports: > +$ref: /schemas/graph.yaml#/properties/ports 'ports' should probably be dropped if what each 'port' is is not defined here. Any users will have to define 'ports' and the child nodes. Reviewed-by: Rob Herring > + > +additionalProperties: true > + > +... > -- > Regards, > > Laurent Pinchart > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/bridge: ti-sn65dsi86: rename GPIO register bits
Hi, On Mon, Jan 11, 2021 at 2:16 PM Doug Anderson wrote: > > Hi, > > On Thu, Dec 10, 2020 at 12:19 AM Shawn Guo wrote: > > > > From: Shawn Guo > > > > It renames GPIO register bits to drop 'SN_' prefix, so that they are > > consistent to other definitions - prefixing register name with 'SN_' but > > not for bit fields. > > > > Signed-off-by: Shawn Guo > > --- > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 26 +- > > 1 file changed, 13 insertions(+), 13 deletions(-) > > Sorry for taking so long to get back to this. I think it came into my > inbox at the same time as a pile of other things and then got lost. > Your change looks good to me. Sorry for being inconsistent when > adding those defines and thanks for fixing them! > > Reviewed-by: Douglas Anderson Hrm, I just caught up on more email and found that in: https://lore.kernel.org/r/20201210174338.kecryijwptzc2...@pengutronix.de ...that Uwe would prefer to keep these bits what I have and change all the others. ;-) I don't have a strong opinion either way, but I definitely agree that it'd be better for all the defines to be consistent. If I had to arbitrarily make the decision one way or the other I'd probably land Shawn's patch but I certainly wouldn't object if we went Uwe's way either. :-P -Doug ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] dt-bindings: display: Augment s6e63m0 bindings
On Fri, 01 Jan 2021 12:45:22 +0100, Linus Walleij wrote: > This fixes the following problems with the s6e63m0 display > bindings: > > - When used on the DSI bus, the panel is listed directly as > a subnode on the DSI host so the "port" node is not > compulsory. Remove "port" from required properties. > > - The panel contains its own backlight control, so reference > the backlight common properties and list default-brightness > and max-brightness as supported but optional properties. > > Cc: devicet...@vger.kernel.org > Signed-off-by: Linus Walleij > --- > .../devicetree/bindings/display/panel/samsung,s6e63m0.yaml| 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/bridge: ti-sn65dsi86: rename GPIO register bits
Hi, On Thu, Dec 10, 2020 at 12:19 AM Shawn Guo wrote: > > From: Shawn Guo > > It renames GPIO register bits to drop 'SN_' prefix, so that they are > consistent to other definitions - prefixing register name with 'SN_' but > not for bit fields. > > Signed-off-by: Shawn Guo > --- > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 26 +- > 1 file changed, 13 insertions(+), 13 deletions(-) Sorry for taking so long to get back to this. I think it came into my inbox at the same time as a pile of other things and then got lost. Your change looks good to me. Sorry for being inconsistent when adding those defines and thanks for fixing them! Reviewed-by: Douglas Anderson -Doug ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 1/2] dt-bindings: drm/bridge: anx7625: add DPI flag and swing setting
On Thu, Dec 31, 2020 at 10:21:12AM +0800, Xin Ji wrote:
> Add DPI flag for distinguish MIPI input signal type, DSI or DPI. Add
> swing setting for adjusting DP tx PHY swing
>
> Signed-off-by: Xin Ji
> ---
> .../bindings/display/bridge/analogix,anx7625.yaml | 25
> --
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
> b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
> index 60585a4..4eb0ea3 100644
> --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
> @@ -34,6 +34,16 @@ properties:
> description: used for reset chip control, RESET_N pin B7.
> maxItems: 1
>
> + analogix,swing-setting:
> +type: uint8-array
Humm, this should have be rejected by the meta-schema.
> +$ref: /schemas/types.yaml#/definitions/uint32-array
This is how types are defined other than boolean or nodes (object).
> +description: an array of swing register setting for DP tx PHY
> +
> + analogix,mipi-dpi-in:
> +type: int
> +$ref: /schemas/types.yaml#/definitions/uint32
> +description: indicate the MIPI rx signal type is DPI or DSI
Why does this need to be in DT, you should be able to determine this
based on what you are connected to.
> +
>ports:
> type: object
>
> @@ -49,8 +59,8 @@ properties:
>Video port for panel or connector.
>
> required:
> -- port@0
> -- port@1
> + - port@0
> + - port@1
>
> required:
>- compatible
> @@ -72,6 +82,17 @@ examples:
> reg = <0x58>;
> enable-gpios = < 45 GPIO_ACTIVE_HIGH>;
> reset-gpios = < 73 GPIO_ACTIVE_HIGH>;
> +analogix,swing-setting = <0x00 0x14>, <0x01 0x54>,
> +<0x02 0x64>, <0x03 0x74>, <0x04 0x29>,
> +<0x05 0x7b>, <0x06 0x77>, <0x07 0x5b>,
> +<0x08 0x7f>, <0x0c 0x20>, <0x0d 0x60>,
> +<0x10 0x60>, <0x12 0x40>, <0x13 0x60>,
> +<0x14 0x14>, <0x15 0x54>, <0x16 0x64>,
> +<0x17 0x74>, <0x18 0x29>, <0x19 0x7b>,
> +<0x1a 0x77>, <0x1b 0x5b>, <0x1c 0x7f>,
> +<0x20 0x20>, <0x21 0x60>, <0x24 0x60>,
> +<0x26 0x40>, <0x27 0x60>;
This is a matrix, which is different from an array type.
> +analogix,mipi-dpi-in = <0>;
>
> ports {
> #address-cells = <1>;
> --
> 2.7.4
>
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12
Hi Christian,
On Tue, 12 Jan 2021 at 01:45, Christian König wrote:
>
> Hi Mike,
>
> Unfortunately not, that's DC stuff. Easiest is to assign this as a bug
> tracker to our DC team.
Ok
> At least some progress. Any objections that I add your e-mail address as
> tested-by tag?
Yes, feel free add me.
> I can take a look at this one here. Looks like some missing error
> handling when allocating memory.
> Can you decode to which line number ttm_tt_swapin+0x34 points to?
$ /usr/src/kernels/`uname -r`/scripts/faddr2line
/lib/debug/lib/modules/`uname
-r`/kernel/drivers/gpu/drm/ttm/ttm.ko.debug ttm_tt_swapin+0x34
ttm_tt_swapin+0x34/0xd0:
mapping_gfp_mask at
/usr/src/debug/kernel-20210108gitf5e6c330254a/linux-5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64/./include/linux/pagemap.h:105
(discriminator 2)
(inlined by) ttm_tt_swapin at
/usr/src/debug/kernel-20210108gitf5e6c330254a/linux-5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64/drivers/gpu/drm/ttm/ttm_tt.c:210
(discriminator 2)
$ cat -s -n
/usr/src/debug/kernel-20210108gitf5e6c330254a/linux-5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64/drivers/gpu/drm/ttm/ttm_tt.c
| head -220 | tail -20
201 struct page *from_page;
202 struct page *to_page;
203 gfp_t gfp_mask;
204 int i, ret;
205
206 swap_storage = ttm->swap_storage;
207 BUG_ON(swap_storage == NULL);
208
209 swap_space = swap_storage->f_mapping;
210 gfp_mask = mapping_gfp_mask(swap_space);
211
212 for (i = 0; i < ttm->num_pages; ++i) {
213 from_page = shmem_read_mapping_page_gfp(swap_space, i,
214 gfp_mask);
215 if (IS_ERR(from_page)) {
216 ret = PTR_ERR(from_page);
217 goto out_err;
218 }
219 to_page = ttm->pages[i];
220 if (unlikely(to_page == NULL)) {
> Please use this one here:
> https://gitlab.freedesktop.org/drm/amd/-/issues/new
>
> If you can't find the DC guys of hand in the assignee list just assign
> to me and I will forward.
https://gitlab.freedesktop.org/drm/amd/-/issues/1439
Ok, let's continue there.
--
Best Regards,
Mike Gavrilov.
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] drm/amdkfd: Fix out-of-bounds read in kdf_create_vcrat_image_cpu()
Am 2021-01-11 um 4:05 p.m. schrieb Jeremy Cline:
> KASAN reported a slab-out-of-bounds read of size 1 in
> kdf_create_vcrat_image_cpu().
>
> This occurs when, for example, when on an x86_64 with a single NUMA node
> because kfd_fill_iolink_info_for_cpu() is a no-op, but afterwards the
> sub_type_hdr->length, which is out-of-bounds, is read and multiplied by
> entries. Fortunately, entries is 0 in this case so the overall
> crat_table->length is still correct.
>
> Check if there were any entries before de-referencing sub_type_hdr which
> may be pointing to out-of-bounds memory.
>
> Fixes: b7b6c38529c9 ("drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)")
> Suggested-by: Felix Kuehling
> Signed-off-by: Jeremy Cline
Thanks. I'll apply this patch.
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 8cac497c2c45..a5640a6138cf 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1040,11 +1040,14 @@ static int kfd_create_vcrat_image_cpu(void
> *pcrat_image, size_t *size)
> (struct crat_subtype_iolink *)sub_type_hdr);
> if (ret < 0)
> return ret;
> - crat_table->length += (sub_type_hdr->length * entries);
> - crat_table->total_entries += entries;
>
> - sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
> - sub_type_hdr->length * entries);
> + if (entries) {
> + crat_table->length += (sub_type_hdr->length * entries);
> + crat_table->total_entries += entries;
> +
> + sub_type_hdr = (typeof(sub_type_hdr))((char
> *)sub_type_hdr +
> + sub_type_hdr->length * entries);
> + }
> #else
> pr_info("IO link not available for non x86 platforms\n");
> #endif
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] dt-bindings: panel-simple: add samsung,s6e3fa2 panel
On Wed, 30 Dec 2020 17:17:10 +0200, Iskren Chernev wrote: > Add samsung,s6e3fa2 in the allowed simple-panel compat strings. > > Signed-off-by: Iskren Chernev > --- > .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8] backlight: lms283gf05: Convert to GPIO descriptors
On Mon, Jan 11, 2021 at 5:19 PM Lee Jones wrote: > > ChangeLog v7->v8: > > - Rebase onto v5.11-rc1 > > - I wonder why this never seems to get merged...? > > Because you need SPI & PXA Acks and a merge plan. Ah you're right I completely missed that the include is down in include/spi/... Mark, can I have your ACK for deleting include/linux/spi/lms283gf05.h As part of this patch sets? I will collect the ACKs and resend with a proposal to merge through the backlight tree. Yours, Linus Walleij ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] drm: Check actual format for legacy pageflip.
On Mon, Jan 11, 2021 at 11:39 AM Bas Nieuwenhuizen
wrote:
>
> On Mon, Jan 11, 2021 at 4:02 PM Alex Deucher wrote:
> >
> > On Sat, Jan 9, 2021 at 9:11 PM Bas Nieuwenhuizen
> > wrote:
> > >
> > > With modifiers one can actually have different format_info structs
> > > for the same format, which now matters for AMDGPU since we convert
> > > implicit modifiers to explicit modifiers with multiple planes.
> > >
> > > I checked other drivers and it doesn't look like they end up triggering
> > > this case so I think this is safe to relax.
> > >
> > > Signed-off-by: Bas Nieuwenhuizen
> > > Reviewed-by: Daniel Vetter
> > > Reviewed-by: Zhan Liu
> > > Acked-by: Christian König
> > > Acked-by: Alex Deucher
> > > Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for converted
> > > metadata.")
> >
> > Do you have commit rights to drm-misc or do you need someone to commit
> > this for you?
>
> I don't have commit rights so if the patch could be committed for me
> that would be appreciated!
Pushed to drm-misc-fixes. Thanks!
If you want access to drm-misc, I don't see any reason you shouldn't have it.
Alex
> >
> > Thanks!
> >
> > Alex
> >
> > > ---
> > > drivers/gpu/drm/drm_plane.c | 9 -
> > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> > > index e6231947f987..a0cb746bcb0a 100644
> > > --- a/drivers/gpu/drm/drm_plane.c
> > > +++ b/drivers/gpu/drm/drm_plane.c
> > > @@ -1163,7 +1163,14 @@ int drm_mode_page_flip_ioctl(struct drm_device
> > > *dev,
> > > if (ret)
> > > goto out;
> > >
> > > - if (old_fb->format != fb->format) {
> > > + /*
> > > +* Only check the FOURCC format code, excluding modifiers. This is
> > > +* enough for all legacy drivers. Atomic drivers have their own
> > > +* checks in their ->atomic_check implementation, which will
> > > +* return -EINVAL if any hw or driver constraint is violated due
> > > +* to modifier changes.
> > > +*/
> > > + if (old_fb->format->format != fb->format->format) {
> > > DRM_DEBUG_KMS("Page flip is not allowed to change frame
> > > buffer format.\n");
> > > ret = -EINVAL;
> > > goto out;
> > > --
> > > 2.29.2
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 209713] amdgpu drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.c:483 dcn10_get_dig_frontend+0x9e/0xc0 [amdgpu] when resuming from S3 state
https://bugzilla.kernel.org/show_bug.cgi?id=209713 --- Comment #5 from Klaus Mueller (kmuel...@justmail.de) --- Seems to be fixed for me since the last firmware update for the Picasso driver: - xf86-video-amdgpu-19.1.0-lp152.67.5.x86_64 - kernel-firmware-20201218-lp152.36.1.noarch -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] drm/amdkfd: Fix out-of-bounds read in kdf_create_vcrat_image_cpu()
KASAN reported a slab-out-of-bounds read of size 1 in
kdf_create_vcrat_image_cpu().
This occurs when, for example, when on an x86_64 with a single NUMA node
because kfd_fill_iolink_info_for_cpu() is a no-op, but afterwards the
sub_type_hdr->length, which is out-of-bounds, is read and multiplied by
entries. Fortunately, entries is 0 in this case so the overall
crat_table->length is still correct.
Check if there were any entries before de-referencing sub_type_hdr which
may be pointing to out-of-bounds memory.
Fixes: b7b6c38529c9 ("drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)")
Suggested-by: Felix Kuehling
Signed-off-by: Jeremy Cline
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 8cac497c2c45..a5640a6138cf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1040,11 +1040,14 @@ static int kfd_create_vcrat_image_cpu(void
*pcrat_image, size_t *size)
(struct crat_subtype_iolink *)sub_type_hdr);
if (ret < 0)
return ret;
- crat_table->length += (sub_type_hdr->length * entries);
- crat_table->total_entries += entries;
- sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
- sub_type_hdr->length * entries);
+ if (entries) {
+ crat_table->length += (sub_type_hdr->length * entries);
+ crat_table->total_entries += entries;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char
*)sub_type_hdr +
+ sub_type_hdr->length * entries);
+ }
#else
pr_info("IO link not available for non x86 platforms\n");
#endif
--
2.29.2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12
Hi Mike, Am 11.01.21 um 20:23 schrieb Mikhail Gavrilov: On Mon, 11 Jan 2021 at 19:01, Christian König wrote: Changing the page table attributes while releasing memory might sleep. So we can't use a spinlock here. Thanks for the report, a patch to fix this is on the mailing list now. Can you look also the first trace? Unfortunately not, that's DC stuff. Easiest is to assign this as a bug tracker to our DC team. Here a same error message "sleeping function called from invalid context" and a lot of [amdgpu] code. [SNIP] -12 is just -ENOMEM. Looks like a memory leak to me, maybe caused by the problem above, maybe something completely unrelated. I will take a look. The looks like a completely unrelated memory leak to me. Probably best if you open up a bug report for this. Yes, the monitor still turns off after applying patch "make the pool shrinker lock a mutex". Anyway patch fixed the issue with flood of message "BUG: sleeping function called from invalid context at mm/vmalloc.c:1756" so kernel log became cleaner. At least some progress. Any objections that I add your e-mail address as tested-by tag? Now the issue with turns off monitor looks in logs so: DMA-API: cacheline tracking ENOMEM, dma-debug disabled amdgpu :0b:00.0: amdgpu: 6b791523 pin failed [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12 BUG: kernel NULL pointer dereference, address: 0060 #PF: supervisor read access in kernel mode #PF: error_code(0x) - not-present page PGD 0 P4D 0 Oops: [#1] SMP NOPTI CPU: 20 PID: 3780 Comm: brave:cs0 Tainted: GW- --- 5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64 #1 Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 2802 10/21/2020 RIP: 0010:ttm_tt_swapin+0x34/0x1b0 [ttm] Code: 55 41 54 55 53 48 83 ec 10 48 8b 47 20 48 89 44 24 08 48 85 c0 0f 84 86 01 00 00 48 8b 44 24 08 49 89 fc 4c 8b a8 e0 01 00 00 <41> 8b 45 60 89 44 24 04 8b 47 0c 85 c0 0f 84 df 00 00 00 31 db 65 RSP: 0018:a7400532b9c0 EFLAGS: 00010286 RAX: 978e2ae25800 RBX: 97910ec12058 RCX: 978e12caac70 RDX: 8010 RSI: RDI: 97912c3d99c0 RBP: 97912c3d99c0 R08: R09: 70b3a000 R10: 0002 R11: R12: 97912c3d99c0 R13: R14: a7400532ba90 R15: 978e182c6350 FS: 7f070bb1b640() GS:97950920() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 0060 CR3: 0001f0cd2000 CR4: 00350ee0 Call Trace: ttm_tt_populate+0xa9/0xe0 [ttm] ttm_bo_handle_move_mem+0x142/0x180 [ttm] ttm_bo_validate+0x12e/0x1c0 [ttm] I can take a look at this one here. Looks like some missing error handling when allocating memory. Can you decode to which line number ttm_tt_swapin+0x34 points to? [SNIP] You said that I need open up a bug report you means site https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7C75040f5053404b0f302b08d8b666769b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459898491581880%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=IbkSfHK%2BD13OCcYMg%2BlNsZixi9gDEQEfS7Mxyf7vGdM%3Dreserved=0 ? I thought mailing lists is better because bug report on bugzilla.kernel.org usually leave opened for several years without attention. Please use this one here: https://gitlab.freedesktop.org/drm/amd/-/issues/new If you can't find the DC guys of hand in the assignee list just assign to me and I will forward. But what you have in your logs so far are only unrelated symptoms, the root of the problem is that somebody is leaking memory. What you could do as well is to try to enable kmemleak and maybe try some bleeding edge branch like drm-misc-fixes or Alex amd-staging-drm-next branch. Thanks for the help, Christian. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object
On 1/11/21 11:15 AM, Daniel Vetter wrote: On Mon, Jan 11, 2021 at 05:13:56PM +0100, Daniel Vetter wrote: On Fri, Jan 08, 2021 at 04:49:55PM +, Grodzovsky, Andrey wrote: Ok then, I guess I will proceed with the dummy pages list implementation then. Andrey From: Koenig, Christian Sent: 08 January 2021 09:52 To: Grodzovsky, Andrey ; Daniel Vetter Cc: amd-...@lists.freedesktop.org ; dri-devel@lists.freedesktop.org ; daniel.vet...@ffwll.ch ; r...@kernel.org ; l.st...@pengutronix.de ; yuq...@gmail.com ; e...@anholt.net ; Deucher, Alexander ; gre...@linuxfoundation.org ; ppaala...@gmail.com ; Wentland, Harry Subject: Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object Mhm, I'm not aware of any let over pointer between TTM and GEM and we worked quite hard on reducing the size of the amdgpu_bo, so another extra pointer just for that corner case would suck quite a bit. We have a ton of other pointers in struct amdgpu_bo (or any of it's lower things) which are fairly single-use, so I'm really not much seeing the point in making this a special case. It also means the lifetime management becomes a bit iffy, since we can't throw away the dummy page then the last reference to the bo is released (since we don't track it there), but only when the last pointer to the device is released. Potentially this means a pile of dangling pages hanging around for too long. Also if you really, really, really want to have this list, please don't reinvent it since we have it already. drmm_ is exactly meant for resources that should be freed when the final drm_device reference disappears. -Daniel I maybe was eager to early, see i need to explicitly allocate the dummy page using page_alloc so i cannot use drmm_kmalloc for this, so once again like with the list i need to wrap it with a container struct which i can then allocate using drmm_kmalloc and inside there will be page pointer. But then on release it needs to free the page and so i supposedly need to use drmm_add_action to free the page before the container struct is released but drmm_kmalloc doesn't allow to set release action on struct allocation. So I created a new drmm_kmalloc_with_action API function but then you also need to supply the optional data pointer for the release action (the struct page in this case) and so this all becomes a bit overcomplicated (but doable). Is this extra API worth adding ? Maybe it can be useful in general. Andrey If you need some ideas for redundant pointers: - destroy callback (kinda not cool to not have this const anyway), we could refcount it all with the overall gem bo. Quite a bit of work. - bdev pointer, if we move the device ttm stuff into struct drm_device, or create a common struct ttm_device, we can ditch that - We could probably merge a few of the fields and find 8 bytes somewhere - we still have 2 krefs, would probably need to fix that before we can merge the destroy callbacks So there's plenty of room still, if the size of a bo struct is really that critical. Imo it's not. Christian. Am 08.01.21 um 15:46 schrieb Andrey Grodzovsky: Daniel had some objections to this (see bellow) and so I guess I need you both to agree on the approach before I proceed. Andrey On 1/8/21 9:33 AM, Christian König wrote: Am 08.01.21 um 15:26 schrieb Andrey Grodzovsky: Hey Christian, just a ping. Was there any question for me here? As far as I can see the best approach would still be to fill the VMA with a single dummy page and avoid pointers in the GEM object. Christian. Andrey On 1/7/21 11:37 AM, Andrey Grodzovsky wrote: On 1/7/21 11:30 AM, Daniel Vetter wrote: On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote: On 1/7/21 11:21 AM, Daniel Vetter wrote: On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote: On 11/23/20 3:01 AM, Christian König wrote: Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky: On 11/21/20 9:15 AM, Christian König wrote: Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky: Will be used to reroute CPU mapped BO's page faults once device is removed. Uff, one page for each exported DMA-buf? That's not something we can do. We need to find a different approach here. Can't we call alloc_page() on each fault and link them together so they are freed when the device is finally reaped? For sure better to optimize and allocate on demand when we reach this corner case, but why the linking ? Shouldn't drm_prime_gem_destroy be good enough place to free ? I want to avoid keeping the page in the GEM object. What we can do is to allocate a page on demand for each fault and link the together in the bdev instead. And when the bdev is then finally destroyed after the last application closed we can finally release all of them. Christian. Hey, started to implement this and then realized that by allocating a page for each fault indiscriminately we will be allocating a new page for each faulting virtual
Re: [PATCH] drm/ttm: Fix address passed to dma_mapping_error() in ttm_pool_map()
On Mon, Jan 11, 2021 at 09:21:48PM +0100, Christian König wrote:
> Am 11.01.21 um 17:40 schrieb Jeremy Cline:
> > check_unmap() is producing a warning about a missing map error check.
> > The return value from dma_map_page() should be checked for an error, not
> > the caller-provided dma_addr.
> >
> > Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3")
> > Signed-off-by: Jeremy Cline
>
> Good catch. Reviewed and pushed to drm-misc-fixes, should be in the -rc by
> the weekend.
>
Great, many thanks!
- Jeremy
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/ttm: Fix address passed to dma_mapping_error() in ttm_pool_map()
Am 11.01.21 um 17:40 schrieb Jeremy Cline:
check_unmap() is producing a warning about a missing map error check.
The return value from dma_map_page() should be checked for an error, not
the caller-provided dma_addr.
Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3")
Signed-off-by: Jeremy Cline
Good catch. Reviewed and pushed to drm-misc-fixes, should be in the -rc
by the weekend.
Thanks for the help,
Christian.
---
drivers/gpu/drm/ttm/ttm_pool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 7b2f60616750..0aa197204b08 100644
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@ -190,7 +190,7 @@ static int ttm_pool_map(struct ttm_pool *pool, unsigned int
order,
size_t size = (1ULL << order) * PAGE_SIZE;
addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);
- if (dma_mapping_error(pool->dev, **dma_addr))
+ if (dma_mapping_error(pool->dev, addr))
return -EFAULT;
}
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12
On Mon, 11 Jan 2021 at 19:01, Christian König wrote:
> Changing the page table attributes while releasing memory might sleep.
> So we can't use a spinlock here.
>
> Thanks for the report, a patch to fix this is on the mailing list now.
Can you look also the first trace?
Here a same error message "sleeping function called from invalid
context" and a lot of [amdgpu] code.
BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:196
in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 501, name: systemd-udevd
1 lock held by systemd-udevd/501:
#0: 978e0278d258 (>mutex){}-{3:3}, at:
device_driver_attach+0x3b/0xb0
CPU: 25 PID: 501 Comm: systemd-udevd Not tainted
5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64 #1
Hardware name: System manufacturer System Product Name/ROG STRIX
X570-I GAMING, BIOS 2802 10/21/2020
Call Trace:
dump_stack+0x8b/0xb0
___might_sleep.cold+0xb6/0xc6
? dcn30_clock_source_create+0x34/0xb0 [amdgpu]
kmem_cache_alloc_trace+0x204/0x230
dcn30_clock_source_create+0x34/0xb0 [amdgpu]
dcn30_create_resource_pool+0x1d9/0x13a0 [amdgpu]
? rcu_read_lock_sched_held+0x3f/0x80
? trace_kmalloc+0xb2/0xe0
? __kmalloc+0x191/0x280
? dc_create_resource_pool+0x110/0x1d0 [amdgpu]
dc_create_resource_pool+0x110/0x1d0 [amdgpu]
dc_create+0x205/0x790 [amdgpu]
? trace_kmalloc+0xb2/0xe0
? kmem_cache_alloc_trace+0x174/0x230
amdgpu_dm_init.isra.0+0x1b9/0x250 [amdgpu]
? dev_vprintk_emit+0x171/0x195
? dev_printk_emit+0x3e/0x40
dm_hw_init+0xe/0x20 [amdgpu]
amdgpu_device_init.cold+0x179f/0x1afd [amdgpu]
? pci_conf1_read+0xa4/0x100
amdgpu_driver_load_kms+0x68/0x280 [amdgpu]
amdgpu_pci_probe+0x129/0x1b0 [amdgpu]
local_pci_probe+0x42/0x80
pci_device_probe+0xd9/0x1a0
really_probe+0x205/0x460
driver_probe_device+0xe1/0x150
device_driver_attach+0xa8/0xb0
__driver_attach+0x8c/0x150
? device_driver_attach+0xb0/0xb0
? device_driver_attach+0xb0/0xb0
bus_for_each_dev+0x67/0x90
bus_add_driver+0x12e/0x1f0
driver_register+0x8f/0xe0
? 0xc0d9c000
do_one_initcall+0x67/0x320
? rcu_read_lock_sched_held+0x3f/0x80
? trace_kmalloc+0xb2/0xe0
? kmem_cache_alloc_trace+0x174/0x230
do_init_module+0x5c/0x270
__do_sys_init_module+0x130/0x190
do_syscall_64+0x33/0x40
entry_SYSCALL_64_after_hwframe+0x44/0xa9
RIP: 0033:0x7f363661deee
Code: 48 8b 0d 85 1f 0c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f
84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 af 00 00 00 0f 05 <48> 3d
01 f0 ff ff 73 01 c3 48 8b 0d 52 1f 0c 00 f7 d8 64 89 01 48
RSP: 002b:7ffeb7191588 EFLAGS: 0246 ORIG_RAX: 00af
RAX: ffda RBX: 561b94563170 RCX: 7f363661deee
RDX: 561b94579df0 RSI: 00b8a356 RDI: 7f3633b9e010
RBP: 7f3633b9e010 R08: 561b94565240 R09: 7ffeb718d786
R10: 561ef5ef1595 R11: 0246 R12: 561b94579df0
R13: 561b9457a3e0 R14: R15: 561b94576530
[drm] Display Core initialized with v3.2.116!
[drm] DMUB hardware initialized: version=0x0201
usb 1-3.2: new high-speed USB device number 5 using xhci_hcd
[drm] REG_WAIT timeout 1us * 10 tries - mpc2_assert_idle_mpcc line:480
> > -12 is just -ENOMEM. Looks like a memory leak to me, maybe caused by
> > the problem above, maybe something completely unrelated.
> >
> > I will take a look.
>
> The looks like a completely unrelated memory leak to me.
>
> Probably best if you open up a bug report for this.
Yes, the monitor still turns off after applying patch "make the pool
shrinker lock a mutex".
Anyway patch fixed the issue with flood of message "BUG: sleeping
function called from invalid context at mm/vmalloc.c:1756" so kernel
log became cleaner.
Now the issue with turns off monitor looks in logs so:
DMA-API: cacheline tracking ENOMEM, dma-debug disabled
amdgpu :0b:00.0: amdgpu: 6b791523 pin failed
[drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin
framebuffer with error -12
BUG: kernel NULL pointer dereference, address: 0060
#PF: supervisor read access in kernel mode
#PF: error_code(0x) - not-present page
PGD 0 P4D 0
Oops: [#1] SMP NOPTI
CPU: 20 PID: 3780 Comm: brave:cs0 Tainted: GW-
--- 5.11.0-0.rc2.20210108gitf5e6c330254a.120.fc34.x86_64 #1
Hardware name: System manufacturer System Product Name/ROG STRIX
X570-I GAMING, BIOS 2802 10/21/2020
RIP: 0010:ttm_tt_swapin+0x34/0x1b0 [ttm]
Code: 55 41 54 55 53 48 83 ec 10 48 8b 47 20 48 89 44 24 08 48 85 c0
0f 84 86 01 00 00 48 8b 44 24 08 49 89 fc 4c 8b a8 e0 01 00 00 <41> 8b
45 60 89 44 24 04 8b 47 0c 85 c0 0f 84 df 00 00 00 31 db 65
RSP: 0018:a7400532b9c0 EFLAGS: 00010286
RAX: 978e2ae25800 RBX: 97910ec12058 RCX: 978e12caac70
RDX: 8010 RSI: RDI: 97912c3d99c0
RBP: 97912c3d99c0 R08: R09: 70b3a000
R10: 0002 R11: R12: 97912c3d99c0
R13: R14: a7400532ba90 R15: 978e182c6350
FS: 7f070bb1b640()
[PATCH 40/40] drm/amd/display/dc/core/dc_stream: Demote non-conformant kernel-doc headers
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:253: warning: Function parameter or member 'pStream' not described in 'dc_optimize_timing_for_fsft' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:253: warning: Function parameter or member 'max_input_rate_in_khz' not described in 'dc_optimize_timing_for_fsft' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:270: warning: Function parameter or member 'stream' not described in 'dc_stream_set_cursor_attributes' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:270: warning: Function parameter or member 'attributes' not described in 'dc_stream_set_cursor_attributes' Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index c103f858375d0..25fa712a78474 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -244,7 +244,7 @@ struct dc_stream_status *dc_stream_get_status( } #ifndef TRIM_FSFT -/** +/* * dc_optimize_timing_for_fsft() - dc to optimize timing */ bool dc_optimize_timing_for_fsft( @@ -260,8 +260,7 @@ bool dc_optimize_timing_for_fsft( } #endif - -/** +/* * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 39/40] drm/amd/display/dc/core/dc_surface: Demote kernel-doc abuse
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_surface.c:119: warning: Cannot understand * Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Aurabindo Pillai Cc: Josip Pavic Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 3d7d27435f15e..e6b9c6a718413 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -115,7 +115,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) return plane_state; } -/** +/* * * Function: dc_plane_get_status * -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 34/40] drm/amd/display/dc/dce110/dce110_transform_v: Demote kernel-doc abuse
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_transform_v.c:228: warning: bad line:void drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_transform_v.c:233: warning: Function parameter or member 'xfm_dce' not described in 'program_overscan' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_transform_v.c:233: warning: Function parameter or member 'data' not described in 'program_overscan' Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- .../display/dc/dce110/dce110_transform_v.c| 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c index b1aaab5590cc6..29438c6050dbb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c @@ -217,16 +217,15 @@ static bool setup_scaling_configuration( return is_scaling_needed; } -/** -* Function: -* void program_overscan -* -* Purpose: Programs overscan border -* Input: overscan -* -* Output: - void -*/ +/* + * Function: + * void program_overscan + * + * Purpose: Programs overscan border + * Input: overscan + * + * Output: void + */ static void program_overscan( struct dce_transform *xfm_dce, const struct scaler_data *data) -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 36/40] drm/amd/display/dc/dce100/dce100_resource: Make local functions and ones called by reference static
Fixes the following W=1 kernel build warning(s):
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:54:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:614:22:
warning: no previous prototype for ‘dce100_link_encoder_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:653:32:
warning: no previous prototype for ‘dce100_opp_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:668:17:
warning: no previous prototype for ‘dce100_aux_engine_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:706:20:
warning: no previous prototype for ‘dce100_i2c_hw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:721:22:
warning: no previous prototype for ‘dce100_clock_source_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:745:6:
warning: no previous prototype for ‘dce100_clock_source_destroy’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:834:6:
warning: no previous prototype for ‘dce100_validate_bandwidth’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce100/dce100_resource.c:879:16:
warning: no previous prototype for ‘dce100_validate_global’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Anthony Koo
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../drm/amd/display/dc/dce100/dce100_resource.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index f20ed05a5050d..648169086bcf8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -611,7 +611,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
};
-struct link_encoder *dce100_link_encoder_create(
+static struct link_encoder *dce100_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@@ -650,7 +650,7 @@ static struct panel_cntl *dce100_panel_cntl_create(const
struct panel_cntl_init_
return _cntl->base;
}
-struct output_pixel_processor *dce100_opp_create(
+static struct output_pixel_processor *dce100_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -665,7 +665,7 @@ struct output_pixel_processor *dce100_opp_create(
return >base;
}
-struct dce_aux *dce100_aux_engine_create(
+static struct dce_aux *dce100_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -703,7 +703,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
-struct dce_i2c_hw *dce100_i2c_hw_create(
+static struct dce_i2c_hw *dce100_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -718,7 +718,7 @@ struct dce_i2c_hw *dce100_i2c_hw_create(
return dce_i2c_hw;
}
-struct clock_source *dce100_clock_source_create(
+static struct clock_source *dce100_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -742,7 +742,7 @@ struct clock_source *dce100_clock_source_create(
return NULL;
}
-void dce100_clock_source_destroy(struct clock_source **clk_src)
+static void dce100_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -831,7 +831,7 @@ static enum dc_status build_mapped_resource(
return DC_OK;
}
-bool dce100_validate_bandwidth(
+static bool dce100_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -876,7 +876,7 @@ static bool dce100_validate_surface_sets(
return true;
}
-enum dc_status dce100_validate_global(
+static enum dc_status dce100_validate_global(
struct dc *dc,
struct dc_state *context)
{
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 32/40] drm/amd/display/dc/dce110/Makefile: Ignore -Woverride-init warning
Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:66: drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_0_sh_mask.h:5936:51: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:116:16: note: in expansion of macro ‘DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:306:2: note: in expansion of macro ‘SE_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_0_sh_mask.h:5936:51: note: (near initialization for ‘se_shift.DIG_STEREOSYNC_SELECT’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:116:16: note: in expansion of macro ‘DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:306:2: note: in expansion of macro ‘SE_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_0_sh_mask.h:5938:52: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:116:16: note: in expansion of macro ‘DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.h:307:2: note: in expansion of macro ‘SE_SF’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_0_sh_mask.h:5938:52: note: (near initialization for ‘se_shift.DIG_STEREOSYNC_GATE_EN’) NB: Snipped for brevity Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/dce110/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile index d564c0eb8b045..84ab48df0c261 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile @@ -23,6 +23,8 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. +CFLAGS_$(AMDDALPATH)/dc/dce110/dce110_resource.o = $(call cc-disable-warning, override-init) + DCE110 = dce110_timing_generator.o \ dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \ dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 33/40] drm/amd/display/dc/dce110/dce110_resource: Make local functions invoked by reference static
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:266:2: note: in expansion of macro ‘stream_enc_regs’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: note: (near initialization for ‘stream_enc_regs[0].TMDS_CNTL’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:266:2: note: in expansion of macro ‘stream_enc_regs’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:267:2: note: in expansion of macro ‘stream_enc_regs’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: note: (near initialization for ‘stream_enc_regs[1].TMDS_CNTL’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:267:2: note: in expansion of macro ‘stream_enc_regs’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:268:2: note: in expansion of macro ‘stream_enc_regs’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:262:15: note: (near initialization for ‘stream_enc_regs[2].TMDS_CNTL’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:268:2: note: in expansion of macro ‘stream_enc_regs’ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:66: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:272:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:276:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:276:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:276:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:276:3: note: in expansion of macro ‘SE_COMMON_MASK_SH_LIST_DCE110’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:553:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:553:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:553:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:553:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:557:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:557:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:557:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:557:3: note: in expansion of macro ‘HWSEQ_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:594:3: note: in expansion of macro ‘MI_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:594:3: note: in expansion of macro ‘MI_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:599:3: note: in expansion of macro ‘MI_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:599:3: note: in expansion of macro ‘MI_DCE11_MASK_SH_LIST’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:718:17: warning: no previous prototype for ‘dce110_aux_engine_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:756:20: warning: no previous prototype for ‘dce110_i2c_hw_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:771:22: warning: no previous prototype for ‘dce110_clock_source_create’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.c:795:6: warning: no previous prototype for ‘dce110_clock_source_destroy’ [-Wmissing-prototypes]
[PATCH 35/40] drm/amd/display/dc/dce60/dce60_timing_generator: Make 'dce60_configure_crc' invoked by reference static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_timing_generator.c:192:6:
warning: no previous prototype for ‘dce60_configure_crc’ [-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Mauro Rossi
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
index fc1af0ff0ca4c..c1a85ee374d9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
@@ -189,8 +189,8 @@ static bool dce60_is_tg_enabled(struct timing_generator *tg)
return field == 1;
}
-bool dce60_configure_crc(struct timing_generator *tg,
- const struct crc_params *params)
+static bool dce60_configure_crc(struct timing_generator *tg,
+ const struct crc_params *params)
{
/* Cannot configure crc on a CRTC that is disabled */
if (!dce60_is_tg_enabled(tg))
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 38/40] drm/amd/display/dc/dce80/dce80_resource: Make local functions static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17:
warning: no previous prototype for ‘dce80_aux_engine_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20:
warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20:
warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22:
warning: no previous prototype for ‘dce80_link_encoder_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22:
warning: no previous prototype for ‘dce80_clock_source_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6:
warning: no previous prototype for ‘dce80_clock_source_destroy’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6:
warning: no previous prototype for ‘dce80_validate_bandwidth’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16:
warning: no previous prototype for ‘dce80_validate_global’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Anthony Koo
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../drm/amd/display/dc/dce80/dce80_resource.c| 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 26fe25caa2813..fe5d716084363 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -524,7 +524,7 @@ static struct output_pixel_processor *dce80_opp_create(
return >base;
}
-struct dce_aux *dce80_aux_engine_create(
+static struct dce_aux *dce80_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -562,7 +562,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
-struct dce_i2c_hw *dce80_i2c_hw_create(
+static struct dce_i2c_hw *dce80_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -578,7 +578,7 @@ struct dce_i2c_hw *dce80_i2c_hw_create(
return dce_i2c_hw;
}
-struct dce_i2c_sw *dce80_i2c_sw_create(
+static struct dce_i2c_sw *dce80_i2c_sw_create(
struct dc_context *ctx)
{
struct dce_i2c_sw *dce_i2c_sw =
@@ -712,7 +712,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
};
-struct link_encoder *dce80_link_encoder_create(
+static struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@@ -751,7 +751,7 @@ static struct panel_cntl *dce80_panel_cntl_create(const
struct panel_cntl_init_d
return _cntl->base;
}
-struct clock_source *dce80_clock_source_create(
+static struct clock_source *dce80_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -775,7 +775,7 @@ struct clock_source *dce80_clock_source_create(
return NULL;
}
-void dce80_clock_source_destroy(struct clock_source **clk_src)
+static void dce80_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -865,7 +865,7 @@ static void dce80_resource_destruct(struct
dce110_resource_pool *pool)
}
}
-bool dce80_validate_bandwidth(
+static bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -910,7 +910,7 @@ static bool dce80_validate_surface_sets(
return true;
}
-enum dc_status dce80_validate_global(
+static enum dc_status dce80_validate_global(
struct dc *dc,
struct dc_state *context)
{
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 37/40] drm/amd/display/dc/dce60/dce60_resource: Make local functions static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:522:17:
warning: no previous prototype for ‘dce60_aux_engine_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:560:20:
warning: no previous prototype for ‘dce60_i2c_hw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:576:20:
warning: no previous prototype for ‘dce60_i2c_sw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:710:22:
warning: no previous prototype for ‘dce60_link_encoder_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:749:22:
warning: no previous prototype for ‘dce60_clock_source_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:773:6:
warning: no previous prototype for ‘dce60_clock_source_destroy’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:863:6:
warning: no previous prototype for ‘dce60_validate_bandwidth’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:908:16:
warning: no previous prototype for ‘dce60_validate_global’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Mauro Rossi
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../drm/amd/display/dc/dce60/dce60_resource.c| 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
index e9dd78c484d6e..64f4a0da146bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -519,7 +519,7 @@ static struct output_pixel_processor *dce60_opp_create(
return >base;
}
-struct dce_aux *dce60_aux_engine_create(
+static struct dce_aux *dce60_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -557,7 +557,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
-struct dce_i2c_hw *dce60_i2c_hw_create(
+static struct dce_i2c_hw *dce60_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -573,7 +573,7 @@ struct dce_i2c_hw *dce60_i2c_hw_create(
return dce_i2c_hw;
}
-struct dce_i2c_sw *dce60_i2c_sw_create(
+static struct dce_i2c_sw *dce60_i2c_sw_create(
struct dc_context *ctx)
{
struct dce_i2c_sw *dce_i2c_sw =
@@ -707,7 +707,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
};
-struct link_encoder *dce60_link_encoder_create(
+static struct link_encoder *dce60_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@@ -746,7 +746,7 @@ static struct panel_cntl *dce60_panel_cntl_create(const
struct panel_cntl_init_d
return _cntl->base;
}
-struct clock_source *dce60_clock_source_create(
+static struct clock_source *dce60_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -770,7 +770,7 @@ struct clock_source *dce60_clock_source_create(
return NULL;
}
-void dce60_clock_source_destroy(struct clock_source **clk_src)
+static void dce60_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -860,7 +860,7 @@ static void dce60_resource_destruct(struct
dce110_resource_pool *pool)
}
}
-bool dce60_validate_bandwidth(
+static bool dce60_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -905,7 +905,7 @@ static bool dce60_validate_surface_sets(
return true;
}
-enum dc_status dce60_validate_global(
+static enum dc_status dce60_validate_global(
struct dc *dc,
struct dc_state *context)
{
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 26/40] drm/amd/display/dc/dce110/dce110_timing_generator: Demote kernel-doc abuses to standard function headers
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:79: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:124: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_enable_crtc' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:179: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:233: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_disable_crtc' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:258: warning: Function parameter or member 'tg' not described in 'program_horz_count_by_2' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:258: warning: Function parameter or member 'timing' not described in 'program_horz_count_by_2' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:284: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_program_timing_generator' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:284: warning: Function parameter or member 'dc_crtc_timing' not described in 'dce110_timing_generator_program_timing_generator' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:356: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:525: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:561: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1118: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_validate_timing' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1118: warning: Function parameter or member 'timing' not described in 'dce110_timing_generator_validate_timing' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1118: warning: Function parameter or member 'signal' not described in 'dce110_timing_generator_validate_timing' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1174: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_wait_for_vblank' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1198: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_wait_for_vactive' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1208: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1386: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1768: warning: Cannot understand * drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1801: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_disable_vga' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1851: warning: Function parameter or member 'tg' not described in 'dce110_timing_generator_set_overscan_color_black' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1851: warning: Function parameter or member 'color' not described in 'dce110_timing_generator_set_overscan_color_black' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.c:1851: warning: Excess function parameter 'param' description in 'dce110_timing_generator_set_overscan_color_black' Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Anthony Koo Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- .../dc/dce110/dce110_timing_generator.c | 71 +-- 1 file changed, 34 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 9a6c411bb7fe6..d88a74559edd7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++
[PATCH 31/40] drm/amd/display/dc/dce110/dce110_mem_input_v: Include our own header, containing prototypes
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:1034:6: warning: no previous prototype for ‘dce110_mem_input_v_construct’ [-Wmissing-prototypes] Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Lee Jones Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 19b1976139b69..8bbb499067f74 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -34,6 +34,7 @@ #include "inc/dce_calcs.h" #include "dce/dce_mem_input.h" +#include "dce110_mem_input_v.h" static void set_flip_control( struct dce_mem_input *mem_input110, -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 29/40] drm/amd/display/dc/dce112/dce112_resource: Make local functions and ones called by reference static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:620:22:
warning: no previous prototype for ‘dce112_link_encoder_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:674:32:
warning: no previous prototype for ‘dce112_opp_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:689:17:
warning: no previous prototype for ‘dce112_aux_engine_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:727:20:
warning: no previous prototype for ‘dce112_i2c_hw_create’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:742:22:
warning: no previous prototype for ‘dce112_clock_source_create’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:766:6:
warning: no previous prototype for ‘dce112_clock_source_destroy’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:1027:16:
warning: no previous prototype for ‘dce112_validate_global’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:1205:29:
warning: no previous prototype for ‘dce112_resource_cap’ [-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Anthony Koo
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../drm/amd/display/dc/dce112/dce112_resource.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index f99b1c0845908..c68e576a21990 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -617,7 +617,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.flags.bits.IS_TPS4_CAPABLE = true
};
-struct link_encoder *dce112_link_encoder_create(
+static struct link_encoder *dce112_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@@ -671,7 +671,7 @@ static struct input_pixel_processor *dce112_ipp_create(
return >base;
}
-struct output_pixel_processor *dce112_opp_create(
+static struct output_pixel_processor *dce112_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -686,7 +686,7 @@ struct output_pixel_processor *dce112_opp_create(
return >base;
}
-struct dce_aux *dce112_aux_engine_create(
+static struct dce_aux *dce112_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -724,7 +724,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
-struct dce_i2c_hw *dce112_i2c_hw_create(
+static struct dce_i2c_hw *dce112_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -739,7 +739,7 @@ struct dce_i2c_hw *dce112_i2c_hw_create(
return dce_i2c_hw;
}
-struct clock_source *dce112_clock_source_create(
+static struct clock_source *dce112_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -763,7 +763,7 @@ struct clock_source *dce112_clock_source_create(
return NULL;
}
-void dce112_clock_source_destroy(struct clock_source **clk_src)
+static void dce112_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -1024,7 +1024,7 @@ enum dc_status dce112_add_stream_to_ctx(
return result;
}
-enum dc_status dce112_validate_global(
+static enum dc_status dce112_validate_global(
struct dc *dc,
struct dc_state *context)
{
@@ -1202,7 +1202,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
dm_pp_notify_wm_clock_changes(dc->ctx, _ranges);
}
-const struct resource_caps *dce112_resource_cap(
+static const struct resource_caps *dce112_resource_cap(
struct hw_asic_id *asic_id)
{
if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 27/40] drm/amd/display/dc/dce110/dce110_compressor: Strip out unused function 'controller_id_to_index'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_compressor.c:429:14:
warning: no previous prototype for ‘controller_id_to_index’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Lee Jones
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../amd/display/dc/dce110/dce110_compressor.c | 25 ---
1 file changed, 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 18b0a69b0b1e8..44564a4742b52 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -425,31 +425,6 @@ void get_max_support_fbc_buffersize(unsigned int *max_x,
unsigned int *max_y)
*/
}
-
-unsigned int controller_id_to_index(enum controller_id controller_id)
-{
- unsigned int index = 0;
-
- switch (controller_id) {
- case CONTROLLER_ID_D0:
- index = 0;
- break;
- case CONTROLLER_ID_D1:
- index = 1;
- break;
- case CONTROLLER_ID_D2:
- index = 2;
- break;
- case CONTROLLER_ID_D3:
- index = 3;
- break;
- default:
- break;
- }
- return index;
-}
-
-
static const struct compressor_funcs dce110_compressor_funcs = {
.power_up_fbc = dce110_compressor_power_up_fbc,
.enable_fbc = dce110_compressor_enable_fbc,
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 30/40] drm/amd/display/dc/dce110/dce110_timing_generator_v: Demote kernel-doc abuse and line up comments
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator_v.c:54:
warning: Function parameter or member 'tg' not described in
'dce110_timing_generator_v_enable_crtc'
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator_v.c:216:
warning: Function parameter or member 'tg' not described in
'dce110_timing_generator_v_wait_for_vactive'
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../dc/dce110/dce110_timing_generator_v.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
index a13a2f58944e3..c509384fff543 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
@@ -46,17 +46,16 @@
*
**/
-/**
-* Enable CRTCV
-*/
+/*
+ * Enable CRTCV
+ */
static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
{
/*
-* Set MASTER_UPDATE_MODE to 0
-* This is needed for DRR, and also suggested to be default value by Syed.
-*/
-
+ * Set MASTER_UPDATE_MODE to 0
+ * This is needed for DRR, and also suggested to be default value by Syed.
+ */
uint32_t value;
value = 0;
@@ -209,9 +208,9 @@ static void
dce110_timing_generator_v_wait_for_vblank(struct timing_generator *t
}
}
-/**
-* Wait till we are in VActive (anywhere in VActive)
-*/
+/*
+ * Wait till we are in VActive (anywhere in VActive)
+ */
static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator
*tg)
{
while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 28/40] drm/amd/display/dc/calcs/dce_calcs: Demote non-conformant kernel-doc function headers
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2753: warning: Function parameter or member 'vbios' not described in 'is_display_configuration_supported' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2753: warning: Function parameter or member 'calcs_output' not described in 'is_display_configuration_supported' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'ctx' not described in 'bw_calcs' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'dceip' not described in 'bw_calcs' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'vbios' not described in 'bw_calcs' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'pipe' not described in 'bw_calcs' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'pipe_count' not described in 'bw_calcs' drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3030: warning: Function parameter or member 'calcs_output' not described in 'bw_calcs' Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Lee Jones Cc: amd-...@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index f69c2b84d432b..967d6d80bd38e 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2743,7 +2743,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, kfree(vbios); } -/** +/* * Compare calculated (required) clocks against the clocks available at * maximum voltage (max Performance Level). */ @@ -3014,13 +3014,12 @@ static bool all_displays_in_sync(const struct pipe_ctx pipe[], return true; } -/** +/* * Return: * true - Display(s) configuration supported. * In this case 'calcs_output' contains data for HW programming * false - Display(s) configuration not supported (not enough bandwidth). */ - bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip, const struct bw_calcs_vbios *vbios, -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 25/40] drm/amd/display/dc/dce120/dce120_timing_generator: Remove unused function 'dce120_timing_generator_get_position'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_timing_generator.c:602:13:
warning: ‘dce120_timing_generator_get_position’ defined but not used
[-Wunused-function]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Lee Jones
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../dc/dce120/dce120_timing_generator.c | 43 ---
1 file changed, 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index d02ecb983c9cd..b57c466124e76 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -589,49 +589,6 @@ static void dce120_timing_generator_set_drr(
}
}
-/*
- *
- * Function: dce120_timing_generator_get_position
- *
- * @brief
- * Returns CRTC vertical/horizontal counters
- *
- * @param [out] position
- *
- */
-static void dce120_timing_generator_get_position(struct timing_generator *tg,
- struct crtc_position *position)
-{
- uint32_t value;
- struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-
- value = dm_read_reg_soc15(
- tg->ctx,
- mmCRTC0_CRTC_STATUS_POSITION,
- tg110->offsets.crtc);
-
- position->horizontal_count = get_reg_field_value(
- value,
- CRTC0_CRTC_STATUS_POSITION,
- CRTC_HORZ_COUNT);
-
- position->vertical_count = get_reg_field_value(
- value,
- CRTC0_CRTC_STATUS_POSITION,
- CRTC_VERT_COUNT);
-
- value = dm_read_reg_soc15(
- tg->ctx,
- mmCRTC0_CRTC_NOM_VERT_POSITION,
- tg110->offsets.crtc);
-
- position->nominal_vcount = get_reg_field_value(
- value,
- CRTC0_CRTC_NOM_VERT_POSITION,
- CRTC_VERT_COUNT_NOM);
-}
-
-
static void dce120_timing_generator_get_crtc_scanoutpos(
struct timing_generator *tg,
uint32_t *v_blank_start,
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 23/40] drm/amd/display/dc/dce110/dce110_mem_input_v: Make local functions static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:471:6:
warning: no previous prototype for ‘dce_mem_input_v_is_surface_pending’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:486:6:
warning: no previous prototype for
‘dce_mem_input_v_program_surface_flip_and_addr’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:563:6:
warning: no previous prototype for ‘dce_mem_input_v_program_pte_vm’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:636:6:
warning: no previous prototype for ‘dce_mem_input_v_program_surface_config’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:922:6:
warning: no previous prototype for ‘dce_mem_input_v_program_display_marks’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:945:6:
warning: no previous prototype for ‘dce_mem_input_program_chroma_display_marks’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:966:6:
warning: no previous prototype for ‘dce110_allocate_mem_input_v’
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_mem_input_v.c:1008:6:
warning: no previous prototype for ‘dce110_free_mem_input_v’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../amd/display/dc/dce110/dce110_mem_input_v.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index d54172d88f5f3..19b1976139b69 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -468,7 +468,7 @@ static void program_pixel_format(
}
}
-bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
+static bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
{
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
uint32_t value;
@@ -483,7 +483,7 @@ bool dce_mem_input_v_is_surface_pending(struct mem_input
*mem_input)
return false;
}
-bool dce_mem_input_v_program_surface_flip_and_addr(
+static bool dce_mem_input_v_program_surface_flip_and_addr(
struct mem_input *mem_input,
const struct dc_plane_address *address,
bool flip_immediate)
@@ -560,7 +560,7 @@ static const unsigned int *get_dvmm_hw_setting(
}
}
-void dce_mem_input_v_program_pte_vm(
+static void dce_mem_input_v_program_pte_vm(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@@ -633,7 +633,7 @@ void dce_mem_input_v_program_pte_vm(
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C,
value);
}
-void dce_mem_input_v_program_surface_config(
+static void dce_mem_input_v_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@@ -919,7 +919,7 @@ static void program_nbp_watermark_c(
marks);
}
-void dce_mem_input_v_program_display_marks(
+static void dce_mem_input_v_program_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@@ -942,7 +942,7 @@ void dce_mem_input_v_program_display_marks(
}
-void dce_mem_input_program_chroma_display_marks(
+static void dce_mem_input_program_chroma_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@@ -963,7 +963,7 @@ void dce_mem_input_program_chroma_display_marks(
stutter);
}
-void dce110_allocate_mem_input_v(
+static void dce110_allocate_mem_input_v(
struct mem_input *mi,
uint32_t h_total,/* for current stream */
uint32_t v_total,/* for current stream */
@@ -1005,7 +1005,7 @@ void dce110_allocate_mem_input_v(
}
-void dce110_free_mem_input_v(
+static void dce110_free_mem_input_v(
struct mem_input *mi,
uint32_t total_stream_num)
{
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 24/40] drm/amd/pm/swsmu/smu11/vangogh_ppt: Make local function 'vangogh_clk_dpm_is_enabled' static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:613:6: warning: no
previous prototype for ‘vangogh_clk_dpm_is_enabled’ [-Wmissing-prototypes]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Xiaojian Du
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 75ddcadf3802a..37bd4c647418d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -610,8 +610,8 @@ static int vangogh_get_profiling_clk_mask(struct
smu_context *smu,
return 0;
}
-bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
- enum smu_clk_type clk_type)
+static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
+ enum smu_clk_type clk_type)
{
enum smu_feature_mask feature_id = 0;
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 21/40] drm/amd/display/dc/dce110/dce110_compressor: Remove unused function 'dce110_get_required_compressed_surfacesize
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_compressor.c:415:6:
warning: no previous prototype for ‘dce110_get_required_compressed_surfacesize’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../amd/display/dc/dce110/dce110_compressor.c | 30 ---
1 file changed, 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 72b580a4eb856..18b0a69b0b1e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -412,36 +412,6 @@ void dce110_compressor_destroy(struct compressor
**compressor)
*compressor = NULL;
}
-bool dce110_get_required_compressed_surfacesize(struct fbc_input_info
fbc_input_info,
- struct
fbc_requested_compressed_size size)
-{
- bool result = false;
-
- unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
-
- get_max_support_fbc_buffersize(_x, _y);
-
- if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
- /*
-* For DCE11 here use Max HW supported size: HW Support up to
3840x2400 resolution
-* or 18000 chunks.
-*/
- size.preferred_size = size.min_size =
align_to_chunks_number_per_line(max_x) * max_y * 4; /* (For FBC when LPT not
supported). */
- size.preferred_size_alignment = size.min_size_alignment =
0x100; /* For FBC when LPT not supported */
- size.bits.preferred_must_be_framebuffer_pool = 1;
- size.bits.min_must_be_framebuffer_pool = 1;
-
- result = true;
- }
- /*
-* Maybe to add registry key support with optional size here to
override above
-* for debugging purposes
-*/
-
- return result;
-}
-
-
void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
{
*max_x = FBC_MAX_X;
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 19/40] drm/amd/display/dc/dce/dce_opp: Remove duplicate entries causing 'field overwritten' issues
Fixes the following W=1 kernel build warning(s):
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:59:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10480:62:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:96:16: note: in
expansion of macro ‘FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:114:2: note: in
expansion of macro ‘OPP_SF’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:148:2: note: in
expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:321:2: note:
in expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_112’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10480:62:
note: (near initialization for ‘opp_shift.FMT_TEMPORAL_DITHER_EN’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:96:16: note: in
expansion of macro ‘FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:114:2: note: in
expansion of macro ‘OPP_SF’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:148:2: note: in
expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:321:2: note:
in expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_112’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10479:60:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:96:16: note: in
expansion of macro ‘FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:114:2: note: in
expansion of macro ‘OPP_SF’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:148:2: note: in
expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:325:2: note:
in expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_112’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10479:60:
note: (near initialization for ‘opp_mask.FMT_TEMPORAL_DITHER_EN’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:96:16: note: in
expansion of macro ‘FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:114:2: note: in
expansion of macro ‘OPP_SF’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.h:148:2: note: in
expansion of macro ‘OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE’
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Mauro Rossi
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index 4d484ef60f357..bf1ffc3629c7f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -111,7 +111,6 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
- OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
@@ -219,7 +218,6 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
- OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
