[PATCH v3 9/9] drm/ingenic: add some jz4780 specific features
From: Paul Boddie
The jz4780 has some features which need initialization
according to the vendor kernel.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 33ce3794aa126..f3b1b10bc079b 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -69,6 +69,10 @@ struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool has_alpha;
+ bool has_pcfg;
+ bool has_recover;
+ bool has_rgbc;
bool use_extended_hwdesc;
unsigned int hwdesc_size;
unsigned int max_width, max_height;
@@ -671,6 +675,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
}
+ if (priv->soc_info->has_recover)
+ cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN;
+
/* set use of the 8-word descriptor and OSD foreground usage. */
if (priv->soc_info->use_extended_hwdesc)
cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
@@ -1208,6 +1215,25 @@ static int ingenic_drm_bind(struct device *dev, bool
has_components)
if (soc_info->has_osd)
regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
+ if (soc_info->has_alpha)
+ regmap_set_bits(priv->map, JZ_REG_LCD_OSDC,
JZ_LCD_OSDC_ALPHAEN);
+
+ /* Magic values from the vendor kernel for the priority thresholds. */
+ if (soc_info->has_pcfg)
+ regmap_write(priv->map, JZ_REG_LCD_PCFG,
+JZ_LCD_PCFG_PRI_MODE |
+JZ_LCD_PCFG_HP_BST_16 |
+(511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) |
+(400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) |
+(256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET));
+
+ /* RGB output control may be superfluous. */
+ if (soc_info->has_rgbc)
+ regmap_write(priv->map, JZ_REG_LCD_RGBC,
+JZ_LCD_RGBC_RGB_FORMAT_ENABLE |
+JZ_LCD_RGBC_ODD_RGB |
+JZ_LCD_RGBC_EVEN_RGB);
+
mutex_init(>clk_mutex);
priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
@@ -1355,6 +1381,9 @@ static const struct jz_soc_info jz4740_soc_info = {
.needs_dev_clk = true,
.has_osd = false,
.map_noncoherent = false,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 800,
.max_height = 600,
@@ -1368,6 +1397,9 @@ static const struct jz_soc_info jz4725b_soc_info = {
.needs_dev_clk = false,
.has_osd = true,
.map_noncoherent = false,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 800,
.max_height = 600,
@@ -1382,6 +1414,9 @@ static const struct jz_soc_info jz4770_soc_info = {
.needs_dev_clk = false,
.has_osd = true,
.map_noncoherent = true,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 1280,
.max_height = 720,
@@ -1395,6 +1430,10 @@ static const struct jz_soc_info jz4770_soc_info = {
static const struct jz_soc_info jz4780_soc_info = {
.needs_dev_clk = true,
.has_osd = true,
+ .has_alpha = true,
+ .has_pcfg = true,
+ .has_recover = true,
+ .has_rgbc = true,
.use_extended_hwdesc = true,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc_ext),
.max_width = 4096,
--
2.31.1
[PATCH v3 7/9] MIPS: DTS: CI20: add HDMI setup
From: Paul Boddie
We need to hook up
* HDMI power regulator
* HDMI connector
* DDC pinmux
* HDMI and LCD endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index a688809beebca..9e87b1169dbdc 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -78,6 +78,28 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ hdmi_power: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
ir: ir {
compatible = "gpio-ir-receiver";
gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -506,6 +528,12 @@ pins_i2c4: i2c4 {
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -536,3 +564,39 @@ pins_mmc1: mmc1 {
bias-disable;
};
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_hdmi_ddc>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
2.31.1
[PATCH v3 6/9] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controllers
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++
1 file changed, 45 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 9e34f433b9b58..4cbc6a4db6cda 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ hdmi: hdmi@1018 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x1018 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+ clock-names = "isfr" , "iahb";
+
+ assigned-clocks = < JZ4780_CLK_HDMI>;
+ assigned-clock-rates = <2700>;
+
+ interrupt-parent = <>;
+ interrupts = <3>;
+
+ /* ddc-i2c-bus = <>; */
+
+ status = "disabled";
+ };
+
+ lcdc0: lcdc0@1305 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x1305 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
+ lcdc1: lcdc1@130a {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x130a 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD1PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc", "simple-mfd";
reg = <0x1341 0x1>;
--
2.31.1
[PATCH v3 8/9] MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780
Enable CONFIG options as modules. Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index ab7ebb0668340..9d47163011ab6 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -98,7 +98,14 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m +CONFIG_DRM=m +CONFIG_DRM_INGENIC=m +CONFIG_DRM_INGENIC_DW_HDMI=y # CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_HID is not set CONFIG_USB=y CONFIG_USB_STORAGE=y -- 2.31.1
[PATCH v3 2/9] drm/bridge: synopsis: Add mode_fixup and bridge timings support
From: Paul Boddie
The platform-specific configuration structure is augmented with
mode_fixup and timings members so that specialisations of the
Synopsys driver can introduce mode flags and bus flags.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++
include/drm/bridge/dw_hdmi.h | 5 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index e7c7c9b9c646f..d53bc557ef4ce 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2766,6 +2766,11 @@ static int dw_hdmi_bridge_atomic_check(struct drm_bridge
*bridge,
bridge_state->input_bus_cfg.format,
bridge_state->output_bus_cfg.format);
+ if (hdmi->plat_data->mode_fixup)
+ if (!hdmi->plat_data->mode_fixup(bridge, _state->mode,
+_state->adjusted_mode))
+ return -EINVAL;
+
return 0;
}
@@ -3364,6 +3369,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device
*pdev,
#ifdef CONFIG_OF
hdmi->bridge.of_node = pdev->dev.of_node;
#endif
+ if (plat_data->timings)
+ hdmi->bridge.timings = plat_data->timings;
memset(, 0, sizeof(pdevinfo));
pdevinfo.parent = dev;
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 6a5716655619b..677137445d534 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -8,6 +8,7 @@
#include
+struct drm_bridge;
struct drm_display_info;
struct drm_display_mode;
struct drm_encoder;
@@ -140,6 +141,10 @@ struct dw_hdmi_plat_data {
enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
const struct drm_display_info *info,
const struct drm_display_mode *mode);
+ bool (*mode_fixup)(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode);
+ const struct drm_bridge_timings *timings;
/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;
--
2.31.1
[PATCH v3 4/9] drm/ingenic: Add support for JZ4780 and HDMI output
From: Paul Boddie
Add support for the LCD controller present on JZ4780 SoCs.
This SoC uses 8-byte descriptors which extend the current
4-byte descriptors used for other Ingenic SoCs.
Also, add special handling for HDMI-A connectors.
For some reason, only the primary planes are working
properly. As soon as the overlay plane is enabled
things go south :P
Tested on MIPS Creator CI20 board.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 119 +++---
drivers/gpu/drm/ingenic/ingenic-drm.h | 42
2 files changed, 148 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index d9a793c314c1e..33ce3794aa126 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -6,6 +6,7 @@
#include "ingenic-drm.h"
+#include
#include
#include
#include
@@ -56,13 +57,24 @@ struct ingenic_dma_hwdescs {
u16 palette[256] __aligned(16);
};
+struct ingenic_dma_hwdesc_ext {
+ struct ingenic_dma_hwdesc base;
+ u32 offsize;
+ u32 pagewidth;
+ u32 cpos;
+ u32 dessize;
+} __packed;
+
struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool use_extended_hwdesc;
+ unsigned int hwdesc_size;
unsigned int max_width, max_height;
const u32 *formats_f0, *formats_f1;
unsigned int num_formats_f0, num_formats_f1;
+ unsigned int max_reg;
};
struct ingenic_drm {
@@ -118,12 +130,11 @@ static bool ingenic_drm_writeable_reg(struct device *dev,
unsigned int reg)
}
}
-static const struct regmap_config ingenic_drm_regmap_config = {
+static struct regmap_config ingenic_drm_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
- .max_register = JZ_REG_LCD_SIZE1,
.writeable_reg = ingenic_drm_writeable_reg,
};
@@ -582,7 +593,40 @@ static void ingenic_drm_plane_atomic_update(struct
drm_plane *plane,
hwdesc = >dma_hwdescs->hwdesc_f1;
hwdesc->addr = addr;
- hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
+ hwdesc->cmd = JZ_LCD_CMD_FRM_ENABLE | JZ_LCD_CMD_EOF_IRQ |
+ (width * height * cpp / 4);
+
+ if (priv->soc_info->use_extended_hwdesc) {
+ struct ingenic_dma_hwdesc_ext *hwdesc_ext;
+
+ /* Extended 8-byte descriptor */
+ hwdesc_ext = (struct ingenic_dma_hwdesc_ext *) hwdesc;
+ hwdesc_ext->cpos = 0;
+ hwdesc_ext->offsize = 0;
+ hwdesc_ext->pagewidth = 0;
+
+ switch (newstate->fb->format->format) {
+ case DRM_FORMAT_XRGB1555:
+ hwdesc_ext->cpos |= JZ_LCD_CPOS_RGB555;
+ fallthrough;
+ case DRM_FORMAT_RGB565:
+ hwdesc_ext->cpos |= JZ_LCD_CPOS_BPP_15_16;
+ break;
+ case DRM_FORMAT_XRGB:
+ hwdesc_ext->cpos |= JZ_LCD_CPOS_BPP_18_24;
+ break;
+ }
+ hwdesc_ext->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD |
+ (JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 <<
+JZ_LCD_CPOS_COEFFICIENT_OFFSET);
+
+ hwdesc_ext->dessize =
+ (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
+ FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK <<
+ JZ_LCD_DESSIZE_HEIGHT_OFFSET, height
- 1) |
+ FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK <<
+ JZ_LCD_DESSIZE_WIDTH_OFFSET, width -
1);
+ }
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
fourcc = newstate->fb->format->format;
@@ -612,8 +656,12 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
struct drm_display_mode *mode = _state->adjusted_mode;
struct drm_connector *conn = conn_state->connector;
struct drm_display_info *info = >display_info;
+ u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
unsigned int cfg, rgbcfg = 0;
+ if (info->num_bus_formats)
+ bus_format = info->bus_formats[0];
+
priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
if (priv->panel_is_sharp) {
@@ -623,6 +671,10 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE |
[PATCH v3 5/9] dt-bindings: display: Add ingenic-jz4780-hdmi DT Schema
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../bindings/display/ingenic-jz4780-hdmi.yaml | 82 +++
1 file changed, 82 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
new file mode 100644
index 0..a545ff8704ebd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: panel/panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: ingenic,jz4780-hdmi
+
+ reg:
+maxItems: 1
+description: the address & size of the LCD controller registers
+
+ reg-io-width:
+const: 4
+
+ interrupts:
+maxItems: 1
+description: Specifies the interrupt provided by parent
+
+ clocks:
+maxItems: 2
+description: Clock specifiers for isrf and iahb clocks
+
+ clock-names:
+items:
+ - const: isfr
+ - const: iahb
+
+ ddc-i2c-bus: true
+ ports: true
+
+required:
+- compatible
+- clocks
+- clock-names
+- ports
+- reg-io-width
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+hdmi: hdmi@1018 {
+compatible = "ingenic,jz4780-hdmi";
+reg = <0x1018 0x8000>;
+reg-io-width = <4>;
+ddc-i2c-bus = <>;
+interrupt-parent = <>;
+interrupts = <3>;
+clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+clock-names = "isfr", "iahb";
+
+ports {
+hdmi_in: port {
+#address-cells = <1>;
+#size-cells = <0>;
+hdmi_in_lcd: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_out_hdmi>;
+};
+};
+};
+};
+
+...
--
2.31.1
[PATCH v3 3/9] drm/ingenic: Add jz4780 Synopsys HDMI driver
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: Ezequiel Garcia
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 9 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 121 ++
3 files changed, 131 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
index 3b57f8be007c4..4c7d311fbefff 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -25,4 +25,13 @@ config DRM_INGENIC_IPU
The Image Processing Unit (IPU) will appear as a second primary plane.
+config DRM_INGENIC_DW_HDMI
+ bool "Ingenic specific support for Synopsys DW HDMI"
+ depends on MACH_JZ4780
+ select DRM_DW_HDMI
+ help
+ Choose this option to enable Synopsys DesignWare HDMI based driver.
+ If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
+ select this option..
+
endif
diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
index d313326bdddbb..3db9888a6c046 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
ingenic-drm-y = ingenic-drm-drv.o
ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o
+ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o
diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
new file mode 100644
index 0..61e7a57d7cec1
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019, 2020 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x }, { 0x21e1, 0x }, { 0x41e2, 0x
} } },
+ { 9250, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005
} } },
+ { 14850, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a
} } },
+ { 21600, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f
} } },
+ { ~0UL, { { 0x, 0x }, { 0x, 0x }, { 0x, 0x
} } }
+};
+
+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static bool
+ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+ adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+
+ return true;
+}
+
+static const struct drm_bridge_timings ingenic_dw_hdmi_timings = {
+ .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
+};
+
+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {
+ .mpll_cfg = ingenic_mpll_cfg,
+ .cur_ctr= ingenic_cur_ctr,
+ .phy_config = ingenic_phy_config,
+ .mode_valid = ingenic_dw_hdmi_mode_valid,
+ .mode_fixup = ingenic_dw_hdmi_mode_fixup,
+ .timings= _dw_hdmi_timings,
+};
+
+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of,
[PATCH v3 0/9] MIPS: JZ4780 and CI20 HDMI
This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU related issue in registration error path) - [patch 1/8] switched from mode_fixup to atomic_check (suggested by robert.f...@linaro.org) - the call to the dw-hdmi specialization is still called mode_fixup - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by p...@crapouillou.net) - factor out some non-HDMI features of the jz4780 into a separate patch - multiple fixes around max height - do not change regmap config but a copy on stack - define some constants - factor out fixing of drm_init error path for IPU into separate patch - use FIELD_PREP() - [patch 8/8] conversion to component framework dropped (suggested by laurent.pinch...@ideasonboard.com and p...@crapouillou.net) PATCH V2 2021-08-05 16:08:05: This series adds HDMI support for JZ4780 and CI20 board V2: - code and commit messages revisited for checkpatch warnings - rebased on v5.14-rc4 - include (failed, hence RFC 8/8) attempt to convert to component framework (was suggested by Paul Cercueil a while ago) H. Nikolaus Schaller (1): MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 Paul Boddie (7): drm/ingenic: fix drm_init error path if IPU was registered drm/bridge: synopsis: Add mode_fixup and bridge timings support drm/ingenic: Add jz4780 Synopsys HDMI driver drm/ingenic: Add support for JZ4780 and HDMI output MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controllers MIPS: DTS: CI20: add HDMI setup drm/ingenic: add some jz4780 specific features Sam Ravnborg (1): dt-bindings: display: Add ingenic-jz4780-hdmi DT Schema .../bindings/display/ingenic-jz4780-hdmi.yaml | 82 + arch/mips/boot/dts/ingenic/ci20.dts | 64 +++ arch/mips/boot/dts/ingenic/jz4780.dtsi| 45 + arch/mips/configs/ci20_defconfig | 7 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 + drivers/gpu/drm/ingenic/Kconfig | 9 + drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 169 -- drivers/gpu/drm/ingenic/ingenic-drm.h | 42 + drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 121 + include/drm/bridge/dw_hdmi.h | 5 + 11 files changed, 538 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c -- 2.31.1
[PATCH v3 1/9] drm/ingenic: fix drm_init error path if IPU was registered
From: Paul Boddie Code structure is in preparation to add hdmi unregistration in error case following the same pattern. Signed-off-by: Paul Boddie Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 5244f47634777..d9a793c314c1e 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -1355,7 +1355,16 @@ static int ingenic_drm_init(void) return err; } - return platform_driver_register(_drm_driver); + err = platform_driver_register(_drm_driver); + if (err) + goto err_ipu_unreg; + + return 0; + +err_ipu_unreg: + if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) + platform_driver_unregister(ingenic_ipu_driver_ptr); + return err; } module_init(ingenic_drm_init); -- 2.31.1
Re: [PATCH v2 3/8] drm/ingenic: Add support for JZ4780 and HDMI output
Hi Paul,
we have v3 ready and I'll post soon.
Before, here are some feedback to your comments.
> Am 05.08.2021 um 17:22 schrieb Paul Cercueil :
>
> Hi Nikolaus & Paul,
>> +
>> +if (priv->soc_info->hwdesc_size == sizeof(struct
>> ingenic_dma_hwdesc_ext)) {
>
> I'd prefer a boolean flag, e.g. "soc_info->use_extended_hwdesc"
Done.
>> +hwdesc_ext->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD |
>> +(3 <<
>> JZ_LCD_CPOS_COEFFICIENT_OFFSET);
>
> Where's that magic value '3' coming from?
We have defined a constant.
>
>> +
>> +hwdesc_ext->dessize =
>> +(0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
>> +(((height - 1) & JZ_LCD_DESSIZE_HEIGHT_MASK) <<
>> + JZ_LCD_DESSIZE_HEIGHT_OFFSET) |
>> +(((width - 1) & JZ_LCD_DESSIZE_WIDTH_MASK) <<
>> +JZ_LCD_DESSIZE_WIDTH_OFFSET);
>
> Use FIELD_PREP() from .
Changed.
>
>> +}
>> if (drm_atomic_crtc_needs_modeset(crtc_state)) {
>> fourcc = newstate->fb->format->format;
>> @@ -612,8 +657,12 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
>> drm_encoder *encoder,
>> struct drm_display_mode *mode = _state->adjusted_mode;
>> struct drm_connector *conn = conn_state->connector;
>> struct drm_display_info *info = >display_info;
>> +u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
>> unsigned int cfg, rgbcfg = 0;
>> +if (info->num_bus_formats)
>> +bus_format = info->bus_formats[0];
>> +
>
> That code is going to change really soon, as I have my own PR ready to
> convert the ingenic-drm driver to use a top-level bridge for bus format /
> flags negociation.
>
> The HDMI driver should therefore implement it as well; see for instance
> drivers/gpu/drm/bridge/ite-it66121.c for an example of how the bus format is
> negociated.
>
> I'll be sure to Cc you as soon as I send it upstream - should be just in a
> couple of days.
This one is still open.
>
>> priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
>> if (priv->panel_is_sharp) {
>> @@ -623,6 +672,13 @@ static void ingenic_drm_encoder_atomic_mode_set(struct
>> drm_encoder *encoder,
>> | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
>> }
>> +if (priv->soc_info->has_recover)
>> +cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN;
>
> Seems out of place. Does it not work without?
Yes. We have moved it into a separate patch which enables additional jz4780
features.
>
>> +
>> +/* CI20: set use of the 8-word descriptor and OSD foreground usage. */
>
> Not really CI20-specific though.
CI20 reference removed.
>
>> +switch (conn_state->connector->connector_type) {
>> +case DRM_MODE_CONNECTOR_TV:
>> +case DRM_MODE_CONNECTOR_HDMIA:
>> +return 0;
>> +}
>
> This switch should move after the check on "num_bus_formats".
> (I understand why you did it, but with proper bus format negociation this
> won't be needed).
Not yet included since it breaks initialization. I think your proposed series
will fix it.
>
>> +
>> if (info->num_bus_formats != 1)
>> return -EINVAL;
>> -drm->mode_config.max_height = 4095;
>> +drm->mode_config.max_height = soc_info->max_height;
>
> The drm->mode_config.max_height is different from soc_info->max_height; the
> former is the maximum framebuffer size, the latter is the maximum size that
> the SoC can display. The framebuffer can be bigger than what the SoC can
> display.
Change removed.
>
>> drm->mode_config.funcs = _drm_mode_config_funcs;
>> drm->mode_config.helper_private = _drm_mode_config_helpers;
>> @@ -934,6 +994,7 @@ static int ingenic_drm_bind(struct device *dev, bool
>> has_components)
>> return PTR_ERR(base);
>> }
>> +ingenic_drm_regmap_config.max_register = soc_info->max_reg;
>
> Avoid modifying a global variable; instead copy it to a local copy of
> ingenic_drm_regmap_config, and use this one in the regmap_init_mmio below.
modifies now a local copy on stack in v3.
>
>> priv->map = devm_regmap_init_mmio(dev, base,
>>_drm_regmap_config);
>> if (IS_ERR(priv->map)) {
>> @@ -966,7 +1027,6 @@ static int ingenic_drm_bind(struct device *dev, bool
>> has_components)
>> if (!priv->dma_hwdescs)
>> return -ENOMEM;
>> -
>
> Cosmetic change - not needed.
removed.
>
>> /* Configure DMA hwdesc for foreground0 plane */
>> dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys
>> + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0);
>> @@ -1147,7 +1207,26 @@ static int ingenic_drm_bind(struct device *dev, bool
>> has_components)
>> /* Enable OSD if available */
>> if (soc_info->has_osd)
>> -
Re: [PATCH v2 1/8] drm/bridge: synopsis: Add mode_fixup and bridge timings support
Hi Robert,
> Am 05.08.2021 um 16:32 schrieb Robert Foss :
>
> Hey Nikolaus,
>
> Thanks for submitting this series.
>
> On Thu, 5 Aug 2021 at 16:08, H. Nikolaus Schaller wrote:
>>
>> From: Paul Boddie
>>
>> static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
>>const struct drm_display_mode *orig_mode,
>>const struct drm_display_mode *mode)
>> @@ -2883,6 +2896,7 @@ static const struct drm_bridge_funcs
>> dw_hdmi_bridge_funcs = {
>>.atomic_disable = dw_hdmi_bridge_atomic_disable,
>>.mode_set = dw_hdmi_bridge_mode_set,
>>.mode_valid = dw_hdmi_bridge_mode_valid,
>> + .mode_fixup = dw_hdmi_bridge_mode_fixup,
>
> mode_fixup() has been deprecated[1] in favor of atomic_check(), care
> has to be taken when switching to atomic_check() as it has access to
> the full atomic commit.
>
> Looking at this driver, it's using mode_set as well, which should be fixed.
>
> [1]
> https://lore.kernel.org/dri-devel/20210722062246.2512666-8-...@ravnborg.org/
We have moved code from mode_fixup() to atomic_check().
Was not difficult.
v3 will come soon.
BR and thanks,
Nikolaus Schaller
[PATCH 2/2] drm/panel: Add support for Sharp LS060T1SX01 panel
Add driver to support Sharp LS06T1SX01 FullHD panel. The panel uses
nt35695 driver IC. For example this LCD module can be found in the
kwaek.ca Dragonboard Display Adapter Bundle.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-sharp-ls060t1sx01.c | 274 ++
3 files changed, 285 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4894913936e9..08f85a5ff738 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -451,6 +451,16 @@ config DRM_PANEL_SHARP_LS043T1LE01
Say Y here if you want to enable support for Sharp LS043T1LE01 qHD
(540x960) DSI panel as found on the Qualcomm APQ8074 Dragonboard
+config DRM_PANEL_SHARP_LS060T1SX01
+ tristate "Sharp LS060T1SX01 FullHD video mode panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for Sharp LS060T1SX01 6.0"
+ FullHD (1080x1920) DSI panel as found in Dragonboard Display Adapter
+ Bundle.
+
config DRM_PANEL_SITRONIX_ST7701
tristate "Sitronix ST7701 panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index cae4d976c069..7dd6bd755e13 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
+obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
diff --git a/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c
b/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c
new file mode 100644
index ..4fece00e6156
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2021 Linaro Ltd.
+// Generated with linux-mdss-dsi-panel-driver-generator from vendor device
tree:
+// Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+struct sharp_ls060 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct regulator *supply;
+ struct gpio_desc *reset_gpio;
+ bool prepared;
+};
+
+static inline struct sharp_ls060 *to_sharp_ls060(struct drm_panel *panel)
+{
+ return container_of(panel, struct sharp_ls060, panel);
+}
+
+#define dsi_dcs_write_seq(dsi, seq...) ({ \
+ static const u8 d[] = { seq }; \
+ \
+ mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
+ })
+
+static void sharp_ls060_reset(struct sharp_ls060 *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(1, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(1, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(1, 11000);
+}
+
+static int sharp_ls060_on(struct sharp_ls060 *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = >dev;
+ int ret;
+
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+ ret = dsi_dcs_write_seq(dsi, 0xbb, 0x13);
+ if (ret < 0) {
+ dev_err(dev, "Failed to send command: %d\n", ret);
+ return ret;
+ }
+
+ ret = dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START);
+ if (ret < 0) {
+ dev_err(dev, "Failed to send command: %d\n", ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
+ return ret;
+ }
+ msleep(120);
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set display on: %d\n", ret);
+ return ret;
+ }
+ msleep(50);
+
+ return 0;
+}
+
+static int sharp_ls060_off(struct sharp_ls060 *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = >dev;
+ int ret;
+
+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+ ret = mipi_dsi_dcs_set_display_off(dsi);
+
[PATCH 1/2] dt-bindings: add bindings for the Sharp LS060T1SX01 panel
Add devicetree bindings for the Sharp LS060T1SX01 6.0" FullHD panel
using NT35695 driver. This panel can be found i.e. in the Dragonboard
Display Adapter bundle.
Signed-off-by: Dmitry Baryshkov
---
.../display/panel/sharp,ls060t1sx01.yaml | 51 +++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/sharp,ls060t1sx01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/sharp,ls060t1sx01.yaml
b/Documentation/devicetree/bindings/display/panel/sharp,ls060t1sx01.yaml
new file mode 100644
index ..e749f20d34aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/sharp,ls060t1sx01.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/sharp,ls043t1le01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sharp Microelectronics 6.0" FullHD TFT LCD panel
+
+maintainers:
+ - Dmitry Baryskov
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: sharp,ls060t1sx01
+
+ reg: true
+ backlight: true
+ reset-gpios: true
+ port: true
+
+ avdd-supply:
+description: handle of the regulator that provides the supply voltage
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+panel@0 {
+compatible = "sharp,ls060t1sx01";
+reg = <0>;
+avdd-supply = <_l22>;
+backlight = <>;
+reset-gpios = <_gpios 25 GPIO_ACTIVE_LOW>;
+};
+};
+
+...
--
2.30.2
Re: [PATCH v2 3/5] drm/atomic-helper: Set fence deadline for vblank
Hi Rob, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.14-rc4 next-20210806] [cannot apply to drm-intel/for-linux-next drm/drm-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Rob-Clark/dma-fence-Deadline-awareness/20210808-023531 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: microblaze-randconfig-r033-20210808 (attached as .config) compiler: microblaze-linux-gcc (GCC) 10.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/237392f7f3f215c77118b9bd985381ca70b7838a git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Rob-Clark/dma-fence-Deadline-awareness/20210808-023531 git checkout 237392f7f3f215c77118b9bd985381ca70b7838a # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=microblaze If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>, old ones prefixed by <<): >> ERROR: modpost: "drm_crtc_next_vblank_time" >> [drivers/gpu/drm/drm_kms_helper.ko] undefined! --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip
Re: [PATCH] drm/i915: Release ctx->syncobj on final put, not on ctx close
On August 6, 2021 15:18:59 Daniel Vetter wrote:
gem context refcounting is another exercise in least locking design it
seems, where most things get destroyed upon context closure (which can
race with anything really). Only the actual memory allocation and the
locks survive while holding a reference.
This tripped up Jason when reimplementing the single timeline feature
in
commit 00dae4d3d35d4f526929633b76e00b0ab4d3970d
Author: Jason Ekstrand
Date: Thu Jul 8 10:48:12 2021 -0500
drm/i915: Implement SINGLE_TIMELINE with a syncobj (v4)
We could fix the bug by holding ctx->mutex, but it's cleaner to just
What bug is this fixing, exactly?
--Jason
make the context object actually invariant over its _entire_ lifetime.
Signed-off-by: Daniel Vetter
Fixes: 00dae4d3d35d ("drm/i915: Implement SINGLE_TIMELINE with a syncobj (v4)")
Cc: Jason Ekstrand
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Matthew Brost
Cc: Matthew Auld
Cc: Maarten Lankhorst
Cc: "Thomas Hellström"
Cc: Lionel Landwerlin
Cc: Dave Airlie
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 754b9b8d4981..93ba0197d70a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -940,6 +940,9 @@ void i915_gem_context_release(struct kref *ref)
trace_i915_context_free(ctx);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ if (ctx->syncobj)
+ drm_syncobj_put(ctx->syncobj);
+
mutex_destroy(>engines_mutex);
mutex_destroy(>lut_mutex);
@@ -1159,9 +1162,6 @@ static void context_close(struct i915_gem_context *ctx)
if (vm)
i915_vm_close(vm);
- if (ctx->syncobj)
- drm_syncobj_put(ctx->syncobj);
-
ctx->file_priv = ERR_PTR(-EBADF);
/*
--
2.32.0
[PATCH] drm/amdgpu: fix kernel-doc warnings on non-kernel-doc comments
Don't use "begin kernel-doc notation" (/**) for comments that are
not kernel-doc. This eliminates warnings reported by the 0day bot.
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:89: warning: This comment starts with
'/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
* This shader is used to clear VGPRS and LDS, and also write the input
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:209: warning: This comment starts with
'/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
* The below shaders are used to clear SGPRS, and also write the input
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:301: warning: This comment starts with
'/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
* This shader is used to clear the uninitiated sgprs after the above
Fixes: 0e0036c7d13b ("drm/amdgpu: fix no full coverage issue for gprs
initialization")
Signed-off-by: Randy Dunlap
Reported-by: kernel test robot
Cc: Alex Deucher
Cc: Christian König
Cc: "Pan, Xinhui"
Cc: Dennis Li
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- linux-next-20210806.orig/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ linux-next-20210806/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -85,7 +85,7 @@ static const struct soc15_reg_golden gol
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20),
};
-/**
+/*
* This shader is used to clear VGPRS and LDS, and also write the input
* pattern into the write back buffer, which will be used by driver to
* check whether all SIMDs have been covered.
@@ -206,7 +206,7 @@ const struct soc15_reg_entry vgpr_init_r
{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x
},
};
-/**
+/*
* The below shaders are used to clear SGPRS, and also write the input
* pattern into the write back buffer. The first two dispatch should be
* scheduled simultaneously which make sure that all SGPRS could be
@@ -302,7 +302,7 @@ const struct soc15_reg_entry sgpr96_init
{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x
},
};
-/**
+/*
* This shader is used to clear the uninitiated sgprs after the above
* two dispatches, because of hardware feature, dispath 0 couldn't clear
* top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs
Re: [PATCH v2 1/2] drm/panel: Add DT bindings for Samsung S6D27A1 display panel
On Sat, Aug 7, 2021 at 3:31 PM Markuss Broks wrote: > This adds device-tree bindings for the Samsung S6D27A1 RGB > DPI display panel. > > Signed-off-by: Markuss Broks > > v1 -> v2: > changed additionalProperties to unevaluatedProperties; > added vci-supply and vccio-supply as required; These bindings look good to me: Reviewed-by: Linus Walleij Will give DT reviewers some slack before applying the patches. Yours, Linus Walleij
Re: [PATCH v2 2/2] drm/panel: s6d27a1: Add driver for Samsung S6D27A1 display panel
Hi Markuss, this is looking really good, the following is just nitty gritty details I could fix while applying, we're mostly waiting for DT review now. On Sat, Aug 7, 2021 at 3:31 PM Markuss Broks wrote: > + /* > +* Exit sleep mode and initialize display - some hammering is > +* necessary. > +*/ > + mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); > + mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); Check if this hammering is really necessary on s6d27a1, on Widechips this is just a bug, what happens if you put just one of them? > + msleep(50); This should be msleep(120) on s6d27a1 (according to board-codina-mcde.c) Yours, Linus Walleij
Re: [PATCH] drm/msm: Disable frequency clamping on a630
On Sat, Aug 7, 2021 at 12:21 PM Caleb Connolly
wrote:
>
> Hi Rob, Akhil,
>
> On 29/07/2021 21:53, Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
> > wrote:
> >>
> >>
> >>
> >> On 29/07/2021 21:24, Rob Clark wrote:
> >>> On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
> >>> wrote:
>
> Hi Rob,
>
> I've done some more testing! It looks like before that patch ("drm/msm:
> Devfreq tuning") the GPU would never get above
> the second frequency in the OPP table (342MHz) (at least, not in
> glxgears). With the patch applied it would more
> aggressively jump up to the max frequency which seems to be unstable at
> the default regulator voltages.
> >>>
> >>> *ohh*, yeah, ok, that would explain it
> >>>
> Hacking the pm8005 s1 regulator (which provides VDD_GFX) up to 0.988v
> (instead of the stock 0.516v) makes the GPU stable
> at the higher frequencies.
>
> Applying this patch reverts the behaviour, and the GPU never goes above
> 342MHz in glxgears, losing ~30% performance in
> glxgear.
>
> I think (?) that enabling CPR support would be the proper solution to
> this - that would ensure that the regulators run
> at the voltage the hardware needs to be stable.
>
> Is hacking the voltage higher (although ideally not quite that high) an
> acceptable short term solution until we have
> CPR? Or would it be safer to just not make use of the higher frequencies
> on a630 for now?
>
> >>>
> >>> tbh, I'm not sure about the regulator stuff and CPR.. Bjorn is already
> >>> on CC and I added sboyd, maybe one of them knows better.
> >>>
> >>> In the short term, removing the higher problematic OPPs from dts might
> >>> be a better option than this patch (which I'm dropping), since there
> >>> is nothing stopping other workloads from hitting higher OPPs.
> >> Oh yeah that sounds like a more sensible workaround than mine .
> >>>
> >>> I'm slightly curious why I didn't have problems at higher OPPs on my
> >>> c630 laptop (sdm850)
> >> Perhaps you won the sillicon lottery - iirc sdm850 is binned for higher
> >> clocks as is out of the factory.
> >>
> >> Would it be best to drop the OPPs for all devices? Or just those affected?
> >> I guess it's possible another c630 might
> >> crash where yours doesn't?
> >
> > I've not heard any reports of similar issues from the handful of other
> > folks with c630's on #aarch64-laptops.. but I can't really say if that
> > is luck or not.
> It looks like this affects at least the OnePlus 6 and PocoPhone F1, I've done
> some more poking and the following diff
> seems to fix the stability issues completely, it seems the delay is required
> to let the update propagate.
>
> This doesn't feel like the right fix, but hopefully it's enough to come up
> with a better solution than disabling the new
> devfreq behaviour on a630.
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index d7cec7f0dde0..69e2a5e84dae 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -139,6 +139,10 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
> dev_pm_opp *opp)
> return;
> }
>
> + dev_pm_opp_set_opp(>pdev->dev, opp);
> +
> + usleep_range(300, 500);
> +
Hmm, this is going to be in the critical path on idle -> active
transition (ie. think response time to user-input).. so we defn don't
want to do this unconditionally..
If I understand the problem, we just want to limit how far we jump the
gpu freq in one go.. maybe deleting the lowest (and perhaps highest)
OPP would accomplish that? Could that be done in the board(s)'s
toplevel dts files?
BR,
-R
> gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
>
> gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
> @@ -158,7 +162,6 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
> dev_pm_opp *opp)
> if (ret)
> dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
>
> - dev_pm_opp_set_opp(>pdev->dev, opp);
> pm_runtime_put(gmu->dev);
> }
> >
> > Maybe just remove it for affected devices? But I'll defer to Bjorn.
> >
> > BR,
> > -R
> >
>
> --
> Kind Regards,
> Caleb (they/them)
Re: [PATCH] drm/msm: Disable frequency clamping on a630
Hi Rob, Akhil,
On 29/07/2021 21:53, Rob Clark wrote:
On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
wrote:
On 29/07/2021 21:24, Rob Clark wrote:
On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
wrote:
Hi Rob,
I've done some more testing! It looks like before that patch ("drm/msm: Devfreq
tuning") the GPU would never get above
the second frequency in the OPP table (342MHz) (at least, not in glxgears).
With the patch applied it would more
aggressively jump up to the max frequency which seems to be unstable at the
default regulator voltages.
*ohh*, yeah, ok, that would explain it
Hacking the pm8005 s1 regulator (which provides VDD_GFX) up to 0.988v (instead
of the stock 0.516v) makes the GPU stable
at the higher frequencies.
Applying this patch reverts the behaviour, and the GPU never goes above 342MHz
in glxgears, losing ~30% performance in
glxgear.
I think (?) that enabling CPR support would be the proper solution to this -
that would ensure that the regulators run
at the voltage the hardware needs to be stable.
Is hacking the voltage higher (although ideally not quite that high) an
acceptable short term solution until we have
CPR? Or would it be safer to just not make use of the higher frequencies on
a630 for now?
tbh, I'm not sure about the regulator stuff and CPR.. Bjorn is already
on CC and I added sboyd, maybe one of them knows better.
In the short term, removing the higher problematic OPPs from dts might
be a better option than this patch (which I'm dropping), since there
is nothing stopping other workloads from hitting higher OPPs.
Oh yeah that sounds like a more sensible workaround than mine .
I'm slightly curious why I didn't have problems at higher OPPs on my
c630 laptop (sdm850)
Perhaps you won the sillicon lottery - iirc sdm850 is binned for higher clocks
as is out of the factory.
Would it be best to drop the OPPs for all devices? Or just those affected? I
guess it's possible another c630 might
crash where yours doesn't?
I've not heard any reports of similar issues from the handful of other
folks with c630's on #aarch64-laptops.. but I can't really say if that
is luck or not.
It looks like this affects at least the OnePlus 6 and PocoPhone F1, I've done some more poking and the following diff
seems to fix the stability issues completely, it seems the delay is required to let the update propagate.
This doesn't feel like the right fix, but hopefully it's enough to come up with a better solution than disabling the new
devfreq behaviour on a630.
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index d7cec7f0dde0..69e2a5e84dae 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -139,6 +139,10 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
dev_pm_opp *opp)
return;
}
+ dev_pm_opp_set_opp(>pdev->dev, opp);
+
+ usleep_range(300, 500);
+
gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
@@ -158,7 +162,6 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct
dev_pm_opp *opp)
if (ret)
dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
- dev_pm_opp_set_opp(>pdev->dev, opp);
pm_runtime_put(gmu->dev);
}
Maybe just remove it for affected devices? But I'll defer to Bjorn.
BR,
-R
--
Kind Regards,
Caleb (they/them)
Re: [PATCH v2 07/14] drm/msm: Convert to Linux IRQ interfaces
On Sat, Aug 7, 2021 at 11:40 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 07.08.21 um 19:08 schrieb Rob Clark:
> > On Tue, Aug 3, 2021 at 2:37 AM Dmitry Baryshkov
> > wrote:
> >>
> >> On 03/08/2021 12:06, Thomas Zimmermann wrote:
> >>> Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
> >>> IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
> >>> don't benefit from using it.
> >>>
> >>> DRM IRQ callbacks are now being called directly or inlined.
> >>>
> >>> Signed-off-by: Thomas Zimmermann
> >>
> >> Reviewed-by: Dmitry Baryshkov
> >>
> >> Rob should probably also give his blessing on this patch though.
> >>
> >
> > I've pushed this to msm-next-staging, but if Thomas would prefer to
> > merge the series together then I can drop it (in which case a-b for
> > this patch)
>
> Yes, please. I'd prefer to merge the whole patchset at once through
> drm-misc-next.
Ok, I've dropped from msm-next-staging.. for merging via drm-msm-next:
Acked-by: Rob Clark
>
> Best regards
> Thomas
>
> >
> > BR,
> > -R
> >
> >>> ---
> >>>drivers/gpu/drm/msm/msm_drv.c | 113 --
> >>>drivers/gpu/drm/msm/msm_kms.h | 2 +-
> >>>2 files changed, 69 insertions(+), 46 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> >>> index 1594ae39d54f..a332b09a5a11 100644
> >>> --- a/drivers/gpu/drm/msm/msm_drv.c
> >>> +++ b/drivers/gpu/drm/msm/msm_drv.c
> >>> @@ -14,7 +14,6 @@
> >>>#include
> >>>#include
> >>>#include
> >>> -#include
> >>>#include
> >>>#include
> >>>#include
> >>> @@ -201,6 +200,71 @@ void msm_rmw(void __iomem *addr, u32 mask, u32 or)
> >>>msm_writel(val | or, addr);
> >>>}
> >>>
> >>> +static irqreturn_t msm_irq(int irq, void *arg)
> >>> +{
> >>> + struct drm_device *dev = arg;
> >>> + struct msm_drm_private *priv = dev->dev_private;
> >>> + struct msm_kms *kms = priv->kms;
> >>> +
> >>> + BUG_ON(!kms);
> >>> +
> >>> + return kms->funcs->irq(kms);
> >>> +}
> >>> +
> >>> +static void msm_irq_preinstall(struct drm_device *dev)
> >>> +{
> >>> + struct msm_drm_private *priv = dev->dev_private;
> >>> + struct msm_kms *kms = priv->kms;
> >>> +
> >>> + BUG_ON(!kms);
> >>> +
> >>> + kms->funcs->irq_preinstall(kms);
> >>> +}
> >>> +
> >>> +static int msm_irq_postinstall(struct drm_device *dev)
> >>> +{
> >>> + struct msm_drm_private *priv = dev->dev_private;
> >>> + struct msm_kms *kms = priv->kms;
> >>> +
> >>> + BUG_ON(!kms);
> >>> +
> >>> + if (kms->funcs->irq_postinstall)
> >>> + return kms->funcs->irq_postinstall(kms);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int msm_irq_install(struct drm_device *dev, unsigned int irq)
> >>> +{
> >>> + int ret;
> >>> +
> >>> + if (irq == IRQ_NOTCONNECTED)
> >>> + return -ENOTCONN;
> >>> +
> >>> + msm_irq_preinstall(dev);
> >>> +
> >>> + ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + ret = msm_irq_postinstall(dev);
> >>> + if (ret) {
> >>> + free_irq(irq, dev);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void msm_irq_uninstall(struct drm_device *dev)
> >>> +{
> >>> + struct msm_drm_private *priv = dev->dev_private;
> >>> + struct msm_kms *kms = priv->kms;
> >>> +
> >>> + kms->funcs->irq_uninstall(kms);
> >>> + free_irq(kms->irq, dev);
> >>> +}
> >>> +
> >>>struct msm_vblank_work {
> >>>struct work_struct work;
> >>>int crtc_id;
> >>> @@ -265,7 +329,7 @@ static int msm_drm_uninit(struct device *dev)
> >>>}
> >>>
> >>>/* We must cancel and cleanup any pending vblank enable/disable
> >>> - * work before drm_irq_uninstall() to avoid work re-enabling an
> >>> + * work before msm_irq_uninstall() to avoid work re-enabling an
> >>> * irq after uninstall has disabled it.
> >>> */
> >>>
> >>> @@ -294,7 +358,7 @@ static int msm_drm_uninit(struct device *dev)
> >>>drm_mode_config_cleanup(ddev);
> >>>
> >>>pm_runtime_get_sync(dev);
> >>> - drm_irq_uninstall(ddev);
> >>> + msm_irq_uninstall(ddev);
> >>>pm_runtime_put_sync(dev);
> >>>
> >>>if (kms && kms->funcs)
> >>> @@ -553,7 +617,7 @@ static int msm_drm_init(struct device *dev, const
> >>> struct drm_driver *drv)
> >>>
> >>>if (kms) {
> >>>pm_runtime_get_sync(dev);
> >>> - ret = drm_irq_install(ddev, kms->irq);
> >>> + ret = msm_irq_install(ddev, kms->irq);
> >>>pm_runtime_put_sync(dev);
> >>>if (ret < 0) {
> >>>DRM_DEV_ERROR(dev, "failed to install IRQ
> >>> handler\n");
> >>> @@ -662,43 +726,6 @@ static void msm_postclose(struct drm_device *dev,
> >>> struct drm_file *file)
> >>>
Re: [PATCH v2 07/14] drm/msm: Convert to Linux IRQ interfaces
Hi
Am 07.08.21 um 19:08 schrieb Rob Clark:
On Tue, Aug 3, 2021 at 2:37 AM Dmitry Baryshkov
wrote:
On 03/08/2021 12:06, Thomas Zimmermann wrote:
Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
don't benefit from using it.
DRM IRQ callbacks are now being called directly or inlined.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Dmitry Baryshkov
Rob should probably also give his blessing on this patch though.
I've pushed this to msm-next-staging, but if Thomas would prefer to
merge the series together then I can drop it (in which case a-b for
this patch)
Yes, please. I'd prefer to merge the whole patchset at once through
drm-misc-next.
Best regards
Thomas
BR,
-R
---
drivers/gpu/drm/msm/msm_drv.c | 113 --
drivers/gpu/drm/msm/msm_kms.h | 2 +-
2 files changed, 69 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 1594ae39d54f..a332b09a5a11 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -14,7 +14,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -201,6 +200,71 @@ void msm_rmw(void __iomem *addr, u32 mask, u32 or)
msm_writel(val | or, addr);
}
+static irqreturn_t msm_irq(int irq, void *arg)
+{
+ struct drm_device *dev = arg;
+ struct msm_drm_private *priv = dev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ BUG_ON(!kms);
+
+ return kms->funcs->irq(kms);
+}
+
+static void msm_irq_preinstall(struct drm_device *dev)
+{
+ struct msm_drm_private *priv = dev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ BUG_ON(!kms);
+
+ kms->funcs->irq_preinstall(kms);
+}
+
+static int msm_irq_postinstall(struct drm_device *dev)
+{
+ struct msm_drm_private *priv = dev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ BUG_ON(!kms);
+
+ if (kms->funcs->irq_postinstall)
+ return kms->funcs->irq_postinstall(kms);
+
+ return 0;
+}
+
+static int msm_irq_install(struct drm_device *dev, unsigned int irq)
+{
+ int ret;
+
+ if (irq == IRQ_NOTCONNECTED)
+ return -ENOTCONN;
+
+ msm_irq_preinstall(dev);
+
+ ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
+ if (ret)
+ return ret;
+
+ ret = msm_irq_postinstall(dev);
+ if (ret) {
+ free_irq(irq, dev);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void msm_irq_uninstall(struct drm_device *dev)
+{
+ struct msm_drm_private *priv = dev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ kms->funcs->irq_uninstall(kms);
+ free_irq(kms->irq, dev);
+}
+
struct msm_vblank_work {
struct work_struct work;
int crtc_id;
@@ -265,7 +329,7 @@ static int msm_drm_uninit(struct device *dev)
}
/* We must cancel and cleanup any pending vblank enable/disable
- * work before drm_irq_uninstall() to avoid work re-enabling an
+ * work before msm_irq_uninstall() to avoid work re-enabling an
* irq after uninstall has disabled it.
*/
@@ -294,7 +358,7 @@ static int msm_drm_uninit(struct device *dev)
drm_mode_config_cleanup(ddev);
pm_runtime_get_sync(dev);
- drm_irq_uninstall(ddev);
+ msm_irq_uninstall(ddev);
pm_runtime_put_sync(dev);
if (kms && kms->funcs)
@@ -553,7 +617,7 @@ static int msm_drm_init(struct device *dev, const struct
drm_driver *drv)
if (kms) {
pm_runtime_get_sync(dev);
- ret = drm_irq_install(ddev, kms->irq);
+ ret = msm_irq_install(ddev, kms->irq);
pm_runtime_put_sync(dev);
if (ret < 0) {
DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
@@ -662,43 +726,6 @@ static void msm_postclose(struct drm_device *dev, struct
drm_file *file)
context_close(ctx);
}
-static irqreturn_t msm_irq(int irq, void *arg)
-{
- struct drm_device *dev = arg;
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_kms *kms = priv->kms;
- BUG_ON(!kms);
- return kms->funcs->irq(kms);
-}
-
-static void msm_irq_preinstall(struct drm_device *dev)
-{
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_kms *kms = priv->kms;
- BUG_ON(!kms);
- kms->funcs->irq_preinstall(kms);
-}
-
-static int msm_irq_postinstall(struct drm_device *dev)
-{
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_kms *kms = priv->kms;
- BUG_ON(!kms);
-
- if (kms->funcs->irq_postinstall)
- return kms->funcs->irq_postinstall(kms);
-
- return 0;
-}
-
-static void msm_irq_uninstall(struct drm_device *dev)
-{
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_kms *kms = priv->kms;
- BUG_ON(!kms);
- kms->funcs->irq_uninstall(kms);
-}
-
int
[PATCH v2 5/5] drm/msm: Add deadline based boost support
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 76 +++
drivers/gpu/drm/msm/msm_fence.h | 20 +++
drivers/gpu/drm/msm/msm_gpu.h | 1 +
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++
4 files changed, 117 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
index f2cece542c3f..67c2a96e1c85 100644
--- a/drivers/gpu/drm/msm/msm_fence.c
+++ b/drivers/gpu/drm/msm/msm_fence.c
@@ -8,6 +8,37 @@
#include "msm_drv.h"
#include "msm_fence.h"
+#include "msm_gpu.h"
+
+static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t
fence);
+
+static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx)
+{
+ struct msm_drm_private *priv = fctx->dev->dev_private;
+ return priv->gpu;
+}
+
+static enum hrtimer_restart deadline_timer(struct hrtimer *t)
+{
+ struct msm_fence_context *fctx = container_of(t,
+ struct msm_fence_context, deadline_timer);
+
+ kthread_queue_work(fctx2gpu(fctx)->worker, >deadline_work);
+
+ return HRTIMER_NORESTART;
+}
+
+static void deadline_work(struct kthread_work *work)
+{
+ struct msm_fence_context *fctx = container_of(work,
+ struct msm_fence_context, deadline_work);
+
+ /* If deadline fence has already passed, nothing to do: */
+ if (fence_completed(fctx, fctx->next_deadline_fence))
+ return;
+
+ msm_devfreq_boost(fctx2gpu(fctx), 2);
+}
struct msm_fence_context *
@@ -26,6 +57,13 @@ msm_fence_context_alloc(struct drm_device *dev, volatile
uint32_t *fenceptr,
fctx->fenceptr = fenceptr;
spin_lock_init(>spinlock);
+ hrtimer_init(>deadline_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+ fctx->deadline_timer.function = deadline_timer;
+
+ kthread_init_work(>deadline_work, deadline_work);
+
+ fctx->next_deadline = ktime_get();
+
return fctx;
}
@@ -49,6 +87,8 @@ void msm_update_fence(struct msm_fence_context *fctx,
uint32_t fence)
{
spin_lock(>spinlock);
fctx->completed_fence = max(fence, fctx->completed_fence);
+ if (fence_completed(fctx, fctx->next_deadline_fence))
+ hrtimer_cancel(>deadline_timer);
spin_unlock(>spinlock);
}
@@ -79,10 +119,46 @@ static bool msm_fence_signaled(struct dma_fence *fence)
return fence_completed(f->fctx, f->base.seqno);
}
+static void msm_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
+{
+ struct msm_fence *f = to_msm_fence(fence);
+ struct msm_fence_context *fctx = f->fctx;
+ unsigned long flags;
+ ktime_t now;
+
+ spin_lock_irqsave(>spinlock, flags);
+ now = ktime_get();
+
+ if (ktime_after(now, fctx->next_deadline) ||
+ ktime_before(deadline, fctx->next_deadline)) {
+ fctx->next_deadline = deadline;
+ fctx->next_deadline_fence =
+ max(fctx->next_deadline_fence, (uint32_t)fence->seqno);
+
+ /*
+* Set timer to trigger boost 3ms before deadline, or
+* if we are already less than 3ms before the deadline
+* schedule boost work immediately.
+*/
+ deadline = ktime_sub(deadline, ms_to_ktime(3));
+
+ if (ktime_after(now, deadline)) {
+ kthread_queue_work(fctx2gpu(fctx)->worker,
+ >deadline_work);
+ } else {
+ hrtimer_start(>deadline_timer, deadline,
+ HRTIMER_MODE_ABS);
+ }
+ }
+
+ spin_unlock_irqrestore(>spinlock, flags);
+}
+
static const struct dma_fence_ops msm_fence_ops = {
.get_driver_name = msm_fence_get_driver_name,
.get_timeline_name = msm_fence_get_timeline_name,
.signaled = msm_fence_signaled,
+ .set_deadline = msm_fence_set_deadline,
};
struct dma_fence *
diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h
index 4783db528bcc..d34e853c555a 100644
--- a/drivers/gpu/drm/msm/msm_fence.h
+++ b/drivers/gpu/drm/msm/msm_fence.h
@@ -50,6 +50,26 @@ struct msm_fence_context {
volatile uint32_t *fenceptr;
spinlock_t spinlock;
+
+ /*
+* TODO this doesn't really deal with multiple deadlines, like
+* if userspace got multiple frames ahead.. OTOH atomic updates
+* don't queue, so maybe that is ok
+*/
+
+ /** next_deadline: Time of next deadline */
+ ktime_t next_deadline;
+
+ /**
+* next_deadline_fence:
+*
+* Fence value for next pending deadline. The deadline timer is
+* canceled when this fence is signaled.
+*/
+ uint32_t next_deadline_fence;
+
+ struct hrtimer deadline_timer;
+ struct kthread_work deadline_work;
};
struct
[PATCH v2 4/5] drm/scheduler: Add fence deadline support
From: Rob Clark
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/scheduler/sched_fence.c | 25 +
drivers/gpu/drm/scheduler/sched_main.c | 3 +++
include/drm/gpu_scheduler.h | 6 ++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/sched_fence.c
b/drivers/gpu/drm/scheduler/sched_fence.c
index 69de2c76731f..f389dca44185 100644
--- a/drivers/gpu/drm/scheduler/sched_fence.c
+++ b/drivers/gpu/drm/scheduler/sched_fence.c
@@ -128,6 +128,30 @@ static void drm_sched_fence_release_finished(struct
dma_fence *f)
dma_fence_put(>scheduled);
}
+static void drm_sched_fence_set_deadline_finished(struct dma_fence *f,
+ ktime_t deadline)
+{
+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
+ unsigned long flags;
+
+ spin_lock_irqsave(>lock, flags);
+
+ /* If we already have an earlier deadline, keep it: */
+ if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, >flags) &&
+ ktime_before(fence->deadline, deadline)) {
+ spin_unlock_irqrestore(>lock, flags);
+ return;
+ }
+
+ fence->deadline = deadline;
+ set_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, >flags);
+
+ spin_unlock_irqrestore(>lock, flags);
+
+ if (fence->parent)
+ dma_fence_set_deadline(fence->parent, deadline);
+}
+
static const struct dma_fence_ops drm_sched_fence_ops_scheduled = {
.get_driver_name = drm_sched_fence_get_driver_name,
.get_timeline_name = drm_sched_fence_get_timeline_name,
@@ -138,6 +162,7 @@ static const struct dma_fence_ops
drm_sched_fence_ops_finished = {
.get_driver_name = drm_sched_fence_get_driver_name,
.get_timeline_name = drm_sched_fence_get_timeline_name,
.release = drm_sched_fence_release_finished,
+ .set_deadline = drm_sched_fence_set_deadline_finished,
};
struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index a2a953693b45..3ab0900d3596 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -818,6 +818,9 @@ static int drm_sched_main(void *param)
if (!IS_ERR_OR_NULL(fence)) {
s_fence->parent = dma_fence_get(fence);
+ if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT,
+_fence->finished.flags))
+ dma_fence_set_deadline(fence,
s_fence->deadline);
r = dma_fence_add_callback(fence, _job->cb,
drm_sched_job_done_cb);
if (r == -ENOENT)
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index d18af49fd009..0f08ade614ae 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -144,6 +144,12 @@ struct drm_sched_fence {
*/
struct dma_fencefinished;
+ /**
+* @deadline: deadline set on _sched_fence.finished which
+* potentially needs to be propagated to _sched_fence.parent
+*/
+ ktime_t deadline;
+
/**
* @parent: the fence returned by _sched_backend_ops.run_job
* when scheduling the job on hardware. We signal the
--
2.31.1
[PATCH v2 3/5] drm/atomic-helper: Set fence deadline for vblank
From: Rob Clark
For an atomic commit updating a single CRTC (ie. a pageflip) calculate
the next vblank time, and inform the fence(s) of that deadline.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_atomic_helper.c | 36 +
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index bc3487964fb5..7caa2c3cc304 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1406,6 +1406,40 @@ void drm_atomic_helper_commit_modeset_enables(struct
drm_device *dev,
}
EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables);
+/*
+ * For atomic updates which touch just a single CRTC, calculate the time of the
+ * next vblank, and inform all the fences of the of the deadline.
+ */
+static void set_fence_deadline(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc, *wait_crtc = NULL;
+ struct drm_crtc_state *new_crtc_state;
+ struct drm_plane *plane;
+ struct drm_plane_state *new_plane_state;
+ ktime_t vbltime;
+ int i;
+
+ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
+ if (wait_crtc)
+ return;
+ wait_crtc = crtc;
+ }
+
+ /* If no CRTCs updated, then nothing to do: */
+ if (!wait_crtc)
+ return;
+
+ if (drm_crtc_next_vblank_time(wait_crtc, ))
+ return;
+
+ for_each_new_plane_in_state (state, plane, new_plane_state, i) {
+ if (!new_plane_state->fence)
+ continue;
+ dma_fence_set_deadline(new_plane_state->fence, vbltime);
+ }
+}
+
/**
* drm_atomic_helper_wait_for_fences - wait for fences stashed in plane state
* @dev: DRM device
@@ -1435,6 +1469,8 @@ int drm_atomic_helper_wait_for_fences(struct drm_device
*dev,
struct drm_plane_state *new_plane_state;
int i, ret;
+ set_fence_deadline(dev, state);
+
for_each_new_plane_in_state(state, plane, new_plane_state, i) {
if (!new_plane_state->fence)
continue;
--
2.31.1
[PATCH v2 2/5] drm/vblank: Add helper to get next vblank time
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_vblank.c | 31 +++
include/drm/drm_vblank.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 3417e1ac7918..88c824c294dc 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -980,6 +980,37 @@ u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
}
EXPORT_SYMBOL(drm_crtc_vblank_count_and_time);
+/**
+ * drm_crtc_next_vblank_time - calculate the time of the next vblank
+ * @crtc: the crtc for which to calculate next vblank time
+ * @vblanktime: pointer to time to receive the next vblank timestamp.
+ *
+ * Calculate the expected time of the next vblank based on time of previous
+ * vblank and frame duration
+ */
+int drm_crtc_next_vblank_time(struct drm_crtc *crtc, ktime_t *vblanktime)
+{
+ unsigned int pipe = drm_crtc_index(crtc);
+ struct drm_vblank_crtc *vblank = >dev->vblank[pipe];
+ u64 count;
+
+ if (!vblank->framedur_ns)
+ return -EINVAL;
+
+ count = drm_vblank_count_and_time(crtc->dev, pipe, vblanktime);
+
+ /*
+* If we don't get a valid count, then we probably also don't
+* have a valid time:
+*/
+ if (!count)
+ return -EINVAL;
+
+ *vblanktime = ktime_add(*vblanktime, ns_to_ktime(vblank->framedur_ns));
+
+ return 0;
+}
+
static void send_vblank_event(struct drm_device *dev,
struct drm_pending_vblank_event *e,
u64 seq, ktime_t now)
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 733a3e2d1d10..a63bc2c92f3c 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -230,6 +230,7 @@ bool drm_dev_has_vblank(const struct drm_device *dev);
u64 drm_crtc_vblank_count(struct drm_crtc *crtc);
u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
ktime_t *vblanktime);
+int drm_crtc_next_vblank_time(struct drm_crtc *crtc, ktime_t *vblanktime);
void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
struct drm_pending_vblank_event *e);
void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
--
2.31.1
[PATCH v2 1/5] dma-fence: Add deadline awareness
From: Rob Clark
Add a way to hint to the fence signaler of an upcoming deadline, such as
vblank, which the fence waiter would prefer not to miss. This is to aid
the fence signaler in making power management decisions, like boosting
frequency as the deadline approaches and awareness of missing deadlines
so that can be factored in to the frequency scaling.
v2: Drop dma_fence::deadline and related logic to filter duplicate
deadlines, to avoid increasing dma_fence size. The fence-context
implementation will need similar logic to track deadlines of all
the fences on the same timeline. [ckoenig]
Signed-off-by: Rob Clark
---
drivers/dma-buf/dma-fence.c | 20
include/linux/dma-fence.h | 16
2 files changed, 36 insertions(+)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index ce0f5eff575d..1f444863b94d 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -910,6 +910,26 @@ dma_fence_wait_any_timeout(struct dma_fence **fences,
uint32_t count,
}
EXPORT_SYMBOL(dma_fence_wait_any_timeout);
+
+/**
+ * dma_fence_set_deadline - set desired fence-wait deadline
+ * @fence:the fence that is to be waited on
+ * @deadline: the time by which the waiter hopes for the fence to be
+ *signaled
+ *
+ * Inform the fence signaler of an upcoming deadline, such as vblank, by
+ * which point the waiter would prefer the fence to be signaled by. This
+ * is intended to give feedback to the fence signaler to aid in power
+ * management decisions, such as boosting GPU frequency if a periodic
+ * vblank deadline is approaching.
+ */
+void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
+{
+ if (fence->ops->set_deadline && !dma_fence_is_signaled(fence))
+ fence->ops->set_deadline(fence, deadline);
+}
+EXPORT_SYMBOL(dma_fence_set_deadline);
+
/**
* dma_fence_init - Initialize a custom fence.
* @fence: the fence to initialize
diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
index 6ffb4b2c6371..9c809f0d5d0a 100644
--- a/include/linux/dma-fence.h
+++ b/include/linux/dma-fence.h
@@ -99,6 +99,7 @@ enum dma_fence_flag_bits {
DMA_FENCE_FLAG_SIGNALED_BIT,
DMA_FENCE_FLAG_TIMESTAMP_BIT,
DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+ DMA_FENCE_FLAG_HAS_DEADLINE_BIT,
DMA_FENCE_FLAG_USER_BITS, /* must always be last member */
};
@@ -261,6 +262,19 @@ struct dma_fence_ops {
*/
void (*timeline_value_str)(struct dma_fence *fence,
char *str, int size);
+
+ /**
+* @set_deadline:
+*
+* Callback to allow a fence waiter to inform the fence signaler of an
+* upcoming deadline, such as vblank, by which point the waiter would
+* prefer the fence to be signaled by. This is intended to give
feedback
+* to the fence signaler to aid in power management decisions, such as
+* boosting GPU frequency.
+*
+* This callback is optional.
+*/
+ void (*set_deadline)(struct dma_fence *fence, ktime_t deadline);
};
void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
@@ -586,6 +600,8 @@ static inline signed long dma_fence_wait(struct dma_fence
*fence, bool intr)
return ret < 0 ? ret : 0;
}
+void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline);
+
struct dma_fence *dma_fence_get_stub(void);
struct dma_fence *dma_fence_allocate_private_stub(void);
u64 dma_fence_context_alloc(unsigned num);
--
2.31.1
[PATCH v2 0/5] dma-fence: Deadline awareness
From: Rob Clark Based on discussion from a previous series[1] to add a "boost" mechanism when, for example, vblank deadlines are missed. Instead of a boost callback, this approach adds a way to set a deadline on the fence, by which the waiter would like to see the fence signalled. I've not yet had a chance to re-work the drm/msm part of this, but wanted to send this out as an RFC in case I don't have a chance to finish the drm/msm part this week. Original description: In some cases, like double-buffered rendering, missing vblanks can trick the GPU into running at a lower frequence, when really we want to be running at a higher frequency to not miss the vblanks in the first place. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers [1] https://patchwork.freedesktop.org/series/90331/ v1: https://patchwork.freedesktop.org/series/93035/ v2: Move filtering out of later deadlines to fence implementation to avoid increasing the size of dma_fence Rob Clark (5): dma-fence: Add deadline awareness drm/vblank: Add helper to get next vblank time drm/atomic-helper: Set fence deadline for vblank drm/scheduler: Add fence deadline support drm/msm: Add deadline based boost support drivers/dma-buf/dma-fence.c | 20 +++ drivers/gpu/drm/drm_atomic_helper.c | 36 drivers/gpu/drm/drm_vblank.c| 31 ++ drivers/gpu/drm/msm/msm_fence.c | 76 + drivers/gpu/drm/msm/msm_fence.h | 20 +++ drivers/gpu/drm/msm/msm_gpu.h | 1 + drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++ drivers/gpu/drm/scheduler/sched_fence.c | 25 drivers/gpu/drm/scheduler/sched_main.c | 3 + include/drm/drm_vblank.h| 1 + include/drm/gpu_scheduler.h | 6 ++ include/linux/dma-fence.h | 16 ++ 12 files changed, 255 insertions(+) -- 2.31.1
Re: [Intel-gfx] [PATCH 0/4] Enable GuC submission by default on DG1
On Fri, Aug 06, 2021 at 01:34:33PM +0200, Thomas Hellström (Intel) wrote: > Hi, > > On 8/3/21 7:26 PM, Matthew Brost wrote: > > On Tue, Aug 03, 2021 at 02:15:13PM +0200, Daniel Vetter wrote: > > > On Tue, Aug 3, 2021 at 6:53 AM Matthew Brost > > > wrote: > > > > Minimum set of patches to enable GuC submission on DG1 and enable it by > > > > default. > > > > > > > > A little difficult to test as IGTs do not work with DG1 due to a bunch > > > > of uAPI features being disabled (e.g. relocations, caching memory > > > > options, etc...). > > > Matt Auld has an igt series which fixes a lot of this stuff, would be > > > good to do at least a Test-With run with that. > > > > It looks like Maarten now merged Matt's series to IGT. Great. > > There is a series on IGT trybot with pending work to have some igt tests > support relocations, > > https://patchwork.freedesktop.org/series/92043/ > Will take a look but at the moment we are blocked because SLPC won't init on the DG1 in CI but it works just fine on all other parts I've tried in RIL. We suspect the DG1 in CI is an early stepping and we may be missing workarounds. Have a possible fix, just need to try it out. We also might just want to replace the DG1 part in CI with a newer stepping so we don't have to upstream WAs for non-shipping parts. > One of the tests that have WIP fixes is gem_exec_whisper, and that > particular test has historically shown occasional hangs with GuC submission > on DG1 so it would be very desirable if we could make that test in > particular work (I haven't verified that that's the case) reliably. > I just ran gem_exec_whisper on DG1, with GuC submission, and kernel hacked to allow relocs. It passed for me. Only 1 run though so it is possible there are still intermittent issues. We really need to get CI up and running ASAP on all platforms where GuC submission is POR. Perhaps on all gen11+ platforms as well because GuC submission is supported and the more coverage we can get, the better. > Also the following series: > > https://patchwork.freedesktop.org/series/93455/ I'll check this series out too. Matt > > tries a bit harder to get some more tests running, squashing the above > series on top of latest IGT. > > Thanks, > /Thomas > >
Re: [PATCH v2] drm/msm: Implement mmap as GEM object function
On Tue, Jul 6, 2021 at 1:47 AM Thomas Zimmermann wrote:
>
> Moving the driver-specific mmap code into a GEM object function allows
> for using DRM helpers for various mmap callbacks.
>
> The respective msm functions are being removed. The file_operations
> structure fops is now being created by the helper macro
> DEFINE_DRM_GEM_FOPS().
>
> v2:
> * rebase onto latest upstream
> * remove declaration of msm_gem_mmap_obj() from msm_fbdev.c
>
> Signed-off-by: Thomas Zimmermann
applied with the following fixup squashed in:
---
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 4d1872916552..28c1a81f7e7f 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -1057,7 +1057,7 @@ static int msm_gem_object_mmap(struct
drm_gem_object *obj, struct vm_area_struct
struct msm_gem_object *msm_obj = to_msm_bo(obj);
vma->vm_flags &= ~VM_PFNMAP;
- vma->vm_flags |= VM_MIXEDMAP;
+ vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags));
return 0;
---
BR,
-R
> ---
> drivers/gpu/drm/msm/msm_drv.c | 14 ++-
> drivers/gpu/drm/msm/msm_drv.h | 1 -
> drivers/gpu/drm/msm/msm_fbdev.c | 12 ++
> drivers/gpu/drm/msm/msm_gem.c | 37 ++---
> drivers/gpu/drm/msm/msm_gem.h | 3 ---
> drivers/gpu/drm/msm/msm_gem_prime.c | 11 -
> 6 files changed, 16 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 9b8fa2ad0d84..a4d238e8d377 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -1004,17 +1004,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
> DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query,
> DRM_RENDER_ALLOW),
> };
>
> -static const struct file_operations fops = {
> - .owner = THIS_MODULE,
> - .open = drm_open,
> - .release= drm_release,
> - .unlocked_ioctl = drm_ioctl,
> - .compat_ioctl = drm_compat_ioctl,
> - .poll = drm_poll,
> - .read = drm_read,
> - .llseek = no_llseek,
> - .mmap = msm_gem_mmap,
> -};
> +DEFINE_DRM_GEM_FOPS(fops);
>
> static const struct drm_driver msm_driver = {
> .driver_features= DRIVER_GEM |
> @@ -1034,7 +1024,7 @@ static const struct drm_driver msm_driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
> - .gem_prime_mmap = msm_gem_prime_mmap,
> + .gem_prime_mmap = drm_gem_prime_mmap,
> #ifdef CONFIG_DEBUG_FS
> .debugfs_init = msm_debugfs_init,
> #endif
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 1a48a709ffb3..1a42903db347 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -309,7 +309,6 @@ void msm_gem_shrinker_cleanup(struct drm_device *dev);
> struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
> int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
> void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map
> *map);
> -int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct
> *vma);
> struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
> struct dma_buf_attachment *attach, struct sg_table *sg);
> int msm_gem_prime_pin(struct drm_gem_object *obj);
> diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
> index 67fae60f2fa5..0daaeb54ff6f 100644
> --- a/drivers/gpu/drm/msm/msm_fbdev.c
> +++ b/drivers/gpu/drm/msm/msm_fbdev.c
> @@ -8,13 +8,12 @@
> #include
> #include
> #include
> +#include
>
> #include "msm_drv.h"
> #include "msm_gem.h"
> #include "msm_kms.h"
>
> -extern int msm_gem_mmap_obj(struct drm_gem_object *obj,
> - struct vm_area_struct *vma);
> static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma);
>
> /*
> @@ -48,15 +47,8 @@ static int msm_fbdev_mmap(struct fb_info *info, struct
> vm_area_struct *vma)
> struct drm_fb_helper *helper = (struct drm_fb_helper *)info->par;
> struct msm_fbdev *fbdev = to_msm_fbdev(helper);
> struct drm_gem_object *bo = msm_framebuffer_bo(fbdev->fb, 0);
> - int ret = 0;
>
> - ret = drm_gem_mmap_obj(bo, bo->size, vma);
> - if (ret) {
> - pr_err("%s:drm_gem_mmap_obj fail\n", __func__);
> - return ret;
> - }
> -
> - return msm_gem_mmap_obj(bo, vma);
> + return drm_gem_prime_mmap(bo, vma);
> }
>
> static int msm_fbdev_create(struct drm_fb_helper *helper,
> diff --git
Re: [PATCH v2 07/14] drm/msm: Convert to Linux IRQ interfaces
On Tue, Aug 3, 2021 at 2:37 AM Dmitry Baryshkov
wrote:
>
> On 03/08/2021 12:06, Thomas Zimmermann wrote:
> > Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
> > IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
> > don't benefit from using it.
> >
> > DRM IRQ callbacks are now being called directly or inlined.
> >
> > Signed-off-by: Thomas Zimmermann
>
> Reviewed-by: Dmitry Baryshkov
>
> Rob should probably also give his blessing on this patch though.
>
I've pushed this to msm-next-staging, but if Thomas would prefer to
merge the series together then I can drop it (in which case a-b for
this patch)
BR,
-R
> > ---
> > drivers/gpu/drm/msm/msm_drv.c | 113 --
> > drivers/gpu/drm/msm/msm_kms.h | 2 +-
> > 2 files changed, 69 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> > index 1594ae39d54f..a332b09a5a11 100644
> > --- a/drivers/gpu/drm/msm/msm_drv.c
> > +++ b/drivers/gpu/drm/msm/msm_drv.c
> > @@ -14,7 +14,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include
> > @@ -201,6 +200,71 @@ void msm_rmw(void __iomem *addr, u32 mask, u32 or)
> > msm_writel(val | or, addr);
> > }
> >
> > +static irqreturn_t msm_irq(int irq, void *arg)
> > +{
> > + struct drm_device *dev = arg;
> > + struct msm_drm_private *priv = dev->dev_private;
> > + struct msm_kms *kms = priv->kms;
> > +
> > + BUG_ON(!kms);
> > +
> > + return kms->funcs->irq(kms);
> > +}
> > +
> > +static void msm_irq_preinstall(struct drm_device *dev)
> > +{
> > + struct msm_drm_private *priv = dev->dev_private;
> > + struct msm_kms *kms = priv->kms;
> > +
> > + BUG_ON(!kms);
> > +
> > + kms->funcs->irq_preinstall(kms);
> > +}
> > +
> > +static int msm_irq_postinstall(struct drm_device *dev)
> > +{
> > + struct msm_drm_private *priv = dev->dev_private;
> > + struct msm_kms *kms = priv->kms;
> > +
> > + BUG_ON(!kms);
> > +
> > + if (kms->funcs->irq_postinstall)
> > + return kms->funcs->irq_postinstall(kms);
> > +
> > + return 0;
> > +}
> > +
> > +static int msm_irq_install(struct drm_device *dev, unsigned int irq)
> > +{
> > + int ret;
> > +
> > + if (irq == IRQ_NOTCONNECTED)
> > + return -ENOTCONN;
> > +
> > + msm_irq_preinstall(dev);
> > +
> > + ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = msm_irq_postinstall(dev);
> > + if (ret) {
> > + free_irq(irq, dev);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void msm_irq_uninstall(struct drm_device *dev)
> > +{
> > + struct msm_drm_private *priv = dev->dev_private;
> > + struct msm_kms *kms = priv->kms;
> > +
> > + kms->funcs->irq_uninstall(kms);
> > + free_irq(kms->irq, dev);
> > +}
> > +
> > struct msm_vblank_work {
> > struct work_struct work;
> > int crtc_id;
> > @@ -265,7 +329,7 @@ static int msm_drm_uninit(struct device *dev)
> > }
> >
> > /* We must cancel and cleanup any pending vblank enable/disable
> > - * work before drm_irq_uninstall() to avoid work re-enabling an
> > + * work before msm_irq_uninstall() to avoid work re-enabling an
> >* irq after uninstall has disabled it.
> >*/
> >
> > @@ -294,7 +358,7 @@ static int msm_drm_uninit(struct device *dev)
> > drm_mode_config_cleanup(ddev);
> >
> > pm_runtime_get_sync(dev);
> > - drm_irq_uninstall(ddev);
> > + msm_irq_uninstall(ddev);
> > pm_runtime_put_sync(dev);
> >
> > if (kms && kms->funcs)
> > @@ -553,7 +617,7 @@ static int msm_drm_init(struct device *dev, const
> > struct drm_driver *drv)
> >
> > if (kms) {
> > pm_runtime_get_sync(dev);
> > - ret = drm_irq_install(ddev, kms->irq);
> > + ret = msm_irq_install(ddev, kms->irq);
> > pm_runtime_put_sync(dev);
> > if (ret < 0) {
> > DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
> > @@ -662,43 +726,6 @@ static void msm_postclose(struct drm_device *dev,
> > struct drm_file *file)
> > context_close(ctx);
> > }
> >
> > -static irqreturn_t msm_irq(int irq, void *arg)
> > -{
> > - struct drm_device *dev = arg;
> > - struct msm_drm_private *priv = dev->dev_private;
> > - struct msm_kms *kms = priv->kms;
> > - BUG_ON(!kms);
> > - return kms->funcs->irq(kms);
> > -}
> > -
> > -static void msm_irq_preinstall(struct drm_device *dev)
> > -{
> > - struct msm_drm_private *priv = dev->dev_private;
> > - struct msm_kms *kms = priv->kms;
> > - BUG_ON(!kms);
> > - kms->funcs->irq_preinstall(kms);
> > -}
> > -
> > -static int msm_irq_postinstall(struct drm_device *dev)
> > -{
> > - struct msm_drm_private *priv =
[PATCH 2/2] drm/msm: Rework SQE version check
From: Rob Clark
This check is really about which SQE firmware, rather than which GPU.
Rework to match minimum version based on firmware name, so it doesn't
need to be updated when adding additional GPUs using the same fw.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index be62f492538c..0e8238f58721 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -747,6 +747,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu
*a6xx_gpu,
{
struct adreno_gpu *adreno_gpu = _gpu->base;
struct msm_gpu *gpu = _gpu->base;
+ const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE];
u32 *buf = msm_gem_get_vaddr(obj);
bool ret = false;
@@ -763,8 +764,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu
*a6xx_gpu,
*
* a660 targets have all the critical security fixes from the start
*/
- if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
- adreno_is_a640_family(adreno_gpu)) {
+ if (!strcmp(sqe_name, "a630_sqe.fw")) {
/*
* If the lowest nibble is 0xa that is an indication that this
* microcode has been patched. The actual version is in dword
@@ -785,7 +785,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu
*a6xx_gpu,
DRM_DEV_ERROR(>pdev->dev,
"a630 SQE ucode is too old. Have version %x need at
least %x\n",
buf[0] & 0xfff, 0x190);
- } else if (adreno_is_a650(adreno_gpu)) {
+ } else if (!strcmp(sqe_name, "a650_sqe.fw")) {
if ((buf[0] & 0xfff) >= 0x095) {
ret = true;
goto out;
@@ -794,7 +794,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu
*a6xx_gpu,
DRM_DEV_ERROR(>pdev->dev,
"a650 SQE ucode is too old. Have version %x need at
least %x\n",
buf[0] & 0xfff, 0x095);
- } else if (adreno_is_a660_family(adreno_gpu)) {
+ } else if (!strcmp(sqe_name, "a660_sqe.fw")) {
ret = true;
} else {
DRM_DEV_ERROR(>pdev->dev,
--
2.31.1
[PATCH 1/2] drm/msm: Add adreno_is_a640_family()
From: Rob Clark
Combine adreno_is_a640() and adreno_is_a680().
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 ++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 9 ++---
4 files changed, 12 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index ab6b22264c2b..a7c58018959f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -521,8 +521,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
pdc_in_aop = true;
- else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu) ||
-adreno_is_a680(adreno_gpu))
+ else if (adreno_is_a618(adreno_gpu) ||
adreno_is_a640_family(adreno_gpu))
pdc_address_offset = 0x30090;
else
pdc_address_offset = 0x30080;
@@ -1527,7 +1526,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
device_node *node)
SZ_16M - SZ_16K, 0x04000);
if (ret)
goto err_memory;
- } else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu)) {
+ } else if (adreno_is_a640_family(adreno_gpu)) {
ret = a6xx_gmu_memory_alloc(gmu, >icache,
SZ_256K - SZ_16K, 0x04000);
if (ret)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6ddd9010cc4b..be62f492538c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -683,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a618(adreno_gpu))
return;
- if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu))
+ if (adreno_is_a640_family(adreno_gpu))
amsbc = 1;
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
@@ -764,7 +764,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu
*a6xx_gpu,
* a660 targets have all the critical security fixes from the start
*/
if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
- adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu)) {
+ adreno_is_a640_family(adreno_gpu)) {
/*
* If the lowest nibble is 0xa that is an indication that this
* microcode has been patched. The actual version is in dword
@@ -904,8 +904,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
a6xx_set_hwcg(gpu, true);
/* VBIF/GBIF start*/
- if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu) ||
- adreno_is_a680(adreno_gpu)) {
+ if (adreno_is_a640_family(adreno_gpu) ||
+ adreno_is_a650_family(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
@@ -943,8 +943,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
- if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu) ||
- adreno_is_a680(adreno_gpu))
+ if (adreno_is_a640_family(adreno_gpu) ||
+ adreno_is_a650_family(adreno_gpu))
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
else
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x01c0);
@@ -961,8 +961,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
*/
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
- else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu) ||
- adreno_is_7c3(adreno_gpu))
+ else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 376d0d9809fa..d4c65bf0a1b7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -458,7 +458,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
if (adreno_is_a618(adreno_gpu))
a618_build_bw_table();
- else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu))
+ else if (adreno_is_a640_family(adreno_gpu))
a640_build_bw_table();
else if
Re: [Intel-gfx] [PATCH] fbdev/efifb: Release PCI device's runtime PM ref during FB destroy
On Thu, Aug 05, 2021 at 12:23:21AM +0200, Daniel Vetter wrote:
> On Mon, Aug 02, 2021 at 04:35:51PM +0300, Imre Deak wrote:
> > Atm the EFI FB driver gets a runtime PM reference for the associated GFX
> > PCI device during driver probing and releases it only when removing the
> > driver.
> >
> > When fbcon switches to the FB provided by the PCI device's driver (for
> > instance i915/drmfb), the EFI FB will get only unregistered without the
> > EFI FB driver getting unloaded, keeping the runtime PM reference
> > acquired during driver probing. This reference will prevent the PCI
> > driver from runtime suspending the device.
> >
> > Fix this by releasing the RPM reference from the EFI FB's destroy hook,
> > called when the FB gets unregistered.
> >
> > Fixes: a6c0fd3d5a8b ("efifb: Ensure graphics device for efifb stays at PCI
> > D0")
> > Cc: Kai-Heng Feng
> > Signed-off-by: Imre Deak
>
> Patch looks good:
>
> Reviewed-by: Daniel Vetter
>
> But I've found a bunch of ordering issues here:
> - we should probably get the runtime pm reference _before_ we register the
> framebuffer. There's a race right now about there.
Yea, missed this will send a v2 moving it earlier.
> - the sysfs_remove_groups and framebuffer_release should also be moved
> into the destroy callback. This is more a leak type of situation.
Those sysfs entries belong to the efifb platform device, showing the
bootup screen_info.lfb_* info, not related to fb_info, so imo
efifb_remove() is the correct place to remove those. But yes, freeing
fb_info seems to belong to fb_destroy().
Atm, things will blow up when unbinding the efifb device after the efifb
framebuffer was unregistered while removing it as a conflicting FB
(since unregister_framebuffer() will be called twice), so that would
need to be solved as well. Maybe remove_conflicting_pci_framebuffers()
could unregister the platform device instead of only unregistering the
framebuffer, similarly to drm_aperture_detach_firmware(), but haven't
checked this in more detail.
> Cheers, Daniel
>
> > ---
> > drivers/video/fbdev/efifb.c | 8 +---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c
> > index 8ea8f079cde26..25cdea32b9633 100644
> > --- a/drivers/video/fbdev/efifb.c
> > +++ b/drivers/video/fbdev/efifb.c
> > @@ -47,6 +47,8 @@ static bool use_bgrt = true;
> > static bool request_mem_succeeded = false;
> > static u64 mem_flags = EFI_MEMORY_WC | EFI_MEMORY_UC;
> >
> > +static struct pci_dev *efifb_pci_dev; /* dev with BAR covering the
> > efifb */
> > +
> > static struct fb_var_screeninfo efifb_defined = {
> > .activate = FB_ACTIVATE_NOW,
> > .height = -1,
> > @@ -243,6 +245,9 @@ static inline void efifb_show_boot_graphics(struct
> > fb_info *info) {}
> >
> > static void efifb_destroy(struct fb_info *info)
> > {
> > + if (efifb_pci_dev)
> > + pm_runtime_put(_pci_dev->dev);
> > +
> > if (info->screen_base) {
> > if (mem_flags & (EFI_MEMORY_UC | EFI_MEMORY_WC))
> > iounmap(info->screen_base);
> > @@ -333,7 +338,6 @@ ATTRIBUTE_GROUPS(efifb);
> >
> > static bool pci_dev_disabled; /* FB base matches BAR of a disabled
> > device */
> >
> > -static struct pci_dev *efifb_pci_dev; /* dev with BAR covering the
> > efifb */
> > static struct resource *bar_resource;
> > static u64 bar_offset;
> >
> > @@ -603,8 +607,6 @@ static int efifb_remove(struct platform_device *pdev)
> > unregister_framebuffer(info);
> > sysfs_remove_groups(>dev.kobj, efifb_groups);
> > framebuffer_release(info);
> > - if (efifb_pci_dev)
> > - pm_runtime_put(_pci_dev->dev);
> >
> > return 0;
> > }
> > --
> > 2.27.0
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
[PATCH] drm/amd/display/dc/dce112/dce112_resource: Drop redundant null-pointer check in bw_calcs_data_update_from_pplib()
The variable dc->bw_vbios is guaranteed to be not NULL by its callers.
Thus the null-pointer check can be dropped.
Reported-by: TOTE Robot
Signed-off-by: Tuo Li
---
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index ee55cda854bf..3fc8e6b664f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1064,7 +1064,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
struct dm_pp_clock_levels clks = {0};
int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
- if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
+ if (dc->bw_vbios->memory_type == bw_def_hbm)
memory_type_multiplier = MEMORY_TYPE_HBM;
/*do system clock TODO PPLIB: after PPLIB implement,
--
2.25.1
[PATCH v2 2/2] drm/panel: s6d27a1: Add driver for Samsung S6D27A1 display panel
This adds a driver for Samsung S6D27A1 display controller and panel.
This panel is found in the Samsung GT-I8160 mobile phone,
and possibly some other mobile phones.
This display needs manufacturer commands to configure it;
the commands used in this driver were taken from downstream driver
by Gareth Phillips; sadly, there is almost no documentation on what they
actually do.
This driver re-uses the DBI infrastructure to communicate with the display.
This driver is heavily based on WideChips WS2401 display controller
driver by Linus Walleij and on other panel drivers for reference.
Signed-off-by: Markuss Broks
v2 -> v3:
fixed checkpatch warnings - not sure about MAINTAINERS, should I
put my name up there?
v3 -> v4:
- add a MAINTAINERS entry;
- drop s6d27a1_command macro; use mipi_dbi_command directly;
- dropped "panel initialized" dev_dbg message;
- add drm_panel_of_backlight call to handle backlight
on panel turn on/off;
- reorder drm_mipi_dbi and drm_modes headers:
I think they should be in alphabetic order?
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-samsung-s6d27a1.c | 320 ++
4 files changed, 338 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 851255b71c..c363209130 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5962,6 +5962,12 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
F: drivers/gpu/drm/panel/panel-samsung-db7430.c
+DRM DRIVER FOR SAMSUNG S6D27A1 PANELS
+M: Markuss Broks
+S: Maintained
+F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
+F: driver/gpu/drm/panel/panel-samsung-s6d27a1.c
+
DRM DRIVER FOR SITRONIX ST7703 PANELS
M: Guido Günther
R: Purism Kernel Team
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index beb581b96e..0b37849413 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -392,6 +392,17 @@ config DRM_PANEL_SAMSUNG_S6D16D0
depends on DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_SAMSUNG_S6D27A1
+ tristate "Samsung S6D27A1 DPI panel driver"
+ depends on OF && SPI && GPIOLIB
+ select DRM_MIPI_DBI
+ help
+ Say Y here if you want to enable support for the Samsung
+ S6D27A1 DPI 480x800 panel.
+
+ This panel can be found in Samsung Galaxy Ace 2
+ GT-I8160 mobile phone.
+
config DRM_PANEL_SAMSUNG_S6E3HA2
tristate "Samsung S6E3HA2 DSI video mode panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index c8132050bc..60c0149fc5 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) +=
panel-samsung-atna33xc20.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
b/drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
new file mode 100644
index 00..2dfcf48f2b
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
@@ -0,0 +1,320 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Panel driver for the Samsung S6D27A1 480x800 DPI RGB panel.
+ * Found in the Samsung Galaxy Ace 2 GT-I8160 mobile phone.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define S6D27A1_PASSWD_L2 0xF0/* Password Command for Level 2 Control
*/
+#define S6D27A1_RESCTL 0xB3/* Resolution Select Control */
+#define S6D27A1_PANELCTL2 0xB4/* ASG Signal Control */
+#define S6D27A1_READID10xDA/* Read panel ID 1 */
+#define S6D27A1_READID20xDB/* Read panel ID 2 */
+#define S6D27A1_READID30xDC/* Read panel ID 3 */
+#define S6D27A1_DISPCTL0xF2/* Display Control */
+#define S6D27A1_MANPWR 0xF3/* Manual Control */
+#define S6D27A1_PWRCTL10xF4/* Power Control */
+#define S6D27A1_SRCCTL 0xF6/* Source Control */
+#define S6D27A1_PANELCTL 0xF7/* Panel Control*/
+
+static const u8 s6d27a1_dbi_read_commands[] = {
+ S6D27A1_READID1,
+ S6D27A1_READID2,
+ S6D27A1_READID3,
+ 0, /*
[PATCH v2 1/2] drm/panel: Add DT bindings for Samsung S6D27A1 display panel
This adds device-tree bindings for the Samsung S6D27A1 RGB
DPI display panel.
Signed-off-by: Markuss Broks
v1 -> v2:
changed additionalProperties to unevaluatedProperties;
added vci-supply and vccio-supply as required;
---
.../display/panel/samsung,s6d27a1.yaml| 98 +++
1 file changed, 98 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
new file mode 100644
index 00..26e3c820a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,s6d27a1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S6D27A1 display panel
+
+description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile
+ Displays (SMD). The panel must obey the rules for a SPI slave device
+ as specified in spi/spi-controller.yaml
+
+maintainers:
+ - Markuss Broks
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,s6d27a1
+
+ reg: true
+
+ interrupts:
+description: provides an optional ESD (electrostatic discharge)
+ interrupt that signals abnormalities in the display hardware.
+ This can also be raised for other reasons like erroneous
+ configuration.
+maxItems: 1
+
+ reset-gpios: true
+
+ vci-supply:
+description: regulator that supplies the VCI analog voltage
+ usually around 3.0 V
+
+ vccio-supply:
+description: regulator that supplies the VCCIO voltage usually
+ around 1.8 V
+
+ backlight: true
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ spi-max-frequency:
+maximum: 120
+
+ port: true
+
+required:
+ - compatible
+ - reg
+ - vci-supply
+ - vccio-supply
+ - spi-cpha
+ - spi-cpol
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+spi {
+compatible = "spi-gpio";
+sck-gpios = < 0 GPIO_ACTIVE_HIGH>;
+miso-gpios = < 1 GPIO_ACTIVE_HIGH>;
+mosi-gpios = < 2 GPIO_ACTIVE_HIGH>;
+cs-gpios = < 3 GPIO_ACTIVE_HIGH>;
+num-chipselects = <1>;
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,s6d27a1";
+spi-max-frequency = <120>;
+spi-cpha;
+spi-cpol;
+reg = <0>;
+vci-supply = <_3v0_reg>;
+vccio-supply = <_1v8_reg>;
+reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+interrupt-parent = <>;
+interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+
+port {
+panel_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+};
+
+...
--
2.32.0
[PATCH 0/2] Add support for Samsung S6D27A1 display panel
Add support for Samsung Mobile Displays(SMD) Samsung S6D27A1 panel. This display panel is used on Samsung mobile devices such as Samsung Galaxy Ace 2 (GT-I8160) also known as Codina. Markuss Broks (2): drm/panel: Add DT bindings for Samsung S6D27A1 display panel drm/panel: s6d27a1: Add driver for Samsung S6D27A1 display panel .../display/panel/samsung,s6d27a1.yaml| 97 ++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-samsung-s6d27a1.c | 323 ++ 4 files changed, 432 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6d27a1.c -- 2.32.0
Re: [PATCH v4 3/3] drm/loongson: Add interrupt driver for LS7A
Hi lichenyang, On Fri, Jul 30, 2021 at 05:41:48PM +0800, lichenyang wrote: > Add LS7A DC vsync interrupt enable and close function, and > register irq_handler function interface. > Add vbrank event processing flow. s/vbrank/vblank/ > > v4: > - Replace drm_irq_install with devm_request_irq. > - Delete the irq_ hooks in drm_driver. > > v3: > - Improve code readability. > - Use the to_pci_dev function to get pci_dev. > > v2: > - Added error handling in the loongson_drm_load function. > > Signed-off-by: lichenyang Patch looks good, Acked-by: Sam Ravnborg But then I am not to fluent in the vblank stuff, so I hope someone else takes a look too. Sam
Re: [PATCH v4 2/3] drm/loongson: Add GPIO and I2C driver for loongson drm.
Hi lichenyang,
On Fri, Jul 30, 2021 at 05:41:47PM +0800, lichenyang wrote:
> Implement use GPIO and I2C driver to detect connector
> and fetch EDID via DDC.
>
> v3:
> - Change some driver log to the drm_ version.
>
> v2:
> - Optimize the error handling process.
> - Delete loongson_i2c_bus_match and loongson_i2c_add function.
> - Optimize part of the code flow.
>
> Signed-off-by: lichenyang
Thanks for keeping me in the loop on this patch series.
In general the code looks pretty clean and well structured which makes
review easier - good.
As already said this driver should be implemented as a bridge which
would make the integration with the display driver simpler and more
straightforward.
When implementing this as a bridge driver there will be no drm_device,
so logging will need to use dev_err and friends.
Try to run the driver(s) with sparse:
make C=2 drivers/gpu/drm/loongson/
I think this will give you a few warnigns to fix.
Likewise use checkpatch --strict as this often resutls in a few easy to
fix warnings.
Last try to build with W=1 and fix warnings too.
The above goes for all files in this driver as we would like to have all
new drivers W=1, sparse and checkpatch clean.
Some more specific comments in the following,
Sam
> ---
> drivers/gpu/drm/loongson/Makefile | 1 +
> drivers/gpu/drm/loongson/loongson_connector.c | 59 -
> drivers/gpu/drm/loongson/loongson_drv.c | 15 +-
> drivers/gpu/drm/loongson/loongson_drv.h | 11 +
> drivers/gpu/drm/loongson/loongson_i2c.c | 249 ++
> drivers/gpu/drm/loongson/loongson_i2c.h | 36 +++
> 6 files changed, 366 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/loongson/loongson_i2c.c
> create mode 100644 drivers/gpu/drm/loongson/loongson_i2c.h
>
> diff --git a/drivers/gpu/drm/loongson/Makefile
> b/drivers/gpu/drm/loongson/Makefile
> index d73ad44fe1d5..a842e85cf6ca 100644
> --- a/drivers/gpu/drm/loongson/Makefile
> +++ b/drivers/gpu/drm/loongson/Makefile
> @@ -10,5 +10,6 @@ loongson-y := loongson_connector.o \
> loongson_device.o \
> loongson_drv.o \
> loongson_encoder.o \
> + loongson_i2c.o \
> loongson_plane.o
> obj-$(CONFIG_DRM_LOONGSON) += loongson.o
> diff --git a/drivers/gpu/drm/loongson/loongson_connector.c
> b/drivers/gpu/drm/loongson/loongson_connector.c
> index a4762d8f9987..bdf7d651d6d1 100644
> --- a/drivers/gpu/drm/loongson/loongson_connector.c
> +++ b/drivers/gpu/drm/loongson/loongson_connector.c
> @@ -4,12 +4,56 @@
>
> static int loongson_get_modes(struct drm_connector *connector)
> {
> - int count;
> + struct drm_device *dev = connector->dev;
> + struct loongson_connector *lconnector =
> + to_loongson_connector(connector);
> + struct i2c_adapter *adapter = lconnector->i2c->adapter;
> + struct edid *edid = NULL;
> + u32 ret;
>
> - count = drm_add_modes_noedid(connector, 1920, 1080);
> - drm_set_preferred_mode(connector, 1024, 768);
> + edid = drm_get_edid(connector, adapter);
> + if (edid) {
> + drm_connector_update_edid_property(connector, edid);
> + ret = drm_add_edid_modes(connector, edid);
> + } else {
> + drm_warn(dev, "Failed to read EDID\n");
> + ret = drm_add_modes_noedid(connector, 1920, 1080);
> + drm_set_preferred_mode(connector, 1024, 768);
> + }
>
> - return count;
> + return ret;
> +}
> +
> +static bool is_connected(struct loongson_connector *lconnector)
> +{
> + struct i2c_adapter *adapter = lconnector->i2c->adapter;
> + unsigned char start = 0x0;
> + struct i2c_msg msgs = {
> + .addr = DDC_ADDR,
> + .flags = 0,
> + .len = 1,
> + .buf = ,
> + };
> +
> + if (!lconnector->i2c)
> + return false;
> +
> + if (i2c_transfer(adapter, , 1) != 1)
> + return false;
> +
> + return true;
> +}
> +
> +static enum drm_connector_status
> +loongson_detect(struct drm_connector *connector, bool force)
> +{
> + struct loongson_connector *lconnector =
> + to_loongson_connector(connector);
> +
> + if (is_connected(lconnector))
> + return connector_status_connected;
> +
> + return connector_status_disconnected;
> }
>
> static const struct drm_connector_helper_funcs loongson_connector_helper = {
> @@ -17,6 +61,7 @@ static const struct drm_connector_helper_funcs
> loongson_connector_helper = {
> };
>
> static const struct drm_connector_funcs loongson_connector_funcs = {
> + .detect = loongson_detect,
> .fill_modes = drm_helper_probe_single_connector_modes,
> .destroy = drm_connector_cleanup,
> .reset = drm_atomic_helper_connector_reset,
> @@ -36,6 +81,12 @@ int loongson_connector_init(struct loongson_device *ldev,
> int index)
>
> lconnector->ldev = ldev;
> lconnector->id =
[PATCH] gpu/drm/i915: Remove duplicated include of intel_region_lmem.h
Duplicate include header file "intel_region_lmem.h"
line 8: #include "intel_region_lmem.h"
line 13: #include "intel_region_lmem.h"
Signed-off-by: zhouchuangao
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 58a3cf7..50d11a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -10,7 +10,6 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
-#include "intel_region_lmem.h"
static int init_fake_lmem_bar(struct intel_memory_region *mem)
{
--
2.7.4
Re: [PATCH v2 00/14] drm: Make DRM's IRQ helpers legacy
Hi
Am 06.08.21 um 01:59 schrieb Chrisanthus, Anitha:
Hi Thomas,
-Original Message-
From: Thomas Zimmermann
Sent: Wednesday, August 4, 2021 12:11 AM
To: Chrisanthus, Anitha ; Sam Ravnborg
Cc: dan...@ffwll.ch; airl...@linux.ie; alexander.deuc...@amd.com;
christian.koe...@amd.com; liviu.du...@arm.com; brian.star...@arm.com;
bbrezil...@kernel.org; nicolas.fe...@microchip.com;
maarten.lankho...@linux.intel.com; mrip...@kernel.org; ste...@agner.ch;
alison.w...@nxp.com; patrik.r.jakobs...@gmail.com; robdcl...@gmail.com;
Dea, Edmund J ; s...@poorly.run;
shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
jyri.sa...@iki.fi; to...@kernel.org; dan.sned...@microchip.com;
tomi.valkei...@ideasonboard.com; amd-...@lists.freedesktop.org; dri-
de...@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org; linux-arm-
m...@vger.kernel.org; freedr...@lists.freedesktop.org
Subject: Re: [PATCH v2 00/14] drm: Make DRM's IRQ helpers legacy
Hi
Am 03.08.21 um 20:36 schrieb Chrisanthus, Anitha:
Hi Thomas,
Can you please hold off on applying the kmb patch, I am seeing some issues
while testing. Modetest works, but video playback only plays once, and it fails
the second time with this patch.
Sounds a bit like the testing issue at [1]. For testing, you need the
latest drm-misc-next or drm-tip. Specifically, you need commit
1e4cd78ed493 ("drm: Don't test for IRQ support in VBLANK ioctls").
You are right, with the above patch video plays fine. It's all good now! Sorry
about the confusion.
Thanks for trying. Can I add your Tested-by tag?
Best regards
Thomas
Let me know whether this works for you.
Best regards
Thomas
[1] https://patchwork.freedesktop.org/patch/447057/?series=93078=1
Thanks,
Anitha
-Original Message-
From: Sam Ravnborg
Sent: Tuesday, August 3, 2021 8:05 AM
To: Thomas Zimmermann
Cc: dan...@ffwll.ch; airl...@linux.ie; alexander.deuc...@amd.com;
christian.koe...@amd.com; liviu.du...@arm.com;
brian.star...@arm.com;
bbrezil...@kernel.org; nicolas.fe...@microchip.com;
maarten.lankho...@linux.intel.com; mrip...@kernel.org;
ste...@agner.ch;
alison.w...@nxp.com; patrik.r.jakobs...@gmail.com; Chrisanthus, Anitha
; robdcl...@gmail.com; Dea, Edmund J
; s...@poorly.run; shawn...@kernel.org;
s.ha...@pengutronix.de; ker...@pengutronix.de; jyri.sa...@iki.fi;
to...@kernel.org; dan.sned...@microchip.com;
tomi.valkei...@ideasonboard.com; amd-...@lists.freedesktop.org; dri-
de...@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org; linux-
arm-
m...@vger.kernel.org; freedr...@lists.freedesktop.org
Subject: Re: [PATCH v2 00/14] drm: Make DRM's IRQ helpers legacy
Hi Thomas,
On Tue, Aug 03, 2021 at 11:06:50AM +0200, Thomas Zimmermann wrote:
DRM's IRQ helpers are only helpful for old, non-KMS drivers. Move
the code behind CONFIG_DRM_LEGACY. Convert KMS drivers to Linux
IRQ interfaces.
DRM provides IRQ helpers for setting up, receiving and removing IRQ
handlers. It's an abstraction over plain Linux functions. The code
is mid-layerish with several callbacks to hook into the rsp drivers.
Old UMS driver have their interrupts enabled via ioctl, so these
abstractions makes some sense. Modern KMS manage all their interrupts
internally. Using the DRM helpers adds indirection without benefits.
Most KMS drivers already use Linux IRQ functions instead of DRM's
abstraction layer. Patches 1 to 12 convert the remaining ones.
The patches also resolve a bug for devices without assigned interrupt
number. DRM helpers don't test for IRQ_NOTCONNECTED, so drivers do
not detect if the device has no interrupt assigned.
Patch 13 removes an unused function.
Patch 14 moves the DRM IRQ helpers behind CONFIG_DRM_LEGACY. Only
the old non-KMS drivers still use the functionality.
v2:
* drop IRQ_NOTCONNECTED test from atmel-hlcdc (Sam)
* use devm_request_irq() in atmel-hlcdc (Sam)
* unify variable names in arm/hlcdc (Sam)
Thomas Zimmermann (14):
The following patches are all:
Acked-by: Sam Ravnborg
drm/fsl-dcu: Convert to Linux IRQ interfaces
drm/gma500: Convert to Linux IRQ interfaces
drm/kmb: Convert to Linux IRQ interfaces
drm/msm: Convert to Linux IRQ interfaces
drm/mxsfb: Convert to Linux IRQ interfaces
drm/tidss: Convert to Linux IRQ interfaces
drm/vc4: Convert to Linux IRQ interfaces
drm: Remove unused devm_drm_irq_install()
The remaining patches I either skipped or already had a feedback from
me or I asked a question.
Sam
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
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