date:20220628

The objective is to test device migration mechanism in pages marked
as COW, for private and coherent device type. In case of writing to
COW private page(s), a page fault will migrate pages back to system
memory first. Then, these pages will be duplicated. In case of COW
device coherent type, pages are duplicated directly from device
memory.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
---
 tools/testing/selftests/vm/hmm-tests.c | 80 ++
 1 file changed, 80 insertions(+)

diff --git a/tools/testing/selftests/vm/hmm-tests.c 
b/tools/testing/selftests/vm/hmm-tests.c
index bb38b9777610..716b62c05e3d 100644
--- a/tools/testing/selftests/vm/hmm-tests.c
+++ b/tools/testing/selftests/vm/hmm-tests.c
@@ -1874,4 +1874,84 @@ TEST_F(hmm, hmm_gup_test)
close(gup_fd);
hmm_buffer_free(buffer);
 }
+
+/*
+ * Test copy-on-write in device pages.
+ * In case of writing to COW private page(s), a page fault will migrate pages
+ * back to system memory first. Then, these pages will be duplicated. In case
+ * of COW device coherent type, pages are duplicated directly from device
+ * memory.
+ */
+TEST_F(hmm, hmm_cow_in_device)
+{
+   struct hmm_buffer *buffer;
+   unsigned long npages;
+   unsigned long size;
+   unsigned long i;
+   int *ptr;
+   int ret;
+   unsigned char *m;
+   pid_t pid;
+   int status;
+
+   npages = 4;
+   size = npages << self->page_shift;
+
+   buffer = malloc(sizeof(*buffer));
+   ASSERT_NE(buffer, NULL);
+
+   buffer->fd = -1;
+   buffer->size = size;
+   buffer->mirror = malloc(size);
+   ASSERT_NE(buffer->mirror, NULL);
+
+   buffer->ptr = mmap(NULL, size,
+  PROT_READ | PROT_WRITE,
+  MAP_PRIVATE | MAP_ANONYMOUS,
+  buffer->fd, 0);
+   ASSERT_NE(buffer->ptr, MAP_FAILED);
+
+   /* Initialize buffer in system memory. */
+   for (i = 0, ptr = buffer->ptr; i < size / sizeof(*ptr); ++i)
+   ptr[i] = i;
+
+   /* Migrate memory to device. */
+
+   ret = hmm_migrate_sys_to_dev(self->fd, buffer, npages);
+   ASSERT_EQ(ret, 0);
+   ASSERT_EQ(buffer->cpages, npages);
+
+   pid = fork();
+   if (pid == -1)
+   ASSERT_EQ(pid, 0);
+   if (!pid) {
+   /* Child process waitd for SIGTERM from the parent. */
+   while (1) {
+   }
+   perror("Should not reach this\n");
+   exit(0);
+   }
+   /* Parent process writes to COW pages(s) and gets a
+* new copy in system. In case of device private pages,
+* this write causes a migration to system mem first.
+*/
+   for (i = 0, ptr = buffer->ptr; i < size / sizeof(*ptr); ++i)
+   ptr[i] = i;
+
+   /* Terminate child and wait */
+   EXPECT_EQ(0, kill(pid, SIGTERM));
+   EXPECT_EQ(pid, waitpid(pid, , 0));
+   EXPECT_NE(0, WIFSIGNALED(status));
+   EXPECT_EQ(SIGTERM, WTERMSIG(status));
+
+   /* Take snapshot to CPU pagetables */
+   ret = hmm_dmirror_cmd(self->fd, HMM_DMIRROR_SNAPSHOT, buffer, npages);
+   ASSERT_EQ(ret, 0);
+   ASSERT_EQ(buffer->cpages, npages);
+   m = buffer->mirror;
+   for (i = 0; i < npages; i++)
+   ASSERT_EQ(HMM_DMIRROR_PROT_WRITE, m[i]);
+
+   hmm_buffer_free(buffer);
+}
 TEST_HARNESS_MAIN
-- 
2.32.0

[PATCH v7 09/14] lib: test_hmm add module param for zone device type

In order to configure device coherent in test_hmm, two module parameters
should be passed, which correspond to the SP start address of each
device (2) spm_addr_dev0 & spm_addr_dev1. If no parameters are passed,
private device type is configured.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Poppple 
Signed-off-by: Christoph Hellwig 
---
 lib/test_hmm.c  | 73 -
 lib/test_hmm_uapi.h |  1 +
 2 files changed, 53 insertions(+), 21 deletions(-)

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index 915ef6b5b0d4..afb30af9f3ff 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -37,6 +37,16 @@
 #define DEVMEM_CHUNK_SIZE  (256 * 1024 * 1024U)
 #define DEVMEM_CHUNKS_RESERVE  16
 
+static unsigned long spm_addr_dev0;
+module_param(spm_addr_dev0, long, 0644);
+MODULE_PARM_DESC(spm_addr_dev0,
+   "Specify start address for SPM (special purpose memory) used 
for device 0. By setting this Coherent device type will be used. Make sure 
spm_addr_dev1 is set too. Minimum SPM size should be DEVMEM_CHUNK_SIZE.");
+
+static unsigned long spm_addr_dev1;
+module_param(spm_addr_dev1, long, 0644);
+MODULE_PARM_DESC(spm_addr_dev1,
+   "Specify start address for SPM (special purpose memory) used 
for device 1. By setting this Coherent device type will be used. Make sure 
spm_addr_dev0 is set too. Minimum SPM size should be DEVMEM_CHUNK_SIZE.");
+
 static const struct dev_pagemap_ops dmirror_devmem_ops;
 static const struct mmu_interval_notifier_ops dmirror_min_ops;
 static dev_t dmirror_dev;
@@ -455,28 +465,44 @@ static int dmirror_write(struct dmirror *dmirror, struct 
hmm_dmirror_cmd *cmd)
return ret;
 }
 
-static bool dmirror_allocate_chunk(struct dmirror_device *mdevice,
+static int dmirror_allocate_chunk(struct dmirror_device *mdevice,
   struct page **ppage)
 {
struct dmirror_chunk *devmem;
-   struct resource *res;
+   struct resource *res = NULL;
unsigned long pfn;
unsigned long pfn_first;
unsigned long pfn_last;
void *ptr;
+   int ret = -ENOMEM;
 
devmem = kzalloc(sizeof(*devmem), GFP_KERNEL);
if (!devmem)
-   return false;
+   return ret;
 
-   res = request_free_mem_region(_resource, DEVMEM_CHUNK_SIZE,
- "hmm_dmirror");
-   if (IS_ERR(res))
+   switch (mdevice->zone_device_type) {
+   case HMM_DMIRROR_MEMORY_DEVICE_PRIVATE:
+   res = request_free_mem_region(_resource, 
DEVMEM_CHUNK_SIZE,
+ "hmm_dmirror");
+   if (IS_ERR_OR_NULL(res))
+   goto err_devmem;
+   devmem->pagemap.range.start = res->start;
+   devmem->pagemap.range.end = res->end;
+   devmem->pagemap.type = MEMORY_DEVICE_PRIVATE;
+   break;
+   case HMM_DMIRROR_MEMORY_DEVICE_COHERENT:
+   devmem->pagemap.range.start = (MINOR(mdevice->cdevice.dev) - 2) 
?
+   spm_addr_dev0 :
+   spm_addr_dev1;
+   devmem->pagemap.range.end = devmem->pagemap.range.start +
+   DEVMEM_CHUNK_SIZE - 1;
+   devmem->pagemap.type = MEMORY_DEVICE_COHERENT;
+   break;
+   default:
+   ret = -EINVAL;
goto err_devmem;
+   }
 
-   devmem->pagemap.type = MEMORY_DEVICE_PRIVATE;
-   devmem->pagemap.range.start = res->start;
-   devmem->pagemap.range.end = res->end;
devmem->pagemap.nr_range = 1;
devmem->pagemap.ops = _devmem_ops;
devmem->pagemap.owner = mdevice;
@@ -497,10 +523,14 @@ static bool dmirror_allocate_chunk(struct dmirror_device 
*mdevice,
mdevice->devmem_capacity = new_capacity;
mdevice->devmem_chunks = new_chunks;
}
-
ptr = memremap_pages(>pagemap, numa_node_id());
-   if (IS_ERR(ptr))
+   if (IS_ERR_OR_NULL(ptr)) {
+   if (ptr)
+   ret = PTR_ERR(ptr);
+   else
+   ret = -EFAULT;
goto err_release;
+   }
 
devmem->mdevice = mdevice;
pfn_first = devmem->pagemap.range.start >> PAGE_SHIFT;
@@ -529,15 +559,17 @@ static bool dmirror_allocate_chunk(struct dmirror_device 
*mdevice,
}
spin_unlock(>lock);
 
-   return true;
+   return 0;
 
 err_release:
mutex_unlock(>devmem_lock);
-   release_mem_region(devmem->pagemap.range.start, 
range_len(>pagemap.range));
+   if (res && devmem->pagemap.type == MEMORY_DEVICE_PRIVATE)
+   release_mem_region(devmem->pagemap.range.start,
+  range_len(>pagemap.range));
 err_devmem:
kfree(devmem);
 
-   return false;
+

[PATCH v7 08/14] lib: test_hmm add ioctl to get zone device type

new ioctl cmd added to query zone device type. This will be
used once the test_hmm adds zone device coherent type.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Poppple 
Signed-off-by: Christoph Hellwig 
---
 lib/test_hmm.c  | 11 +--
 lib/test_hmm_uapi.h | 14 ++
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index cfe632047839..915ef6b5b0d4 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -87,6 +87,7 @@ struct dmirror_chunk {
 struct dmirror_device {
struct cdev cdevice;
struct hmm_devmem   *devmem;
+   unsigned intzone_device_type;
 
unsigned intdevmem_capacity;
unsigned intdevmem_count;
@@ -1260,14 +1261,20 @@ static void dmirror_device_remove(struct dmirror_device 
*mdevice)
 static int __init hmm_dmirror_init(void)
 {
int ret;
-   int id;
+   int id = 0;
+   int ndevices = 0;
 
ret = alloc_chrdev_region(_dev, 0, DMIRROR_NDEVICES,
  "HMM_DMIRROR");
if (ret)
goto err_unreg;
 
-   for (id = 0; id < DMIRROR_NDEVICES; id++) {
+   memset(dmirror_devices, 0, DMIRROR_NDEVICES * 
sizeof(dmirror_devices[0]));
+   dmirror_devices[ndevices++].zone_device_type =
+   HMM_DMIRROR_MEMORY_DEVICE_PRIVATE;
+   dmirror_devices[ndevices++].zone_device_type =
+   HMM_DMIRROR_MEMORY_DEVICE_PRIVATE;
+   for (id = 0; id < ndevices; id++) {
ret = dmirror_device_init(dmirror_devices + id, id);
if (ret)
goto err_chrdev;
diff --git a/lib/test_hmm_uapi.h b/lib/test_hmm_uapi.h
index f14dea5dcd06..0511af7464ee 100644
--- a/lib/test_hmm_uapi.h
+++ b/lib/test_hmm_uapi.h
@@ -31,10 +31,11 @@ struct hmm_dmirror_cmd {
 /* Expose the address space of the calling process through hmm device file */
 #define HMM_DMIRROR_READ   _IOWR('H', 0x00, struct hmm_dmirror_cmd)
 #define HMM_DMIRROR_WRITE  _IOWR('H', 0x01, struct hmm_dmirror_cmd)
-#define HMM_DMIRROR_MIGRATE_IOWR('H', 0x02, struct hmm_dmirror_cmd)
-#define HMM_DMIRROR_SNAPSHOT   _IOWR('H', 0x03, struct hmm_dmirror_cmd)
-#define HMM_DMIRROR_EXCLUSIVE  _IOWR('H', 0x04, struct hmm_dmirror_cmd)
-#define HMM_DMIRROR_CHECK_EXCLUSIVE_IOWR('H', 0x05, struct hmm_dmirror_cmd)
+#define HMM_DMIRROR_MIGRATE_TO_DEV _IOWR('H', 0x02, struct hmm_dmirror_cmd)
+#define HMM_DMIRROR_MIGRATE_TO_SYS _IOWR('H', 0x03, struct hmm_dmirror_cmd)
+#define HMM_DMIRROR_SNAPSHOT   _IOWR('H', 0x04, struct hmm_dmirror_cmd)
+#define HMM_DMIRROR_EXCLUSIVE  _IOWR('H', 0x05, struct hmm_dmirror_cmd)
+#define HMM_DMIRROR_CHECK_EXCLUSIVE_IOWR('H', 0x06, struct hmm_dmirror_cmd)
 
 /*
  * Values returned in hmm_dmirror_cmd.ptr for HMM_DMIRROR_SNAPSHOT.
@@ -62,4 +63,9 @@ enum {
HMM_DMIRROR_PROT_DEV_PRIVATE_REMOTE = 0x30,
 };
 
+enum {
+   /* 0 is reserved to catch uninitialized type fields */
+   HMM_DMIRROR_MEMORY_DEVICE_PRIVATE = 1,
+};
+
 #endif /* _LIB_TEST_HMM_UAPI_H */
-- 
2.32.0

[PATCH v7 10/14] lib: add support for device coherent type in test_hmm

Device Coherent type uses device memory that is coherently accesible by
the CPU. This could be shown as SP (special purpose) memory range
at the BIOS-e820 memory enumeration. If no SP memory is supported in
system, this could be faked by setting CONFIG_EFI_FAKE_MEMMAP.

Currently, test_hmm only supports two different SP ranges of at least
256MB size. This could be specified in the kernel parameter variable
efi_fake_mem. Ex. Two SP ranges of 1GB starting at 0x1 &
0x14000 physical address. Ex.
efi_fake_mem=1G@0x1:0x4,1G@0x14000:0x4

Private and coherent device mirror instances can be created in the same
probed. This is done by passing the module parameters spm_addr_dev0 &
spm_addr_dev1. In this case, it will create four instances of
device_mirror. The first two correspond to private device type, the
last two to coherent type. Then, they can be easily accessed from user
space through /dev/hmm_mirror. Usually num_device 0 and 1
are for private, and 2 and 3 for coherent types. If no module
parameters are passed, two instances of private type device_mirror will
be created only.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Poppple 
---
 lib/test_hmm.c  | 253 +---
 lib/test_hmm_uapi.h |   4 +
 2 files changed, 196 insertions(+), 61 deletions(-)

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index afb30af9f3ff..7930853e7fc5 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -32,11 +32,22 @@
 
 #include "test_hmm_uapi.h"
 
-#define DMIRROR_NDEVICES   2
+#define DMIRROR_NDEVICES   4
 #define DMIRROR_RANGE_FAULT_TIMEOUT1000
 #define DEVMEM_CHUNK_SIZE  (256 * 1024 * 1024U)
 #define DEVMEM_CHUNKS_RESERVE  16
 
+/*
+ * For device_private pages, dpage is just a dummy struct page
+ * representing a piece of device memory. dmirror_devmem_alloc_page
+ * allocates a real system memory page as backing storage to fake a
+ * real device. zone_device_data points to that backing page. But
+ * for device_coherent memory, the struct page represents real
+ * physical CPU-accessible memory that we can use directly.
+ */
+#define BACKING_PAGE(page) (is_device_private_page((page)) ? \
+  (page)->zone_device_data : (page))
+
 static unsigned long spm_addr_dev0;
 module_param(spm_addr_dev0, long, 0644);
 MODULE_PARM_DESC(spm_addr_dev0,
@@ -125,6 +136,21 @@ static int dmirror_bounce_init(struct dmirror_bounce 
*bounce,
return 0;
 }
 
+static bool dmirror_is_private_zone(struct dmirror_device *mdevice)
+{
+   return (mdevice->zone_device_type ==
+   HMM_DMIRROR_MEMORY_DEVICE_PRIVATE) ? true : false;
+}
+
+static enum migrate_vma_direction
+dmirror_select_device(struct dmirror *dmirror)
+{
+   return (dmirror->mdevice->zone_device_type ==
+   HMM_DMIRROR_MEMORY_DEVICE_PRIVATE) ?
+   MIGRATE_VMA_SELECT_DEVICE_PRIVATE :
+   MIGRATE_VMA_SELECT_DEVICE_COHERENT;
+}
+
 static void dmirror_bounce_fini(struct dmirror_bounce *bounce)
 {
vfree(bounce->ptr);
@@ -575,16 +601,19 @@ static int dmirror_allocate_chunk(struct dmirror_device 
*mdevice,
 static struct page *dmirror_devmem_alloc_page(struct dmirror_device *mdevice)
 {
struct page *dpage = NULL;
-   struct page *rpage;
+   struct page *rpage = NULL;
 
/*
-* This is a fake device so we alloc real system memory to store
-* our device memory.
+* For ZONE_DEVICE private type, this is a fake device so we allocate
+* real system memory to store our device memory.
+* For ZONE_DEVICE coherent type we use the actual dpage to store the
+* data and ignore rpage.
 */
-   rpage = alloc_page(GFP_HIGHUSER);
-   if (!rpage)
-   return NULL;
-
+   if (dmirror_is_private_zone(mdevice)) {
+   rpage = alloc_page(GFP_HIGHUSER);
+   if (!rpage)
+   return NULL;
+   }
spin_lock(>lock);
 
if (mdevice->free_pages) {
@@ -603,7 +632,8 @@ static struct page *dmirror_devmem_alloc_page(struct 
dmirror_device *mdevice)
return dpage;
 
 error:
-   __free_page(rpage);
+   if (rpage)
+   __free_page(rpage);
return NULL;
 }
 
@@ -629,12 +659,16 @@ static void dmirror_migrate_alloc_and_copy(struct 
migrate_vma *args,
 * unallocated pte_none() or read-only zero page.
 */
spage = migrate_pfn_to_page(*src);
+   if (WARN(spage && is_zone_device_page(spage),
+"page already in device spage pfn: 0x%lx\n",
+page_to_pfn(spage)))
+   continue;
 
dpage = dmirror_devmem_alloc_page(mdevice);
if (!dpage)
continue;
 
-   rpage = dpage->zone_device_data;
+   rpage = BACKING_PAGE(dpage);

[PATCH v7 13/14] tools: add hmm gup tests for device coherent type

The intention is to test hmm device coherent type under different get
user pages paths. Also, test gup with FOLL_LONGTERM flag set in
device coherent pages. These pages should get migrated back to system
memory.

Signed-off-by: Alex Sierra 
Reviewed-by: Alistair Popple 
---
 tools/testing/selftests/vm/hmm-tests.c | 110 +
 1 file changed, 110 insertions(+)

diff --git a/tools/testing/selftests/vm/hmm-tests.c 
b/tools/testing/selftests/vm/hmm-tests.c
index 4b547188ec40..bb38b9777610 100644
--- a/tools/testing/selftests/vm/hmm-tests.c
+++ b/tools/testing/selftests/vm/hmm-tests.c
@@ -36,6 +36,7 @@
  * in the usual include/uapi/... directory.
  */
 #include "../../../../lib/test_hmm_uapi.h"
+#include "../../../../mm/gup_test.h"
 
 struct hmm_buffer {
void*ptr;
@@ -59,6 +60,9 @@ enum {
 #define NTIMES 10
 
 #define ALIGN(x, a) (((x) + (a - 1)) & (~((a) - 1)))
+/* Just the flags we need, copied from mm.h: */
+#define FOLL_WRITE 0x01/* check pte is writable */
+#define FOLL_LONGTERM   0x1 /* mapping lifetime is indefinite */
 
 FIXTURE(hmm)
 {
@@ -1764,4 +1768,110 @@ TEST_F(hmm, exclusive_cow)
hmm_buffer_free(buffer);
 }
 
+static int gup_test_exec(int gup_fd, unsigned long addr, int cmd,
+int npages, int size, int flags)
+{
+   struct gup_test gup = {
+   .nr_pages_per_call  = npages,
+   .addr   = addr,
+   .gup_flags  = FOLL_WRITE | flags,
+   .size   = size,
+   };
+
+   if (ioctl(gup_fd, cmd, )) {
+   perror("ioctl on error\n");
+   return errno;
+   }
+
+   return 0;
+}
+
+/*
+ * Test get user device pages through gup_test. Setting PIN_LONGTERM flag.
+ * This should trigger a migration back to system memory for both, private
+ * and coherent type pages.
+ * This test makes use of gup_test module. Make sure GUP_TEST_CONFIG is added
+ * to your configuration before you run it.
+ */
+TEST_F(hmm, hmm_gup_test)
+{
+   struct hmm_buffer *buffer;
+   int gup_fd;
+   unsigned long npages;
+   unsigned long size;
+   unsigned long i;
+   int *ptr;
+   int ret;
+   unsigned char *m;
+
+   gup_fd = open("/sys/kernel/debug/gup_test", O_RDWR);
+   if (gup_fd == -1)
+   SKIP(return, "Skipping test, could not find gup_test driver");
+
+   npages = 4;
+   size = npages << self->page_shift;
+
+   buffer = malloc(sizeof(*buffer));
+   ASSERT_NE(buffer, NULL);
+
+   buffer->fd = -1;
+   buffer->size = size;
+   buffer->mirror = malloc(size);
+   ASSERT_NE(buffer->mirror, NULL);
+
+   buffer->ptr = mmap(NULL, size,
+  PROT_READ | PROT_WRITE,
+  MAP_PRIVATE | MAP_ANONYMOUS,
+  buffer->fd, 0);
+   ASSERT_NE(buffer->ptr, MAP_FAILED);
+
+   /* Initialize buffer in system memory. */
+   for (i = 0, ptr = buffer->ptr; i < size / sizeof(*ptr); ++i)
+   ptr[i] = i;
+
+   /* Migrate memory to device. */
+   ret = hmm_migrate_sys_to_dev(self->fd, buffer, npages);
+   ASSERT_EQ(ret, 0);
+   ASSERT_EQ(buffer->cpages, npages);
+   /* Check what the device read. */
+   for (i = 0, ptr = buffer->mirror; i < size / sizeof(*ptr); ++i)
+   ASSERT_EQ(ptr[i], i);
+
+   ASSERT_EQ(gup_test_exec(gup_fd,
+   (unsigned long)buffer->ptr,
+   GUP_BASIC_TEST, 1, self->page_size, 0), 0);
+   ASSERT_EQ(gup_test_exec(gup_fd,
+   (unsigned long)buffer->ptr + 1 * 
self->page_size,
+   GUP_FAST_BENCHMARK, 1, self->page_size, 0), 0);
+   ASSERT_EQ(gup_test_exec(gup_fd,
+   (unsigned long)buffer->ptr + 2 * 
self->page_size,
+   PIN_FAST_BENCHMARK, 1, self->page_size, 
FOLL_LONGTERM), 0);
+   ASSERT_EQ(gup_test_exec(gup_fd,
+   (unsigned long)buffer->ptr + 3 * 
self->page_size,
+   PIN_LONGTERM_BENCHMARK, 1, self->page_size, 0), 
0);
+
+   /* Take snapshot to CPU pagetables */
+   ret = hmm_dmirror_cmd(self->fd, HMM_DMIRROR_SNAPSHOT, buffer, npages);
+   ASSERT_EQ(ret, 0);
+   ASSERT_EQ(buffer->cpages, npages);
+   m = buffer->mirror;
+   if (hmm_is_coherent_type(variant->device_number)) {
+   ASSERT_EQ(HMM_DMIRROR_PROT_DEV_COHERENT_LOCAL | 
HMM_DMIRROR_PROT_WRITE, m[0]);
+   ASSERT_EQ(HMM_DMIRROR_PROT_DEV_COHERENT_LOCAL | 
HMM_DMIRROR_PROT_WRITE, m[1]);
+   } else {
+   ASSERT_EQ(HMM_DMIRROR_PROT_WRITE, m[0]);
+   ASSERT_EQ(HMM_DMIRROR_PROT_WRITE, m[1]);
+   }
+   ASSERT_EQ(HMM_DMIRROR_PROT_WRITE, m[2]);
+   ASSERT_EQ(HMM_DMIRROR_PROT_WRITE, m[3]);
+   /*
+* Check again the content

[PATCH v7 06/14] mm/gup: migrate device coherent pages when pinning instead of failing

From: Alistair Popple 

Currently any attempts to pin a device coherent page will fail. This is
because device coherent pages need to be managed by a device driver, and
pinning them would prevent a driver from migrating them off the device.

However this is no reason to fail pinning of these pages. These are
coherent and accessible from the CPU so can be migrated just like
pinning ZONE_MOVABLE pages. So instead of failing all attempts to pin
them first try migrating them out of ZONE_DEVICE.

Signed-off-by: Alistair Popple 
Acked-by: Felix Kuehling 
[hch: rebased to the split device memory checks,
  moved migrate_device_page to migrate_device.c]
Signed-off-by: Christoph Hellwig 
---
 mm/gup.c| 47 +++-
 mm/internal.h   |  1 +
 mm/migrate_device.c | 53 +
 3 files changed, 96 insertions(+), 5 deletions(-)

diff --git a/mm/gup.c b/mm/gup.c
index b65fe8bf5af4..9b6b9923d22d 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -1891,9 +1891,43 @@ static long check_and_migrate_movable_pages(unsigned 
long nr_pages,
continue;
prev_folio = folio;
 
-   if (folio_is_longterm_pinnable(folio))
+   /*
+* Device private pages will get faulted in during gup so it
+* shouldn't be possible to see one here.
+*/
+   if (WARN_ON_ONCE(folio_is_device_private(folio))) {
+   ret = -EFAULT;
+   goto unpin_pages;
+   }
+
+   /*
+* Device coherent pages are managed by a driver and should not
+* be pinned indefinitely as it prevents the driver moving the
+* page. So when trying to pin with FOLL_LONGTERM instead try
+* to migrate the page out of device memory.
+*/
+   if (folio_is_device_coherent(folio)) {
+   WARN_ON_ONCE(PageCompound(>page));
+
+   /*
+* Migration will fail if the page is pinned, so convert
+* the pin on the source page to a normal reference.
+*/
+   if (gup_flags & FOLL_PIN) {
+   get_page(>page);
+   unpin_user_page(>page);
+   }
+
+   pages[i] = migrate_device_page(>page, gup_flags);
+   if (!pages[i]) {
+   ret = -EBUSY;
+   goto unpin_pages;
+   }
continue;
+   }
 
+   if (folio_is_longterm_pinnable(folio))
+   continue;
/*
 * Try to move out any movable page before pinning the range.
 */
@@ -1929,10 +1963,13 @@ static long check_and_migrate_movable_pages(unsigned 
long nr_pages,
return nr_pages;
 
 unpin_pages:
-   if (gup_flags & FOLL_PIN) {
-   unpin_user_pages(pages, nr_pages);
-   } else {
-   for (i = 0; i < nr_pages; i++)
+   for (i = 0; i < nr_pages; i++) {
+   if (!pages[i])
+   continue;
+
+   if (gup_flags & FOLL_PIN)
+   unpin_user_page(pages[i]);
+   else
put_page(pages[i]);
}
 
diff --git a/mm/internal.h b/mm/internal.h
index c0f8fbe0445b..eeab4ee7a4a3 100644
--- a/mm/internal.h
+++ b/mm/internal.h
@@ -853,6 +853,7 @@ int numa_migrate_prep(struct page *page, struct 
vm_area_struct *vma,
  unsigned long addr, int page_nid, int *flags);
 
 void free_zone_device_page(struct page *page);
+struct page *migrate_device_page(struct page *page, unsigned int gup_flags);
 
 /*
  * mm/gup.c
diff --git a/mm/migrate_device.c b/mm/migrate_device.c
index cf9668376c5a..5decd26dd551 100644
--- a/mm/migrate_device.c
+++ b/mm/migrate_device.c
@@ -794,3 +794,56 @@ void migrate_vma_finalize(struct migrate_vma *migrate)
}
 }
 EXPORT_SYMBOL(migrate_vma_finalize);
+
+/*
+ * Migrate a device coherent page back to normal memory.  The caller should 
have
+ * a reference on page which will be copied to the new page if migration is
+ * successful or dropped on failure.
+ */
+struct page *migrate_device_page(struct page *page, unsigned int gup_flags)
+{
+   unsigned long src_pfn, dst_pfn = 0;
+   struct migrate_vma args;
+   struct page *dpage;
+
+   lock_page(page);
+   src_pfn = migrate_pfn(page_to_pfn(page)) | MIGRATE_PFN_MIGRATE;
+   args.src = _pfn;
+   args.dst = _pfn;
+   args.cpages = 1;
+   args.npages = 1;
+   args.vma = NULL;
+   migrate_vma_setup();
+   if (!(src_pfn & MIGRATE_PFN_MIGRATE))
+   return NULL;
+
+   dpage = alloc_pages(GFP_USER | __GFP_NOWARN, 0);
+
+   /*
+*

[PATCH v7 11/14] tools: update hmm-test to support device coherent type

Test cases such as migrate_fault and migrate_multiple, were modified to
explicit migrate from device to sys memory without the need of page
faults, when using device coherent type.

Snapshot test case updated to read memory device type first and based
on that, get the proper returned results migrate_ping_pong test case
added to test explicit migration from device to sys memory for both
private and coherent zone types.

Helpers to migrate from device to sys memory and vicerversa
were also added.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Popple 
Signed-off-by: Christoph Hellwig 
---
 tools/testing/selftests/vm/hmm-tests.c | 121 -
 1 file changed, 100 insertions(+), 21 deletions(-)

diff --git a/tools/testing/selftests/vm/hmm-tests.c 
b/tools/testing/selftests/vm/hmm-tests.c
index 203323967b50..4b547188ec40 100644
--- a/tools/testing/selftests/vm/hmm-tests.c
+++ b/tools/testing/selftests/vm/hmm-tests.c
@@ -46,6 +46,13 @@ struct hmm_buffer {
uint64_tfaults;
 };
 
+enum {
+   HMM_PRIVATE_DEVICE_ONE,
+   HMM_PRIVATE_DEVICE_TWO,
+   HMM_COHERENCE_DEVICE_ONE,
+   HMM_COHERENCE_DEVICE_TWO,
+};
+
 #define TWOMEG (1 << 21)
 #define HMM_BUFFER_SIZE (1024 << 12)
 #define HMM_PATH_MAX64
@@ -60,6 +67,21 @@ FIXTURE(hmm)
unsigned intpage_shift;
 };
 
+FIXTURE_VARIANT(hmm)
+{
+   int device_number;
+};
+
+FIXTURE_VARIANT_ADD(hmm, hmm_device_private)
+{
+   .device_number = HMM_PRIVATE_DEVICE_ONE,
+};
+
+FIXTURE_VARIANT_ADD(hmm, hmm_device_coherent)
+{
+   .device_number = HMM_COHERENCE_DEVICE_ONE,
+};
+
 FIXTURE(hmm2)
 {
int fd0;
@@ -68,6 +90,24 @@ FIXTURE(hmm2)
unsigned intpage_shift;
 };
 
+FIXTURE_VARIANT(hmm2)
+{
+   int device_number0;
+   int device_number1;
+};
+
+FIXTURE_VARIANT_ADD(hmm2, hmm2_device_private)
+{
+   .device_number0 = HMM_PRIVATE_DEVICE_ONE,
+   .device_number1 = HMM_PRIVATE_DEVICE_TWO,
+};
+
+FIXTURE_VARIANT_ADD(hmm2, hmm2_device_coherent)
+{
+   .device_number0 = HMM_COHERENCE_DEVICE_ONE,
+   .device_number1 = HMM_COHERENCE_DEVICE_TWO,
+};
+
 static int hmm_open(int unit)
 {
char pathname[HMM_PATH_MAX];
@@ -81,12 +121,19 @@ static int hmm_open(int unit)
return fd;
 }
 
+static bool hmm_is_coherent_type(int dev_num)
+{
+   return (dev_num >= HMM_COHERENCE_DEVICE_ONE);
+}
+
 FIXTURE_SETUP(hmm)
 {
self->page_size = sysconf(_SC_PAGE_SIZE);
self->page_shift = ffs(self->page_size) - 1;
 
-   self->fd = hmm_open(0);
+   self->fd = hmm_open(variant->device_number);
+   if (self->fd < 0 && hmm_is_coherent_type(variant->device_number))
+   SKIP(exit(0), "DEVICE_COHERENT not available");
ASSERT_GE(self->fd, 0);
 }
 
@@ -95,9 +142,11 @@ FIXTURE_SETUP(hmm2)
self->page_size = sysconf(_SC_PAGE_SIZE);
self->page_shift = ffs(self->page_size) - 1;
 
-   self->fd0 = hmm_open(0);
+   self->fd0 = hmm_open(variant->device_number0);
+   if (self->fd0 < 0 && hmm_is_coherent_type(variant->device_number0))
+   SKIP(exit(0), "DEVICE_COHERENT not available");
ASSERT_GE(self->fd0, 0);
-   self->fd1 = hmm_open(1);
+   self->fd1 = hmm_open(variant->device_number1);
ASSERT_GE(self->fd1, 0);
 }
 
@@ -211,6 +260,20 @@ static void hmm_nanosleep(unsigned int n)
nanosleep(, NULL);
 }
 
+static int hmm_migrate_sys_to_dev(int fd,
+  struct hmm_buffer *buffer,
+  unsigned long npages)
+{
+   return hmm_dmirror_cmd(fd, HMM_DMIRROR_MIGRATE_TO_DEV, buffer, npages);
+}
+
+static int hmm_migrate_dev_to_sys(int fd,
+  struct hmm_buffer *buffer,
+  unsigned long npages)
+{
+   return hmm_dmirror_cmd(fd, HMM_DMIRROR_MIGRATE_TO_SYS, buffer, npages);
+}
+
 /*
  * Simple NULL test of device open/close.
  */
@@ -875,7 +938,7 @@ TEST_F(hmm, migrate)
ptr[i] = i;
 
/* Migrate memory to device. */
-   ret = hmm_dmirror_cmd(self->fd, HMM_DMIRROR_MIGRATE, buffer, npages);
+   ret = hmm_migrate_sys_to_dev(self->fd, buffer, npages);
ASSERT_EQ(ret, 0);
ASSERT_EQ(buffer->cpages, npages);
 
@@ -923,7 +986,7 @@ TEST_F(hmm, migrate_fault)
ptr[i] = i;
 
/* Migrate memory to device. */
-   ret = hmm_dmirror_cmd(self->fd, HMM_DMIRROR_MIGRATE, buffer, npages);
+   ret = hmm_migrate_sys_to_dev(self->fd, buffer, npages);
ASSERT_EQ(ret, 0);
ASSERT_EQ(buffer->cpages, npages);
 
@@ -936,7 +999,7 @@ TEST_F(hmm, migrate_fault)
ASSERT_EQ(ptr[i], i);
 
/* Migrate memory to the device again. */
-   ret = hmm_dmirror_cmd(self->fd, HMM_DMIRROR_MIGRATE, buffer, npages);
+   ret = hmm_migrate_sys_to_dev(self->fd, buffer, npages);
ASSERT_EQ(ret, 0);
ASSERT_EQ(buffer->cpages,

[PATCH v7 12/14] tools: update test_hmm script to support SP config

Add two more parameters to set spm_addr_dev0 & spm_addr_dev1
addresses. These two parameters configure the start SP
addresses for each device in test_hmm driver.
Consequently, this configures zone device type as coherent.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Popple 
Signed-off-by: Christoph Hellwig 
---
 tools/testing/selftests/vm/test_hmm.sh | 24 +---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/vm/test_hmm.sh 
b/tools/testing/selftests/vm/test_hmm.sh
index 0647b525a625..539c9371e592 100755
--- a/tools/testing/selftests/vm/test_hmm.sh
+++ b/tools/testing/selftests/vm/test_hmm.sh
@@ -40,11 +40,26 @@ check_test_requirements()
 
 load_driver()
 {
-   modprobe $DRIVER > /dev/null 2>&1
+   if [ $# -eq 0 ]; then
+   modprobe $DRIVER > /dev/null 2>&1
+   else
+   if [ $# -eq 2 ]; then
+   modprobe $DRIVER spm_addr_dev0=$1 spm_addr_dev1=$2
+   > /dev/null 2>&1
+   else
+   echo "Missing module parameters. Make sure pass"\
+   "spm_addr_dev0 and spm_addr_dev1"
+   usage
+   fi
+   fi
if [ $? == 0 ]; then
major=$(awk "\$2==\"HMM_DMIRROR\" {print \$1}" /proc/devices)
mknod /dev/hmm_dmirror0 c $major 0
mknod /dev/hmm_dmirror1 c $major 1
+   if [ $# -eq 2 ]; then
+   mknod /dev/hmm_dmirror2 c $major 2
+   mknod /dev/hmm_dmirror3 c $major 3
+   fi
fi
 }
 
@@ -58,7 +73,7 @@ run_smoke()
 {
echo "Running smoke test. Note, this test provides basic coverage."
 
-   load_driver
+   load_driver $1 $2
$(dirname "${BASH_SOURCE[0]}")/hmm-tests
unload_driver
 }
@@ -75,6 +90,9 @@ usage()
echo "# Smoke testing"
echo "./${TEST_NAME}.sh smoke"
echo
+   echo "# Smoke testing with SPM enabled"
+   echo "./${TEST_NAME}.sh smoke  "
+   echo
exit 0
 }
 
@@ -84,7 +102,7 @@ function run_test()
usage
else
if [ "$1" = "smoke" ]; then
-   run_smoke
+   run_smoke $2 $3
else
usage
fi
-- 
2.32.0

[PATCH v7 05/14] mm: remove the vma check in migrate_vma_setup()

From: Alistair Popple 

migrate_vma_setup() checks that a valid vma is passed so that the page
tables can be walked to find the pfns associated with a given address
range. However in some cases the pfns are already known, such as when
migrating device coherent pages during pin_user_pages() meaning a valid
vma isn't required.

Signed-off-by: Alistair Popple 
Acked-by: Felix Kuehling 
Signed-off-by: Christoph Hellwig 
---
 mm/migrate_device.c | 34 +-
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/mm/migrate_device.c b/mm/migrate_device.c
index 18bc6483f63a..cf9668376c5a 100644
--- a/mm/migrate_device.c
+++ b/mm/migrate_device.c
@@ -486,24 +486,24 @@ int migrate_vma_setup(struct migrate_vma *args)
 
args->start &= PAGE_MASK;
args->end &= PAGE_MASK;
-   if (!args->vma || is_vm_hugetlb_page(args->vma) ||
-   (args->vma->vm_flags & VM_SPECIAL) || vma_is_dax(args->vma))
-   return -EINVAL;
-   if (nr_pages <= 0)
-   return -EINVAL;
-   if (args->start < args->vma->vm_start ||
-   args->start >= args->vma->vm_end)
-   return -EINVAL;
-   if (args->end <= args->vma->vm_start || args->end > args->vma->vm_end)
-   return -EINVAL;
if (!args->src || !args->dst)
return -EINVAL;
-
-   memset(args->src, 0, sizeof(*args->src) * nr_pages);
-   args->cpages = 0;
-   args->npages = 0;
-
-   migrate_vma_collect(args);
+   if (args->vma) {
+   if (is_vm_hugetlb_page(args->vma) ||
+   (args->vma->vm_flags & VM_SPECIAL) || vma_is_dax(args->vma))
+   return -EINVAL;
+   if (args->start < args->vma->vm_start ||
+   args->start >= args->vma->vm_end)
+   return -EINVAL;
+   if (args->end <= args->vma->vm_start ||
+   args->end > args->vma->vm_end)
+   return -EINVAL;
+   memset(args->src, 0, sizeof(*args->src) * nr_pages);
+   args->cpages = 0;
+   args->npages = 0;
+
+   migrate_vma_collect(args);
+   }
 
if (args->cpages)
migrate_vma_unmap(args);
@@ -685,7 +685,7 @@ void migrate_vma_pages(struct migrate_vma *migrate)
continue;
}
 
-   if (!page) {
+   if (!page && migrate->vma) {
if (!(migrate->src[i] & MIGRATE_PFN_MIGRATE))
continue;
if (!notified) {
-- 
2.32.0

[PATCH v7 03/14] mm: handling Non-LRU pages returned by vm_normal_pages

With DEVICE_COHERENT, we'll soon have vm_normal_pages() return
device-managed anonymous pages that are not LRU pages. Although they
behave like normal pages for purposes of mapping in CPU page, and for
COW. They do not support LRU lists, NUMA migration or THP.

Callers to follow_page that expect LRU pages, are also checked for
device zone pages due to DEVICE_COHERENT type.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling  (v2)
Reviewed-by: Alistair Popple  (v6)
---
 fs/proc/task_mmu.c | 2 +-
 mm/huge_memory.c   | 2 +-
 mm/khugepaged.c| 9 ++---
 mm/ksm.c   | 6 +++---
 mm/madvise.c   | 4 ++--
 mm/memory.c| 9 -
 mm/mempolicy.c | 2 +-
 mm/migrate.c   | 4 ++--
 mm/mlock.c | 2 +-
 mm/mprotect.c  | 2 +-
 10 files changed, 26 insertions(+), 16 deletions(-)

diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 2d04e3470d4c..2dd8c8a66924 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -1792,7 +1792,7 @@ static struct page *can_gather_numa_stats(pte_t pte, 
struct vm_area_struct *vma,
return NULL;
 
page = vm_normal_page(vma, addr, pte);
-   if (!page)
+   if (!page || is_zone_device_page(page))
return NULL;
 
if (PageReserved(page))
diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 834f288b3769..c47e95b02244 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -2910,7 +2910,7 @@ static int split_huge_pages_pid(int pid, unsigned long 
vaddr_start,
 
if (IS_ERR(page))
continue;
-   if (!page)
+   if (!page || is_zone_device_page(page))
continue;
 
if (!is_transparent_hugepage(page))
diff --git a/mm/khugepaged.c b/mm/khugepaged.c
index 16be62d493cd..671ac7800e53 100644
--- a/mm/khugepaged.c
+++ b/mm/khugepaged.c
@@ -618,7 +618,7 @@ static int __collapse_huge_page_isolate(struct 
vm_area_struct *vma,
goto out;
}
page = vm_normal_page(vma, address, pteval);
-   if (unlikely(!page)) {
+   if (unlikely(!page) || unlikely(is_zone_device_page(page))) {
result = SCAN_PAGE_NULL;
goto out;
}
@@ -1267,7 +1267,7 @@ static int khugepaged_scan_pmd(struct mm_struct *mm,
writable = true;
 
page = vm_normal_page(vma, _address, pteval);
-   if (unlikely(!page)) {
+   if (unlikely(!page) || unlikely(is_zone_device_page(page))) {
result = SCAN_PAGE_NULL;
goto out_unmap;
}
@@ -1479,7 +1479,8 @@ void collapse_pte_mapped_thp(struct mm_struct *mm, 
unsigned long addr)
goto abort;
 
page = vm_normal_page(vma, addr, *pte);
-
+   if (WARN_ON_ONCE(page && is_zone_device_page(page)))
+   page = NULL;
/*
 * Note that uprobe, debugger, or MAP_PRIVATE may change the
 * page table, but the new page will not be a subpage of hpage.
@@ -1497,6 +1498,8 @@ void collapse_pte_mapped_thp(struct mm_struct *mm, 
unsigned long addr)
if (pte_none(*pte))
continue;
page = vm_normal_page(vma, addr, *pte);
+   if (WARN_ON_ONCE(page && is_zone_device_page(page)))
+   goto abort;
page_remove_rmap(page, vma, false);
}
 
diff --git a/mm/ksm.c b/mm/ksm.c
index 54f78c9eecae..831b18a7a50b 100644
--- a/mm/ksm.c
+++ b/mm/ksm.c
@@ -475,7 +475,7 @@ static int break_ksm(struct vm_area_struct *vma, unsigned 
long addr)
cond_resched();
page = follow_page(vma, addr,
FOLL_GET | FOLL_MIGRATION | FOLL_REMOTE);
-   if (IS_ERR_OR_NULL(page))
+   if (IS_ERR_OR_NULL(page) || is_zone_device_page(page))
break;
if (PageKsm(page))
ret = handle_mm_fault(vma, addr,
@@ -560,7 +560,7 @@ static struct page *get_mergeable_page(struct rmap_item 
*rmap_item)
goto out;
 
page = follow_page(vma, addr, FOLL_GET);
-   if (IS_ERR_OR_NULL(page))
+   if (IS_ERR_OR_NULL(page) || is_zone_device_page(page))
goto out;
if (PageAnon(page)) {
flush_anon_page(vma, page, addr);
@@ -2308,7 +2308,7 @@ static struct rmap_item *scan_get_next_rmap_item(struct 
page **page)
if (ksm_test_exit(mm))
break;
*page = follow_page(vma, ksm_scan.address, FOLL_GET);
-   if (IS_ERR_OR_NULL(*page)) {
+   if (IS_ERR_OR_NULL(*page) || 
is_zone_device_page(*page)) {
ksm_scan.address += PAGE_SIZE;

[PATCH v7 04/14] mm: add device coherent vma selection for memory migration

This case is used to migrate pages from device memory, back to system
memory. Device coherent type memory is cache coherent from device and CPU
point of view.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Poppple 
Signed-off-by: Christoph Hellwig 
---
 include/linux/migrate.h |  1 +
 mm/migrate_device.c | 12 +---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/include/linux/migrate.h b/include/linux/migrate.h
index 069a89e847f3..b84908debe5c 100644
--- a/include/linux/migrate.h
+++ b/include/linux/migrate.h
@@ -148,6 +148,7 @@ static inline unsigned long migrate_pfn(unsigned long pfn)
 enum migrate_vma_direction {
MIGRATE_VMA_SELECT_SYSTEM = 1 << 0,
MIGRATE_VMA_SELECT_DEVICE_PRIVATE = 1 << 1,
+   MIGRATE_VMA_SELECT_DEVICE_COHERENT = 1 << 2,
 };
 
 struct migrate_vma {
diff --git a/mm/migrate_device.c b/mm/migrate_device.c
index a4847ad65da3..18bc6483f63a 100644
--- a/mm/migrate_device.c
+++ b/mm/migrate_device.c
@@ -148,15 +148,21 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
if (is_writable_device_private_entry(entry))
mpfn |= MIGRATE_PFN_WRITE;
} else {
-   if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM))
-   goto next;
pfn = pte_pfn(pte);
-   if (is_zero_pfn(pfn)) {
+   if (is_zero_pfn(pfn) &&
+   (migrate->flags & MIGRATE_VMA_SELECT_SYSTEM)) {
mpfn = MIGRATE_PFN_MIGRATE;
migrate->cpages++;
goto next;
}
page = vm_normal_page(migrate->vma, addr, pte);
+   if (page && !is_zone_device_page(page) &&
+   !(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM))
+   goto next;
+   else if (page && is_device_coherent_page(page) &&
+   (!(migrate->flags & 
MIGRATE_VMA_SELECT_DEVICE_COHERENT) ||
+page->pgmap->owner != migrate->pgmap_owner))
+   goto next;
mpfn = migrate_pfn(pfn) | MIGRATE_PFN_MIGRATE;
mpfn |= pte_write(pte) ? MIGRATE_PFN_WRITE : 0;
}
-- 
2.32.0

[PATCH v7 07/14] drm/amdkfd: add SPM support for SVM

When CPU is connected throug XGMI, it has coherent
access to VRAM resource. In this case that resource
is taken from a table in the device gmc aperture base.
This resource is used along with the device type, which could
be DEVICE_PRIVATE or DEVICE_COHERENT to create the device
page map region.
Also, MIGRATE_VMA_SELECT_DEVICE_COHERENT flag is selected for
coherent type case during migration to device.

Signed-off-by: Alex Sierra 
Reviewed-by: Felix Kuehling 
Signed-off-by: Christoph Hellwig 
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 34 +++-
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index e44376c2ecdc..f73e3e340413 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -671,13 +671,15 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct 
svm_range *prange,
migrate.vma = vma;
migrate.start = start;
migrate.end = end;
-   migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev);
+   if (adev->gmc.xgmi.connected_to_cpu)
+   migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT;
+   else
+   migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
 
buf = kvcalloc(npages,
   2 * sizeof(*migrate.src) + sizeof(uint64_t) + 
sizeof(dma_addr_t),
   GFP_KERNEL);
-
if (!buf)
goto out;
 
@@ -947,7 +949,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
 {
struct kfd_dev *kfddev = adev->kfd.dev;
struct dev_pagemap *pgmap;
-   struct resource *res;
+   struct resource *res = NULL;
unsigned long size;
void *r;
 
@@ -962,28 +964,34 @@ int svm_migrate_init(struct amdgpu_device *adev)
 * should remove reserved size
 */
size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20);
-   res = devm_request_free_mem_region(adev->dev, _resource, size);
-   if (IS_ERR(res))
-   return -ENOMEM;
+   if (adev->gmc.xgmi.connected_to_cpu) {
+   pgmap->range.start = adev->gmc.aper_base;
+   pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 
1;
+   pgmap->type = MEMORY_DEVICE_COHERENT;
+   } else {
+   res = devm_request_free_mem_region(adev->dev, _resource, 
size);
+   if (IS_ERR(res))
+   return -ENOMEM;
+   pgmap->range.start = res->start;
+   pgmap->range.end = res->end;
+   pgmap->type = MEMORY_DEVICE_PRIVATE;
+   }
 
-   pgmap->type = MEMORY_DEVICE_PRIVATE;
pgmap->nr_range = 1;
-   pgmap->range.start = res->start;
-   pgmap->range.end = res->end;
pgmap->ops = _migrate_pgmap_ops;
pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev);
-   pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
-
+   pgmap->flags = 0;
/* Device manager releases device-specific resources, memory region and
 * pgmap when driver disconnects from device.
 */
r = devm_memremap_pages(adev->dev, pgmap);
if (IS_ERR(r)) {
pr_err("failed to register HMM device memory\n");
-
/* Disable SVM support capability */
pgmap->type = 0;
-   devm_release_mem_region(adev->dev, res->start, 
resource_size(res));
+   if (pgmap->type == MEMORY_DEVICE_PRIVATE)
+   devm_release_mem_region(adev->dev, res->start,
+   res->end - res->start + 1);
return PTR_ERR(r);
}
 
-- 
2.32.0

[PATCH v7 02/14] mm: add zone device coherent type memory support

Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a process can be migrated to such memory. However,
no one should be allowed to pin such memory so that it can always be
evicted.

Signed-off-by: Alex Sierra 
Acked-by: Felix Kuehling 
Reviewed-by: Alistair Popple 
[hch: rebased ontop of the refcount changes,
  removed is_dev_private_or_coherent_page]
Signed-off-by: Christoph Hellwig 
---
 include/linux/memremap.h | 22 +-
 mm/memcontrol.c  |  7 ---
 mm/memory-failure.c  |  8 ++--
 mm/memremap.c| 10 ++
 mm/migrate_device.c  | 16 +++-
 mm/rmap.c|  5 +++--
 6 files changed, 51 insertions(+), 17 deletions(-)

diff --git a/include/linux/memremap.h b/include/linux/memremap.h
index c272bd0af3c1..6fc0ced64b2d 100644
--- a/include/linux/memremap.h
+++ b/include/linux/memremap.h
@@ -41,6 +41,13 @@ struct vmem_altmap {
  * A more complete discussion of unaddressable memory may be found in
  * include/linux/hmm.h and Documentation/vm/hmm.rst.
  *
+ * MEMORY_DEVICE_COHERENT:
+ * Device memory that is cache coherent from device and CPU point of view. This
+ * is used on platforms that have an advanced system bus (like CAPI or CXL). A
+ * driver can hotplug the device memory using ZONE_DEVICE and with that memory
+ * type. Any page of a process can be migrated to such memory. However no one
+ * should be allowed to pin such memory so that it can always be evicted.
+ *
  * MEMORY_DEVICE_FS_DAX:
  * Host memory that has similar access semantics as System RAM i.e. DMA
  * coherent and supports page pinning. In support of coordinating page
@@ -61,6 +68,7 @@ struct vmem_altmap {
 enum memory_type {
/* 0 is reserved to catch uninitialized type fields */
MEMORY_DEVICE_PRIVATE = 1,
+   MEMORY_DEVICE_COHERENT,
MEMORY_DEVICE_FS_DAX,
MEMORY_DEVICE_GENERIC,
MEMORY_DEVICE_PCI_P2PDMA,
@@ -143,6 +151,17 @@ static inline bool folio_is_device_private(const struct 
folio *folio)
return is_device_private_page(>page);
 }
 
+static inline bool is_device_coherent_page(const struct page *page)
+{
+   return is_zone_device_page(page) &&
+   page->pgmap->type == MEMORY_DEVICE_COHERENT;
+}
+
+static inline bool folio_is_device_coherent(const struct folio *folio)
+{
+   return is_device_coherent_page(>page);
+}
+
 static inline bool is_pci_p2pdma_page(const struct page *page)
 {
return IS_ENABLED(CONFIG_PCI_P2PDMA) &&
@@ -160,7 +179,8 @@ static inline bool is_longterm_pinnable_page(struct page 
*page)
if (mt == MIGRATE_CMA || mt == MIGRATE_ISOLATE)
return false;
 #endif
-   return !(is_zone_movable_page(page) ||
+   return !(is_device_coherent_page(page) ||
+is_zone_movable_page(page) ||
 is_zero_pfn(page_to_pfn(page)));
 }
 #else
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 618c366a2f07..5d37a85c67da 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -5665,8 +5665,8 @@ static int mem_cgroup_move_account(struct page *page,
  *   2(MC_TARGET_SWAP): if the swap entry corresponding to this pte is a
  * target for charge migration. if @target is not NULL, the entry is stored
  * in target->ent.
- *   3(MC_TARGET_DEVICE): like MC_TARGET_PAGE  but page is 
MEMORY_DEVICE_PRIVATE
- * (so ZONE_DEVICE page and thus not on the lru).
+ *   3(MC_TARGET_DEVICE): like MC_TARGET_PAGE  but page is device memory and
+ *   thus not on the lru.
  * For now we such page is charge like a regular page would be as for all
  * intent and purposes it is just special memory taking the place of a
  * regular page.
@@ -5704,7 +5704,8 @@ static enum mc_target_type get_mctgt_type(struct 
vm_area_struct *vma,
 */
if (page_memcg(page) == mc.from) {
ret = MC_TARGET_PAGE;
-   if (is_device_private_page(page))
+   if (is_device_private_page(page) ||
+   is_device_coherent_page(page))
ret = MC_TARGET_DEVICE;
if (target)
target->page = page;
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index da39ec8afca8..79f175eeb190 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -1685,12 +1685,16 @@ static int memory_failure_dev_pagemap(unsigned long 
pfn, int flags,
goto unlock;
}
 
-   if (pgmap->type == MEMORY_DEVICE_PRIVATE) {
+   switch (pgmap->type) {
+   case MEMORY_DEVICE_PRIVATE:
+   case MEMORY_DEVICE_COHERENT:
/*
-* TODO: Handle HMM pages which may need coordination
+* TODO: Handle device pages which may need coordination
 * with device-side memory.
 */

[PATCH v7 01/14] mm: rename is_pinnable_pages to is_pinnable_longterm_pages

is_pinnable_page() and folio_is_pinnable() were renamed to
is_longterm_pinnable_page() and folio_is_longterm_pinnable()
respectively. These functions are used in the FOLL_LONGTERM flag
context.

Signed-off-by: Alex Sierra 
---
 include/linux/memremap.h | 24 
 include/linux/mm.h   | 24 
 mm/gup.c |  4 ++--
 mm/gup_test.c|  4 ++--
 mm/hugetlb.c |  2 +-
 5 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/include/linux/memremap.h b/include/linux/memremap.h
index 8af304f6b504..c272bd0af3c1 100644
--- a/include/linux/memremap.h
+++ b/include/linux/memremap.h
@@ -150,6 +150,30 @@ static inline bool is_pci_p2pdma_page(const struct page 
*page)
page->pgmap->type == MEMORY_DEVICE_PCI_P2PDMA;
 }
 
+/* MIGRATE_CMA and ZONE_MOVABLE do not allow pin pages */
+#ifdef CONFIG_MIGRATION
+static inline bool is_longterm_pinnable_page(struct page *page)
+{
+#ifdef CONFIG_CMA
+   int mt = get_pageblock_migratetype(page);
+
+   if (mt == MIGRATE_CMA || mt == MIGRATE_ISOLATE)
+   return false;
+#endif
+   return !(is_zone_movable_page(page) ||
+is_zero_pfn(page_to_pfn(page)));
+}
+#else
+static inline bool is_longterm_pinnable_page(struct page *page)
+{
+   return true;
+}
+#endif
+static inline bool folio_is_longterm_pinnable(struct folio *folio)
+{
+   return is_longterm_pinnable_page(>page);
+}
+
 #ifdef CONFIG_ZONE_DEVICE
 void *memremap_pages(struct dev_pagemap *pgmap, int nid);
 void memunmap_pages(struct dev_pagemap *pgmap);
diff --git a/include/linux/mm.h b/include/linux/mm.h
index cf3d0d673f6b..bc0f201a4cff 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1590,30 +1590,6 @@ static inline bool page_needs_cow_for_dma(struct 
vm_area_struct *vma,
return page_maybe_dma_pinned(page);
 }
 
-/* MIGRATE_CMA and ZONE_MOVABLE do not allow pin pages */
-#ifdef CONFIG_MIGRATION
-static inline bool is_pinnable_page(struct page *page)
-{
-#ifdef CONFIG_CMA
-   int mt = get_pageblock_migratetype(page);
-
-   if (mt == MIGRATE_CMA || mt == MIGRATE_ISOLATE)
-   return false;
-#endif
-   return !is_zone_movable_page(page) || is_zero_pfn(page_to_pfn(page));
-}
-#else
-static inline bool is_pinnable_page(struct page *page)
-{
-   return true;
-}
-#endif
-
-static inline bool folio_is_pinnable(struct folio *folio)
-{
-   return is_pinnable_page(>page);
-}
-
 static inline void set_page_zone(struct page *page, enum zone_type zone)
 {
page->flags &= ~(ZONES_MASK << ZONES_PGSHIFT);
diff --git a/mm/gup.c b/mm/gup.c
index 551264407624..b65fe8bf5af4 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -133,7 +133,7 @@ struct folio *try_grab_folio(struct page *page, int refs, 
unsigned int flags)
 * path.
 */
if (unlikely((flags & FOLL_LONGTERM) &&
-!is_pinnable_page(page)))
+!is_longterm_pinnable_page(page)))
return NULL;
 
/*
@@ -1891,7 +1891,7 @@ static long check_and_migrate_movable_pages(unsigned long 
nr_pages,
continue;
prev_folio = folio;
 
-   if (folio_is_pinnable(folio))
+   if (folio_is_longterm_pinnable(folio))
continue;
 
/*
diff --git a/mm/gup_test.c b/mm/gup_test.c
index d974dec19e1c..9d705ba6737e 100644
--- a/mm/gup_test.c
+++ b/mm/gup_test.c
@@ -1,5 +1,5 @@
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -53,7 +53,7 @@ static void verify_dma_pinned(unsigned int cmd, struct page 
**pages,
dump_page(page, "gup_test failure");
break;
} else if (cmd == PIN_LONGTERM_BENCHMARK &&
-   WARN(!is_pinnable_page(page),
+   WARN(!is_longterm_pinnable_page(page),
 "pages[%lu] is NOT pinnable but pinned\n",
 i)) {
dump_page(page, "gup_test failure");
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index a57e1be41401..368fd33787b0 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -1135,7 +1135,7 @@ static struct page *dequeue_huge_page_node_exact(struct 
hstate *h, int nid)
 
lockdep_assert_held(_lock);
list_for_each_entry(page, >hugepage_freelists[nid], lru) {
-   if (pin && !is_pinnable_page(page))
+   if (pin && !is_longterm_pinnable_page(page))
continue;
 
if (PageHWPoison(page))
-- 
2.32.0

[PATCH v7 00/14] Add MEMORY_DEVICE_COHERENT for coherent device memory mapping

This is our MEMORY_DEVICE_COHERENT patch series rebased and updated
for current 5.19.0-rc4

Changes since the last version:
- Fixed problems with migration during long-term pinning in
get_user_pages
- Open coded vm_normal_lru_pages as suggested in previous code review
- Update hmm_gup_test with more get_user_pages calls, include
hmm_cow_in_device in hmm-test.

This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
owned by a device that can be mapped into CPU page tables like
MEMORY_DEVICE_GENERIC and can also be migrated like
MEMORY_DEVICE_PRIVATE.

This patch series is mostly self-contained except for a few places where
it needs to update other subsystems to handle the new memory type.

System stability and performance are not affected according to our
ongoing testing, including xfstests.

How it works: The system BIOS advertises the GPU device memory
(aka VRAM) as SPM (special purpose memory) in the UEFI system address
map.

The amdgpu driver registers the memory with devmap as
MEMORY_DEVICE_COHERENT using devm_memremap_pages. The initial user for
this hardware page migration capability is the Frontier supercomputer
project. This functionality is not AMD-specific. We expect other GPU
vendors to find this functionality useful, and possibly other hardware
types in the future.

Our test nodes in the lab are similar to the Frontier configuration,
with .5 TB of system memory plus 256 GB of device memory split across
4 GPUs, all in a single coherent address space. Page migration is
expected to improve application efficiency significantly. We will
report empirical results as they become available.

Coherent device type pages at gup are now migrated back to system
memory if they are being pinned long-term (FOLL_LONGTERM). The reason
is, that long-term pinning would interfere with the device memory
manager owning the device-coherent pages (e.g. evictions in TTM).
These series incorporate Alistair Popple patches to do this
migration from pin_user_pages() calls. hmm_gup_test has been added to
hmm-test to test different get user pages calls.

This series includes handling of device-managed anonymous pages
returned by vm_normal_pages. Although they behave like normal pages
for purposes of mapping in CPU page tables and for COW, they do not
support LRU lists, NUMA migration or THP.

We also introduced a FOLL_LRU flag that adds the same behaviour to
follow_page and related APIs, to allow callers to specify that they
expect to put pages on an LRU list.

v2:
- Rebase to latest 5.18-rc7.
- Drop patch "mm: add device coherent checker to remove migration pte"
and modify try_to_migrate_one, to let DEVICE_COHERENT pages fall
through to normal page path. Based on Alistair Popple's comment.
- Fix comment formatting.
- Reword comment in vm_normal_page about pte_devmap().
- Merge "drm/amdkfd: coherent type as sys mem on migration to ram" to
"drm/amdkfd: add SPM support for SVM".

v3:
- Rebase to latest 5.18.0.
- Patch "mm: handling Non-LRU pages returned by vm_normal_pages"
reordered.
- Add WARN_ON_ONCE for thp device coherent case.

v4:
- Rebase to latest 5.18.0
- Fix consitency between pages with FOLL_LRU flag set and pte_devmap
at follow_page_pte.

v5:
- Remove unused zone_device_type from lib/test_hmm and
selftest/vm/hmm-test.c.

v6:
- Rebase to 5.19.0-rc4
- Rename is_pinnable_page to is_longterm_pinnable_page and add a
coherent device checker.
- Add a new gup test to hmm-test to cover fast pinnable case with
FOLL_LONGTERM.

v7:
- Reorder patch series.
- Remove FOLL_LRU and check on each caller for LRU pages handling
instead.

Alex Sierra (12):
  mm: rename is_pinnable_pages to is_pinnable_longterm_pages
  mm: add zone device coherent type memory support
  mm: handling Non-LRU pages returned by vm_normal_pages
  mm: add device coherent vma selection for memory migration
  drm/amdkfd: add SPM support for SVM
  lib: test_hmm add ioctl to get zone device type
  lib: test_hmm add module param for zone device type
  lib: add support for device coherent type in test_hmm
  tools: update hmm-test to support device coherent type
  tools: update test_hmm script to support SP config
  tools: add hmm gup tests for device coherent type
  tools: add selftests to hmm for COW in device memory

Alistair Popple (2):
  mm: remove the vma check in migrate_vma_setup()
  mm/gup: migrate device coherent pages when pinning instead of failing

 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c |  34 ++-
 fs/proc/task_mmu.c   |   2 +-
 include/linux/memremap.h |  44 +++
 include/linux/migrate.h  |   1 +
 include/linux/mm.h   |  24 --
 lib/test_hmm.c   | 337 +--
 lib/test_hmm_uapi.h  |  19 +-
 mm/gup.c |  49 +++-
 mm/gup_test.c|   4 +-
 mm/huge_memory.c |   2 +-
 mm/hugetlb.c |   2 +-
 mm/internal.h

[Bug 201957] amdgpu: ring gfx timeout

https://bugzilla.kernel.org/show_bug.cgi?id=201957

rafael castillo (jrch2...@gmail.com) changed:

   What|Removed |Added

 CC||jrch2...@gmail.com

--- Comment #80 from rafael castillo (jrch2...@gmail.com) ---
same issue here with (also LTS kernel as well)

Linux archlinux 5.18.7-262-tkg-pds #1 TKG SMP PREEMPT_DYNAMIC Mon, 27 Jun 2022
15:50:06 + x86_64 GNU/Linux

[11090.086287] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.086296] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.086302] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.195133] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.195139] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.195143] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.195150] [drm] Cannot get clockgating state when UVD is powergated.
[11090.195152] [drm] Cannot get clockgating state when VCE is powergated.
[11090.695288] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11090.699331] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11091.194893] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11091.194898] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11091.194901] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11091.194908] [drm] Cannot get clockgating state when UVD is powergated.
[11091.194909] [drm] Cannot get clockgating state when VCE is powergated.
[11091.695473] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11092.194965] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11092.194969] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11092.194973] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11092.194979] [drm] Cannot get clockgating state when UVD is powergated.
[11092.194980] [drm] Cannot get clockgating state when VCE is powergated.
[11092.695749] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11093.195046] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11093.195050] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11093.195053] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11093.195060] [drm] Cannot get clockgating state when UVD is powergated.
[11093.195061] [drm] Cannot get clockgating state when VCE is powergated.
[11093.695004] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11094.195065] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11094.195070] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11094.195074] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11094.195082] [drm] Cannot get clockgating state when UVD is powergated.
[11094.195083] [drm] Cannot get clockgating state when VCE is powergated.
[11094.695286] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11095.131026] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for
fences timed out!
[11095.195055] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11095.195061] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11095.195065] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11095.195071] [drm] Cannot get clockgating state when UVD is powergated.
[11095.195072] [drm] Cannot get clockgating state when VCE is powergated.
[11095.695232] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11096.195132] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11096.195137] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11096.195140] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11096.195146] [drm] Cannot get clockgating state when UVD is powergated.
[11096.195147] [drm] Cannot get clockgating state when VCE is powergated.
[11096.694900] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11097.195057] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11097.195061] amdgpu :02:00.0: amdgpu: 
   last message was failed ret is 65535
[11097.195064] amdgpu :02:00.0: amdgpu:

linux-next: manual merge of the drm-misc tree with Linus' tree

2022-06-28 Thread Stephen Rothwell

Hi all,

Today's linux-next merge of the drm-misc tree got a conflict in:

  drivers/gpu/drm/vc4/vc4_drv.c

between commit:

  538f6061 ("drm/vc4: drv: Register a different driver on BCM2711")

from Linus' tree and commit:

  da8e393e23ef ("drm/vc4: drv: Adopt the dma configuration from the HVS or V3D 
component")

from the drm-misc tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/vc4/vc4_drv.c
index 0f0f0263e744,14a7d529144d..
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@@ -281,16 -230,25 +290,26 @@@ static int vc4_drm_bind(struct device *
  
dev->coherent_dma_mask = DMA_BIT_MASK(32);
  
 -  /* If VC4 V3D is missing, don't advertise render nodes. */
 -  node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
 -  if (!node || !of_device_is_available(node))
 -  vc4_drm_driver.driver_features &= ~DRIVER_RENDER;
 -  of_node_put(node);
 +  is_vc5 = of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5");
 +  if (is_vc5)
 +  driver = _drm_driver;
 +  else
 +  driver = _drm_driver;
  
+   node = of_find_matching_node_and_match(NULL, vc4_dma_range_matches,
+  NULL);
+   if (node) {
+   ret = of_dma_configure(dev, node, true);
+   of_node_put(node);
+ 
+   if (ret)
+   return ret;
+   }
+ 
 -  vc4 = devm_drm_dev_alloc(dev, _drm_driver, struct vc4_dev, base);
 +  vc4 = devm_drm_dev_alloc(dev, driver, struct vc4_dev, base);
if (IS_ERR(vc4))
return PTR_ERR(vc4);
 +  vc4->is_vc5 = is_vc5;
  
drm = >base;
platform_set_drvdata(pdev, drm);


pgpmdo9pUdKVc.pgp
Description: OpenPGP digital signature

[Bug 216173] amdgpu [gfxhub] page fault (src_id:0 ring:173 vmid:1 pasid:32769, for process Xorg pid 2994 thread Xorg:cs0 pid 3237)

https://bugzilla.kernel.org/show_bug.cgi?id=216173

--- Comment #9 from Witold Baryluk (witold.baryluk+ker...@gmail.com) ---
Bisected:

9cad937c0c58618fe5b0310fd539a854dc1ae95 is the first bad commit
commit c9cad937c0c58618fe5b0310fd539a854dc1ae95
Author: Arunpravin Paneer Selvam 
Date:   Fri Apr 8 04:18:43 2022 +0530

drm/amdgpu: add drm buddy support to amdgpu

-- 
You may reply to this email to add a comment.

You are receiving this mail because:
You are watching the assignee of the bug.

[PATCH] drm/i915: Remove __dma_fence_is_chain()

2022-06-28 Thread Rob Clark

From: Rob Clark 

drive-by cleanup

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/i915/gem/i915_gem_wait.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c 
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 319936f91ac5..667841780514 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -73,11 +73,6 @@ static void fence_set_priority(struct dma_fence *fence,
rcu_read_unlock();
 }
 
-static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
-{
-   return fence->ops == _fence_chain_ops;
-}
-
 void i915_gem_fence_wait_priority(struct dma_fence *fence,
  const struct i915_sched_attr *attr)
 {
@@ -93,7 +88,7 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
 
for (i = 0; i < array->num_fences; i++)
fence_set_priority(array->fences[i], attr);
-   } else if (__dma_fence_is_chain(fence)) {
+   } else if (dma_fence_is_chain(fence)) {
struct dma_fence *iter;
 
/* The chain is ordered; if we boost the last, we boost all */
-- 
2.36.1

Re: [PATCH v6 00/22] Add generic memory shrinker to VirtIO-GPU and Panfrost DRM drivers

2022-06-28 Thread Dmitry Osipenko

On 6/28/22 19:48, Rob Clark wrote:
> On Tue, Jun 28, 2022 at 5:51 AM Dmitry Osipenko
>  wrote:
>>
>> On 6/28/22 15:31, Robin Murphy wrote:
>>> ->8-
>>> [   68.295951] ==
>>> [   68.295956] WARNING: possible circular locking dependency detected
>>> [   68.295963] 5.19.0-rc3+ #400 Not tainted
>>> [   68.295972] --
>>> [   68.295977] cc1/295 is trying to acquire lock:
>>> [   68.295986] 08d7f1a0
>>> (reservation_ww_class_mutex){+.+.}-{3:3}, at: drm_gem_shmem_free+0x7c/0x198
>>> [   68.296036]
>>> [   68.296036] but task is already holding lock:
>>> [   68.296041] 8c14b820 (fs_reclaim){+.+.}-{0:0}, at:
>>> __alloc_pages_slowpath.constprop.0+0x4d8/0x1470
>>> [   68.296080]
>>> [   68.296080] which lock already depends on the new lock.
>>> [   68.296080]
>>> [   68.296085]
>>> [   68.296085] the existing dependency chain (in reverse order) is:
>>> [   68.296090]
>>> [   68.296090] -> #1 (fs_reclaim){+.+.}-{0:0}:
>>> [   68.296111]fs_reclaim_acquire+0xb8/0x150
>>> [   68.296130]dma_resv_lockdep+0x298/0x3fc
>>> [   68.296148]do_one_initcall+0xe4/0x5f8
>>> [   68.296163]kernel_init_freeable+0x414/0x49c
>>> [   68.296180]kernel_init+0x2c/0x148
>>> [   68.296195]ret_from_fork+0x10/0x20
>>> [   68.296207]
>>> [   68.296207] -> #0 (reservation_ww_class_mutex){+.+.}-{3:3}:
>>> [   68.296229]__lock_acquire+0x1724/0x2398
>>> [   68.296246]lock_acquire+0x218/0x5b0
>>> [   68.296260]__ww_mutex_lock.constprop.0+0x158/0x2378
>>> [   68.296277]ww_mutex_lock+0x7c/0x4d8
>>> [   68.296291]drm_gem_shmem_free+0x7c/0x198
>>> [   68.296304]panfrost_gem_free_object+0x118/0x138
>>> [   68.296318]drm_gem_object_free+0x40/0x68
>>> [   68.296334]drm_gem_shmem_shrinker_run_objects_scan+0x42c/0x5b8
>>> [   68.296352]drm_gem_shmem_shrinker_scan_objects+0xa4/0x170
>>> [   68.296368]do_shrink_slab+0x220/0x808
>>> [   68.296381]shrink_slab+0x11c/0x408
>>> [   68.296392]shrink_node+0x6ac/0xb90
>>> [   68.296403]do_try_to_free_pages+0x1dc/0x8d0
>>> [   68.296416]try_to_free_pages+0x1ec/0x5b0
>>> [   68.296429]__alloc_pages_slowpath.constprop.0+0x528/0x1470
>>> [   68.296444]__alloc_pages+0x4e0/0x5b8
>>> [   68.296455]__folio_alloc+0x24/0x60
>>> [   68.296467]vma_alloc_folio+0xb8/0x2f8
>>> [   68.296483]alloc_zeroed_user_highpage_movable+0x58/0x68
>>> [   68.296498]__handle_mm_fault+0x918/0x12a8
>>> [   68.296513]handle_mm_fault+0x130/0x300
>>> [   68.296527]do_page_fault+0x1d0/0x568
>>> [   68.296539]do_translation_fault+0xa0/0xb8
>>> [   68.296551]do_mem_abort+0x68/0xf8
>>> [   68.296562]el0_da+0x74/0x100
>>> [   68.296572]el0t_64_sync_handler+0x68/0xc0
>>> [   68.296585]el0t_64_sync+0x18c/0x190
>>> [   68.296596]
>>> [   68.296596] other info that might help us debug this:
>>> [   68.296596]
>>> [   68.296601]  Possible unsafe locking scenario:
>>> [   68.296601]
>>> [   68.296604]CPU0CPU1
>>> [   68.296608]
>>> [   68.296612]   lock(fs_reclaim);
>>> [   68.296622] lock(reservation_ww_class_mutex);
>>> [   68.296633]lock(fs_reclaim);
>>> [   68.296644]   lock(reservation_ww_class_mutex);
>>> [   68.296654]
>>> [   68.296654]  *** DEADLOCK ***
>>
>> This splat could be ignored for now. I'm aware about it, although
>> haven't looked closely at how to fix it since it's a kind of a lockdep
>> misreporting.
> 
> The lockdep splat could be fixed with something similar to what I've
> done in msm, ie. basically just not acquire the lock in the finalizer:
> 
> https://patchwork.freedesktop.org/patch/489364/
> 
> There is one gotcha to watch for, as danvet pointed out
> (scan_objects() could still see the obj in the LRU before the
> finalizer removes it), but if scan_objects() does the
> kref_get_unless_zero() trick, it is safe.

Nice, thank you!

-- 
Best regards,
Dmitry

Re: [PATCH RESEND] drm: i915: fix a possible refcount leak in intel_dp_add_mst_connector()

Ah-nevermind! Seems like someone already pushed this for you :)

On Tue, 2022-06-28 at 18:55 -0400, Lyude Paul wrote:
> Nice catch!
> 
> Reviewed-by: Lyude Paul 
> 
> Will push to drm-intel-next
> 
> On Fri, 2022-06-24 at 10:28 +0800, Hangyu Hua wrote:
> > If drm_connector_init fails, intel_connector_free will be called to take
> > care of proper free. So it is necessary to drop the refcount of port
> > before intel_connector_free.
> > 
> > Fixes: 091a4f91942a ("drm/i915: Handle drm-layer errors in
> > intel_dp_add_mst_connector")
> > Signed-off-by: Hangyu Hua 
> > Reviewed-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 061b277e5ce7..14d2a64193b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -839,6 +839,7 @@ static struct drm_connector
> > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > ret = drm_connector_init(dev, connector,
> > _dp_mst_connector_funcs,
> >  DRM_MODE_CONNECTOR_DisplayPort);
> > if (ret) {
> > +   drm_dp_mst_put_port_malloc(port);
> > intel_connector_free(intel_connector);
> > return NULL;
> > }
> 

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [PATCH RESEND] drm: i915: fix a possible refcount leak in intel_dp_add_mst_connector()

Nice catch!

Reviewed-by: Lyude Paul 

Will push to drm-intel-next

On Fri, 2022-06-24 at 10:28 +0800, Hangyu Hua wrote:
> If drm_connector_init fails, intel_connector_free will be called to take
> care of proper free. So it is necessary to drop the refcount of port
> before intel_connector_free.
> 
> Fixes: 091a4f91942a ("drm/i915: Handle drm-layer errors in
> intel_dp_add_mst_connector")
> Signed-off-by: Hangyu Hua 
> Reviewed-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 061b277e5ce7..14d2a64193b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -839,6 +839,7 @@ static struct drm_connector
> *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> ret = drm_connector_init(dev, connector,
> _dp_mst_connector_funcs,
>  DRM_MODE_CONNECTOR_DisplayPort);
> if (ret) {
> +   drm_dp_mst_put_port_malloc(port);
> intel_connector_free(intel_connector);
> return NULL;
> }

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [PATCH] gpu: drm: selftests: drop unexpected word 'for' in comments

Oh-it's back up now! will push now :)

On Tue, 2022-06-28 at 17:35 -0400, Lyude Paul wrote:
> …ah, I totally forgot that gitlab happens to be down right now which part of
> the DRM maintainer scripts rely on - so I can't actually push this patch
> upstream right away. I will set this email as unread so hopefully I don't
> lose
> track of this, but please feel free to ping me if I do end up forgetting.
> 
> On Tue, 2022-06-28 at 17:32 -0400, Lyude Paul wrote:
> > Reviewed-by: Lyude Paul 
> > 
> > Going to change the name of the patch slightly so it's more obvious this
> > is
> > just about the MST selftests
> > 
> > On Thu, 2022-06-23 at 18:06 +0800, Jiang Jian wrote:
> > > there is an unexpected word 'for' in the comments that need to be
> > > dropped
> > > 
> > > file - ./drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > > line - 3
> > > 
> > > * Test cases for for the DRM DP MST helpers
> > > 
> > > changed to:
> > > 
> > > * Test cases for the DRM DP MST helpers
> > > 
> > > Signed-off-by: Jiang Jian 
> > > ---
> > >  drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > > b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > > index 967c52150b67..4caa9be900ac 100644
> > > --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > > +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > > @@ -1,6 +1,6 @@
> > >  // SPDX-License-Identifier: GPL-2.0-only
> > >  /*
> > > - * Test cases for for the DRM DP MST helpers
> > > + * Test cases for the DRM DP MST helpers
> > >   */
> > >  
> > >  #define PREFIX_STR "[drm_dp_mst_helper]"
> > 
> 

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [PATCH v1] drm/tegra: Fix vmapping of prime buffers

2022-06-28 Thread Dmitry Osipenko

On 6/29/22 01:42, Dmitry Osipenko wrote:
> The code assumes that Tegra GEM is permanently vmapped, which is not
> true for the scattered buffers. After converting Tegra video decoder
> driver to V4L API, we're now getting a BUG_ON from dma-buf core on playing
> video using libvdpau-tegra on T30+ because tegra_gem_prime_vmap() sets
> vaddr to NULL. Older pre-V4L video decoder driver wasn't vmapping dma-bufs.
> Fix it by actually vmapping the exported GEMs.
> 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Dmitry Osipenko 
> ---
>  drivers/gpu/drm/tegra/gem.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
> index 7c7dd84e6db8..81991090adcc 100644
> --- a/drivers/gpu/drm/tegra/gem.c
> +++ b/drivers/gpu/drm/tegra/gem.c
> @@ -704,14 +704,23 @@ static int tegra_gem_prime_vmap(struct dma_buf *buf, 
> struct iosys_map *map)
>  {
>   struct drm_gem_object *gem = buf->priv;
>   struct tegra_bo *bo = to_tegra_bo(gem);
> + void *vaddr;
>  
> - iosys_map_set_vaddr(map, bo->vaddr);
> + vaddr = tegra_bo_mmap(>base);
> + if (IS_ERR(vaddr))
> + return PTR_ERR(vaddr);
> +
> + iosys_map_set_vaddr(map, vaddr);
>  
>   return 0;
>  }
>  
>  static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct iosys_map 
> *map)
>  {
> + struct drm_gem_object *gem = buf->priv;
> + struct tegra_bo *bo = to_tegra_bo(gem);
> +
> + tegra_bo_munmap(>base, map->vaddr);
>  }
>  
>  static const struct dma_buf_ops tegra_gem_prime_dmabuf_ops = {

BTW, previously I only tested video dec on T30 using the grate-driver
kernel that properly vmaps GEMs. That's why it wasn't caught earlier.

-- 
Best regards,
Dmitry

[PATCH v1] drm/tegra: Fix vmapping of prime buffers

2022-06-28 Thread Dmitry Osipenko

The code assumes that Tegra GEM is permanently vmapped, which is not
true for the scattered buffers. After converting Tegra video decoder
driver to V4L API, we're now getting a BUG_ON from dma-buf core on playing
video using libvdpau-tegra on T30+ because tegra_gem_prime_vmap() sets
vaddr to NULL. Older pre-V4L video decoder driver wasn't vmapping dma-bufs.
Fix it by actually vmapping the exported GEMs.

Cc: sta...@vger.kernel.org
Signed-off-by: Dmitry Osipenko 
---
 drivers/gpu/drm/tegra/gem.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 7c7dd84e6db8..81991090adcc 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -704,14 +704,23 @@ static int tegra_gem_prime_vmap(struct dma_buf *buf, 
struct iosys_map *map)
 {
struct drm_gem_object *gem = buf->priv;
struct tegra_bo *bo = to_tegra_bo(gem);
+   void *vaddr;
 
-   iosys_map_set_vaddr(map, bo->vaddr);
+   vaddr = tegra_bo_mmap(>base);
+   if (IS_ERR(vaddr))
+   return PTR_ERR(vaddr);
+
+   iosys_map_set_vaddr(map, vaddr);
 
return 0;
 }
 
 static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct iosys_map *map)
 {
+   struct drm_gem_object *gem = buf->priv;
+   struct tegra_bo *bo = to_tegra_bo(gem);
+
+   tegra_bo_munmap(>base, map->vaddr);
 }
 
 static const struct dma_buf_ops tegra_gem_prime_dmabuf_ops = {
-- 
2.36.1

[PATCH v2 32/32] drm/via: Modify DRM core to be able to build OpenChrome DRM

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/Kconfig  | 2 ++
 drivers/gpu/drm/Makefile | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 30d5b91b717f..475d20c58da0 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -385,6 +385,8 @@ source "drivers/gpu/drm/solomon/Kconfig"

 source "drivers/gpu/drm/sprd/Kconfig"

+source "drivers/gpu/drm/via/Kconfig"
+
 config DRM_HYPERV
tristate "DRM Support for Hyper-V synthetic video device"
depends on DRM && PCI && MMU && HYPERV
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index e6d0daca9bc2..72c6db91ee61 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_DRM_VC4)  += vc4/
 obj-$(CONFIG_DRM_SIS)   += sis/
 obj-$(CONFIG_DRM_SAVAGE)+= savage/
 obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/
+obj-$(CONFIG_DRM_OPENCHROME) +=via/
 obj-$(CONFIG_DRM_VGEM) += vgem/
 obj-$(CONFIG_DRM_VKMS) += vkms/
 obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/
--
2.35.1

[PATCH v2 31/32] drm/via: Add Makefile

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/Makefile | 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 drivers/gpu/drm/via/Makefile

diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
new file mode 100644
index ..73ccacb4cd11
--- /dev/null
+++ b/drivers/gpu/drm/via/Makefile
@@ -0,0 +1,26 @@
+#
+# Makefile for the drm device driver.  This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+
+ccflags-y := -Iinclude/drm
+via-y := via_crtc.o \
+   via_crtc_hw.o \
+   via_cursor.o \
+   via_dac.o \
+   via_display.o \
+   via_drv.o \
+   via_encoder.o \
+   via_hdmi.o \
+   via_i2c.o \
+   via_init.o \
+   via_ioctl.o \
+   via_lvds.o \
+   via_object.o \
+   via_pll.o \
+   via_pm.o \
+   via_sii164.o \
+   via_tmds.o \
+   via_ttm.o \
+   via_vt1632.o
+
+obj-$(CONFIG_DRM_OPENCHROME)   += via.o
--
2.35.1

[PATCH v2 30/32] drm/via: Add Kconfig

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/Kconfig | 10 ++
 1 file changed, 10 insertions(+)
 create mode 100644 drivers/gpu/drm/via/Kconfig

diff --git a/drivers/gpu/drm/via/Kconfig b/drivers/gpu/drm/via/Kconfig
new file mode 100644
index ..760bf5906d3c
--- /dev/null
+++ b/drivers/gpu/drm/via/Kconfig
@@ -0,0 +1,10 @@
+config DRM_OPENCHROME
+   tristate "OpenChrome (VIA Technologies)"
+   depends on DRM && PCI && X86
+   select DRM_KMS_HELPER
+   select DRM_TTM
+   help
+ Choose this option if you have VIA Technologies UniChrome or
+ Chrome9 integrated graphics. If M is selected the module will
+ be called via.
+
--
2.35.1

[PATCH v2 28/32] drm/via: Zero out chip type field

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 include/drm/drm_pciids.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e91b93d635fa..a4567d2918a9 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -770,18 +770,18 @@

 #define viadrv_PCI_IDS \
{0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-   {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
+   {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-   {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
-   {0x1106, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
-   {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
-   {0x1106, 0x1122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
-   {0x1106, 0x5122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
-   {0x1106, 0x7122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
+   {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+   {0x1106, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+   {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+   {0x1106, 0x1122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+   {0x1106, 0x5122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+   {0x1106, 0x7122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0, 0, 0}

 #define i810_PCI_IDS \
--
2.35.1

[PATCH v2 29/32] drm/via: Add new VIA Technologies PCI device IDs related to graphics

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 include/linux/pci_ids.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0178823ce8c2..809c61a10fe1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1423,8 +1423,11 @@
 #define PCI_DEVICE_ID_VIA_VT3324   0x0324
 #define PCI_DEVICE_ID_VIA_VT3336   0x0336
 #define PCI_DEVICE_ID_VIA_VT3351   0x0351
+#define PCI_DEVICE_ID_VIA_VT3353   0x0353
 #define PCI_DEVICE_ID_VIA_VT3364   0x0364
 #define PCI_DEVICE_ID_VIA_8371_0   0x0391
+#define PCI_DEVICE_ID_VIA_VT3409   0x0409
+#define PCI_DEVICE_ID_VIA_VT3410   0x0410
 #define PCI_DEVICE_ID_VIA_6415 0x0415
 #define PCI_DEVICE_ID_VIA_8501_0   0x0501
 #define PCI_DEVICE_ID_VIA_82C561   0x0561
@@ -1438,6 +1441,7 @@
 #define PCI_DEVICE_ID_VIA_8605_0   0x0605
 #define PCI_DEVICE_ID_VIA_82C686   0x0686
 #define PCI_DEVICE_ID_VIA_82C691_0 0x0691
+#define PCI_DEVICE_ID_VIA_VT1122   0x1122
 #define PCI_DEVICE_ID_VIA_82C576_1 0x1571
 #define PCI_DEVICE_ID_VIA_82C586_2 0x3038
 #define PCI_DEVICE_ID_VIA_82C586_3 0x3040
@@ -1452,16 +1456,20 @@
 #define PCI_DEVICE_ID_VIA_8653_0   0x3101
 #define PCI_DEVICE_ID_VIA_8622 0x3102
 #define PCI_DEVICE_ID_VIA_8235_USB_2   0x3104
+#define PCI_DEVICE_ID_VIA_K8M800   0x3108
 #define PCI_DEVICE_ID_VIA_8233C_0  0x3109
 #define PCI_DEVICE_ID_VIA_8361 0x3112
 #define PCI_DEVICE_ID_VIA_XM2660x3116
+#define PCI_DEVICE_ID_VIA_PM8000x3118
 #define PCI_DEVICE_ID_VIA_612X 0x3119
+#define PCI_DEVICE_ID_VIA_CLE266   0x3122
 #define PCI_DEVICE_ID_VIA_862X_0   0x3123
 #define PCI_DEVICE_ID_VIA_8753_0   0x3128
 #define PCI_DEVICE_ID_VIA_8233A0x3147
 #define PCI_DEVICE_ID_VIA_8703_51_00x3148
 #define PCI_DEVICE_ID_VIA_8237_SATA0x3149
 #define PCI_DEVICE_ID_VIA_XN2660x3156
+#define PCI_DEVICE_ID_VIA_VT3157   0x3157
 #define PCI_DEVICE_ID_VIA_6410 0x3164
 #define PCI_DEVICE_ID_VIA_8754C_0  0x3168
 #define PCI_DEVICE_ID_VIA_8235 0x3177
@@ -1470,11 +1478,18 @@
 #define PCI_DEVICE_ID_VIA_8378_0   0x3205
 #define PCI_DEVICE_ID_VIA_8783_0   0x3208
 #define PCI_DEVICE_ID_VIA_8237 0x3227
+#define PCI_DEVICE_ID_VIA_K8M890   0x3230
 #define PCI_DEVICE_ID_VIA_8251 0x3287
+#define PCI_DEVICE_ID_VIA_VT3343   0x3343
+#define PCI_DEVICE_ID_VIA_CN7000x3344
+#define PCI_DEVICE_ID_VIA_P4M900   0x3371
 #define PCI_DEVICE_ID_VIA_8261 0x3402
 #define PCI_DEVICE_ID_VIA_8237A0x3337
 #define PCI_DEVICE_ID_VIA_8237S0x3372
+#define PCI_DEVICE_ID_VIA_VX8750x5122
 #define PCI_DEVICE_ID_VIA_SATA_EIDE0x5324
+#define PCI_DEVICE_ID_VIA_VX900_VGA0x7122
+#define PCI_DEVICE_ID_VIA_KM4000x7205
 #define PCI_DEVICE_ID_VIA_8231 0x8231
 #define PCI_DEVICE_ID_VIA_8231_4   0x8235
 #define PCI_DEVICE_ID_VIA_8365_1   0x8305
--
2.35.1

[PATCH v2 27/32] drm/via: Add new VIA Technologies Chrome supporting PCI IDs to DRM

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 include/drm/drm_pciids.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index b7e899ce44f0..e91b93d635fa 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -777,7 +777,11 @@
{0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
{0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
+   {0x1106, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
{0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
+   {0x1106, 0x1122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
+   {0x1106, 0x5122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
+   {0x1106, 0x7122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
{0, 0, 0}

 #define i810_PCI_IDS \
--
2.35.1

[PATCH v2 26/32] drm/via: Add via_drm.h

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 include/uapi/drm/via_drm.h | 309 +
 1 file changed, 309 insertions(+)
 create mode 100644 include/uapi/drm/via_drm.h

diff --git a/include/uapi/drm/via_drm.h b/include/uapi/drm/via_drm.h
new file mode 100644
index ..e9da45ce130a
--- /dev/null
+++ b/include/uapi/drm/via_drm.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright © 2020 Kevin Brace
+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS, COPYRIGHT HOLDERS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+ * OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
+ * THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _VIA_DRM_H_
+#define _VIA_DRM_H_
+
+#include "drm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ */
+
+#ifndef _VIA_DEFINES_
+#define _VIA_DEFINES_
+
+
+#define VIA_NR_SAREA_CLIPRECTS 8
+#define VIA_NR_XVMC_PORTS   10
+#define VIA_NR_XVMC_LOCKS   5
+#define VIA_MAX_CACHELINE_SIZE  64
+#define XVMCLOCKPTR(saPriv,lockNo) \
+   ((volatile struct drm_hw_lock *)(unsigned long) 
(saPriv)->XvMCLockArea) + \
+ (VIA_MAX_CACHELINE_SIZE - 1)) &   \
+~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
+   VIA_MAX_CACHELINE_SIZE*(lockNo)))
+
+/* Each region is a minimum of 64k, and there are at most 64 of them.
+ */
+#define VIA_NR_TEX_REGIONS 64
+#define VIA_LOG_MIN_TEX_REGION_SIZE 16
+#endif
+
+#define VIA_UPLOAD_TEX0IMAGE  0x1  /* handled clientside */
+#define VIA_UPLOAD_TEX1IMAGE  0x2  /* handled clientside */
+#define VIA_UPLOAD_CTX0x4
+#define VIA_UPLOAD_BUFFERS0x8
+#define VIA_UPLOAD_TEX0   0x10
+#define VIA_UPLOAD_TEX1   0x20
+#define VIA_UPLOAD_CLIPRECTS  0x40
+#define VIA_UPLOAD_ALL0xff
+
+/* VIA specific ioctls */
+#define DRM_VIA_ALLOCMEM   0x00
+#define DRM_VIA_FREEMEM0x01
+#define DRM_VIA_AGP_INIT   0x02
+#define DRM_VIA_FB_INIT0x03
+#define DRM_VIA_MAP_INIT   0x04
+#define DRM_VIA_DEC_FUTEX   0x05
+#define NOT_USED
+#define DRM_VIA_DMA_INIT   0x07
+#define DRM_VIA_CMDBUFFER  0x08
+#define DRM_VIA_FLUSH  0x09
+#define DRM_VIA_PCICMD 0x0a
+#define DRM_VIA_CMDBUF_SIZE0x0b
+#define NOT_USED
+#define DRM_VIA_WAIT_IRQ0x0d
+#define DRM_VIA_DMA_BLIT0x0e
+#define DRM_VIA_BLIT_SYNC   0x0f
+
+#defineDRM_VIA_GEM_CREATE  0x10
+#defineDRM_VIA_GEM_MAP 0x11
+#defineDRM_VIA_GEM_UNMAP   0x12
+
+
+#define DRM_IOCTL_VIA_ALLOCMEM   DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, 
drm_via_mem_t)
+#define DRM_IOCTL_VIA_FREEMEMDRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, 
drm_via_mem_t)
+#define DRM_IOCTL_VIA_AGP_INIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, 
drm_via_agp_t)
+#define DRM_IOCTL_VIA_FB_INITDRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, 
drm_via_fb_t)
+#define DRM_IOCTL_VIA_MAP_INIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, 
drm_via_init_t)
+#define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + 
DRM_VIA_DEC_FUTEX, drm_via_futex_t)
+#define DRM_IOCTL_VIA_DMA_INIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, 
drm_via_dma_init_t)
+#define DRM_IOCTL_VIA_CMDBUFFER  DRM_IOW( DRM_COMMAND_BASE + 
DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_FLUSH  DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
+#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, 
drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + 
DRM_VIA_CMDBUF_SIZE, \
+   drm_via_cmdbuf_size_t)
+#define DRM_IOCTL_VIA_WAIT_IRQDRM_IOWR(

[PATCH v2 25/32] drm/via: Add via_vt1632.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_vt1632.c | 583 +++
 1 file changed, 583 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_vt1632.c

diff --git a/drivers/gpu/drm/via/via_vt1632.c b/drivers/gpu/drm/via/via_vt1632.c
new file mode 100644
index ..c621b116933b
--- /dev/null
+++ b/drivers/gpu/drm/via/via_vt1632.c
@@ -0,0 +1,583 @@
+/*
+ * Copyright © 2016-2018 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+#define VIA_VT1632_VEN BIT(5)
+#define VIA_VT1632_HEN BIT(4)
+#define VIA_VT1632_DSELBIT(3)
+#define VIA_VT1632_BSELBIT(2)
+#define VIA_VT1632_EDGEBIT(1)
+#define VIA_VT1632_PDB BIT(0)
+
+
+static void via_vt1632_power(struct i2c_adapter *i2c_bus, bool power_state)
+{
+   u8 buf;
+   u8 power_bit;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_i2c_readbytes(i2c_bus, 0x08, 0x08, , 1);
+   power_bit = power_state ? VIA_VT1632_PDB : 0x00;
+   buf &= ~power_bit;
+   buf |= power_bit;
+   via_i2c_writebytes(i2c_bus, 0x08, 0x08, , 1);
+   DRM_DEBUG_KMS("VT1632 (DVI) Power: %s\n",
+   power_state ? "On" : "Off");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+
+static bool via_vt1632_sense(struct i2c_adapter *i2c_bus)
+{
+   u8 buf;
+   bool rx_detected = false;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_i2c_readbytes(i2c_bus, 0x08, 0x09, , 1);
+   if (buf & BIT(2)) {
+   rx_detected = true;
+   }
+
+   DRM_DEBUG_KMS("VT1632 (DVI) Connector Sense: %s\n",
+   rx_detected ? "Connected" : "Not Connected");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return rx_detected;
+}
+
+static void via_vt1632_display_registers(struct i2c_adapter *i2c_bus)
+{
+   uint8_t i;
+   u8 buf;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   DRM_DEBUG_KMS("VT1632(A) Registers:\n");
+   for (i = 0; i < 0x10; i++) {
+   via_i2c_readbytes(i2c_bus, 0x08, i, , 1);
+   DRM_DEBUG_KMS("0x%02x: 0x%02x\n", i, buf);
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_vt1632_init_registers(struct i2c_adapter *i2c_bus)
+{
+   u8 buf;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   /*
+* For Wyse Cx0 thin client VX855 chipset DVP1 (Digital Video
+* Port 1), use 12-bit mode with dual edge transfer, along
+* with rising edge data capture first mode. This is likely
+* true for CX700, VX700, VX800, and VX900 chipsets as well.
+*/
+   buf = VIA_VT1632_VEN | VIA_VT1632_HEN |
+   VIA_VT1632_DSEL |
+   VIA_VT1632_EDGE | VIA_VT1632_PDB;
+   via_i2c_writebytes(i2c_bus, 0x08, 0x08, , 1);
+
+   /*
+* Route receiver detect bit (Offset 0x09[2]) as the output
+* of MSEN pin.
+*/
+   buf = BIT(5);
+   via_i2c_writebytes(i2c_bus, 0x08, 0x09, , 1);
+
+   /*
+* Turning on deskew feature caused screen display issues.
+* This was observed with Wyse Cx0.
+*/
+   buf = 0x00;
+   via_i2c_writebytes(i2c_bus, 0x08, 0x0a, , 1);
+
+   /*
+* While VIA Technologies VT1632A datasheet insists on setting
+* this register to 0x89 as the recommended setting, in
+* practice, this leads to a blank screen on the display with
+* Wyse Cx0. According to Silicon Image SiI 164 datasheet
+* (VT1632(A) is a pin and mostly register compatible chip),
+* offset 0x0C is for PLL filter enable, PLL filter setting,
+* and continuous SYNC enable bits. All of these are turned
+* off for proper operation.
+

[PATCH v2 24/32] drm/via: Add via_ttm.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_ttm.c | 168 ++
 1 file changed, 168 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_ttm.c

diff --git a/drivers/gpu/drm/via/via_ttm.c b/drivers/gpu/drm/via/via_ttm.c
new file mode 100644
index ..8676623ee074
--- /dev/null
+++ b/drivers/gpu/drm/via/via_ttm.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright © 2018-2019 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+/*
+ * via_ttm.c
+ *
+ * TTM code as part of the TTM memory allocator.
+ * Currently a basic implementation with no DMA support.
+ *
+ */
+
+#include 
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+static void via_bo_move_notify(struct ttm_buffer_object *bo, bool evict,
+   struct ttm_resource *new_mem)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return;
+}
+
+static struct ttm_tt *via_ttm_tt_create(struct ttm_buffer_object *bo,
+   uint32_t page_flags)
+{
+   struct ttm_tt *tt;
+   int ret;
+
+   tt = kzalloc(sizeof(*tt), GFP_KERNEL);
+   if (!tt)
+   return NULL;
+
+   ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
+   if (ret < 0)
+   goto err_ttm_tt_init;
+
+   return tt;
+
+err_ttm_tt_init:
+   kfree(tt);
+   return NULL;
+}
+
+static void via_ttm_tt_destroy(struct ttm_device *bdev, struct ttm_tt *tt)
+{
+   ttm_tt_fini(tt);
+   kfree(tt);
+}
+
+static void via_bo_evict_flags(struct ttm_buffer_object *bo,
+   struct ttm_placement *placement)
+{
+   struct via_bo *driver_bo = to_ttm_bo(bo);
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   if (bo->destroy == _ttm_bo_destroy) {
+   goto exit;
+   }
+
+   switch (bo->resource->mem_type) {
+   case TTM_PL_VRAM:
+   via_ttm_domain_to_placement(driver_bo, TTM_PL_VRAM);
+   break;
+   default:
+   via_ttm_domain_to_placement(driver_bo, TTM_PL_SYSTEM);
+   break;
+   }
+
+   *placement = driver_bo->placement;
+exit:
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static int via_bo_move(struct ttm_buffer_object *bo, bool evict,
+   struct ttm_operation_ctx *ctx,
+   struct ttm_resource *new_mem,
+   struct ttm_place *hop)
+{
+   int ret;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_bo_move_notify(bo, evict, new_mem);
+   ret = ttm_bo_move_memcpy(bo, ctx, new_mem);
+   if (ret) {
+   swap(*new_mem, *bo->resource);
+   via_bo_move_notify(bo, false, new_mem);
+   swap(*new_mem, *bo->resource);
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+static void via_bo_delete_mem_notify(struct ttm_buffer_object *bo)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_bo_move_notify(bo, false, NULL);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return;
+}
+
+static int via_bo_io_mem_reserve(struct ttm_device *bdev,
+   struct ttm_resource *mem)
+{
+   struct via_drm_priv *dev_priv = container_of(bdev,
+   struct via_drm_priv, bdev);
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch (mem->mem_type) {
+   case TTM_PL_SYSTEM:
+   break;
+   case TTM_PL_VRAM:
+   mem->bus.offset = dev_priv->vram_start +
+   (mem->start << PAGE_SHIFT);
+   mem->bus.is_iomem = true;
+   break;
+   default:
+   ret = -EINVAL;
+

[PATCH v2 23/32] drm/via: Add via_tmds.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_tmds.c | 714 +
 1 file changed, 714 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_tmds.c

diff --git a/drivers/gpu/drm/via/via_tmds.c b/drivers/gpu/drm/via/via_tmds.c
new file mode 100644
index ..5404fc7f8b64
--- /dev/null
+++ b/drivers/gpu/drm/via/via_tmds.c
@@ -0,0 +1,714 @@
+/*
+ * Copyright © 2016-2018 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+#include 
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+static void via_tmds_power(struct via_drm_priv *dev_priv,
+   bool power_state)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   if (power_state) {
+   via_lvds1_set_soft_display_period(VGABASE, true);
+   via_lvds1_set_soft_data(VGABASE, true);
+   via_tmds_set_power(VGABASE, true);
+   } else {
+   via_tmds_set_power(VGABASE, false);
+   via_lvds1_set_soft_data(VGABASE, false);
+   via_lvds1_set_soft_display_period(VGABASE, false);
+   }
+
+   DRM_INFO("DVI Power: %s\n",
+   power_state ? "On" : "Off");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_tmds_io_pad_setting(struct via_drm_priv *dev_priv,
+   u32 di_port, bool io_pad_on)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch(di_port) {
+   case VIA_DI_PORT_TMDS:
+   via_lvds1_set_io_pad_setting(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   default:
+   break;
+   }
+
+   DRM_DEBUG_KMS("DVI I/O Pad: %s\n", io_pad_on ? "On": "Off");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+/*
+ * Initializes most registers related to VIA Technologies IGP
+ * integrated TMDS transmitter. Synchronization polarity and
+ * display output source need to be set separately.
+ */
+static void via_tmds_init_reg(struct via_drm_priv *dev_priv)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   /* Turn off hardware controlled FP power on / off circuit. */
+   via_lvds_set_primary_hard_power(VGABASE, false);
+
+   /* Use software FP power sequence control. */
+   via_lvds_set_primary_power_seq_type(VGABASE, false);
+
+   /* Turn off software controlled primary FP power rails. */
+   via_lvds_set_primary_soft_vdd(VGABASE, false);
+   via_lvds_set_primary_soft_vee(VGABASE, false);
+
+   /* Turn off software controlled primary FP back light
+   * control. */
+   via_lvds_set_primary_soft_back_light(VGABASE, false);
+
+   /* Turn off direct control of FP back light. */
+   via_lvds_set_primary_direct_back_light_ctrl(VGABASE, false);
+
+   /* Activate DVI + LVDS2 mode. */
+   /* 3X5.D2[5:4] - Display Channel Select
+*   00: LVDS1 + LVDS2
+*   01: DVI + LVDS2
+*   10: One Dual LVDS Channel (High Resolution Pannel)
+*   11: Single Channel DVI */
+   svga_wcrt_mask(VGABASE, 0xd2, 0x10, 0x30);
+
+   /* Various DVI PLL settings should be set to default settings. */
+   /* 3X5.D1[7]   - PLL2 Reference Clock Edge Select Bit
+*   0: PLLCK lock to rising edge of reference clock
+*   1: PLLCK lock to falling edge of reference clock
+* 3X5.D1[6:5] - PLL2 Charge Pump Current Set Bits
+*   00: ICH = 12.5 uA
+*   01: ICH = 25.0 uA
+*   10: ICH = 37.5 uA
+*   11: ICH = 50.0 uA
+* 3X5.D1[4:1] - Reserved
+* 3X5.D1[0]   - PLL2 Control Voltage Measurement Enable Bit */
+   svga_wcrt_mask(VGABASE, 0xd1, 0x00, 0xe1);
+
+

[PATCH v2 22/32] drm/via: Add via_sii164.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_sii164.c | 563 +++
 1 file changed, 563 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_sii164.c

diff --git a/drivers/gpu/drm/via/via_sii164.c b/drivers/gpu/drm/via/via_sii164.c
new file mode 100644
index ..76f8dd783eca
--- /dev/null
+++ b/drivers/gpu/drm/via/via_sii164.c
@@ -0,0 +1,563 @@
+/*
+ * Copyright © 2016-2018 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+#define SII164_VEN BIT(5)
+#define SII164_HEN BIT(4)
+#define SII164_DSELBIT(3)
+#define SII164_BSELBIT(2)
+#define SII164_EDGEBIT(1)
+#define SII164_PDB BIT(0)
+
+
+static void via_sii164_power(struct i2c_adapter *i2c_bus, bool power_state)
+{
+   u8 buf;
+   u8 power_bit;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_i2c_readbytes(i2c_bus, 0x38, 0x08, , 1);
+   power_bit = power_state ? SII164_PDB : 0x00;
+   buf &= ~power_bit;
+   buf |= power_bit;
+   via_i2c_writebytes(i2c_bus, 0x38, 0x08, , 1);
+   DRM_DEBUG_KMS("SiI 164 (DVI) Power: %s\n",
+   power_state ? "On" : "Off");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+
+static bool via_sii164_sense(struct i2c_adapter *i2c_bus)
+{
+   u8 buf;
+   bool rx_detected = false;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_i2c_readbytes(i2c_bus, 0x38, 0x09, , 1);
+   if (buf & BIT(2)) {
+   rx_detected = true;
+   }
+
+   DRM_DEBUG_KMS("SiI 164 (DVI) Connector Sense: %s\n",
+   rx_detected ? "Connected" : "Not Connected");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return rx_detected;
+}
+
+static void via_sii164_display_registers(struct i2c_adapter *i2c_bus)
+{
+   uint8_t i;
+   u8 buf;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   DRM_DEBUG_KMS("SiI 164 Registers:\n");
+   for (i = 0; i < 0x10; i++) {
+   via_i2c_readbytes(i2c_bus, 0x38, i, , 1);
+   DRM_DEBUG_KMS("0x%02x: 0x%02x\n", i, buf);
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_sii164_init_registers(struct i2c_adapter *i2c_bus)
+{
+   u8 buf;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   buf = SII164_VEN | SII164_HEN |
+   SII164_DSEL |
+   SII164_EDGE | SII164_PDB;
+   via_i2c_writebytes(i2c_bus, 0x38, 0x08, , 1);
+
+   /*
+* Route receiver detect bit (Offset 0x09[2]) as the output
+* of MSEN pin.
+*/
+   buf = BIT(5);
+   via_i2c_writebytes(i2c_bus, 0x38, 0x09, , 1);
+
+   buf = 0x90;
+   via_i2c_writebytes(i2c_bus, 0x38, 0x0a, , 1);
+
+   buf = 0x89;
+   via_i2c_writebytes(i2c_bus, 0x38, 0x0c, , 1);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+
+static const struct drm_encoder_funcs via_sii164_drm_encoder_funcs = {
+   .destroy = via_encoder_cleanup,
+};
+
+static void via_sii164_dpms(struct drm_encoder *encoder, int mode)
+{
+   struct via_encoder *enc = container_of(encoder,
+   struct via_encoder, base);
+   struct drm_device *dev = encoder->dev;
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   struct i2c_adapter *i2c_bus;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   if (enc->i2c_bus & VIA_I2C_BUS1) {
+   i2c_bus = via_find_ddc_bus(0x26);
+   } else if (enc->i2c_bus & VIA_I2C_BUS2) {
+   i2c_bus = via_find_ddc_bus(0x31);
+   } else if (enc->i2c_bus & VIA_I2C_BUS3) {
+   i2c_bus = via_find_ddc_bus(0x25);
+   } else if (enc->i2c_bus & VIA_I2C_BUS4) {
+

[PATCH v2 21/32] drm/via: Add via_pm.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_pm.c | 187 +++
 1 file changed, 187 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_pm.c

diff --git a/drivers/gpu/drm/via/via_pm.c b/drivers/gpu/drm/via/via_pm.c
new file mode 100644
index ..9b80886ab06a
--- /dev/null
+++ b/drivers/gpu/drm/via/via_pm.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright © 2017-2020 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+int via_dev_pm_ops_suspend(struct device *dev)
+{
+   struct pci_dev *pdev = to_pci_dev(dev);
+   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(drm_dev);
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   console_lock();
+
+   /*
+* Frame Buffer Size Control register (SR14) and GTI registers
+* (SR66 through SR6F) need to be saved and restored upon standby
+* resume or can lead to a display corruption issue. These registers
+* are only available on VX800, VX855, and VX900 chipsets. This bug
+* was observed on VIA Embedded EPIA-M830 mainboard.
+*/
+   if ((pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+   (pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+   (pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+   dev_priv->saved_sr14 = vga_rseq(VGABASE, 0x14);
+
+   dev_priv->saved_sr66 = vga_rseq(VGABASE, 0x66);
+   dev_priv->saved_sr67 = vga_rseq(VGABASE, 0x67);
+   dev_priv->saved_sr68 = vga_rseq(VGABASE, 0x68);
+   dev_priv->saved_sr69 = vga_rseq(VGABASE, 0x69);
+   dev_priv->saved_sr6a = vga_rseq(VGABASE, 0x6a);
+   dev_priv->saved_sr6b = vga_rseq(VGABASE, 0x6b);
+   dev_priv->saved_sr6c = vga_rseq(VGABASE, 0x6c);
+   dev_priv->saved_sr6d = vga_rseq(VGABASE, 0x6d);
+   dev_priv->saved_sr6e = vga_rseq(VGABASE, 0x6e);
+   dev_priv->saved_sr6f = vga_rseq(VGABASE, 0x6f);
+   }
+
+   /*
+* 3X5.3B through 3X5.3F are scratch pad registers.
+* They are important for FP detection.
+* Their values need to be saved because they get lost
+* when resuming from standby.
+*/
+   dev_priv->saved_cr3b = vga_rcrt(VGABASE, 0x3b);
+   dev_priv->saved_cr3c = vga_rcrt(VGABASE, 0x3c);
+   dev_priv->saved_cr3d = vga_rcrt(VGABASE, 0x3d);
+   dev_priv->saved_cr3e = vga_rcrt(VGABASE, 0x3e);
+   dev_priv->saved_cr3f = vga_rcrt(VGABASE, 0x3f);
+
+   console_unlock();
+
+   ret = drm_mode_config_helper_suspend(drm_dev);
+   if (ret) {
+   DRM_ERROR("Failed to prepare for suspend.\n");
+   goto exit;
+   }
+
+   pci_save_state(pdev);
+   pci_disable_device(pdev);
+exit:
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+int via_dev_pm_ops_resume(struct device *dev)
+{
+   struct pci_dev *pdev = to_pci_dev(dev);
+   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(drm_dev);
+   void __iomem *regs = ioport_map(0x3c0, 100);
+   u8 val;
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   if (pci_enable_device(pdev)) {
+   DRM_ERROR("Failed to initialize a PCI "
+   "after resume.\n");
+   ret = -EIO;
+   goto exit;
+   }
+
+   console_lock();
+
+   val = ioread8(regs + 0x03);
+   iowrite8(val | 0x1, regs + 0x03);
+   val = ioread8(regs + 0x0C);
+   iowrite8(val | 0x1, regs + 0x02);
+
+   /*
+* Unlock Extended IO Space.
+*/
+   iowrite8(0x10,

[PATCH v2 20/32] drm/via: Add via_pll.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_pll.c | 263 ++
 1 file changed, 263 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_pll.c

diff --git a/drivers/gpu/drm/via/via_pll.c b/drivers/gpu/drm/via/via_pll.c
new file mode 100644
index ..ec61d044504d
--- /dev/null
+++ b/drivers/gpu/drm/via/via_pll.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * James Simmons 
+ */
+
+#include 
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+#define CSR_VCO_UP 6
+#define CSR_VCO_DOWN   3
+
+#define PLL_DTZ_DEFAULT(BIT(0) | BIT(1))
+
+#define VIA_CLK_REFERENCE  14318180
+
+struct pll_mrn_value {
+   u32 pll_m;
+   u32 pll_r;
+   u32 pll_n;
+   u32 diff_clk;
+   u32 pll_fout;
+};
+
+/*
+ * This function first gets the best frequency M, R, N value
+ * to program the PLL according to the supplied frequence
+ * passed in. After we get the MRN values the results are
+ * formatted to fit properly into the PLL clock registers.
+ *
+ * PLL registers M, R, N value
+ * [31:16]  DM[7:0]
+ * [15:8 ]  DR[2:0]
+ * [7 :0 ]  DN[6:0]
+ */
+u32 via_get_clk_value(struct drm_device *dev, u32 freq)
+{
+   struct pci_dev *pdev = to_pci_dev(dev->dev);
+   u32 best_pll_n = 2, best_pll_r = 0, best_pll_m = 2, best_clk_diff = 
freq;
+   u32 pll_fout, pll_fvco, pll_mrn = 0;
+   u32 pll_n, pll_r, pll_m, clk_diff;
+   struct pll_mrn_value pll_tmp[5] = {
+   { 0, 0, 0, 0, 0 },
+   { 0, 0, 0, 0, 0 },
+   { 0, 0, 0, 0, 0 },
+   { 0, 0, 0, 0, 0 },
+   { 0, 0, 0, 0, 0 } };
+   int count;
+
+   if ((pdev->device != PCI_DEVICE_ID_VIA_CLE266) &&
+   (pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
+   /* DN[6:0] */
+   for (pll_n = 2; pll_n < 6; pll_n++) {
+   /* DR[2:0] */
+   for (pll_r = 0; pll_r < 6; pll_r++) {
+   /* DM[9:0] */
+   for (pll_m = 2; pll_m < 512; pll_m++) {
+   /* first divide pll_n then multiply
+* pll_m. We have to reduce pll_m
+* to 512 to get rid of the overflow */
+   pll_fvco = (VIA_CLK_REFERENCE / pll_n) 
* pll_m;
+   if ((pll_fvco >= CSR_VCO_DOWN) && 
(pll_fvco <= CSR_VCO_UP)) {
+   pll_fout = pll_fvco >> pll_r;
+   if (pll_fout < freq)
+   clk_diff = freq - 
pll_fout;
+   else
+   clk_diff = pll_fout - 
freq;
+
+   /* if frequency (which is the 
PLL we want
+* to set) > 150MHz, the MRN 
value we
+* write in register must < 
frequency, and
+* get MRN value whose M is the 
largeset */
+   if (freq >= 15000) {
+   if ((clk_diff <= 
pll_tmp[0].diff_clk) || pll_tmp[0].pll_fout == 0) {
+   for (count = 
ARRAY_SIZE(pll_tmp) - 1; count >= 1; count--)
+

[PATCH v2 19/32] drm/via: Add via_object.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_object.c | 324 +++
 1 file changed, 324 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_object.c

diff --git a/drivers/gpu/drm/via/via_object.c b/drivers/gpu/drm/via/via_object.c
new file mode 100644
index ..96fb2934d0de
--- /dev/null
+++ b/drivers/gpu/drm/via/via_object.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright © 2018-2019 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+/*
+ * via_object.c
+ *
+ * Manages Buffer Objects (BO) via TTM.
+ * Part of the TTM memory allocator.
+ *
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+static void via_gem_free(struct drm_gem_object *obj)
+{
+   struct ttm_buffer_object *ttm_bo;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   ttm_bo = container_of(obj, struct ttm_buffer_object, base);
+
+   ttm_bo_put(ttm_bo);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static const struct vm_operations_struct via_ttm_bo_vm_ops = {
+   .fault = ttm_bo_vm_fault,
+   .open = ttm_bo_vm_open,
+   .close = ttm_bo_vm_close,
+   .access = ttm_bo_vm_access
+};
+
+static const struct drm_gem_object_funcs via_gem_object_funcs = {
+   .free = via_gem_free,
+   .vmap = drm_gem_ttm_vmap,
+   .vunmap = drm_gem_ttm_vunmap,
+   .mmap = drm_gem_ttm_mmap,
+   .vm_ops = _ttm_bo_vm_ops,
+};
+
+void via_ttm_domain_to_placement(struct via_bo *bo,
+   uint32_t ttm_domain)
+{
+   unsigned i = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   bo->placement.placement = bo->placements;
+   bo->placement.busy_placement = bo->placements;
+
+   if (ttm_domain == TTM_PL_SYSTEM) {
+   bo->placements[i].fpfn = 0;
+   bo->placements[i].lpfn = 0;
+   bo->placements[i].mem_type = TTM_PL_SYSTEM;
+   bo->placements[i].flags = 0;
+   i++;
+   }
+
+   if (ttm_domain == TTM_PL_TT) {
+   bo->placements[i].fpfn = 0;
+   bo->placements[i].lpfn = 0;
+   bo->placements[i].mem_type = TTM_PL_TT;
+   bo->placements[i].flags = 0;
+   i++;
+   }
+
+   if (ttm_domain == TTM_PL_VRAM) {
+   bo->placements[i].fpfn = 0;
+   bo->placements[i].lpfn = 0;
+   bo->placements[i].mem_type = TTM_PL_VRAM;
+   bo->placements[i].flags = 0;
+   i++;
+   }
+
+   bo->placement.num_placement = i;
+   bo->placement.num_busy_placement = i;
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void via_ttm_bo_destroy(struct ttm_buffer_object *tbo)
+{
+   struct via_bo *bo;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   bo = to_ttm_bo(tbo);
+
+   drm_gem_object_release(>base);
+   kfree(bo);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+int via_bo_pin(struct via_bo *bo, uint32_t ttm_domain)
+{
+   struct ttm_buffer_object *ttm_bo;
+   struct ttm_operation_ctx ctx = {false, false};
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   ttm_bo = >ttm_bo;
+
+   if (ttm_bo->pin_count) {
+   goto pin;
+   }
+
+   via_ttm_domain_to_placement(bo, ttm_domain);
+   ret = ttm_bo_validate(ttm_bo, >placement, );
+   if (ret) {
+   goto exit;
+   }
+
+pin:
+   ttm_bo_pin(ttm_bo);
+exit:
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+void via_bo_unpin(struct via_bo *bo)
+{
+   struct ttm_buffer_object *ttm_bo;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   ttm_bo = >ttm_bo;
+
+   ttm_bo_unpin(ttm_bo);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+

[PATCH v2 18/32] drm/via: Add via_lvds.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_lvds.c | 1420 
 1 file changed, 1420 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_lvds.c

diff --git a/drivers/gpu/drm/via/via_lvds.c b/drivers/gpu/drm/via/via_lvds.c
new file mode 100644
index ..44f80cc0d6ef
--- /dev/null
+++ b/drivers/gpu/drm/via/via_lvds.c
@@ -0,0 +1,1420 @@
+/*
+ * Copyright © 2016-2018 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+#define TD0 200
+#define TD1 25
+#define TD2 0
+#define TD3 25
+
+/* Non-I2C bus FP native screen resolution information table.*/
+static via_lvds_info via_lvds_info_table[] = {
+   { 640,  480},
+   { 800,  600},
+   {1024,  768},
+   {1280,  768},
+   {1280, 1024},
+   {1400, 1050},
+   {1600, 1200},
+   {1280,  800},
+   { 800,  480},
+   {1024,  768},
+   {1366,  768},
+   {1024,  768},
+   {1280,  768},
+   {1280, 1024},
+   {1400, 1050},
+   {1600, 1200}
+};
+
+/* Power sequence relations */
+struct td_timer {
+   struct vga_regset tdRegs[2];
+};
+
+static struct td_timer td_timer_regs[] = {
+   /* td_timer0 */
+   { { { VGA_CRT_IC, 0x8B, 0, 7 }, { VGA_CRT_IC, 0x8F, 0, 3 } } },
+   /* td_timer1 */
+   { { { VGA_CRT_IC, 0x8C, 0, 7 }, { VGA_CRT_IC, 0x8F, 4, 7 } } },
+   /* td_timer2 */
+   { { { VGA_CRT_IC, 0x8D, 0, 7 }, { VGA_CRT_IC, 0x90, 0, 3 } } },
+   /* td_timer3 */
+   { { { VGA_CRT_IC, 0x8E, 0, 7 }, { VGA_CRT_IC, 0x90, 4, 7 } } }
+};
+
+/*
+ * Function Name:  via_init_td_timing_regs
+ * Description: Init TD timing register (power sequence)
+ */
+static void via_init_td_timing_regs(struct drm_device *dev)
+{
+   struct pci_dev *pdev = to_pci_dev(dev->dev);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   unsigned int td_timer[4] = { 500, 50, 0, 510 }, i;
+   struct vga_registers timings;
+   u32 reg_value;
+
+   /* Fill primary power sequence */
+   for (i = 0; i < 4; i++) {
+   /* Calculate TD Timer, every step is 572.1uSec */
+   reg_value = td_timer[i] * 1 / 5721;
+
+   timings.count = ARRAY_SIZE(td_timer_regs[i].tdRegs);
+   timings.regs = td_timer_regs[i].tdRegs;
+   load_value_to_registers(VGABASE, , reg_value);
+   }
+
+   /* Note: VT3353 have two hardware power sequences
+* other chips only have one hardware power sequence */
+   if (pdev->device == PCI_DEVICE_ID_VIA_VT1122) {
+   /* set CRD4[0] to "1" to select 2nd LCD power sequence. */
+   svga_wcrt_mask(VGABASE, 0xD4, BIT(0), BIT(0));
+   /* Fill secondary power sequence */
+   for (i = 0; i < 4; i++) {
+   /* Calculate TD Timer, every step is 572.1uSec */
+   reg_value = td_timer[i] * 1 / 5721;
+
+   timings.count = ARRAY_SIZE(td_timer_regs[i].tdRegs);
+   timings.regs = td_timer_regs[i].tdRegs;
+   load_value_to_registers(VGABASE, , reg_value);
+   }
+   }
+}
+
+static bool via_fp_probe_edid(struct i2c_adapter *i2c_bus)
+{
+   u8 out = 0x0;
+   u8 buf[8];
+   struct i2c_msg msgs[] = {
+   {
+   .addr = DDC_ADDR,
+   .flags = 0,
+   .len = 1,
+   .buf = ,
+   },
+   {
+   .addr = DDC_ADDR,
+

[PATCH v2 16/32] drm/via: Add via_init.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_init.c | 1300 
 1 file changed, 1300 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_init.c

diff --git a/drivers/gpu/drm/via/via_init.c b/drivers/gpu/drm/via/via_init.c
new file mode 100644
index ..a46b9fb79884
--- /dev/null
+++ b/drivers/gpu/drm/via/via_init.c
@@ -0,0 +1,1300 @@
+/*
+ * Copyright © 2019 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 2006-2009 Luc Verhaegen.
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ * Luc Verhaegen
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+static int cle266_mem_type(struct via_drm_priv *dev_priv,
+   struct pci_dev *bridge)
+{
+   u8 type, fsb, freq;
+   int ret;
+
+   ret = pci_read_config_byte(bridge, 0x54, );
+   if (ret)
+   return ret;
+   ret = pci_read_config_byte(bridge, 0x69, );
+   if (ret)
+   return ret;
+
+   freq >>= 6;
+   fsb >>= 6;
+
+   /* FSB frequency */
+   switch (fsb) {
+   case 0x01: /* 100MHz */
+   switch (freq) {
+   case 0x00:
+   freq = 100;
+   break;
+   case 0x01:
+   freq = 133;
+   break;
+   case 0x02:
+   freq = 66;
+   break;
+   default:
+   freq = 0;
+   break;
+   }
+   break;
+
+   case 0x02: /* 133 MHz */
+   case 0x03:
+   switch (freq) {
+   case 0x00:
+   freq = 133;
+   break;
+   case 0x02:
+   freq = 100;
+   break;
+   default:
+   freq = 0;
+   break;
+   }
+   break;
+   default:
+   freq = 0;
+   break;
+   }
+
+   ret = pci_read_config_byte(bridge, 0x60, );
+   if (ret)
+   return ret;
+   ret = pci_read_config_byte(bridge, 0xE3, );
+   if (ret)
+   return ret;
+
+   /* On bank 2/3 */
+   if (type & 0x02)
+   fsb >>= 2;
+
+   /* Memory type */
+   switch (fsb & 0x03) {
+   case 0x00: /* SDR */
+   switch (freq) {
+   case 66:
+   dev_priv->vram_type = VIA_MEM_SDR66;
+   break;
+   case 100:
+   dev_priv->vram_type = VIA_MEM_SDR100;
+   break;
+   case 133:
+   dev_priv->vram_type = VIA_MEM_SDR133;
+   break;
+   default:
+   break;
+   }
+   break;
+
+   case 0x02: /* DDR */
+   switch (freq) {
+   case 100:
+   dev_priv->vram_type = VIA_MEM_DDR_200;
+   break;
+   case 133:
+   dev_priv->vram_type = VIA_MEM_DDR_266;
+   break;
+   default:
+   break;
+   }
+   break;
+   default:
+   break;
+   }
+   return ret;
+}
+
+static int km400_mem_type(struct via_drm_priv *dev_priv,
+   struct pci_dev *bridge)
+{
+   u8 fsb, freq, rev;
+   int ret;
+
+   ret = pci_read_config_byte(bridge, 0xF6, );
+   if (ret)
+   return ret;
+   ret = pci_read_config_byte(bridge,

[PATCH v2 17/32] drm/via: Add via_ioctl.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_ioctl.c | 122 
 1 file changed, 122 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_ioctl.c

diff --git a/drivers/gpu/drm/via/via_ioctl.c b/drivers/gpu/drm/via/via_ioctl.c
new file mode 100644
index ..24d72bf4d53a
--- /dev/null
+++ b/drivers/gpu/drm/via/via_ioctl.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright © 2020 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+#include 
+#include 
+
+#include 
+
+#include 
+
+#include "via_drv.h"
+
+
+static int via_gem_create_ioctl(struct drm_device *dev,
+   void *data,
+   struct drm_file *file_priv)
+{
+   struct drm_via_gem_create *args = data;
+   struct ttm_buffer_object *ttm_bo;
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   struct via_bo *bo;
+   uint32_t handle;
+   int ret;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   ret = via_bo_create(dev, _priv->bdev, args->size,
+   ttm_bo_type_device, args->domain, false, );
+   if (ret) {
+   goto exit;
+   }
+
+   ttm_bo = >ttm_bo;
+
+   ret = drm_gem_handle_create(file_priv, _bo->base, );
+   drm_gem_object_put(_bo->base);
+   if (ret) {
+   via_bo_destroy(bo, false);
+   goto exit;
+   }
+
+   args->size  = ttm_bo->base.size;
+   args->domain= ttm_bo->resource->placement;
+   args->handle= handle;
+   args->offset= ttm_bo->resource->start << PAGE_SHIFT;
+exit:
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+static int via_gem_map_ioctl(struct drm_device *dev,
+   void *data,
+   struct drm_file *file_priv)
+{
+   struct drm_via_gem_map *args = data;
+   struct drm_gem_object *gem;
+   struct ttm_buffer_object *ttm_bo;
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   gem = drm_gem_object_lookup(file_priv, args->handle);
+   if (!gem) {
+   ret = -EINVAL;
+   goto exit;
+   }
+
+   ttm_bo = container_of(gem, struct ttm_buffer_object, base);
+
+   args->map_offset = drm_vma_node_offset_addr(_bo->base.vma_node);
+exit:
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+static int via_gem_unmap_ioctl(struct drm_device *dev,
+   void *data,
+   struct drm_file *file_priv)
+{
+   struct drm_via_gem_unmap *args = data;
+   int ret;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   ret = drm_gem_handle_delete(file_priv, args->handle);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+
+const struct drm_ioctl_desc via_driver_ioctls[] = {
+   DRM_IOCTL_DEF_DRV(VIA_GEM_CREATE, via_gem_create_ioctl, DRM_AUTH | 
DRM_UNLOCKED),
+   DRM_IOCTL_DEF_DRV(VIA_GEM_MAP, via_gem_map_ioctl, DRM_AUTH | 
DRM_UNLOCKED),
+   DRM_IOCTL_DEF_DRV(VIA_GEM_UNMAP, via_gem_unmap_ioctl, DRM_AUTH | 
DRM_UNLOCKED),
+};
+
+
+int via_driver_num_ioctls = ARRAY_SIZE(via_driver_ioctls);
--
2.35.1

[PATCH v2 15/32] drm/via: Add via_i2c.c

From: Kevin Brace 

Note that the code here is GPL based.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_i2c.c | 209 ++
 1 file changed, 209 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_i2c.c

diff --git a/drivers/gpu/drm/via/via_i2c.c b/drivers/gpu/drm/via/via_i2c.c
new file mode 100644
index ..f2e8b118754e
--- /dev/null
+++ b/drivers/gpu/drm/via/via_i2c.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Author(s):
+ * James Simmons 
+ */
+
+#include 
+
+#include "via_drv.h"
+
+enum viafb_i2c_adap;
+
+#include 
+
+#define SERIAL 0
+#defineGPIO1
+
+static struct via_i2c_stuff via_i2c_par[5];
+
+static void via_i2c_setsda(void *data, int state)
+{
+   struct via_i2c_stuff *i2c = data;
+   struct drm_device *dev = i2c_get_adapdata(>adapter);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   u8 value, mask;
+
+   if (i2c->is_active == GPIO) {
+   mask = state ? BIT(6) : BIT(6) | BIT(4);
+   value = state ? 0x00 : BIT(6);
+   } else {
+   value = state ? BIT(4) | BIT(0) : BIT(0);
+   mask = BIT(4) | BIT(0);
+   }
+
+   svga_wseq_mask(VGABASE, i2c->i2c_port, value, mask);
+}
+
+static void via_i2c_setscl(void *data, int state)
+{
+   struct via_i2c_stuff *i2c = data;
+   struct drm_device *dev = i2c_get_adapdata(>adapter);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   u8 value, mask;
+
+   if (i2c->is_active == GPIO) {
+   mask = state ? BIT(7) : BIT(7) | BIT(5);
+   value = state ? 0x00 : BIT(7);
+   } else {
+   value = state ? BIT(5) | BIT(0) : BIT(0);
+   mask = BIT(5) | BIT(0);
+   }
+
+   svga_wseq_mask(VGABASE, i2c->i2c_port, value, mask);
+}
+
+static int via_i2c_getsda(void *data)
+{
+   struct via_i2c_stuff *i2c = data;
+   struct drm_device *dev = i2c_get_adapdata(>adapter);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+
+   return vga_rseq(VGABASE, i2c->i2c_port) & BIT(2);
+}
+
+static int via_i2c_getscl(void *data)
+{
+   struct via_i2c_stuff *i2c = data;
+   struct drm_device *dev = i2c_get_adapdata(>adapter);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+
+   return vga_rseq(VGABASE, i2c->i2c_port) & BIT(3);
+}
+
+struct i2c_adapter *via_find_ddc_bus(int port)
+{
+   struct i2c_adapter *adapter = NULL;
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(via_i2c_par); i++) {
+   struct via_i2c_stuff *i2c = _i2c_par[i];
+
+   if (i2c->i2c_port == port) {
+   adapter = >adapter;
+   break;
+   }
+   }
+   return adapter;
+}
+
+static int create_i2c_bus(struct drm_device *dev,
+   struct via_i2c_stuff *i2c_par)
+{
+   struct i2c_adapter *adapter = _par->adapter;
+   struct i2c_algo_bit_data *algo = _par->algo;
+
+   algo->setsda = via_i2c_setsda;
+   algo->setscl = via_i2c_setscl;
+   algo->getsda = via_i2c_getsda;
+   algo->getscl = via_i2c_getscl;
+   algo->udelay = 15;
+   algo->timeout = usecs_to_jiffies(2200); /* from VESA */
+   algo->data = i2c_par;
+
+   sprintf(adapter->name, "via i2c bit bus 0x%02x", i2c_par->i2c_port);
+   adapter->owner = THIS_MODULE;
+   adapter->class = I2C_CLASS_DDC;
+   adapter->algo_data = algo;
+   i2c_set_adapdata(adapter, dev);
+
+   /* Raise SCL and SDA */
+   via_i2c_setsda(i2c_par, 1);
+   via_i2c_setscl(i2c_par, 1);
+   udelay(20);
+
+   return i2c_bit_add_bus(adapter);
+}
+
+void via_i2c_readbytes(struct i2c_adapter *adapter,
+   u8 slave_addr, char offset,
+   u8 *buffer, unsigned int size)
+{
+   u8 out_buf[2];
+   u8 in_buf[2];
+   struct i2c_msg msgs[] = {
+   {
+   .addr = slave_addr,
+   .flags = 0,
+   .len = 1,
+   .buf = out_buf,
+   },
+   {
+   .addr = slave_addr,
+   .flags = I2C_M_RD,
+   .len = size,
+   .buf = in_buf,
+   }
+   };
+
+   out_buf[0] = offset;
+   out_buf[1] = 0;
+
+   if (i2c_transfer(adapter, msgs, 2) != 2)
+   printk(KERN_WARNING "%s failed\n", __func__);
+   else
+   *buffer = in_buf[0];
+}
+
+void via_i2c_writebytes(struct i2c_adapter *adapter,
+   u8 slave_addr, char offset,
+   u8 *data, unsigned int size)
+{
+   struct i2c_msg msg = { 0 };
+   u8 *out_buf;
+
+

[PATCH v2 14/32] drm/via: Add via_hdmi.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_hdmi.c | 719 +
 1 file changed, 719 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_hdmi.c

diff --git a/drivers/gpu/drm/via/via_hdmi.c b/drivers/gpu/drm/via/via_hdmi.c
new file mode 100644
index ..9412054a24df
--- /dev/null
+++ b/drivers/gpu/drm/via/via_hdmi.c
@@ -0,0 +1,719 @@
+/*
+ * Copyright 2013 James Simmons. All Rights Reserved.
+ * Copyright 1998-2012 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2012 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * James Simmons 
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+#define HDMI_AUDIO_ENABLED BIT(0)
+
+int via_hdmi_audio = 0;
+
+MODULE_PARM_DESC(audio, "HDMI Audio enable (1 = enable)");
+module_param_named(audio, via_hdmi_audio, int, 0444);
+
+/*
+ * Routines for controlling stuff on the HDMI port
+ */
+static const struct drm_encoder_funcs via_hdmi_enc_funcs = {
+   .destroy = via_encoder_cleanup,
+};
+
+static void via_hdmi_enc_dpms(struct drm_encoder *encoder, int mode)
+{
+   struct drm_device *dev = encoder->dev;
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+
+   switch (mode) {
+   case DRM_MODE_DPMS_SUSPEND:
+   case DRM_MODE_DPMS_STANDBY:
+   case DRM_MODE_DPMS_OFF:
+   /* disable HDMI */
+   VIA_WRITE_MASK(0xC280, 0x0, 0x2);
+   break;
+
+   case DRM_MODE_DPMS_ON:
+   default:
+   /* enable band gap */
+   VIA_WRITE_MASK(0xC740, BIT(0), BIT(0));
+   /* enable video */
+   VIA_WRITE_MASK(0xC640, BIT(3), BIT(3));
+   /* enable HDMI */
+   VIA_WRITE_MASK(0xC280, BIT(1), BIT(1));
+   break;
+   }
+}
+
+static bool via_hdmi_enc_mode_fixup(struct drm_encoder *encoder,
+   const struct drm_display_mode *mode,
+   struct drm_display_mode *adjusted_mode)
+{
+   uint32_t panelHSyncTime = 0, panelHBlankStart = 0, newHBlankStart = 0;
+   uint32_t panelVSyncTime = 0, panelVBlankStart = 0, newVBlankStart = 0;
+   uint32_t left_border = 0, right_border = 0;
+   uint32_t top_border = 0, bottom_border = 0;
+
+   if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+   /* when interlace mode, we should consider halve vertical
+* timings. */
+   panelHSyncTime = adjusted_mode->hsync_end -
+   adjusted_mode->hsync_start;
+   panelVSyncTime = adjusted_mode->vsync_end / 2 -
+   adjusted_mode->vsync_start / 2;
+   panelHBlankStart = adjusted_mode->hdisplay;
+   panelVBlankStart = adjusted_mode->vdisplay / 2;
+   newHBlankStart = adjusted_mode->hdisplay - left_border;
+   newVBlankStart = adjusted_mode->vdisplay / 2 - top_border;
+
+   adjusted_mode->hdisplay =
+   adjusted_mode->hdisplay - left_border - right_border;
+   adjusted_mode->hsync_start =
+   (adjusted_mode->hsync_start - panelHBlankStart) +
+   newHBlankStart;
+   adjusted_mode->hsync_end =
+   adjusted_mode->hsync_start + panelHSyncTime;
+
+   adjusted_mode->vdisplay = adjusted_mode->vdisplay / 2 -
+   top_border - bottom_border;
+   adjusted_mode->vsync_start =
+   (adjusted_mode->vsync_start / 2 - 
panelVBlankStart) +
+   newVBlankStart;
+   adjusted_mode->vsync_end =
+

[PATCH v2 13/32] drm/via: Add via_encoder.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_encoder.c | 173 ++
 1 file changed, 173 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_encoder.c

diff --git a/drivers/gpu/drm/via/via_encoder.c 
b/drivers/gpu/drm/via/via_encoder.c
new file mode 100644
index ..eae693fc5141
--- /dev/null
+++ b/drivers/gpu/drm/via/via_encoder.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright © 2017-2018 Kevin Brace.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ */
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
+   uint32_t di_port,
+   bool io_pad_on)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch(di_port) {
+   case VIA_DI_PORT_DVP0:
+   via_dvp0_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case VIA_DI_PORT_DVP1:
+   via_dvp1_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case VIA_DI_PORT_FPDPLOW:
+   via_fpdp_low_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case VIA_DI_PORT_FPDPHIGH:
+   via_fpdp_high_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case (VIA_DI_PORT_FPDPLOW |
+   VIA_DI_PORT_FPDPHIGH):
+   via_fpdp_low_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   via_fpdp_high_set_io_pad_state(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case VIA_DI_PORT_LVDS1:
+   via_lvds1_set_io_pad_setting(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case VIA_DI_PORT_LVDS2:
+   via_lvds2_set_io_pad_setting(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   case (VIA_DI_PORT_LVDS1 |
+   VIA_DI_PORT_LVDS2):
+   via_lvds1_set_io_pad_setting(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   via_lvds2_set_io_pad_setting(VGABASE,
+   io_pad_on ? 0x03 : 0x00);
+   break;
+   default:
+   break;
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void via_transmitter_clock_drive_strength(
+   struct via_drm_priv *dev_priv,
+   u32 di_port, u8 drive_strength)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch(di_port) {
+   case VIA_DI_PORT_DVP0:
+   via_dvp0_set_clock_drive_strength(VGABASE,
+   drive_strength);
+   break;
+   case VIA_DI_PORT_DVP1:
+   via_dvp1_set_clock_drive_strength(VGABASE,
+   drive_strength);
+   break;
+   default:
+   break;
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void via_transmitter_data_drive_strength(
+   struct via_drm_priv *dev_priv,
+   u32 di_port, u8 drive_strength)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch(di_port) {
+   case VIA_DI_PORT_DVP0:
+   via_dvp0_set_data_drive_strength(VGABASE,
+   drive_strength);
+   break;
+   case

[PATCH v2 12/32] drm/via: Add via_drv.c

From: Kevin Brace 

Note that GPL is chosen as a license type.  This is due to via_i2c.c
being GPL based.  Everything else is MIT license based.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_drv.c | 313 ++
 1 file changed, 313 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_drv.c

diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c
new file mode 100644
index ..25d7967c938b
--- /dev/null
+++ b/drivers/gpu/drm/via/via_drv.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright © 2019-2021 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "via_drv.h"
+
+
+extern const struct drm_ioctl_desc via_driver_ioctls[];
+
+/*
+ * For now, this device driver will be disabled, unless the
+ * user decides to enable it.
+ */
+int via_modeset = 0;
+
+MODULE_PARM_DESC(modeset, "Enable DRM device driver "
+   "(Default: Disabled, "
+   "0 = Disabled,"
+   "1 = Enabled)");
+module_param_named(modeset, via_modeset, int, 0400);
+
+static int via_driver_open(struct drm_device *dev,
+   struct drm_file *file_priv)
+{
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+static void via_driver_postclose(struct drm_device *dev,
+   struct drm_file *file_priv)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_driver_lastclose(struct drm_device *dev)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   drm_fb_helper_lastclose(dev);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static int via_driver_dumb_create(struct drm_file *file_priv,
+   struct drm_device *dev,
+   struct drm_mode_create_dumb *args)
+{
+   struct ttm_buffer_object *ttm_bo;
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   struct via_bo *bo;
+   uint32_t handle, pitch;
+   uint64_t size;
+   int ret;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   /*
+* Calculate the parameters for the dumb buffer.
+*/
+   pitch = args->width * ((args->bpp + 7) >> 3);
+   size = pitch * args->height;
+
+   ret = via_bo_create(dev, _priv->bdev, size,
+   ttm_bo_type_device, TTM_PL_VRAM, false, );
+   if (ret) {
+   goto exit;
+   }
+
+   ttm_bo = >ttm_bo;
+
+   ret = drm_gem_handle_create(file_priv, _bo->base, );
+   drm_gem_object_put(_bo->base);
+   if (ret) {
+   via_bo_destroy(bo, false);
+   goto exit;
+   }
+
+   args->handle = handle;
+   args->pitch = pitch;
+   args->size = size;
+exit:
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+   return ret;
+}
+
+static int via_driver_dumb_map_offset(struct drm_file *file_priv,
+   struct drm_device *dev,
+   uint32_t handle,
+   uint64_t *offset)
+{
+   struct drm_gem_object *gem;
+   struct ttm_buffer_object *ttm_bo;
+   struct via_bo *bo;
+   int ret = 0;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   gem = drm_gem_object_lookup(file_priv, handle);
+   if (!gem) {
+   ret = -ENOENT;
+   goto exit;
+   }
+
+   ttm_bo = container_of(gem, struct

[PATCH v2 11/32] drm/via: Add via_display.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_display.c | 125 ++
 1 file changed, 125 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_display.c

diff --git a/drivers/gpu/drm/via/via_display.c 
b/drivers/gpu/drm/via/via_display.c
new file mode 100644
index ..2f82764038c0
--- /dev/null
+++ b/drivers/gpu/drm/via/via_display.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright © 2017-2020 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include "via_drv.h"
+
+void via_encoder_cleanup(struct drm_encoder *encoder)
+{
+   struct via_encoder *enc = container_of(encoder, struct via_encoder, 
base);
+
+   drm_encoder_cleanup(encoder);
+   kfree(enc);
+}
+
+void via_connector_destroy(struct drm_connector *connector)
+{
+   struct via_connector *con = container_of(connector, struct 
via_connector, base);
+   struct drm_property *property, *tmp;
+
+   list_for_each_entry_safe(property, tmp, >props, head)
+   drm_property_destroy(connector->dev, property);
+   list_del(>props);
+
+   drm_connector_update_edid_property(connector, NULL);
+   drm_connector_unregister(connector);
+   drm_connector_cleanup(connector);
+}
+
+int via_modeset_init(struct drm_device *dev)
+{
+   struct pci_dev *pdev = to_pci_dev(dev->dev);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   uint32_t i;
+   int ret = 0;
+
+   via_mode_config_init(dev_priv);
+
+   /* Initialize the number of display connectors. */
+   dev_priv->number_fp = 0;
+   dev_priv->number_dvi = 0;
+
+   via_i2c_reg_init(dev_priv);
+   ret = via_i2c_init(dev);
+   if (ret) {
+   DRM_ERROR("Failed to initialize I2C bus!\n");
+   goto exit;
+   }
+
+   for (i = 0; i < VIA_MAX_CRTC; i++) {
+   ret = via_crtc_init(dev_priv, i);
+   if (ret) {
+   goto exit;
+   }
+   }
+
+   via_ext_dvi_probe(dev);
+   via_tmds_probe(dev);
+
+   via_lvds_probe(dev);
+
+   via_dac_probe(dev);
+
+
+   via_ext_dvi_init(dev);
+   via_tmds_init(dev);
+
+   via_dac_init(dev);
+
+   via_lvds_init(dev);
+
+   switch (pdev->device) {
+   case PCI_DEVICE_ID_VIA_VX900_VGA:
+   via_hdmi_init(dev, VIA_DI_PORT_NONE);
+   break;
+   default:
+   break;
+   }
+
+   drm_mode_config_reset(dev);
+
+   drm_kms_helper_poll_init(dev);
+exit:
+   return ret;
+}
+
+void via_modeset_fini(struct drm_device *dev)
+{
+   drm_kms_helper_poll_fini(dev);
+
+   drm_helper_force_disable_all(dev);
+
+   drm_mode_config_cleanup(dev);
+
+   via_i2c_exit();
+}
--
2.35.1

[PATCH v2 09/32] drm/via: Add via_cursor.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_cursor.c | 419 +++
 1 file changed, 419 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_cursor.c

diff --git a/drivers/gpu/drm/via/via_cursor.c b/drivers/gpu/drm/via/via_cursor.c
new file mode 100644
index ..9a6bce1cf922
--- /dev/null
+++ b/drivers/gpu/drm/via/via_cursor.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright © 2019-2020 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "via_drv.h"
+
+
+static void via_hide_cursor(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct pci_dev *pdev = to_pci_dev(dev->dev);
+   struct via_crtc *iga = container_of(crtc,
+   struct via_crtc, base);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+   uint32_t temp;
+
+   switch (pdev->device) {
+   case PCI_DEVICE_ID_VIA_VT3157:
+   case PCI_DEVICE_ID_VIA_VT3343:
+   case PCI_DEVICE_ID_VIA_P4M900:
+   case PCI_DEVICE_ID_VIA_VT1122:
+   case PCI_DEVICE_ID_VIA_VX875:
+   case PCI_DEVICE_ID_VIA_VX900_VGA:
+   if (iga->index) {
+   temp = VIA_READ(HI_CONTROL);
+   VIA_WRITE(HI_CONTROL, temp & 0xFFFA);
+   } else {
+   temp = VIA_READ(PRIM_HI_CTRL);
+   VIA_WRITE(PRIM_HI_CTRL, temp & 0xFFFA);
+   }
+
+   break;
+   default:
+   temp = VIA_READ(HI_CONTROL);
+   VIA_WRITE(HI_CONTROL, temp & 0xFFFA);
+   break;
+   }
+}
+
+static void via_show_cursor(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct pci_dev *pdev = to_pci_dev(dev->dev);
+   struct via_crtc *iga = container_of(crtc,
+   struct via_crtc, base);
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+
+   switch (pdev->device) {
+   case PCI_DEVICE_ID_VIA_VT3157:
+   case PCI_DEVICE_ID_VIA_VT3343:
+   case PCI_DEVICE_ID_VIA_P4M900:
+   case PCI_DEVICE_ID_VIA_VT1122:
+   case PCI_DEVICE_ID_VIA_VX875:
+   case PCI_DEVICE_ID_VIA_VX900_VGA:
+   /*
+* Program Hardware Icon (HI) FIFO, foreground color,
+* and background color.
+*/
+   if (iga->index) {
+   VIA_WRITE(HI_TRANSPARENT_COLOR, 0x);
+   VIA_WRITE(HI_INVTCOLOR, 0x00FF);
+   VIA_WRITE(ALPHA_V3_PREFIFO_CONTROL,
+   0x000E);
+   VIA_WRITE(ALPHA_V3_FIFO_CONTROL, 0x0E0F);
+   } else {
+   VIA_WRITE(PRIM_HI_TRANSCOLOR, 0x);
+   VIA_WRITE(PRIM_HI_INVTCOLOR, 0x00FF);
+   VIA_WRITE(V327_HI_INVTCOLOR, 0x00FF);
+   VIA_WRITE(PRIM_HI_FIFO, 0x0D000D0F);
+   }
+
+   break;
+   default:
+   /*
+* Program Hardware Icon (HI) FIFO, foreground color,
+* and background color.
+*/
+   VIA_WRITE(HI_TRANSPARENT_COLOR, 0x);
+   VIA_WRITE(HI_INVTCOLOR, 0x00FF);
+   VIA_WRITE(ALPHA_V3_PREFIFO_CONTROL, 0x000E);
+   VIA_WRITE(ALPHA_V3_FIFO_CONTROL,

[PATCH v2 10/32] drm/via: Add via_dac.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_dac.c | 504 ++
 1 file changed, 504 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_dac.c

diff --git a/drivers/gpu/drm/via/via_dac.c b/drivers/gpu/drm/via/via_dac.c
new file mode 100644
index ..4921c93d1089
--- /dev/null
+++ b/drivers/gpu/drm/via/via_dac.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright © 2016-2018 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+
+#include 
+#include 
+
+#include "via_crtc_hw.h"
+#include "via_drv.h"
+
+
+/*
+ * Enables or disables DAC (VGA) output.
+ */
+static void via_dac_power(struct via_drm_priv *dev_priv, bool outputState)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+
+   via_dac_set_power(VGABASE, outputState);
+   DRM_INFO("DAC (VGA) Power: %s\n",
+   outputState ? "On" : "Off");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+/*
+ * Set DAC (VGA) sync polarity.
+ */
+static void via_dac_sync_polarity(struct via_drm_priv *dev_priv,
+   unsigned int flags)
+{
+   u8 syncPolarity = 0x00;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   if (flags & DRM_MODE_FLAG_NHSYNC) {
+   syncPolarity |= BIT(0);
+   }
+
+   if (flags & DRM_MODE_FLAG_NVSYNC) {
+   syncPolarity |= BIT(1);
+   }
+
+   via_dac_set_sync_polarity(VGABASE, syncPolarity);
+   DRM_INFO("DAC (VGA) Horizontal Sync Polarity: %s\n",
+   (syncPolarity & BIT(0)) ? "-" : "+");
+   DRM_INFO("DAC (VGA) Vertical Sync Polarity: %s\n",
+   (syncPolarity & BIT(1)) ? "-" : "+");
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+/*
+ * Sets DAC (VGA) display source.
+ */
+static void via_dac_display_source(struct via_drm_priv *dev_priv,
+   int index)
+{
+   u8 displaySource = index;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   via_dac_set_display_source(VGABASE, displaySource & 0x01);
+   DRM_INFO("DAC (VGA) Display Source: IGA%d\n",
+   (displaySource & 0x01) + 1);
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+/*
+ * Routines for controlling stuff on the DAC port
+ */
+static const struct drm_encoder_funcs via_dac_enc_funcs = {
+   .destroy = via_encoder_cleanup,
+};
+
+/*
+ * Manage the power state of DAC (VGA).
+ */
+static void via_dac_dpms(struct drm_encoder *encoder, int mode)
+{
+   struct drm_device *dev = encoder->dev;
+   struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   switch (mode) {
+   case DRM_MODE_DPMS_ON:
+   via_dac_set_dpms_control(VGABASE, VIA_DAC_DPMS_ON);
+   via_dac_power(dev_priv, true);
+   break;
+   case DRM_MODE_DPMS_STANDBY:
+   via_dac_set_dpms_control(VGABASE, VIA_DAC_DPMS_STANDBY);
+   via_dac_power(dev_priv, true);
+   break;
+   case DRM_MODE_DPMS_SUSPEND:
+   via_dac_set_dpms_control(VGABASE, VIA_DAC_DPMS_SUSPEND);
+   via_dac_power(dev_priv, true);
+   break;
+   case DRM_MODE_DPMS_OFF:
+   via_dac_set_dpms_control(VGABASE, VIA_DAC_DPMS_OFF);
+   via_dac_power(dev_priv, false);
+   break;
+   default:
+   DRM_ERROR("Bad DPMS mode.");
+   break;
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+/* Pass our mode to the connectors and the CRTC to give them a chance to
+ * adjust it according to limitations or connector properties, and also
+ * a chance to reject the mode entirely. Useful for things like scaling.
+ */

[PATCH v2 08/32] drm/via: Add via_crtc_hw.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_crtc_hw.c | 91 +++
 1 file changed, 91 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_crtc_hw.c

diff --git a/drivers/gpu/drm/via/via_crtc_hw.c 
b/drivers/gpu/drm/via/via_crtc_hw.c
new file mode 100644
index ..f5446da52c0f
--- /dev/null
+++ b/drivers/gpu/drm/via/via_crtc_hw.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * James Simmons 
+ */
+
+#include 
+
+#include "via_crtc_hw.h"
+
+/*
+ * load_register_table enables the ability to set entire
+ * tables of registers. For each register defined by the
+ * port and the index for that register is programmed
+ * with a masked value.
+ */
+void
+load_register_tables(void __iomem *regbase, struct vga_registers *regs)
+{
+   u8 cr_index, orig, reg_mask, data;
+   unsigned int i;
+   u16 port;
+
+   for (i = 0; i < regs->count; i++) {
+   reg_mask = regs->regs[i].start_bit;
+   data = regs->regs[i].end_bit;
+   cr_index = regs->regs[i].io_addr;
+   port = regs->regs[i].ioport;
+
+   vga_w(regbase, port, cr_index);
+   orig = (vga_r(regbase, port + 1) & ~reg_mask);
+   vga_w(regbase, port + 1, ((data & reg_mask) | orig));
+   }
+}
+
+/*
+ * Due to the limitation of how much data you can write to a single
+ * register we run into data that can't be written in only one register.
+ * So load_value_to_register was developed to be able to define register
+ * tables that can load different bit ranges of the data to different
+ * registers.
+ */
+void
+load_value_to_registers(void __iomem *regbase, struct vga_registers *regs,
+   unsigned int value)
+{
+   unsigned int bit_num = 0, shift_next_reg, reg_mask;
+   u8 start_index, end_index, cr_index, orig;
+   unsigned int data, i, j;
+   u16 get_bit, port;
+
+   for (i = 0; i < regs->count; i++) {
+   start_index = regs->regs[i].start_bit;
+   end_index = regs->regs[i].end_bit;
+   cr_index = regs->regs[i].io_addr;
+   port = regs->regs[i].ioport;
+   reg_mask = data = 0;
+
+   shift_next_reg = bit_num;
+   for (j = start_index; j <= end_index; j++) {
+   reg_mask = reg_mask | (1 << j);
+   get_bit = (value & (1 << bit_num));
+   data |= ((get_bit >> shift_next_reg) << start_index);
+   bit_num++;
+   }
+
+   vga_w(regbase, port, cr_index);
+   orig = (vga_r(regbase, port + 1) & ~reg_mask);
+   vga_w(regbase, port + 1, ((data & reg_mask) | orig));
+   }
+}
--
2.35.1

[PATCH v2 07/32] drm/via: Add via_crtc.c

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_crtc.c | 2324 
 1 file changed, 2324 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_crtc.c

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
new file mode 100644
index ..afd42bd99f25
--- /dev/null
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -0,0 +1,2324 @@
+/*
+ * Copyright © 2019-2020 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "via_drv.h"
+#include "via_disp_reg.h"
+
+
+static struct vga_regset vpit_table[] = {
+   {VGA_SEQ_I, 0x01, 0xFF, 0x01 },
+   {VGA_SEQ_I, 0x02, 0xFF, 0x0F },
+   {VGA_SEQ_I, 0x03, 0xFF, 0x00 },
+   {VGA_SEQ_I, 0x04, 0xFF, 0x0E },
+   {VGA_GFX_I, 0x00, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x01, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x02, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x03, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x04, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x05, 0xFF, 0x00 },
+   {VGA_GFX_I, 0x06, 0xFF, 0x05 },
+   {VGA_GFX_I, 0x07, 0xFF, 0x0F },
+   {VGA_GFX_I, 0x08, 0xFF, 0xFF }
+};
+
+static void via_iga_common_init(void __iomem *regs)
+{
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   /* Be careful with 3C5.15[5] - Wrap Around Disable.
+* It must be set to 1 for proper operation. */
+   /* 3C5.15[5]   - Wrap Around Disable
+*   0: Disable (For Mode 0-13)
+*   1: Enable
+* 3C5.15[1]   - Extended Display Mode Enable
+*   0: Disable
+*   1: Enable */
+   svga_wseq_mask(regs, 0x15, BIT(5) | BIT(1), BIT(5) | BIT(1));
+
+   /*
+* Disable simultaneous display.
+* Turning this on causes IGA1 to have a display issue.
+*/
+   /*
+* 3X5.6B[3]   - Simultaneous Display Enable
+*   0: Disable
+*   1: Enable
+*/
+   svga_wcrt_mask(regs, 0x6B, 0x00, BIT(3));
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_iga1_set_color_depth(struct via_drm_priv *dev_priv,
+   u8 depth)
+{
+   u8 value;
+
+   DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+   value = 0x00;
+
+   /* Set the color depth for IGA1. */
+   switch (depth) {
+   case 8:
+   break;
+   case 16:
+   /* Bit 4 is for 555 (15-bit) / 565 (16-bit) color selection. */
+   value |= BIT(4) | BIT(2);
+   break;
+   case 24:
+   value |= BIT(3) | BIT(2);
+   break;
+   default:
+   break;
+   }
+
+   if ((depth == 8) || (depth == 16) || (depth == 24)) {
+   /* 3C5.15[4]   - Hi Color Mode Select
+*   0: 555
+*   1: 565
+* 3C5.15[3:2] - Display Color Depth Select
+*   00: 8bpp
+*   01: 16bpp
+*   10: 30bpp
+*   11: 32bpp */
+   svga_wseq_mask(VGABASE, 0x15, value,
+   BIT(4) | BIT(3) | BIT(2));
+   DRM_INFO("IGA1 Color Depth: %d bit\n", depth);
+   } else {
+   DRM_ERROR("Unsupported IGA1 Color Depth: %d bit\n",
+   depth);
+   }
+
+   DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void

[PATCH v2 06/32] drm/via: Add via_regs.h

From: Kevin Brace 

Likely originated from VIA Technologies.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_regs.h | 296 +
 1 file changed, 296 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_regs.h

diff --git a/drivers/gpu/drm/via/via_regs.h b/drivers/gpu/drm/via/via_regs.h
new file mode 100644
index ..5ac06d75f0b5
--- /dev/null
+++ b/drivers/gpu/drm/via/via_regs.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ *
+ *  File:   via_regs.h
+ *  Content:The defines of VIA Technologies Chrome registers.
+ *
+ /
+
+#ifndef _VIA_REGS_H_
+#define _VIA_REGS_H_ 1
+
+#define BIOS_BSIZE  1024
+#define BIOS_BASE   0xc
+
+#define VIA_MMIO_REGSIZE0xD000 /* DisplayPort:0xC610~0xC7D4 */
+#define VIA_MMIO_REGBASE0x0
+#define VIA_MMIO_VGABASE0x8000
+#define VIA_MMIO_BLTBASE0x20
+#define VIA_MMIO_BLTSIZE0x20
+
+/* defines for VIA 2D registers */
+#define VIA_REG_GECMD  0x000
+#define VIA_REG_GEMODE 0x004
+#define VIA_REG_GESTATUS   0x004   /* as same as VIA_REG_GEMODE */
+#define VIA_REG_SRCPOS 0x008
+#define VIA_REG_DSTPOS 0x00C
+#define VIA_REG_LINE_K1K2  0x008
+#define VIA_REG_LINE_XY0x00C
+#define VIA_REG_DIMENSION  0x010   /* width and height */
+#define VIA_REG_PATADDR0x014
+#define VIA_REG_FGCOLOR0x018
+#define VIA_REG_DSTCOLORKEY0x018   /* as same as VIA_REG_FG */
+#define VIA_REG_BGCOLOR0x01C
+#define VIA_REG_SRCCOLORKEY0x01C   /* as same as VIA_REG_BG */
+#define VIA_REG_CLIPTL 0x020   /* top and left of clipping */
+#define VIA_REG_CLIPBR 0x024   /* bottom and right of clipping */
+#define VIA_REG_OFFSET 0x028
+#define VIA_REG_LINE_ERROR 0x028
+#define VIA_REG_KEYCONTROL 0x02C   /* color key control */
+#define VIA_REG_SRCBASE0x030
+#define VIA_REG_DSTBASE0x034
+#define VIA_REG_PITCH  0x038   /* pitch of src and dst */
+#define VIA_REG_MONOPAT0   0x03C
+#define VIA_REG_MONOPAT1   0x040
+#define VIA_REG_COLORPAT   0x100   /* from 0x100 to 0x1ff */
+
+/* defineds vor VIA 2D registers for VT3353 (M1 engine) */
+#define VIA_REG_GECMD_M1   0x000
+#define VIA_REG_GEMODE_M1  0x004
+#define VIA_REG_GESTATUS_M10x004   /* as same as VIA_REG_GEMODE */
+#define VIA_REG_PITCH_M1   0x008   /* pitch of src and dst */
+#define VIA_REG_DIMENSION_M1   0x00C   /* width and height */
+#define VIA_REG_DSTPOS_M1  0x010
+#define VIA_REG_LINE_XY_M1 0x010
+#define VIA_REG_DSTBASE_M1 0x014
+#define VIA_REG_SRCPOS_M1  0x018
+#define VIA_REG_LINE_K1K2_M1   0x018
+#define VIA_REG_SRCBASE_M1 0x01C
+#define VIA_REG_PATADDR_M1 0x020
+#define VIA_REG_MONOPAT0_M10x024
+#define VIA_REG_MONOPAT1_M10x028
+#define VIA_REG_OFFSET_M1  0x02C
+#define VIA_REG_LINE_ERROR_M1  0x02C
+#define VIA_REG_CLIPTL_M1  0x040   /* top and left of clipping */
+#define VIA_REG_CLIPBR_M1  0x044   /* bottom and right of clipping */
+#define VIA_REG_KEYCONTROL_M1  0x048   /* color key control */
+#define VIA_REG_FGCOLOR_M1 0x04C
+#define VIA_REG_DSTCOLORKEY_M1 0x04C   /* as same as VIA_REG_FG */
+#define VIA_REG_BGCOLOR_M1 0x050
+#define VIA_REG_SRCCOLORKEY_M1 0x050   /* as same as VIA_REG_BG */
+#define VIA_REG_MONOPATFGC_M1  0x058   /* Add foreground color of Pattern */
+#define VIA_REG_MONOPATBGC_M1  0x05C   /* Add background color of Pattern */
+#define VIA_REG_COLORPAT_M1

[PATCH v2 05/32] drm/via: Add via_drv.h

From: Kevin Brace 

Main header file for the module.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_drv.h | 437 ++
 1 file changed, 437 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_drv.h

diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
new file mode 100644
index ..330ab8905417
--- /dev/null
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -0,0 +1,437 @@
+/*
+ * Copyright © 2019 Kevin Brace.
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * Kevin Brace 
+ * James Simmons 
+ */
+
+#ifndef _VIA_DRV_H
+#define _VIA_DRV_H
+
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "via_crtc_hw.h"
+#include "via_regs.h"
+
+
+#define DRIVER_MAJOR   3
+#define DRIVER_MINOR   5
+#define DRIVER_PATCHLEVEL  2
+#define DRIVER_NAME"via"
+#define DRIVER_DESC"OpenChrome DRM for VIA Technologies Chrome IGP"
+#define DRIVER_DATE"20220620"
+#define DRIVER_AUTHOR  "OpenChrome Project"
+
+
+#define VIA_TTM_PL_NUM 2
+
+#define VIA_MAX_CRTC   2
+
+#define VIA_CURSOR_SIZE64
+
+#define VIA_MM_ALIGN_SIZE  16
+
+
+#define CLE266_REVISION_AX 0x0A
+#define CLE266_REVISION_CX 0x0C
+
+#define CX700_REVISION_700 0x0
+#define CX700_REVISION_700M0x1
+#define CX700_REVISION_700M2   0x2
+
+#define VIA_MEM_NONE   0x00
+#define VIA_MEM_SDR66  0x01
+#define VIA_MEM_SDR100 0x02
+#define VIA_MEM_SDR133 0x03
+#define VIA_MEM_DDR_2000x04
+#define VIA_MEM_DDR_2660x05
+#define VIA_MEM_DDR_3330x06
+#define VIA_MEM_DDR_4000x07
+#define VIA_MEM_DDR2_400   0x08
+#define VIA_MEM_DDR2_533   0x09
+#define VIA_MEM_DDR2_667   0x0A
+#define VIA_MEM_DDR2_800   0x0B
+#define VIA_MEM_DDR2_1066  0x0C
+#define VIA_MEM_DDR3_533   0x0D
+#define VIA_MEM_DDR3_667   0x0E
+#define VIA_MEM_DDR3_800   0x0F
+#define VIA_MEM_DDR3_1066  0x10
+#define VIA_MEM_DDR3_1333  0x11
+#define VIA_MEM_DDR3_1600  0x12
+
+/* IGA Scaling disable */
+#define VIA_NO_SCALING 0
+
+/* IGA Scaling down */
+#define VIA_HOR_SHRINK BIT(0)
+#define VIA_VER_SHRINK BIT(1)
+#define VIA_SHRINK (BIT(0) | BIT(1))
+
+/* IGA Scaling up */
+#define VIA_HOR_EXPAND BIT(2)
+#define VIA_VER_EXPAND BIT(3)
+#define VIA_EXPAND (BIT(2) | BIT(3))
+
+/* Define IGA Scaling up/down status :  Horizontal or Vertical  */
+/* Is IGA Hor scaling up/down status */
+#defineHOR_SCALE   BIT(0)
+/* Is IGA Ver scaling up/down status */
+#defineVER_SCALE   BIT(1)
+/* Is IGA Hor and Ver scaling up/down status */
+#defineHOR_VER_SCALE   (BIT(0) | BIT(1))
+
+#defineVIA_I2C_NONE0x0
+#defineVIA_I2C_BUS1BIT(0)
+#defineVIA_I2C_BUS2BIT(1)
+#defineVIA_I2C_BUS3BIT(2)
+#defineVIA_I2C_BUS4BIT(3)
+#defineVIA_I2C_BUS5BIT(4)
+
+#define VIA_DI_PORT_NONE   0x0
+#define VIA_DI_PORT_DIP0   BIT(0)
+#define VIA_DI_PORT_DIP1   BIT(1)
+#define VIA_DI_PORT_DVP0   BIT(2)
+#define VIA_DI_PORT_DVP1   BIT(3)
+#define VIA_DI_PORT_DFPL   BIT(4)
+#define VIA_DI_PORT_FPDPLOWBIT(4)
+#define VIA_DI_PORT_DFPH   BIT(5)
+#define VIA_DI_PORT_FPDPHIGH   BIT(5)
+#define VIA_DI_PORT_DFPBIT(6)
+#define VIA_DI_PORT_LVDS1  BIT(7)
+#define VIA_DI_PORT_TMDS   BIT(7)
+#define VIA_DI_PORT_LVDS2  BIT(8)
+
+/* External TMDS (DVI) Transmitter Type */
+#defineVIA_TMDS_NONE   0x0
+#defineVIA_TMDS_VT1632 BIT(0)
+#defineVIA_TMDS_SII164 BIT(1)
+
+
+typedef struct _via_lvds_info {
+   u32 x;
+   u32 y;
+} via_lvds_info;
+
+struct via_crtc {

[PATCH v2 04/32] drm/via: Add via_disp_reg.h

From: Kevin Brace 

Likely originated from VIA Technologies.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_disp_reg.h | 513 +
 1 file changed, 513 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_disp_reg.h

diff --git a/drivers/gpu/drm/via/via_disp_reg.h 
b/drivers/gpu/drm/via/via_disp_reg.h
new file mode 100644
index ..e2bd895bb495
--- /dev/null
+++ b/drivers/gpu/drm/via/via_disp_reg.h
@@ -0,0 +1,513 @@
+/*
+ * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __VIA_DISP_REG_H__
+#define __VIA_DISP_REG_H__
+
+//
+/* Definition IGA Design Method of FIFO Registers  */
+//
+#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)  ((x >> 1) - 1)
+#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)  ((x >> 3) - 1)
+
+/* Define Display OFFSET */
+/* VT3314 chipset */
+#define CN700_IGA1_FIFO_MAX_DEPTH  96  /* location: 
{SR17,0,7}*/
+#define CN700_IGA1_FIFO_THRESHOLD  80  /* location: 
{SR16,0,5},{SR16,7,7}*/
+#define CN700_IGA1_FIFO_HIGH_THRESHOLD 64  /* location: 
{SR18,0,5},{SR18,7,7}*/
+#define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM128 /* location: 
{SR22,0,4}. (128/4) =64,
+* P800 must be set 
zero, because HW
+* only 5 bits */
+#define CN700_IGA2_FIFO_MAX_DEPTH  96  /* location: 
{CR68,4,7},{CR94,7,7},{CR95,7,7}*/
+#define CN700_IGA2_FIFO_THRESHOLD  80  /* location: 
{CR68,0,3},{CR95,4,6}*/
+#define CN700_IGA2_FIFO_HIGH_THRESHOLD 32  /* location: 
{CR92,0,3},{CR95,0,2}*/
+#define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM128 /* location: 
{CR94,0,6}*/
+
+/* For VT3324, these values are suggested by HW */
+#define CX700_IGA1_FIFO_MAX_DEPTH  192 /* location: 
{SR17,0,7}*/
+#define CX700_IGA1_FIFO_THRESHOLD  128 /* location: 
{SR16,0,5},{SR16,7,7}*/
+#define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 /* location: 
{SR18,0,5},{SR18,7,7} */
+#define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM124 /* location: {SR22,0,4} 
*/
+
+#define CX700_IGA2_FIFO_MAX_DEPTH  96  /* location: 
{CR68,4,7},{CR94,7,7},{CR95,7,7}*/
+#define CX700_IGA2_FIFO_THRESHOLD  64  /* location: 
{CR68,0,3},{CR95,4,6}*/
+#define CX700_IGA2_FIFO_HIGH_THRESHOLD 32  /* location: 
{CR92,0,3},{CR95,0,2} */
+#define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM128 /* location: 
{CR94,0,6}*/
+
+/* VT3336 chipset */
+#define K8M890_IGA1_FIFO_MAX_DEPTH 360 /* location: 
{SR17,0,7}*/
+#define K8M890_IGA1_FIFO_THRESHOLD 328 /* location: 
{SR16,0,5},{SR16,7,7}*/
+#define K8M890_IGA1_FIFO_HIGH_THRESHOLD296 /* location: 
{SR18,0,5},{SR18,7,7}*/
+#define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM   124 /* location: 
{SR22,0,4}.*/
+
+#define K8M890_IGA2_FIFO_MAX_DEPTH 360 /* location: 
{CR68,4,7},{CR94,7,7},{CR95,7,7}*/
+#define K8M890_IGA2_FIFO_THRESHOLD 328 /* location: 
{CR68,0,3},{CR95,4,6}*/
+#define K8M890_IGA2_FIFO_HIGH_THRESHOLD296 /* location: 
{CR92,0,3},{CR95,0,2}*/
+#define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM   124 /* location: 
{CR94,0,6}*/
+
+/* VT3327 chipset */
+#define P4M890_IGA1_FIFO_MAX_DEPTH 96  /* location: 
{SR17,0,7}*/
+#define P4M890_IGA1_FIFO_THRESHOLD 76  /* location: 
{SR16,0,5},{SR16,7,7}*/
+#define P4M890_IGA1_FIFO_HIGH_THRESHOLD64  /* location: 
{SR18,0,5},{SR18,7,7}*/
+#define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM

[PATCH v2 03/32] drm/via: Add via_crtc_hw.h

From: Kevin Brace 

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_crtc_hw.h | 1048 +
 1 file changed, 1048 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_crtc_hw.h

diff --git a/drivers/gpu/drm/via/via_crtc_hw.h 
b/drivers/gpu/drm/via/via_crtc_hw.h
new file mode 100644
index ..9cce4fdcb33a
--- /dev/null
+++ b/drivers/gpu/drm/via/via_crtc_hw.h
@@ -0,0 +1,1048 @@
+/*
+ * Copyright 2012 James Simmons. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author(s):
+ * James Simmons 
+ */
+
+#ifndef __CRTC_HW_H__
+#define __CRTC_HW_H__
+
+#include 
+
+#include 
+
+
+/* To be used with via_dac_set_dpms_control inline function. */
+#define VIA_DAC_DPMS_ON0x00
+#define VIA_DAC_DPMS_STANDBY   0x01
+#define VIA_DAC_DPMS_SUSPEND   0x02
+#define VIA_DAC_DPMS_OFF   0x03
+
+
+struct vga_regset {
+   u16 ioport;
+   u8  io_addr;
+   u8  start_bit;
+   u8  end_bit;
+};
+
+struct vga_registers {
+   unsigned int count;
+   struct vga_regset *regs;
+};
+
+/
+ * Display Timing   *
+ /
+
+struct crtc_timings {
+   struct vga_registers htotal;
+   struct vga_registers hdisplay;
+   struct vga_registers hblank_start;
+   struct vga_registers hblank_end;
+   struct vga_registers hsync_start;
+   struct vga_registers hsync_end;
+   struct vga_registers vtotal;
+   struct vga_registers vdisplay;
+   struct vga_registers vblank_start;
+   struct vga_registers vblank_end;
+   struct vga_registers vsync_start;
+   struct vga_registers vsync_end;
+};
+
+/* Write a value to misc register with a mask */
+static inline void svga_wmisc_mask(void __iomem *regbase, u8 data, u8 mask)
+{
+   vga_w(regbase, VGA_MIS_W, (data & mask) | (vga_r(regbase, VGA_MIS_R) & 
~mask));
+}
+
+/* Write a value to a sequence register with a mask */
+static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 
mask)
+{
+   vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & 
~mask));
+}
+
+/* Write a value to a CRT register with a mask */
+static inline void svga_wcrt_mask(void __iomem *regbase, u8 index, u8 data, u8 
mask)
+{
+   vga_wcrt(regbase, index, (data & mask) | (vga_rcrt(regbase, index) & 
~mask));
+}
+
+
+/***
+
+ VIA Technologies Chrome IGP Register Access Helper Functions
+
+***/
+
+static inline void
+via_iga1_set_palette_lut_resolution(void __iomem *regs,
+   bool palette_lut)
+{
+   /* Set the palette LUT resolution for IGA1. */
+   /* 3C5.15[7] - IGA1 6 / 8 Bit LUT
+* 0: 6-bit
+* 1: 8-bit */
+   svga_wseq_mask(regs, 0x15, palette_lut ? BIT(7) : 0x00, BIT(7));
+   DRM_DEBUG_KMS("IGA1 Palette LUT Resolution: %s bit\n",
+   palette_lut ? "8" : "6");
+}
+
+static inline void
+via_iga2_set_palette_lut_resolution(void __iomem *regs,
+   bool palette_lut)
+{
+   /* Set the palette LUT resolution for IGA2. */
+   /* 3X5.6A[5] - IGA2 6 / 8 Bit LUT
+* 0: 6-bit
+* 1: 8-bit */
+   svga_wcrt_mask(regs, 0x6a, palette_lut ? BIT(5) : 0x00, BIT(5));
+   DRM_DEBUG_KMS("IGA2 Palette LUT Resolution: %s bit\n",
+   palette_lut ? "8" : "6");
+}
+
+static inline void
+via_iga1_set_interlace_mode(void __iomem *regs, bool interlace_mode)
+{
+   svga_wcrt_mask(regs, 0x33,
+   interlace_mode ? BIT(6) : 0x00, BIT(6));
+   DRM_DEBUG_KMS("IGA1 Interlace Mode: %s\n",
+

[PATCH v2 02/32] drm/via: Add via_3d_reg.h

From: Kevin Brace 

Originated from VIA Technologies.  Currently unused.

Signed-off-by: Kevin Brace 
---
 drivers/gpu/drm/via/via_3d_reg.h | 1863 ++
 1 file changed, 1863 insertions(+)
 create mode 100644 drivers/gpu/drm/via/via_3d_reg.h

diff --git a/drivers/gpu/drm/via/via_3d_reg.h b/drivers/gpu/drm/via/via_3d_reg.h
new file mode 100644
index ..fc74647f512a
--- /dev/null
+++ b/drivers/gpu/drm/via/via_3d_reg.h
@@ -0,0 +1,1863 @@
+/*
+ * Copyright 1998-2011 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2011 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VIA_3D_REG_H
+#define VIA_3D_REG_H
+#define HC_REG_BASE 0x0400
+
+#define HC_REG_TRANS_SPACE  0x0040
+
+#define HC_ParaN_MASK   0x
+#define HC_Para_MASK0x00ff
+#define HC_SubA_MASK0xff00
+#define HC_SubA_SHIFT   24
+/* Transmission Setting
+ */
+#define HC_REG_TRANS_SET0x003c
+#define HC_ParaSubType_MASK 0xff00
+#define HC_ParaType_MASK0x00ff
+#define HC_ParaOS_MASK  0xff00
+#define HC_ParaAdr_MASK 0x00ff
+#define HC_ParaSubType_SHIFT24
+#define HC_ParaType_SHIFT   16
+#define HC_ParaOS_SHIFT 8
+#define HC_ParaAdr_SHIFT0
+
+#define HC_ParaType_CmdVdata0x
+#define HC_ParaType_NotTex  0x0001
+#define HC_ParaType_Tex 0x0002
+#define HC_ParaType_Palette 0x0003
+#define HC_ParaType_PreCR   0x0010
+#define HC_ParaType_Auto0x00fe
+#define INV_ParaType_Dummy  0x0030
+
+/* Transmission Space
+ */
+#define HC_REG_Hpara0   0x0040
+#define HC_REG_HpataAF  0x02fc
+
+/* Read
+ */
+#define HC_REG_HREngSt  0x
+#define HC_REG_HRFIFOempty  0x0004
+#define HC_REG_HRFIFOfull   0x0008
+#define HC_REG_HRErr0x000c
+#define HC_REG_FIFOstatus   0x0010
+/* HC_REG_HREngSt  0x
+ */
+#define HC_HDASZC_MASK  0x0001
+#define HC_HSGEMI_MASK  0xf000
+#define HC_HLGEMISt_MASK0x0f00
+#define HC_HCRSt_MASK   0x0080
+#define HC_HSE0St_MASK  0x0040
+#define HC_HSE1St_MASK  0x0020
+#define HC_HPESt_MASK   0x0010
+#define HC_HXESt_MASK   0x0008
+#define HC_HBESt_MASK   0x0004
+#define HC_HE2St_MASK   0x0002
+#define HC_HE3St_MASK   0x0001
+/* HC_REG_HRFIFOempty  0x0004
+ */
+#define HC_HRZDempty_MASK   0x0010
+#define HC_HRTXAempty_MASK  0x0008
+#define HC_HRTXDempty_MASK  0x0004
+#define HC_HWZDempty_MASK   0x0002
+#define HC_HWCDempty_MASK   0x0001
+/* HC_REG_HRFIFOfull   0x0008
+ */
+#define HC_HRZDfull_MASK0x0010
+#define HC_HRTXAfull_MASK   0x0008
+#define HC_HRTXDfull_MASK   0x0004
+#define HC_HWZDfull_MASK0x0002
+#define HC_HWCDfull_MASK0x0001
+/* HC_REG_HRErr0x000c
+ */
+#define HC_HAGPCMErr_MASK   0x8000
+#define HC_HAGPCMErrC_MASK  0x7000
+/* HC_REG_FIFOstatus   0x0010
+ */
+#define HC_HRFIFOATall_MASK 0x8000
+#define HC_HRFIFOATbusy_MASK0x4000
+#define HC_HRATFGMDo_MASK   0x0100
+#define HC_HRATFGMDi_MASK   0x0080
+#define HC_HRATFRZD_MASK0x0040
+#define HC_HRATFRTXA_MASK   0x0020
+#define HC_HRATFRTXD_MASK   0x0010
+#define HC_HRATFWZD_MASK0x0008
+#define HC_HRATFWCD_MASK0x0004
+#define HC_HRATTXTAG_MASK   0x0002
+#define HC_HRATTXCH_MASK0x0001
+
+/* AGP Command Setting
+ */
+#define HC_SubA_HAGPBstL0x0060
+#define HC_SubA_HAGPBendL   0x0061
+#define HC_SubA_HAGPCMNT0x0062
+#define HC_SubA_HAGPBpL 0x0063
+#define HC_SubA_HAGPBpH 0x0064
+/* HC_SubA_HAGPCMNT

[PATCH v2 00/32] OpenChrome DRM for Linux 5.20

From: Kevin Brace 

OpenChrome DRM for Linux 5.20

Hi Dave and Daniel,

This is my first attempt (this is not a RFC posting) in trying to get
OpenChrome DRM pulled in for Linux 5.20.
I started to work on this seriously around the summer of 2017, so it has
been a long journey.
I know that the code is not quite perfect, but I have done as much work
as I can do on my own, and I now think that I should post the code on
dri-devel mailing list for other people to take a look at it.
Whether or not the code itself works or not, no, OpenChrome DRM is not
some vaporware, and the code reliability is comparable to the existing
OpenChrome DDX UMS code path.
The code reliability is more than good enough to the point where I utilize
the module almost every time I work on developing the code.
I am aware that the hardware (silicon) is quite old by today's standards,
so not too many people "still" (the word one open source software focused
journalist often uses to describe greater than 5 year old computer
hardware) own the VIA silicon hardware to actually test the code
themselves.
The current code is developed against drm-next branch
drm-next-2022-06-03-1 tag.
The current iteration of the code has no support for acceleration.
It is currently a mode setting only DRM module.
Even if the code is pulled into the Linux kernel tree, I will consider
the code experimental until at least 2D acceleration is implemented for
all supported devices.
Because of this, the DRM module requires via.modeset=1 to be added to
Linux kernel boot option line for it to function, and I intend to keep
this arrangement in place until at least 2D acceleration is fully
supported.
As a result, I think the code is fairly low risk to be pulled into the
Linux kernel tree.
The current module version is 3.5.2, but when the code is about to
be pulled into the kernel tree, I will like to up the version to 4.0.0.
This is because James Simmons era OpenChrome DRM used version number
3.0.x, but the current OpenChrome DRM uAPI implementation is different
from his implementation, so I will like to assign a new major version
(i.e., 4) so that DDX can distinguish the old and new OpenChrome DRM.
The current uAPI has no backward compatibility with the older DRI1 based
implementation, although some remnants of old DRI1 based uAPI still needs
to be there inside via_drm.h for XvMC based libraries on the DDX side to
properly compile.
It is my intention to replace the old DRI1 based VIA DRM located at
drivers/gpu/drm/via/ with OpenChrome DRM at the same location.
As I indicated previously, I do not wish to get pulled into the staging
area of the kernel tree.
I personally will like to have the option of porting the code to
BSD someday, however, the I2C bus access module (via_i2c.c) is GPL
based, so the DRM module license type is GPL (everything else is MIT
license based), for now.
I hope to replace this module someday with equivalent functionality
code that will be MIT license based.
I hope the uAPI variable types are compatible with BSD (please give
me advise on this since I do not know too much about this) since James
Simmons brought this up back in 2013 when he posted the code as RFC.

https://lists.freedesktop.org/archives/dri-devel/2013-June/039594.html
https://lists.freedesktop.org/archives/dri-devel/2013-June/040811.html


Features:

- Supports 12 different generations of VIA Technologies Chrome based
integrated graphics (CLE266 / KM400 / K8M800 / P4M800 Pro / PM800 /
P4M890 / K8M890 / P4M900 / CX700 / VX800 / VX855 / VX900 chipset) and
their variants
- Support for DAC (VGA), LVDS flat panel, DVI (CX700 / VX800 chipset
integrated, VX900 chipset integrated, and Silicon Image SiI164 /
VIA Technologies VT1632(A) DVI transmitter), and HDMI (VX900H chipset
integrated)
- Support for standby resume (ACPI S3 State)
- Support for dual head operation
- Supports atomic mode setting (implementation might still be incomplete
especially around gamma correction / palette initialization)
- Utilizes GEM / TTM for memory management
- Utilizes DRM FB Helper for FBDEV emulation


Known issues:

- via_lvds.c gives out 3 unused function warnings (willing to delete
the offending functions since they are not used)
- Gamma correction / palette initialization code is still legacy KMS
based (Daniel, how do I convert it for atomic mode setting?)
- uAPI might not be quite right (Do I need something like
DRM_IOCTL_VIA_GEM_DESTROY or DRM_IOCTL_VIA_GEM_FREE call to pair it
against DRM_IOCTL_VIA_GEM_CREATE?)


Code repository:
https://cgit.freedesktop.org/openchrome/drm-openchrome/

Current bleeding edge branch (drm-next-5.20 branch):
https://cgit.freedesktop.org/openchrome/drm-openchrome/?h=drm-next-5.20

Current bleeding edge branch (drm-next-5.20 branch) code location:
https://cgit.freedesktop.org/openchrome/drm-openchrome/tree/drivers/gpu/drm/via?h=drm-next-5.20
https://cgit.freedesktop.org/openchrome/drm-openchrome/tree/include/uapi/drm?h=drm-next-5.20

Obviously, I do not expect to get the code

Re: [PATCH] gpu: drm: selftests: drop unexpected word 'for' in comments

…ah, I totally forgot that gitlab happens to be down right now which part of
the DRM maintainer scripts rely on - so I can't actually push this patch
upstream right away. I will set this email as unread so hopefully I don't lose
track of this, but please feel free to ping me if I do end up forgetting.

On Tue, 2022-06-28 at 17:32 -0400, Lyude Paul wrote:
> Reviewed-by: Lyude Paul 
> 
> Going to change the name of the patch slightly so it's more obvious this is
> just about the MST selftests
> 
> On Thu, 2022-06-23 at 18:06 +0800, Jiang Jian wrote:
> > there is an unexpected word 'for' in the comments that need to be dropped
> > 
> > file - ./drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > line - 3
> > 
> > * Test cases for for the DRM DP MST helpers
> > 
> > changed to:
> > 
> > * Test cases for the DRM DP MST helpers
> > 
> > Signed-off-by: Jiang Jian 
> > ---
> >  drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > index 967c52150b67..4caa9be900ac 100644
> > --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> > @@ -1,6 +1,6 @@
> >  // SPDX-License-Identifier: GPL-2.0-only
> >  /*
> > - * Test cases for for the DRM DP MST helpers
> > + * Test cases for the DRM DP MST helpers
> >   */
> >  
> >  #define PREFIX_STR "[drm_dp_mst_helper]"
> 

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [RFC PATCH 4/5] drm/drm_color_mgmt: add 3D LUT to color mgmt properties




On 6/19/22 18:31, Melissa Wen wrote:
> Add 3D LUT for gammar correction using a 3D lookup table.  The position
> in the color correction pipeline where 3D LUT is applied depends on hw
> design, being after CTM or gamma. If just after CTM, a shaper lut must
> be set to shape the content for a non-linear space. That details should
> be handled by the driver according to its color capabilities.
> 
> Signed-off-by: Melissa Wen 
> ---
>  drivers/gpu/drm/drm_atomic_state_helper.c |  3 ++
>  drivers/gpu/drm/drm_atomic_uapi.c | 14 +-
>  drivers/gpu/drm/drm_color_mgmt.c  | 58 +++
>  drivers/gpu/drm/drm_fb_helper.c   |  2 +
>  drivers/gpu/drm/drm_mode_config.c | 14 ++
>  include/drm/drm_color_mgmt.h  |  4 ++
>  include/drm/drm_crtc.h| 12 -
>  include/drm/drm_mode_config.h | 13 +
>  8 files changed, 117 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c 
> b/drivers/gpu/drm/drm_atomic_state_helper.c
> index cf0545bb6e00..64800bc41365 100644
> --- a/drivers/gpu/drm/drm_atomic_state_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_state_helper.c
> @@ -141,6 +141,8 @@ void __drm_atomic_helper_crtc_duplicate_state(struct 
> drm_crtc *crtc,
>   drm_property_blob_get(state->ctm);
>   if (state->shaper_lut)
>   drm_property_blob_get(state->shaper_lut);
> + if (state->lut3d)
> + drm_property_blob_get(state->lut3d);
>   if (state->gamma_lut)
>   drm_property_blob_get(state->gamma_lut);
>  
> @@ -216,6 +218,7 @@ void __drm_atomic_helper_crtc_destroy_state(struct 
> drm_crtc_state *state)
>   drm_property_blob_put(state->degamma_lut);
>   drm_property_blob_put(state->ctm);
>   drm_property_blob_put(state->shaper_lut);
> + drm_property_blob_put(state->lut3d);
>   drm_property_blob_put(state->gamma_lut);
>  }
>  EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 6468f2a080bc..1896c0422f73 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -472,6 +472,14 @@ static int drm_atomic_crtc_set_property(struct drm_crtc 
> *crtc,
>   );
>   state->color_mgmt_changed |= replaced;
>   return ret;
> + } else if (property == config->lut3d_property) {
> + ret = drm_atomic_replace_property_blob_from_id(dev,
> + >lut3d,
> + val,
> + -1, sizeof(struct drm_color_lut),
> + );
> + state->color_mgmt_changed |= replaced;
> + return ret;
>   } else if (property == config->gamma_lut_property) {
>   ret = drm_atomic_replace_property_blob_from_id(dev,
>   >gamma_lut,
> @@ -523,10 +531,12 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
>   *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
>   else if (property == config->ctm_property)
>   *val = (state->ctm) ? state->ctm->base.id : 0;
> - else if (property == config->gamma_lut_property)
> - *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
>   else if (property == config->shaper_lut_property)
>   *val = (state->shaper_lut) ? state->shaper_lut->base.id : 0;
> + else if (property == config->lut3d_property)
> + *val = (state->lut3d) ? state->lut3d->base.id : 0;
> + else if (property == config->gamma_lut_property)
> + *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
>   else if (property == config->prop_out_fence_ptr)
>   *val = 0;
>   else if (property == crtc->scaling_filter_property)
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c 
> b/drivers/gpu/drm/drm_color_mgmt.c
> index 4f57dc60fe03..696fe1e37801 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -87,6 +87,25 @@
>   *   publish the largest size, and sub-sample smaller sized LUTs
>   *   appropriately.
>   *
> + * “LUT3D”:
> + *   Blob property to set the 3D LUT mapping pixel data after the color
> + *   transformation matrix and before gamma 1D lut correction. The
> + *   data is interpreted as an array of  drm_color_lut elements.
> + *   Hardware might choose not to use the full precision of the LUT
> + *   elements.
> + *
> + *   Setting this to NULL (blob property value set to 0) means a the output
> + *   color is identical to the input color. This is generally the driver
> + *   boot-up state too. Drivers can access this blob through
> + *   _crtc_state.gamma_lut.
> + *
> + * “LUT3D_SIZE”:
> + *   Unsigned range property to give the size of the 3D lookup table to be
> + *   set on the LUT3D

[Bug 216119] 087451f372bf76d breaks hibernation on amdgpu Radeon R9 390

https://bugzilla.kernel.org/show_bug.cgi?id=216119

--- Comment #27 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301300
  --> https://bugzilla.kernel.org/attachment.cgi?id=301300=edit
patch 2/2

-- 
You may reply to this email to add a comment.

You are receiving this mail because:
You are watching the assignee of the bug.

[Bug 216119] 087451f372bf76d breaks hibernation on amdgpu Radeon R9 390

https://bugzilla.kernel.org/show_bug.cgi?id=216119

--- Comment #26 from Alex Deucher (alexdeuc...@gmail.com) ---
Created attachment 301299
  --> https://bugzilla.kernel.org/attachment.cgi?id=301299=edit
patch 1/2

Can you try the attached 2 patches (without any previous patches) both with and
without amdgpu.dc=0?

-- 
You may reply to this email to add a comment.

You are receiving this mail because:
You are watching the assignee of the bug.

Re: [PATCH] gpu: drm: selftests: drop unexpected word 'for' in comments

Reviewed-by: Lyude Paul 

Going to change the name of the patch slightly so it's more obvious this is
just about the MST selftests

On Thu, 2022-06-23 at 18:06 +0800, Jiang Jian wrote:
> there is an unexpected word 'for' in the comments that need to be dropped
> 
> file - ./drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> line - 3
> 
> * Test cases for for the DRM DP MST helpers
> 
> changed to:
> 
> * Test cases for the DRM DP MST helpers
> 
> Signed-off-by: Jiang Jian 
> ---
>  drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> index 967c52150b67..4caa9be900ac 100644
> --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  /*
> - * Test cases for for the DRM DP MST helpers
> + * Test cases for the DRM DP MST helpers
>   */
>  
>  #define PREFIX_STR "[drm_dp_mst_helper]"

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [RFC PATCH 2/5] Documentation/amdgpu/display: add DC color caps info




On 6/19/22 18:31, Melissa Wen wrote:
> Add details about color correction capabilities and explain a bit about
> differences between DC hw generations and also how they are mapped
> between DRM and DC interface. Two schemas for DCN 2.0 and 3.0
> (rasterized from the original png) is included to illustrate it. They
> were obtained from a discussion[1] in the amd-gfx mailing list.
> 
> [1] 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Famd-gfx%2F20220422142811.dm6vtk6v64jcwydk%40mail.igalia.com%2Fdata=05%7C01%7Charry.wentland%40amd.com%7C11fb474339ba49ad492a08da52439534%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637912748027800719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7Csdata=1eUQmjydQoDifmsZHfS%2F9PPEJeaZvQ4xGgjblTL9dZE%3Dreserved=0
> 
> Signed-off-by: Melissa Wen 
> ---
>  .../amdgpu/display/dcn2_cm_drm_current.svg| 1370 +++
>  .../amdgpu/display/dcn3_cm_drm_current.svg| 1528 +
>  .../gpu/amdgpu/display/display-manager.rst|   35 +
>  drivers/gpu/drm/amd/display/dc/dc.h   |   53 +-
>  4 files changed, 2985 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>  create mode 100644 Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
> 
> diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg 
> b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> new file mode 100644
> index ..0156f56d4482
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> @@ -0,0 +1,1370 @@
> +
> +
> +
> + +   version="1.1"
> +   id="svg2019"
> +   width="1702"
> +   height="1845"
> +   viewBox="0 0 1702 1845"
> +   sodipodi:docname="dcn2_cm_drm_current.svg"
> +   inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
> +   
> xmlns:inkscape="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.inkscape.org%2Fnamespaces%2Finkscapedata=05%7C01%7Charry.wentland%40amd.com%7C11fb474339ba49ad492a08da52439534%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637912748027800719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7Csdata=RV2BnPZ1Ash3pjMW8pWj%2FG%2FMiWXYfuxgCsaeDIchYOQ%3Dreserved=0;
> +   
> xmlns:sodipodi="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fsodipodi.sourceforge.net%2FDTD%2Fsodipodi-0.dtddata=05%7C01%7Charry.wentland%40amd.com%7C11fb474339ba49ad492a08da52439534%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637912748027800719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7Csdata=HMMzEZP%2BCNjxPLjW8R0sK3Q%2FRANhtKg7Q65pQZdWDw8%3Dreserved=0;
> +   
> xmlns="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.w3.org%2F2000%2Fsvgdata=05%7C01%7Charry.wentland%40amd.com%7C11fb474339ba49ad492a08da52439534%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637912748027800719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7Csdata=vx9VHcwk90HcOCQRAFGldDF0qI4teUyzWiojodX3tKc%3Dreserved=0;
> +   
> xmlns:svg="https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.w3.org%2F2000%2Fsvgdata=05%7C01%7Charry.wentland%40amd.com%7C11fb474339ba49ad492a08da52439534%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637912748027800719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000%7C%7C%7Csdata=vx9VHcwk90HcOCQRAFGldDF0qI4teUyzWiojodX3tKc%3Dreserved=0;>
> +   + id="defs2023" />
> +   + id="namedview2021"
> + pagecolor="#ff"
> + bordercolor="#66"
> + borderopacity="1.0"
> + inkscape:pageshadow="2"
> + inkscape:pageopacity="0.0"
> + inkscape:pagecheckerboard="0"
> + showgrid="false"
> + inkscape:zoom="0.56413987"
> + inkscape:cx="1004.1836"
> + inkscape:cy="833.12673"
> + inkscape:window-width="1920"
> + inkscape:window-height="1131"
> + inkscape:window-x="0"
> + inkscape:window-y="0"
> + inkscape:window-maximized="1"
> + inkscape:current-layer="g2025" />
> +   + inkscape:groupmode="layer"
> + inkscape:label="Image"
> + id="g2025">
> + +   style="fill:#00;fill-opacity:0;stroke:#00;stroke-opacity:1"
> +   id="rect34"
> +   width="208.83351"
> +   height="486.09872"
> +   x="0.90158081"
> +   y="132.77872" />
> + +   style="fill:#fad7ac;fill-opacity:1;stroke:#00;stroke-opacity:1"
> +   id="rect1019"
> +   width="126.38867"
> +   height="55.320732"
> +   x="25.960823"
> +   y="188.06937" />
> + +   style="fill:#d0cee2;fill-opacity:1;stroke:#00;stroke-opacity:1"
> +   id="rect1021"
> +   width="126.38867"
> +   height="55.320732"
> +   x="25.960823"
> +   y="346.06937" />
> + +

Re: [PATCH v6 14/22] dma-buf: Introduce new locking convention

2022-06-28 Thread Intel

On 5/30/22 15:57, Dmitry Osipenko wrote:

On 5/30/22 16:41, Christian König wrote:

Hi Dmitry,

Am 30.05.22 um 15:26 schrieb Dmitry Osipenko:

Hello Christian,

On 5/30/22 09:50, Christian König wrote:

Hi Dmitry,

First of all please separate out this patch from the rest of the series,
since this is a complex separate structural change.

I assume all the patches will go via the DRM tree in the end since the
rest of the DRM patches in this series depend on this dma-buf change.
But I see that separation may ease reviewing of the dma-buf changes, so
let's try it.

That sounds like you are underestimating a bit how much trouble this
will be.

I have tried this before and failed because catching all the locks in
the right code paths are very tricky. So expect some fallout from this
and make sure the kernel test robot and CI systems are clean.

Sure, I'll fix up all the reported things in the next iteration.

BTW, have you ever posted yours version of the patch? Will be great if
we could compare the changed code paths.

No, I never even finished creating it after realizing how much work it
would be.

This patch introduces new locking convention for dma-buf users. From
now
on all dma-buf importers are responsible for holding dma-buf
reservation
lock around operations performed over dma-bufs.

This patch implements the new dma-buf locking convention by:

1. Making dma-buf API functions to take the reservation lock.

2. Adding new locked variants of the dma-buf API functions for
drivers
that need to manage imported dma-bufs under the held lock.

Instead of adding new locked variants please mark all variants which
expect to be called without a lock with an _unlocked postfix.

This should make it easier to remove those in a follow up patch set and
then fully move the locking into the importer.

Do we really want to move all the locks to the importers? Seems the
majority of drivers should be happy with the dma-buf helpers handling
the locking for them.

Yes, I clearly think so.

3. Converting all drivers to the new locking scheme.

I have strong doubts that you got all of them. At least radeon and
nouveau should grab the reservation lock in their ->attach callbacks
somehow.

Radeon and Nouveau use gem_prime_import_sg_table() and they take resv
lock already, seems they should be okay (?)

You are looking at the wrong side. You need to fix the export code path,
not the import ones.

See for example attach on radeon works like this
drm_gem_map_attach->drm_gem_pin->radeon_gem_prime_pin->radeon_bo_reserve->ttm_bo_reserve->dma_resv_lock.

Yeah, I was looking at the both sides, but missed this one.

Also i915 will run into trouble with attach. In particular since i915
starts a full ww transaction in its attach callback to be able to lock
other objects if migration is needed. I think i915 CI would catch this
in a selftest.

Perhaps it's worthwile to take a step back and figure out, if the
importer is required to lock, which callbacks might need a ww acquire
context?

(And off-topic, Since we do a lot of fancy stuff under dma-resv locks
including waiting for fences and other locks, IMO taking these locks
uninterruptible should ring a warning bell)

/Thomas

Same for nouveau and probably a few other exporters as well. That will
certainly cause a deadlock if you don't fix it.

I strongly suggest to do this step by step, first attach/detach and then
the rest.

Thank you very much for the suggestions. I'll implement them in the next
version.

[Bug 216119] 087451f372bf76d breaks hibernation on amdgpu Radeon R9 390

https://bugzilla.kernel.org/show_bug.cgi?id=216119

--- Comment #25 from Harald Judt (h.j...@gmx.at) ---
Created attachment 301298
  --> https://bugzilla.kernel.org/attachment.cgi?id=301298=edit
dmesg.out

I report success, partly.

Setting amdgpu.dc=0 on the kernel command line also exhibits the behaviour =>
Screen suspended, comes back after a while, goes blank again (but powered on),
also keyboard back for sysreq, but ssh unresponsive.

After applying patch 4 and setting amdgpu.dc=0, the system restores again, but
not smoothly. Screen suspends, comes back after a while, also keyboard, display
switches back on, machine is responsive and I could generate a dmesg which
shows that there have been test failures. dmesg.out attached, but the relevant
messages are these:

amdgpu :01:00.0: [drm:amdgpu_ib_ring_tests] *ERROR* IB test failed on sdma0
(-110).
[drm:process_one_work] *ERROR* ib ring test failed (-110).

-- 
You may reply to this email to add a comment.

You are receiving this mail because:
You are watching the assignee of the bug.

Re: [PATCH v5 5/9] drm/bridge: anx7625: Add typec_mux_set callback function

2022-06-28 Thread Prashant Malani

On Tue, Jun 28, 2022 at 1:40 PM Stephen Boyd  wrote:
>
> Quoting Prashant Malani (2022-06-28 12:48:11)
> > On Tue, Jun 28, 2022 at 12:25 PM Stephen Boyd  wrote:
> > >
> > > Quoting Prashant Malani (2022-06-22 10:34:34)
> > > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
> > > > b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > index bd21f159b973..5992fc8beeeb 100644
> > > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> [..]
> > > > +
> > > > +   if (ctx->num_typec_switches == 1)
> > >
> > > How do we handle the case where the usb-c-connector is directly
> > > connected to the RX1/TX1 and RX2/TX2 pins? This device would be an
> > > orientation (normal/reverse) and mode switch (usb/dp) in that scenario,
> > > but this code is written in a way that the orientation switch isn't
> > > going to flip the crosspoint switch for the different pin assignments.
> >
> > If all 4 SS lanes are connected to 1 usb-c-connector; there would be
> > just 1 "typec-switch" node.
> > In that case, the DT would only specify it as an "orientation-switch"
> > and register
> > an orientation-switch with the Type-C framework. The orientation switch 
> > would
> > pretty much do what the mode-switch callback does here (configuring
> > the crosspoint
> > switch).
> > One could also register a "mode-switch" there but it wouldn't do
> > anything (all 4 lanes are already
> > connected so there is nothing to re-route in the crosspoint switch).
> > Hence the above "if" check.
>
> Would we still want to route the DP traffic out if the pin assignment
> didn't have DP? Does the hardware support some mode where the DP traffic
> is shutdown? Or maybe the HPD pin needs to be quieted unless DP is
> assigned?

I reference this below, but in the 1 connector case, CC lines would also be
routed to the anx7625 from the usb-connector, so it will know when HPD
is asserted
or not.

>
> I suppose none of those things matter though as long as there is some
> typec switch registered here so that the driver can be informed of the
> pin assignment. Is it right that the "mode-switch" property is only
> required in DT if this device is going to control the mode of the
> connector, i.e. USB+DP, or just DP? Where this device can't do that
> because it doesn't support only DP.

If the anx7625 is used just to route all lanes from 1 usb-c-connector (i.e
the USB+DP case), a mode-switch wouldn't be of much use, since one
would also route the CC lines to the built-in PD controller; so it will
already have knowledge of what mode the switch is in.

The mode-switch is likely only relevant for this hardware configuration(
it's "DP only" in the sense that the USB pins to the SoC never go anywhere).
One only has 2 SS lanes each (from each usb-c-connector).

Since there is no CC-line, the anx7625 needs to know which one has DP
enabled on it.

>
> >
> > Unfortunately, I don't have hardware which connects all 4 SS lanes
> > from 1 Type-C port
> > to the anx7625, so I didn't add the orientation switch handling to the
> > driver (since I have no way of verifying it).
>
> Alright. Maybe add a TODO then so it's more obvious that orientation
> isn't handled.

Ack. Will add a comment in v6.

>
> >
> > Regarding DP alt-mode pin assignments : I think anx7625 will only support 
> > Pin D
> > (only 2 lane DP, no 4 lane DP).
> >
>
> Makes sense. Thanks!

[PATCH] fbdev: fbmem: Fix logo center image dx issue

2022-06-28 Thread Guiling Deng

Image.dx gets wrong value because of missing '()'.

If xres == logo->width and n == 1, image.dx = -16.

Signed-off-by: Guiling Deng 
---
 drivers/video/fbdev/core/fbmem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index c4a18322dee9..1fd2bdb11266 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -511,7 +511,7 @@ static int fb_show_logo_line(struct fb_info *info, int 
rotate,
 
while (n && (n * (logo->width + 8) - 8 > xres))
--n;
-   image.dx = (xres - n * (logo->width + 8) - 8) / 2;
+   image.dx = (xres - (n * (logo->width + 8) - 8)) / 2;
image.dy = y ?: (yres - logo->height) / 2;
} else {
image.dx = 0;
-- 
2.25.1

Re: [PATCH v6 3/4] fbcon: Prevent that screen size is smaller than font size

2022-06-28 Thread Helge Deller

On 6/28/22 10:39, Geert Uytterhoeven wrote:
> Hi Helge,
>
> On Sun, Jun 26, 2022 at 12:33 PM Helge Deller  wrote:
>> We need to prevent that users configure a screen size which is smaller than 
>> the
>> currently selected font size. Otherwise rendering chars on the screen will
>> access memory outside the graphics memory region.
>>
>> This patch adds a new function fbcon_modechange_possible() which
>> implements this check and which later may be extended with other checks
>> if necessary.  The new function is called from the FBIOPUT_VSCREENINFO
>> ioctl handler in fbmem.c, which will return -EINVAL if userspace asked
>> for a too small screen size.
>>
>> Signed-off-by: Helge Deller 
>> Reviewed-by: Daniel Vetter 
>> Cc: sta...@vger.kernel.org # v5.4+
>
> Thanks for your patch, which is now commit f0b6a66d33ca6e7e ("fbcon:
> Prevent that screen size is smaller than font size") in fbdev/for-next
>
>> --- a/drivers/video/fbdev/core/fbcon.c
>> +++ b/drivers/video/fbdev/core/fbcon.c
>
>> --- a/drivers/video/fbdev/core/fbmem.c
>> +++ b/drivers/video/fbdev/core/fbmem.c
>> @@ -1112,7 +1112,9 @@ static long do_fb_ioctl(struct fb_info *info, unsigned 
>> int cmd,
>> return -EFAULT;
>> console_lock();
>> lock_fb_info(info);
>> -   ret = fb_set_var(info, );
>> +   ret = fbcon_modechange_possible(info, );
>
> Again, this should be done (if done at all) after the call to
> fb_ops.check_var(), as it breaks the FBIOPUT_VSCREENINFO rounding rule.
>
> What if the user just wants to display graphics, not text?

Yes, I need to go back to an older version here too and check that
the test is only run on text consoles.
That check was dropped, due feedback that you could switch
back from graphics (e.g. X11) to text console at any timeso the
check for text-only is not correct.

> Can't the text console be disabled instead?

I think the solution is to return failure if switching back to text mode isn't 
possible if
fonts are bigger than the screen resolution. That will be another patch.

Thanks!

Helge


>
>> +   if (!ret)
>> +   ret = fb_set_var(info, );
>> if (!ret)
>> fbcon_update_vcs(info, var.activate & 
>> FB_ACTIVATE_ALL);
>> unlock_fb_info(info);
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH v6 2/4] fbmem: Prevent invalid virtual screen sizes

2022-06-28 Thread Helge Deller

Hi Geert,

On 6/28/22 10:36, Geert Uytterhoeven wrote:
> On Sun, Jun 26, 2022 at 12:32 PM Helge Deller  wrote:
>> Prevent that drivers or the user sets the virtual screen resolution
>> smaller than the physical screen resolution.  This is important, because
>> otherwise we may access memory outside of the graphics memory area.
>>
>> Signed-off-by: Helge Deller 
>> Reviewed-by: Daniel Vetter 
>> Cc: sta...@vger.kernel.org # v5.4+
>
> Thanks for your patch, which is now commit fe04405ce5de13a5 ("fbmem:
> Prevent invalid virtual screen sizes") in fbdev/for-next.
>
>> --- a/drivers/video/fbdev/core/fbmem.c
>> +++ b/drivers/video/fbdev/core/fbmem.c
>> @@ -1006,6 +1006,12 @@ fb_set_var(struct fb_info *info, struct 
>> fb_var_screeninfo *var)
>> if (var->xres < 8 || var->yres < 8)
>> return -EINVAL;
>>
>> +   /* make sure virtual resolution >= physical resolution */
>> +   if (var->xres_virtual < var->xres)
>> +   return -EINVAL;
>> +   if (var->yres_virtual < var->yres)
>> +   return -EINVAL;
>
> This breaks valid use cases (e.g. "fbset -xres ") ,
> as the FBIOPUT_VSCREENINFO rule is to round up invalid values,
> if possible.

You are right, fbset doesn't change the virtual screen size (unless the value
was given), so indeed we need to round up vres values in FBIOPUT_VSCREENINFO.

> Individual drivers may not follow that rule, so you could indeed end up
> with a virtual resolution here if such a driver fails to sanitize var.
> So either you have to move this after the call to fbops.fb_check_var()
> below, and/or change the code to enlarge virtual resolution to match
> physical resolution (at the risk of introducing another regression
> with an obscure driver?).
>
> So I'd go for moving it below.  And perhaps add a WARN(), as this
> is a driver bug?

That was exactly how I implemented in the first round, but changed it
due to feedback.
I'll respin the patch.

Thanks for reviewing that series!

Helge
>> /* Too huge resolution causes multiplication overflow. */
>> if (check_mul_overflow(var->xres, var->yres, ) ||
>> check_mul_overflow(var->xres_virtual, var->yres_virtual, 
>> ))
>
> Note that doing the multiplication overflow check before calling
> fbops.fb_check_var() is fine, as too large values can never be
> rounded up to a valid value.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH v5 5/9] drm/bridge: anx7625: Add typec_mux_set callback function

2022-06-28 Thread Stephen Boyd

Quoting Prashant Malani (2022-06-28 12:48:11)
> On Tue, Jun 28, 2022 at 12:25 PM Stephen Boyd  wrote:
> >
> > Quoting Prashant Malani (2022-06-22 10:34:34)
> > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
> > > b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > index bd21f159b973..5992fc8beeeb 100644
> > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
[..]
> > > +
> > > +   if (ctx->num_typec_switches == 1)
> >
> > How do we handle the case where the usb-c-connector is directly
> > connected to the RX1/TX1 and RX2/TX2 pins? This device would be an
> > orientation (normal/reverse) and mode switch (usb/dp) in that scenario,
> > but this code is written in a way that the orientation switch isn't
> > going to flip the crosspoint switch for the different pin assignments.
>
> If all 4 SS lanes are connected to 1 usb-c-connector; there would be
> just 1 "typec-switch" node.
> In that case, the DT would only specify it as an "orientation-switch"
> and register
> an orientation-switch with the Type-C framework. The orientation switch would
> pretty much do what the mode-switch callback does here (configuring
> the crosspoint
> switch).
> One could also register a "mode-switch" there but it wouldn't do
> anything (all 4 lanes are already
> connected so there is nothing to re-route in the crosspoint switch).
> Hence the above "if" check.

Would we still want to route the DP traffic out if the pin assignment
didn't have DP? Does the hardware support some mode where the DP traffic
is shutdown? Or maybe the HPD pin needs to be quieted unless DP is
assigned?

I suppose none of those things matter though as long as there is some
typec switch registered here so that the driver can be informed of the
pin assignment. Is it right that the "mode-switch" property is only
required in DT if this device is going to control the mode of the
connector, i.e. USB+DP, or just DP? Where this device can't do that
because it doesn't support only DP.

>
> Unfortunately, I don't have hardware which connects all 4 SS lanes
> from 1 Type-C port
> to the anx7625, so I didn't add the orientation switch handling to the
> driver (since I have no way of verifying it).

Alright. Maybe add a TODO then so it's more obvious that orientation
isn't handled.

>
> Regarding DP alt-mode pin assignments : I think anx7625 will only support Pin 
> D
> (only 2 lane DP, no 4 lane DP).
>

Makes sense. Thanks!

Re: [RFC PATCH 1/5] Documentation/amdgpu_dm: Add DM color correction documentation




On 2022-06-19 18:31, Melissa Wen wrote:
> AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
> to DC color correction entities. Part of this mapping is already
> documented as code comments and can be converted as kernel docs.
> 
> Signed-off-by: Melissa Wen 
> ---
>  .../gpu/amdgpu/display/display-manager.rst|   9 ++
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   2 +
>  .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 122 +-
>  3 files changed, 101 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst 
> b/Documentation/gpu/amdgpu/display/display-manager.rst
> index 7ce31f89d9a0..b1b0f11aed83 100644
> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> @@ -40,3 +40,12 @@ Atomic Implementation
>  
>  .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
> +
> +Color Management Properties
> +===
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +   :doc: overview
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +   :internal:
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index 3cc5c15303e6..8fd1be7f2583 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -242,6 +242,8 @@ struct hpd_rx_irq_offload_work {
>   * @force_timing_sync: set via debugfs. When set, indicates that all 
> connected
>   *  displays will be forced to synchronize.
>   * @dmcub_trace_event_en: enable dmcub trace events
> + * @num_of_edps: dumber of embedded Display Ports

/s/dumber/number

Thanks for turning these into kerneldocs. With the above minor nit fixed this is
Reviewed-by: Harry Wentland 

Harry

> + * @disable_hpd_irq: disable Hot Plug Detect handling
>   */
>  struct amdgpu_display_manager {
>  
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> index a71177305bcd..1f4a7c908587 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> @@ -29,7 +29,9 @@
>  #include "modules/color/color_gamma.h"
>  #include "basics/conversion.h"
>  
> -/*
> +/**
> + * DOC: overview
> + *
>   * The DC interface to HW gives us the following color management blocks
>   * per pipe (surface):
>   *
> @@ -71,8 +73,8 @@
>  
>  #define MAX_DRM_LUT_VALUE 0x
>  
> -/*
> - * Initialize the color module.
> +/**
> + * amdgpu_dm_init_color_mod - Initialize the color module.
>   *
>   * We're not using the full color module, only certain components.
>   * Only call setup functions for components that we need.
> @@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
>   setup_x_points_distribution();
>  }
>  
> -/* Extracts the DRM lut and lut size from a blob. */
> +/**
> + * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
> + * @blob: DRM color mgmt property blob
> + * @size: lut size
> + *
> + * Returns:
> + * DRM LUT or NULL
> + */
>  static const struct drm_color_lut *
>  __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
>  {
> @@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, 
> uint32_t *size)
>   return blob ? (struct drm_color_lut *)blob->data : NULL;
>  }
>  
> -/*
> - * Return true if the given lut is a linear mapping of values, i.e. it acts
> - * like a bypass LUT.
> +/**
> + * __is_lut_linear - check if the given lut is a linear mapping of values
> + * @lut: given lut to check values
> + * @size: lut size
>   *
>   * It is considered linear if the lut represents:
> - * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
> - *   [0, MAX_COLOR_LUT_ENTRIES)
> + * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
> + * MAX_COLOR_LUT_ENTRIES)
> + *
> + * Returns:
> + * True if the given lut is a linear mapping of values, i.e. it acts like a
> + * bypass LUT. Otherwise, false.
>   */
>  static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
>  {
> @@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut 
> *lut, uint32_t size)
>   return true;
>  }
>  
> -/*
> - * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
> - * of the lut - whether or not it's legacy.
> +/**
> + * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
> + * @lut: DRM lookup table for color conversion
> + * @gamma: DC gamma to set entries
> + * @is_legacy: legacy or atomic gamma
> + *
> + * The conversion depends on the size of the lut - whether or not it's 
> legacy.
>   */
>  static void

Re: [PATCH] drm/msm/dp: make eDP panel as the first connected connector

2022-06-28 Thread Dmitry Baryshkov




On 28 June 2022 18:20:06 GMT+03:00, Kuogee Hsieh  
wrote:
>Some userspace presumes that the first connected connector is the main
>display, where it's supposed to display e.g. the login screen. For
>laptops, this should be the main panel.
>
>This patch call drm_helper_move_panel_connectors_to_head() after
>drm_bridge_connector_init() to make sure eDP stay at head of
>connected connector list. This fixes unexpected corruption happen
>at eDP panel if eDP is not placed at head of connected connector
>list.

The change itself is a good fix anyway. (And I'd ack it.) However I would like 
to understand why does it fix the corruption issue. What is we have eDP and 
DSI, with DSI ending up before the eDP? Would we see the issue?
Also could you please describe the mind of corruption you are observing?


>
>Signed-off-by: Kuogee Hsieh 
>---
> drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
>index ce0ec3a..2d18884 100644
>--- a/drivers/gpu/drm/msm/dp/dp_drm.c
>+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
>@@ -136,5 +136,7 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp 
>*dp_display)
> 
>   drm_connector_attach_encoder(connector, dp_display->encoder);
> 
>+  drm_helper_move_panel_connectors_to_head(dp_display->drm_dev);
>+
>   return connector;
> }

Re: [PATCH v6 01/22] drm/gem: Properly annotate WW context on drm_gem_lock_reservations() error

2022-06-28 Thread Intel


Hi,

On 5/27/22 01:50, Dmitry Osipenko wrote:

Use ww_acquire_fini() in the error code paths. Otherwise lockdep
thinks that lock is held when lock's memory is freed after the
drm_gem_lock_reservations() error. The WW needs to be annotated
as "freed"


s /WW/ww_acquire_context/ ?
s /"freed"/"released"/ ?



, which fixes the noisy "WARNING: held lock freed!" splat
of VirtIO-GPU driver with CONFIG_DEBUG_MUTEXES=y and enabled lockdep.

Cc: sta...@vger.kernel.org


Can you dig up the commit in error and add a Fixes: Tag?

Using that and "dim fixes" will also make the Cc: stable tag a bit more 
verbose.


With that fixed,

Reviewed-by: Thomas Hellström 



Signed-off-by: Dmitry Osipenko 
---
  drivers/gpu/drm/drm_gem.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index eb0c2d041f13..86d670c71286 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1226,7 +1226,7 @@ drm_gem_lock_reservations(struct drm_gem_object **objs, 
int count,
ret = dma_resv_lock_slow_interruptible(obj->resv,
 acquire_ctx);
if (ret) {
-   ww_acquire_done(acquire_ctx);
+   ww_acquire_fini(acquire_ctx);
return ret;
}
}
@@ -1251,7 +1251,7 @@ drm_gem_lock_reservations(struct drm_gem_object **objs, 
int count,
goto retry;
}
  
-			ww_acquire_done(acquire_ctx);

+   ww_acquire_fini(acquire_ctx);
return ret;
}
}

Re: [RFC PATCH 0/5] DRM CRTC 3D LUT interface for AMD DCN

On 2022-06-19 18:30, Melissa Wen wrote:
> Hi,
> 
> I've been working on a proposal to add 3D LUT interface to DRM CRTC
> color mgmt, that means new **after-blending** properties for color
> correction. As I'm targeting AMD display drivers, I need to map these
> new properties to AMD DC interface and I have some doubts about the 3D
> LUT programming on DCN blocks.
> 
> First of all, this patchset is a working in progress and further
> discussions about the DRM interface should be done. I've examined
> previous proposal to add 3D LUT[1][2] and I understand that the main
> difference between them is regarding the property position in the DRM
> color management pipeline (between CTM and Gamma 1D or after Gamma 1D).
> On the other hand, AMD DC always considers a shaper (1D) LUT before a 3D
> LUT, used to delinearize and shape the content.  These LUTs are then
> positioned between DRM CTM and Gamma (1D).
> 
> By comparing the AMD design with the other proposals, I see that it's
> possible to cover all of them by adding and combining shaper (1D) LUT
> and 3D LUT as new color mgmt properties. Moreover, it'll not limit the
> exposure of AMD color correction caps to the userspace. Therefore, my
> proposal is to add these two new properties in the DRM color mgmt
> pipeline as follows:
> 
>  ++
>  ||
>  |  Degamma   |
>  +-+--+
>|
>  +-v--+
>  ||
>  |CTM |
>  +-+--+
>|
> ++-v--++
> ||||
> || Shaper LUT ||
> ++-+--++
>|
> ++-v--++
> ||||
> ||  3D LUT||
> ++-+--++
>|
>  +-v--+
>  ||
>  | Gamma (1D) |
>  ++
> 

As Ville already mentioned on patch 4, the increasing complexity of the
color pipeline and the arguments about the placement of the 3D LUT means
that we will probably need a definition of a particular HW's color
pipeline. Something like this proposal from Sebastian:
https://gitlab.freedesktop.org/pq/color-and-hdr/-/issues/11

> However, many doubts arose when I was mapping these two new properties
> to DC interface. This is why I decided to share an not-yet-completed
> implementation to get some feedback and explanation.
> 
> This RFC patchset is divided in three scopes of change. The first two
> patches document the AMD DM color correction mapping. Some comments were
> rewritten as kernel doc entries. I also summarize all information
> provided in previous discussions[3] and also redid those diagrams to
> svg. All doc should be reviewed and some struct members lack
> explanation. I can add them to documentation if you can provide a
> description. Some examples that lack description so far:
> * in amdgpu_display_manager: dmub_outbox_params, dmub_aux_transfer_done, 
> delayed_hpd_wq;
> * in dpp_color_caps: dgam_ram, dgam_rom_for_yuv;
> * in mpc_color_caps: ogam_ram.
> 
> The next two patches expand DRM color mgmt interface to add shaper LUT
> and 3D LUT. Finally, the last patch focuses on mapping DRM properties to
> DC interface and these are my doubts so far:
> 
> - To configure a shaper LUT, I related it to the current configuration
>   of gamma 1D. For dc_transfer_func, I should set tf according to the
>   input space, that means, LINEAR for shaper LUT after blending, right?
>   When 3D LUT is set, the input space for gamma 1D will no longer be
>   linear, so how to define the tf?  should I set tf as sRGB, BT709 or
>   what?
> 

We don't know the input space. It's nowhere defined in the KMS API. It
entirely depends on how a compositor renders the framebuffer (or transforms
it using some future KMS plane API).

DC interfaces are designed for a system where the driver is aware of the input
color space and linearity/non-linearity. This means that you'll often need
to dig through the API down to the HW programming bits to understand what
it actually does. A leaky abstraction, essentially.

Because KMS drivers don't know the linearity/non-linearity at any point
int the pipeline we need an API where the KMS client provides the
appropriate shaper LUT. In the case of any current KMS client that
will always be non-colormanaged and is assumed to be sRGB.

If your framebuffer is non-linear (sRGB) and you're not linearizing it
using the CRTC Degamma you'll already have non-linear values and won't
need to program the shaper LUT (i.e. use it in bypass or linear).

If your framebuffer is linear and you're not de-linearizing it with the
CRTC Degamma LUT you'll have linear values and need to program the
inverse EOTF for sRGB in your shaper (or degamma) LUT.

> - I see the 3dlut values being mapped to struct tetrahedral_17 as four
>   arrays lut0-4. From that I am considering tetrahedral interpolation.
>   Is there any other interpolation option? Also, as the total size of the
>   four arrays is the same of the 3D LUT size, I'm mapping DRM color lut
>   values in ascending order, starting by filling lut0 to lut4. Is it right
>   or is

Re: [PATCH v5 5/9] drm/bridge: anx7625: Add typec_mux_set callback function

2022-06-28 Thread Prashant Malani

On Tue, Jun 28, 2022 at 12:25 PM Stephen Boyd  wrote:
>
> Quoting Prashant Malani (2022-06-22 10:34:34)
> > From: Pin-Yen Lin 
> >
> > Add the callback function when the driver receives state
> > changes of the Type-C port. The callback function configures the
> > crosspoint switch of the anx7625 bridge chip, which can change the
> > output pins of the signals according to the port state.
>
> Can this be combined with the previous two patches? They really don't
> stand alone because the previous two patches are adding stubs that are
> filled out later.

I split it out for ease of reviewing, but sure, I will combine it if
there is a v6.

>
> > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
> > b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > index bd21f159b973..5992fc8beeeb 100644
> > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > @@ -15,6 +15,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >
> > @@ -2582,9 +2583,64 @@ static void anx7625_runtime_disable(void *data)
> > pm_runtime_disable(data);
> >  }
> >
> > +static void anx7625_set_crosspoint_switch(struct anx7625_data *ctx,
> > + enum typec_orientation 
> > orientation)
> > +{
> > +   if (orientation == TYPEC_ORIENTATION_NORMAL) {
> > +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
> > + SW_SEL1_SSRX_RX1 | SW_SEL1_DPTX0_RX2);
> > +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
> > + SW_SEL2_SSTX_TX1 | SW_SEL2_DPTX1_TX2);
> > +   } else if (orientation == TYPEC_ORIENTATION_REVERSE) {
> > +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
> > + SW_SEL1_SSRX_RX2 | SW_SEL1_DPTX0_RX1);
> > +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
> > + SW_SEL2_SSTX_TX2 | SW_SEL2_DPTX1_TX1);
> > +   }
> > +}
> > +
> > +static void anx7625_typec_two_ports_update(struct anx7625_data *ctx)
> > +{
> > +   if (ctx->typec_ports[0].dp_connected && 
> > ctx->typec_ports[1].dp_connected)
> > +   /* Both ports available, do nothing to retain the current 
> > one. */
> > +   return;
> > +   else if (ctx->typec_ports[0].dp_connected)
> > +   anx7625_set_crosspoint_switch(ctx, 
> > TYPEC_ORIENTATION_NORMAL);
> > +   else if (ctx->typec_ports[1].dp_connected)
> > +   anx7625_set_crosspoint_switch(ctx, 
> > TYPEC_ORIENTATION_REVERSE);
> > +}
> > +
> >  static int anx7625_typec_mux_set(struct typec_mux_dev *mux,
> >  struct typec_mux_state *state)
> >  {
> > +   struct anx7625_port_data *data = typec_mux_get_drvdata(mux);
> > +   struct anx7625_data *ctx = data->ctx;
> > +   struct device *dev = >client->dev;
> > +   bool new_dp_connected, old_dp_connected;
> > +
> > +   if (ctx->num_typec_switches == 1)
>
> How do we handle the case where the usb-c-connector is directly
> connected to the RX1/TX1 and RX2/TX2 pins? This device would be an
> orientation (normal/reverse) and mode switch (usb/dp) in that scenario,
> but this code is written in a way that the orientation switch isn't
> going to flip the crosspoint switch for the different pin assignments.

If all 4 SS lanes are connected to 1 usb-c-connector; there would be
just 1 "typec-switch" node.
In that case, the DT would only specify it as an "orientation-switch"
and register
an orientation-switch with the Type-C framework. The orientation switch would
pretty much do what the mode-switch callback does here (configuring
the crosspoint
switch).
One could also register a "mode-switch" there but it wouldn't do
anything (all 4 lanes are already
connected so there is nothing to re-route in the crosspoint switch).
Hence the above "if" check.

Unfortunately, I don't have hardware which connects all 4 SS lanes
from 1 Type-C port
to the anx7625, so I didn't add the orientation switch handling to the
driver (since I have no way of verifying it).

Regarding DP alt-mode pin assignments : I think anx7625 will only support Pin D
(only 2 lane DP, no 4 lane DP).

BR,

-Prashant

Re: [RFC PATCH 4/5] drm/drm_color_mgmt: add 3D LUT to color mgmt properties




On 2022-06-27 08:18, Ville Syrjälä wrote:
> On Sun, Jun 19, 2022 at 09:31:03PM -0100, Melissa Wen wrote:
>> Add 3D LUT for gammar correction using a 3D lookup table.  The position
>> in the color correction pipeline where 3D LUT is applied depends on hw
>> design, being after CTM or gamma. If just after CTM, a shaper lut must
>> be set to shape the content for a non-linear space. That details should
>> be handled by the driver according to its color capabilities.
> 
> I also cooked up a WIP 3D LUT support some time ago for Intel hw:
> https://github.com/vsyrjala/linux/commits/3dlut>> But that dried up due to 
> having no userspace for it.
> 
> I also cooked up some basic igts for it:
> https://patchwork.freedesktop.org/series/90165/>> 
> 
>> + * “LUT3D”:
>> + *  Blob property to set the 3D LUT mapping pixel data after the color
>> + *  transformation matrix and before gamma 1D lut correction.
> 
> On Intel hw the 3DLUT is after the gamma LUT in the pipeline, which is
> where I placed it in my branch.
> 
> There is now some discussion happening about exposing some
> kind of color pipeline description/configuration properties:
> https://gitlab.freedesktop.org/pq/color-and-hdr/-/issues/11>> 

After all the discussions about properties to support color management for
HDR and other features it's becoming clear to me that we'll need some color
pipeline description going forward, i.e. something like the one Sebastian
proposed. It's complex but if we're not defining this now we'll be in a pickle
when the next driver implementer goes and finds that their HW looks different
yet again and doesn't match any of the orders we've defined so far.

Harry

Re: [PATCH v5 5/9] drm/bridge: anx7625: Add typec_mux_set callback function

2022-06-28 Thread Stephen Boyd

Quoting Prashant Malani (2022-06-22 10:34:34)
> From: Pin-Yen Lin 
>
> Add the callback function when the driver receives state
> changes of the Type-C port. The callback function configures the
> crosspoint switch of the anx7625 bridge chip, which can change the
> output pins of the signals according to the port state.

Can this be combined with the previous two patches? They really don't
stand alone because the previous two patches are adding stubs that are
filled out later.

> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
> b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index bd21f159b973..5992fc8beeeb 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> @@ -2582,9 +2583,64 @@ static void anx7625_runtime_disable(void *data)
> pm_runtime_disable(data);
>  }
>
> +static void anx7625_set_crosspoint_switch(struct anx7625_data *ctx,
> + enum typec_orientation orientation)
> +{
> +   if (orientation == TYPEC_ORIENTATION_NORMAL) {
> +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
> + SW_SEL1_SSRX_RX1 | SW_SEL1_DPTX0_RX2);
> +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
> + SW_SEL2_SSTX_TX1 | SW_SEL2_DPTX1_TX2);
> +   } else if (orientation == TYPEC_ORIENTATION_REVERSE) {
> +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
> + SW_SEL1_SSRX_RX2 | SW_SEL1_DPTX0_RX1);
> +   anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
> + SW_SEL2_SSTX_TX2 | SW_SEL2_DPTX1_TX1);
> +   }
> +}
> +
> +static void anx7625_typec_two_ports_update(struct anx7625_data *ctx)
> +{
> +   if (ctx->typec_ports[0].dp_connected && 
> ctx->typec_ports[1].dp_connected)
> +   /* Both ports available, do nothing to retain the current 
> one. */
> +   return;
> +   else if (ctx->typec_ports[0].dp_connected)
> +   anx7625_set_crosspoint_switch(ctx, TYPEC_ORIENTATION_NORMAL);
> +   else if (ctx->typec_ports[1].dp_connected)
> +   anx7625_set_crosspoint_switch(ctx, TYPEC_ORIENTATION_REVERSE);
> +}
> +
>  static int anx7625_typec_mux_set(struct typec_mux_dev *mux,
>  struct typec_mux_state *state)
>  {
> +   struct anx7625_port_data *data = typec_mux_get_drvdata(mux);
> +   struct anx7625_data *ctx = data->ctx;
> +   struct device *dev = >client->dev;
> +   bool new_dp_connected, old_dp_connected;
> +
> +   if (ctx->num_typec_switches == 1)

How do we handle the case where the usb-c-connector is directly
connected to the RX1/TX1 and RX2/TX2 pins? This device would be an
orientation (normal/reverse) and mode switch (usb/dp) in that scenario,
but this code is written in a way that the orientation switch isn't
going to flip the crosspoint switch for the different pin assignments.

[PATCH] drm/i915/reset: Handle reset timeouts under unrelated kernel hangs

2022-06-28 Thread Ashutosh Dixit

From: Chris Wilson 

When resuming after hibernate sometimes we see hangs in unrelated kernel
subsystems. These hangs often result in the following i915 trace:

i915 :00:02.0: [drm] \
*ERROR* intel_gt_reset_global timed out, cancelling all in-flight 
rendering.

implying our reset task has been starved by the hanging kernel subsystem,
causing us to inappropiately declare the system as wedged beyond recovery.

The trace would be caused by our synchronize_srcu_expedited() taking more
than the allowed 5s due to the unrelated kernel hang. But we neither need
to perform that synchronisation inside the reset watchdog, nor do we need
such a short timeout before declaring the device as unrecoverable.

Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/3575
Signed-off-by: Chris Wilson 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index a5338c3fde7a0..e72744f6faedc 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1259,12 +1259,9 @@ static void intel_gt_reset_global(struct intel_gt *gt,
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
 
/* Use a watchdog to ensure that our reset completes */
-   intel_wedge_on_timeout(, gt, 5 * HZ) {
+   intel_wedge_on_timeout(, gt, 60 * HZ) {
intel_display_prepare_reset(gt->i915);
 
-   /* Flush everyone using a resource about to be clobbered */
-   synchronize_srcu_expedited(>reset.backoff_srcu);
-
intel_gt_reset(gt, engine_mask, reason);
 
intel_display_finish_reset(gt->i915);
@@ -1373,6 +1370,9 @@ void intel_gt_handle_error(struct intel_gt *gt,
}
}
 
+   /* Flush everyone using a resource about to be clobbered */
+   synchronize_srcu_expedited(>reset.backoff_srcu);
+
intel_gt_reset_global(gt, engine_mask, msg);
 
if (!intel_uc_uses_guc_submission(>uc)) {
-- 
2.36.1

[CI 2/2] iosys-map: Add per-word write

Like was done for read, provide the equivalent for write. Even if
current users are not in the hot path, this should future-proof it.

v2:
  - Remove default from _Generic() - callers wanting to write more
than u64 should use iosys_map_memcpy_to()
  - Add WRITE_ONCE() cases dereferencing the pointer when using system
memory
v3:
  - Fix precedence issue when casting inside WRITE_ONCE(). By not using ()
around vaddr__ the offset was not part of the cast, but rather added
to it, producing a wrong address
  - Remove compiletime_assert() as WRITE_ONCE() already contains it

Signed-off-by: Lucas De Marchi 
Reviewed-by: Reviewed-by: Christian König  # v1
Reviewed-by: Thomas Zimmermann 
---
 include/linux/iosys-map.h | 38 +-
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 48e550b290fa..08dad5b0ad17 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -337,9 +337,13 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
 #ifdef CONFIG_64BIT
 #define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
u64: val_ = readq(vaddr_iomem_)
+#define __iosys_map_wr_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: writeq(val_, vaddr_iomem_)
 #else
 #define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
u64: memcpy_fromio(&(val_), vaddr_iomem_, sizeof(u64))
+#define __iosys_map_wr_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: memcpy_toio(vaddr_iomem_, &(val_), sizeof(u64))
 #endif
 
 #define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
@@ -351,6 +355,15 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
 #define __iosys_map_rd_sys(val__, vaddr__, type__) 
\
val__ = READ_ONCE(*(type__ *)(vaddr__));
 
+#define __iosys_map_wr_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: writeb(val__, vaddr_iomem__),   
\
+   u16: writew(val__, vaddr_iomem__),  
\
+   u32: writel(val__, vaddr_iomem__),  
\
+   __iosys_map_wr_io_u64_case(val__, vaddr_iomem__))
+
+#define __iosys_map_wr_sys(val__, vaddr__, type__) 
\
+   WRITE_ONCE(*(type__ *)(vaddr__), val__);
+
 /**
  * iosys_map_rd - Read a C-type value from the iosys_map
  *
@@ -383,12 +396,17 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @type__:Type of the value being written
  * @val__: Value to write
  *
- * Write a C-type value to the iosys_map, handling possible un-aligned accesses
- * to the mapping.
+ * Write a C type value (u8, u16, u32 and u64) to the iosys_map. For other 
types
+ * or if pointer may be unaligned (and problematic for the architecture
+ * supported), use iosys_map_memcpy_to()
  */
-#define iosys_map_wr(map__, offset__, type__, val__) ({
\
-   type__ val = (val__);   \
-   iosys_map_memcpy_to(map__, offset__, , sizeof(val));\
+#define iosys_map_wr(map__, offset__, type__, val__) ({
\
+   type__ val = (val__);   
\
+   if ((map__)->is_iomem) {
\
+   __iosys_map_wr_io(val, (map__)->vaddr_iomem + (offset__), 
type__);\
+   } else {
\
+   __iosys_map_wr_sys(val, (map__)->vaddr + (offset__), type__);   
\
+   }   
\
 })
 
 /**
@@ -469,10 +487,12 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @field__:   Member of the struct to read
  * @val__: Value to write
  *
- * Write a value to the iosys_map considering its layout is described by a C 
struct
- * starting at @struct_offset__. The field offset and size is calculated and 
the
- * @val__ is written handling possible un-aligned memory accesses. Refer to
- * iosys_map_rd_field() for expected usage and memory layout.
+ * Write a value to the iosys_map considering its layout is described by a C
+ * struct starting at @struct_offset__. The field offset and size is calculated
+ * and the @val__ is written. If the field access would incur in un-aligned
+ * access, then either iosys_map_memcpy_to() needs to be used or the
+ * architecture must support it. Refer to iosys_map_rd_field() for expected
+ * usage and memory layout.
  */
 #define iosys_map_wr_field(map__, struct_offset__, struct_type__, field__, 
val__) ({   \
struct_type__ *s;

[CI 1/2] iosys-map: Add per-word read

Instead of always falling back to memcpy_fromio() for any size, prefer
using read{b,w,l}(). When reading struct members it's common to read
individual integer variables individually. Going through memcpy_fromio()
for each of them poses a high penalty.

Employ a similar trick as __seqprop() by using _Generic() to generate
only the specific call based on a type-compatible variable.

For a pariticular i915 workload producing GPU context switches,
__get_engine_usage_record() is particularly hot since the engine usage
is read from device local memory with dgfx, possibly multiple times
since it's racy. Test execution time for this test shows a ~12.5%
improvement with DG2:

Before:
nrepeats = 1000; min = 7.63243e+06; max = 1.01817e+07;
median = 9.52548e+06; var = 526149;
After:
nrepeats = 1000; min = 7.03402e+06; max = 8.8832e+06;
median = 8.33955e+06; var = 333113;

Other things attempted that didn't prove very useful:
1) Change the _Generic() on x86 to just dereference the memory address
2) Change __get_engine_usage_record() to do just 1 read per loop,
   comparing with the previous value read
3) Change __get_engine_usage_record() to access the fields directly as it
   was before the conversion to iosys-map

(3) did gave a small improvement (~3%), but doesn't seem to scale well
to other similar cases in the driver.

Additional test by Chris Wilson using gem_create from igt with some
changes to track object creation time. This happens to accidentally
stress this code path:

Pre iosys_map conversion of engine busyness:
lmem0: Creating262144 4KiB objects took 59274.2ms

Unpatched:
lmem0: Creating262144 4KiB objects took 108830.2ms

With readl (this patch):
lmem0: Creating262144 4KiB objects took 61348.6ms

s/readl/READ_ONCE/
lmem0: Creating262144 4KiB objects took 61333.2ms

So we do take a little bit more time than before the conversion, but
that is due to other factors: bringing the READ_ONCE back would be as
good as just doing this conversion.

v2:
  - Remove default from _Generic() - callers wanting to read more
than u64 should use iosys_map_memcpy_from()
  - Add READ_ONCE() cases dereferencing the pointer when using system
memory
v3:
  - Fix precedence issue when casting inside READ_ONCE(). By not using ()
around vaddr__ the offset was not part of the cast, but rather added
to it, producing a wrong address
  - Remove compiletime_assert() as READ_ONCE() already contains it

Signed-off-by: Lucas De Marchi 
Reviewed-by: Christian König  # v1
Reviewed-by: Thomas Zimmermann 
---
 include/linux/iosys-map.h | 42 ++-
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 4b8406ee8bc4..48e550b290fa 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -6,6 +6,7 @@
 #ifndef __IOSYS_MAP_H__
 #define __IOSYS_MAP_H__
 
+#include 
 #include 
 #include 
 
@@ -333,6 +334,23 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
memset(dst->vaddr + offset, value, len);
 }
 
+#ifdef CONFIG_64BIT
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: val_ = readq(vaddr_iomem_)
+#else
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: memcpy_fromio(&(val_), vaddr_iomem_, sizeof(u64))
+#endif
+
+#define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: val__ = readb(vaddr_iomem__),   
\
+   u16: val__ = readw(vaddr_iomem__),  
\
+   u32: val__ = readl(vaddr_iomem__),  
\
+   __iosys_map_rd_io_u64_case(val__, vaddr_iomem__))
+
+#define __iosys_map_rd_sys(val__, vaddr__, type__) 
\
+   val__ = READ_ONCE(*(type__ *)(vaddr__));
+
 /**
  * iosys_map_rd - Read a C-type value from the iosys_map
  *
@@ -340,16 +358,21 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @offset__:  The offset from which to read
  * @type__:Type of the value being read
  *
- * Read a C type value from iosys_map, handling possible un-aligned accesses to
- * the mapping.
+ * Read a C type value (u8, u16, u32 and u64) from iosys_map. For other types 
or
+ * if pointer may be unaligned (and problematic for the architecture 
supported),
+ * use iosys_map_memcpy_from().
  *
  * Returns:
  * The value read from the mapping.
  */
-#define iosys_map_rd(map__, offset__, type__) ({   \
-   type__ val; \
-   iosys_map_memcpy_from(, map__, offset__, sizeof(val));  \
-   val;\
+#define iosys_map_rd(map__, offset__, type__) ({

Re: [CI 1/3] drm-tip: 2022y-06m-27d-16h-18m-47s UTC integration manifest


On Tue, Jun 28, 2022 at 11:47:45AM -0700, Lucas De Marchi wrote:

From: Ville Syrjälä 


Sorry for the noise.

This should NOT be the patch 1, of course. It went here beacuse my local
and remote branch were out of sync (and drm-tip/drm-tip.. then includes
it)

This is intended for CI, but it will fail to apply. I will re-submit
this.

Lucas De Marchi

Re: [PATCH 0/4] KUnit tests for RGB565 conversion

2022-06-28 Thread Tales

Em seg., 27 de jun. de 2022 às 13:13, José Expósito
 escreveu:
>
> Hello everyone,
>
> This series is a follow up of the XRGB to RGB332 conversion KUnit tests.
>
> The first 3 patches refactor the existing test to make them agnostic of the 
> target format and add support for "swab".
>
> The last patch adds the RGB565 conversion values, and shows how more formats 
> will be easily added in the future.
>
> Thank you very much in advance for your feedback,
> José Expósito
>
> José Expósito (4):
>   drm/format-helper: Rename test cases to make them more generic
>   drm/format-helper: Transform tests to be agnostic of target format
>   drm/format-helper: Add support for conversion functions with swab
>   drm/format-helper: Add KUnit tests for drm_fb_xrgb_to_rgb565()
>
>  .../gpu/drm/tests/drm_format_helper_test.c| 231 +++---
>  1 file changed, 196 insertions(+), 35 deletions(-)
>
>
> base-commit: 6fde8eec71796f3534f0c274066862829813b21f
> prerequisite-patch-id: 8a16f4c8004d6161035eaea275c8eafaa0ac927e
> prerequisite-patch-id: 53fded2a49e6212b546db76ec52563a683752e65
> prerequisite-patch-id: 294b0ca27a6ee57096c8f097c0572336b8a2d583
> prerequisite-patch-id: 5e05bfc5287d16c207bfc616b2776ad72eb4ab29
> prerequisite-patch-id: e94560be85dffb62a5b3cf58d1f0fc3d278ad806
> prerequisite-patch-id: a471df39c7b32c69dd2b138a7d0af015ea42e00a
> --
> 2.25.1


Tested with "./tools/testing/kunit/kunit.py run
--kunitconfig=drivers/gpu/drm/tests --arch=x86_64", "... --arch=i386"
and baremetal on x86_64 to be sure; everything looks fine, but I feel
like some patches could be squashed, though.

Tested-by: Tales L. Aparecida 

Inspiring work, José, keep it up!
Best regards, Tales

[CI 2/3] iosys-map: Add per-word read

Instead of always falling back to memcpy_fromio() for any size, prefer
using read{b,w,l}(). When reading struct members it's common to read
individual integer variables individually. Going through memcpy_fromio()
for each of them poses a high penalty.

Employ a similar trick as __seqprop() by using _Generic() to generate
only the specific call based on a type-compatible variable.

For a pariticular i915 workload producing GPU context switches,
__get_engine_usage_record() is particularly hot since the engine usage
is read from device local memory with dgfx, possibly multiple times
since it's racy. Test execution time for this test shows a ~12.5%
improvement with DG2:

Before:
nrepeats = 1000; min = 7.63243e+06; max = 1.01817e+07;
median = 9.52548e+06; var = 526149;
After:
nrepeats = 1000; min = 7.03402e+06; max = 8.8832e+06;
median = 8.33955e+06; var = 333113;

Other things attempted that didn't prove very useful:
1) Change the _Generic() on x86 to just dereference the memory address
2) Change __get_engine_usage_record() to do just 1 read per loop,
   comparing with the previous value read
3) Change __get_engine_usage_record() to access the fields directly as it
   was before the conversion to iosys-map

(3) did gave a small improvement (~3%), but doesn't seem to scale well
to other similar cases in the driver.

Additional test by Chris Wilson using gem_create from igt with some
changes to track object creation time. This happens to accidentally
stress this code path:

Pre iosys_map conversion of engine busyness:
lmem0: Creating262144 4KiB objects took 59274.2ms

Unpatched:
lmem0: Creating262144 4KiB objects took 108830.2ms

With readl (this patch):
lmem0: Creating262144 4KiB objects took 61348.6ms

s/readl/READ_ONCE/
lmem0: Creating262144 4KiB objects took 61333.2ms

So we do take a little bit more time than before the conversion, but
that is due to other factors: bringing the READ_ONCE back would be as
good as just doing this conversion.

v2:
  - Remove default from _Generic() - callers wanting to read more
than u64 should use iosys_map_memcpy_from()
  - Add READ_ONCE() cases dereferencing the pointer when using system
memory
v3:
  - Fix precedence issue when casting inside READ_ONCE(). By not using ()
around vaddr__ the offset was not part of the cast, but rather added
to it, producing a wrong address
  - Remove compiletime_assert() as READ_ONCE() already contains it

Signed-off-by: Lucas De Marchi 
Reviewed-by: Christian König  # v1
Reviewed-by: Thomas Zimmermann 
---
 include/linux/iosys-map.h | 42 ++-
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 4b8406ee8bc4..48e550b290fa 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -6,6 +6,7 @@
 #ifndef __IOSYS_MAP_H__
 #define __IOSYS_MAP_H__
 
+#include 
 #include 
 #include 
 
@@ -333,6 +334,23 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
memset(dst->vaddr + offset, value, len);
 }
 
+#ifdef CONFIG_64BIT
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: val_ = readq(vaddr_iomem_)
+#else
+#define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: memcpy_fromio(&(val_), vaddr_iomem_, sizeof(u64))
+#endif
+
+#define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: val__ = readb(vaddr_iomem__),   
\
+   u16: val__ = readw(vaddr_iomem__),  
\
+   u32: val__ = readl(vaddr_iomem__),  
\
+   __iosys_map_rd_io_u64_case(val__, vaddr_iomem__))
+
+#define __iosys_map_rd_sys(val__, vaddr__, type__) 
\
+   val__ = READ_ONCE(*(type__ *)(vaddr__));
+
 /**
  * iosys_map_rd - Read a C-type value from the iosys_map
  *
@@ -340,16 +358,21 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @offset__:  The offset from which to read
  * @type__:Type of the value being read
  *
- * Read a C type value from iosys_map, handling possible un-aligned accesses to
- * the mapping.
+ * Read a C type value (u8, u16, u32 and u64) from iosys_map. For other types 
or
+ * if pointer may be unaligned (and problematic for the architecture 
supported),
+ * use iosys_map_memcpy_from().
  *
  * Returns:
  * The value read from the mapping.
  */
-#define iosys_map_rd(map__, offset__, type__) ({   \
-   type__ val; \
-   iosys_map_memcpy_from(, map__, offset__, sizeof(val));  \
-   val;\
+#define iosys_map_rd(map__, offset__, type__) ({

[CI 3/3] iosys-map: Add per-word write

Like was done for read, provide the equivalent for write. Even if
current users are not in the hot path, this should future-proof it.

v2:
  - Remove default from _Generic() - callers wanting to write more
than u64 should use iosys_map_memcpy_to()
  - Add WRITE_ONCE() cases dereferencing the pointer when using system
memory
v3:
  - Fix precedence issue when casting inside WRITE_ONCE(). By not using ()
around vaddr__ the offset was not part of the cast, but rather added
to it, producing a wrong address
  - Remove compiletime_assert() as WRITE_ONCE() already contains it

Signed-off-by: Lucas De Marchi 
Reviewed-by: Reviewed-by: Christian König  # v1
Reviewed-by: Thomas Zimmermann 
---
 include/linux/iosys-map.h | 38 +-
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 48e550b290fa..08dad5b0ad17 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -337,9 +337,13 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
 #ifdef CONFIG_64BIT
 #define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
u64: val_ = readq(vaddr_iomem_)
+#define __iosys_map_wr_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: writeq(val_, vaddr_iomem_)
 #else
 #define __iosys_map_rd_io_u64_case(val_, vaddr_iomem_) 
\
u64: memcpy_fromio(&(val_), vaddr_iomem_, sizeof(u64))
+#define __iosys_map_wr_io_u64_case(val_, vaddr_iomem_) 
\
+   u64: memcpy_toio(vaddr_iomem_, &(val_), sizeof(u64))
 #endif
 
 #define __iosys_map_rd_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
@@ -351,6 +355,15 @@ static inline void iosys_map_memset(struct iosys_map *dst, 
size_t offset,
 #define __iosys_map_rd_sys(val__, vaddr__, type__) 
\
val__ = READ_ONCE(*(type__ *)(vaddr__));
 
+#define __iosys_map_wr_io(val__, vaddr_iomem__, type__) _Generic(val__,
\
+   u8: writeb(val__, vaddr_iomem__),   
\
+   u16: writew(val__, vaddr_iomem__),  
\
+   u32: writel(val__, vaddr_iomem__),  
\
+   __iosys_map_wr_io_u64_case(val__, vaddr_iomem__))
+
+#define __iosys_map_wr_sys(val__, vaddr__, type__) 
\
+   WRITE_ONCE(*(type__ *)(vaddr__), val__);
+
 /**
  * iosys_map_rd - Read a C-type value from the iosys_map
  *
@@ -383,12 +396,17 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @type__:Type of the value being written
  * @val__: Value to write
  *
- * Write a C-type value to the iosys_map, handling possible un-aligned accesses
- * to the mapping.
+ * Write a C type value (u8, u16, u32 and u64) to the iosys_map. For other 
types
+ * or if pointer may be unaligned (and problematic for the architecture
+ * supported), use iosys_map_memcpy_to()
  */
-#define iosys_map_wr(map__, offset__, type__, val__) ({
\
-   type__ val = (val__);   \
-   iosys_map_memcpy_to(map__, offset__, , sizeof(val));\
+#define iosys_map_wr(map__, offset__, type__, val__) ({
\
+   type__ val = (val__);   
\
+   if ((map__)->is_iomem) {
\
+   __iosys_map_wr_io(val, (map__)->vaddr_iomem + (offset__), 
type__);\
+   } else {
\
+   __iosys_map_wr_sys(val, (map__)->vaddr + (offset__), type__);   
\
+   }   
\
 })
 
 /**
@@ -469,10 +487,12 @@ static inline void iosys_map_memset(struct iosys_map 
*dst, size_t offset,
  * @field__:   Member of the struct to read
  * @val__: Value to write
  *
- * Write a value to the iosys_map considering its layout is described by a C 
struct
- * starting at @struct_offset__. The field offset and size is calculated and 
the
- * @val__ is written handling possible un-aligned memory accesses. Refer to
- * iosys_map_rd_field() for expected usage and memory layout.
+ * Write a value to the iosys_map considering its layout is described by a C
+ * struct starting at @struct_offset__. The field offset and size is calculated
+ * and the @val__ is written. If the field access would incur in un-aligned
+ * access, then either iosys_map_memcpy_to() needs to be used or the
+ * architecture must support it. Refer to iosys_map_rd_field() for expected
+ * usage and memory layout.
  */
 #define iosys_map_wr_field(map__, struct_offset__, struct_type__, field__, 
val__) ({   \
struct_type__ *s;

[CI 1/3] drm-tip: 2022y-06m-27d-16h-18m-47s UTC integration manifest

From: Ville Syrjälä 

---
 integration-manifest | 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 integration-manifest

diff --git a/integration-manifest b/integration-manifest
new file mode 100644
index ..baffa2a57cd4
--- /dev/null
+++ b/integration-manifest
@@ -0,0 +1,26 @@
+drm drm-fixes 03c765b0e3b4cb5063276b086c76f7a612856a9a
+   Linux 5.19-rc4
+drm-misc drm-misc-fixes 5f701324c0fb6f9f5aaac3f8d1575321375f6d8f
+   drm/vc4: perfmon: Fix variable dereferenced before check
+drm-intel drm-intel-fixes 79538490fd7ade244dba400923e792519a2bdfea
+   drm/i915: tweak the ordering in cpu_write_needs_clflush
+drm drm-next 805ada63ba0567b15d10d40419bcc5e6f0b461e6
+   Merge tag 'drm-intel-next-2022-06-22' of 
git://anongit.freedesktop.org/drm/drm-intel into drm-next
+drm-misc drm-misc-next-fixes 5ee8c8f930ba7d20717c4fc2d9f1ce0e757d1155
+   drm/rockchip: Change register space names in vop2
+drm-intel drm-intel-next-fixes f2906aa863381afb0015a9eb7fefad885d4e5a56
+   Linux 5.19-rc1
+drm-misc drm-misc-next 7d008eecb0cfc2b1a1a742d6faa0a02f339535c2
+   drm/stm: ltdc: update hardware error management
+drm-intel drm-intel-next f7fb92cd2e39357f14846d69ae0e1d8692371f82
+   drm/i915: Move the color stuff under INTEL_INFO->display
+drm-intel drm-intel-gt-next 7d8097073caa334ed6187a964645335324231e01
+   drm/i915: Prefer "XEHP_" prefix for registers
+sound-upstream for-linus 7cf3dead1ad70c72edb03e2d98e1f3dcd332cdb2
+   Linux 5.13
+sound-upstream for-next 7cf3dead1ad70c72edb03e2d98e1f3dcd332cdb2
+   Linux 5.13
+drm-intel topic/core-for-CI f7d7dddaab81eeae4508197b5f38f0b974d97b8c
+   topic/core-for-CI: Add remaining DG2 and ATS-M device IDs
+drm-misc topic/i915-ttm 1e3944578b749449bd7fa6bf0bae4c3d3f5f1733
+   Merge tag 'amd-drm-next-5.16-2021-09-27' of 
https://gitlab.freedesktop.org/agd5f/linux into drm-next
-- 
2.36.1

Re: [PATCH][next] treewide: uapi: Replace zero-length arrays with flexible-array members

2022-06-28 Thread Jason Gunthorpe

On Tue, Jun 28, 2022 at 10:54:58AM -0700, Kees Cook wrote:

> which must also be assuming it's a header. So probably better to just
> drop the driver_data field? I don't see anything using it (that I can
> find) besides as a sanity-check that the field exists and is at the end
> of the struct.

The field is guaranteeing alignment of the following structure. IIRC
there are a few cases that we don't have a u64 already to force this.

Jason

Re: [PATCH v5 1/9] dt-bindings: usb: Add Type-C switch binding

2022-06-28 Thread Rob Herring

On Mon, Jun 27, 2022 at 02:43:39PM -0700, Prashant Malani wrote:
> Hello Rob,
> 
> On Mon, Jun 27, 2022 at 2:04 PM Rob Herring  wrote:
> >
> > On Wed, Jun 22, 2022 at 05:34:30PM +, Prashant Malani wrote:
> > > Introduce a binding which represents a component that can control the
> > > routing of USB Type-C data lines as well as address data line
> > > orientation (based on CC lines' orientation).
> > >
> > > Reviewed-by: Krzysztof Kozlowski 
> > > Reviewed-by: AngeloGioacchino Del Regno 
> > > 
> > > Reviewed-by: Nícolas F. R. A. Prado 
> > > Tested-by: Nícolas F. R. A. Prado 
> > > Signed-off-by: Prashant Malani 
> > > ---
> > >
> > > Changes since v4:
> > > - Added Reviewed-by tags.
> > > - Patch moved to 1/9 position (since Patch v4 1/7 and 2/7 were
> > >   applied to usb-next)
> > >
> > > Changes since v3:
> > > - No changes.
> > >
> > > Changes since v2:
> > > - Added Reviewed-by and Tested-by tags.
> > >
> > > Changes since v1:
> > > - Removed "items" from compatible.
> > > - Fixed indentation in example.
> > >
> > >  .../devicetree/bindings/usb/typec-switch.yaml | 74 +++
> > >  1 file changed, 74 insertions(+)
> > >  create mode 100644 
> > > Documentation/devicetree/bindings/usb/typec-switch.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/typec-switch.yaml 
> > > b/Documentation/devicetree/bindings/usb/typec-switch.yaml
> > > new file mode 100644
> > > index ..78b0190c8543
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/typec-switch.yaml
> > > @@ -0,0 +1,74 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/usb/typec-switch.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: USB Type-C Switch
> > > +
> > > +maintainers:
> > > +  - Prashant Malani 
> > > +
> > > +description:
> > > +  A USB Type-C switch represents a component which routes USB Type-C data
> > > +  lines to various protocol host controllers (e.g USB, VESA DisplayPort,
> > > +  Thunderbolt etc.) depending on which mode the Type-C port, port partner
> > > +  and cable are operating in. It can also modify lane routing based on
> > > +  the orientation of a connected Type-C peripheral.
> > > +
> > > +properties:
> > > +  compatible:
> > > +const: typec-switch
> > > +
> > > +  mode-switch:
> > > +type: boolean
> > > +description: Specify that this switch can handle alternate mode 
> > > switching.
> > > +
> > > +  orientation-switch:
> > > +type: boolean
> > > +description: Specify that this switch can handle orientation 
> > > switching.
> > > +
> > > +  ports:
> > > +$ref: /schemas/graph.yaml#/properties/ports
> > > +description: OF graph binding modelling data lines to the Type-C 
> > > switch.
> > > +
> > > +properties:
> > > +  port@0:
> > > +$ref: /schemas/graph.yaml#/properties/port
> > > +description: Link between the switch and a Type-C connector.
> > > +
> > > +required:
> > > +  - port@0
> > > +
> > > +required:
> > > +  - compatible
> > > +  - ports
> > > +
> > > +anyOf:
> > > +  - required:
> > > +  - mode-switch
> > > +  - required:
> > > +  - orientation-switch
> > > +
> > > +additionalProperties: true
> > > +
> > > +examples:
> > > +  - |
> > > +drm-bridge {
> > > +usb-switch {
> > > +compatible = "typec-switch";
> >
> > Unless this child is supposed to represent what the parent output is
> > connected to, this is just wrong as, at least for the it6505 chip, it
> > doesn't know anything about Type-C functionality. The bridge is
> > just a protocol converter AFAICT.
> 
> I'll let Pin-Yen comment on the specifics of the it6505 chip.

We're all waiting...

> > If the child node represents what the output is connected to (like a
> > bus), then yes that is a pattern we have used.
> 
> For the anx7625 case, the child node does represent what the output is 
> connected
> to (the usb-c-connector via the switch). Does that not qualify? Or do you mean
> the child node should be a usb-c-connector itself?
> 
> > For example, a panel
> > represented as child node of a display controller. However, that only
> > works for simple cases, and is a pattern we have gotten away from in
> > favor of using the graph binding.
> 
> The child node will still use a OF graph binding to connect to the
> usb-c-connector.
> Is that insufficient to consider a child node usage here?
> By "using the graph binding", do you mean "only use the top-level ports" ?
> I'm trying to clarify this, so that it will inform future versions and 
> patches.

What I want to see is block diagrams of possible h/w with different 
scenarios and then what the binding looks like in those cases. The 
switching/muxing could be in the SoC, a bridge chip, a Type C 
controller, a standalone mux chip, or . If you want a somewhat 
genericish binding, then you need to consider all of these.

I

[PATCH v3 4/4] drm/panel: simple: add bus-format support for panel-dpi

From: Max Krummenacher 

Evaluate the device tree bus-format property to set bus_format for
a 'panel-dpi' panel. Additionally infer the bpc value from the
given bus-format.

Valid values for bus-format are found in:


This completes the addition of panel-dpi to completely specify
a panel-simple panel from the device tree.

Signed-off-by: Max Krummenacher 

---

Changes in v3:
- Moved the bus-format property under the port/endpoint node as
  suggested by Rob Herring

Changes in v2:
- Fix errors found by dt_binding_check

 drivers/gpu/drm/panel/panel-simple.c | 49 
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 4a2e580a2f7b..f1a457f1069e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -21,9 +21,11 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -449,10 +451,12 @@ static int panel_dpi_probe(struct device *dev,
   struct panel_simple *panel)
 {
struct display_timing *timing;
+   struct device_node *endpoint;
const struct device_node *np;
struct panel_desc *desc;
unsigned int bus_flags;
struct videomode vm;
+   u32 bus_format;
int ret;
 
np = dev->of_node;
@@ -477,6 +481,51 @@ static int panel_dpi_probe(struct device *dev,
of_property_read_u32(np, "width-mm", >size.width);
of_property_read_u32(np, "height-mm", >size.height);
 
+   endpoint = of_graph_get_endpoint_by_regs(np, -1, -1);
+   if (endpoint &&
+   !of_property_read_u32(endpoint, "bus-format", _format)) {
+   /* infer bpc from bus-format */
+   switch (bus_format) {
+   case DT_MEDIA_BUS_FMT_RGB565_1X16:
+   desc->bus_format = MEDIA_BUS_FMT_RGB565_1X16;
+   desc->bpc = 6;
+   break;
+   case DT_MEDIA_BUS_FMT_RGB666_1X18:
+   desc->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
+   desc->bpc = 6;
+   break;
+   case DT_MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+   desc->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
+   desc->bpc = 6;
+   break;
+   case DT_MEDIA_BUS_FMT_BGR888_1X24:
+   desc->bus_format = MEDIA_BUS_FMT_BGR888_1X24;
+   desc->bpc = 8;
+   break;
+   case DT_MEDIA_BUS_FMT_GBR888_1X24:
+   desc->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
+   desc->bpc = 8;
+   break;
+   case DT_MEDIA_BUS_FMT_RBG888_1X24:
+   desc->bus_format = MEDIA_BUS_FMT_RBG888_1X24;
+   desc->bpc = 8;
+   break;
+   case DT_MEDIA_BUS_FMT_RGB888_1X24:
+   desc->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+   desc->bpc = 8;
+   break;
+   case DT_MEDIA_BUS_FMT_RGB888_1X32_PADHI:
+   desc->bus_format = MEDIA_BUS_FMT_RGB888_1X32_PADHI;
+   desc->bpc = 8;
+   break;
+   default:
+   dev_err(dev, "%pOF: unknown bus-format property\n", np);
+   return -EINVAL;
+   }
+   }
+
+   of_node_put(endpoint);
+
/* Extract bus_flags from display_timing */
bus_flags = 0;
vm.flags = timing->flags;
-- 
2.20.1

[PATCH v3 2/4] dt-bindings: display: add new bus-format property for panel-dpi

From: Max Krummenacher 

The property is used to set the enum bus_format and infer the bpc
for a panel defined by 'panel-dpi'.
This specifies how the panel is connected to the display interface.

Signed-off-by: Max Krummenacher 

---

Changes in v3:
- Changed the V4L number space as suggested by Rob Herring
- Set constraints for bus-format as suggested by Rob Herring, used
  the range reserved for RGB formats.
- Editorial changes as suggested by Rob Herring
- Moved the bus-format property under the port/endpoint node as
  suggested by Rob Herring

Changes in v2:
- Fix errors found by dt_binding_check

 .../bindings/display/panel/panel-dpi.yaml | 26 ++-
 .../dt-bindings/display/dt-media-bus-format.h | 23 
 2 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/display/dt-media-bus-format.h

diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml 
b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
index dae0676b5c6e..52f5db03b6a8 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.yaml
@@ -26,7 +26,28 @@ properties:
   height-mm: true
   label: true
   panel-timing: true
-  port: true
+
+  port:
+$ref: /schemas/graph.yaml#/$defs/port-base
+description:
+  Input port node, receives the panel data.
+
+properties:
+  endpoint:
+$ref: /schemas/graph.yaml#/$defs/endpoint-base
+
+properties:
+  bus-format:
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0x1001
+maximum: 0x1fff
+description: |
+  Describes how the display panel is connected to the display 
interface.
+  Valid values are defined in 
.
+  The mapping between the color/significance of the panel lines to 
the
+  parallel data lines are defined in:
+  
https://www.kernel.org/doc/html/v5.17/userspace-api/media/v4l/subdev-formats.html#packed-rgb-formats
+
   power-supply: true
   reset-gpios: true
   width-mm: true
@@ -39,6 +60,8 @@ additionalProperties: false
 
 examples:
   - |
+#include 
+
 panel {
 compatible = "startek,startek-kd050c", "panel-dpi";
 label = "osddisplay";
@@ -47,6 +70,7 @@ examples:
 
 port {
 lcd_in: endpoint {
+bus-format = ;
 remote-endpoint = <_out>;
 };
 };
diff --git a/include/dt-bindings/display/dt-media-bus-format.h 
b/include/dt-bindings/display/dt-media-bus-format.h
new file mode 100644
index ..a032d9724ed4
--- /dev/null
+++ b/include/dt-bindings/display/dt-media-bus-format.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2022 Max Krummenacher 
+ */
+
+#ifndef __DT_BINDINGS_DT_MEDIA_BUS_FORMAT_H
+#define __DT_BINDINGS_DT_MEDIA_BUS_FORMAT_H
+
+/*
+ * Attention: Keep these macro names in sync with
+ * include/uapi/linux/media-bus-format.h
+ */
+
+#define DT_MEDIA_BUS_FMT_RGB565_1X16   0x1017
+#define DT_MEDIA_BUS_FMT_RGB666_1X18   0x1009
+#define DT_MEDIA_BUS_FMT_RBG888_1X24   0x100e
+#define DT_MEDIA_BUS_FMT_RGB666_1X24_CPADHI0x1015
+#define DT_MEDIA_BUS_FMT_BGR888_1X24   0x1013
+#define DT_MEDIA_BUS_FMT_GBR888_1X24   0x1014
+#define DT_MEDIA_BUS_FMT_RGB888_1X24   0x100a
+#define DT_MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
+
+#endif /* __DT_BINDINGS_DT_MEDIA_BUS_FORMAT_H */
-- 
2.20.1

[PATCH v3 3/4] dt-bindings: display: startek, startek-kd050c: allow bus-format property

From: Max Krummenacher 

Allow to specify the optional bus-format property newly added to
panel-dpi.

Signed-off-by: Max Krummenacher 

---

(no changes since v2)

Changes in v2:
- New commit allowing bus-format property for derived startek yaml

 .../bindings/display/panel/startek,startek-kd050c.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.yaml 
b/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.yaml
index fd668640afd1..05306713044e 100644
--- 
a/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.yaml
+++ 
b/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.yaml
@@ -19,6 +19,7 @@ properties:
   - {} # panel-dpi, but not listed here to avoid false select
 
   backlight: true
+  bus-format: true
   enable-gpios: true
   height-mm: true
   label: true
-- 
2.20.1

[PATCH v3 1/4] dt-bindings: display: panel-common: allow for additional port node properties