Re: [PATCH] drm/i915: Fix CFI violations in gt_sysfs
On Fri, Sep 23, 2022 at 09:57:47PM -0700, Kees Cook wrote:
> On Thu, Sep 22, 2022 at 12:51:27PM -0700, Nathan Chancellor wrote:
> > [...]
> > To make everything work properly, adjust certain functions to match the
> > type of the ->show() and ->store() members in 'struct kobj_attribute'.
> > Add a macro to generate functions for that can be called via both
> > dev_attr_{show,store}() or kobj_attr_{show,store}() so that they can be
> > called through both kobject locations without violating kCFI and adjust
> > the attribute groups to account for this.
>
> This was quite a roller coaster! I think the solution looks good, even
> if I'm suspicious of the original design that has the same stuff
> available twice in different places. (I have a dim memory of rdma
> needing a refactoring like this too?)
Right, I noticed this comment in intel_gt_sysfs_register() once I fully
saw what was going on:
/*
* We need to make things right with the
* ABI compatibility. The files were originally
* generated under the parent directory.
*
* We generate the files only for gt 0
* to avoid duplicates.
*/
Makes it seem like there will be userspace breakage if these files do
not exist? I figured this was the cleanest solution within those
parameters.
> Reviewed-by: Kees Cook
Thanks for looking it over!
Cheers,
Nathan
Re: [PATCH 2/2] drivers: gpu: drm: remove support for sofef00 driver on s6e3fc2x01 panel
On 24/09/2022 21:36, Nia Espera wrote:
> Removes functionality from sofef00 panel driver which allowed it to
> drive the s6e3fc2x01 panel
>
> Signed-off-by: Nia Espera
Reviewed-by: Caleb Connolly
> ---
> drivers/gpu/drm/panel/Kconfig | 6 +++---
> drivers/gpu/drm/panel/panel-samsung-sofef00.c | 18 --
> 2 files changed, 3 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index ee62d5d8828a..62b9cb6acd05 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -547,16 +547,16 @@ config DRM_PANEL_SAMSUNG_S6E8AA0
> select VIDEOMODE_HELPERS
>
> config DRM_PANEL_SAMSUNG_SOFEF00
> - tristate "Samsung sofef00/s6e3fc2x01 OnePlus 6/6T DSI cmd mode panels"
> + tristate "Samsung sofef00 OnePlus 6 DSI cmd mode panel"
> depends on OF
> depends on DRM_MIPI_DSI
> depends on BACKLIGHT_CLASS_DEVICE
> select VIDEOMODE_HELPERS
> help
> Say Y or M here if you want to enable support for the Samsung AMOLED
> - command mode panels found in the OnePlus 6/6T smartphones.
> + command mode panel found in the OnePlus 6 smartphone.
>
> - The panels are 2280x1080@60Hz and 2340x1080@60Hz respectively
> + The panel is 2280x1080@60Hz
>
> config DRM_PANEL_SAMSUNG_S6E3FC2X01
> tristate "Samsung s6e3fc2x01 OnePlus 6T DSI cmd mode panel"
> diff --git a/drivers/gpu/drm/panel/panel-samsung-sofef00.c
> b/drivers/gpu/drm/panel/panel-samsung-sofef00.c
> index bd02af81a4fe..68e58b9b8c5c 100644
> --- a/drivers/gpu/drm/panel/panel-samsung-sofef00.c
> +++ b/drivers/gpu/drm/panel/panel-samsung-sofef00.c
> @@ -181,20 +181,6 @@ static const struct drm_display_mode
> enchilada_panel_mode = {
> .height_mm = 145,
> };
>
> -static const struct drm_display_mode fajita_panel_mode = {
> - .clock = (1080 + 72 + 16 + 36) * (2340 + 32 + 4 + 18) * 60 / 1000,
> - .hdisplay = 1080,
> - .hsync_start = 1080 + 72,
> - .hsync_end = 1080 + 72 + 16,
> - .htotal = 1080 + 72 + 16 + 36,
> - .vdisplay = 2340,
> - .vsync_start = 2340 + 32,
> - .vsync_end = 2340 + 32 + 4,
> - .vtotal = 2340 + 32 + 4 + 18,
> - .width_mm = 68,
> - .height_mm = 145,
> -};
> -
> static int sofef00_panel_get_modes(struct drm_panel *panel, struct
> drm_connector *connector)
> {
> struct drm_display_mode *mode;
> @@ -327,10 +313,6 @@ static const struct of_device_id
> sofef00_panel_of_match[] = {
> .compatible = "samsung,sofef00",
> .data = _panel_mode,
> },
> - { // OnePlus 6T / fajita
> - .compatible = "samsung,s6e3fc2x01",
> - .data = _panel_mode,
> - },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, sofef00_panel_of_match);
> --
> 2.37.3
>
--
Kind Regards,
Caleb
Re: [PATCH v1] drivers/amd/kv_dpm: check the return value of amdgpu_kv_smc_bapm_enable
On Thu, Sep 22, 2022 at 8:04 PM Lazar, Lijo wrote:
>
>
>
> On 9/23/2022 1:36 AM, Li Zhong wrote:
> > Check the return value of amdgpu_kv_smc_bapm_enable() and log the error
> > when it fails.
> >
> > Signed-off-by: Li Zhong
> > ---
> > drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> > b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> > index 8fd0782a2b20..d392256effe2 100644
> > --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> > +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> > @@ -1384,13 +1384,16 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
> > static void kv_dpm_disable(struct amdgpu_device *adev)
> > {
> > struct kv_power_info *pi = kv_get_pi(adev);
> > + int err;
> >
> > amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
> > AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
> > amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
> > AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
> >
> > - amdgpu_kv_smc_bapm_enable(adev, false);
> > + err = amdgpu_kv_smc_bapm_enable(adev, false);
> > + if (ret)
> > + DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
>
> Return code is captured in 'err' and check is for ret' variable.
>
> BTW, does this code compile?
>
> Thanks,
> Lijo
>
> >
> > if (adev->asic_type == CHIP_MULLINS)
> > kv_enable_nb_dpm(adev, false);
> >
Thanks for your reply. So sorry for submitting the wrong commit. Now it's
fixed in v2 patch.
[PATCH v2] drivers/amd/pm: check the return value of amdgpu_bo_kmap
amdgpu_bo_kmap() returns error when fails to map buffer object. Add the
error check and propagate the error.
Signed-off-by: Li Zhong
---
v2: revise the compile error
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 5 -
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 8fd0782a2b20..f5e08b60f66e 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -1384,13 +1384,16 @@ static int kv_dpm_enable(struct amdgpu_device *adev)
static void kv_dpm_disable(struct amdgpu_device *adev)
{
struct kv_power_info *pi = kv_get_pi(adev);
+ int err;
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
amdgpu_irq_put(adev, >pm.dpm.thermal.irq,
AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
- amdgpu_kv_smc_bapm_enable(adev, false);
+ err = amdgpu_kv_smc_bapm_enable(adev, false);
+ if (err)
+ DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
if (adev->asic_type == CHIP_MULLINS)
kv_enable_nb_dpm(adev, false);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 1eb4e613b27a..ec055858eb95 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1485,6 +1485,7 @@ static int pp_get_prv_buffer_details(void *handle, void
**addr, size_t *size)
{
struct pp_hwmgr *hwmgr = handle;
struct amdgpu_device *adev = hwmgr->adev;
+ int err;
if (!addr || !size)
return -EINVAL;
@@ -1492,7 +1493,9 @@ static int pp_get_prv_buffer_details(void *handle, void
**addr, size_t *size)
*addr = NULL;
*size = 0;
if (adev->pm.smu_prv_buffer) {
- amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
+ err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
+ if (err)
+ return err;
*size = adev->pm.smu_prv_buffer_size;
}
--
2.25.1
Re: [PATCH 1/2] drivers: gpu: drm: add driver for samsung s6e3fc2x01 cmd mode panel
On 24/09/2022 21:36, Nia Espera wrote:
> Adds a dedicated driver for the Samsung s6e3fc2x01 panel used in OnePlus
> 6T smartphones which was previously driven by the sofef00 panel driver
>
> Signed-off-by: Nia Espera
Hi Nia,
Thanks for sending this, I'm glad to see proper support for this panel in it's
own driver rather than the somewhat hacky solution I submitted originally.
There is just one note below, but otherwise:
Reviewed-by: Caleb Connolly
> ---
> MAINTAINERS | 5 +
> drivers/gpu/drm/panel/Kconfig | 11 +
> drivers/gpu/drm/panel/Makefile| 1 +
> .../gpu/drm/panel/panel-samsung-s6e3fc2x01.c | 395 ++
> 4 files changed, 412 insertions(+)
> create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 936490dcc97b..7e9455ac5a13 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6630,6 +6630,11 @@ S: Maintained
> F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml
> F: drivers/gpu/drm/panel/panel-samsung-s6d27a1.c
>
> +DRM DRIVER FOR SAMSUNG S6E3FC2X01 PANELS
> +M: Nia Espera
> +S: Maintained
> +F: drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
> +
> DRM DRIVER FOR SITRONIX ST7703 PANELS
> M: Guido Günther
> R: Purism Kernel Team
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index 9a281120363c..ee62d5d8828a 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -558,6 +558,17 @@ config DRM_PANEL_SAMSUNG_SOFEF00
>
> The panels are 2280x1080@60Hz and 2340x1080@60Hz respectively
>
> +config DRM_PANEL_SAMSUNG_S6E3FC2X01
> + tristate "Samsung s6e3fc2x01 OnePlus 6T DSI cmd mode panel"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + depends on BACKLIGHT_CLASS_DEVICE
> + select VIDEOMODE_HELPERS
> + Say Y or M here if you want to enable support for the Samsung AMOLED
> + command mode panel found in the OnePlus 6T smartphone.
> +
> + The panel is 2340x1080@60Hz
> +
> config DRM_PANEL_SEIKO_43WVF1G
> tristate "Seiko 43WVF1G panel"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index 6d493b9d64fe..b54de8812e91 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI) +=
> panel-samsung-s6e63m0-dsi.o
> obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01) +=
> panel-samsung-s6e88a0-ams452ef01.o
> obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
> obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF00) += panel-samsung-sofef00.o
> +obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FC2X01) += panel-samsung-s6e3fc2x01.o
> obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
> obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
> obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
> diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
> b/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
> new file mode 100644
> index ..719907107bf1
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
> @@ -0,0 +1,395 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +// Copyright (c) 2022 Nia Espera
> +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device
> tree:
> +// Copyright (c) 2022, The Linux Foundation. All rights reserved.
Please use C-style comments for this block (/* ... */), ignoring the SPDX
identifier.
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include
> +#include
> +#include
> +
> +struct samsung_s6e3fc2x01 {
> + struct drm_panel panel;
> + struct mipi_dsi_device *dsi;
> + struct regulator *supply;
> + struct gpio_desc *reset_gpio;
> + const struct drm_display_mode *mode;
> + bool prepared;
> +};
> +
> +static inline
> +struct samsung_s6e3fc2x01 *to_samsung_s6e3fc2x01(struct drm_panel *panel)
> +{
> + return container_of(panel, struct samsung_s6e3fc2x01, panel);
> +}
> +
> +#define dsi_dcs_write_seq(dsi, seq...) do { \
> + static const u8 d[] = { seq }; \
> + int ret;\
> + ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
> + if (ret < 0)\
> + return ret; \
> + } while (0)
> +
> +static void samsung_s6e3fc2x01_reset(struct samsung_s6e3fc2x01 *ctx)
> +{
> + gpiod_set_value_cansleep(ctx->reset_gpio, 0);
> + usleep_range(5000, 6000);
> + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> + usleep_range(2000, 3000);
> +
Re: [PATCH v8 01/12] dt-bindings: display/msm: split qcom, mdss bindings
Hi, On Sat, 24 Sept 2022 at 20:23, Krzysztof Kozlowski wrote: > > On Sat, 24 Sep 2022 15:36:00 +0300, Dmitry Baryshkov wrote: > > Split Mobile Display SubSystem (MDSS) root node bindings to the separate > > yaml file. Changes to the existing (txt) schema: > > - Added optional "vbif_nrt_phys" region used by msm8996 > > - Made "bus" and "vsync" clocks optional (they are not used by some > >platforms) > > - Added optional resets property referencing MDSS reset > > - Defined child nodes pointing to corresponding reference schema. > > - Dropped the "lut" clock. It was added to the schema by mistake (it is > >a part of mdp4 schema, not the mdss). > > > > Reviewed-by: Rob Herring > > Signed-off-by: Dmitry Baryshkov > > --- > > .../devicetree/bindings/display/msm/mdp5.txt | 30 +- > > .../bindings/display/msm/qcom,mdss.yaml | 264 ++ > > 2 files changed, 265 insertions(+), 29 deletions(-) > > create mode 100644 > > Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:0: 'byte' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:1: 'byte_intf' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:2: 'pixel' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:3: 'core' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:4: 'iface' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: clock-names:5: 'bus' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: phy-names:0: 'dsi' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: 'power-domains' is a required property > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: > dsi@1a98000: 'operating-points-v2' is a required property > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml These are the errors generated by the dsi@ node from the example. The DSI schema is handled separately (by Bryan, added to the Cc list). Can we have a lifter for this patch? Or I can revert to dropping the dsi@ part from the example. > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/1681881 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. -- With best wishes Dmitry
Re: [PATCH v8 03/12] dt-bindings: display/msm: add interconnects property to qcom,mdss-smd845
On Sat, 24 Sept 2022 at 20:23, Krzysztof Kozlowski
wrote:
>
> On Sat, 24 Sep 2022 15:36:02 +0300, Dmitry Baryshkov wrote:
> > Add interconnects required for the SDM845 MDSS device tree node. This
> > change was made in the commit c8c61c09e38b ("arm64: dts: qcom: sdm845:
> > Add interconnects property for display"), but was not reflected in the
> > schema.
> >
> > Reviewed-by: Krzysztof Kozlowski
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > .../devicetree/bindings/display/msm/dpu-sdm845.yaml| 10 ++
> > 1 file changed, 10 insertions(+)
> >
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1681884
>
>
> mdss@ae0: 'dsi-phy@ae94400', 'dsi-phy@ae96400', 'dsi@ae94000',
> 'dsi@ae96000' do not match any of the regexes:
> '^display-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
> arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dtb
> arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dtb
> arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb
> arch/arm64/boot/dts/qcom/sdm845-db845c.dtb
> arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dtb
> arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dtb
> arch/arm64/boot/dts/qcom/sdm845-mtp.dtb
> arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb
> arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dtb
> arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dtb
> arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dtb
> arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dtb
> arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dtb
> arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dtb
> arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dtb
> arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dtb
> arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dtb
This is expected and fixed by one of the later patches.
--
With best wishes
Dmitry
Re: [PATCH v2 02/33] drm/tests: Add Kunit Helpers
Den 24.09.2022 19.56, skrev Noralf Trønnes:
>
>
> Den 22.09.2022 16.25, skrev Maxime Ripard:
>> As the number of kunit tests in KMS grows further, we start to have
>> multiple test suites that, for example, need to register a mock DRM
>> driver to interact with the KMS function they are supposed to test.
>>
>> Let's add a file meant to provide those kind of helpers to avoid
>> duplication.
>>
>> Signed-off-by: Maxime Ripard
>>
>> diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile
>> index 2d9f49b62ecb..b29ef1085cad 100644
>> --- a/drivers/gpu/drm/tests/Makefile
>> +++ b/drivers/gpu/drm/tests/Makefile
>> @@ -8,6 +8,7 @@ obj-$(CONFIG_DRM_KUNIT_TEST) += \
>> drm_format_helper_test.o \
>> drm_format_test.o \
>> drm_framebuffer_test.o \
>> +drm_kunit_helpers.o \
>> drm_mm_test.o \
>> drm_plane_helper_test.o \
>> drm_rect_test.o
>> diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.c
>> b/drivers/gpu/drm/tests/drm_kunit_helpers.c
>> new file mode 100644
>> index ..7ebd620481c1
>> --- /dev/null
>> +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.c
>> @@ -0,0 +1,54 @@
>> +#include
>> +#include
>> +
>> +#include
>> +
>> +static const struct drm_mode_config_funcs drm_mode_config_funcs = {
>> +};
>> +
>> +static const struct drm_driver drm_mode_driver = {
>> +};
>> +
>> +static void drm_kunit_free_device(struct drm_device *drm, void *ptr)
>> +{
>> +struct device *dev = ptr;
>> +
>> +root_device_unregister(dev);
>> +}
>> +
>> +struct drm_device *drm_kunit_device_init(const char *name)
>> +{
>> +struct drm_device *drm;
>> +struct device *dev;
>> +int ret;
>> +
>> +dev = root_device_register(name);
>> +if (IS_ERR(dev))
>> +return ERR_CAST(dev);
>> +
>> +drm = drm_dev_alloc(_mode_driver, dev);
>
> I can't find drm being freed anywhere?
> Maybe you could assign it to drm->managed.final_kfree.
>
Perhaps a better solution would be to use devm_drm_dev_alloc() and
unregister the root device on exit. That avoids reaching into the drm
managed internals and it looks more like a regular driver.
> Noralf.
>
>> +if (IS_ERR(drm)) {
>> +root_device_unregister(dev);
>> +return ERR_CAST(drm);
>> +}
>> +drm->mode_config.funcs = _mode_config_funcs;
>> +
>> +ret = drmm_add_action_or_reset(drm, drm_kunit_free_device, dev);
>> +if (ret)
>> +goto err_put_device;
>> +
>> +ret = drmm_mode_config_init(drm);
>> +if (ret)
>> +return ERR_PTR(ret);
>> +
>> +return drm;
>> +
>> +err_put_device:
>> +drm_dev_put(drm);
>> +return ERR_PTR(ret);
>> +}
>> +
>> +void drm_kunit_device_exit(struct drm_device *drm)
>> +{
>> +drm_dev_put(drm);
>> +}
>> diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.h
>> b/drivers/gpu/drm/tests/drm_kunit_helpers.h
>> new file mode 100644
>> index ..5015a327a8c1
>> --- /dev/null
>> +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.h
>> @@ -0,0 +1,9 @@
>> +#ifndef DRM_KUNIT_HELPERS_H_
>> +#define DRM_KUNIT_HELPERS_H_
>> +
>> +struct drm_device;
>> +
>> +struct drm_device *drm_kunit_device_init(const char *name);
>> +void drm_kunit_device_exit(struct drm_device *drm);
>> +
>> +#endif // DRM_KUNIT_HELPERS_H_
>>
Re: [PATCH v2 02/33] drm/tests: Add Kunit Helpers
Den 22.09.2022 16.25, skrev Maxime Ripard:
> As the number of kunit tests in KMS grows further, we start to have
> multiple test suites that, for example, need to register a mock DRM
> driver to interact with the KMS function they are supposed to test.
>
> Let's add a file meant to provide those kind of helpers to avoid
> duplication.
>
> Signed-off-by: Maxime Ripard
>
> diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile
> index 2d9f49b62ecb..b29ef1085cad 100644
> --- a/drivers/gpu/drm/tests/Makefile
> +++ b/drivers/gpu/drm/tests/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_DRM_KUNIT_TEST) += \
> drm_format_helper_test.o \
> drm_format_test.o \
> drm_framebuffer_test.o \
> + drm_kunit_helpers.o \
> drm_mm_test.o \
> drm_plane_helper_test.o \
> drm_rect_test.o
> diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.c
> b/drivers/gpu/drm/tests/drm_kunit_helpers.c
> new file mode 100644
> index ..7ebd620481c1
> --- /dev/null
> +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.c
> @@ -0,0 +1,54 @@
> +#include
> +#include
> +
> +#include
> +
> +static const struct drm_mode_config_funcs drm_mode_config_funcs = {
> +};
> +
> +static const struct drm_driver drm_mode_driver = {
> +};
> +
> +static void drm_kunit_free_device(struct drm_device *drm, void *ptr)
> +{
> + struct device *dev = ptr;
> +
> + root_device_unregister(dev);
> +}
> +
> +struct drm_device *drm_kunit_device_init(const char *name)
> +{
> + struct drm_device *drm;
> + struct device *dev;
> + int ret;
> +
> + dev = root_device_register(name);
> + if (IS_ERR(dev))
> + return ERR_CAST(dev);
> +
> + drm = drm_dev_alloc(_mode_driver, dev);
I can't find drm being freed anywhere?
Maybe you could assign it to drm->managed.final_kfree.
Noralf.
> + if (IS_ERR(drm)) {
> + root_device_unregister(dev);
> + return ERR_CAST(drm);
> + }
> + drm->mode_config.funcs = _mode_config_funcs;
> +
> + ret = drmm_add_action_or_reset(drm, drm_kunit_free_device, dev);
> + if (ret)
> + goto err_put_device;
> +
> + ret = drmm_mode_config_init(drm);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + return drm;
> +
> +err_put_device:
> + drm_dev_put(drm);
> + return ERR_PTR(ret);
> +}
> +
> +void drm_kunit_device_exit(struct drm_device *drm)
> +{
> + drm_dev_put(drm);
> +}
> diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.h
> b/drivers/gpu/drm/tests/drm_kunit_helpers.h
> new file mode 100644
> index ..5015a327a8c1
> --- /dev/null
> +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.h
> @@ -0,0 +1,9 @@
> +#ifndef DRM_KUNIT_HELPERS_H_
> +#define DRM_KUNIT_HELPERS_H_
> +
> +struct drm_device;
> +
> +struct drm_device *drm_kunit_device_init(const char *name);
> +void drm_kunit_device_exit(struct drm_device *drm);
> +
> +#endif // DRM_KUNIT_HELPERS_H_
>
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Sat, Sep 24, 2022 at 12:07:44PM -0500, Rob Herring wrote: > On Tue, Sep 20, 2022 at 09:59:04AM -0500, Chris Morgan wrote: > > From: Chris Morgan > > > > Add documentation for the NewVision NV3051D panel bindings. > > Note that for the two expected consumers of this panel binding > > the underlying LCD model is unknown. Name "anbernic,rg353p-panel" > > is used because the hardware itself is known as "anbernic,rg353p". > > > > Signed-off-by: Chris Morgan > > --- > > .../display/panel/newvision,nv3051d.yaml | 55 +++ > > 1 file changed, 55 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > new file mode 100644 > > index ..d90bca4171c2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fpanel%2Fnewvision%2Cnv3051d.yaml%23data=05%7C01%7C%7C4f204345128d4cb827ca08da9e4f4d06%7C84df9e7fe9f640afb435%7C1%7C0%7C637996360672620588%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=9%2B66S0t1p9EqWBdmaLBj8pKte2fjzsmL%2FSbmmD8eNi0%3Dreserved=0 > > +$schema: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23data=05%7C01%7C%7C4f204345128d4cb827ca08da9e4f4d06%7C84df9e7fe9f640afb435%7C1%7C0%7C637996360672620588%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=r%2BzTHlte226t9fXktNC9k4NO%2FE2RomRIxuWBuRshIw0%3Dreserved=0 > > + > > +title: NewVision NV3051D based LCD panel > > + > > +description: | > > + The NewVision NV3051D is a driver chip used to drive DSI panels. For now, > > + this driver only supports the 640x480 panels found in the Anbernic RG353 > > + based devices. > > + > > +maintainers: > > + - Chris Morgan > > + > > +allOf: > > + - $ref: panel-common.yaml# > > + > > +properties: > > + compatible: > > +items: > > + - enum: > > + - anbernic,rg353p-panel > > + - anbernic,rg353v-panel > > Is 'panel' redundant? IOW, could 'rg353v' identify something else other > than the panel? It is not redundant, the device itself is identified as "anbernic,rg353v". I don't have a part number for the LCD panel itself, only the controller IC. Thank you. > > Rob
Re: [PATCH v2 01/33] drm/tests: Order Kunit tests in Makefile
Den 22.09.2022 16.25, skrev Maxime Ripard: > Since we've recently added a ton of tests, the list starts to be a bit > of a mess and creates unneeded conflicts. > > Let's order it alphabetically. > > Signed-off-by: Maxime Ripard > Reviewed-by: Noralf Trønnes
Re: [PATCH v8 01/12] dt-bindings: display/msm: split qcom,mdss bindings
On Sat, 24 Sep 2022 15:36:00 +0300, Dmitry Baryshkov wrote: > Split Mobile Display SubSystem (MDSS) root node bindings to the separate > yaml file. Changes to the existing (txt) schema: > - Added optional "vbif_nrt_phys" region used by msm8996 > - Made "bus" and "vsync" clocks optional (they are not used by some >platforms) > - Added optional resets property referencing MDSS reset > - Defined child nodes pointing to corresponding reference schema. > - Dropped the "lut" clock. It was added to the schema by mistake (it is >a part of mdp4 schema, not the mdss). > > Reviewed-by: Rob Herring > Signed-off-by: Dmitry Baryshkov > --- > .../devicetree/bindings/display/msm/mdp5.txt | 30 +- > .../bindings/display/msm/qcom,mdss.yaml | 264 ++ > 2 files changed, 265 insertions(+), 29 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:0: 'byte' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:1: 'byte_intf' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:2: 'pixel' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:3: 'core' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:4: 'iface' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: clock-names:5: 'bus' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: phy-names:0: 'dsi' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: 'power-domains' is a required property From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.example.dtb: dsi@1a98000: 'operating-points-v2' is a required property From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1681881 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Re: [PATCH v8 03/12] dt-bindings: display/msm: add interconnects property to qcom,mdss-smd845
On Sat, 24 Sep 2022 15:36:02 +0300, Dmitry Baryshkov wrote:
> Add interconnects required for the SDM845 MDSS device tree node. This
> change was made in the commit c8c61c09e38b ("arm64: dts: qcom: sdm845:
> Add interconnects property for display"), but was not reflected in the
> schema.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Dmitry Baryshkov
> ---
> .../devicetree/bindings/display/msm/dpu-sdm845.yaml| 10 ++
> 1 file changed, 10 insertions(+)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1681884
mdss@ae0: 'dsi-phy@ae94400', 'dsi-phy@ae96400', 'dsi@ae94000',
'dsi@ae96000' do not match any of the regexes:
'^display-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dtb
arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dtb
arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb
arch/arm64/boot/dts/qcom/sdm845-db845c.dtb
arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dtb
arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dtb
arch/arm64/boot/dts/qcom/sdm845-mtp.dtb
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dtb
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dtb
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dtb
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dtb
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dtb
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dtb
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dtb
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dtb
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dtb
Re: [PATCH v2 32/33] drm/vc4: vec: Add support for more analog TV standards
Den 22.09.2022 16.25, skrev Maxime Ripard: > From: Mateusz Kwiatkowski > > Add support for the following composite output modes (all of them are > somewhat more obscure than the previously defined ones): > > - NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to > 4.43361875 MHz (the PAL subcarrier frequency). Never used for > broadcasting, but sometimes used as a hack to play NTSC content in PAL > regions (e.g. on VCRs). > - PAL_N - PAL with alternative chroma subcarrier frequency, > 3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay > and Uruguay to fit 576i50 with colour in 6 MHz channel raster. > - PAL60 - 480i60 signal with PAL-style color at normal European PAL > frequency. Another non-standard, non-broadcast mode, used in similar > contexts as NTSC_443. Some displays support one but not the other. > - SECAM - French frequency-modulated analog color standard; also have > been broadcast in Eastern Europe and various parts of Africa and Asia. > Uses the same 576i50 timings as PAL. > > Also added some comments explaining color subcarrier frequency > registers. > > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > Acked-by: Noralf Trønnes
Re: [PATCH v2 31/33] drm/vc4: vec: Convert to the new TV mode property
Den 22.09.2022 16.25, skrev Maxime Ripard:
> Now that the core can deal fine with analog TV modes, let's convert the vc4
> VEC driver to leverage those new features.
>
> We've added some backward compatibility to support the old TV mode property
> and translate it into the new TV norm property.
>
You can mention here that atomic_check is added in order to trigger a
modeset should tv.mode change.
> Signed-off-by: Maxime Ripard
>
> diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
> index 6828b79a1001..a9463364015b 100644
> --- a/drivers/gpu/drm/vc4/vc4_vec.c
> +++ b/drivers/gpu/drm/vc4/vc4_vec.c
> @@ -172,6 +172,8 @@ struct vc4_vec {
>
> struct clk *clock;
>
> + struct drm_property *legacy_tv_mode_property;
> +
> struct debugfs_regset32 regset;
> };
>
> @@ -184,6 +186,12 @@ encoder_to_vc4_vec(struct drm_encoder *encoder)
> return container_of(encoder, struct vc4_vec, encoder.base);
> }
>
> +static inline struct vc4_vec *
> +connector_to_vc4_vec(struct drm_connector *connector)
> +{
> + return container_of(connector, struct vc4_vec, connector);
> +}
> +
> enum vc4_vec_tv_mode_id {
> VC4_VEC_TV_MODE_NTSC,
> VC4_VEC_TV_MODE_NTSC_J,
> @@ -192,7 +200,7 @@ enum vc4_vec_tv_mode_id {
> };
>
> struct vc4_vec_tv_mode {
> - const struct drm_display_mode *mode;
> + unsigned int mode;
> u32 config0;
> u32 config1;
> u32 custom_freq;
> @@ -225,43 +233,51 @@ static const struct debugfs_reg32 vec_regs[] = {
> VC4_REG32(VEC_DAC_MISC),
> };
>
> -static const struct drm_display_mode ntsc_mode = {
> - DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
> - 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
> - 480, 480 + 7, 480 + 7 + 6, 525, 0,
> - DRM_MODE_FLAG_INTERLACE)
> -};
> -
> -static const struct drm_display_mode pal_mode = {
> - DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
> - 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
> - 576, 576 + 4, 576 + 4 + 6, 625, 0,
> - DRM_MODE_FLAG_INTERLACE)
> -};
> -
> static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
> - [VC4_VEC_TV_MODE_NTSC] = {
> - .mode = _mode,
> + {
> + .mode = DRM_MODE_TV_MODE_NTSC,
> .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
> .config1 = VEC_CONFIG1_C_CVBS_CVBS,
> },
> - [VC4_VEC_TV_MODE_NTSC_J] = {
> - .mode = _mode,
> + {
> + .mode = DRM_MODE_TV_MODE_NTSC_J,
> .config0 = VEC_CONFIG0_NTSC_STD,
> .config1 = VEC_CONFIG1_C_CVBS_CVBS,
> },
> - [VC4_VEC_TV_MODE_PAL] = {
> - .mode = _mode,
> + {
> + .mode = DRM_MODE_TV_MODE_PAL,
> .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
> .config1 = VEC_CONFIG1_C_CVBS_CVBS,
> },
> - [VC4_VEC_TV_MODE_PAL_M] = {
> - .mode = _mode,
> + {
> + .mode = DRM_MODE_TV_MODE_PAL_M,
> .config0 = VEC_CONFIG0_PAL_M_STD,
> .config1 = VEC_CONFIG1_C_CVBS_CVBS,
> },
> };
>
> +static inline const struct vc4_vec_tv_mode *
> +vc4_vec_tv_mode_lookup(unsigned int mode)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
> + const struct vc4_vec_tv_mode *tv_mode = _vec_tv_modes[i];
> +
> + if (tv_mode->mode == mode)
> + return tv_mode;
> + }
> +
> + return NULL;
> +}
> +
> +static const struct drm_prop_enum_list tv_mode_names[] = {
> + { VC4_VEC_TV_MODE_NTSC, "NTSC", },
> + { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
> + { VC4_VEC_TV_MODE_PAL, "PAL", },
> + { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
> +};
> +
> static enum drm_connector_status
> vc4_vec_connector_detect(struct drm_connector *connector, bool force)
> {
> @@ -276,19 +292,99 @@ static void vc4_vec_connector_reset(struct
> drm_connector *connector)
>
> static int vc4_vec_connector_get_modes(struct drm_connector *connector)
> {
> - struct drm_connector_state *state = connector->state;
> struct drm_display_mode *mode;
> + int count = 0;
>
> - mode = drm_mode_duplicate(connector->dev,
> - vc4_vec_tv_modes[state->tv.legacy_mode].mode);
> + mode = drm_mode_analog_ntsc_480i(connector->dev);
> if (!mode) {
> DRM_ERROR("Failed to create a new display mode\n");
> return -ENOMEM;
> }
>
> + mode->type |= DRM_MODE_TYPE_PREFERRED;
> drm_mode_probed_add(connector, mode);
> + count += 1;
>
> - return 1;
> + mode = drm_mode_analog_pal_576i(connector->dev);
> + if (!mode) {
> + DRM_ERROR("Failed to create a new display mode\n");
> + return -ENOMEM;
> + }
> +
> + drm_mode_probed_add(connector, mode);
> + count += 1;
> +
> + return count;
Why not just
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Tue, Sep 20, 2022 at 09:59:04AM -0500, Chris Morgan wrote: > From: Chris Morgan > > Add documentation for the NewVision NV3051D panel bindings. > Note that for the two expected consumers of this panel binding > the underlying LCD model is unknown. Name "anbernic,rg353p-panel" > is used because the hardware itself is known as "anbernic,rg353p". > > Signed-off-by: Chris Morgan > --- > .../display/panel/newvision,nv3051d.yaml | 55 +++ > 1 file changed, 55 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > diff --git > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > new file mode 100644 > index ..d90bca4171c2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/panel/newvision,nv3051d.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NewVision NV3051D based LCD panel > + > +description: | > + The NewVision NV3051D is a driver chip used to drive DSI panels. For now, > + this driver only supports the 640x480 panels found in the Anbernic RG353 > + based devices. > + > +maintainers: > + - Chris Morgan > + > +allOf: > + - $ref: panel-common.yaml# > + > +properties: > + compatible: > +items: > + - enum: > + - anbernic,rg353p-panel > + - anbernic,rg353v-panel Is 'panel' redundant? IOW, could 'rg353v' identify something else other than the panel? Rob
Re: [PATCH v2 30/33] drm/vc4: vec: Check for VEC output constraints
Den 22.09.2022 16.25, skrev Maxime Ripard: > From: Mateusz Kwiatkowski > > The VEC can accept pretty much any relatively reasonable mode, but still > has a bunch of constraints to meet. > > Let's create an atomic_check() implementation that will make sure we > don't end up accepting a non-functional mode. > > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > Acked-by: Noralf Trønnes
Re: [PATCH v2 28/33] drm/vc4: vec: Fix definition of PAL-M mode
Den 22.09.2022 16.25, skrev Maxime Ripard: > From: Mateusz Kwiatkowski > > PAL-M is a Brazilian analog TV standard that uses a PAL-style chroma > subcarrier at 3.575611[888111] MHz on top of 525-line (480i60) timings. > This commit makes the driver actually use the proper VEC preset for this > mode instead of just changing PAL subcarrier frequency. > > Signed-off-by: Mateusz Kwiatkowski > Signed-off-by: Maxime Ripard > Acked-by: Noralf Trønnes
Re: [PATCH v2 27/33] drm/atomic-helper: Add an analog TV atomic_check implementation
Den 22.09.2022 16.25, skrev Maxime Ripard:
> The analog TV connector drivers share some atomic_check logic, and the new
> TV standard property have created a bunch of new constraints that needs to
> be shared across drivers too.
The constraints part doesn't apply anymore after removing the display
mode check. It's only about detecting changes now.
Noralf.
>
> Let's create an atomic_check helper for those use cases.
>
> Reviewed-by: Noralf Trønnes
> Signed-off-by: Maxime Ripard
>
> diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
> b/drivers/gpu/drm/drm_atomic_state_helper.c
> index 0373c3dc824b..e88c57a4f7be 100644
> --- a/drivers/gpu/drm/drm_atomic_state_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_state_helper.c
> @@ -556,6 +556,55 @@ void drm_atomic_helper_connector_tv_reset(struct
> drm_connector *connector)
> }
> EXPORT_SYMBOL(drm_atomic_helper_connector_tv_reset);
>
> +/**
> + * @drm_atomic_helper_connector_tv_check: Validate an analog TV connector
> state
> + * @connector: DRM Connector
> + * @state: the DRM State object
> + *
> + * Checks the state object to see if the requested state is valid for an
> + * analog TV connector.
> + *
> + * Returns:
> + * Zero for success, a negative error code on error.
> + */
> +int drm_atomic_helper_connector_tv_check(struct drm_connector *connector,
> + struct drm_atomic_state *state)
> +{
> + struct drm_connector_state *old_conn_state =
> + drm_atomic_get_old_connector_state(state, connector);
> + struct drm_connector_state *new_conn_state =
> + drm_atomic_get_new_connector_state(state, connector);
> + struct drm_crtc_state *crtc_state;
> + struct drm_crtc *crtc;
> +
> + crtc = new_conn_state->crtc;
> + if (!crtc)
> + return 0;
> +
> + crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> + if (!crtc_state)
> + return -EINVAL;
> +
> + if (old_conn_state->tv.mode != new_conn_state->tv.mode)
> + crtc_state->mode_changed = true;
> +
> + if ((old_conn_state->tv.margins.left !=
> new_conn_state->tv.margins.left) ||
> + (old_conn_state->tv.margins.right !=
> new_conn_state->tv.margins.right) ||
> + (old_conn_state->tv.margins.top != new_conn_state->tv.margins.top)
> ||
> + (old_conn_state->tv.margins.bottom !=
> new_conn_state->tv.margins.bottom) ||
> + (old_conn_state->tv.mode != new_conn_state->tv.mode) ||
> + (old_conn_state->tv.brightness != new_conn_state->tv.brightness) ||
> + (old_conn_state->tv.contrast != new_conn_state->tv.contrast) ||
> + (old_conn_state->tv.flicker_reduction !=
> new_conn_state->tv.flicker_reduction) ||
> + (old_conn_state->tv.overscan != new_conn_state->tv.overscan) ||
> + (old_conn_state->tv.saturation != new_conn_state->tv.saturation) ||
> + (old_conn_state->tv.hue != new_conn_state->tv.hue))
> + crtc_state->connectors_changed = true;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_atomic_helper_connector_tv_check);
> +
> /**
> * __drm_atomic_helper_connector_duplicate_state - copy atomic connector
> state
> * @connector: connector object
> diff --git a/include/drm/drm_atomic_state_helper.h
> b/include/drm/drm_atomic_state_helper.h
> index c8fbce795ee7..b9740edb2658 100644
> --- a/include/drm/drm_atomic_state_helper.h
> +++ b/include/drm/drm_atomic_state_helper.h
> @@ -26,6 +26,7 @@
>
> #include
>
> +struct drm_atomic_state;
> struct drm_bridge;
> struct drm_bridge_state;
> struct drm_crtc;
> @@ -71,6 +72,8 @@ void __drm_atomic_helper_connector_reset(struct
> drm_connector *connector,
>struct drm_connector_state
> *conn_state);
> void drm_atomic_helper_connector_reset(struct drm_connector *connector);
> void drm_atomic_helper_connector_tv_reset(struct drm_connector *connector);
> +int drm_atomic_helper_connector_tv_check(struct drm_connector *connector,
> + struct drm_atomic_state *state);
> void drm_atomic_helper_connector_tv_margins_reset(struct drm_connector
> *connector);
> void
> __drm_atomic_helper_connector_duplicate_state(struct drm_connector
> *connector,
>
Re: [PATCH v2 09/33] drm/connector: Add TV standard property
Den 22.09.2022 16.25, skrev Maxime Ripard:
> The TV mode property has been around for a while now to select and get the
> current TV mode output on an analog TV connector.
>
> Despite that property name being generic, its content isn't and has been
> driver-specific which makes it hard to build any generic behaviour on top
> of it, both in kernel and user-space.
>
> Let's create a new enum tv norm property, that can contain any of the
> analog TV standards currently supported by kernel drivers. Each driver can
> then pass in a bitmask of the modes it supports, and the property
> creation function will filter out the modes not supported.
>
> We'll then be able to phase out the older tv mode property.
>
> Signed-off-by: Maxime Ripard
>
Please can you add per patch changelogs, it's hard to review when I have
to recall what might have happened with each patch. If you do it drm
style and put in the commit message it should be easy enough to do.
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 4e4fbc9e0049..e7aa8de08f5b 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -980,6 +980,18 @@ static const struct drm_prop_enum_list
> drm_dvi_i_subconnector_enum_list[] = {
> DRM_ENUM_NAME_FN(drm_get_dvi_i_subconnector_name,
>drm_dvi_i_subconnector_enum_list)
>
> +static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = {
> + { DRM_MODE_TV_MODE_NONE, "None" },
> + { DRM_MODE_TV_MODE_NTSC, "NTSC" },
I think going back to plain NTSC and PAL is a good choice for the common
variants.
> + { DRM_MODE_TV_MODE_NTSC_443, "NTSC-443" },
> + { DRM_MODE_TV_MODE_NTSC_J, "NTSC-J" },
> + { DRM_MODE_TV_MODE_PAL, "PAL" },
> + { DRM_MODE_TV_MODE_PAL_M, "PAL-M" },
> + { DRM_MODE_TV_MODE_PAL_N, "PAL-N" },
> + { DRM_MODE_TV_MODE_SECAM, "SECAM" },
> +};
> +DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list)
> +
> static const struct drm_prop_enum_list drm_tv_select_enum_list[] = {
> { DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
> { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
> @@ -1645,6 +1657,10 @@ EXPORT_SYMBOL(drm_mode_create_tv_margin_properties);
> * responsible for allocating a list of format names and passing them to
> * this routine.
> *
> + * NOTE: This functions registers the deprecated "mode" connector
> + * property to select the analog TV mode (ie, NTSC, PAL, etc.). New
> + * drivers must use drm_mode_create_tv_properties() instead.
> + *
> * Returns:
> * 0 on success or a negative error code on failure.
> */
> @@ -1686,7 +1702,6 @@ int drm_mode_create_tv_properties_legacy(struct
> drm_device *dev,
> if (drm_mode_create_tv_margin_properties(dev))
> goto nomem;
>
> -
> if (num_modes) {
> dev->mode_config.legacy_tv_mode_property =
> drm_property_create(dev, DRM_MODE_PROP_ENUM,
> @@ -1735,6 +1750,49 @@ int drm_mode_create_tv_properties_legacy(struct
> drm_device *dev,
> }
> EXPORT_SYMBOL(drm_mode_create_tv_properties_legacy);
>
> +/**
> + * drm_mode_create_tv_properties - create TV specific connector properties
> + * @dev: DRM device
> + * @supported_tv_modes: Bitmask of TV modes supported (See
> DRM_MODE_TV_MODE_*)
> +
> + * Called by a driver's TV initialization routine, this function creates
> + * the TV specific connector properties for a given device. Caller is
> + * responsible for allocating a list of format names and passing them to
> + * this routine.
Copy-paste error, there are no format names in this version.
> + *
> + * Returns:
> + * 0 on success or a negative error code on failure.
> + */
> +int drm_mode_create_tv_properties(struct drm_device *dev,
> + unsigned int supported_tv_modes)
> +{
> + struct drm_prop_enum_list tv_mode_list[DRM_MODE_TV_MODE_MAX];
> + struct drm_property *tv_mode;
> + unsigned int i, len = 0;
> +
> + if (dev->mode_config.tv_mode_property)
> + return 0;
> +
> + for (i = 0; i < DRM_MODE_TV_MODE_MAX; i++) {
> + if (!(supported_tv_modes & BIT(i)))
> + continue;
> +
> + tv_mode_list[len].type = i;
> + tv_mode_list[len].name = drm_get_tv_mode_name(i);
> + len++;
> + }
> +
> + tv_mode = drm_property_create_enum(dev, 0, "TV mode",
> +tv_mode_list, len);
> + if (!tv_mode)
> + return -ENOMEM;
> +
> + dev->mode_config.tv_mode_property = tv_mode;
> +
> + return drm_mode_create_tv_properties_legacy(dev, 0, NULL);
> +}
> +EXPORT_SYMBOL(drm_mode_create_tv_properties);
> +
> /**
> * drm_mode_create_scaling_mode_property - create scaling mode property
> * @dev: DRM device
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index d566b4a4709c..fffacbfd0a45 100644
> ---
Re: [PATCH v2 08/33] drm/connector: Rename drm_mode_create_tv_properties
Den 22.09.2022 16.25, skrev Maxime Ripard: > drm_mode_create_tv_properties(), among other things, will create the > "mode" property that stores the analog TV mode that connector is > supposed to output. > > However, that property is getting deprecated, so let's rename that > function to mention it's deprecated. We'll introduce a new variant of > that function creating the property superseeding it in a later patch. > > Signed-off-by: Maxime Ripard > Reviewed-by: Noralf Trønnes
Re: [PATCH v2 06/33] drm/connector: Rename legacy TV property
Den 22.09.2022 16.25, skrev Maxime Ripard: > The current tv_mode has driver-specific values that don't allow to > easily share code using it, either at the userspace or kernel level. > > Since we're going to introduce a new, generic, property that fit the > same purpose, let's rename this one to legacy_tv_mode to make it > obvious we should move away from it. > > Signed-off-by: Maxime Ripard > Reviewed-by: Noralf Trønnes
Re: [PATCH v2 00/41] drm: Analog TV Improvements
Den 21.09.2022 16.03, skrev Maxime Ripard:
> On Wed, Sep 07, 2022 at 06:44:53PM +0200, Noralf Trønnes wrote:
>>
>>
>> Den 07.09.2022 12.36, skrev Stefan Wahren:
>>> Hi Maxime,
>>>
>>> Am 05.09.22 um 16:57 schrieb Maxime Ripard:
On Fri, Sep 02, 2022 at 01:28:16PM +0200, Noralf Trønnes wrote:
>
> Den 01.09.2022 21.35, skrev Noralf Trønnes:
>>
>> I have finally found a workaround for my kernel hangs.
>>
>> Dom had a look at my kernel and found that the VideoCore was fine, and
>> he said this:
>>
>>> That suggests cause of lockup was on arm side rather than VC side.
>>>
>>> But it's hard to diagnose further. Once you've had a peripheral not
>>> respond, the AXI bus locks up and no further operations are possible.
>>> Usual causes of this are required clocks being stopped or domains
>>> disabled and then trying to access the hardware.
>>>
>> So when I got this on my 64-bit build:
>>
>> [ 166.702171] SError Interrupt on CPU1, code 0xbf02 --
>> SError
>> [ 166.702187] CPU: 1 PID: 8 Comm: kworker/u8:0 Tainted: G W
>> 5.19.0-rc6-00096-gba7973977976-dirty #1
>> [ 166.702200] Hardware name: Raspberry Pi 4 Model B Rev 1.1 (DT)
>> [ 166.702206] Workqueue: events_freezable_power_
>> thermal_zone_device_check
>> [ 166.702231] pstate: 20c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS
>> BTYPE=--)
>> [ 166.702242] pc : regmap_mmio_read32le+0x10/0x28
>> [ 166.702261] lr : regmap_mmio_read+0x44/0x70
>> ...
>> [ 166.702606] bcm2711_get_temp+0x58/0xb0 [bcm2711_thermal]
>>
>> I wondered if that reg read was stalled due to a clock being stopped.
>>
>> Lo and behold, disabling runtime pm and keeping the vec clock running
>> all the time fixed it[1].
>>
>> I don't know what the problem is, but at least I can now test this
>> patchset.
>>
>> [1] https://gist.github.com/notro/23b984e7fa05cfbda2db50a421cac065
>>
> It turns out I didn't have to disable runtime pm:
> https://gist.github.com/notro/0adcfcb12460b54e54458afe11dc8ea2
If the bcm2711_thermal IP needs that clock to be enabled, it should grab
a reference itself, but it looks like even the device tree binding
doesn't ask for one.
>>> The missing clock in the device tree binding is expected, because
>>> despite of the code there is not much information about the BCM2711
>>> clock tree. But i'm skeptical that the AVS IP actually needs the VEC
>>> clock, i think it's more likely that the VEC clock parent is changed and
>>> that cause this issue. I could take care of the bcm2711 binding & driver
>>> if i know which clock is really necessary.
>>
>> Seems you're right, keeping the parent always enabled is enough:
>>
>> clk_prepare_enable(clk_get_parent(vec->clock)); // pllc_per
>>
>> I tried enabling just the grandparent clock as well, but that didn't help.
>
> Yeah, adding tracing to the clock framework shows that it indeed
> disables PLLC_PER. So there's probably some other device that depends on
> it but doesn't take a reference to it.
>
> I had a look, but it's not really obvious what that might be.
>
> This patch makes sure that the PLL*_PER are never disabled, could you
> test it? It seems to work for me.
>
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 48a1eb9f2d55..3839261ee419 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1675,7 +1675,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] =
> {
> .load_mask = CM_PLLA_LOADPER,
> .hold_mask = CM_PLLA_HOLDPER,
> .fixed_divider = 1,
> - .flags = CLK_SET_RATE_PARENT),
> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
> [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
> SOC_ALL,
> .name = "plla_dsi0",
> @@ -1784,7 +1784,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] =
> {
> .load_mask = CM_PLLC_LOADPER,
> .hold_mask = CM_PLLC_HOLDPER,
> .fixed_divider = 1,
> - .flags = CLK_SET_RATE_PARENT),
> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
>
Yes, this worked, but it's enough to mark pllc_per as critical.
Noralf.
> /*
>* PLLD is the display PLL, used to drive DSI display panels.
> @@ -1891,7 +1891,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] =
> {
> .load_mask = CM_PLLH_LOADAUX,
> .hold_mask = 0,
> .fixed_divider = 1,
> - .flags = CLK_SET_RATE_PARENT),
> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
> [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
> SOC_BCM2835,
> .name = "pllh_pix",
>
>
> Maxime
[PATCH v3 5/7] drm/ivpu: Implement firmware parsing and booting
Read, parse and boot VPU firmware image.
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 1 +
drivers/gpu/drm/ivpu/ivpu_drv.c | 122 +++-
drivers/gpu/drm/ivpu/ivpu_drv.h | 10 +
drivers/gpu/drm/ivpu/ivpu_fw.c | 422
drivers/gpu/drm/ivpu/ivpu_fw.h | 38 +++
drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 11 +
drivers/gpu/drm/ivpu/vpu_boot_api.h | 241
include/uapi/drm/ivpu_drm.h | 21 ++
8 files changed, 865 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_fw.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_fw.h
create mode 100644 drivers/gpu/drm/ivpu/vpu_boot_api.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index 4e33860c0dc4..8e9b3ae1a4cc 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -3,6 +3,7 @@
intel_vpu-y := \
ivpu_drv.o \
+ ivpu_fw.o \
ivpu_gem.o \
ivpu_hw_mtl.o \
ivpu_ipc.o \
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index b7e2bc54897a..67384671092e 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -13,10 +13,13 @@
#include
#include
+#include "vpu_boot_api.h"
#include "ivpu_drv.h"
+#include "ivpu_fw.h"
#include "ivpu_gem.h"
#include "ivpu_hw.h"
#include "ivpu_ipc.h"
+#include "ivpu_jsm_msg.h"
#include "ivpu_mmu.h"
#include "ivpu_mmu_context.h"
@@ -31,6 +34,10 @@ int ivpu_dbg_mask;
module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
+int ivpu_test_mode;
+module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
+MODULE_PARM_DESC(test_mode, "Test mode: 0 - normal operation, 1 - fw unit
test, 2 - null hw");
+
u8 ivpu_pll_min_ratio;
module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency");
@@ -126,6 +133,28 @@ static int ivpu_get_param_ioctl(struct drm_device *dev,
void *data, struct drm_f
case DRM_IVPU_PARAM_CONTEXT_ID:
args->value = file_priv->ctx.id;
break;
+ case DRM_IVPU_PARAM_FW_API_VERSION:
+ if (args->index < VPU_FW_API_VER_NUM) {
+ struct vpu_firmware_header *fw_hdr;
+
+ fw_hdr = (struct vpu_firmware_header
*)vdev->fw->file->data;
+ args->value = fw_hdr->api_version[args->index];
+ } else {
+ ret = -EINVAL;
+ }
+ break;
+ case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
+ ret = ivpu_jsm_get_heartbeat(vdev, args->index, >value);
+ break;
+ case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
+ args->value =
(u64)atomic64_inc_return(>unique_id_counter);
+ break;
+ case DRM_IVPU_PARAM_TILE_CONFIG:
+ args->value = vdev->hw->tile_fuse;
+ break;
+ case DRM_IVPU_PARAM_SKU:
+ args->value = vdev->hw->sku;
+ break;
default:
ret = -EINVAL;
}
@@ -197,6 +226,70 @@ static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
DEFINE_DRM_GEM_FOPS(ivpu_fops);
+static int ivpu_wait_for_ready(struct ivpu_device *vdev)
+{
+ struct ivpu_ipc_consumer cons;
+ struct ivpu_ipc_hdr ipc_hdr;
+ unsigned long timeout;
+ int ret;
+
+ if (ivpu_test_mode == IVPU_TEST_MODE_FW_TEST)
+ return 0;
+
+ ivpu_ipc_consumer_add(vdev, , IVPU_IPC_CHAN_BOOT_MSG);
+
+ timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
+ while (1) {
+ if (ivpu_ipc_irq_handler(vdev) != IRQ_HANDLED) {
+ ret = -EIO;
+ break;
+ }
+ ret = ivpu_ipc_receive(vdev, , _hdr, NULL, 0);
+ if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
+ break;
+
+ cond_resched();
+ }
+
+ ivpu_ipc_consumer_del(vdev, );
+
+ if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
+ ivpu_err(vdev, "Invalid VPU ready message: 0x%x\n",
+ipc_hdr.data_addr);
+ return -EIO;
+ }
+
+ if (!ret)
+ ivpu_info(vdev, "VPU ready message received successfully\n");
+
+ return ret;
+}
+
+int ivpu_boot(struct ivpu_device *vdev)
+{
+ int ret;
+
+ /* Update boot params located at first 4KB of FW memory */
+ ivpu_fw_boot_params_setup(vdev, vdev->fw->mem->kvaddr);
+
+ ret = ivpu_hw_boot_fw(vdev);
+ if (ret) {
+ ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
+ return ret;
+ }
+
+ ret = ivpu_wait_for_ready(vdev);
+
[PATCH v3 4/7] drm/ivpu: Add IPC driver and JSM messages
The IPC driver is used to send and receive messages to/from firmware
running on the VPU.
The only supported IPC message format is Job Submission Model (JSM)
defined in vpu_jsm_api.h header.
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 2 +
drivers/gpu/drm/ivpu/ivpu_drv.c | 15 +
drivers/gpu/drm/ivpu/ivpu_drv.h | 2 +
drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 4 +
drivers/gpu/drm/ivpu/ivpu_ipc.c | 499 ++
drivers/gpu/drm/ivpu/ivpu_ipc.h | 90
drivers/gpu/drm/ivpu/ivpu_jsm_msg.c | 220 ++
drivers/gpu/drm/ivpu/ivpu_jsm_msg.h | 25 ++
drivers/gpu/drm/ivpu/vpu_jsm_api.h | 616
9 files changed, 1473 insertions(+)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_ipc.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_ipc.h
create mode 100644 drivers/gpu/drm/ivpu/ivpu_jsm_msg.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_jsm_msg.h
create mode 100644 drivers/gpu/drm/ivpu/vpu_jsm_api.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index 4053fe341d56..4e33860c0dc4 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -5,6 +5,8 @@ intel_vpu-y := \
ivpu_drv.o \
ivpu_gem.o \
ivpu_hw_mtl.o \
+ ivpu_ipc.o \
+ ivpu_jsm_msg.o \
ivpu_mmu.o \
ivpu_mmu_context.o
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index b0442e2a4960..b7e2bc54897a 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -16,6 +16,7 @@
#include "ivpu_drv.h"
#include "ivpu_gem.h"
#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
#include "ivpu_mmu.h"
#include "ivpu_mmu_context.h"
@@ -201,6 +202,7 @@ int ivpu_shutdown(struct ivpu_device *vdev)
int ret;
ivpu_hw_irq_disable(vdev);
+ ivpu_ipc_disable(vdev);
ivpu_mmu_disable(vdev);
ret = ivpu_hw_power_down(vdev);
@@ -318,6 +320,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
if (!vdev->mmu)
return -ENOMEM;
+ vdev->ipc = devm_kzalloc(vdev->drm.dev, sizeof(*vdev->ipc), GFP_KERNEL);
+ if (!vdev->ipc)
+ return -ENOMEM;
+
vdev->hw->ops = _hw_mtl_ops;
vdev->platform = IVPU_PLATFORM_INVALID;
@@ -361,8 +367,16 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
goto err_mmu_gctx_fini;
}
+ ret = ivpu_ipc_init(vdev);
+ if (ret) {
+ ivpu_err(vdev, "Failed to initialize IPC: %d\n", ret);
+ goto err_mmu_fini;
+ }
+
return 0;
+err_mmu_fini:
+ ivpu_mmu_fini(vdev);
err_mmu_gctx_fini:
ivpu_mmu_global_context_fini(vdev);
err_power_down:
@@ -378,6 +392,7 @@ static void ivpu_dev_fini(struct ivpu_device *vdev)
{
ivpu_shutdown(vdev);
+ ivpu_ipc_fini(vdev);
ivpu_mmu_fini(vdev);
ivpu_mmu_global_context_fini(vdev);
ivpu_irq_fini(vdev);
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.h b/drivers/gpu/drm/ivpu/ivpu_drv.h
index 6eec3eb76c2f..48e5ed442f71 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.h
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.h
@@ -73,6 +73,7 @@ struct ivpu_wa_table {
struct ivpu_hw_info;
struct ivpu_mmu_info;
+struct ivpu_ipc_info;
struct ivpu_device {
struct drm_device drm; /* Must be first */
@@ -84,6 +85,7 @@ struct ivpu_device {
struct ivpu_wa_table wa;
struct ivpu_hw_info *hw;
struct ivpu_mmu_info *mmu;
+ struct ivpu_ipc_info *ipc;
struct ivpu_mmu_context gctx;
struct xarray context_xa;
diff --git a/drivers/gpu/drm/ivpu/ivpu_hw_mtl.c
b/drivers/gpu/drm/ivpu/ivpu_hw_mtl.c
index 525b57c4029c..5e31aec36bfa 100644
--- a/drivers/gpu/drm/ivpu/ivpu_hw_mtl.c
+++ b/drivers/gpu/drm/ivpu/ivpu_hw_mtl.c
@@ -7,6 +7,7 @@
#include "ivpu_hw_mtl_reg.h"
#include "ivpu_hw_reg_io.h"
#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
#include "ivpu_mmu.h"
#define TILE_FUSE_ENABLE_BOTH 0x0
@@ -931,6 +932,9 @@ static irqreturn_t ivpu_hw_mtl_irqv_handler(struct
ivpu_device *vdev, int irq)
REGV_WR32(MTL_VPU_HOST_SS_ICB_CLEAR_0, status);
+ if (REG_TEST_FLD(MTL_VPU_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT,
status))
+ ret &= ivpu_ipc_irq_handler(vdev);
+
if (REG_TEST_FLD(MTL_VPU_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
ret &= ivpu_mmu_irq_evtq_handler(vdev);
diff --git a/drivers/gpu/drm/ivpu/ivpu_ipc.c b/drivers/gpu/drm/ivpu/ivpu_ipc.c
new file mode 100644
index ..9eac5d25f3ea
--- /dev/null
+++ b/drivers/gpu/drm/ivpu/ivpu_ipc.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2020-2022 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_reg_io.h"
+#include
[PATCH v3 6/7] drm/ivpu: Add command buffer submission logic
Each of the user contexts has two command queues, one for compute engine
and one for the copy engine. Command queues are allocated and registered
in the device when the first job (command buffer) is submitted from
the user space to the VPU device. The userspace provides a list of
GEM buffer object handles to submit to the VPU, the driver resolves
buffer handles, pins physical memory if needed, increments ref count
for each buffer and stores pointers to buffer objects in
the ivpu_job objects that track jobs submitted to the device.
The VPU signals job completion with an asynchronous message that
contains the job id passed to firmware when the job was submitted.
Currently, the driver supports simple scheduling logic
where jobs submitted from user space are immediately pushed
to the VPU device command queues. In the future, it will be
extended to use hardware base scheduling and/or drm_sched.
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 1 +
drivers/gpu/drm/ivpu/ivpu_drv.c | 26 +-
drivers/gpu/drm/ivpu/ivpu_drv.h | 6 +-
drivers/gpu/drm/ivpu/ivpu_gem.c | 13 +
drivers/gpu/drm/ivpu/ivpu_job.c | 617
drivers/gpu/drm/ivpu/ivpu_job.h | 73
include/uapi/drm/ivpu_drm.h | 96 +
7 files changed, 828 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_job.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_job.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index 8e9b3ae1a4cc..e87d8182c5c7 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -7,6 +7,7 @@ intel_vpu-y := \
ivpu_gem.o \
ivpu_hw_mtl.o \
ivpu_ipc.o \
+ ivpu_job.o \
ivpu_jsm_msg.o \
ivpu_mmu.o \
ivpu_mmu_context.o
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index 67384671092e..51e1f124139a 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -19,6 +19,7 @@
#include "ivpu_gem.h"
#include "ivpu_hw.h"
#include "ivpu_ipc.h"
+#include "ivpu_job.h"
#include "ivpu_jsm_msg.h"
#include "ivpu_mmu.h"
#include "ivpu_mmu_context.h"
@@ -78,8 +79,11 @@ static void file_priv_release(struct kref *ref)
ivpu_dbg(FILE, "file_priv release: ctx %u\n", file_priv->ctx.id);
- if (file_priv->ctx.id)
+ if (file_priv->ctx.id) {
+ ivpu_cmdq_release_all(file_priv);
+ ivpu_bo_remove_all_bos_from_context(_priv->ctx);
ivpu_mmu_user_context_fini(file_priv);
+ }
kfree(file_priv);
}
@@ -222,6 +226,8 @@ static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(IVPU_BO_USERPTR, ivpu_bo_userptr_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, DRM_RENDER_ALLOW),
};
DEFINE_DRM_GEM_FOPS(ivpu_fops);
@@ -428,6 +434,7 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
vdev->context_xa_limit.min = IVPU_GLOBAL_CONTEXT_MMU_SSID + 1;
vdev->context_xa_limit.max = IVPU_CONTEXT_LIMIT;
+ xa_init_flags(>submitted_jobs_xa, XA_FLAGS_ALLOC1);
atomic64_set(>unique_id_counter, 0);
ret = ivpu_pci_init(vdev);
@@ -478,20 +485,30 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
goto err_fw_fini;
}
+ ret = ivpu_job_done_thread_init(vdev);
+ if (ret) {
+ ivpu_err(vdev, "Failed to initialize job done thread: %d\n",
ret);
+ goto err_ipc_fini;
+ }
+
ret = ivpu_fw_load(vdev);
if (ret) {
ivpu_err(vdev, "Failed to load firmware: %d\n", ret);
- goto err_fw_fini;
+ goto err_job_done_thread_fini;
}
ret = ivpu_boot(vdev);
if (ret) {
ivpu_err(vdev, "Failed to boot: %d\n", ret);
- goto err_fw_fini;
+ goto err_job_done_thread_fini;
}
return 0;
+err_job_done_thread_fini:
+ ivpu_job_done_thread_fini(vdev);
+err_ipc_fini:
+ ivpu_ipc_fini(vdev);
err_fw_fini:
ivpu_fw_fini(vdev);
err_mmu_fini:
@@ -511,6 +528,7 @@ static void ivpu_dev_fini(struct ivpu_device *vdev)
{
ivpu_shutdown(vdev);
+ ivpu_job_done_thread_fini(vdev);
ivpu_ipc_fini(vdev);
ivpu_fw_fini(vdev);
ivpu_mmu_fini(vdev);
@@ -520,6 +538,8 @@ static void ivpu_dev_fini(struct ivpu_device *vdev)
WARN_ON(!xa_empty(>context_xa));
xa_destroy(>context_xa);
+ WARN_ON(!xa_empty(>submitted_jobs_xa));
+ xa_destroy(>submitted_jobs_xa);
}
static struct pci_device_id ivpu_pci_ids[] = {
diff --git
[PATCH v3 2/7] drm/ivpu: Add Intel VPU MMU support
VPU Memory Management Unit is based on ARM MMU-600.
It allows to create multiple virtual address spaces for the device and
map noncontinuous host memory (there is no dedicated memory on the VPU).
Address space is implemented as a struct ivpu_mmu_context, it has an ID,
drm_mm allocator for VPU addresses and struct ivpu_mmu_pgtable that holds
actual 3-level, 4KB page table.
Context with ID 0 (global context) is created upon driver initialization
and it's mainly used for mapping memory required to execute
the firmware.
Contexts with non-zero IDs are user contexts allocated each time
the devices is open()-ed and they map command buffers and other
workload-related memory.
Workloads executing in a given contexts have access only
to the memory mapped in this context.
This patch is has to main files:
- ivpu_mmu_context.c handles MMU page tables and memory mapping
- ivpu_mmu.c implements a driver that programs the MMU device
Signed-off-by: Karol Wachowski
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 4 +-
drivers/gpu/drm/ivpu/ivpu_drv.c | 59 +-
drivers/gpu/drm/ivpu/ivpu_drv.h | 7 +
drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 10 +
drivers/gpu/drm/ivpu/ivpu_mmu.c | 883
drivers/gpu/drm/ivpu/ivpu_mmu.h | 53 ++
drivers/gpu/drm/ivpu/ivpu_mmu_context.c | 419 +++
drivers/gpu/drm/ivpu/ivpu_mmu_context.h | 49 ++
include/uapi/drm/ivpu_drm.h | 4 +
9 files changed, 1485 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu.h
create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu_context.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu_context.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index e59dc65abe6a..95bb04f26296 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -3,6 +3,8 @@
intel_vpu-y := \
ivpu_drv.o \
- ivpu_hw_mtl.o
+ ivpu_hw_mtl.o \
+ ivpu_mmu.o \
+ ivpu_mmu_context.o
obj-$(CONFIG_DRM_IVPU) += intel_vpu.o
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index a01c7244f6e5..cbeb9a801a31 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -14,6 +14,8 @@
#include "ivpu_drv.h"
#include "ivpu_hw.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
#ifndef DRIVER_VERSION_STR
#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
@@ -50,6 +52,11 @@ char *ivpu_platform_to_str(u32 platform)
void ivpu_file_priv_get(struct ivpu_file_priv *file_priv, struct
ivpu_file_priv **link)
{
+ struct ivpu_device *vdev = file_priv->vdev;
+
+ ivpu_dbg(KREF, "file_priv get: ctx %u refcount %u\n",
+file_priv->ctx.id, kref_read(_priv->ref));
+
kref_get(_priv->ref);
*link = file_priv;
}
@@ -57,6 +64,12 @@ void ivpu_file_priv_get(struct ivpu_file_priv *file_priv,
struct ivpu_file_priv
static void file_priv_release(struct kref *ref)
{
struct ivpu_file_priv *file_priv = container_of(ref, struct
ivpu_file_priv, ref);
+ struct ivpu_device *vdev = file_priv->vdev;
+
+ ivpu_dbg(FILE, "file_priv release: ctx %u\n", file_priv->ctx.id);
+
+ if (file_priv->ctx.id)
+ ivpu_mmu_user_context_fini(file_priv);
kfree(file_priv);
}
@@ -64,6 +77,10 @@ static void file_priv_release(struct kref *ref)
void ivpu_file_priv_put(struct ivpu_file_priv **link)
{
struct ivpu_file_priv *file_priv = *link;
+ struct ivpu_device *vdev = file_priv->vdev;
+
+ ivpu_dbg(KREF, "file_priv put: ctx %u refcount %u\n",
+file_priv->ctx.id, kref_read(_priv->ref));
*link = NULL;
kref_put(_priv->ref, file_priv_release);
@@ -75,7 +92,11 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void
*data, struct drm_f
struct ivpu_device *vdev = file_priv->vdev;
struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
struct drm_ivpu_param *args = data;
- int ret = 0;
+ int ret;
+
+ ret = ivpu_mmu_user_context_init(file_priv);
+ if (ret)
+ return ret;
switch (args->param) {
case DRM_IVPU_PARAM_DEVICE_ID:
@@ -99,6 +120,9 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void
*data, struct drm_f
case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
args->value = file_priv->priority;
break;
+ case DRM_IVPU_PARAM_CONTEXT_ID:
+ args->value = file_priv->ctx.id;
+ break;
default:
ret = -EINVAL;
}
@@ -110,7 +134,11 @@ static int ivpu_set_param_ioctl(struct drm_device *dev,
void *data, struct drm_f
{
struct ivpu_file_priv *file_priv = file->driver_priv;
struct drm_ivpu_param *args = data;
- int ret = 0;
+ int
[PATCH v3 7/7] drm/ivpu: Add PM support
- Implement cold and warm firmware boot flows
- Add hang recovery support
- Add runtime power management support
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 3 +-
drivers/gpu/drm/ivpu/ivpu_drv.c| 34 ++-
drivers/gpu/drm/ivpu/ivpu_drv.h| 2 +
drivers/gpu/drm/ivpu/ivpu_fw.c | 4 +
drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 16 +-
drivers/gpu/drm/ivpu/ivpu_ipc.c| 11 +-
drivers/gpu/drm/ivpu/ivpu_job.c| 14 +-
drivers/gpu/drm/ivpu/ivpu_mmu.c| 7 +-
drivers/gpu/drm/ivpu/ivpu_pm.c | 352 +
drivers/gpu/drm/ivpu/ivpu_pm.h | 38
10 files changed, 475 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_pm.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_pm.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index e87d8182c5c7..c17e4a25f751 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -10,6 +10,7 @@ intel_vpu-y := \
ivpu_job.o \
ivpu_jsm_msg.o \
ivpu_mmu.o \
- ivpu_mmu_context.o
+ ivpu_mmu_context.o \
+ ivpu_pm.o
obj-$(CONFIG_DRM_IVPU) += intel_vpu.o
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index 51e1f124139a..c31ce1bbc5be 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -23,6 +23,7 @@
#include "ivpu_jsm_msg.h"
#include "ivpu_mmu.h"
#include "ivpu_mmu_context.h"
+#include "ivpu_pm.h"
#ifndef DRIVER_VERSION_STR
#define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
@@ -80,9 +81,11 @@ static void file_priv_release(struct kref *ref)
ivpu_dbg(FILE, "file_priv release: ctx %u\n", file_priv->ctx.id);
if (file_priv->ctx.id) {
+ ivpu_rpm_get(vdev);
ivpu_cmdq_release_all(file_priv);
ivpu_bo_remove_all_bos_from_context(_priv->ctx);
ivpu_mmu_user_context_fini(file_priv);
+ ivpu_rpm_put(vdev);
}
kfree(file_priv);
@@ -273,6 +276,7 @@ static int ivpu_wait_for_ready(struct ivpu_device *vdev)
int ivpu_boot(struct ivpu_device *vdev)
{
+ struct ivpu_pm_info *pm = vdev->pm;
int ret;
/* Update boot params located at first 4KB of FW memory */
@@ -290,6 +294,7 @@ int ivpu_boot(struct ivpu_device *vdev)
return ret;
}
+ atomic_set(>in_recovery, 0);
ivpu_hw_irq_clear(vdev);
ivpu_hw_irq_enable(vdev);
ivpu_ipc_enable(vdev);
@@ -427,6 +432,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
if (!vdev->ipc)
return -ENOMEM;
+ vdev->pm = devm_kzalloc(vdev->drm.dev, sizeof(*vdev->pm), GFP_KERNEL);
+ if (!vdev->pm)
+ return -ENOMEM;
+
vdev->hw->ops = _hw_mtl_ops;
vdev->platform = IVPU_PLATFORM_INVALID;
@@ -485,10 +494,16 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
goto err_fw_fini;
}
+ ret = ivpu_pm_init(vdev);
+ if (ret) {
+ ivpu_err(vdev, "Failed to initialize PM: %d\n", ret);
+ goto err_ipc_fini;
+ }
+
ret = ivpu_job_done_thread_init(vdev);
if (ret) {
ivpu_err(vdev, "Failed to initialize job done thread: %d\n",
ret);
- goto err_ipc_fini;
+ goto err_pm_fini;
}
ret = ivpu_fw_load(vdev);
@@ -507,6 +522,8 @@ static int ivpu_dev_init(struct ivpu_device *vdev)
err_job_done_thread_fini:
ivpu_job_done_thread_fini(vdev);
+err_pm_fini:
+ ivpu_pm_fini(vdev);
err_ipc_fini:
ivpu_ipc_fini(vdev);
err_fw_fini:
@@ -529,6 +546,7 @@ static void ivpu_dev_fini(struct ivpu_device *vdev)
ivpu_shutdown(vdev);
ivpu_job_done_thread_fini(vdev);
+ ivpu_pm_fini(vdev);
ivpu_ipc_fini(vdev);
ivpu_fw_fini(vdev);
ivpu_mmu_fini(vdev);
@@ -583,11 +601,25 @@ static void ivpu_remove(struct pci_dev *pdev)
ivpu_dev_fini(vdev);
}
+static const struct dev_pm_ops ivpu_drv_pci_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
+ SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb,
ivpu_pm_runtime_resume_cb, NULL)
+};
+
+static const struct pci_error_handlers ivpu_drv_pci_err = {
+ .reset_prepare = ivpu_pm_reset_prepare_cb,
+ .reset_done = ivpu_pm_reset_done_cb,
+};
+
static struct pci_driver ivpu_pci_driver = {
.name = KBUILD_MODNAME,
.id_table = ivpu_pci_ids,
.probe = ivpu_probe,
.remove = ivpu_remove,
+ .driver = {
+ .pm = _drv_pci_pm,
+ },
+ .err_handler = _drv_pci_err,
};
static __init int ivpu_init(void)
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.h b/drivers/gpu/drm/ivpu/ivpu_drv.h
index 59544b3efec8..57f87e0a62c8 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.h
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.h
@@
[PATCH v3 3/7] drm/ivpu: Add GEM buffer object management
Adds four types of GEM-based BOs for the VPU:
- shmem
- userptr
- internal
- prime
All types are implemented as struct ivpu_bo, based on
struct drm_gem_object. VPU address is allocated when buffer is created
except for imported prime buffers that allocate it in BO_INFO IOCTL due
to missing file_priv arg in gem_prime_import callback.
Internal buffers are pinned on creation, the rest of buffers types
can be pinned on demand (in SUBMIT IOCTL).
Buffer VPU address, allocated pages and mappings are relased when the
buffer is destroyed.
Eviction mechism is planned for future versions.
Add three new IOCTLs: BO_CREATE, BO_INFO, BO_USERPTR
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 1 +
drivers/gpu/drm/ivpu/ivpu_drv.c | 9 +
drivers/gpu/drm/ivpu/ivpu_gem.c | 823
drivers/gpu/drm/ivpu/ivpu_gem.h | 128 +
include/uapi/drm/ivpu_drm.h | 127 +
5 files changed, 1088 insertions(+)
create mode 100644 drivers/gpu/drm/ivpu/ivpu_gem.c
create mode 100644 drivers/gpu/drm/ivpu/ivpu_gem.h
diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile
index 95bb04f26296..4053fe341d56 100644
--- a/drivers/gpu/drm/ivpu/Makefile
+++ b/drivers/gpu/drm/ivpu/Makefile
@@ -3,6 +3,7 @@
intel_vpu-y := \
ivpu_drv.o \
+ ivpu_gem.o \
ivpu_hw_mtl.o \
ivpu_mmu.o \
ivpu_mmu_context.o
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.c b/drivers/gpu/drm/ivpu/ivpu_drv.c
index cbeb9a801a31..b0442e2a4960 100644
--- a/drivers/gpu/drm/ivpu/ivpu_drv.c
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.c
@@ -11,8 +11,10 @@
#include
#include
#include
+#include
#include "ivpu_drv.h"
+#include "ivpu_gem.h"
#include "ivpu_hw.h"
#include "ivpu_mmu.h"
#include "ivpu_mmu_context.h"
@@ -187,6 +189,9 @@ static void ivpu_postclose(struct drm_device *dev, struct
drm_file *file)
static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(IVPU_BO_USERPTR, ivpu_bo_userptr_ioctl,
DRM_RENDER_ALLOW),
};
DEFINE_DRM_GEM_FOPS(ivpu_fops);
@@ -210,6 +215,10 @@ static const struct drm_driver driver = {
.open = ivpu_open,
.postclose = ivpu_postclose,
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_import = ivpu_gem_prime_import,
+ .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/ivpu/ivpu_gem.c b/drivers/gpu/drm/ivpu/ivpu_gem.c
new file mode 100644
index ..54319a25c18e
--- /dev/null
+++ b/drivers/gpu/drm/ivpu/ivpu_gem.c
@@ -0,0 +1,823 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2020-2022 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
+
+MODULE_IMPORT_NS(DMA_BUF);
+
+static const struct drm_gem_object_funcs ivpu_gem_funcs;
+
+static int __must_check prime_alloc_pages_locked(struct ivpu_bo *bo)
+{
+ /* Pages are managed by the underlying dma-buf */
+ return 0;
+}
+
+static void prime_free_pages_locked(struct ivpu_bo *bo)
+{
+ /* Pages are managed by the underlying dma-buf */
+}
+
+static int prime_map_pages_locked(struct ivpu_bo *bo)
+{
+ struct ivpu_device *vdev = ivpu_bo_to_vdev(bo);
+ struct sg_table *sgt;
+
+ WARN_ON(!bo->base.import_attach);
+
+ sgt = dma_buf_map_attachment(bo->base.import_attach, DMA_BIDIRECTIONAL);
+ if (IS_ERR(sgt)) {
+ ivpu_err(vdev, "Failed to map attachment: %ld\n", PTR_ERR(sgt));
+ return PTR_ERR(sgt);
+ }
+
+ bo->sgt = sgt;
+ return 0;
+}
+
+static void prime_unmap_pages_locked(struct ivpu_bo *bo)
+{
+ WARN_ON(!bo->base.import_attach);
+
+ dma_buf_unmap_attachment(bo->base.import_attach, bo->sgt,
DMA_BIDIRECTIONAL);
+ bo->sgt = NULL;
+}
+
+static const struct ivpu_bo_ops prime_ops = {
+ .type = IVPU_BO_TYPE_PRIME,
+ .name = "prime",
+ .alloc_pages = prime_alloc_pages_locked,
+ .free_pages = prime_free_pages_locked,
+ .map_pages = prime_map_pages_locked,
+ .unmap_pages = prime_unmap_pages_locked,
+};
+
+static int __must_check shmem_alloc_pages_locked(struct ivpu_bo *bo)
+{
+ int npages = bo->base.size >> PAGE_SHIFT;
+ struct page **pages;
+
+ pages = drm_gem_get_pages(>base);
+ if (IS_ERR(pages))
+ return PTR_ERR(pages);
+
+ if
[PATCH v3 1/7] drm/ivpu: Introduce a new DRM driver for Intel VPU
VPU stands for Versatile Processing Unit and it's a CPU-integrated inference accelerator for Computer Vision and Deep Learning applications. The VPU device consist of following componensts: - Buttress - provides CPU to VPU integration, interrupt, frequency and power management. - Memory Management Unit (based on ARM MMU-600) - translates VPU to host DMA addresses, isolates user workloads. - RISC based microcontroller - executes firmware that provides job execution API for the kernel-mode driver - Neural Compute Subsystem (NCS) - does the actual work, provides Compute and Copy engines. - Network on Chip (NoC) - network fabric connecting all the components This driver supports VPU IP v2.7 integrated into Intel Meteor Lake client CPUs (14th generation). Module sources are at drivers/gpu/drm/ivpu and module name is "intel_vpu.ko". This patch includes only very besic functionality: - module, PCI device and IRQ initialization - register definitions and low level register manipulation functions - SET/GET_PARAM ioctls - power up without firmware Signed-off-by: Krystian Pradzynski Signed-off-by: Jacek Lawrynowicz --- MAINTAINERS|8 + drivers/gpu/drm/Kconfig|2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/ivpu/Kconfig | 12 + drivers/gpu/drm/ivpu/Makefile |8 + drivers/gpu/drm/ivpu/TODO |7 + drivers/gpu/drm/ivpu/ivpu_drv.c| 392 + drivers/gpu/drm/ivpu/ivpu_drv.h| 153 drivers/gpu/drm/ivpu/ivpu_hw.h | 169 drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 1021 drivers/gpu/drm/ivpu/ivpu_hw_mtl_reg.h | 468 +++ drivers/gpu/drm/ivpu/ivpu_hw_reg_io.h | 115 +++ include/uapi/drm/ivpu_drm.h| 95 +++ 13 files changed, 2451 insertions(+) create mode 100644 drivers/gpu/drm/ivpu/Kconfig create mode 100644 drivers/gpu/drm/ivpu/Makefile create mode 100644 drivers/gpu/drm/ivpu/TODO create mode 100644 drivers/gpu/drm/ivpu/ivpu_drv.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_drv.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_mtl.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_mtl_reg.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_reg_io.h create mode 100644 include/uapi/drm/ivpu_drm.h diff --git a/MAINTAINERS b/MAINTAINERS index 9475aa701a3f..d72ceef107e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7046,6 +7046,14 @@ F: Documentation/devicetree/bindings/gpu/vivante,gc.yaml F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h +DRM DRIVERS FOR VPU +M: Jacek Lawrynowicz +M: Stanislaw Gruszka +S: Supported +T: git git://anongit.freedesktop.org/drm/drm-misc +F: drivers/gpu/drm/ivpu/ +F: include/uapi/drm/ivpu_drm.h + DRM DRIVERS FOR XEN M: Oleksandr Andrushchenko L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 198ba846d34b..0aaac0e5366f 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -364,6 +364,8 @@ source "drivers/gpu/drm/v3d/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" +source "drivers/gpu/drm/ivpu/Kconfig" + source "drivers/gpu/drm/etnaviv/Kconfig" source "drivers/gpu/drm/hisilicon/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 25d0ba310509..1bfd7415c2d0 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -94,6 +94,7 @@ obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb/ obj-$(CONFIG_DRM_MGAG200) += mgag200/ obj-$(CONFIG_DRM_V3D) += v3d/ obj-$(CONFIG_DRM_VC4) += vc4/ +obj-$(CONFIG_DRM_IVPU) += ivpu/ obj-$(CONFIG_DRM_SIS) += sis/ obj-$(CONFIG_DRM_SAVAGE)+= savage/ obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/ diff --git a/drivers/gpu/drm/ivpu/Kconfig b/drivers/gpu/drm/ivpu/Kconfig new file mode 100644 index ..30af359c52f2 --- /dev/null +++ b/drivers/gpu/drm/ivpu/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_IVPU + tristate "Intel VPU for Meteor Lake and newer" + depends on DRM + depends on X86_64 && PCI + select SHMEM + help + Choose this option if you have a system that has an 14th generation Intel CPU + or newer. VPU stands for Versatile Processing Unit and it's a CPU-integrated + inference accelerator for Computer Vision and Deep Learning applications. + + If "M" is selected, the module will be called intel_vpu. diff --git a/drivers/gpu/drm/ivpu/Makefile b/drivers/gpu/drm/ivpu/Makefile new file mode 100644 index ..e59dc65abe6a --- /dev/null +++ b/drivers/gpu/drm/ivpu/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright © 2022 Intel Corporation + +intel_vpu-y := \ + ivpu_drv.o \ + ivpu_hw_mtl.o + +obj-$(CONFIG_DRM_IVPU) += intel_vpu.o diff --git
[PATCH v3 RESEND 0/7] New DRM driver for Intel VPU
Hi, This patchset contains a new Linux* Kernel Driver for Intel® VPUs. VPU stands for Versatile Processing Unit and it is an AI inference accelerator integrated with Intel non-server CPUs starting from 14th generation. VPU enables efficient execution of Deep Learning applications like object detection, classification etc. Driver is part of gpu/drm subsystem because VPU is similar in operation to an integrated GPU. Reusing drm driver init, ioctl handling, gem and prime helpers and drm_mm allows to minimize code duplication in the kernel. The whole driver is licensed under GPL-2.0-only except for two headers imported from the firmware that are MIT licensed. User mode driver stack consists of Level Zero API driver and OpenVINO plugin. Both should be open-sourced by the end of Q4. The firmware for the VPU will be distributed as a closed source binary. I'm resending v3 patchset with correct Dave's email. Regards, Jacek v3: - Fixed alignment warning in ivpu_ipc.c when building with W=1 v2: https://lore.kernel.org/all/20220913121017.993825-1-jacek.lawrynow...@linux.intel.com/ - Rename the driver from "drm/vpu" to "drm/ivpu" - Add a TODO file - Add support for WC buffers v1: https://lore.kernel.org/all/20220728131709.1087188-1-jacek.lawrynow...@linux.intel.com/ Jacek Lawrynowicz (7): drm/ivpu: Introduce a new DRM driver for Intel VPU drm/ivpu: Add Intel VPU MMU support drm/ivpu: Add GEM buffer object management drm/ivpu: Add IPC driver and JSM messages drm/ivpu: Implement firmware parsing and booting drm/ivpu: Add command buffer submission logic drm/ivpu: Add PM support MAINTAINERS |8 + drivers/gpu/drm/Kconfig |2 + drivers/gpu/drm/Makefile|1 + drivers/gpu/drm/ivpu/Kconfig| 12 + drivers/gpu/drm/ivpu/Makefile | 16 + drivers/gpu/drm/ivpu/TODO |7 + drivers/gpu/drm/ivpu/ivpu_drv.c | 643 ++ drivers/gpu/drm/ivpu/ivpu_drv.h | 178 drivers/gpu/drm/ivpu/ivpu_fw.c | 426 + drivers/gpu/drm/ivpu/ivpu_fw.h | 38 + drivers/gpu/drm/ivpu/ivpu_gem.c | 836 ++ drivers/gpu/drm/ivpu/ivpu_gem.h | 128 +++ drivers/gpu/drm/ivpu/ivpu_hw.h | 169 drivers/gpu/drm/ivpu/ivpu_hw_mtl.c | 1060 +++ drivers/gpu/drm/ivpu/ivpu_hw_mtl_reg.h | 468 ++ drivers/gpu/drm/ivpu/ivpu_hw_reg_io.h | 115 +++ drivers/gpu/drm/ivpu/ivpu_ipc.c | 508 +++ drivers/gpu/drm/ivpu/ivpu_ipc.h | 90 ++ drivers/gpu/drm/ivpu/ivpu_job.c | 629 ++ drivers/gpu/drm/ivpu/ivpu_job.h | 73 ++ drivers/gpu/drm/ivpu/ivpu_jsm_msg.c | 220 + drivers/gpu/drm/ivpu/ivpu_jsm_msg.h | 25 + drivers/gpu/drm/ivpu/ivpu_mmu.c | 888 +++ drivers/gpu/drm/ivpu/ivpu_mmu.h | 53 ++ drivers/gpu/drm/ivpu/ivpu_mmu_context.c | 419 + drivers/gpu/drm/ivpu/ivpu_mmu_context.h | 49 ++ drivers/gpu/drm/ivpu/ivpu_pm.c | 352 drivers/gpu/drm/ivpu/ivpu_pm.h | 38 + drivers/gpu/drm/ivpu/vpu_boot_api.h | 241 ++ drivers/gpu/drm/ivpu/vpu_jsm_api.h | 616 + include/uapi/drm/ivpu_drm.h | 343 31 files changed, 8651 insertions(+) create mode 100644 drivers/gpu/drm/ivpu/Kconfig create mode 100644 drivers/gpu/drm/ivpu/Makefile create mode 100644 drivers/gpu/drm/ivpu/TODO create mode 100644 drivers/gpu/drm/ivpu/ivpu_drv.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_drv.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_fw.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_fw.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_gem.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_gem.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_mtl.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_mtl_reg.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_hw_reg_io.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_ipc.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_ipc.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_job.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_job.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_jsm_msg.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_jsm_msg.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu_context.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_mmu_context.h create mode 100644 drivers/gpu/drm/ivpu/ivpu_pm.c create mode 100644 drivers/gpu/drm/ivpu/ivpu_pm.h create mode 100644 drivers/gpu/drm/ivpu/vpu_boot_api.h create mode 100644 drivers/gpu/drm/ivpu/vpu_jsm_api.h create mode 100644 include/uapi/drm/ivpu_drm.h -- 2.34.1
[PATCH] dt-bindings: display/msm: convert MDP5 schema to YAML format
Convert the mdp5.txt into the yaml format. Changes to the existing (txt) schema:
- MSM8996 has additional "iommu" clock, define it separately
- Add new properties used on some of platforms:
- interconnects, interconnect-names
- iommus
- power-domains
- operating-points-v2, opp-table
Signed-off-by: Dmitry Baryshkov
---
Dependency:
https://lore.kernel.org/linux-arm-msm/20220924123611.225520-2-dmitry.barysh...@linaro.org/
---
.../devicetree/bindings/display/msm/mdp5.txt | 132 -
.../bindings/display/msm/qcom,mdp5.yaml | 137 ++
2 files changed, 137 insertions(+), 132 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/mdp5.txt
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt
b/Documentation/devicetree/bindings/display/msm/mdp5.txt
deleted file mode 100644
index 65d03c58dee6..
--- a/Documentation/devicetree/bindings/display/msm/mdp5.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-Qualcomm adreno/snapdragon MDP5 display controller
-
-Description:
-
-This is the bindings documentation for the MDP5 display
-controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
-
-MDP5:
-Required properties:
-- compatible:
- * "qcom,mdp5" - MDP5
-- reg: Physical base address and length of the controller's registers.
-- reg-names: The names of register regions. The following regions are required:
- * "mdp_phys"
-- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
-- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required.
-- * "bus"
-- * "iface"
-- * "core"
-- * "vsync"
-- ports: contains the list of output ports from MDP. These connect to
interfaces
- that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
- special case since it is a part of the MDP block itself).
-
- Each output port contains an endpoint that describes how it is connected to
an
- external interface. These are described by the standard properties documented
- here:
- Documentation/devicetree/bindings/graph.txt
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
- The availability of output ports can vary across SoC revisions:
-
- For MSM8974 and APQ8084:
-Port 0 -> MDP_INTF0 (eDP)
-Port 1 -> MDP_INTF1 (DSI1)
-Port 2 -> MDP_INTF2 (DSI2)
-Port 3 -> MDP_INTF3 (HDMI)
-
- For MSM8916:
-Port 0 -> MDP_INTF1 (DSI1)
-
- For MSM8994 and MSM8996:
-Port 0 -> MDP_INTF1 (DSI1)
-Port 1 -> MDP_INTF2 (DSI2)
-Port 2 -> MDP_INTF3 (HDMI)
-
-Optional properties:
-- clock-names: the following clocks are optional:
- * "lut"
- * "tbu"
- * "tbu_rt"
-
-Example:
-
-/ {
- ...
-
- mdss: mdss@1a0 {
- compatible = "qcom,mdss";
- reg = <0x1a0 0x1000>,
- <0x1ac8000 0x3000>;
- reg-names = "mdss_phys", "vbif_phys";
-
- power-domains = < MDSS_GDSC>;
-
- clocks = < GCC_MDSS_AHB_CLK>,
-< GCC_MDSS_AXI_CLK>,
-< GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "vsync"
-
- interrupts = <0 72 0>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mdp: mdp@1a01000 {
- compatible = "qcom,mdp5";
- reg = <0x1a01000 0x9>;
- reg-names = "mdp_phys";
-
- interrupt-parent = <>;
- interrupts = <0 0>;
-
- clocks = < GCC_MDSS_AHB_CLK>,
-< GCC_MDSS_AXI_CLK>,
-< GCC_MDSS_MDP_CLK>,
-< GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "core",
- "vsync";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <_in>;
- };
- };
- };
- };
-
- dsi0: dsi@1a98000 {
- ...
- ports {
- ...
- port@0 {
-
Re: [PATCH v3 2/2] drm/msm/dsi: Add phy configuration for QCM2290
On 24.09.2022 14:19, Dmitry Baryshkov wrote:
> From: Loic Poulain
>
> The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not
> fully compatible with the standard 14nm PHY, so it requires a separate
> compatible and config entry.
>
> Signed-off-by: Loic Poulain
> [DB: rebased and updated commit msg]
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
(sorry I didn't notice earlier that there was a v2)
Konrad
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
> 3 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 7fc0975cb869..ee6051367679 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
> { .compatible = "qcom,dsi-phy-14nm",
> .data = _phy_14nm_cfgs },
> + { .compatible = "qcom,dsi-phy-14nm-2290",
> + .data = _phy_14nm_2290_cfgs },
> { .compatible = "qcom,dsi-phy-14nm-660",
> .data = _phy_14nm_660_cfgs },
> { .compatible = "qcom,dsi-phy-14nm-8953",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 60a99c6525b2..1096afedd616 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 0f8f4ca46429..9f488adea7f5 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
> .io_start = { 0x1a94400, 0x1a96400 },
> .num_dsi_phy = 2,
> };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
> + .has_phy_lane = true,
> + .regulator_data = dsi_phy_14nm_17mA_regulators,
> + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
> + .ops = {
> + .enable = dsi_14nm_phy_enable,
> + .disable = dsi_14nm_phy_disable,
> + .pll_init = dsi_pll_14nm_init,
> + .save_pll_state = dsi_14nm_pll_save_state,
> + .restore_pll_state = dsi_14nm_pll_restore_state,
> + },
> + .min_pll_rate = VCO_MIN_RATE,
> + .max_pll_rate = VCO_MAX_RATE,
> + .io_start = { 0x5e94400 },
> + .num_dsi_phy = 1,
> +};
Re: [PATCH 2/2] arm64: dts: qcom: msm8996: change HDMI PHY node name to generic one
On 24.09.2022 11:43, Dmitry Baryshkov wrote:
> Change HDMI PHY node name from custom 'hdmi-phy' to the generic 'phy'.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index a7d0e5d68141..ed9863854904 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1144,7 +1144,7 @@ hdmi_in: endpoint {
> };
> };
>
> - hdmi_phy: hdmi-phy@9a0600 {
> + hdmi_phy: phy@9a0600 {
> #phy-cells = <0>;
> compatible = "qcom,hdmi-phy-8996";
> reg = <0x009a0600 0x1c4>,
Re: [PATCH 1/2] ARM: dts: qcom-apq8064: change HDMI PHY node name to generic one
On 24.09.2022 11:43, Dmitry Baryshkov wrote:
> Change HDMI PHY node names from custom 'hdmi-phy' to the generic 'phy'.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +-
> arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> index 0322cb88d448..497c4012a65b 100644
> --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
> @@ -361,7 +361,7 @@ endpoint {
> };
> };
>
> - hdmi-phy@4a00400 {
> + phy@4a00400 {
> status = "okay";
>
> core-vdda-supply = <_hdmi_switch>;
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
> b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 1b704c7ea890..58f239218639 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -1453,7 +1453,7 @@ hdmi_out: endpoint {
> };
> };
>
> - hdmi_phy: hdmi-phy@4a00400 {
> + hdmi_phy: phy@4a00400 {
> compatible = "qcom,hdmi-phy-8960";
> reg = <0x4a00400 0x60>,
> <0x4a00500 0x100>;
Re: [PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
On 24.09.2022 11:00, Dmitry Baryshkov wrote: > Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace > them with generic phy@ names. > > Dmitry Baryshkov (9): > ARM: dts: qcom-apq8064: change DSI PHY node name to generic one > ARM: dts: qcom-msm8974: change DSI PHY node name to generic one > arm64: dts: qcom: msm8916: change DSI PHY node name to generic one > arm64: dts: qcom: msm8996: change DSI PHY node name to generic one > arm64: dts: qcom: sc7180: change DSI PHY node name to generic one > arm64: dts: qcom: sdm630: change DSI PHY node name to generic one > arm64: dts: qcom: sdm660: change DSI PHY node name to generic one > arm64: dts: qcom: sdm845: change DSI PHY node name to generic one > arm64: dts: qcom: sm8250: change DSI PHY node name to generic one Reviewed-by: Konrad Dybcio for the entire series Konrad > > arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 2 +- > arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +- > arch/arm/boot/dts/qcom-msm8974.dtsi| 2 +- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- > 10 files changed, 13 insertions(+), 13 deletions(-) >
Re: [PATCH v2 2/2] drm/msm/dsi: Add phy configuration for QCM2290
On 24.09.2022 10:51, Dmitry Baryshkov wrote:
> From: Loic Poulain
>
> The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not
> fully compatible with the standard 14nm PHY, so it requires a separate
> compatible and config entry.
>
> Signed-off-by: Loic Poulain
> [DB: changed compat to follow the agreed scheme, rebased and updated commit
> msg]
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Konrad Dybcio
Konrad
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
> 3 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 7fc0975cb869..724d5fa0788a 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -553,6 +553,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = _phy_14nm_660_cfgs },
> { .compatible = "qcom,dsi-phy-14nm-8953",
> .data = _phy_14nm_8953_cfgs },
> + { .compatible = "qcom,qcm2290-dsi-phy-14nm",
> + .data = _phy_14nm_2290_cfgs },
> #endif
> #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
> { .compatible = "qcom,dsi-phy-10nm",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 60a99c6525b2..1096afedd616 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 0f8f4ca46429..9f488adea7f5 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
> .io_start = { 0x1a94400, 0x1a96400 },
> .num_dsi_phy = 2,
> };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
> + .has_phy_lane = true,
> + .regulator_data = dsi_phy_14nm_17mA_regulators,
> + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
> + .ops = {
> + .enable = dsi_14nm_phy_enable,
> + .disable = dsi_14nm_phy_disable,
> + .pll_init = dsi_pll_14nm_init,
> + .save_pll_state = dsi_14nm_pll_save_state,
> + .restore_pll_state = dsi_14nm_pll_restore_state,
> + },
> + .min_pll_rate = VCO_MIN_RATE,
> + .max_pll_rate = VCO_MAX_RATE,
> + .io_start = { 0x5e94400 },
> + .num_dsi_phy = 1,
> +};
[Bug 216525] amdgpu VM_L2_PROTECTION_FAULT_STATUS:0x00000000
https://bugzilla.kernel.org/show_bug.cgi?id=216525 --- Comment #1 from sander44 (ionut_n2...@yahoo.com) --- Created attachment 301863 --> https://bugzilla.kernel.org/attachment.cgi?id=301863=edit journalctl -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
[Bug 216525] New: amdgpu VM_L2_PROTECTION_FAULT_STATUS:0x00000000
https://bugzilla.kernel.org/show_bug.cgi?id=216525 Bug ID: 216525 Summary: amdgpu VM_L2_PROTECTION_FAULT_STATUS:0x Product: Drivers Version: 2.5 Kernel Version: 6.0.0-rc4 Hardware: AMD OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: ionut_n2...@yahoo.com Regression: No Hi Kernel Team, I notice today one issue with amdgpu driver. This driver is crashed, but within 40 seconds it is recovered and my display appears correctly. Output Error: [ 7706.167995] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168007] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f from IH client 0x1b (UTCL2) [ 7706.168014] amdgpu :04:00.0: amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00241051 [ 7706.168018] amdgpu :04:00.0: amdgpu: Faulty UTCL2 client ID: TCP (0x8) [ 7706.168022] amdgpu :04:00.0: amdgpu: MORE_FAULTS: 0x1 [ 7706.168024] amdgpu :04:00.0: amdgpu: WALKER_ERROR: 0x0 [ 7706.168028] amdgpu :04:00.0: amdgpu: PERMISSION_FAULTS: 0x5 [ 7706.168031] amdgpu :04:00.0: amdgpu: MAPPING_ERROR: 0x0 [ 7706.168033] amdgpu :04:00.0: amdgpu: RW: 0x1 [ 7706.168039] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168047] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f1000 from IH client 0x1b (UTCL2) [ 7706.168053] amdgpu :04:00.0: amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x [ 7706.168056] amdgpu :04:00.0: amdgpu: Faulty UTCL2 client ID: CB (0x0) [ 7706.168059] amdgpu :04:00.0: amdgpu: MORE_FAULTS: 0x0 [ 7706.168061] amdgpu :04:00.0: amdgpu: WALKER_ERROR: 0x0 [ 7706.168063] amdgpu :04:00.0: amdgpu: PERMISSION_FAULTS: 0x0 [ 7706.168064] amdgpu :04:00.0: amdgpu: MAPPING_ERROR: 0x0 [ 7706.168067] amdgpu :04:00.0: amdgpu: RW: 0x0 [ 7706.168070] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168075] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f from IH client 0x1b (UTCL2) [ 7706.168078] amdgpu :04:00.0: amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x [ 7706.168080] amdgpu :04:00.0: amdgpu: Faulty UTCL2 client ID: CB (0x0) [ 7706.168083] amdgpu :04:00.0: amdgpu: MORE_FAULTS: 0x0 [ 7706.168085] amdgpu :04:00.0: amdgpu: WALKER_ERROR: 0x0 [ 7706.168088] amdgpu :04:00.0: amdgpu: PERMISSION_FAULTS: 0x0 [ 7706.168090] amdgpu :04:00.0: amdgpu: MAPPING_ERROR: 0x0 [ 7706.168092] amdgpu :04:00.0: amdgpu: RW: 0x0 [ 7706.168094] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168099] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f from IH client 0x1b (UTCL2) [ 7706.168103] amdgpu :04:00.0: amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x [ 7706.168105] amdgpu :04:00.0: amdgpu: Faulty UTCL2 client ID: CB (0x0) [ 7706.168108] amdgpu :04:00.0: amdgpu: MORE_FAULTS: 0x0 [ 7706.168110] amdgpu :04:00.0: amdgpu: WALKER_ERROR: 0x0 [ 7706.168112] amdgpu :04:00.0: amdgpu: PERMISSION_FAULTS: 0x0 [ 7706.168115] amdgpu :04:00.0: amdgpu: MAPPING_ERROR: 0x0 [ 7706.168117] amdgpu :04:00.0: amdgpu: RW: 0x0 [ 7706.168119] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168124] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f from IH client 0x1b (UTCL2) [ 7706.168129] amdgpu :04:00.0: amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x [ 7706.168132] amdgpu :04:00.0: amdgpu: Faulty UTCL2 client ID: CB (0x0) [ 7706.168134] amdgpu :04:00.0: amdgpu: MORE_FAULTS: 0x0 [ 7706.168137] amdgpu :04:00.0: amdgpu: WALKER_ERROR: 0x0 [ 7706.168140] amdgpu :04:00.0: amdgpu: PERMISSION_FAULTS: 0x0 [ 7706.168143] amdgpu :04:00.0: amdgpu: MAPPING_ERROR: 0x0 [ 7706.168146] amdgpu :04:00.0: amdgpu: RW: 0x0 [ 7706.168149] amdgpu :04:00.0: amdgpu: [gfxhub0] no-retry page fault (src_id:0 ring:40 vmid:2 pasid:32773, for process yandex_browser pid 63982 thread yandex_bro:cs0 pid 64029) [ 7706.168155] amdgpu :04:00.0: amdgpu: in page starting at address 0x8001191f1000
Re: [PATCH v7 0/9] dyndbg: drm.debug adaptation
On Sun, Sep 11, 2022 at 11:28:43PM -0600, Jim Cromie wrote:
> hi Greg, Dan, Jason, DRM-folk,
>
> heres follow-up to V6:
> rebased on driver-core/driver-core-next for -v6 applied bits (thanks)
> rework drm_debug_enabled{_raw,_instrumented,} per Dan.
>
> It excludes:
> nouveau parts (immature)
> tracefs parts (I missed --to=Steve on v6)
> split _ddebug_site and de-duplicate experiment (way unready)
>
> IOW, its the remaining commits of V6 on which Dan gave his Reviewed-by.
>
> If these are good to apply, I'll rebase and repost the rest separately.
All now queued up, thanks.
greg k-h
Re: [PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
On 24/09/2022 12:29, Krzysztof Kozlowski wrote: On 24/09/2022 11:20, Dmitry Baryshkov wrote: On 24/09/2022 12:11, Krzysztof Kozlowski wrote: On 24/09/2022 11:00, Dmitry Baryshkov wrote: Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace them with generic phy@ names. Dmitry Baryshkov (9): ARM: dts: qcom-apq8064: change DSI PHY node name to generic one dsi-phy is similar to other generic names (usb-phy, ethernet-phy) [1] so it could stay. Is there particular need for this, like coming from DT schema? No, there is no requirement from the DT schema. However: 1) The resent qcom DT files already use just phy@ for most of PHY nodes 2) The recommended list mentions usb-phy/ethernet-phy, but not -phy, so I'd think that those two are mostly for backwards compatibility. 3) I liked the example of sc7280 which switched all MDSS PHYs to just phy@ (this includes DSI PHY, eDP PHY and, by extension, the HDMI PHY). Good explanation. If there is going to be resent/submit, please add it to cover letter. :) I hope, there will be no v2. For now I have included this explanation into the HDMI PHY counterpart. -- With best wishes Dmitry
[PATCH v8 09/12] dt-bindings: display/msm: split dpu-msm8998 into DPU and MDSS parts
In order to make the schema more readable, split dpu-msm8998 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/qcom,msm8998-dpu.yaml | 95 +++
...pu-msm8998.yaml => qcom,msm8998-mdss.yaml} | 47 ++---
2 files changed, 101 insertions(+), 41 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml
rename Documentation/devicetree/bindings/display/msm/{dpu-msm8998.yaml =>
qcom,msm8998-mdss.yaml} (69%)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml
new file mode 100644
index ..b02adba36e9e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for MSM8998 target
+
+maintainers:
+ - AngeloGioacchino Del Regno
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,msm8998-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for regdma register set
+ - description: Address offset and size for vbif register set
+ - description: Address offset and size for non-realtime vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: regdma
+ - const: vbif
+ - const: vbif_nrt
+
+ clocks:
+items:
+ - description: Display ahb clock
+ - description: Display axi clock
+ - description: Display mem-noc clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: mnoc
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+display-controller@c901000 {
+compatible = "qcom,msm8998-dpu";
+reg = <0x0c901000 0x8f000>,
+ <0x0c9a8e00 0xf0>,
+ <0x0c9b 0x2008>,
+ <0x0c9b8000 0x1040>;
+reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
+
+clocks = < MDSS_AHB_CLK>,
+ < MDSS_AXI_CLK>,
+ < MNOC_AHB_CLK>,
+ < MDSS_MDP_CLK>,
+ < MDSS_VSYNC_CLK>;
+clock-names = "iface", "bus", "mnoc", "core", "vsync";
+
+interrupt-parent = <>;
+interrupts = <0>;
+operating-points-v2 = <_opp_table>;
+power-domains = < MSM8998_VDDMX>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
similarity index 69%
rename from Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
rename to Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
index 67791dbc3b5d..192a832ef808 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
@@ -1,18 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
+$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display DPU dt properties for MSM8998 target
+title: Qualcomm MSM8998 Display MDSS
maintainers:
- AngeloGioacchino Del Regno
-description: |
+description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
- bindings of MDSS and DPU are mentioned for MSM8998 target.
+ bindings of MDSS are mentioned for MSM8998 target.
$ref: /schemas/display/msm/mdss-common.yaml#
@@ -39,44 +39,9 @@ properties:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
-$ref: /schemas/display/msm/dpu-common.yaml#
-description: Node containing the properties of DPU.
-unevaluatedProperties: false
-
properties:
compatible:
-items:
- - const: qcom,msm8998-dpu
-
- reg:
-items:
- - description: Address
[PATCH v8 12/12] dt-bindings: display/msm: add support for the display on SM8250
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8250 platform.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/mdss-common.yaml | 4 +-
.../bindings/display/msm/qcom,sm8250-dpu.yaml | 92 +
.../display/msm/qcom,sm8250-mdss.yaml | 330 ++
3 files changed, 424 insertions(+), 2 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
index 2a476bd0215e..27d7242657b2 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -27,11 +27,11 @@ properties:
clocks:
minItems: 2
-maxItems: 3
+maxItems: 4
clock-names:
minItems: 2
-maxItems: 3
+maxItems: 4
interrupts:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
new file mode 100644
index ..9ff8a265c85f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8250 Display DPU
+
+maintainers:
+ - Dmitry Baryshkov
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8250-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display ahb clock
+ - description: Display hf axi clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8250-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "iface", "bus", "core", "vsync";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM8250_MMCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+...
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
new file mode 100644
index ..0d3be5386b3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
@@ -0,0 +1,330 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8250 Display MDSS
+
+maintainers:
+ - Dmitry Baryshkov
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
+ bindings of MDSS are mentioned for SM8250 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8250-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+
[PATCH v8 11/12] dt-bindings: display/msm: add missing device nodes to mdss-* schemas
Add missing device nodes (DSI, PHYs, DP/eDP) to the existing MDSS
schemas.
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/qcom,msm8998-mdss.yaml| 153 +
.../display/msm/qcom,qcm2290-mdss.yaml| 81 +
.../display/msm/qcom,sc7180-mdss.yaml | 179 +++
.../display/msm/qcom,sc7280-mdss.yaml | 292 ++
.../display/msm/qcom,sdm845-mdss.yaml | 153 +
5 files changed, 858 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
index 192a832ef808..cf52ff77a41a 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
@@ -43,11 +43,24 @@ patternProperties:
compatible:
const: qcom,msm8998-dpu
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-10nm-8998
+
unevaluatedProperties: false
examples:
- |
#include
+#include
#include
#include
@@ -111,5 +124,145 @@ examples:
};
};
};
+
+dsi@c994000 {
+compatible = "qcom,mdss-dsi-ctrl";
+reg = <0x0c994000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <4>;
+
+clocks = < MDSS_BYTE0_CLK>,
+ < MDSS_BYTE0_INTF_CLK>,
+ < MDSS_PCLK0_CLK>,
+ < MDSS_ESC0_CLK>,
+ < MDSS_AHB_CLK>,
+ < MDSS_AXI_CLK>;
+clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+assigned-clocks = < BYTE0_CLK_SRC>, < PCLK0_CLK_SRC>;
+assigned-clock-parents = <_phy 0>, <_phy 1>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < MSM8998_VDDCX>;
+
+phys = <_phy>;
+phy-names = "dsi";
+
+#address-cells = <1>;
+#size-cells = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dsi0_in: endpoint {
+remote-endpoint = <_intf1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+dsi0_out: endpoint {
+};
+};
+};
+};
+
+dsi0_phy: phy@c994400 {
+compatible = "qcom,dsi-phy-10nm-8998";
+reg = <0x0c994400 0x200>,
+ <0x0c994600 0x280>,
+ <0x0c994a00 0x1e0>;
+reg-names = "dsi_phy",
+"dsi_phy_lane",
+"dsi_pll";
+
+#clock-cells = <1>;
+#phy-cells = <0>;
+
+clocks = < MDSS_AHB_CLK>,
+ < RPM_SMD_XO_CLK_SRC>;
+clock-names = "iface", "ref";
+
+vdds-supply = <_l1>;
+};
+
+dsi@c996000 {
+compatible = "qcom,mdss-dsi-ctrl";
+reg = <0x0c996000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <5>;
+
+clocks = < MDSS_BYTE1_CLK>,
+ < MDSS_BYTE1_INTF_CLK>,
+ < MDSS_PCLK1_CLK>,
+ < MDSS_ESC1_CLK>,
+ < MDSS_AHB_CLK>,
+ < MDSS_AXI_CLK>;
+clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+assigned-clocks = < BYTE1_CLK_SRC>, < PCLK1_CLK_SRC>;
+assigned-clock-parents = <_phy 0>, <_phy 1>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < MSM8998_VDDCX>;
+
+phys = <_phy>;
+phy-names = "dsi";
+
+#address-cells = <1>;
+#size-cells = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dsi1_in: endpoint {
+remote-endpoint = <_intf2_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+dsi1_out: endpoint {
+};
+};
+};
+};
+
+dsi1_phy: phy@c996400 {
+compatible = "qcom,dsi-phy-10nm-8998";
[PATCH v8 02/12] dt-bindings: display/msm: add gcc-bus clock to dpu-smd845
Add gcc-bus clock required for the SDM845 DPU device tree node. This
change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845:
move bus clock to mdp node for sdm845 target"), but was not reflected in
the schema.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-sdm845.yaml| 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
index 7d1037373175..3cb2ae336996 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -84,6 +84,7 @@ patternProperties:
clocks:
items:
+ - description: Display GCC bus clock
- description: Display ahb clock
- description: Display axi clock
- description: Display core clock
@@ -91,6 +92,7 @@ patternProperties:
clock-names:
items:
+ - const: gcc-bus
- const: iface
- const: bus
- const: core
@@ -183,11 +185,12 @@ examples:
<0x0aeb 0x2008>;
reg-names = "mdp", "vbif";
-clocks = < DISP_CC_MDSS_AHB_CLK>,
+clocks = < GCC_DISP_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_AXI_CLK>,
< DISP_CC_MDSS_MDP_CLK>,
< DISP_CC_MDSS_VSYNC_CLK>;
-clock-names = "iface", "bus", "core", "vsync";
+clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
interrupt-parent = <>;
interrupts = <0>;
--
2.35.1
[PATCH v8 07/12] dt-bindings: display/msm: split dpu-sc7280 into DPU and MDSS parts
In order to make the schema more readable, split dpu-sc7280 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7280.yaml | 162 --
.../bindings/display/msm/qcom,sc7280-dpu.yaml | 98 +++
.../display/msm/qcom,sc7280-mdss.yaml | 130 ++
3 files changed, 228 insertions(+), 162 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
deleted file mode 100644
index 01ff88c06c51..
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
+++ /dev/null
@@ -1,162 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
-%YAML 1.2
-$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DPU dt properties for SC7280
-
-maintainers:
- - Krishna Manikandan
-
-description: |
- Device tree bindings for MSM Mobile Display Subsystem (MDSS) that
encapsulates
- sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
- bindings of MDSS and DPU are mentioned for SC7280.
-
-$ref: /schemas/display/msm/mdss-common.yaml#
-
-properties:
- compatible:
-const: qcom,sc7280-mdss
-
- clocks:
-items:
- - description: Display AHB clock from gcc
- - description: Display AHB clock from dispcc
- - description: Display core clock
-
- clock-names:
-items:
- - const: iface
- - const: ahb
- - const: core
-
- iommus:
-maxItems: 1
-
- interconnects:
-maxItems: 1
-
- interconnect-names:
-maxItems: 1
-
-patternProperties:
- "^display-controller@[0-9a-f]+$":
-type: object
-$ref: /schemas/display/msm/dpu-common.yaml#
-description: Node containing the properties of DPU.
-unevaluatedProperties: false
-
-properties:
- compatible:
-const: qcom,sc7280-dpu
-
- reg:
-items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
-items:
- - const: mdp
- - const: vbif
-
- clocks:
-items:
- - description: Display hf axi clock
- - description: Display sf axi clock
- - description: Display ahb clock
- - description: Display lut clock
- - description: Display core clock
- - description: Display vsync clock
-
- clock-names:
-items:
- - const: bus
- - const: nrt_bus
- - const: iface
- - const: lut
- - const: core
- - const: vsync
-
-unevaluatedProperties: false
-
-examples:
- - |
-#include
-#include
-#include
-#include
-#include
-
-display-subsystem@ae0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "qcom,sc7280-mdss";
- reg = <0xae0 0x1000>;
- reg-names = "mdss";
- power-domains = < DISP_CC_MDSS_CORE_GDSC>;
- clocks = < GCC_DISP_AHB_CLK>,
- < DISP_CC_MDSS_AHB_CLK>,
- < DISP_CC_MDSS_MDP_CLK>;
- clock-names = "iface",
- "ahb",
- "core";
-
- interrupts = ;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interconnects = <_noc MASTER_MDP0 _virt SLAVE_EBI1>;
- interconnect-names = "mdp0-mem";
-
- iommus = <_smmu 0x900 0x402>;
- ranges;
-
- display-controller@ae01000 {
- compatible = "qcom,sc7280-dpu";
- reg = <0x0ae01000 0x8f000>,
- <0x0aeb 0x2008>;
-
- reg-names = "mdp", "vbif";
-
- clocks = < GCC_DISP_HF_AXI_CLK>,
-< GCC_DISP_SF_AXI_CLK>,
-< DISP_CC_MDSS_AHB_CLK>,
-< DISP_CC_MDSS_MDP_LUT_CLK>,
-< DISP_CC_MDSS_MDP_CLK>,
-< DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "bus",
- "nrt_bus",
- "iface",
- "lut",
- "core",
- "vsync";
-
- interrupt-parent = <>;
- interrupts = <0>;
- power-domains = < SC7280_CX>;
- operating-points-v2 = <_opp_table>;
-
- ports {
- #address-cells =
[PATCH v8 05/12] dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml
Move properties common to all MDSS DT nodes to the mdss-common.yaml. This extends qcom,msm8998-mdss schema to allow interconnect nodes, which will be added later, once msm8998 gains interconnect support. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 41 + .../bindings/display/msm/dpu-qcm2290.yaml | 51 ++-- .../bindings/display/msm/dpu-sc7180.yaml | 50 ++- .../bindings/display/msm/dpu-sc7280.yaml | 50 ++- .../bindings/display/msm/dpu-sdm845.yaml | 54 ++-- .../bindings/display/msm/mdss-common.yaml | 83 +++ 6 files changed, 111 insertions(+), 218 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 200eeace1c71..67791dbc3b5d 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -14,20 +14,13 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for MSM8998 target. +$ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,msm8998-mdss - reg: -maxItems: 1 - - reg-names: -const: mdss - - power-domains: -maxItems: 1 - clocks: items: - description: Display AHB clock @@ -40,23 +33,8 @@ properties: - const: bus - const: core - interrupts: -maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true +maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -100,18 +78,7 @@ patternProperties: - const: core - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index d5f1d16b13d3..42e676bdda4e 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -14,20 +14,13 @@ description: | sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS and DPU are mentioned for QCM2290 target. +$ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,qcm2290-mdss - reg: -maxItems: 1 - - reg-names: -const: mdss - - power-domains: -maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -40,35 +33,14 @@ properties: - const: bus - const: core - interrupts: -maxItems: 1 - - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true +maxItems: 2 interconnects: -items: - - description: Interconnect path specifying the port ids for data bus +maxItems: 1 interconnect-names: -const: mdp0-mem - - resets: -items: - - description: MDSS_CORE reset +maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -108,18 +80,7 @@ patternProperties: - const: lut - const: vsync -required: - - compatible - - reg - - reg-names - - power-domains - - clocks - - interrupts - - interrupt-controller - - iommus - - ranges - -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index 2ac10664d79a..99d6bbd45faf 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -14,20 +14,13 @@ description: | sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for SC7180 target. +$ref: /schemas/display/msm/mdss-common.yaml# + properties: compatible: items: - const: qcom,sc7180-mdss - reg: -maxItems: 1 - - reg-names: -const: mdss - - power-domains: -maxItems: 1 - clocks: items: - description: Display AHB clock from gcc @@ -40,34 +33,14 @@ properties:
[PATCH v8 08/12] dt-bindings: display/msm: split dpu-sdm845 into DPU and MDSS parts
In order to make the schema more readable, split dpu-sdm845 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sdm845.yaml | 148 --
.../bindings/display/msm/qcom,sdm845-dpu.yaml | 90 +++
.../display/msm/qcom,sdm845-mdss.yaml | 117 ++
3 files changed, 207 insertions(+), 148 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
deleted file mode 100644
index ae649bb6aa81..
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ /dev/null
@@ -1,148 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
-%YAML 1.2
-$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DPU dt properties for SDM845 target
-
-maintainers:
- - Krishna Manikandan
-
-description: |
- Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
- sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
- bindings of MDSS and DPU are mentioned for SDM845 target.
-
-$ref: /schemas/display/msm/mdss-common.yaml#
-
-properties:
- compatible:
-items:
- - const: qcom,sdm845-mdss
-
- clocks:
-items:
- - description: Display AHB clock from gcc
- - description: Display core clock
-
- clock-names:
-items:
- - const: iface
- - const: core
-
- iommus:
-maxItems: 2
-
- interconnects:
-maxItems: 2
-
- interconnect-names:
-maxItems: 2
-
-patternProperties:
- "^display-controller@[0-9a-f]+$":
-type: object
-$ref: /schemas/display/msm/dpu-common.yaml#
-description: Node containing the properties of DPU.
-unevaluatedProperties: false
-
-properties:
- compatible:
-items:
- - const: qcom,sdm845-dpu
-
- reg:
-items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
-items:
- - const: mdp
- - const: vbif
-
- clocks:
-items:
- - description: Display GCC bus clock
- - description: Display ahb clock
- - description: Display axi clock
- - description: Display core clock
- - description: Display vsync clock
-
- clock-names:
-items:
- - const: gcc-bus
- - const: iface
- - const: bus
- - const: core
- - const: vsync
-
-unevaluatedProperties: false
-
-examples:
- - |
-#include
-#include
-#include
-#include
-
-display-subsystem@ae0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "qcom,sdm845-mdss";
- reg = <0x0ae0 0x1000>;
- reg-names = "mdss";
- power-domains = < MDSS_GDSC>;
-
- clocks = < GCC_DISP_AHB_CLK>,
- < DISP_CC_MDSS_MDP_CLK>;
- clock-names = "iface", "core";
-
- interrupts = ;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- iommus = <_smmu 0x880 0x8>,
- <_smmu 0xc80 0x8>;
- ranges;
-
- display-controller@ae01000 {
-compatible = "qcom,sdm845-dpu";
-reg = <0x0ae01000 0x8f000>,
- <0x0aeb 0x2008>;
-reg-names = "mdp", "vbif";
-
-clocks = < GCC_DISP_AXI_CLK>,
- < DISP_CC_MDSS_AHB_CLK>,
- < DISP_CC_MDSS_AXI_CLK>,
- < DISP_CC_MDSS_MDP_CLK>,
- < DISP_CC_MDSS_VSYNC_CLK>;
-clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
-
-interrupt-parent = <>;
-interrupts = <0>;
-power-domains = < SDM845_CX>;
-operating-points-v2 = <_opp_table>;
-
-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dpu_intf1_out: endpoint {
- remote-endpoint = <_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- dpu_intf2_out: endpoint {
-
[PATCH v8 04/12] dt-bindings: display/msm: move common DPU properties to dpu-common.yaml
Move properties common to all DPU DT nodes to the dpu-common.yaml. Note, this removes description of individual DPU port@ nodes. However such definitions add no additional value. The reg values do not correspond to hardware INTF indices. The driver discovers and binds these ports not paying any care for the order of these items. Thus just leave the reference to graph.yaml#/properties/ports and the description. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-common.yaml | 52 +++ .../bindings/display/msm/dpu-msm8998.yaml | 44 +--- .../bindings/display/msm/dpu-qcm2290.yaml | 39 +- .../bindings/display/msm/dpu-sc7180.yaml | 43 +-- .../bindings/display/msm/dpu-sc7280.yaml | 43 +-- .../bindings/display/msm/dpu-sdm845.yaml | 44 +--- 6 files changed, 62 insertions(+), 203 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml new file mode 100644 index ..8ffbc30c6b7f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -0,0 +1,52 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU common properties + +maintainers: + - Krishna Manikandan + - Dmitry Baryshkov + - Rob Clark + +description: | + Common properties for QCom DPU display controller. + +properties: + interrupts: +maxItems: 1 + + power-domains: +maxItems: 1 + + operating-points-v2: true + opp-table: +type: object + + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. + +patternProperties: + "^port@[0-9a-f]+$": +$ref: /schemas/graph.yaml#/properties/port + +# at least one port is required +required: + - port@0 + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 253665c693e6..200eeace1c71 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -61,8 +61,9 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +$ref: /schemas/display/msm/dpu-common.yaml# description: Node containing the properties of DPU. -additionalProperties: false +unevaluatedProperties: false properties: compatible: @@ -99,47 +100,6 @@ patternProperties: - const: core - const: vsync - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - opp-table: -type: object - - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - - port@1: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF2 (DSI2) - -required: - - port@0 - - port@1 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index c5824e1d2382..d5f1d16b13d3 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -73,8 +73,9 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +$ref: /schemas/display/msm/dpu-common.yaml# description: Node containing the properties of DPU. -additionalProperties: false +unevaluatedProperties: false properties: compatible: @@ -107,42 +108,6 @@ patternProperties: - const: lut - const: vsync - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - -
[PATCH v8 01/12] dt-bindings: display/msm: split qcom,mdss bindings
Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +- .../bindings/display/msm/qcom,mdss.yaml | 264 ++ 2 files changed, 265 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 43d11279c925..65d03c58dee6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller Description: -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +This is the bindings documentation for the MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - MDP5: Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml new file mode 100644 index ..92a1cbae6d76 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -0,0 +1,264 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) + +maintainers: + - Dmitry Baryshkov + - Rob Clark + +description: + This is the bindings documentation for the Mobile Display Subsytem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + compatible: +enum: + - qcom,mdss + + reg: +minItems: 2 +maxItems: 3 + + reg-names: +minItems: 2 +items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: +maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": +const: 1 + + power-domains: +maxItems: 1 +description: | + The MDSS power domain provided by GCC + + clocks: +minItems: 1 +items: + - description: Display abh clock + - description: Display axi clock + - description: Display vsync clock + + clock-names: +minItems: 1 +items: + - const: iface + - const: bus + - const: vsync + + "#address-cells": +const: 1 + + "#size-cells": +const: 1 + + ranges: true + + resets: +items: + - description: MDSS_CORE reset + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^mdp@[1-9a-f][0-9a-f]*$": +type: object +properties: + compatible: +const: qcom,mdp5 + + "^dsi@[1-9a-f][0-9a-f]*$": +type: object +properties: + compatible: +const: qcom,mdss-dsi-ctrl + + "^phy@[1-9a-f][0-9a-f]*$": +type: object +properties: + compatible: +enum: + - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-14nm-8953 + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + +
[PATCH v8 10/12] dt-bindings: display/msm: split dpu-qcm2290 into DPU and MDSS parts
In order to make the schema more readable, split dpu-qcm2290 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-qcm2290.yaml | 148 --
.../display/msm/qcom,qcm2290-dpu.yaml | 84 ++
.../display/msm/qcom,qcm2290-mdss.yaml| 117 ++
3 files changed, 201 insertions(+), 148 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
deleted file mode 100644
index 42e676bdda4e..
--- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
+++ /dev/null
@@ -1,148 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
-%YAML 1.2
-$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DPU dt properties for QCM2290 target
-
-maintainers:
- - Loic Poulain
-
-description: |
- Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
- sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
- and DPU are mentioned for QCM2290 target.
-
-$ref: /schemas/display/msm/mdss-common.yaml#
-
-properties:
- compatible:
-items:
- - const: qcom,qcm2290-mdss
-
- clocks:
-items:
- - description: Display AHB clock from gcc
- - description: Display AXI clock
- - description: Display core clock
-
- clock-names:
-items:
- - const: iface
- - const: bus
- - const: core
-
- iommus:
-maxItems: 2
-
- interconnects:
-maxItems: 1
-
- interconnect-names:
-maxItems: 1
-
-patternProperties:
- "^display-controller@[0-9a-f]+$":
-type: object
-$ref: /schemas/display/msm/dpu-common.yaml#
-description: Node containing the properties of DPU.
-unevaluatedProperties: false
-
-properties:
- compatible:
-items:
- - const: qcom,qcm2290-dpu
-
- reg:
-items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
-items:
- - const: mdp
- - const: vbif
-
- clocks:
-items:
- - description: Display AXI clock from gcc
- - description: Display AHB clock from dispcc
- - description: Display core clock from dispcc
- - description: Display lut clock from dispcc
- - description: Display vsync clock from dispcc
-
- clock-names:
-items:
- - const: bus
- - const: iface
- - const: core
- - const: lut
- - const: vsync
-
-unevaluatedProperties: false
-
-examples:
- - |
-#include
-#include
-#include
-#include
-#include
-
-mdss: mdss@5e0 {
-#address-cells = <1>;
-#size-cells = <1>;
-compatible = "qcom,qcm2290-mdss";
-reg = <0x05e0 0x1000>;
-reg-names = "mdss";
-power-domains = < MDSS_GDSC>;
-clocks = < GCC_DISP_AHB_CLK>,
- < GCC_DISP_HF_AXI_CLK>,
- < DISP_CC_MDSS_MDP_CLK>;
-clock-names = "iface", "bus", "core";
-
-interrupts = ;
-interrupt-controller;
-#interrupt-cells = <1>;
-
-interconnects = <_virt MASTER_MDP0 SLAVE_EBI1>;
-interconnect-names = "mdp0-mem";
-
-iommus = <_smmu 0x420 0x2>,
- <_smmu 0x421 0x0>;
-ranges;
-
-mdss_mdp: display-controller@5e01000 {
-compatible = "qcom,qcm2290-dpu";
-reg = <0x05e01000 0x8f000>,
- <0x05eb 0x2008>;
-reg-names = "mdp", "vbif";
-
-clocks = < GCC_DISP_HF_AXI_CLK>,
- < DISP_CC_MDSS_AHB_CLK>,
- < DISP_CC_MDSS_MDP_CLK>,
- < DISP_CC_MDSS_MDP_LUT_CLK>,
- < DISP_CC_MDSS_VSYNC_CLK>;
-clock-names = "bus", "iface", "core", "lut", "vsync";
-
-operating-points-v2 = <_opp_table>;
-power-domains = < QCM2290_VDDCX>;
-
-interrupt-parent = <>;
-interrupts = <0>;
-
-ports {
-#address-cells = <1>;
-#size-cells = <0>;
-
-port@0 {
-reg = <0>;
-dpu_intf1_out: endpoint {
-remote-endpoint = <_in>;
-};
-};
-
[PATCH v8 06/12] dt-bindings: display/msm: split dpu-sc7180 into DPU and MDSS parts
In order to make the schema more readable, split dpu-sc7180 into the DPU
and MDSS parts, each one describing just a single device binding.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7180.yaml | 158 --
.../bindings/display/msm/qcom,sc7180-dpu.yaml | 95 +++
.../display/msm/qcom,sc7180-mdss.yaml | 125 ++
3 files changed, 220 insertions(+), 158 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
deleted file mode 100644
index 99d6bbd45faf..
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ /dev/null
@@ -1,158 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
-%YAML 1.2
-$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DPU dt properties for SC7180 target
-
-maintainers:
- - Krishna Manikandan
-
-description: |
- Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
- sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
- bindings of MDSS and DPU are mentioned for SC7180 target.
-
-$ref: /schemas/display/msm/mdss-common.yaml#
-
-properties:
- compatible:
-items:
- - const: qcom,sc7180-mdss
-
- clocks:
-items:
- - description: Display AHB clock from gcc
- - description: Display AHB clock from dispcc
- - description: Display core clock
-
- clock-names:
-items:
- - const: iface
- - const: ahb
- - const: core
-
- iommus:
-maxItems: 1
-
- interconnects:
-maxItems: 1
-
- interconnect-names:
-maxItems: 1
-
-patternProperties:
- "^display-controller@[0-9a-f]+$":
-type: object
-$ref: /schemas/display/msm/dpu-common.yaml#
-description: Node containing the properties of DPU.
-unevaluatedProperties: false
-
-properties:
- compatible:
-items:
- - const: qcom,sc7180-dpu
-
- reg:
-items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
-items:
- - const: mdp
- - const: vbif
-
- clocks:
-items:
- - description: Display hf axi clock
- - description: Display ahb clock
- - description: Display rotator clock
- - description: Display lut clock
- - description: Display core clock
- - description: Display vsync clock
-
- clock-names:
-items:
- - const: bus
- - const: iface
- - const: rot
- - const: lut
- - const: core
- - const: vsync
-
-unevaluatedProperties: false
-
-examples:
- - |
-#include
-#include
-#include
-#include
-#include
-
-display-subsystem@ae0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "qcom,sc7180-mdss";
- reg = <0xae0 0x1000>;
- reg-names = "mdss";
- power-domains = < MDSS_GDSC>;
- clocks = < GCC_DISP_AHB_CLK>,
- < DISP_CC_MDSS_AHB_CLK>,
- < DISP_CC_MDSS_MDP_CLK>;
- clock-names = "iface", "ahb", "core";
-
- interrupts = ;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interconnects = <_noc MASTER_MDP0 _virt SLAVE_EBI1>;
- interconnect-names = "mdp0-mem";
-
- iommus = <_smmu 0x800 0x2>;
- ranges;
-
- display-controller@ae01000 {
- compatible = "qcom,sc7180-dpu";
- reg = <0x0ae01000 0x8f000>,
- <0x0aeb 0x2008>;
-
- reg-names = "mdp", "vbif";
-
- clocks = < GCC_DISP_HF_AXI_CLK>,
-< DISP_CC_MDSS_AHB_CLK>,
-< DISP_CC_MDSS_ROT_CLK>,
-< DISP_CC_MDSS_MDP_LUT_CLK>,
-< DISP_CC_MDSS_MDP_CLK>,
-< DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "bus", "iface", "rot", "lut", "core",
- "vsync";
-
- interrupt-parent = <>;
- interrupts = <0>;
- power-domains = < SC7180_CX>;
- operating-points-v2 = <_opp_table>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
[PATCH v8 03/12] dt-bindings: display/msm: add interconnects property to qcom, mdss-smd845
Add interconnects required for the SDM845 MDSS device tree node. This
change was made in the commit c8c61c09e38b ("arm64: dts: qcom: sdm845:
Add interconnects property for display"), but was not reflected in the
schema.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-sdm845.yaml| 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
index 3cb2ae336996..a87deea8e9bc 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -57,6 +57,16 @@ properties:
ranges: true
+ interconnects:
+items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from mdp1 port to the data bus
+
+ interconnect-names:
+items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
resets:
items:
- description: MDSS_CORE reset
--
2.35.1
[PATCH v8 00/12] dt-bindings: display/msm: rework MDSS and DPU bindings
Create separate YAML schema for MDSS devicesd$ (both for MDP5 and DPU devices). Cleanup DPU schema files, so that they do not contain schema for both MDSS and DPU nodes. Apply misc small fixes to the DPU schema afterwards. Add schema for the MDSS and DPU on sm8250 platform. Soft dependency on [1] to define qcom,dsi-phy-14nm-2290 binding used in examples [1] https://lore.kernel.org/linux-arm-msm/20220924121900.222711-1-dmitry.barysh...@linaro.org/ Changes since v7: - Expanded examples to include MDSS child nodes (Krzysztof) Changes since v6: - Removed extra newlines (Krzysztof) - Added $ref to dpu-common.yaml#/ports/port@foo to enforce schema for the port nodes (Rob) - Removed unused allOf's (Rob) - Fixed repeated interconnects descriptions (Rob) - Fixed dpu-common.yaml and mdss-common.yaml descriptions (Rob) - Fixed intentation of examples (Krzysztof) - Renamed MDSS and DPU schema to follow compat names (Rob) Changes since v5: - Dropped the core clock from mdss.yaml. It will be handled in a separate patchset together with adding the clock itself. - Fixed a typo in two commit subjects (mdm -> msm). Changes since v4: - Created separate mdss-common.yaml - Rather than squashing everything into mdss.yaml, create individual schema files for MDSS devices. Changes since v3: - Changed mdss->(dpu, dsi, etc.) relationship into the tight binding depending on the mdss compatible string. - Added sm8250 dpu schema and added qcom,sm8250-mdss to mdss.yaml Changes since v2: - Added a patch to allow opp-table under the dpu* nodes. - Removed the c issue which allowed the @0 nodes under the MDSS device node. Changes since v1: - Renamed DPU device nodes from mdp@ to display-controller@ - Described removal of mistakenly mentioned "lut" clock - Switched mdss.yaml to use $ref instead of fixing compatible strings - Dropped mdp-opp-table description (renamed by Krzysztof in his patchset) - Reworked DPU's ports definitions. Dropped description of individual ports, left only /ports $ref and description in dpu-common.yaml. Dmitry Baryshkov (12): dt-bindings: display/msm: split qcom,mdss bindings dt-bindings: display/msm: add gcc-bus clock to dpu-smd845 dt-bindings: display/msm: add interconnects property to qcom,mdss-smd845 dt-bindings: display/msm: move common DPU properties to dpu-common.yaml dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml dt-bindings: display/msm: split dpu-sc7180 into DPU and MDSS parts dt-bindings: display/msm: split dpu-sc7280 into DPU and MDSS parts dt-bindings: display/msm: split dpu-sdm845 into DPU and MDSS parts dt-bindings: display/msm: split dpu-msm8998 into DPU and MDSS parts dt-bindings: display/msm: split dpu-qcm2290 into DPU and MDSS parts dt-bindings: display/msm: add missing device nodes to mdss-* schemas dt-bindings: display/msm: add support for the display on SM8250 .../bindings/display/msm/dpu-common.yaml | 52 +++ .../bindings/display/msm/dpu-msm8998.yaml | 223 - .../bindings/display/msm/dpu-qcm2290.yaml | 222 - .../bindings/display/msm/dpu-sc7180.yaml | 235 -- .../bindings/display/msm/dpu-sc7280.yaml | 239 -- .../bindings/display/msm/dpu-sdm845.yaml | 217 - .../devicetree/bindings/display/msm/mdp5.txt | 30 +- .../bindings/display/msm/mdss-common.yaml | 83 .../bindings/display/msm/qcom,mdss.yaml | 264 +++ .../display/msm/qcom,msm8998-dpu.yaml | 95 .../display/msm/qcom,msm8998-mdss.yaml| 268 +++ .../display/msm/qcom,qcm2290-dpu.yaml | 84 .../display/msm/qcom,qcm2290-mdss.yaml| 198 .../bindings/display/msm/qcom,sc7180-dpu.yaml | 95 .../display/msm/qcom,sc7180-mdss.yaml | 304 + .../bindings/display/msm/qcom,sc7280-dpu.yaml | 98 .../display/msm/qcom,sc7280-mdss.yaml | 422 ++ .../bindings/display/msm/qcom,sdm845-dpu.yaml | 90 .../display/msm/qcom,sdm845-mdss.yaml | 270 +++ .../bindings/display/msm/qcom,sm8250-dpu.yaml | 92 .../display/msm/qcom,sm8250-mdss.yaml | 330 ++ 21 files changed, 2746 insertions(+), 1165 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-common.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml create mode 100644
[PATCH v3 1/2] dt-bindings: display/msm: Add QCM2290 DSI phy
From: Loic Poulain QCM2290 platform uses the 14nm DSI PHY driver. Signed-off-by: Loic Poulain Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index bc3d0b4063c7..054d8f65d9fa 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -15,6 +15,7 @@ properties: compatible: enum: - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-2290 - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 -- 2.35.1
[PATCH v3 0/2] drm/msm/dsi: Add support for DSI PHY on QCM2290
The QCM2290 platform uses 14nm DSI PHY. As the configuration is not
fully compatible with the main qcom,dsi-phy-14nm, a separate compatible
is added.
Changes since v2:
- Changed compatible back to qcom,dsi-phy-14nm-2290
Changes since v1:
- Rebased on top of msm-next, fixed DSI PHY config to follow upstream
changes.
- Changed compatible to follow agreed scheme
('qcom,qcm2290-dsi-phy-14nm').
- Updated commit messages.
Loic Poulain (2):
dt-bindings: display/msm: Add QCM2290 DSI phy
drm/msm/dsi: Add phy configuration for QCM2290
.../bindings/display/msm/dsi-phy-14nm.yaml | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
4 files changed, 21 insertions(+)
--
2.35.1
[PATCH v3 2/2] drm/msm/dsi: Add phy configuration for QCM2290
From: Loic Poulain
The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not
fully compatible with the standard 14nm PHY, so it requires a separate
compatible and config entry.
Signed-off-by: Loic Poulain
[DB: rebased and updated commit msg]
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 7fc0975cb869..ee6051367679 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
{ .compatible = "qcom,dsi-phy-14nm",
.data = _phy_14nm_cfgs },
+ { .compatible = "qcom,dsi-phy-14nm-2290",
+ .data = _phy_14nm_2290_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-660",
.data = _phy_14nm_660_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-8953",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 60a99c6525b2..1096afedd616 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 0f8f4ca46429..9f488adea7f5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_14nm_17mA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
+ .ops = {
+ .enable = dsi_14nm_phy_enable,
+ .disable = dsi_14nm_phy_disable,
+ .pll_init = dsi_pll_14nm_init,
+ .save_pll_state = dsi_14nm_pll_save_state,
+ .restore_pll_state = dsi_14nm_pll_restore_state,
+ },
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
+ .io_start = { 0x5e94400 },
+ .num_dsi_phy = 1,
+};
--
2.35.1
Re: [PATCH v5 04/15] mei: bus: extend bus API to support command streamer API
On Mon, Sep 12, 2022 at 05:57:28PM -0700, Daniele Ceraolo Spurio wrote: > From: Vitaly Lubart > > Add mei bus API for sending gsc commands: mei_cldev_send_gsc_command() > > The GSC commands are originated in the graphics stack > and are in form of SGL DMA buffers. > The GSC commands are synchronous, the response is received > in the same call on the out sg list buffers. > The function setups pointers for in and out sg lists in the > mei sgl extended header and sends it to the firmware. > > Signed-off-by: Vitaly Lubart > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Greg Kroah-Hartman > --- Reviewed-by: Greg Kroah-Hartman
Re: [PATCH v5 05/15] mei: pxp: add command streamer API to the PXP driver
On Mon, Sep 12, 2022 at 05:57:29PM -0700, Daniele Ceraolo Spurio wrote: > From: Vitaly Lubart > > The discrete graphics card with GSC firmware > using command streamer API hence it requires to enhance > pxp module with the new gsc_command() handler. > > The handler is implemented via mei_pxp_gsc_command() which is > just a thin wrapper around mei_cldev_send_gsc_command() > > Signed-off-by: Vitaly Lubart > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Greg Kroah-Hartman > Reviewed-by: Alan Previn > --- Reviewed-by: Greg Kroah-Hartman
Re: [PATCH v5 02/15] mei: bus: enable sending gsc commands
On Mon, Sep 12, 2022 at 05:57:26PM -0700, Daniele Ceraolo Spurio wrote: > From: Tomas Winkler > > GSC command is and extended header containing a scatter gather > list and without a data buffer. Using MEI_CL_IO_SGL flag, > the caller send the GSC command as a data and the function internally > moves it to the extended header. > > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Vitaly Lubart > Cc: Greg Kroah-Hartman > --- Reviewed-by: Greg Kroah-Hartman
[PATCH v2] drm/etnaviv: add HWDB entry for GC7000 r6203
From: Marco Felsch
The GPU is found on the NXP i.MX8MN SoC. The feature bits are taken from
the NXP downstream kernel driver 6.4.3.p2.
Signed-off-by: Marco Felsch
---
v2: Make match more specific, as there are some other GPUs with the
same model/revision, so we should also look at the customer and product
IDs.
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index f2fc645c7956..57f334e24189 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -68,6 +68,37 @@ static const struct etnaviv_chip_identity
etnaviv_chip_identities[] = {
.minor_features10 = 0x4040,
.minor_features11 = 0x0024,
},
+ {
+ .model = 0x7000,
+ .revision = 0x6203,
+ .product_id = 0x70003,
+ .customer_id = 0x4,
+ .eco_id = 0,
+ .stream_count = 16,
+ .register_max = 64,
+ .thread_count = 512,
+ .shader_core_count = 2,
+ .vertex_cache_size = 16,
+ .vertex_output_buffer_size = 1024,
+ .pixel_pipes = 1,
+ .instruction_count = 512,
+ .num_constants = 320,
+ .buffer_size = 0,
+ .varyings_count = 16,
+ .features = 0xe0287c8d,
+ .minor_features0 = 0xc1589eff,
+ .minor_features1 = 0xfefbfad9,
+ .minor_features2 = 0xeb9d4fbf,
+ .minor_features3 = 0xedfffced,
+ .minor_features4 = 0xdb0dafc7,
+ .minor_features5 = 0x3b5ac333,
+ .minor_features6 = 0xfcce6000,
+ .minor_features7 = 0xfffbfa6f,
+ .minor_features8 = 0x00e10ef3,
+ .minor_features9 = 0x00c8003c,
+ .minor_features10 = 0x4040,
+ .minor_features11 = 0x0024,
+ },
{
.model = 0x7000,
.revision = 0x6204,
--
2.30.2
Re: [PATCH v5 06/15] mei: pxp: support matching with a gfx discrete card
On Mon, Sep 12, 2022 at 05:57:30PM -0700, Daniele Ceraolo Spurio wrote: > From: Tomas Winkler > > With on-boards graphics card, both i915 and MEI > are in the same device hierarchy with the same parent, > while for discrete gfx card the MEI is its child device. > Adjust the match function for that scenario > by matching MEI parent device with i915. > > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Vitaly Lubart > Cc: Greg Kroah-Hartman > Reviewed-by: Alan Previn > --- Reviewed-by: Greg Kroah-Hartman
Re: [PATCH v5 03/15] mei: adjust extended header kdocs
On Mon, Sep 12, 2022 at 05:57:27PM -0700, Daniele Ceraolo Spurio wrote: > From: Tomas Winkler > > Fix kdoc for struct mei_ext_hdr and mei_ext_begin(). > > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Greg Kroah-Hartman > --- Reviewed-by: Greg Kroah-Hartman
Re: [PATCH v5 01/15] mei: add support to GSC extended header
On Mon, Sep 12, 2022 at 05:57:25PM -0700, Daniele Ceraolo Spurio wrote: > From: Tomas Winkler > > GSC extend header is of variable size and data > is provided in a sgl list inside the header > and not in the data buffers, need to enable the path. > > Signed-off-by: Tomas Winkler > Signed-off-by: Daniele Ceraolo Spurio > Cc: Vitaly Lubart > Cc: Greg Kroah-Hartman > --- Reviewed-by: Greg Kroah-Hartman
[PATCH 2/2] arm64: dts: qcom: msm8996: change HDMI PHY node name to generic one
Change HDMI PHY node name from custom 'hdmi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index a7d0e5d68141..ed9863854904 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1144,7 +1144,7 @@ hdmi_in: endpoint {
};
};
- hdmi_phy: hdmi-phy@9a0600 {
+ hdmi_phy: phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
--
2.35.1
[PATCH 0/2] arm: dts: qcom: rename HDMI PHY nodes
Historically HDMI PHY device tree nodes used the hdmi-phy@ names. Replace them with generic phy@ names. While there is no such requirement in the DT schema, it's worth doing that because: 1) The recent qcom DT files already use just phy@ for most of PHY nodes 2) The recommended list from devicetree specs mentions usb-phy/ethernet-phy, but not -phy, so I'd think that those two are mostly for backwards compatibility. 3) I liked the example of sc7280 which switched all MDSS PHYs to just phy@ (this includes DSI PHY, eDP PHY and, by extension, the HDMI PHY). Dmitry Baryshkov (2): ARM: dts: qcom-apq8064: change HDMI PHY node name to generic one arm64: dts: qcom: msm8996: change HDMI PHY node name to generic one arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +- arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.35.1
[PATCH 1/2] ARM: dts: qcom-apq8064: change HDMI PHY node name to generic one
Change HDMI PHY node names from custom 'hdmi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +-
arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 0322cb88d448..497c4012a65b 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -361,7 +361,7 @@ endpoint {
};
};
- hdmi-phy@4a00400 {
+ phy@4a00400 {
status = "okay";
core-vdda-supply = <_hdmi_switch>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1b704c7ea890..58f239218639 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1453,7 +1453,7 @@ hdmi_out: endpoint {
};
};
- hdmi_phy: hdmi-phy@4a00400 {
+ hdmi_phy: phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
--
2.35.1
Re: [PATCH 9/9] arm64: dts: qcom: sm8250: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 8/9] arm64: dts: qcom: sdm845: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 7/9] arm64: dts: qcom: sdm660: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 6/9] arm64: dts: qcom: sdm630: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 5/9] arm64: dts: qcom: sc7180: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 4/9] arm64: dts: qcom: msm8996: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 3/9] arm64: dts: qcom: msm8916: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 2/9] ARM: dts: qcom-msm8974: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 1/9] ARM: dts: qcom-apq8064: change DSI PHY node name to generic one
On 24/09/2022 11:01, Dmitry Baryshkov wrote: > Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
On 24/09/2022 11:20, Dmitry Baryshkov wrote: > On 24/09/2022 12:11, Krzysztof Kozlowski wrote: >> On 24/09/2022 11:00, Dmitry Baryshkov wrote: >>> Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace >>> them with generic phy@ names. >>> >>> Dmitry Baryshkov (9): >>>ARM: dts: qcom-apq8064: change DSI PHY node name to generic one >> >> dsi-phy is similar to other generic names (usb-phy, ethernet-phy) [1] so >> it could stay. Is there particular need for this, like coming from DT >> schema? > > No, there is no requirement from the DT schema. However: > 1) The resent qcom DT files already use just phy@ for most of PHY nodes > 2) The recommended list mentions usb-phy/ethernet-phy, but not > -phy, so I'd think that those two are mostly for backwards > compatibility. > 3) I liked the example of sc7280 which switched all MDSS PHYs to just > phy@ (this includes DSI PHY, eDP PHY and, by extension, the HDMI PHY). Good explanation. If there is going to be resent/submit, please add it to cover letter. :) Best regards, Krzysztof
[PATCH] arm64: dts: qcom: sc7280: assign DSI clocks
The driver (and the DT schema) requires us to assign DSI clocks in the
DT node, so that the clock tree is setup propertly.
Fixes: 43137272f0bc ("arm64: dts: qcom: sc7280: Add DSI display nodes")
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 13d7f267b289..d5c01ee1d2fa 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3636,6 +3636,10 @@ mdss_dsi: dsi@ae94000 {
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <
DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <_dsi_phy 0>,
<_dsi_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SC7280_CX>;
--
2.35.1
Re: [PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
On 24/09/2022 12:11, Krzysztof Kozlowski wrote: On 24/09/2022 11:00, Dmitry Baryshkov wrote: Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace them with generic phy@ names. Dmitry Baryshkov (9): ARM: dts: qcom-apq8064: change DSI PHY node name to generic one dsi-phy is similar to other generic names (usb-phy, ethernet-phy) [1] so it could stay. Is there particular need for this, like coming from DT schema? No, there is no requirement from the DT schema. However: 1) The resent qcom DT files already use just phy@ for most of PHY nodes 2) The recommended list mentions usb-phy/ethernet-phy, but not -phy, so I'd think that those two are mostly for backwards compatibility. 3) I liked the example of sc7280 which switched all MDSS PHYs to just phy@ (this includes DSI PHY, eDP PHY and, by extension, the HDMI PHY). [1] https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Best regards, Krzysztof -- With best wishes Dmitry
Re: [PATCH v2 1/2] dt-bindings: display/msm: Add QCM2290 DSI phy
On 24/09/2022 12:12, Krzysztof Kozlowski wrote: On 24/09/2022 10:51, Dmitry Baryshkov wrote: From: Loic Poulain QCM2290 platform uses the 14nm DSI PHY driver. Signed-off-by: Loic Poulain [DB: changed compat to follow the agreed scheme] Bjorn asked to keep consistency in other case: https://lore.kernel.org/all/20220829210408.gxbv6szxfwiiw...@builder.lan/ Ack. Should I use qcom,dsi-phy-14nm-2290 or qcom,dsi-phy-14nm-qcm2290? Note we already have "qcom,sc7280-dsi-phy-10nm". --- Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index bc3d0b4063c7..088a03ed5f80 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -17,6 +17,7 @@ properties: - qcom,dsi-phy-14nm - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 + - qcom,qcm2290-dsi-phy-14nm Best regards, Krzysztof -- With best wishes Dmitry
Re: [PATCH v2 1/2] dt-bindings: display/msm: Add QCM2290 DSI phy
On 24/09/2022 10:51, Dmitry Baryshkov wrote: > From: Loic Poulain > > QCM2290 platform uses the 14nm DSI PHY driver. > > Signed-off-by: Loic Poulain > [DB: changed compat to follow the agreed scheme] Bjorn asked to keep consistency in other case: https://lore.kernel.org/all/20220829210408.gxbv6szxfwiiw...@builder.lan/ > --- > Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > index bc3d0b4063c7..088a03ed5f80 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > @@ -17,6 +17,7 @@ properties: >- qcom,dsi-phy-14nm >- qcom,dsi-phy-14nm-660 >- qcom,dsi-phy-14nm-8953 > + - qcom,qcm2290-dsi-phy-14nm Best regards, Krzysztof
Re: [PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
On 24/09/2022 11:00, Dmitry Baryshkov wrote: > Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace > them with generic phy@ names. > > Dmitry Baryshkov (9): > ARM: dts: qcom-apq8064: change DSI PHY node name to generic one dsi-phy is similar to other generic names (usb-phy, ethernet-phy) [1] so it could stay. Is there particular need for this, like coming from DT schema? [1] https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Best regards, Krzysztof
Re: [PATCH v2 03/16] skbuff: Proactively round up to kmalloc bucket size
On Fri, Sep 23, 2022 at 01:28:09PM -0700, Kees Cook wrote:
> Instead of discovering the kmalloc bucket size _after_ allocation, round
> up proactively so the allocation is explicitly made for the full size,
> allowing the compiler to correctly reason about the resulting size of
> the buffer through the existing __alloc_size() hint.
>
> This will allow for kernels built with CONFIG_UBSAN_BOUNDS or the
> coming dynamic bounds checking under CONFIG_FORTIFY_SOURCE to gain
> back the __alloc_size() hints that were temporarily reverted in commit
> 93dd04ab0b2b ("slab: remove __alloc_size attribute from
> __kmalloc_track_caller")
>
> Additionally tries to normalize size variables to u32 from int. Most
> interfaces are using "int", but notably __alloc_skb uses unsigned int.
>
> Also fix some reverse Christmas tree and comments while touching nearby
> code.
Something in this patch is breaking things -- I've refactored it again
to avoid overwriting the incoming size argument, and instead add a
dedicated outgoing size variable. Here's what will be v3 ...
---
net/core/skbuff.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index 974e7138..9b5a9fb69d9d 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -346,11 +346,12 @@ EXPORT_SYMBOL(napi_build_skb);
* memory is free
*/
static void *kmalloc_reserve(size_t size, gfp_t flags, int node,
-bool *pfmemalloc)
+bool *pfmemalloc, size_t *alloc_size)
{
void *obj;
bool ret_pfmemalloc = false;
+ size = kmalloc_size_roundup(size);
/*
* Try a regular allocation, when that fails and we're not entitled
* to the reserves, fail.
@@ -369,6 +370,7 @@ static void *kmalloc_reserve(size_t size, gfp_t flags, int
node,
if (pfmemalloc)
*pfmemalloc = ret_pfmemalloc;
+ *alloc_size = size;
return obj;
}
@@ -400,7 +402,7 @@ struct sk_buff *__alloc_skb(unsigned int size, gfp_t
gfp_mask,
{
struct kmem_cache *cache;
struct sk_buff *skb;
- unsigned int osize;
+ size_t alloc_size;
bool pfmemalloc;
u8 *data;
@@ -427,15 +429,15 @@ struct sk_buff *__alloc_skb(unsigned int size, gfp_t
gfp_mask,
*/
size = SKB_DATA_ALIGN(size);
size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- data = kmalloc_reserve(size, gfp_mask, node, );
- if (unlikely(!data))
- goto nodata;
- /* kmalloc(size) might give us more room than requested.
+ /* kmalloc(size) might give us more room than requested, so
+* allocate the true bucket size up front.
* Put skb_shared_info exactly at the end of allocated zone,
* to allow max possible filling before reallocation.
*/
- osize = ksize(data);
- size = SKB_WITH_OVERHEAD(osize);
+ data = kmalloc_reserve(size, gfp_mask, node, , _size);
+ if (unlikely(!data))
+ goto nodata;
+ size = SKB_WITH_OVERHEAD(alloc_size);
prefetchw(data + size);
/*
@@ -444,7 +446,7 @@ struct sk_buff *__alloc_skb(unsigned int size, gfp_t
gfp_mask,
* the tail pointer in struct sk_buff!
*/
memset(skb, 0, offsetof(struct sk_buff, tail));
- __build_skb_around(skb, data, osize);
+ __build_skb_around(skb, data, alloc_size);
skb->pfmemalloc = pfmemalloc;
if (flags & SKB_ALLOC_FCLONE) {
@@ -1709,6 +1711,7 @@ int pskb_expand_head(struct sk_buff *skb, int nhead, int
ntail,
{
int i, osize = skb_end_offset(skb);
int size = osize + nhead + ntail;
+ size_t alloc_size;
long off;
u8 *data;
@@ -1723,10 +1726,10 @@ int pskb_expand_head(struct sk_buff *skb, int nhead,
int ntail,
if (skb_pfmemalloc(skb))
gfp_mask |= __GFP_MEMALLOC;
data = kmalloc_reserve(size + SKB_DATA_ALIGN(sizeof(struct
skb_shared_info)),
- gfp_mask, NUMA_NO_NODE, NULL);
+ gfp_mask, NUMA_NO_NODE, NULL, _size);
if (!data)
goto nodata;
- size = SKB_WITH_OVERHEAD(ksize(data));
+ size = SKB_WITH_OVERHEAD(alloc_size);
/* Copy only real data... and, alas, header. This should be
* optimized for the cases when header is void.
@@ -6063,19 +6066,19 @@ static int pskb_carve_inside_header(struct sk_buff
*skb, const u32 off,
int i;
int size = skb_end_offset(skb);
int new_hlen = headlen - off;
+ size_t alloc_size;
u8 *data;
size = SKB_DATA_ALIGN(size);
if (skb_pfmemalloc(skb))
gfp_mask |= __GFP_MEMALLOC;
- data = kmalloc_reserve(size +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
- gfp_mask, NUMA_NO_NODE, NULL);
+
[PATCH 8/9] arm64: dts: qcom: sdm845: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index f0e286715d1b..df6427ba2284 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4537,7 +4537,7 @@ dsi0_out: endpoint {
};
};
- dsi0_phy: dsi-phy@ae94400 {
+ dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -4609,7 +4609,7 @@ dsi1_out: endpoint {
};
};
- dsi1_phy: dsi-phy@ae96400 {
+ dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
--
2.35.1
[PATCH 5/9] arm64: dts: qcom: sc7180: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index b82c335c25af..0002d92eb29b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3057,7 +3057,7 @@ opp-35800 {
};
};
- dsi_phy: dsi-phy@ae94400 {
+ dsi_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
--
2.35.1
[PATCH 3/9] arm64: dts: qcom: msm8916: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 48bc2e09128d..9e0a5cb469c8 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1056,7 +1056,7 @@ dsi0_out: endpoint {
};
};
- dsi_phy0: dsi-phy@1a98300 {
+ dsi_phy0: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
--
2.35.1
[PATCH 1/9] ARM: dts: qcom-apq8064: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 2 +-
arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index fee278e32cb6..2c5ee2e98fe2 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -252,7 +252,7 @@ dsi0_out: endpoint {
};
};
- dsi-phy@4700200 {
+ phy@4700200 {
status = "okay";
vddio-supply = <_lvs7>;/*VDD_PLL2_1 to 7*/
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index ada4c828bf2f..1b704c7ea890 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1303,7 +1303,7 @@ dsi0_out: endpoint {
};
- dsi0_phy: dsi-phy@4700200 {
+ dsi0_phy: phy@4700200 {
compatible = "qcom,dsi-phy-28nm-8960";
#clock-cells = <1>;
#phy-cells = <0>;
--
2.35.1
[PATCH 2/9] ARM: dts: qcom-msm8974: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 8baca2a77717..d3a7de42f693 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1592,7 +1592,7 @@ dsi0_out: endpoint {
};
};
- dsi0_phy: dsi-phy@fd922a00 {
+ dsi0_phy: phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
--
2.35.1
[PATCH 7/9] arm64: dts: qcom: sdm660: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi
b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index 43220af1b685..d102c7e25b79 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -213,7 +213,7 @@ dsi1_out: endpoint {
};
};
- dsi1_phy: dsi-phy@c996400 {
+ dsi1_phy: phy@c996400 {
compatible = "qcom,dsi-phy-14nm-660";
reg = <0x0c996400 0x100>,
<0x0c996500 0x300>,
--
2.35.1
[PATCH 9/9] arm64: dts: qcom: sm8250: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 5843e46a3164..e3ea39fcec13 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3592,7 +3592,7 @@ opp-35800 {
};
};
- dsi0_phy: dsi-phy@ae94400 {
+ dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -3665,7 +3665,7 @@ dsi1_out: endpoint {
};
};
- dsi1_phy: dsi-phy@ae96400 {
+ dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
--
2.35.1
[PATCH 4/9] arm64: dts: qcom: msm8996: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 742eac4ce9b3..a7d0e5d68141 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1017,7 +1017,7 @@ dsi0_out: endpoint {
};
};
- dsi0_phy: dsi-phy@994400 {
+ dsi0_phy: phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00994400 0x100>,
<0x00994500 0x300>,
@@ -1085,7 +1085,7 @@ dsi1_out: endpoint {
};
};
- dsi1_phy: dsi-phy@996400 {
+ dsi1_phy: phy@996400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00996400 0x100>,
<0x00996500 0x300>,
--
2.35.1
[PATCH 6/9] arm64: dts: qcom: sdm630: change DSI PHY node name to generic one
Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 1bc9091cad2a..dc83329689a1 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1633,7 +1633,7 @@ dsi0_out: endpoint {
};
};
- dsi0_phy: dsi-phy@c994400 {
+ dsi0_phy: phy@c994400 {
compatible = "qcom,dsi-phy-14nm-660";
reg = <0x0c994400 0x100>,
<0x0c994500 0x300>,
--
2.35.1
[PATCH 0/9] arm: dts: qcom: rename DSI PHY nodes
Historically DSI PHY device tree nodes used the dsi-phy@ names. Replace them with generic phy@ names. Dmitry Baryshkov (9): ARM: dts: qcom-apq8064: change DSI PHY node name to generic one ARM: dts: qcom-msm8974: change DSI PHY node name to generic one arm64: dts: qcom: msm8916: change DSI PHY node name to generic one arm64: dts: qcom: msm8996: change DSI PHY node name to generic one arm64: dts: qcom: sc7180: change DSI PHY node name to generic one arm64: dts: qcom: sdm630: change DSI PHY node name to generic one arm64: dts: qcom: sdm660: change DSI PHY node name to generic one arm64: dts: qcom: sdm845: change DSI PHY node name to generic one arm64: dts: qcom: sm8250: change DSI PHY node name to generic one arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 2 +- arch/arm/boot/dts/qcom-apq8064.dtsi| 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi| 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- 10 files changed, 13 insertions(+), 13 deletions(-) -- 2.35.1
[PATCH v2 2/2] drm/msm/dsi: Add phy configuration for QCM2290
From: Loic Poulain
The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not
fully compatible with the standard 14nm PHY, so it requires a separate
compatible and config entry.
Signed-off-by: Loic Poulain
[DB: changed compat to follow the agreed scheme, rebased and updated commit msg]
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 7fc0975cb869..724d5fa0788a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -553,6 +553,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = _phy_14nm_660_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-8953",
.data = _phy_14nm_8953_cfgs },
+ { .compatible = "qcom,qcm2290-dsi-phy-14nm",
+ .data = _phy_14nm_2290_cfgs },
#endif
#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
{ .compatible = "qcom,dsi-phy-10nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 60a99c6525b2..1096afedd616 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 0f8f4ca46429..9f488adea7f5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_14nm_17mA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
+ .ops = {
+ .enable = dsi_14nm_phy_enable,
+ .disable = dsi_14nm_phy_disable,
+ .pll_init = dsi_pll_14nm_init,
+ .save_pll_state = dsi_14nm_pll_save_state,
+ .restore_pll_state = dsi_14nm_pll_restore_state,
+ },
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
+ .io_start = { 0x5e94400 },
+ .num_dsi_phy = 1,
+};
--
2.35.1
[PATCH v2 0/2] drm/msm/dsi: Add support for DSI PHY on QCM2290
The QCM2290 platform uses 14nm DSI PHY. As the configuration is not
fully compatible with the main qcom,dsi-phy-14nm, a separate compatible
is added.
V1 was not sent to freedreno@, so it nearly got missed by me.
Changes since v1:
- Rebased on top of msm-next, fixed DSI PHY config to follow upstream
changes.
- Changed compatible to follow agreed scheme
('qcom,qcm2290-dsi-phy-14nm').
- Updated commit messages.
Loic Poulain (2):
dt-bindings: display/msm: Add QCM2290 DSI phy
drm/msm/dsi: Add phy configuration for QCM2290
.../bindings/display/msm/dsi-phy-14nm.yaml | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +
4 files changed, 21 insertions(+)
--
2.35.1
[PATCH v2 1/2] dt-bindings: display/msm: Add QCM2290 DSI phy
From: Loic Poulain QCM2290 platform uses the 14nm DSI PHY driver. Signed-off-by: Loic Poulain [DB: changed compat to follow the agreed scheme] Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index bc3d0b4063c7..088a03ed5f80 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -17,6 +17,7 @@ properties: - qcom,dsi-phy-14nm - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 + - qcom,qcm2290-dsi-phy-14nm reg: items: -- 2.35.1
Re: [PATCH v2 14/16] kasan: Remove ksize()-related tests
On Fri, 23 Sept 2022 at 22:28, Kees Cook wrote:
>
> In preparation for no longer unpoisoning in ksize(), remove the behavioral
> self-tests for ksize().
>
> Cc: Andrey Ryabinin
> Cc: Alexander Potapenko
> Cc: Andrey Konovalov
> Cc: Dmitry Vyukov
> Cc: Vincenzo Frascino
> Cc: Andrew Morton
> Cc: kasan-...@googlegroups.com
> Cc: linux...@kvack.org
> Signed-off-by: Kees Cook
> ---
> lib/test_kasan.c | 42 --
> mm/kasan/shadow.c | 4 +---
> 2 files changed, 1 insertion(+), 45 deletions(-)
>
> diff --git a/lib/test_kasan.c b/lib/test_kasan.c
> index 58c1b01ccfe2..bdd0ced8f8d7 100644
> --- a/lib/test_kasan.c
> +++ b/lib/test_kasan.c
> @@ -753,46 +753,6 @@ static void kasan_global_oob_left(struct kunit *test)
> KUNIT_EXPECT_KASAN_FAIL(test, *(volatile char *)p);
> }
>
> -/* Check that ksize() makes the whole object accessible. */
> -static void ksize_unpoisons_memory(struct kunit *test)
> -{
> - char *ptr;
> - size_t size = 123, real_size;
> -
> - ptr = kmalloc(size, GFP_KERNEL);
> - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);
> - real_size = ksize(ptr);
> -
> - OPTIMIZER_HIDE_VAR(ptr);
> -
> - /* This access shouldn't trigger a KASAN report. */
> - ptr[size] = 'x';
I would rather keep the tests and update to the new behavior. We had
bugs in ksize, we need test coverage.
I assume ptr[size] access must now produce an error even after ksize.
> - /* This one must. */
> - KUNIT_EXPECT_KASAN_FAIL(test, ((volatile char *)ptr)[real_size]);
> -
> - kfree(ptr);
> -}
> -
> -/*
> - * Check that a use-after-free is detected by ksize() and via normal accesses
> - * after it.
> - */
> -static void ksize_uaf(struct kunit *test)
> -{
> - char *ptr;
> - int size = 128 - KASAN_GRANULE_SIZE;
> -
> - ptr = kmalloc(size, GFP_KERNEL);
> - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);
> - kfree(ptr);
> -
> - OPTIMIZER_HIDE_VAR(ptr);
> - KUNIT_EXPECT_KASAN_FAIL(test, ksize(ptr));
This is still a bug that should be detected, right? Calling ksize on a
freed pointer is a bug.
> - KUNIT_EXPECT_KASAN_FAIL(test, ((volatile char *)ptr)[0]);
> - KUNIT_EXPECT_KASAN_FAIL(test, ((volatile char *)ptr)[size]);
> -}
> -
> static void kasan_stack_oob(struct kunit *test)
> {
> char stack_array[10];
> @@ -1392,8 +1352,6 @@ static struct kunit_case kasan_kunit_test_cases[] = {
> KUNIT_CASE(kasan_stack_oob),
> KUNIT_CASE(kasan_alloca_oob_left),
> KUNIT_CASE(kasan_alloca_oob_right),
> - KUNIT_CASE(ksize_unpoisons_memory),
> - KUNIT_CASE(ksize_uaf),
> KUNIT_CASE(kmem_cache_double_free),
> KUNIT_CASE(kmem_cache_invalid_free),
> KUNIT_CASE(kmem_cache_double_destroy),
> diff --git a/mm/kasan/shadow.c b/mm/kasan/shadow.c
> index 0e3648b603a6..0895c73e9b69 100644
> --- a/mm/kasan/shadow.c
> +++ b/mm/kasan/shadow.c
> @@ -124,9 +124,7 @@ void kasan_unpoison(const void *addr, size_t size, bool
> init)
> addr = kasan_reset_tag(addr);
>
> /*
> -* Skip KFENCE memory if called explicitly outside of sl*b. Also note
> -* that calls to ksize(), where size is not a multiple of machine-word
> -* size, would otherwise poison the invalid portion of the word.
> +* Skip KFENCE memory if called explicitly outside of sl*b.
> */
> if (is_kfence_address(addr))
> return;
> --
> 2.34.1
[PATCH v4 4/6] Revert "drm/mediatek: Add mediatek-drm of vdosys0 support for mt8195"
This reverts commit 7266e90a51a32722a94daa3cb5b8fa278059e49e.
Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 8 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 150 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 -
3 files changed, 14 insertions(+), 150 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0ec2e4049e07..2cb90466798c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -370,8 +370,8 @@ static const struct mtk_disp_rdma_data
mt8183_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
-static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
- .fifo_size = 1920,
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
};
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
@@ -381,8 +381,8 @@ static const struct of_device_id
mtk_disp_rdma_driver_dt_match[] = {
.data = _rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = _rdma_driver_data},
- { .compatible = "mediatek,mt8195-disp-rdma",
- .data = _rdma_driver_data},
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = _rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5f02f8d0e4fc..adc9a4f4085b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,8 +4,6 @@
* Author: YT SHEN
*/
-#include
-#include
#include
#include
#include
@@ -197,19 +195,6 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
-static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
- DDP_COMPONENT_OVL0,
- DDP_COMPONENT_RDMA0,
- DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_CCORR,
- DDP_COMPONENT_AAL0,
- DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER0,
- DDP_COMPONENT_DSC0,
- DDP_COMPONENT_MERGE0,
- DDP_COMPONENT_DP_INTF0,
-};
-
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -218,13 +203,6 @@ static const struct mtk_mmsys_driver_data
mt2701_mmsys_driver_data = {
.shadow_register = true,
};
-static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.main_path = mt7623_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -233,13 +211,6 @@ static const struct mtk_mmsys_driver_data
mt7623_mmsys_driver_data = {
.shadow_register = true,
};
-static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.main_path = mt2712_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -249,25 +220,11 @@ static const struct mtk_mmsys_driver_data
mt2712_mmsys_driver_data = {
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
};
-static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
};
-static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -275,13 +232,6 @@ static const struct mtk_mmsys_driver_data
mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
-static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_path = mt8183_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -289,13 +239,6 @@ static const struct mtk_mmsys_driver_data
mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
-static
[PATCH v4 3/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0". 2. Add mt8195 routing table settings of vdosys0. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 370 drivers/soc/mediatek/mtk-mmsys.c| 11 + 2 files changed, 381 insertions(+) create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index ..abfe94a30248 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H + +#define MT8195_VDO0_OVL_MOUT_EN0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1(0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE(1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0(0 << 22) + +#define MT8195_VDO0_SEL_OUT0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1(3 << 8) +#define
[PATCH v4 2/6] Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0"
This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254. Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys" to "mediatek,mt8195-vdosys0", we have to revert this patch and send a new patch with the new compatible. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 370 drivers/soc/mediatek/mtk-mmsys.c| 152 +--- drivers/soc/mediatek/mtk-mmsys.h| 6 - 3 files changed, 11 insertions(+), 517 deletions(-) delete mode 100644 drivers/soc/mediatek/mt8195-mmsys.h diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h deleted file mode 100644 index abfe94a30248.. --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H -#define __SOC_MEDIATEK_MT8195_MMSYS_H - -#define MT8195_VDO0_OVL_MOUT_EN0xf14 -#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0BIT(0) -#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0BIT(1) -#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1BIT(4) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1BIT(5) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) - -#define MT8195_VDO0_SEL_IN 0xf34 -#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) -#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) -#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) -#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) -#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) -#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) -#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) -#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) -#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) -#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) -#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) -#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) -#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1(0 << 20) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE(1 << 20) -#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) -#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) -#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) -#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) -#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0(0 << 22) - -#define MT8195_VDO0_SEL_OUT0xf38 -#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) -#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) -#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) -#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) -#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) -#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) -#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) -#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) -#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
