Re: [PATCH net-next v3 3/6] net: bcmasp: Add support for ASP2.0 Ethernet controller
On Fri, 19 May 2023 14:19:41 -0700 Justin Chen wrote: > Add support for the Broadcom ASP 2.0 Ethernet controller which is first > introduced with 72165. This controller features two distinct Ethernet > ports that can be independently operated. > > This patch supports: > > - Wake-on-LAN using magic packets > - basic ethtool operations (link, counters, message level) > - MAC destination address filtering (promiscuous, ALL_MULTI, etc.) There are some sparse warnings where (try building with C=1). Please also remove the inline keyword from all functions in source files, unless you actually checked that the compiler does the wrong thing. -- pw-bot: cr
Re: [git pull] drm fixes for 6.4-rc3
The pull request you sent on Sat, 20 May 2023 11:09:38 +1000: > git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-05-20 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/d635f6cc934bcd467c5d67148ece74632fd96abf Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html
Re: [v1 2/2] drm/panel: Support for Starry-ili9882t TDDI MIPI-DSI panel
Hi,Doug, Thank you very much for your suggestion. It seems that this
cannot be changed on the hardware(already discussed with vendor, TDDI's IC
design is this) we really want the touchscreen to power on and off
together with the panel, where the panel is in charge and the touchscreen
always powers on after the panel and powers off before the panel.=>As
shown in T16 in the datasheet, the current TDDI IC not only depends on the
power supply (the 1.8V power supply uses the same power supply for the
touch driver and the panel driver)， also depends on the RST state of the
panel. Only when the RST state is high touch HID can ready.
On Fri, May 19, 2023 at 4:02 PM Cong Yang <
yangco...@huaqin.corp-partner.google.com> wrote:
> The Starry-ili9882 panel also is a TDDI IC. From the datasheet,panel
> need the RST signal is high when touch communicate and also MIPI needs
> to keep the LP11 state before the lcm_reset pin is pulled high. So add
> enable_gpio_init_value and lp11_before_reset flag.
>
> Signed-off-by: Cong Yang
> ---
> .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 371 ++
> 1 file changed, 371 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index 7aaa85b0de8a..8d564df6e5e3 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -146,6 +146,344 @@ static const struct panel_init_cmd
> starry_himax83102_j02_init_cmd[] = {
> {},
> };
>
> +static const struct panel_init_cmd starry_ili9882t_init_cmd[] = {
> + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x01),
> + _INIT_DCS_CMD(0x00, 0x42),
> + _INIT_DCS_CMD(0x01, 0x11),
> + _INIT_DCS_CMD(0x02, 0x00),
> + _INIT_DCS_CMD(0x03, 0x00),
> +
> + _INIT_DCS_CMD(0x04, 0x01),
> + _INIT_DCS_CMD(0x05, 0x11),
> + _INIT_DCS_CMD(0x06, 0x00),
> + _INIT_DCS_CMD(0x07, 0x00),
> +
> + _INIT_DCS_CMD(0x08, 0x80),
> + _INIT_DCS_CMD(0x09, 0x81),
> + _INIT_DCS_CMD(0x0A, 0x71),
> + _INIT_DCS_CMD(0x0B, 0x00),
> +
> + _INIT_DCS_CMD(0x0C, 0x00),
> + _INIT_DCS_CMD(0x0E, 0x1A),
> +
> + _INIT_DCS_CMD(0x24, 0x00),
> + _INIT_DCS_CMD(0x25, 0x00),
> + _INIT_DCS_CMD(0x26, 0x00),
> + _INIT_DCS_CMD(0x27, 0x00),
> +
> + _INIT_DCS_CMD(0x2C, 0xD4),
> + _INIT_DCS_CMD(0xB9, 0x40),
> +
> + _INIT_DCS_CMD(0xB0, 0x11),
> +
> + _INIT_DCS_CMD(0xE6, 0x32),
> + _INIT_DCS_CMD(0xD1, 0x30),
> +
> + _INIT_DCS_CMD(0xD6, 0x55),
> +
> + _INIT_DCS_CMD(0xD0, 0x01),
> + _INIT_DCS_CMD(0xE3, 0x93),
> + _INIT_DCS_CMD(0xE4, 0x00),
> + _INIT_DCS_CMD(0xE5, 0x80),
> +
> + _INIT_DCS_CMD(0x31, 0x07),
> + _INIT_DCS_CMD(0x32, 0x07),
> + _INIT_DCS_CMD(0x33, 0x07),
> + _INIT_DCS_CMD(0x34, 0x07),
> + _INIT_DCS_CMD(0x35, 0x07),
> + _INIT_DCS_CMD(0x36, 0x01),
> + _INIT_DCS_CMD(0x37, 0x00),
> + _INIT_DCS_CMD(0x38, 0x28),
> + _INIT_DCS_CMD(0x39, 0x29),
> + _INIT_DCS_CMD(0x3A, 0x11),
> + _INIT_DCS_CMD(0x3B, 0x13),
> + _INIT_DCS_CMD(0x3C, 0x15),
> + _INIT_DCS_CMD(0x3D, 0x17),
> + _INIT_DCS_CMD(0x3E, 0x09),
> + _INIT_DCS_CMD(0x3F, 0x0D),
> + _INIT_DCS_CMD(0x40, 0x02),
> + _INIT_DCS_CMD(0x41, 0x02),
> + _INIT_DCS_CMD(0x42, 0x02),
> + _INIT_DCS_CMD(0x43, 0x02),
> + _INIT_DCS_CMD(0x44, 0x02),
> + _INIT_DCS_CMD(0x45, 0x02),
> + _INIT_DCS_CMD(0x46, 0x02),
> +
> + _INIT_DCS_CMD(0x47, 0x07),
> + _INIT_DCS_CMD(0x48, 0x07),
> + _INIT_DCS_CMD(0x49, 0x07),
> + _INIT_DCS_CMD(0x4A, 0x07),
> + _INIT_DCS_CMD(0x4B, 0x07),
> + _INIT_DCS_CMD(0x4C, 0x01),
> + _INIT_DCS_CMD(0x4D, 0x00),
> + _INIT_DCS_CMD(0x4E, 0x28),
> + _INIT_DCS_CMD(0x4F, 0x29),
> + _INIT_DCS_CMD(0x50, 0x10),
> + _INIT_DCS_CMD(0x51, 0x12),
> + _INIT_DCS_CMD(0x52, 0x14),
> + _INIT_DCS_CMD(0x53, 0x16),
> + _INIT_DCS_CMD(0x54, 0x08),
> + _INIT_DCS_CMD(0x55, 0x0C),
> + _INIT_DCS_CMD(0x56, 0x02),
> + _INIT_DCS_CMD(0x57, 0x02),
> + _INIT_DCS_CMD(0x58, 0x02),
> + _INIT_DCS_CMD(0x59, 0x02),
> + _INIT_DCS_CMD(0x5A, 0x02),
> + _INIT_DCS_CMD(0x5B, 0x02),
> + _INIT_DCS_CMD(0x5C, 0x02),
> +
> + _INIT_DCS_CMD(0x61, 0x07),
> + _INIT_DCS_CMD(0x62, 0x07),
> + _INIT_DCS_CMD(0x63, 0x07),
> + _INIT_DCS_CMD(0x64, 0x07),
> + _INIT_DCS_CMD(0x65, 0x07),
> + _INIT_DCS_CMD(0x66, 0x01),
> + _INIT_DCS_CMD(0x67, 0x00),
> + _INIT_DCS_CMD(0x68, 0x28),
> + _INIT_DCS_CMD(0x69, 0x29),
> + _INIT_DCS_CMD(0x6A, 0x16),
> + _INIT_DCS_CMD(0x6B, 0x14),
> + _INIT_DCS_CMD(0x6C, 0x12),
> + _INIT_DCS_CMD(0x6D, 0x10),
> + _INIT_DCS_CMD(0x6E, 0x0C),
> + _INIT_DCS_CMD(0x6F, 0x08),
> + _INIT_DCS_CMD(0x70, 0x02),
> + _INIT_DCS_CMD(0x71, 0x02),
Re: [PATCH v4 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
On 19/05/2023 20:04, Konrad Dybcio wrote: It got broken at some point, fix it up. Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v4 09/12] drm/msm: mdss: Add SM6375 support
On 19/05/2023 20:04, Konrad Dybcio wrote: Add support for MDSS on SM6375. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v4 08/12] drm/msm/dpu: Add SM6375 support
On 19/05/2023 20:04, Konrad Dybcio wrote: Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + 4 files changed, 156 insertions(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 3/3] drm/msm/dp: Clean up pdev/dev duplication in dp_power
On 15/05/2023 06:02, Bjorn Andersson wrote:
The dp_power module keeps track of both the DP controller's struct
platform_device and struct device - with the prior pulled out of the
dp_parser module.
Clean up the duplication by dropping the platform_device reference and
just track the passed struct device.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_power.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index 031d2eefef07..9be645f91211 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -14,7 +14,6 @@
struct dp_power_private {
struct dp_parser *parser;
- struct platform_device *pdev;
struct device *dev;
struct drm_device *drm_dev;
struct clk *link_clk_src;
@@ -28,7 +27,7 @@ static int dp_power_clk_init(struct dp_power_private *power)
{
int rc = 0;
struct dss_module_power *core, *ctrl, *stream;
- struct device *dev = >pdev->dev;
+ struct device *dev = power->dev;
core = >parser->mp[DP_CORE_PM];
ctrl = >parser->mp[DP_CTRL_PM];
@@ -153,7 +152,7 @@ int dp_power_client_init(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
- pm_runtime_enable(>pdev->dev);
+ pm_runtime_enable(power->dev);
return dp_power_clk_init(power);
}
@@ -164,7 +163,7 @@ void dp_power_client_deinit(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
- pm_runtime_disable(>pdev->dev);
+ pm_runtime_disable(power->dev);
}
int dp_power_init(struct dp_power *dp_power, bool flip)
@@ -174,11 +173,11 @@ int dp_power_init(struct dp_power *dp_power, bool flip)
power = container_of(dp_power, struct dp_power_private, dp_power);
- pm_runtime_get_sync(>pdev->dev);
+ pm_runtime_get_sync(power->dev);
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
if (rc)
- pm_runtime_put_sync(>pdev->dev);
+ pm_runtime_put_sync(power->dev);
return rc;
}
@@ -190,7 +189,7 @@ int dp_power_deinit(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
- pm_runtime_put_sync(>pdev->dev);
+ pm_runtime_put_sync(power->dev);
return 0;
}
@@ -199,12 +198,11 @@ struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser)
Technically we don't even need to pass struct device here, we can get it
from parser->pdev->dev.
struct dp_power_private *power;
struct dp_power *dp_power;
- power = devm_kzalloc(>pdev->dev, sizeof(*power), GFP_KERNEL);
+ power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
if (!power)
return ERR_PTR(-ENOMEM);
power->parser = parser;
- power->pdev = parser->pdev;
power->dev = dev;
dp_power = >dp_power;
--
With best wishes
Dmitry
Re: [PATCH 2/3] drm/msm/dp: Clean up logs dp_power module
On 15/05/2023 06:02, Bjorn Andersson wrote:
The clk_bulk API already provides error messages indicating which
specific clock in the request for which the operation failed, further
more these errors are associated with the specific DisplayPort
controller (rather than the shared drm_device). The additional error
messages int he dp_power module does thereby not provide any benefit.
While at it, none of the dp_power handles passed to these functions are
dynamic in nature, so there should not be any need for runtime checking
them. Drop these as well.
It might have been slightly better to have this split into two patches,
but as this is a debug/logs only, it's fine with me.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/dp/dp_power.c | 62 +--
1 file changed, 9 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index c0aaabb03389..031d2eefef07 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -35,25 +35,16 @@ static int dp_power_clk_init(struct dp_power_private *power)
stream = >parser->mp[DP_STREAM_PM];
rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks);
- if (rc) {
- DRM_ERROR("failed to get %s clk. err=%d\n",
- dp_parser_pm_name(DP_CORE_PM), rc);
+ if (rc)
return rc;
- }
rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks);
- if (rc) {
- DRM_ERROR("failed to get %s clk. err=%d\n",
- dp_parser_pm_name(DP_CTRL_PM), rc);
+ if (rc)
return -ENODEV;
- }
rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks);
- if (rc) {
- DRM_ERROR("failed to get %s clk. err=%d\n",
- dp_parser_pm_name(DP_CTRL_PM), rc);
+ if (rc)
return -ENODEV;
- }
return 0;
}
@@ -121,11 +112,9 @@ int dp_power_clk_enable(struct dp_power *dp_power,
mp = >parser->mp[DP_CORE_PM];
rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
- if (rc) {
- DRM_ERROR("fail to enable clks: %s. err=%d\n",
- dp_parser_pm_name(DP_CORE_PM), rc);
+ if (rc)
return rc;
- }
+
dp_power->core_clks_on = true;
}
}
@@ -133,10 +122,8 @@ int dp_power_clk_enable(struct dp_power *dp_power,
mp = >parser->mp[pm_type];
if (enable) {
rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks);
- if (rc) {
- DRM_ERROR("failed to enable clks, err: %d\n", rc);
+ if (rc)
return rc;
- }
} else {
clk_bulk_disable_unprepare(mp->num_clk, mp->clocks);
}
@@ -162,34 +149,19 @@ int dp_power_clk_enable(struct dp_power *dp_power,
int dp_power_client_init(struct dp_power *dp_power)
{
- int rc = 0;
struct dp_power_private *power;
- if (!dp_power) {
- DRM_ERROR("invalid power data\n");
- return -EINVAL;
- }
-
power = container_of(dp_power, struct dp_power_private, dp_power);
pm_runtime_enable(>pdev->dev);
- rc = dp_power_clk_init(power);
- if (rc)
- DRM_ERROR("failed to init clocks %d\n", rc);
-
- return rc;
+ return dp_power_clk_init(power);
}
void dp_power_client_deinit(struct dp_power *dp_power)
{
struct dp_power_private *power;
- if (!dp_power) {
- DRM_ERROR("invalid power data\n");
- return;
- }
-
power = container_of(dp_power, struct dp_power_private, dp_power);
pm_runtime_disable(>pdev->dev);
@@ -200,25 +172,14 @@ int dp_power_init(struct dp_power *dp_power, bool flip)
int rc = 0;
struct dp_power_private *power = NULL;
- if (!dp_power) {
- DRM_ERROR("invalid power data\n");
- return -EINVAL;
- }
-
power = container_of(dp_power, struct dp_power_private, dp_power);
pm_runtime_get_sync(>pdev->dev);
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
- if (rc) {
- DRM_ERROR("failed to enable DP core clocks, %d\n", rc);
- goto exit;
- }
-
- return 0;
+ if (rc)
+ pm_runtime_put_sync(>pdev->dev);
-exit:
- pm_runtime_put_sync(>pdev->dev);
return rc;
}
@@ -238,11 +199,6 @@ struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser)
struct dp_power_private *power;
struct dp_power *dp_power;
- if (!parser) {
- DRM_ERROR("invalid input\n");
- return ERR_PTR(-EINVAL);
-
Re: [PATCH 1/3] drm/msm/dp: Drop now unused dp_hpd module
On 15/05/2023 06:02, Bjorn Andersson wrote: The dp_hpd module is a remnant from the downstream design and is now completely unused. Drop it and all references to it. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_debug.c | 8 ++- drivers/gpu/drm/msm/dp/dp_debug.h | 12 ++--- drivers/gpu/drm/msm/dp/dp_display.c | 35 + drivers/gpu/drm/msm/dp/dp_hpd.c | 67 - drivers/gpu/drm/msm/dp/dp_hpd.h | 78 - drivers/gpu/drm/msm/dp/dp_panel.h | 1 - 6 files changed, 11 insertions(+), 190 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c delete mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.h I think this is not complete. Could you please check if https://patchwork.freedesktop.org/patch/433883/?series=90198=1 works for you? -- With best wishes Dmitry
[git pull] drm fixes for 6.4-rc3
Hi Linus, Regular fixes pull, amdgpu and msm make up most of these, nothing too serious, also one i915 and one exynos. I didn't get a misc fixes pull this week (one of the maintainers is off, so have to engage the backup) so I think there are a few outstanding patches that will show up next week, Dave. drm-fixes-2023-05-20: drm fixes for 6.4-rc3 amdgpu: - update gfx11 clock counter logic - Fix a race when disabling gfxoff on gfx10/11 for profiling - Raven/Raven2/PCO clock counter fix - Add missing get_vbios_fb_size for GMC 11 - Fix a spurious irq warning in the device remove case - Fix possible power mode mismatch between driver and PMFW - USB4 fix exynos: - fix build warning i915: - fix missing NULL check in HDCP code msm: - display: - msm8998: fix fetch and qos to align with downstream - msm8998: fix LM pairs to align with downstream - remove unused INTF0 interrupt mask on some chipsets - remove TE2 block from relevant chipsets - relocate non-MDP_TOP offset to different header - fix some indentation - fix register offets/masks for dither blocks - make ping-ping block length 0 - remove duplicated defines - fix log mask for writeback block - unregister the hdmi codec for dp during unbind - fix yaml warnings - gpu: - fix submit error path leak - arm-smmu-qcom fix for regression that broke per-process page tables - fix no-iommu crash The following changes since commit f1fcbaa18b28dec10281551dfe6ed3a3ed80e3d6: Linux 6.4-rc2 (2023-05-14 12:51:40 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-05-20 for you to fetch changes up to 79ef1c9d14c65a5c3f7eec47389d8c2a33be8e8d: Merge tag 'amd-drm-fixes-6.4-2023-05-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes (2023-05-19 11:26:21 +1000) drm fixes for 6.4-rc3 amdgpu: - update gfx11 clock counter logic - Fix a race when disabling gfxoff on gfx10/11 for profiling - Raven/Raven2/PCO clock counter fix - Add missing get_vbios_fb_size for GMC 11 - Fix a spurious irq warning in the device remove case - Fix possible power mode mismatch between driver and PMFW - USB4 fix exynos: - fix build warning i915: - fix missing NULL check in HDCP code msm: - display: - msm8998: fix fetch and qos to align with downstream - msm8998: fix LM pairs to align with downstream - remove unused INTF0 interrupt mask on some chipsets - remove TE2 block from relevant chipsets - relocate non-MDP_TOP offset to different header - fix some indentation - fix register offets/masks for dither blocks - make ping-ping block length 0 - remove duplicated defines - fix log mask for writeback block - unregister the hdmi codec for dp during unbind - fix yaml warnings - gpu: - fix submit error path leak - arm-smmu-qcom fix for regression that broke per-process page tables - fix no-iommu crash Alex Deucher (2): drm/amdgpu/gfx11: update gpu_clock_counter logic drm/amdgpu/gmc11: implement get_vbios_fb_size() Arnaud Vrac (2): drm/msm/dpu: tweak msm8998 hw catalog values drm/msm/dpu: tweak lm pairings in msm8998 hw catalog Arnd Bergmann (1): drm/exynos: fix g2d_open/close helper function definitions Bas Nieuwenhuizen (1): drm/amdgpu/gfx10: Disable gfxoff before disabling powergating. Dave Airlie (4): Merge tag 'exynos-drm-fixes-for-v6.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes Merge tag 'drm-intel-fixes-2023-05-17' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes Merge tag 'drm-msm-fixes-2023-05-17' of https://gitlab.freedesktop.org/drm/msm into drm-fixes Merge tag 'amd-drm-fixes-6.4-2023-05-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes Evan Quan (1): drm/amd/pm: fix possible power mode mismatch between driver and PMFW Guchun Chen (1): drm/amdgpu: skip disabling fence driver src_irqs when device is unplugged Guilherme G. Piccoli (1): drm/amdgpu/gfx11: Adjust gfxoff before powergating on gfx11 as well Jesse Zhang (1): drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id Jianhua Lu (1): dt-bindings: display/msm: dsi-controller-main: Document qcom, master-dsi and qcom, sync-dual-dsi Luca Weiss (1): drm/msm/iommu: Fix null pointer dereference in no-IOMMU case Marijn Suijten (9): drm/msm/dpu: Assign missing writeback log_mask drm/msm/dpu: Remove unused INTF0 interrupt mask from SM6115/QCM2290 drm/msm/dpu: Remove TE2 block and feature from DPU >= 5.0.0 hardware drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header drm/msm/dpu: Reindent REV_7xxx interrupt masks with tabs drm/msm/dpu: Fix PP_BLK_DIPHER -> DITHER typo drm/msm/dpu: Use V2 DITHER PINGPONG sub-block in SM8[34]50/SC8280XP drm/msm/dpu: Set PINGPONG block length to zero
[PATCH 2/2] drm/msm/dsi: use mult_frac for pclk_bpp calculation
Simplify calculatoins around pixel_clk_rate division. Replace common
pattern of doing 64-bit multiplication and then a do_div() call with
simpler mult_frac call.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2b257b459974..744f2398a6d6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -585,7 +585,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi);
- u64 pclk_bpp = (u64)pclk_rate * bpp;
+ unsigned long pclk_bpp;
if (lanes == 0) {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
@@ -594,9 +594,9 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
/* CPHY "byte_clk" is in units of 16 bits */
if (msm_host->cphy_mode)
- do_div(pclk_bpp, (16 * lanes));
+ pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes);
else
- do_div(pclk_bpp, (8 * lanes));
+ pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes);
return pclk_bpp;
}
@@ -627,15 +627,12 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
u32 bpp = dsi_get_bpp(msm_host->format);
- u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
dsi_calc_pclk(msm_host, is_bonded_dsi);
- pclk_bpp = (u64)msm_host->pixel_clk_rate * bpp;
- do_div(pclk_bpp, 8);
- msm_host->src_clk_rate = pclk_bpp;
+ msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8);
/*
* esc clock is byte clock followed by a 4 bit divider,
--
2.39.2
[PATCH 1/2] drm/msm/dsi: remove extra call to dsi_get_pclk_rate()
In dsi_calc_clk_rate_v2() there is no need to call dsi_get_pclk_rate(). This functions has just been called and it's result is stored at msm_host->pixel_clk_rate. Use this variable directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 961689a255c4..2b257b459974 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -633,7 +633,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) dsi_calc_pclk(msm_host, is_bonded_dsi); - pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp; + pclk_bpp = (u64)msm_host->pixel_clk_rate * bpp; do_div(pclk_bpp, 8); msm_host->src_clk_rate = pclk_bpp; -- 2.39.2
Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
On 5/19/2023 11:45 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticated only after the GSC auth
step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 94 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 16 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +
include/uapi/drm/i915_drm.h | 3 +-
5 files changed, 91 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c189ede4ef55..60f95d98e5fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,7 @@
#include "intel_huc.h"
#include "intel_huc_print.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include
#include
@@ -106,7 +107,7 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
{
struct intel_huc *huc = container_of(hrtimer, struct intel_huc,
delayed_load.timer);
- if (!intel_huc_is_authenticated(huc)) {
+ if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
@@ -124,7 +125,7 @@ static void huc_delayed_load_start(struct
intel_huc *huc)
{
ktime_t delay;
- GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
/*
* On resume we don't have to wait for MEI-GSC to be re-probed,
but we
@@ -284,13 +285,23 @@ void intel_huc_init_early(struct intel_huc *huc)
}
if (GRAPHICS_VER(i915) >= 11) {
- huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
- huc->status.mask = HUC_LOAD_SUCCESSFUL;
- huc->status.value = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
} else {
- huc->status.reg = HUC_STATUS2;
- huc->status.mask = HUC_FW_VERIFIED;
- huc->status.value = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED;
+ }
+
+ if (IS_DG2(i915)) {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL;
+ } else {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
HECI_FWSTS5(MTL_GSC_HECI1_BASE);
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask =
HECI_FWSTS5_HUC_AUTH_DONE;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value =
HECI_FWSTS5_HUC_AUTH_DONE;
}
}
@@ -381,28 +392,39 @@ void intel_huc_suspend(struct intel_huc *huc)
delayed_huc_load_complete(huc);
}
-int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+static const char *auth_mode_string(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
+{
+ bool partial = !huc->loaded_via_gsc && huc->fw.is_meu_binary &&
+ type == INTEL_HUC_AUTH_BY_GUC;
partial = !loaded_via_gsc?
If it is not a GSC load then there is no two stage authentication, is
there? Does that mean the single stage auth does not count as 'all
workloads' even on platforms where two stage is not supported?
Single step authentication always counts as "all workloads". The auth is
partial only if this is a DMA (i.e. non-gsc) load with a gsc-enabled
binary and we're doing an auth via GuC, which is what the condition
above is checking.
+
+ return partial ? "clear media" : "all workloads";
+}
+
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
{
struct intel_gt *gt = huc_to_gt(huc);
int ret;
ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
+ huc->status[type].reg,
+
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 5/19/2023 11:03 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "MEU binary" for
clarity, while the latter is now based on the fuse instead of the binary
format. This way, all the legacy load paths are automatically taken
(including the auth by GuC) without having to implement further code
changes.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 27 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 14 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 062ff914b274..c189ede4ef55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,38 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool fw_is_meu = huc->fw.is_meu_binary;
/*
* The fuse for HuC load via GSC is only valid on platforms
that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !fw_is_meu) {
+ huc_err(huc, "HW requires a MEU blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we
need it */
+ /*
+ * Newer meu blobs contain the old FW structure inside. If we found
+ * that, we can use it to load the legacy way.
+ */
+ if (!huc->loaded_via_gsc && fw_is_meu &&
!huc->fw.dma_start_offset) {
+ huc_err(huc," HW in legacy mode, but we have an incompatible
meu blob\n");
Leading space in the message? MEU or meu?
As mentioned in the reply on the previous patch, I'm going to drop the
meu tag.
+ return -ENOEXEC;
+ }
+
+ /* make sure we can access the GSC if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
- fw_needs_gsc) {
+ !HAS_ENGINE(gt, GSC0) && huc->loaded_via_gsc) {
Should that be || !HAS_ENGINE ?
No. The config check is for DG2, while the engine check is for MTL+. We
need one of the two to be true, not both, so we only fail if both are false.
huc_info(huc, "can't load due to missing MEI modules\n");
'missing MEI modules or GSC engine'?
I'll update it to "missing requirements" or something like that.
return -EIO;
}
- huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n",
str_yes_no(huc->loaded_via_gsc));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index db555b3c1f56..345e1b9aa062 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -39,6 +39,8 @@ struct intel_huc {
struct notifier_block nb;
enum intel_huc_delayed_load_status status;
} delayed_load;
+
+ bool loaded_via_gsc;
};
int intel_huc_sanitize(struct intel_huc *huc);
@@ -73,7 +75,7 @@ static inline bool intel_huc_is_used(struct
intel_huc *huc)
static inline bool intel_huc_is_loaded_by_gsc(const struct
intel_huc *huc)
{
- return huc->fw.loaded_via_gsc;
+ return huc->loaded_via_gsc;
}
static inline bool intel_huc_wait_required(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index f1c973e1c676..88ad2c322c4a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -34,7 +34,7 @@ int intel_huc_fw_get_binary_info(struct intel_uc_fw
*huc_fw, const void *data, s
size_t min_size = sizeof(*header);
int i;
- if (!huc_fw->loaded_via_gsc) {
+ if (!huc_fw->is_meu_binary) {
huc_err(huc, "Invalid FW type MEU parsing!\n");
[PATCH v2 3/4] drm/msm/dpu: use PINGPONG_NONE for LMs with no PP attached
On msm8998/sdm845 some LM blocks do not have corresponding PINGPONG
block. Currently the driver uses PINGPONG_MAX for such cases. Switch
that to use PINGPONG_NONE instead, which is more logical.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
5 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 37a52b4ef8d3..3c732a0360c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -104,9 +104,9 @@ static const struct dpu_lm_cfg msm8998_lm[] = {
LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_2, LM_5, 0),
LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_MAX, 0, 0),
+ _lm_sblk, PINGPONG_NONE, 0, 0),
LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_MAX, 0, 0),
+ _lm_sblk, PINGPONG_NONE, 0, 0),
LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 0b727252671c..36ea1af10894 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -102,9 +102,9 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_2, LM_5, 0),
LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
- _lm_sblk, PINGPONG_MAX, 0, 0),
+ _lm_sblk, PINGPONG_NONE, 0, 0),
LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
- _lm_sblk, PINGPONG_MAX, 0, 0),
+ _lm_sblk, PINGPONG_NONE, 0, 0),
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1cb5699a5a47..677048cc3b7d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -529,7 +529,7 @@ struct dpu_sspp_cfg {
* @base register offset of this block
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
- * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
+ * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
*/
struct dpu_lm_cfg {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 1913a19de733..02a0f48aac94 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -191,7 +191,8 @@ enum dpu_dsc {
};
enum dpu_pingpong {
- PINGPONG_0 = 1,
+ PINGPONG_NONE,
+ PINGPONG_0,
PINGPONG_1,
PINGPONG_2,
PINGPONG_3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index d5a06628885e..bf7b8e7c45b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -117,7 +117,7 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_mixer *hw;
const struct dpu_lm_cfg *lm = >mixer[i];
- if (lm->pingpong == PINGPONG_MAX) {
+ if (lm->pingpong == PINGPONG_NONE) {
DPU_DEBUG("skip mixer %d without pingpong\n", lm->id);
continue;
}
--
2.39.2
[PATCH v2 2/4] drm/msm/dpu: remove futile checks from dpu_rm_init()
dpu_rm_init() contains checks for block->id values. These were logical
in the vendor driver, when one can not be sure which values were passed
from DT. In the upstream driver this is not necessary: the catalog is a
part of the driver, we control specified IDs.
Suggested-by: Marijn Suijten
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index dffd3dd0a877..d5a06628885e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -122,10 +122,6 @@ int dpu_rm_init(struct dpu_rm *rm,
continue;
}
- if (lm->id < LM_0 || lm->id >= LM_MAX) {
- DPU_ERROR("skip mixer %d with invalid id\n", lm->id);
- continue;
- }
hw = dpu_hw_lm_init(lm, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -139,10 +135,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_merge_3d *hw;
const struct dpu_merge_3d_cfg *merge_3d = >merge_3d[i];
- if (merge_3d->id < MERGE_3D_0 || merge_3d->id >= MERGE_3D_MAX) {
- DPU_ERROR("skip merge_3d %d with invalid id\n",
merge_3d->id);
- continue;
- }
hw = dpu_hw_merge_3d_init(merge_3d, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -157,10 +149,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_pingpong *hw;
const struct dpu_pingpong_cfg *pp = >pingpong[i];
- if (pp->id < PINGPONG_0 || pp->id >= PINGPONG_MAX) {
- DPU_ERROR("skip pingpong %d with invalid id\n", pp->id);
- continue;
- }
hw = dpu_hw_pingpong_init(pp, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -177,10 +165,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_intf *hw;
const struct dpu_intf_cfg *intf = >intf[i];
- if (intf->id < INTF_0 || intf->id >= INTF_MAX) {
- DPU_ERROR("skip intf %d with invalid id\n", intf->id);
- continue;
- }
hw = dpu_hw_intf_init(intf, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -194,11 +178,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_wb *hw;
const struct dpu_wb_cfg *wb = >wb[i];
- if (wb->id < WB_0 || wb->id >= WB_MAX) {
- DPU_ERROR("skip intf %d with invalid id\n", wb->id);
- continue;
- }
-
hw = dpu_hw_wb_init(wb, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -212,10 +191,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_ctl *hw;
const struct dpu_ctl_cfg *ctl = >ctl[i];
- if (ctl->id < CTL_0 || ctl->id >= CTL_MAX) {
- DPU_ERROR("skip ctl %d with invalid id\n", ctl->id);
- continue;
- }
hw = dpu_hw_ctl_init(ctl, mmio, cat->mixer_count, cat->mixer);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -229,10 +204,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_dspp *hw;
const struct dpu_dspp_cfg *dspp = >dspp[i];
- if (dspp->id < DSPP_0 || dspp->id >= DSPP_MAX) {
- DPU_ERROR("skip dspp %d with invalid id\n", dspp->id);
- continue;
- }
hw = dpu_hw_dspp_init(dspp, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
@@ -259,11 +230,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_sspp *hw;
const struct dpu_sspp_cfg *sspp = >sspp[i];
- if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) {
- DPU_ERROR("skip intf %d with invalid id\n", sspp->id);
- continue;
- }
-
hw = dpu_hw_sspp_init(sspp, mmio, cat->ubwc);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
--
2.39.2
[PATCH v2 1/4] drm/msm/dpu: replace IS_ERR_OR_NULL with IS_ERR during DSC init
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If
the value is NULL, then the function will return 0 instead of a proper
return code. Moreover dpu_hw_dsc_init() can not return NULL.
Replace the IS_ERR_OR_NULL() call with IS_ERR().
This follows the commit 740828c73a36 ("drm/msm/dpu: fix error handling
in dpu_rm_init"), which removed IS_ERR_OR_NULL() from RM init code, but
then the commit f2803ee91a41 ("drm/msm/disp/dpu1: Add DSC support in
RM") added it for DSC init.
Suggested-by: Marijn Suijten
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f0fc70422e56..dffd3dd0a877 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -247,7 +247,7 @@ int dpu_rm_init(struct dpu_rm *rm,
const struct dpu_dsc_cfg *dsc = >dsc[i];
hw = dpu_hw_dsc_init(dsc, mmio);
- if (IS_ERR_OR_NULL(hw)) {
+ if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed dsc object creation: err %d\n", rc);
goto fail;
--
2.39.2
[PATCH v2 4/4] drm/msm/dpu: move PINGPONG_NONE check to dpu_lm_init()
Move the check for lm->pingpong being not NONE from dpu_rm_init() to
dpu_lm_init(), following the change to dpu_hw_intf_init().
Suggested-by: Marijn Suijten
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 5 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 214f207ddf8a..d1c3bd8379ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -161,6 +161,11 @@ struct dpu_hw_mixer *dpu_hw_lm_init(const struct
dpu_lm_cfg *cfg,
{
struct dpu_hw_mixer *c;
+ if (cfg->pingpong == PINGPONG_NONE) {
+ DPU_DEBUG("skip mixer %d without pingpong\n", cfg->id);
+ return NULL;
+ }
+
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bf7b8e7c45b1..2ca3c666e22f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -117,11 +117,6 @@ int dpu_rm_init(struct dpu_rm *rm,
struct dpu_hw_mixer *hw;
const struct dpu_lm_cfg *lm = >mixer[i];
- if (lm->pingpong == PINGPONG_NONE) {
- DPU_DEBUG("skip mixer %d without pingpong\n", lm->id);
- continue;
- }
-
hw = dpu_hw_lm_init(lm, mmio);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
--
2.39.2
[PATCH v2 0/4] drm/msm/dpu: simplity RM code
Implement several small simplifications for the DPU resource manager. The ideas behind these patches were suggested by Marijn. Changes since v1: - Reworded commit message for the patch 1 (Marijn) - Fixed documentation for dpu_lm_cfg::pingpong (Marijn) - Added Suggested-by to the last patch (Marijn) Dmitry Baryshkov (4): drm/msm/dpu: replace IS_ERR_OR_NULL with IS_ERR during DSC init drm/msm/dpu: remove futile checks from dpu_rm_init() drm/msm/dpu: use PINGPONG_NONE for LMs with no PP attached drm/msm/dpu: move PINGPONG_NONE check to dpu_lm_init() .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 +- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 4 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 41 +-- 6 files changed, 13 insertions(+), 46 deletions(-) -- 2.39.2
Re: [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On 20/05/2023 00:16, Rodrigo Vivi wrote: On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote: On 19/04/2023 18:43, Mark Yacoub wrote: Hi all, This is v10 of the HDCP patches. The patches are authored by Sean Paul. I rebased and addressed the review comments in v6-v10. Main change in v10 is handling the kernel test bot warnings. Patches 1-4 focus on moving the common HDCP helpers to common DRM. This introduces a slight change in the original intel flow as it splits the unique driver protocol from the generic implementation. Patches 5-7 split the HDCP flow on the i915 driver to make use of the common DRM helpers. Patches 8-10 implement HDCP on MSM driver. Thanks, -Mark Yacoub Sean Paul (10): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 dt-bindings: msm/dp: Add bindings for HDCP registers arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller Dear i915 maintainers, I wanted to ping you regarding this patch series. If there are no comments for the series from you side, would it be possible to land Intel-specific and generic patches into drm-intel tree? We will continue working on the msm specific parts and merge them through the msm tree. pushed to drm-intel-next. should be propagated in a few weeks to drm-next on our next pull request. Probably there is some kind of confusion here. You've pushed the DSC patches, while the response was sent to the HDCP series. -- With best wishes Dmitry
Re: [PATCH v3 5/5] drm/msm/dsi: Remove incorrect references to slice_count
On 5/19/2023 2:24 PM, Marijn Suijten wrote:
On 2023-05-19 14:17:30, Jessica Zhang wrote:
Currently, slice_count is being used to calculate word count and
pkt_per_line. In downstream, these values are calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice per packet. For example, it is
possible to have cases where there are multiple soft slices per interface
but the panel specifies only one slice per packet.
Thus, use the default value of one slice per packet and remove slice_count
from the aforementioned calculations.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Fixes: bc6b6ff8135c ("drm/msm/dsi: Use DSC slice(s) packet size to compute word
count")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index d04f8bbd707d..8c8858ee59ec 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -866,18 +866,15 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
*/
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
- /*
-* If slice_count is greater than slice_per_intf
-* then default to 1. This can happen during partial
-* update.
-*/
- if (dsc->slice_count > slice_per_intf)
- dsc->slice_count = 1;
-
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+
+ /*
+* Default to 1 slice_per_pkt, so pkt_per_line will be equal to
+* slice per intf.
+*/
+ pkt_per_line = slice_per_intf;
Same as the comment below, perhaps it is a good idea to clarify in the
comment here that the original value wa *multiplied by* slice_per_pkt?
Otherwise this default of 1 is "invisible".
Hi Marijn,
Acked.
Alternatively we could have a `const slice_per_pkt = 1;` at the top, and
have the comment (the elaborate one from below) there?
Since the default slice_per_pkt = 1 and there's only 2 places where I
have to add a clarifying comment, I think having a separate
slice_per_pkt variable is a bit redundant.
Plus, if support for multiple slice_per_pkt values is added in the
future, we'd also have to drop this variable anyways.
Thanks,
Jessica Zhang
- Marijn
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -1001,7 +998,14 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
if (!msm_host->dsc)
wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
else
- wc = msm_host->dsc->slice_chunk_size *
msm_host->dsc->slice_count + 1;
+ /*
+* When DSC is enabled, WC = slice_chunk_size *
slice_per_packet + 1.
+* Currently, the driver only supports default value of
slice_per_packet = 1
+*
+* TODO: Expand mipi_dsi_device struct to hold
slice_per_packet info
+* and adjust DSC math to account for
slice_per_packet.
+*/
+ wc = msm_host->dsc->slice_chunk_size + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
2.40.1
Re: [PATCH v2] drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK
On 20.05.2023 00:00, Abhinav Kumar wrote:
>
>
> On 5/19/2023 11:49 AM, Konrad Dybcio wrote:
>> DPU5 and newer targets enable this unconditionally. Move it from the
>> SC7280 mask to the SC7180 one.
>>
>
> You mean DPU 5.0.0 right?
Yep!
>
>> Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280
>> target")
>> Reviewed-by: Dmitry Baryshkov
>> Reviewed-by: Marijn Suijten
>> Signed-off-by: Konrad Dybcio
>> ---
>
> I have cross-checked all the chipsets affected by this and confirmed
> DATA_HCTL is present and those 3 registers programmed with that feature bit
> are valid, hence
>
> Reviewed-by: Abhinav Kumar
Thanks!
Konrad
>
[Bug 217464] New: Radeon Driver Crash
https://bugzilla.kernel.org/show_bug.cgi?id=217464 Bug ID: 217464 Summary: Radeon Driver Crash Product: Drivers Version: 2.5 Hardware: AMD OS: Linux Status: NEW Severity: high Priority: P3 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: neilsi...@gmail.com Regression: No I have a Dell Precision M4800 laptop running Debian with a custom built vanilla kernel 6.3.3 taken from kernel.org with this GPU shown in lspci: 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Venus XT [Radeon HD 8870M / R9 M270X/M370X] (rev ff) I have HDMI out connected to my TV to play video games and watch movies, with the laptop lid shut. Whenever I play a 3D OpenGL game or use VLC to watch videos with hardware rendering enabled, I get a driver crash after a few minutes (more frequently and reliably reproduced with the OpenGL video game). The kernel stays up and I can ssh into it, but the TV screen loses signal. Heres the dmesg output: [30834.383138] radeon :01:00.0: ring 0 stalled for more than 10236msec [30834.383144] radeon :01:00.0: GPU lockup (current fence id 0x0006080c last fence id 0x00060812 on ring 0) [30835.171667] BUG: unable to handle page fault for address: ae54809f1ffc [30835.171672] #PF: supervisor read access in kernel mode [30835.171674] #PF: error_code(0x) - not-present page [30835.171675] PGD 10067 P4D 10067 PUD 0 [30835.171678] Oops: [#1] PREEMPT SMP PTI [30835.171680] CPU: 0 PID: 13942 Comm: kworker/0:2H Tainted: GW E 6.3.3 #6 [30835.171683] Hardware name: Dell Inc. Precision M4800/0T3YTY, BIOS A09 06/26/2014 [30835.171684] Workqueue: radeon-crtc radeon_flip_work_func [radeon] [30835.171731] RIP: 0010:radeon_ring_backup+0xc4/0x140 [radeon] [30835.171764] Code: cd 49 89 06 48 85 c0 74 6d 41 8d 7c 24 ff 31 d2 48 c1 e7 02 eb 07 49 8b 06 48 83 c2 04 48 8b 75 10 8d 4b 01 89 db 48 8d 34 9e <8b> 36 89 34 10 23 4d 5c 89 cb 48 39 d7 75 dd 4c 89 ef e8 85 b7 b2 [30835.171766] RSP: 0018:ae5083217d60 EFLAGS: 00010206 [30835.171768] RAX: 8907ce60 RBX: RCX: [30835.171769] RDX: RSI: ae54809f1ffc RDI: 000cb400 [30835.171770] RBP: 8905018895c0 R08: R09: 0006 [30835.171771] R10: 0002 R11: 0100 R12: 00032d01 [30835.171772] R13: 8905018895a0 R14: ae5083217dc0 R15: 890501888000 [30835.171774] FS: () GS:89081dc0() knlGS: [30835.171775] CS: 0010 DS: ES: CR0: 80050033 [30835.171776] CR2: ae54809f1ffc CR3: 00037a61a003 CR4: 001706f0 [30835.171777] DR0: DR1: DR2: [30835.171778] DR3: DR6: fffe0ff0 DR7: 0400 [30835.171779] Call Trace: [30835.171791] [30835.171794] radeon_gpu_reset+0xb3/0x300 [radeon] [30835.171827] ? radeon_fence_wait_timeout+0x7c/0xe0 [radeon] [30835.171854] radeon_flip_work_func+0x201/0x260 [radeon] [30835.171884] ? __schedule+0x3c7/0xaa0 [30835.171888] process_one_work+0x1e5/0x3f0 [30835.171891] ? __pfx_worker_thread+0x10/0x10 [30835.171893] worker_thread+0x54/0x3a0 [30835.171894] ? __pfx_worker_thread+0x10/0x10 [30835.171895] kthread+0xdc/0x100 [30835.171898] ? __pfx_kthread+0x10/0x10 [30835.171900] ret_from_fork+0x2c/0x50 [30835.171904] [30835.171905] Modules linked in: intel_rapl_msr(E) intel_rapl_common(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) coretemp(E) kvm_intel(E) kvm(E) irqbypass(E) ghash_clmulni_intel(E) iwldvm(E) sha512_ssse3(E) sha512_generic(E) snd_hda_codec_realtek(E) snd_hda_codec_generic(E) mac80211(E) ledtrig_audio(E) uvcvideo(E) snd_hda_codec_hdmi(E) libarc4(E) aesni_intel(E) videobuf2_vmalloc(E) uvc(E) snd_hda_intel(E) libaes(E) videobuf2_memops(E) snd_soc_rt5640(E) snd_intel_dspcfg(E) mei_wdt(E) mei_hdcp(E) crypto_simd(E) videobuf2_v4l2(E) snd_usb_audio(E) snd_intel_sdw_acpi(E) snd_soc_rl6231(E) iwlwifi(E) cryptd(E) snd_hda_codec(E) snd_usbmidi_lib(E) videodev(E) snd_soc_core(E) rapl(E) snd_hda_core(E) iTCO_wdt(E) snd_rawmidi(E) tpm_tis(E) dell_smm_hwmon(E) intel_cstate(E) mei_me(E) snd_seq_device(E) videobuf2_common(E) snd_compress(E) snd_hwdep(E) intel_pmc_bxt(E) tpm_tis_core(E) cfg80211(E) snd_pcm(E) iTCO_vendor_support(E) joydev(E) mc(E) intel_uncore(E) watchdog(E) snd_timer(E) sg(E) mei(E) wmi_bmof(E) at24(E) rfkill(E) [30835.171939] serio_raw(E) pcspkr(E) tpm(E) snd(E) rng_core(E) soundcore(E) evdev(E) ac(E) parport_pc(E) ppdev(E) lp(E) parport(E) fuse(E) configfs(E) ip_tables(E) x_tables(E) autofs4(E) ext4(E) crc32c_generic(E) crc16(E) mbcache(E) jbd2(E) amdgpu(E) drm_buddy(E) gpu_sched(E) sd_mod(E) t10_pi(E) hid_generic(E) crc64_rocksoft(E) crc64(E) sr_mod(E) crc_t10dif(E)
Re: [PATCH v2] drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK
On 5/19/2023 11:49 AM, Konrad Dybcio wrote:
DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.
You mean DPU 5.0.0 right?
Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
I have cross-checked all the chipsets affected by this and confirmed
DATA_HCTL is present and those 3 registers programmed with that feature
bit are valid, hence
Reviewed-by: Abhinav Kumar
Re: [PATCH v3 3/5] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag
On 2023-05-19 14:17:28, Jessica Zhang wrote:
> Add DATA_COMPRESS feature flag to DPU INTF block.
>
> In DPU 7.x and later, DSC/DCE enablement registers have been moved from
> PINGPONG to INTF.
>
> Reviewed-by: Marijn Suijten
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 7944481d0a33..c74051906d05 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -104,7 +104,7 @@
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) |
> BIT(DPU_INTF_STATUS_SUPPORTED))
>
> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
> +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) |
> BIT(DPU_INTF_DATA_COMPRESS)
We should really wrap these in parenthesis at some point.
>
> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
>BIT(DPU_WB_UBWC) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 4eda2cc847ef..01c65f940f2a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -185,6 +185,7 @@ enum {
> * @DPU_DATA_HCTL_ENAllows data to be transferred at
> different rate
> * than video timing
> * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
> + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
> * @DPU_INTF_MAX
> */
> enum {
> @@ -192,6 +193,7 @@ enum {
> DPU_INTF_TE,
> DPU_DATA_HCTL_EN,
> DPU_INTF_STATUS_SUPPORTED,
> + DPU_INTF_DATA_COMPRESS,
> DPU_INTF_MAX
> };
>
>
> --
> 2.40.1
>
Re: [PATCH v3 1/5] msm/drm/dsi: Round up DSC hdisplay calculation
On 2023-05-19 14:17:26, Jessica Zhang wrote:
> Currently, when compression is enabled, hdisplay is reduced via integer
> division. This causes issues for modes where the original hdisplay is
> not a multiple of 3.
The "issue" probably being some kind of underflow, because the stream
size is too small compared to how much data we actually send?
> To fix this, use DIV_ROUND_UP to divide hdisplay.
>
> Reported-by: Marijn Suijten
> Fixes: f3a99460406b ("drm/msm/dsi: update hdisplay calculation for
> dsi_timing_setup")
> Signed-off-by: Jessica Zhang
Yes, downstream has as very clear:
dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
which is used for width_final in SDE, and this is one of the mandatory
fixes on a 1096-pixels-wide panel, which is not a multiple of 3.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 9223d7ec5a73..18d38b90eb28 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -952,7 +952,7 @@ static void dsi_timing_setup(struct msm_dsi_host
> *msm_host, bool is_bonded_dsi)
>* pulse width same
>*/
> h_total -= hdisplay;
> - hdisplay = msm_dsc_get_bytes_per_line(msm_host->dsc) / 3;
> + hdisplay =
> DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
> h_total += hdisplay;
> ha_end = ha_start + hdisplay;
> }
>
> --
> 2.40.1
>
Re: [PATCH v3 5/5] drm/msm/dsi: Remove incorrect references to slice_count
On 2023-05-19 14:17:30, Jessica Zhang wrote:
> Currently, slice_count is being used to calculate word count and
> pkt_per_line. In downstream, these values are calculated using slice per
> packet, which is not the same as slice_count.
>
> Slice count represents the number of soft slices per interface, and its
> value will not always match that of slice per packet. For example, it is
> possible to have cases where there are multiple soft slices per interface
> but the panel specifies only one slice per packet.
>
> Thus, use the default value of one slice per packet and remove slice_count
> from the aforementioned calculations.
>
> Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
> Fixes: bc6b6ff8135c ("drm/msm/dsi: Use DSC slice(s) packet size to compute
> word count")
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 24 ++--
> 1 file changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index d04f8bbd707d..8c8858ee59ec 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -866,18 +866,15 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
> *msm_host, bool is_cmd_mod
>*/
> slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
>
> - /*
> - * If slice_count is greater than slice_per_intf
> - * then default to 1. This can happen during partial
> - * update.
> - */
> - if (dsc->slice_count > slice_per_intf)
> - dsc->slice_count = 1;
> -
> total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
>
> eol_byte_num = total_bytes_per_intf % 3;
> - pkt_per_line = slice_per_intf / dsc->slice_count;
> +
> + /*
> + * Default to 1 slice_per_pkt, so pkt_per_line will be equal to
> + * slice per intf.
> + */
> + pkt_per_line = slice_per_intf;
Same as the comment below, perhaps it is a good idea to clarify in the
comment here that the original value wa *multiplied by* slice_per_pkt?
Otherwise this default of 1 is "invisible".
Alternatively we could have a `const slice_per_pkt = 1;` at the top, and
have the comment (the elaborate one from below) there?
- Marijn
>
> if (is_cmd_mode) /* packet data type */
> reg =
> DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> @@ -1001,7 +998,14 @@ static void dsi_timing_setup(struct msm_dsi_host
> *msm_host, bool is_bonded_dsi)
> if (!msm_host->dsc)
> wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> else
> - wc = msm_host->dsc->slice_chunk_size *
> msm_host->dsc->slice_count + 1;
> + /*
> + * When DSC is enabled, WC = slice_chunk_size *
> slice_per_packet + 1.
> + * Currently, the driver only supports default value of
> slice_per_packet = 1
> + *
> + * TODO: Expand mipi_dsi_device struct to hold
> slice_per_packet info
> + * and adjust DSC math to account for
> slice_per_packet.
> + */
> + wc = msm_host->dsc->slice_chunk_size + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
>
> --
> 2.40.1
>
Re: [PATCH v2 1/4] drm/msm/dsi: Adjust pclk rate for compression
On 2023-05-19 12:04:00, Jessica Zhang wrote:
> >>> + /* If DSC is enabled, divide hdisplay by compression ratio */
> >>> + if (dsc) {
> >>> + int new_hdisplay = DIV_ROUND_UP(mode->hdisplay *
> >>> msm_dsc_get_bpp_int(dsc),
> >>> + dsc->bits_per_component * 3);
> >>> + int fps = DIV_ROUND_UP(pclk_rate, mode->htotal * mode->vtotal);
> >>
> >> Should've used drm_mode_vrefresh() here... Will spin a v3 with that
> >> change (along with any additional comments)
> >
> > Perhaps unsigned long on some of these? Overall the computations and
> > multi-lines look rather cluttered, perhaps (parts of) this is/are a
> > prime candidate to go into the new helpers?
>
> Hi Marijn,
>
> Sorry for the late reply, wanted to get the MSM DSC helpers series
> settled first before addressing these changes.
No hurry and no worry, that is exactly why I requested this to be split
across multiple series so that we can make progress on that in isolation
(or rather, make progress on the first series in the chain before
iterating on the next). On the other hand Dmitry made the right remark
that it does cause contention for some patches that only become relevant
in future series... but that's mostly down to how the patches are
distributed across series.
> Sounds good, I'll put these calculations in a separate
> dsi_adjust_compressed_pclk() helper.
Not sure if "adjust" carries the meaning, but I'll leave it to you to
come up with an initial revision and then we can discuss. I am mostly
curious if there are generic (DSI) timing rules that apply DRM-wide, or
if these would be MSM-specific.
Otherwise assigning them to properly named local variables is the
perfect way to self-document the code.
> > Note that I cannot get the 4k mode working at 60Hz on one of my panels
> > (30Hz works with minor corruption), regardless of this patch. See also:
> > https://gitlab.freedesktop.org/drm/msm/-/issues/24#note_1900031
> As discussed elsewhere, we suspect that this is unrelated to DSC
> specifically and might be an issue with the upstream driver not taking
> transfer time into account with calculating pclk_rate.
>
> We will look into this as a separate issue.
Yes that is very likely, but it is still a good idea to take into
account when looking into adjusting DSC timing: can we do that in any
sensible way without first accounting for transfer time?
> >>> dsi_calc_pclk(msm_host, is_bonded_dsi);
> >>>
> >>> - pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp;
> >>> + pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, msm_host->dsc,
> >>> is_bonded_dsi) * bpp;
> >
> > Let's rebase on top of "drm/msm/dsi: simplify pixel clk rate handling"
> > [1] to clean this up.
> >
> > [1]:
> > https://lore.kernel.org/linux-arm-msm/20230118130031.2345941-1-dmitry.barysh...@linaro.org/
>
> I've looked into this patch and have made a comment on it. Just have
> some reservations about it as it changes the functionality of a clk
> handler op.
>
> I will hold off on rebasing and wait for that thread to resolve first.
Looks like the resolution was to drop it, but we should still first
apply the following hunk from it so that this line in your patch can be
skipped entirely.
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
- Marijn
[PATCH v3 5/5] drm/msm/dsi: Remove incorrect references to slice_count
Currently, slice_count is being used to calculate word count and
pkt_per_line. In downstream, these values are calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice per packet. For example, it is
possible to have cases where there are multiple soft slices per interface
but the panel specifies only one slice per packet.
Thus, use the default value of one slice per packet and remove slice_count
from the aforementioned calculations.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Fixes: bc6b6ff8135c ("drm/msm/dsi: Use DSC slice(s) packet size to compute word
count")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index d04f8bbd707d..8c8858ee59ec 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -866,18 +866,15 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
*/
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
- /*
-* If slice_count is greater than slice_per_intf
-* then default to 1. This can happen during partial
-* update.
-*/
- if (dsc->slice_count > slice_per_intf)
- dsc->slice_count = 1;
-
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+
+ /*
+* Default to 1 slice_per_pkt, so pkt_per_line will be equal to
+* slice per intf.
+*/
+ pkt_per_line = slice_per_intf;
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -1001,7 +998,14 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
if (!msm_host->dsc)
wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
else
- wc = msm_host->dsc->slice_chunk_size *
msm_host->dsc->slice_count + 1;
+ /*
+* When DSC is enabled, WC = slice_chunk_size *
slice_per_packet + 1.
+* Currently, the driver only supports default value of
slice_per_packet = 1
+*
+* TODO: Expand mipi_dsi_device struct to hold
slice_per_packet info
+* and adjust DSC math to account for
slice_per_packet.
+*/
+ wc = msm_host->dsc->slice_chunk_size + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
2.40.1
[PATCH v3 4/5] drm/msm/dpu: Set DATA_COMPRESS for command mode
Add a DPU INTF op to set DATA_COMPRESS register if the
DPU_INTF_DATA_COMPRESS feature is enabled. This bit needs to be set in
order for DSC v1.2 to work.
Note: For now, this op is called for command mode encoders only. Changes to
set DATA_COMPRESS for video mode encoders will be posted along with DSC
v1.2 support for DP.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 ++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index d8ed85a238af..1a4c20f02312 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -68,6 +68,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
phys_enc->hw_intf,
true,
phys_enc->hw_pp->idx);
+
+ if (phys_enc->hw_intf->ops.enable_compression)
+ phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
}
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 6485500eedb8..a462c6780e6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -91,6 +91,7 @@
#define INTF_CFG2_DATABUS_WIDENBIT(0)
#define INTF_CFG2_DATA_HCTL_EN BIT(4)
+#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12)
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
const struct intf_timing_params *p,
@@ -522,6 +523,15 @@ static void dpu_hw_intf_disable_autorefresh(struct
dpu_hw_intf *intf,
}
+static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
+{
+ u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
+
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
+ DPU_REG_WRITE(>hw, INTF_CONFIG2, intf_cfg2);
+}
+
static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
unsigned long cap)
{
@@ -542,6 +552,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
ops->vsync_sel = dpu_hw_intf_vsync_sel;
ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
}
+
+ if (cap & BIT(DPU_INTF_DATA_COMPRESS))
+ ops->enable_compression = dpu_hw_intf_enable_compression;
}
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 73b0885918f8..72fe907729f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -70,6 +70,7 @@ struct intf_status {
* @get_autorefresh:Retrieve autorefresh config from hardware
* Return: 0 on success, -ETIMEDOUT on timeout
* @vsync_sel: Select vsync signal for tear-effect
configuration
+ * @enable_compression: Enable data compression
*/
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -107,6 +108,7 @@ struct dpu_hw_intf_ops {
* Disable autorefresh if enabled
*/
void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t
encoder_id, u16 vdisplay);
+ void (*enable_compression)(struct dpu_hw_intf *intf);
};
struct dpu_hw_intf {
--
2.40.1
[PATCH v3 1/5] msm/drm/dsi: Round up DSC hdisplay calculation
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide hdisplay.
Reported-by: Marijn Suijten
Fixes: f3a99460406b ("drm/msm/dsi: update hdisplay calculation for
dsi_timing_setup")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 9223d7ec5a73..18d38b90eb28 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -952,7 +952,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
* pulse width same
*/
h_total -= hdisplay;
- hdisplay = msm_dsc_get_bytes_per_line(msm_host->dsc) / 3;
+ hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
h_total += hdisplay;
ha_end = ha_start + hdisplay;
}
--
2.40.1
[PATCH v3 3/5] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 7944481d0a33..c74051906d05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -104,7 +104,7 @@
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) |
BIT(DPU_INTF_STATUS_SUPPORTED))
-#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
+#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) |
BIT(DPU_INTF_DATA_COMPRESS)
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4eda2cc847ef..01c65f940f2a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -185,6 +185,7 @@ enum {
* @DPU_DATA_HCTL_ENAllows data to be transferred at different
rate
* than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
+ * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
* @DPU_INTF_MAX
*/
enum {
@@ -192,6 +193,7 @@ enum {
DPU_INTF_TE,
DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
+ DPU_INTF_DATA_COMPRESS,
DPU_INTF_MAX
};
--
2.40.1
[PATCH v3 0/5] Add DSC v1.2 Support for DSI
This is a series of changes for DSI to enable command mode support for DSC v1.2. This includes: 1) Rounding up `hdisplay / 3` in dsc_timing_setup() 2) Adjusting pclk_rate to account for compression 3) Fixing incorrect uses of slice_count in DSI DSC calculations 4) Setting the DATA_COMPRESS bit when DSC is enabled With these changes (and the dependency below), DSC v1.2 should work over DSI in command mode. Note: Changes that add DSC v1.2 support for video mode will be posted with the DP support changes. Depends-on: "add DSC 1.2 dpu supports" [1] and "Introduce MSM-specific DSC helpers" [2] [1] https://patchwork.freedesktop.org/series/116789/ [2] https://patchwork.freedesktop.org/series/115833/ Signed-off-by: Jessica Zhang --- Changes in v3: - Added fix to round up hdisplay DSC adjustment - Fixed inconsistent whitespace in dpu_hw_intf_ops comment doc - Moved placement of dpu_hw_intf_enable_compression - Picked up "drm/msm/dsi: Fix calculation for pkt_per_line" patch and squashed all slice_count fixes into a single patch - Use drm_mode_vrefresh() to calculate adjusted pclk rate - Moved compressed pclk adjustment to dsi_adjust_compressed_pclk() helper - Rebased changes on top of updated dependencies - Reworded commit message for "drm/msm/dpu: Set DATA_COMPRESS for command mode" for clarity - Removed revision changelog in commit messages - Link to v2: https://lore.kernel.org/r/20230405-add-dsc-support-v2-0-1072c70e9...@quicinc.com Changes in v2: - Changed has_data_compress dpu_cap to a DATA_COMPRESS INTF feature flag - Changed pclk math to only divide hdisplay by compression ratio - Reworded word count TODO comment - Make DATA_COMPRESS an INTF flag - Read INTF_CONFIG2 before writing to DATA_COMPRESS bit - Fixed whitespace issue in macro definition - Removed `inline` from dpu_hw_intf_enable_compression declaration - Only set dpu_hw_intf_ops.data_compress if DATA_COMPRESS feature is set - Reworded commit messages and cover letter for clarity - Link to v1: https://lore.kernel.org/r/20230405-add-dsc-support-v1-0-6bc6f03ae...@quicinc.com --- Jessica Zhang (5): msm/drm/dsi: Round up DSC hdisplay calculation drm/msm/dsi: Adjust pclk rate for compression drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag drm/msm/dpu: Set DATA_COMPRESS for command mode drm/msm/dsi: Remove incorrect references to slice_count .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 13 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 2 + drivers/gpu/drm/msm/dsi/dsi_host.c | 49 +++--- 6 files changed, 55 insertions(+), 16 deletions(-) --- base-commit: 2f0218fa4805d7c7eed8dc072e1bdf9f100492c7 change-id: 20230405-add-dsc-support-fe130ba49841 Best regards, -- Jessica Zhang
[PATCH v3 2/5] drm/msm/dsi: Adjust pclk rate for compression
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18d38b90eb28..d04f8bbd707d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -561,7 +561,18 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
-static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
bool is_bonded_dsi)
+static unsigned long dsi_adjust_compressed_pclk(const struct drm_display_mode
*mode,
+ const struct drm_dsc_config *dsc)
+{
+ int new_hdisplay = DIV_ROUND_UP(mode->hdisplay *
drm_dsc_get_bpp_int(dsc),
+ dsc->bits_per_component * 3);
+
+ return (new_hdisplay + (mode->htotal - mode->hdisplay))
+ * mode->vtotal * drm_mode_vrefresh(mode);
+}
+
+static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
+ const struct drm_dsc_config *dsc, bool is_bonded_dsi)
{
unsigned long pclk_rate;
@@ -576,6 +587,10 @@ static unsigned long dsi_get_pclk_rate(const struct
drm_display_mode *mode, bool
if (is_bonded_dsi)
pclk_rate /= 2;
+ /* If DSC is enabled, divide hdisplay by compression ratio */
+ if (dsc)
+ pclk_rate = dsi_adjust_compressed_pclk(mode, dsc);
+
return pclk_rate;
}
@@ -585,7 +600,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
- unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi);
+ unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc,
is_bonded_dsi);
u64 pclk_bpp = (u64)pclk_rate * bpp;
if (lanes == 0) {
@@ -604,7 +619,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
- msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode,
is_bonded_dsi);
+ msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode,
msm_host->dsc, is_bonded_dsi);
msm_host->byte_clk_rate = dsi_byte_clk_get_rate(_host->base,
is_bonded_dsi,
msm_host->mode);
@@ -634,7 +649,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
dsi_calc_pclk(msm_host, is_bonded_dsi);
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp;
+ pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, msm_host->dsc,
is_bonded_dsi) * bpp;
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
--
2.40.1
Re: [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On Fri, May 19, 2023 at 07:55:47PM +0300, Dmitry Baryshkov wrote: > On 19/04/2023 18:43, Mark Yacoub wrote: > > Hi all, > > This is v10 of the HDCP patches. The patches are authored by Sean Paul. > > I rebased and addressed the review comments in v6-v10. > > > > Main change in v10 is handling the kernel test bot warnings. > > > > Patches 1-4 focus on moving the common HDCP helpers to common DRM. > > This introduces a slight change in the original intel flow > > as it splits the unique driver protocol from the generic implementation. > > > > Patches 5-7 split the HDCP flow on the i915 driver to make use of the > > common DRM helpers. > > > > Patches 8-10 implement HDCP on MSM driver. > > > > Thanks, > > -Mark Yacoub > > > > Sean Paul (10): > >drm/hdcp: Add drm_hdcp_atomic_check() > >drm/hdcp: Avoid changing crtc state in hdcp atomic check > >drm/hdcp: Update property value on content type and user changes > >drm/hdcp: Expand HDCP helper library for enable/disable/check > >drm/i915/hdcp: Consolidate HDCP setup/state cache > >drm/i915/hdcp: Retain hdcp_capable return codes > >drm/i915/hdcp: Use HDCP helpers for i915 > >dt-bindings: msm/dp: Add bindings for HDCP registers > >arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller > > Dear i915 maintainers, > > I wanted to ping you regarding this patch series. If there are no comments > for the series from you side, would it be possible to land Intel-specific > and generic patches into drm-intel tree? We will continue working on the msm > specific parts and merge them through the msm tree. pushed to drm-intel-next. should be propagated in a few weeks to drm-next on our next pull request. > > >drm/msm: Implement HDCP 1.x using the new drm HDCP helpers > > > > .../bindings/display/msm/dp-controller.yaml |7 +- > > arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi |8 + > > drivers/gpu/drm/display/drm_hdcp_helper.c | 1224 + > > drivers/gpu/drm/i915/display/intel_atomic.c |8 +- > > drivers/gpu/drm/i915/display/intel_ddi.c | 32 +- > > .../drm/i915/display/intel_display_debugfs.c | 12 +- > > .../drm/i915/display/intel_display_types.h| 51 +- > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 352 ++--- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +- > > drivers/gpu/drm/i915/display/intel_hdcp.c | 1060 +++--- > > drivers/gpu/drm/i915/display/intel_hdcp.h | 48 +- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 267 ++-- > > drivers/gpu/drm/msm/Kconfig |1 + > > drivers/gpu/drm/msm/Makefile |1 + > > drivers/gpu/drm/msm/dp/dp_catalog.c | 156 +++ > > drivers/gpu/drm/msm/dp/dp_catalog.h | 18 + > > drivers/gpu/drm/msm/dp/dp_debug.c | 46 +- > > drivers/gpu/drm/msm/dp/dp_debug.h | 11 +- > > drivers/gpu/drm/msm/dp/dp_display.c | 39 +- > > drivers/gpu/drm/msm/dp/dp_display.h |5 + > > drivers/gpu/drm/msm/dp/dp_drm.c | 39 +- > > drivers/gpu/drm/msm/dp/dp_drm.h |7 + > > drivers/gpu/drm/msm/dp/dp_hdcp.c | 389 ++ > > drivers/gpu/drm/msm/dp/dp_hdcp.h | 33 + > > drivers/gpu/drm/msm/dp/dp_parser.c| 14 + > > drivers/gpu/drm/msm/dp/dp_parser.h|4 + > > drivers/gpu/drm/msm/dp/dp_reg.h | 30 +- > > drivers/gpu/drm/msm/msm_atomic.c | 19 + > > include/drm/display/drm_hdcp.h| 296 > > include/drm/display/drm_hdcp_helper.h | 23 + > > 30 files changed, 2867 insertions(+), 1349 deletions(-) > > create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c > > create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h > > > > -- > With best wishes > Dmitry >
[PATCH] fbdev: udlfb: Use usb_control_msg_send()
Use the newly introduced usb_control_msg_send() instead of usb_control_msg()
when selecting the channel.
Signed-off-by: Helge Deller
---
drivers/video/fbdev/udlfb.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/video/fbdev/udlfb.c b/drivers/video/fbdev/udlfb.c
index 256d9b61f4ea..dabc30a09f96 100644
--- a/drivers/video/fbdev/udlfb.c
+++ b/drivers/video/fbdev/udlfb.c
@@ -1543,24 +1543,16 @@ static const struct device_attribute fb_device_attrs[]
= {
static int dlfb_select_std_channel(struct dlfb_data *dlfb)
{
int ret;
- void *buf;
static const u8 set_def_chn[] = {
0x57, 0xCD, 0xDC, 0xA7,
0x1C, 0x88, 0x5E, 0x15,
0x60, 0xFE, 0xC6, 0x97,
0x16, 0x3D, 0x47, 0xF2 };
- buf = kmemdup(set_def_chn, sizeof(set_def_chn), GFP_KERNEL);
-
- if (!buf)
- return -ENOMEM;
-
- ret = usb_control_msg(dlfb->udev, usb_sndctrlpipe(dlfb->udev, 0),
- NR_USB_REQUEST_CHANNEL,
+ ret = usb_control_msg_send(dlfb->udev, 0, NR_USB_REQUEST_CHANNEL,
(USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0,
- buf, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT);
-
- kfree(buf);
+ _def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT,
+ GFP_KERNEL);
return ret;
}
--
2.40.0
Re: [Freedreno] [PATCH] drm/msm/dsi: simplify pixel clk rate handling
On 2023-05-19 22:37:34, Dmitry Baryshkov wrote:
> >> + ret = cfg_hnd->ops->calc_clk_rate(msm_host);
> >
> > I am not too sure what we are gaining by this.
> >
> > Its not that we are replacing dsi_get_pclk_rate().
> >
> > We are moving the dsi_get_pclk_rate() from the calc_clk_rate() to
> > the msm_dsi_host_get_phy_clk_req().
> >
> > Also, with this change, dsi_calc_clk_rate_6g() looks kind of empty
> > to stand on its own.
> >
> > The original intention of the calc_clk_rate() op seems to be
> > calculate and store all the clocks (byte, pixel and esc).
> >
> > Why change that behavior by breaking it up?
>
> Unification between platforms. Both v2 and 6g platforms call
> dsi_calc_pclk(). Let's just move it to a common code path.
> >>>
> >>> Hi Dmitry,
> >>>
> >>> I think what Abhinav means here is that the meaning and functionality
> >>> of calc_clk_rate() changes with this patch.
> >>>
> >>> Before, calc_clk_rate() does *all* the clk_rate calculations and
> >>> assignments. But after this change, it will only calculate and assign
> >>> the escape clk rate.
> >>>
> >>> I agree with Abhinav that this change renders the calc_clk_rate() op
> >>> misleading as it will not calculate all of the clock rates anymore.
> >>
> >> Would it make sense if I rename it to calc_other_clock_rates()?
> >>
> >
> > Not really. I would rather still have it separate and drop this patch.
> >
> > So even if pixel clock calculation looks common today between v2 and 6g,
> > lets say tomorrow there is a 7g or 8g which needs some other math there,
> > I think this is the right place where it should stay so that we
> > calculate all clocks together.
>
> Ack.
Unfortunate, but okay. Then don't forget to send the following hunk of
this patch in isolation:
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
- Marijn
> >> Moving pclk calculation to the core code emphasises that pclk
> >> calculation is common between v2 and 6g hosts.
> >>
> >>>
> >>> Thanks,
> >>>
> >>> Jessica Zhang
> >>>
>
> >
> >> if (ret) {
> >> pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
> >> return;
>
> --
> With best wishes
> Dmitry
>
> >>
>
> --
> With best wishes
> Dmitry
>
Re: [PATCH v2] drm/i915: Fix memory leaks in function live_nop_switch
On Wed, May 17, 2023 at 01:02:03PM +0800, Cong Liu wrote:
> Be sure to properly free the allocated memory before exiting
> the live_nop_switch function.
>
> Signed-off-by: Cong Liu
> Suggested-by: Rodrigo Vivi
pushed, thanks for the patch
> ---
> .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index a81fa6a20f5a..2fb125d0cb5e 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -66,7 +66,7 @@ static int live_nop_switch(void *arg)
> ctx[n] = live_context(i915, file);
> if (IS_ERR(ctx[n])) {
> err = PTR_ERR(ctx[n]);
> - goto out_file;
> + goto out_ctx;
> }
> }
>
> @@ -82,7 +82,7 @@ static int live_nop_switch(void *arg)
> this = igt_request_alloc(ctx[n], engine);
> if (IS_ERR(this)) {
> err = PTR_ERR(this);
> - goto out_file;
> + goto out_ctx;
> }
> if (rq) {
> i915_request_await_dma_fence(this, >fence);
> @@ -96,7 +96,7 @@ static int live_nop_switch(void *arg)
> intel_gt_set_wedged(to_gt(i915));
> i915_request_put(rq);
> err = -EIO;
> - goto out_file;
> + goto out_ctx;
> }
> i915_request_put(rq);
>
> @@ -107,7 +107,7 @@ static int live_nop_switch(void *arg)
>
> err = igt_live_test_begin(, i915, __func__, engine->name);
> if (err)
> - goto out_file;
> + goto out_ctx;
>
> end_time = jiffies + i915_selftest.timeout_jiffies;
> for_each_prime_number_from(prime, 2, 8192) {
> @@ -120,7 +120,7 @@ static int live_nop_switch(void *arg)
> this = igt_request_alloc(ctx[n % nctx], engine);
> if (IS_ERR(this)) {
> err = PTR_ERR(this);
> - goto out_file;
> + goto out_ctx;
> }
>
> if (rq) { /* Force submission order */
> @@ -165,7 +165,7 @@ static int live_nop_switch(void *arg)
>
> err = igt_live_test_end();
> if (err)
> - goto out_file;
> + goto out_ctx;
>
> pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
> engine->name,
> @@ -173,6 +173,8 @@ static int live_nop_switch(void *arg)
> prime - 1, div64_u64(ktime_to_ns(times[1]), prime - 1));
> }
>
> +out_ctx:
> + kfree(ctx);
> out_file:
> fput(file);
> return err;
> --
> 2.34.1
>
>
> No virus found
> Checked by Hillstone Network AntiVirus
Re: [RFC 4/4] drm/i915: Expose RPS thresholds in sysfs
On Fri, May 19, 2023 at 07:36:56PM +, Prahlad Kilambi wrote: > > One question is are we able to find a "one size fits all" values. > > > However regardless of that, given we already expose frequency controls in > > sysfs > > with the same reasoning of allowing system owners explicit control if so > > wanted, > > I think exposing the thresholds can be equally justified. > > Exposing these RPS thresholds via sysfs allows for dynamic tuning of these > values at runtime. Common scenarios where we can benefit from variable > frequency ramping include plugged in vs battery where differing thresholds > allow to weight more for performance vs power. Data from testing on ChromeOS > Gen12 platforms where GuC isn't enabled indicates gains > 10% across several > games. See > https://gitlab.freedesktop.org/drm/intel/-/issues/8389#note_1890428 for > details. > In general we should always try to reduce the knobs and specially with a register that doesn't work with the new platforms with FW on control of all these variations. But this is a compelling argument. Acked-by: Rodrigo Vivi (if patch 3 doesn't break compilation and the other chunk has the placement explained this is a rv-b for the series)
Re: [Intel-gfx] [RFC 3/4] drm/i915: Add helpers for managing rps thresholds
On Fri, Apr 28, 2023 at 09:14:56AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
> drivers/gpu/drm/i915/gt/intel_rps.h | 4
> 2 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index a39eee444849..a5a7315f5ace 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2573,6 +2573,42 @@ int intel_rps_set_min_frequency(struct intel_rps *rps,
> u32 val)
> return set_min_freq(rps, val);
> }
>
> +u8 intel_rps_get_up_threshold(struct intel_rps *rps)
> +{
> + return rps->power.up_threshold;
> +}
> +
> +static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)
> +{
> + int ret;
> +
> + if (val > 100)
> + return -EINVAL;
> +
> + ret = mutex_lock_interruptible(>lock);
> + if (ret)
> + return ret;
> + *threshold = val;
> + mutex_unlock(>lock);
> +
> + return 0;
> +}
> +
> +int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold)
> +{
> + return rps_set_threshold(rps, >power.up_threshold, threshold);
> +}
> +
> +u8 intel_rps_get_down_threshold(struct intel_rps *rps)
> +{
> + return rps->power.down_threshold;
> +}
> +
> +int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold)
> +{
> + return rps_set_threshold(rps, >power.down_threshold, threshold);
> +}
> +
Isn't this breaking compilation with the unused functions?
> static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
> {
> struct intel_uncore *uncore = rps_to_uncore(rps);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
> b/drivers/gpu/drm/i915/gt/intel_rps.h
> index a3fa987aa91f..92fb01f5a452 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -37,6 +37,10 @@ void intel_rps_mark_interactive(struct intel_rps *rps,
> bool interactive);
>
> int intel_gpu_freq(struct intel_rps *rps, int val);
> int intel_freq_opcode(struct intel_rps *rps, int val);
> +u8 intel_rps_get_up_threshold(struct intel_rps *rps);
> +int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold);
> +u8 intel_rps_get_down_threshold(struct intel_rps *rps);
> +int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold);
> u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
> u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps);
> u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
> --
> 2.37.2
>
Re: [Intel-gfx] [RFC 4/4] drm/i915: Expose RPS thresholds in sysfs
On Fri, Apr 28, 2023 at 09:44:53AM +0100, Tvrtko Ursulin wrote:
>
> On 28/04/2023 09:14, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > User feedback indicates significant performance gains are possible in
> > specific games with non default RPS up/down thresholds.
> >
> > Expose these tunables via sysfs which will allow users to achieve best
> > performance when running games and best power efficiency elsewhere.
> >
> > Note this patch supports non GuC based platforms only.
> >
> > Signed-off-by: Tvrtko Ursulin
> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/8389
>
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index a5a7315f5ace..f790e81546ff 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2588,7 +2588,12 @@ static int rps_set_threshold(struct intel_rps *rps,
> > u8 *threshold, u8 val)
> > ret = mutex_lock_interruptible(>lock);
> > if (ret)
> > return ret;
> > - *threshold = val;
> > + if (*threshold != val) {
> > + *threshold = val;
> > + intel_rps_set(rps, clamp(rps->cur_freq,
> > +rps->min_freq_softlimit,
> > +rps->max_freq_softlimit));
> > + }
> > mutex_unlock(>lock);
> > return 0;
>
> This hunk belongs to a previous patch - moved locally.
I probably missed something then becuase I didn't miss this in any
of the previous patches. To the point that this looked like a new
separated patch.
>
> Regards,
>
> Tvrtko
Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Parse the GSC-enabled HuC binary
On 5/17/2023 2:04 PM, John Harrison wrote:
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
'meu manifest' needs some kind of explanation. 'meu' is mentioned many
times but nothing ever seems to explain what it is or where it comes
from. Also, sometimes it is capitalised and sometimes not.
MEU is the name of the tool that packages the binary. I think I'll
switch it to gsc_binary instead of meu_binary, so we don't have
references to non-public tools.
manifest of the GSC binary. The manifest consist of a partition header
followed by entries, one of which contains the offset we're looking for.
Note that the DG2 GSC binary contains entries with the same names, but
it doesn't contain a full legacy binary, so we need to skip assigning
the dma offset in that case (which we can do by checking the ccs).
Also, since we're now parsing the entries, we can extract the HuC
version that way instead of using hardcoded offsets.
Note that the meu structure will be re-used for parsing the GSC binary,
so they've been added in their own header.
v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
message, check ccs validity, drop old version location defines.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
.../drm/i915/gt/uc/intel_gsc_meu_headers.h | 74 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 11 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 135 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 71 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 -
8 files changed, 272 insertions(+), 53 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
new file mode 100644
index ..d55a66202576
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_MEU_H_
+#define _INTEL_GSC_MEU_H_
+
+#include
+
+/* Code partition directory (CPD) structures */
+struct intel_gsc_cpd_header_v2 {
+ u32 header_marker;
+#define INTEL_GSC_CPD_HEADER_MARKER 0x44504324
+
+ u32 num_of_entries;
+ u8 header_version;
+ u8 entry_version;
+ u8 header_length; /* in bytes */
+ u8 flags;
+ u32 partition_name;
+ u32 crc32;
+} __packed;
+
+struct intel_gsc_cpd_entry {
+ u8 name[12];
+
+ /*
+ * Bits 0-24: offset from the beginning of the code partition
+ * Bit 25: huffman compressed
+ * Bits 26-31: reserved
+ */
+ u32 offset;
+#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
+#define INTEL_GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)
+
+ /*
+ * Module/Item length, in bytes. For Huffman-compressed modules,
this
+ * refers to the uncompressed size. For software-compressed
modules,
+ * this refers to the compressed size.
+ */
+ u32 length;
+
+ u8 reserved[4];
+} __packed;
+
+struct intel_gsc_meu_version {
+ u16 major;
+ u16 minor;
+ u16 hotfix;
+ u16 build;
+} __packed;
+
+struct intel_gsc_manifest_header {
+ u32 header_type; /* 0x4 for manifest type */
+ u32 header_length; /* in dwords */
+ u32 header_version;
+ u32 flags;
+ u32 vendor;
+ u32 date;
+ u32 size; /* In dwords, size of entire manifest (header +
extensions) */
+ u32 header_id;
+ u32 internal_data;
+ struct intel_gsc_meu_version fw_version;
+ u32 security_version;
+ struct intel_gsc_meu_version meu_kit_version;
+ u32 meu_manifest_version;
+ u8 general_data[4];
+ u8 reserved3[56];
+ u32 modulus_size; /* in dwords */
+ u32 exponent_size; /* in dwords */
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 9721761373fb..062ff914b274 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,23 +6,14 @@
#include
#include "gt/intel_gt.h"
-#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
+#include "intel_huc_print.h"
#include "i915_drv.h"
#include
#include
-#define huc_printk(_huc, _level, _fmt, ...) \
- gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
-#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
-#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
-#define
Re: [Freedreno] [PATCH] drm/msm/dsi: simplify pixel clk rate handling
On 19/05/2023 22:36, Abhinav Kumar wrote:
On 5/19/2023 12:33 PM, Dmitry Baryshkov wrote:
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2
hosts.
Also, while we are at it, replace another dsi_get_pclk_rate()
invocation
with using the stored value at msm_host->pixel_clk_rate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 ++--
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 24
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
b/drivers/gpu/drm/msm/dsi/dsi.h
index bd3763a5d723..93ec54478eb6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -129,8 +129,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host
*msm_host, uint64_t *iova);
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t
*iova);
int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state,
struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct
mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 44be4a88aa83..5106e66846c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -51,7 +51,7 @@ struct msm_dsi_host_cfg_ops {
void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
void (*tx_buf_put)(struct msm_dsi_host *msm_host);
int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t
*iova);
- int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..7d99a108bff6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -616,28 +616,21 @@ static void dsi_calc_pclk(struct
msm_dsi_host *msm_host, bool is_bonded_dsi)
}
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
{
- if (!msm_host->mode) {
- pr_err("%s: mode not set\n", __func__);
- return -EINVAL;
- }
-
- dsi_calc_pclk(msm_host, is_bonded_dsi);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
+
return 0;
}
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
{
u32 bpp = dsi_get_bpp(msm_host->format);
u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
- dsi_calc_pclk(msm_host, is_bonded_dsi);
-
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode,
is_bonded_dsi) * bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
@@ -2292,7 +2285,14 @@ void msm_dsi_host_get_phy_clk_req(struct
mipi_dsi_host *host,
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
- ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
+ if (!msm_host->mode) {
+ pr_err("%s: mode not set\n", __func__);
+ return;
+ }
+
+ dsi_calc_pclk(msm_host, is_bonded_dsi);
+
+ ret = cfg_hnd->ops->calc_clk_rate(msm_host);
I am not too sure what we are gaining by this.
Its not that we are replacing dsi_get_pclk_rate().
We are moving the dsi_get_pclk_rate() from the calc_clk_rate() to
the msm_dsi_host_get_phy_clk_req().
Also, with this change, dsi_calc_clk_rate_6g() looks kind of empty
to stand on its own.
The original intention of the calc_clk_rate() op seems to be
calculate and store all the clocks (byte, pixel and esc).
Why change that behavior by breaking it up?
Unification between platforms. Both v2 and 6g platforms call
dsi_calc_pclk(). Let's just move it to a common code path.
Hi Dmitry,
I think what Abhinav means here is that the meaning and functionality
of calc_clk_rate() changes with this patch.
Before, calc_clk_rate() does *all* the clk_rate calculations and
assignments. But after this change, it will only calculate and assign
the escape clk rate.
I agree with Abhinav that this change renders the
[RFC 4/4] drm/i915: Expose RPS thresholds in sysfs
> One question is are we able to find a "one size fits all" values. > However regardless of that, given we already expose frequency controls in > sysfs > with the same reasoning of allowing system owners explicit control if so > wanted, > I think exposing the thresholds can be equally justified. Exposing these RPS thresholds via sysfs allows for dynamic tuning of these values at runtime. Common scenarios where we can benefit from variable frequency ramping include plugged in vs battery where differing thresholds allow to weight more for performance vs power. Data from testing on ChromeOS Gen12 platforms where GuC isn't enabled indicates gains > 10% across several games. See https://gitlab.freedesktop.org/drm/intel/-/issues/8389#note_1890428 for details.
Re: [Freedreno] [PATCH] drm/msm/dsi: simplify pixel clk rate handling
On 5/19/2023 12:33 PM, Dmitry Baryshkov wrote:
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we are at it, replace another dsi_get_pclk_rate()
invocation
with using the stored value at msm_host->pixel_clk_rate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 ++--
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 24
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
b/drivers/gpu/drm/msm/dsi/dsi.h
index bd3763a5d723..93ec54478eb6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -129,8 +129,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host
*msm_host, uint64_t *iova);
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t
*iova);
int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state,
struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct
mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 44be4a88aa83..5106e66846c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -51,7 +51,7 @@ struct msm_dsi_host_cfg_ops {
void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
void (*tx_buf_put)(struct msm_dsi_host *msm_host);
int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t
*iova);
- int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..7d99a108bff6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -616,28 +616,21 @@ static void dsi_calc_pclk(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
}
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
{
- if (!msm_host->mode) {
- pr_err("%s: mode not set\n", __func__);
- return -EINVAL;
- }
-
- dsi_calc_pclk(msm_host, is_bonded_dsi);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
+
return 0;
}
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
{
u32 bpp = dsi_get_bpp(msm_host->format);
u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
- dsi_calc_pclk(msm_host, is_bonded_dsi);
-
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode,
is_bonded_dsi) * bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
@@ -2292,7 +2285,14 @@ void msm_dsi_host_get_phy_clk_req(struct
mipi_dsi_host *host,
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
- ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
+ if (!msm_host->mode) {
+ pr_err("%s: mode not set\n", __func__);
+ return;
+ }
+
+ dsi_calc_pclk(msm_host, is_bonded_dsi);
+
+ ret = cfg_hnd->ops->calc_clk_rate(msm_host);
I am not too sure what we are gaining by this.
Its not that we are replacing dsi_get_pclk_rate().
We are moving the dsi_get_pclk_rate() from the calc_clk_rate() to
the msm_dsi_host_get_phy_clk_req().
Also, with this change, dsi_calc_clk_rate_6g() looks kind of empty
to stand on its own.
The original intention of the calc_clk_rate() op seems to be
calculate and store all the clocks (byte, pixel and esc).
Why change that behavior by breaking it up?
Unification between platforms. Both v2 and 6g platforms call
dsi_calc_pclk(). Let's just move it to a common code path.
Hi Dmitry,
I think what Abhinav means here is that the meaning and functionality
of calc_clk_rate() changes with this patch.
Before, calc_clk_rate() does *all* the clk_rate calculations and
assignments. But after this change, it will only calculate and assign
the escape clk rate.
I agree with Abhinav that this change renders the calc_clk_rate() op
misleading as it will not calculate
Re: [PATCH v4 06/12] drm/msm/dpu: Add SM6350 support
On 19/05/2023 20:04, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the fact that newer SoCs dropped the .fl (fill level)-based
logic and don't provide real values, resulting in all entries but
the last one being unused.
I think that the commit message is misleading. The DPU driver uses
fill-level logic. It doesn't yet support selecting between portrait and
landscape LUT settings (for danger and safe LUTs) and it doesn't provide
full support for qseed/non-qseed usescases (for QoS LUT).
Signed-off-by: Konrad Dybcio
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 195 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index ..5d66a194155a
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ _dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x7, PINGPONG_SM8150_MASK, 0,
sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0,
sdm845_pp_sblk,
+
Re: [Freedreno] [PATCH] drm/msm/dsi: simplify pixel clk rate handling
On 19/05/2023 21:54, Jessica Zhang wrote:
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we are at it, replace another dsi_get_pclk_rate()
invocation
with using the stored value at msm_host->pixel_clk_rate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 ++--
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 24
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
b/drivers/gpu/drm/msm/dsi/dsi.h
index bd3763a5d723..93ec54478eb6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -129,8 +129,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host
*msm_host, uint64_t *iova);
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t
*iova);
int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state,
struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct
mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 44be4a88aa83..5106e66846c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -51,7 +51,7 @@ struct msm_dsi_host_cfg_ops {
void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
void (*tx_buf_put)(struct msm_dsi_host *msm_host);
int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t
*iova);
- int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..7d99a108bff6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -616,28 +616,21 @@ static void dsi_calc_pclk(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
}
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
{
- if (!msm_host->mode) {
- pr_err("%s: mode not set\n", __func__);
- return -EINVAL;
- }
-
- dsi_calc_pclk(msm_host, is_bonded_dsi);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
+
return 0;
}
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
{
u32 bpp = dsi_get_bpp(msm_host->format);
u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
- dsi_calc_pclk(msm_host, is_bonded_dsi);
-
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode,
is_bonded_dsi) * bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
@@ -2292,7 +2285,14 @@ void msm_dsi_host_get_phy_clk_req(struct
mipi_dsi_host *host,
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
- ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
+ if (!msm_host->mode) {
+ pr_err("%s: mode not set\n", __func__);
+ return;
+ }
+
+ dsi_calc_pclk(msm_host, is_bonded_dsi);
+
+ ret = cfg_hnd->ops->calc_clk_rate(msm_host);
I am not too sure what we are gaining by this.
Its not that we are replacing dsi_get_pclk_rate().
We are moving the dsi_get_pclk_rate() from the calc_clk_rate() to the
msm_dsi_host_get_phy_clk_req().
Also, with this change, dsi_calc_clk_rate_6g() looks kind of empty to
stand on its own.
The original intention of the calc_clk_rate() op seems to be
calculate and store all the clocks (byte, pixel and esc).
Why change that behavior by breaking it up?
Unification between platforms. Both v2 and 6g platforms call
dsi_calc_pclk(). Let's just move it to a common code path.
Hi Dmitry,
I think what Abhinav means here is that the meaning and functionality of
calc_clk_rate() changes with this patch.
Before, calc_clk_rate() does *all* the clk_rate calculations and
assignments. But after this change, it will only calculate and assign
the escape clk rate.
I agree with Abhinav that this change renders the calc_clk_rate() op
misleading as it will not calculate all of the clock rates anymore.
Would it make sense
Re: [PATCH v4 05/12] dt-bindings: display/msm: Add SM6375 MDSS
On 19.05.2023 21:05, Rob Herring wrote: > > On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote: >> Document the SM6375 MDSS. >> >> Signed-off-by: Konrad Dybcio >> --- >> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 >> + >> 1 file changed, 216 insertions(+) >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: > display-controller@5e01000: clock-names:0: 'bus' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: > display-controller@5e01000: clock-names:1: 'iface' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: > display-controller@5e01000: clock-names:2: 'rot' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: > display-controller@5e01000: clock-names:4: 'core' was expected > From schema: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml > Whoops, forgot to fix the bindings.. there was going to be a v5 anyway. Konrad > doc reference errors (make refcheckdocs): > > See > https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v4-5-68e7e25d7...@linaro.org > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
Re: [PATCH v4 05/12] dt-bindings: display/msm: Add SM6375 MDSS
On Fri, 19 May 2023 19:04:26 +0200, Konrad Dybcio wrote: > Document the SM6375 MDSS. > > Signed-off-by: Konrad Dybcio > --- > .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 > + > 1 file changed, 216 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: display-controller@5e01000: clock-names:0: 'bus' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: display-controller@5e01000: clock-names:1: 'iface' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: display-controller@5e01000: clock-names:2: 'rot' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: display-controller@5e01000: clock-names:4: 'core' was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v4-5-68e7e25d7...@linaro.org The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [PATCH v2 1/4] drm/msm/dsi: Adjust pclk rate for compression
On 5/8/2023 2:56 PM, Marijn Suijten wrote:
On 2023-05-05 14:49:08, Jessica Zhang wrote:
On 5/5/2023 2:23 PM, Jessica Zhang wrote:
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Changes in v2:
- Adjusted pclk_rate math to divide only the hdisplay value by
compression ratio
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 43a5ec33eee8..0e5778e8091f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -561,7 +561,8 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
-static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi)
+static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
+ struct drm_dsc_config *dsc, bool is_bonded_dsi)
{
unsigned long pclk_rate;
@@ -576,6 +577,14 @@ static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool
if (is_bonded_dsi)
pclk_rate /= 2;
+ /* If DSC is enabled, divide hdisplay by compression ratio */
+ if (dsc) {
+ int new_hdisplay = DIV_ROUND_UP(mode->hdisplay *
msm_dsc_get_bpp_int(dsc),
+ dsc->bits_per_component * 3);
+ int fps = DIV_ROUND_UP(pclk_rate, mode->htotal * mode->vtotal);
Should've used drm_mode_vrefresh() here... Will spin a v3 with that
change (along with any additional comments)
Perhaps unsigned long on some of these? Overall the computations and
multi-lines look rather cluttered, perhaps (parts of) this is/are a
prime candidate to go into the new helpers?
Hi Marijn,
Sorry for the late reply, wanted to get the MSM DSC helpers series
settled first before addressing these changes.
Sounds good, I'll put these calculations in a separate
dsi_adjust_compressed_pclk() helper.
Note that I cannot get the 4k mode working at 60Hz on one of my panels
(30Hz works with minor corruption), regardless of this patch. See also:
https://gitlab.freedesktop.org/drm/msm/-/issues/24#note_1900031
As discussed elsewhere, we suspect that this is unrelated to DSC
specifically and might be an issue with the upstream driver not taking
transfer time into account with calculating pclk_rate.
We will look into this as a separate issue.
+ pclk_rate = (new_hdisplay + (mode->htotal - mode->hdisplay)) *
mode->vtotal * fps;
+ }
+
return pclk_rate;
}
@@ -585,7 +594,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
- unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi);
+ unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc,
is_bonded_dsi);
u64 pclk_bpp = (u64)pclk_rate * bpp;
if (lanes == 0) {
@@ -604,7 +613,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host
*host, bool is_bonded_d
static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
- msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode,
is_bonded_dsi);
+ msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode,
msm_host->dsc, is_bonded_dsi);
msm_host->byte_clk_rate = dsi_byte_clk_get_rate(_host->base,
is_bonded_dsi,
msm_host->mode);
@@ -634,7 +643,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
dsi_calc_pclk(msm_host, is_bonded_dsi);
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp;
+ pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, msm_host->dsc,
is_bonded_dsi) * bpp;
Let's rebase on top of "drm/msm/dsi: simplify pixel clk rate handling"
[1] to clean this up.
[1]:
https://lore.kernel.org/linux-arm-msm/20230118130031.2345941-1-dmitry.barysh...@linaro.org/
I've looked into this patch and have made a comment on it. Just have
some reservations about it as it changes the functionality of a clk
handler op.
I will hold off on rebasing and wait for that thread to resolve first.
Thanks,
Jessica Zhang
- Marijn
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
--
2.40.1
Re: [Freedreno] [PATCH] drm/msm/dsi: simplify pixel clk rate handling
On 3/28/2023 6:04 AM, Dmitry Baryshkov wrote:
On 26/01/2023 02:07, Abhinav Kumar wrote:
On 1/18/2023 5:00 AM, Dmitry Baryshkov wrote:
Move a call to dsi_calc_pclk() out of calc_clk_rate directly towards
msm_dsi_host_get_phy_clk_req(). It is called for both 6g and v2 hosts.
Also, while we are at it, replace another dsi_get_pclk_rate() invocation
with using the stored value at msm_host->pixel_clk_rate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 ++--
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 24
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
b/drivers/gpu/drm/msm/dsi/dsi.h
index bd3763a5d723..93ec54478eb6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -129,8 +129,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host
*msm_host, uint64_t *iova);
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t
*iova);
int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state,
struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct
mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 44be4a88aa83..5106e66846c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -51,7 +51,7 @@ struct msm_dsi_host_cfg_ops {
void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
void (*tx_buf_put)(struct msm_dsi_host *msm_host);
int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t
*iova);
- int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool
is_bonded_dsi);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..7d99a108bff6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -616,28 +616,21 @@ static void dsi_calc_pclk(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
}
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
{
- if (!msm_host->mode) {
- pr_err("%s: mode not set\n", __func__);
- return -EINVAL;
- }
-
- dsi_calc_pclk(msm_host, is_bonded_dsi);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
+
return 0;
}
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool
is_bonded_dsi)
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
{
u32 bpp = dsi_get_bpp(msm_host->format);
u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
- dsi_calc_pclk(msm_host, is_bonded_dsi);
-
- pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi)
* bpp;
+ pclk_bpp = msm_host->pixel_clk_rate * bpp;
do_div(pclk_bpp, 8);
msm_host->src_clk_rate = pclk_bpp;
@@ -2292,7 +2285,14 @@ void msm_dsi_host_get_phy_clk_req(struct
mipi_dsi_host *host,
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
int ret;
- ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
+ if (!msm_host->mode) {
+ pr_err("%s: mode not set\n", __func__);
+ return;
+ }
+
+ dsi_calc_pclk(msm_host, is_bonded_dsi);
+
+ ret = cfg_hnd->ops->calc_clk_rate(msm_host);
I am not too sure what we are gaining by this.
Its not that we are replacing dsi_get_pclk_rate().
We are moving the dsi_get_pclk_rate() from the calc_clk_rate() to the
msm_dsi_host_get_phy_clk_req().
Also, with this change, dsi_calc_clk_rate_6g() looks kind of empty to
stand on its own.
The original intention of the calc_clk_rate() op seems to be calculate
and store all the clocks (byte, pixel and esc).
Why change that behavior by breaking it up?
Unification between platforms. Both v2 and 6g platforms call
dsi_calc_pclk(). Let's just move it to a common code path.
Hi Dmitry,
I think what Abhinav means here is that the meaning and functionality of
calc_clk_rate() changes with this patch.
Before, calc_clk_rate() does *all* the clk_rate calculations and
assignments. But after this change, it will only calculate and assign
the escape clk rate.
I agree with Abhinav that this change renders the calc_clk_rate() op
misleading as it will not calculate all of the clock rates anymore.
Thanks,
Jessica Zhang
if (ret) {
[PATCH v2] drm/msm/dpu: Set DPU_DATA_HCTL_EN for in INTF_SC7180_MASK
DPU5 and newer targets enable this unconditionally. Move it from the
SC7280 mask to the SC7180 one.
Fixes: 7e6ee55320f0 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
Depends on:
https://lore.kernel.org/linux-arm-msm/20230405-add-dsc-support-v2-0-1072c70e9...@quicinc.com/
---
Changes in v2:
- Use a more fitting fixes tag
- Add braces around 7280 macro definition (checkpatch)
- Link to v1:
https://lore.kernel.org/r/20230508-topic-hctl_en-v1-1-0f8b5df60...@linaro.org
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27420fc863d6..005f09fcf334 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -98,9 +98,12 @@
#define INTF_SDM845_MASK (0)
#define INTF_SC7180_MASK \
- (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) |
BIT(DPU_INTF_STATUS_SUPPORTED))
+ (BIT(DPU_INTF_INPUT_CTRL) | \
+BIT(DPU_INTF_TE) | \
+BIT(DPU_INTF_STATUS_SUPPORTED) | \
+BIT(DPU_DATA_HCTL_EN))
-#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) |
BIT(DPU_INTF_DATA_COMPRESS)
+#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
---
base-commit: c47189dee0decd9ecc1e65ae376ad6d4b0b7f1f2
change-id: 20230508-topic-hctl_en-3abb999a6c99
Best regards,
--
Konrad Dybcio
Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticated only after the GSC auth
step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 94 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 16 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +
include/uapi/drm/i915_drm.h | 3 +-
5 files changed, 91 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c189ede4ef55..60f95d98e5fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,7 @@
#include "intel_huc.h"
#include "intel_huc_print.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include
#include
@@ -106,7 +107,7 @@ static enum hrtimer_restart
huc_delayed_load_timer_callback(struct hrtimer *hrti
{
struct intel_huc *huc = container_of(hrtimer, struct intel_huc,
delayed_load.timer);
- if (!intel_huc_is_authenticated(huc)) {
+ if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
huc_notice(huc, "timed out waiting for MEI GSC\n");
else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
@@ -124,7 +125,7 @@ static void huc_delayed_load_start(struct intel_huc *huc)
{
ktime_t delay;
- GEM_BUG_ON(intel_huc_is_authenticated(huc));
+ GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
/*
* On resume we don't have to wait for MEI-GSC to be re-probed, but we
@@ -284,13 +285,23 @@ void intel_huc_init_early(struct intel_huc *huc)
}
if (GRAPHICS_VER(i915) >= 11) {
- huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
- huc->status.mask = HUC_LOAD_SUCCESSFUL;
- huc->status.value = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
} else {
- huc->status.reg = HUC_STATUS2;
- huc->status.mask = HUC_FW_VERIFIED;
- huc->status.value = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;
+ huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED;
+ }
+
+ if (IS_DG2(i915)) {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL;
+ } else {
+ huc->status[INTEL_HUC_AUTH_BY_GSC].reg =
HECI_FWSTS5(MTL_GSC_HECI1_BASE);
+ huc->status[INTEL_HUC_AUTH_BY_GSC].mask =
HECI_FWSTS5_HUC_AUTH_DONE;
+ huc->status[INTEL_HUC_AUTH_BY_GSC].value =
HECI_FWSTS5_HUC_AUTH_DONE;
}
}
@@ -381,28 +392,39 @@ void intel_huc_suspend(struct intel_huc *huc)
delayed_huc_load_complete(huc);
}
-int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+static const char *auth_mode_string(struct intel_huc *huc,
+ enum intel_huc_authentication_type type)
+{
+ bool partial = !huc->loaded_via_gsc && huc->fw.is_meu_binary &&
+ type == INTEL_HUC_AUTH_BY_GUC;
partial = !loaded_via_gsc?
If it is not a GSC load then there is no two stage authentication, is
there? Does that mean the single stage auth does not count as 'all
workloads' even on platforms where two stage is not supported?
+
+ return partial ? "clear media" : "all workloads";
+}
+
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
+enum intel_huc_authentication_type type)
{
struct intel_gt *gt = huc_to_gt(huc);
int ret;
ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
+ huc->status[type].reg,
+
Re: [syzbot] [fbdev?] [usb?] WARNING in dlfb_submit_urb/usb_submit_urb (2)
On 5/19/23 17:42, Alan Stern wrote: On Fri, May 19, 2023 at 12:38:15PM +0200, Helge Deller wrote: Patch looks good and survived the test. Will you send a proper patch to the fbdev mailing list, so that I can include it? Will do. Great! Thanks! While you're working on this driver, I'm not working on that driver. Just looked into it because of this sysbot issue. I even don't have that hardware to test. here's a suggestion for another improvement you can make. The temporary buffer allocations and calls to usb_control_msg() in dlfb_get_edid() and dlfb_select_std_channel() can be replaced with calls to usb_control_msg_recv() and usb_control_msg_send() respectively. Ok, I'll look into it. Helge
[PATCH v2 3/3] drm/bridge: display-connector: handle hdmi-pwr supply
On some devices the +5V Power pin of the HDMI connector and/or the ESD
protection logic is powered on by a separate regulator. Instead of
declaring this regulator as always-on, make hdmi-connector support the
additional hdmi-pwr supply.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 55 --
1 file changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/bridge/display-connector.c
b/drivers/gpu/drm/bridge/display-connector.c
index 1d37e57242dd..d6a9aa589d17 100644
--- a/drivers/gpu/drm/bridge/display-connector.c
+++ b/drivers/gpu/drm/bridge/display-connector.c
@@ -191,6 +191,18 @@ static irqreturn_t display_connector_hpd_irq(int irq, void
*arg)
return IRQ_HANDLED;
}
+static int display_connector_get_supply(struct platform_device *pdev,
+ struct display_connector *conn,
+ const char *name)
+{
+ conn->supply = devm_regulator_get_optional(>dev, "dp-pwr");
+
+ if (conn->supply == ERR_PTR(-ENODEV))
+ conn->supply = NULL;
+
+ return PTR_ERR_OR_ZERO(conn->supply);
+}
+
static int display_connector_probe(struct platform_device *pdev)
{
struct display_connector *conn;
@@ -319,36 +331,15 @@ static int display_connector_probe(struct platform_device
*pdev)
if (type == DRM_MODE_CONNECTOR_DisplayPort) {
int ret;
- conn->supply = devm_regulator_get_optional(>dev,
"dp-pwr");
-
- if (IS_ERR(conn->supply)) {
- ret = PTR_ERR(conn->supply);
-
- switch (ret) {
- case -ENODEV:
- conn->supply = NULL;
- break;
-
- case -EPROBE_DEFER:
- return -EPROBE_DEFER;
-
- default:
- dev_err(>dev, "failed to get DP PWR
regulator: %d\n", ret);
- return ret;
- }
- }
-
- if (conn->supply) {
- ret = regulator_enable(conn->supply);
- if (ret) {
- dev_err(>dev, "failed to enable DP PWR
regulator: %d\n", ret);
- return ret;
- }
- }
+ ret = display_connector_get_supply(pdev, conn, "dp-pwr");
+ if (ret < 0)
+ return dev_err_probe(>dev, ret, "failed to get DP
PWR regulator\n");
}
/* enable DDC */
if (type == DRM_MODE_CONNECTOR_HDMIA) {
+ int ret;
+
conn->ddc_en = devm_gpiod_get_optional(>dev, "ddc-en",
GPIOD_OUT_HIGH);
@@ -356,6 +347,18 @@ static int display_connector_probe(struct platform_device
*pdev)
dev_err(>dev, "Couldn't get ddc-en gpio\n");
return PTR_ERR(conn->ddc_en);
}
+
+ ret = display_connector_get_supply(pdev, conn, "hdmi-pwr");
+ if (ret < 0)
+ return dev_err_probe(>dev, ret, "failed to get
HDMI +5V Power regulator\n");
+ }
+
+ if (conn->supply) {
+ ret = regulator_enable(conn->supply);
+ if (ret) {
+ dev_err(>dev, "failed to enable DP PWR regulator:
%d\n", ret);
+ return ret;
+ }
}
conn->bridge.funcs = _connector_bridge_funcs;
--
2.39.2
[PATCH v2 1/3] dt-bindings: display: hdmi-connector: add hdmi-pwr supply
Follow the dp-connector example and add hdmi-pwr supply to drive the 5V pin of the HDMI connector (together with some simple glue logic possibly attached to the connector). Reviewed-by: Laurent Pinchart Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/connector/hdmi-connector.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml b/Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml index 83c0d008265b..3ee8f9225984 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml @@ -36,6 +36,9 @@ properties: description: GPIO signal to enable DDC bus maxItems: 1 + hdmi-pwr-supply: +description: Power supply for the HDMI +5V Power pin + port: $ref: /schemas/graph.yaml#/properties/port description: Connection to controller providing HDMI signals -- 2.39.2
[PATCH v2 2/3] drm/bridge: display-connector: rename dp_pwr to connector_pwr
In preparation to adding support for the hdmi_pwr supply, rename dp_pwr
structure field to the generic connector_pwr.
Reviewed-by: Laurent Pinchart
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/display-connector.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/display-connector.c
b/drivers/gpu/drm/bridge/display-connector.c
index 9a12449ad7b8..1d37e57242dd 100644
--- a/drivers/gpu/drm/bridge/display-connector.c
+++ b/drivers/gpu/drm/bridge/display-connector.c
@@ -24,7 +24,7 @@ struct display_connector {
struct gpio_desc*hpd_gpio;
int hpd_irq;
- struct regulator*dp_pwr;
+ struct regulator*supply;
struct gpio_desc*ddc_en;
};
@@ -319,14 +319,14 @@ static int display_connector_probe(struct platform_device
*pdev)
if (type == DRM_MODE_CONNECTOR_DisplayPort) {
int ret;
- conn->dp_pwr = devm_regulator_get_optional(>dev,
"dp-pwr");
+ conn->supply = devm_regulator_get_optional(>dev,
"dp-pwr");
- if (IS_ERR(conn->dp_pwr)) {
- ret = PTR_ERR(conn->dp_pwr);
+ if (IS_ERR(conn->supply)) {
+ ret = PTR_ERR(conn->supply);
switch (ret) {
case -ENODEV:
- conn->dp_pwr = NULL;
+ conn->supply = NULL;
break;
case -EPROBE_DEFER:
@@ -338,8 +338,8 @@ static int display_connector_probe(struct platform_device
*pdev)
}
}
- if (conn->dp_pwr) {
- ret = regulator_enable(conn->dp_pwr);
+ if (conn->supply) {
+ ret = regulator_enable(conn->supply);
if (ret) {
dev_err(>dev, "failed to enable DP PWR
regulator: %d\n", ret);
return ret;
@@ -389,8 +389,8 @@ static int display_connector_remove(struct platform_device
*pdev)
if (conn->ddc_en)
gpiod_set_value(conn->ddc_en, 0);
- if (conn->dp_pwr)
- regulator_disable(conn->dp_pwr);
+ if (conn->supply)
+ regulator_disable(conn->supply);
drm_bridge_remove(>bridge);
--
2.39.2
[PATCH v2 0/3] drm/bridge: display-connector: add external supply support
On some devices the 5V pin of the HDMI connector and/or the ESD protection logic is powered on by a separate regulator. The dp-connector for such usecases provides dp-pwr supply support. Follow this example and make hdmi-connector support the hdmi-pwr supply. Changes since v1: - Changed the pin description to HDMI +5V Power - Renamed 'connector_pwr' to simpler 'supply' - Extracted the common supply-handling code for DP and HDMI Dmitry Baryshkov (3): dt-bindings: display: hdmi-connector: add hdmi-pwr supply drm/bridge: display-connector: rename dp_pwr to connector_pwr drm/bridge: display-connector: handle hdmi-pwr supply .../display/connector/hdmi-connector.yaml | 3 + drivers/gpu/drm/bridge/display-connector.c| 61 ++- 2 files changed, 35 insertions(+), 29 deletions(-) -- 2.39.2
[RESUBMIT][PATCH] x86/mm: Fix PAT bit missing from page protection modify mask
Visible glitches have been observed when running graphics applications on
Linux under Xen hypervisor. Those observations have been confirmed with
failures from kms_pwrite_crc Intel GPU test that verifies data coherency
of DRM frame buffer objects using hardware CRC checksums calculated by
display controllers, exposed to userspace via debugfs. Affected
processing paths have then been identified with new IGT test variants that
mmap the objects using different methods and caching modes [1].
When running as a Xen PV guest, Linux uses Xen provided PAT configuration
which is different from its native one. In particular, Xen specific PTE
encoding of write-combining caching, likely used by graphics applications,
differs from the Linux default one found among statically defined minimal
set of supported modes. Since Xen defines PTE encoding of the WC mode as
_PAGE_PAT, it no longer belongs to the minimal set, depends on correct
handling of _PAGE_PAT bit, and can be mismatched with write-back caching.
When a user calls mmap() for a DRM buffer object, DRM device specific
.mmap file operation, called from mmap_region(), takes care of setting PTE
encoding bits in a vm_page_prot field of an associated virtual memory area
structure. Unfortunately, _PAGE_PAT bit is not preserved when the vma's
.vm_flags are then applied to .vm_page_prot via vm_set_page_prot(). Bits
to be preserved are determined with _PAGE_CHG_MASK symbol that doesn't
cover _PAGE_PAT. As a consequence, WB caching is requested instead of WC
when running under Xen (also, WP is silently changed to WT, and UC
downgraded to UC_MINUS). When running on bare metal, WC is not affected,
but WP and WT extra modes are unintentionally replaced with WC and UC,
respectively.
WP and WT modes, encoded with _PAGE_PAT bit set, were introduced by commit
281d4078bec3 ("x86: Make page cache mode a real type"). Care was taken
to extend _PAGE_CACHE_MASK symbol with that additional bit, but that
symbol has never been used for identification of bits preserved when
applying page protection flags. Support for all cache modes under Xen,
including the problematic WC mode, was then introduced by commit
47591df50512 ("xen: Support Xen pv-domains using PAT").
Extend bitmask used by pgprot_modify() for selecting bits to be preserved
with _PAGE_PAT bit. However, since that bit can be reused as _PAGE_PSE,
and the _PAGE_CHG_MASK symbol, primarly used by pte_modify(), is likely
intentionally defined with that bit not set, keep that symbol unchanged.
[1] https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/commit/0f0754413f14
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7648
Fixes: 281d4078bec3 ("x86: Make page cache mode a real type")
Signed-off-by: Janusz Krzysztofik
Tested-by: Marek Marczykowski-Górecki
Reviewed-by: Andi Shyti
Cc: sta...@vger.kernel.org # v3.19+
---
arch/x86/include/asm/pgtable.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 15ae4d6ba4768..56466afd04307 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -654,8 +654,10 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
#define pgprot_modify pgprot_modify
static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
{
- pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
- pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK;
+ unsigned long mask = _PAGE_CHG_MASK | _PAGE_CACHE_MASK;
+
+ pgprotval_t preservebits = pgprot_val(oldprot) & mask;
+ pgprotval_t addbits = pgprot_val(newprot) & ~mask;
return __pgprot(preservebits | addbits);
}
--
2.40.1
Re: [PATCH v5 1/3] dt-bindings: display: panel: Add Samsung S6D7AA0 LCD panel controller
On Fri, May 19, 2023 at 07:03:52PM +0200, Artur Weber wrote: > Add bindings for the S6D7AA0 LCD panel controller, including the > S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family > of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels > used in the Samsung Galaxy Tab A 8.0 and 9.7 2015. > > Signed-off-by: Artur Weber > --- > Changed in v2: > - Updated commit message > - Added reg to required properties > - Reordered required properties > Changed in v3: > - Fixed patch that didn't apply > Changed in v4: > - Added LSL080AL03, LTL101AT01 compatibles > - Added description to reset-gpios > - Added vmipi-supply, renamed enable-supply to power-supply > Changed in v5: > - Changed compatibles to avoid concatenating multiple model numbers > - Removed '|' from multiline descriptions > - Fixed license Looks like you've resolved the things Krzysztof and Rob took issue with. Reviewed-by: Conor Dooley Thanks, Conor. signature.asc Description: PGP signature
Re: [PATCH v4 00/12] SM63(50|75) DPU support
On 2023-05-19 19:04:21, Konrad Dybcio wrote: > v3 -> v4: > - Drop adding new QoS LUT entries > - Add safe_lut_tbl for both SoCs I may not have pinged you correctly with this message [1], but can you add the DSC configuration for both SoCs? [1]: https://lore.kernel.org/linux-arm-msm/u47xthqfjxpbbzjbvnrz4qa2f2m3aip4iose7cwuhzg4raf7db@qxbos7u55wko/ - Marijn > > Depends on: > - > https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/ > > v3: > https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v3-0-9837d6b35...@linaro.org > > v2 -> v3: > - Don't duplicate qcm2290_lm_sblk > - Use DEFAULT_DPU_LINE_WIDTH defines > - Fix up sspp clk assignments for sm6350 > - Add 6350-6375-common QoS data straight to the common file > instead of moving it around after adding it > - Fix up iommu compatible order before adding new entries > - Reuse sm6350 msm_mdss_data for sm6375 > - INTF_SC7180_MASK -> INTF_SC7280_MASK (enable HCTL) on 6375 > - use double tabs in catalog headers > - remove one unused entry in 6350 dpu_qos_lut_entry > - add missing tear IRQs, drop INTF0 irq on 6375 > - don't overduplicate DPU bindings, reuse 7180 > - Pick up tags > - Rebase on INTF_TE v4 and next-20230504 > > Depends on: > - > https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/ > > v2: > https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v2-0-5def73f50...@linaro.org > > v1 -> v2: > - Rebase on the DPU catalog rework and INTF_TE > - Fix QSEED(3L/4) discrepancies > - Fixed DMA/cursor discrepancies for 6350 > - No deduplication, that's gonna be handled in catalogrework 2: > "the return of the catalogrework" > - Split MDSS & DPU binding additions > - Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework > - Split MDSS and DPU additions > - Pick up Rob's acks > > Depends on (and based on): > https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v2-0-ef76c877e...@somainline.org/T/#t > > v1: > https://lore.kernel.org/linux-arm-msm/20230211122656.1479141-1-konrad.dyb...@linaro.org/ > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (12): > dt-bindings: display/msm: dsi-controller-main: Add SM6350 > dt-bindings: display/msm: dsi-controller-main: Add SM6375 > dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 > dt-bindings: display/msm: Add SM6350 MDSS > dt-bindings: display/msm: Add SM6375 MDSS > drm/msm/dpu: Add SM6350 support > drm/msm: mdss: Add SM6350 support > drm/msm/dpu: Add SM6375 support > drm/msm: mdss: Add SM6375 support > iommu/arm-smmu-qcom: Sort the compatible list alphabetically > iommu/arm-smmu-qcom: Add SM6375 DPU compatible > iommu/arm-smmu-qcom: Add SM6350 DPU compatible > > .../bindings/display/msm/dsi-controller-main.yaml | 4 + > .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++- > .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 > .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 > + > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 ++ > .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 + > drivers/gpu/drm/msm/msm_mdss.c | 10 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +- > 11 files changed, 821 insertions(+), 3 deletions(-) > --- > base-commit: c437aff71b13c5ca77821ec1bab98ca7e18716d0 > change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26 > > Best regards, > -- > Konrad Dybcio >
[PATCH v2 2/4] video: backlight: lp855x: get PWM for PWM mode during probe
Also deprecate the pwm-period DT property, as it is now redundant
(pwms property already contains period value).
Signed-off-by: Artur Weber
---
drivers/video/backlight/lp855x_bl.c | 48 -
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/video/backlight/lp855x_bl.c
b/drivers/video/backlight/lp855x_bl.c
index a57c9ef3b1cc..0ef850dd8e84 100644
--- a/drivers/video/backlight/lp855x_bl.c
+++ b/drivers/video/backlight/lp855x_bl.c
@@ -218,23 +218,10 @@ static int lp855x_configure(struct lp855x *lp)
static void lp855x_pwm_ctrl(struct lp855x *lp, int br, int max_br)
{
- struct pwm_device *pwm;
struct pwm_state state;
- /* request pwm device with the consumer name */
- if (!lp->pwm) {
- pwm = devm_pwm_get(lp->dev, lp->chipname);
- if (IS_ERR(pwm))
- return;
-
- lp->pwm = pwm;
-
- pwm_init_state(lp->pwm, );
- } else {
- pwm_get_state(lp->pwm, );
- }
+ pwm_get_state(lp->pwm, );
- state.period = lp->pdata->period_ns;
state.duty_cycle = div_u64(br * state.period, max_br);
state.enabled = state.duty_cycle;
@@ -339,6 +326,7 @@ static int lp855x_parse_dt(struct lp855x *lp)
of_property_read_string(node, "bl-name", >name);
of_property_read_u8(node, "dev-ctrl", >device_control);
of_property_read_u8(node, "init-brt", >initial_brightness);
+ /* Deprecated, specify period in pwms property instead */
of_property_read_u32(node, "pwm-period", >period_ns);
/* Fill ROM platform data if defined */
@@ -399,6 +387,7 @@ static int lp855x_probe(struct i2c_client *cl)
const struct i2c_device_id *id = i2c_client_get_device_id(cl);
const struct acpi_device_id *acpi_id = NULL;
struct device *dev = >dev;
+ struct pwm_state pwmstate;
struct lp855x *lp;
int ret;
@@ -457,11 +446,6 @@ static int lp855x_probe(struct i2c_client *cl)
}
}
- if (lp->pdata->period_ns > 0)
- lp->mode = PWM_BASED;
- else
- lp->mode = REGISTER_BASED;
-
lp->supply = devm_regulator_get(dev, "power");
if (IS_ERR(lp->supply)) {
if (PTR_ERR(lp->supply) == -EPROBE_DEFER)
@@ -472,11 +456,31 @@ static int lp855x_probe(struct i2c_client *cl)
lp->enable = devm_regulator_get_optional(dev, "enable");
if (IS_ERR(lp->enable)) {
ret = PTR_ERR(lp->enable);
- if (ret == -ENODEV) {
+ if (ret == -ENODEV)
lp->enable = NULL;
- } else {
+ else
return dev_err_probe(dev, ret, "getting enable
regulator\n");
- }
+ }
+
+ lp->pwm = devm_pwm_get(lp->dev, lp->chipname);
+ if (IS_ERR(lp->pwm)) {
+ ret = PTR_ERR(lp->pwm);
+ if (ret == -ENODEV || ret == -EINVAL)
+ lp->pwm = NULL;
+ else
+ return dev_err_probe(dev, ret, "getting PWM\n");
+
+ lp->mode = REGISTER_BASED;
+ dev_dbg(dev, "mode: register based\n");
+ } else {
+ pwm_init_state(lp->pwm, );
+ /* Legacy platform data compatibility */
+ if (lp->pdata->period_ns > 0)
+ pwmstate.period = lp->pdata->period_ns;
+ pwm_apply_state(lp->pwm, );
+
+ lp->mode = PWM_BASED;
+ dev_dbg(dev, "mode: PWM based\n");
}
if (lp->supply) {
--
2.40.1
[PATCH v2 4/4] arm64: dts: adapt to LP855X bindings changes
Change underscores in ROM node names to dashes, and remove deprecated
pwm-period property.
Signed-off-by: Artur Weber
---
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 38f4ff229bef..a6a58e51822d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -58,19 +58,17 @@ backlight: backlight@2c {
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0xff>;
- pwm-period = <29334>;
-
pwms = < 0 29334>;
pwm-names = "lp8557";
/* boost frequency 1 MHz */
- rom_13h {
+ rom-13h {
rom-addr = /bits/ 8 <0x13>;
rom-val = /bits/ 8 <0x01>;
};
/* 3 LED string */
- rom_14h {
+ rom-14h {
rom-addr = /bits/ 8 <0x14>;
rom-val = /bits/ 8 <0x87>;
};
--
2.40.1
[PATCH v2 1/4] dt-bindings: backlight: lp855x: convert to YAML and modernize
Notable changes:
- ROM child nodes use dashes instead of underscores; the driver
reads all child nodes regardless of their names, so this doesn't
break ABI.
- pwm-period argument is deprecated, as it effectively duplicates
the period value provided in pwms. The driver continues to accept
the property, so this should not break ABI.
Signed-off-by: Artur Weber
Reviewed-by: Rob Herring
---
Changed in v2:
- Added additionalProperties to ROM patternProperties
---
.../leds/backlight/lp855x-backlight.yaml | 149 ++
.../bindings/leds/backlight/lp855x.txt| 72 -
2 files changed, 149 insertions(+), 72 deletions(-)
create mode 100644
Documentation/devicetree/bindings/leds/backlight/lp855x-backlight.yaml
delete mode 100644 Documentation/devicetree/bindings/leds/backlight/lp855x.txt
diff --git
a/Documentation/devicetree/bindings/leds/backlight/lp855x-backlight.yaml
b/Documentation/devicetree/bindings/leds/backlight/lp855x-backlight.yaml
new file mode 100644
index ..9416e1bfab92
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/lp855x-backlight.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/lp855x-backlight.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments LP855X backlight controllers
+
+maintainers:
+ - Artur Weber
+
+properties:
+ compatible:
+enum:
+ - ti,lp8550
+ - ti,lp8551
+ - ti,lp8552
+ - ti,lp8553
+ - ti,lp8555
+ - ti,lp8556
+ - ti,lp8557
+
+ reg:
+maxItems: 1
+
+ dev-ctrl:
+$ref: /schemas/types.yaml#/definitions/uint8
+description:
+ Value of device control register. This is a device-specific value.
+
+ bl-name:
+$ref: /schemas/types.yaml#/definitions/string
+description: Backlight device name.
+
+ init-brt:
+$ref: /schemas/types.yaml#/definitions/uint8
+description: Initial value of backlight brightness.
+
+ power-supply:
+description: Regulator which controls the 3V rail.
+
+ enable-supply:
+description: Regulator which controls the EN/VDDIO input.
+
+ pwms:
+maxItems: 1
+description: |
+ PWM channel to use for controlling the backlight; setting this
+ enables the PWM-based backlight control mode.
+
+ pwm-names: true
+
+ pwm-period:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ PWM period value. Deprecated; set the period value in the pwms
+ property instead.
+deprecated: true
+
+patternProperties:
+ "^rom-[0-9a-f]{2}h$":
+type: object
+description: Nodes containing the values of configuration registers.
+additionalProperties: false
+properties:
+ rom-addr:
+$ref: /schemas/types.yaml#/definitions/uint8
+description: Register address of ROM area to be updated.
+
+ rom-val:
+$ref: /schemas/types.yaml#/definitions/uint8
+description: Value to write to the ROM register.
+
+required:
+ - compatible
+ - reg
+ - dev-ctrl
+
+unevaluatedProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+backlight@2c {
+compatible = "ti,lp8555";
+reg = <0x2c>;
+
+dev-ctrl = /bits/ 8 <0x00>;
+
+pwms = < 0 1>;
+pwm-names = "lp8555";
+
+/* 4V OV, 4 output LED0 string enabled */
+rom-14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0xcf>;
+};
+
+/* Heavy smoothing, 24ms ramp time step */
+rom-15h {
+ rom-addr = /bits/ 8 <0x15>;
+ rom-val = /bits/ 8 <0xc7>;
+};
+
+/* 4 output LED1 string enabled */
+rom-19h {
+ rom-addr = /bits/ 8 <0x19>;
+ rom-val = /bits/ 8 <0x0f>;
+};
+};
+};
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+backlight@2c {
+compatible = "ti,lp8556";
+reg = <0x2c>;
+
+bl-name = "lcd-bl";
+dev-ctrl = /bits/ 8 <0x85>;
+init-brt = /bits/ 8 <0x10>;
+};
+ };
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+backlight@2c {
+compatible = "ti,lp8557";
+reg = <0x2c>;
+enable-supply = <_vddio>;
+power-supply = <_vdd>;
+
+dev-ctrl = /bits/ 8 <0x41>;
+init-brt = /bits/ 8 <0x0a>;
+
+/* 4V OV, 4 output LED string enabled */
+rom-14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0xcf>;
+};
+};
+};
diff --git a/Documentation/devicetree/bindings/leds/backlight/lp855x.txt
b/Documentation/devicetree/bindings/leds/backlight/lp855x.txt
deleted file mode 100644
index
[PATCH v2 0/4] video: backlight: lp855x: modernize bindings
Convert TI LP855X backlight controller bindings from TXT to YAML and, while we're at it, rework some of the code related to PWM handling. Also correct existing DTS files to avoid introducing new dtb_check errors. Signed-off-by: Artur Weber Changed in v2: - Added additionalProperties to ROM patternProperties in DT binding Artur Weber (4): dt-bindings: backlight: lp855x: convert to YAML and modernize video: backlight: lp855x: get PWM for PWM mode during probe ARM: dts: adapt to LP855X bindings changes arm64: dts: adapt to LP855X bindings changes .../leds/backlight/lp855x-backlight.yaml | 149 ++ .../bindings/leds/backlight/lp855x.txt| 72 - .../dts/qcom-apq8026-samsung-matisse-wifi.dts | 1 - ...-msm8974pro-sony-xperia-shinano-castor.dts | 23 +-- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 6 +- drivers/video/backlight/lp855x_bl.c | 48 +++--- 6 files changed, 189 insertions(+), 110 deletions(-) create mode 100644 Documentation/devicetree/bindings/leds/backlight/lp855x-backlight.yaml delete mode 100644 Documentation/devicetree/bindings/leds/backlight/lp855x.txt base-commit: fb200218b40b7864f64f1a47de61e035d8934e92 -- 2.40.1
Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "MEU binary" for
clarity, while the latter is now based on the fuse instead of the binary
format. This way, all the legacy load paths are automatically taken
(including the auth by GuC) without having to implement further code
changes.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 27 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 14 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
5 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 062ff914b274..c189ede4ef55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -298,31 +298,38 @@ void intel_huc_init_early(struct intel_huc *huc)
static int check_huc_loading_mode(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
- bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
- bool hw_uses_gsc = false;
+ bool fw_is_meu = huc->fw.is_meu_binary;
/*
* The fuse for HuC load via GSC is only valid on platforms that have
* GuC deprivilege.
*/
if (HAS_GUC_DEPRIVILEGE(gt->i915))
- hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
- GSC_LOADS_HUC;
+ huc->loaded_via_gsc = intel_uncore_read(gt->uncore,
GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
- if (fw_needs_gsc != hw_uses_gsc) {
- huc_err(huc, "mismatch between FW (%s) and HW (%s) load
modes\n",
- HUC_LOAD_MODE_STRING(fw_needs_gsc),
HUC_LOAD_MODE_STRING(hw_uses_gsc));
+ if (huc->loaded_via_gsc && !fw_is_meu) {
+ huc_err(huc, "HW requires a MEU blob, but we found a legacy
one\n");
return -ENOEXEC;
}
- /* make sure we can access the GSC via the mei driver if we need it */
+ /*
+* Newer meu blobs contain the old FW structure inside. If we found
+* that, we can use it to load the legacy way.
+*/
+ if (!huc->loaded_via_gsc && fw_is_meu && !huc->fw.dma_start_offset) {
+ huc_err(huc," HW in legacy mode, but we have an incompatible meu
blob\n");
Leading space in the message? MEU or meu?
+ return -ENOEXEC;
+ }
+
+ /* make sure we can access the GSC if we need it */
if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_INTEL_MEI_GSC))
&&
- fw_needs_gsc) {
+ !HAS_ENGINE(gt, GSC0) && huc->loaded_via_gsc) {
Should that be || !HAS_ENGINE ?
huc_info(huc, "can't load due to missing MEI modules\n");
'missing MEI modules or GSC engine'?
return -EIO;
}
- huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(fw_needs_gsc));
+ huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(huc->loaded_via_gsc));
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index db555b3c1f56..345e1b9aa062 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -39,6 +39,8 @@ struct intel_huc {
struct notifier_block nb;
enum intel_huc_delayed_load_status status;
} delayed_load;
+
+ bool loaded_via_gsc;
};
int intel_huc_sanitize(struct intel_huc *huc);
@@ -73,7 +75,7 @@ static inline bool intel_huc_is_used(struct intel_huc *huc)
static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
{
- return huc->fw.loaded_via_gsc;
+ return huc->loaded_via_gsc;
}
static inline bool intel_huc_wait_required(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index f1c973e1c676..88ad2c322c4a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -34,7 +34,7 @@ int intel_huc_fw_get_binary_info(struct intel_uc_fw *huc_fw,
const void *data, s
size_t min_size = sizeof(*header);
int i;
- if (!huc_fw->loaded_via_gsc) {
+ if (!huc_fw->is_meu_binary) {
huc_err(huc, "Invalid FW type MEU parsing!\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index da6fcfe1d80a..3338dd45e78b 100644
---
[PATCH 0/2] drm/panel: add fannal c3004 panel
Fannal C3004 is a 2 lane MIPI DSI 480x800 panel which requires initialization with DSI DCS commands. After some commands delay is required. In previous discussions for device tree [1] [2] and device driver [3] were named mipi-dsi-bringup. [1] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/cao9szn3t-givipb5oh_3mzqzbnxbdqqz0weg8uamo-1w2uk...@mail.gmail.com/ [2] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/CAO9szn18KsR0c+U8EEY1=xnmsKMxy6SEArMUic0z=ayjdvw...@mail.gmail.com/ [3] https://lists.freedesktop.org/archives/dri-devel/2023-May/404775.html Paulo Pavacic (2): dt-bindings: display: panel: add fannal,c3004 drm/panel-fannal-c3004: Add fannal c3004 DSI panel .../bindings/display/panel/fannal,c3004.yaml | 75 .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 7 + drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-fannal-c3004.c| 405 ++ 6 files changed, 501 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml create mode 100644 drivers/gpu/drm/panel/panel-fannal-c3004.c -- 2.40.1
[PATCH 1/2] dt-bindings: display: panel: add fannal,c3004
Added fannal to vendor-prefixes and dt bindings for Fannal C3004.
Fannal C3004 is a 480x800 MIPI DSI Panel which requires
DCS initialization sequences with certain delays between certain
commands.
Signed-off-by: Paulo Pavacic
---
v3 changelog:
- renamed yml file
- refactored yml file to describe fannal,c3004
- added matrix URI to MAINTAINERS
v2 changelog:
- revised driver title, now describes purpose
- revised description, now describes hw
- revised maintainers, now has only 1 mail
- removed diacritics from commit/commit author
- properties/compatible is now enum
- compatible using only lowercase
- revised dts example
- modified MAINTAINERS in this commit (instead of driver commit)
- dt_bindings_check checked yml
- checkpatch warning fixed
---
.../bindings/display/panel/fannal,c3004.yaml | 75 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 6 ++
3 files changed, 83 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml
diff --git a/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml
b/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml
new file mode 100644
index ..a86b5ce02aa2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/fannal,c3004.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fannal C3004 MIPI-DSI
+
+maintainers:
+ - Paulo Pavacic
+
+description: |
+ Fannal C3004 is a 480x800 panel which requires DSI DCS
+ initialization sequences.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: fannal,c3004
+
+ reg: true
+ reset-gpios: true
+
+ vdd-supply:
+description: power supply voltage
+ vddio-supply:
+description: power supply voltage for IO
+
+ width-mm:
+description: physical panel width [mm]
+ height-mm:
+description: physical panel height [mm]
+
+ panel-timing: true
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "fannal,c3004";
+reg = <0>;
+pinctrl-0 = <_mipi_dsi_rst>;
+pinctrl-names = "default";
+reset-gpios = < 9 GPIO_ACTIVE_LOW>;
+vdd-supply = <>;
+vddio-supply = <>;
+width-mm = <93>;
+height-mm = <56>;
+panel-timing {
+clock-frequency = <2700>;
+hactive = <480>;
+vactive = <800>;
+hfront-porch = <30>;
+hback-porch = <30>;
+hsync-len = <8>;
+vback-porch = <30>;
+vfront-porch = <30>;
+vsync-len = <8>;
+};
+};
+};
+...
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 82d39ab0231b..f962750f630a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -462,6 +462,8 @@ patternProperties:
description: Facebook
"^fairphone,.*":
description: Fairphone B.V.
+ "^fannal,.*":
+description: Fannal Electronics Co., Ltd
"^faraday,.*":
description: Faraday Technology Corporation
"^fastrax,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index 5c22c828ab46..62374c8424b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6427,6 +6427,12 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/panel/ebbg,ft8719.yaml
F: drivers/gpu/drm/panel/panel-ebbg-ft8719.c
+DRM DRIVER FOR FANNAL C3004373132019A
+M: Paulo Pavacic
+S: Maintained
+C: matrix:r/mipi-dsi-bringup:matrix.org
+F: Documentation/devicetree/bindings/display/panel/panel-fannal,c3004.yaml
+
DRM DRIVER FOR FARADAY TVE200 TV ENCODER
M: Linus Walleij
S: Maintained
--
2.40.1
[PATCH 2/2] drm/panel-fannal-c3004: Add fannal c3004 DSI panel
Fannal C3004 is a 480x800 display made by fannal that requires
DCS initialization sequences.
Signed-off-by: Paulo Pavacic
---
v2 changelog:
- renamed from panel-mipi-dsi-bringup
- only one MAINTAINER e-mail
---
MAINTAINERS| 1 +
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-fannal-c3004.c | 405 +
4 files changed, 418 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-fannal-c3004.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 62374c8424b9..93fc1ae6832f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6432,6 +6432,7 @@ M:Paulo Pavacic
S: Maintained
C: matrix:r/mipi-dsi-bringup:matrix.org
F: Documentation/devicetree/bindings/display/panel/panel-fannal,c3004.yaml
+F: drivers/gpu/drm/panel/panel-fannal-c3004.c
DRM DRIVER FOR FARADAY TVE200 TV ENCODER
M: Linus Walleij
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 2b9d6db7860b..a1041c1e6bf6 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -144,6 +144,17 @@ config DRM_PANEL_ELIDA_KD35T133
KD35T133 controller for 320x480 LCD panels with MIPI-DSI
system interfaces.
+config DRM_PANEL_FANNAL_C3004
+ tristate "Fannal C3004 panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ help
+ Say Y here if you want to enable support for the Fannal C3004
+ 2-lane 480x800 MIPI DSI panel which requires initialization
+ sequence.
+
+ If M is selected the module will be called panel-fannal-c3004.
+
config DRM_PANEL_FEIXIN_K101_IM2BA02
tristate "Feixin K101 IM2BA02 panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index ff169781e82d..13c0f00038b5 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o
obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
+obj-$(CONFIG_DRM_PANEL_FANNAL_C3004) += panel-fannal-c3004.o
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) +=
panel-feiyang-fy07024di26a30d.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o
diff --git a/drivers/gpu/drm/panel/panel-fannal-c3004.c
b/drivers/gpu/drm/panel/panel-fannal-c3004.c
new file mode 100644
index ..decbd0c59093
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-fannal-c3004.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MIPI DSI driver for Fannal C3004.
+ * Copyright (C) 2023, Zenitel
+ * Author: Paulo Pavacic
+ */
+
+// ↓ include headers, static values, static functions ↓
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static const struct fann_panel_info fann_c3004_panel_info;
+
+struct fann_panel_info {
+ const struct drm_display_mode *display_mode;
+ u32 num_of_dsi_lanes;
+ u32 mipi_dsi_format;
+ u32 mipi_dsi_mode_flags;
+ u32 bus_flags;
+ u32 video_mode;
+ void (*panel_enable_function)(struct mipi_dsi_device *dsi);
+};
+
+struct fann_panel_data {
+ const struct fann_panel_info *panel_info;
+ struct drm_panel panel;
+ struct gpio_desc *reset;
+};
+
+static struct fann_panel_data *
+get_fann_panel_data_from_panel(struct drm_panel *panel)
+{
+ return container_of(panel, struct fann_panel_data, panel);
+}
+
+static const struct fann_panel_info *
+get_fann_panel_info_from_panel(struct drm_panel *panel)
+{
+ return get_fann_panel_data_from_panel(panel)->panel_info;
+}
+
+enum FANN_VIDEO_MODES_ENUM {
+ FANN_BURST,
+ FANN_SYNC_EVENT,
+ FANN_SYNC_PULSE,
+ FANN_COMMAND,
+};
+
+static const u32 FANN_VIDEO_MODES[] = {
+ MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO, //BURST
+ MIPI_DSI_MODE_VIDEO, //SYNC_EVENT
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO, //SYNC_PULSE
+ MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_VSYNC_FLUSH //COMMAND MODE
+};
+
+//macro for writing to DSI
+#define WRITE_DSI(dsi, seq...)
\
+ {
\
+ const u8 d[] = { seq };
\
+ int ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d));
\
+ if (ret < 0) {
\
+ dev_err(>dev,
\
+ "Error (%d) occurred while trying to"
\
+ " write MIPI
Re: [v13,1/2] drm: add kms driver for loongson display controller
I test this on my 3A5000 + 7A1000 and 3A5000 + 7A2000 desktop, and this works well, so: Tested-by: Liu Peibao Br, Peibao On 5/15/23 11:57 PM, Sui Jingfeng wrote: > Loongson display controller IP has been integrated in both Loongson north > bridge chipset(ls7a1000/ls7a2000) and Loongson SoCs(ls2k1000/ls2k2000), it > has been even included in Loongson self-made BMC products. > > This display controller is a PCI device. It has two display pipes and each > display pipe support a primary plane and a cursor plane. For the DC in the > ls7a1000 and ls2k1000, each display pipe has a DVO output interface which > provide RGB888 signals, vertical & horizontal synchronisations and pixel > clock. Each CRTC is able to support 1920x1080@60Hz, the maximum resolution > of each display pipe is 2048x2048 according to the hardware spec. > > For the DC in LS7A2000, each display pipe is equipped with a built-in HDMI > encoder which is compliant with the HDMI 1.4 specification, thus it support > 3840x2160@30Hz. The first display pipe is also equipped with a transparent > vga encoder which is parallel with the HDMI encoder. The DC in LS7A2000 is > more complete compare with the one in old chips, besides above feature, it > has two hardware cursors, two hardware vblank counter and two scanout > position recorders unit. It also support tiled framebuffer format which > can be scanout the tiled framebuffer rendered by the LoongGPU directly. > > v1 -> v2: > 1) Use hpd status reg when polling for ls7a2000 > 2) Fix all warnings emerged when compile with W=1 > > v2 -> v3: > 1) Add COMPILE_TEST in Kconfig and make the driver off by default > 2) Alphabetical sorting headers (Thomas) > 3) Untangle register access functions as much as possible (Thomas) > 4) Switch to TTM based memory manager and prefer cached mapping > for Loongson SoC (Thomas) > 5) Add chip id detection method, now all models are distinguishable. > 6) Revise builtin HDMI phy driver, nearly all main stream mode > below 4K@30Hz is tested, this driver supported these mode very > well including clone display mode and extend display mode. > > v3 -> v4: > 1) Quickly fix a small mistake. > > v4 -> v5: > 1) Drop potential support for Loongson 2K series SoC temporary, > this part should be resend with the DT binding patch in the future. > 2) Add per display pipe debugfs support to the builtin HDMI encoder. > 3) Rewrite atomic_update() for hardware cursors plane(Thomas) > 4) Rewrite encoder and connector initialization part, untangle it > according to the chip(Thomas). > > v5 -> v6: > 1) Remove stray code which didn't get used, say lsdc_of_get_reserved_ram > 2) Fix all typos I could found, make sentences and code more readable > 3) Untangle lsdc_hdmi*_connector_detect() function according to the pipe > 4) After a serious consideration, we rename this driver as loongson. > Because we also have drivers toward the LoongGPU IP in LS7A2000 and > LS2K2000. Besides, there are also drivers about the external encoder, > HDMI audio driver and vbios support etc. This patch only provide DC > driver part, my teammate Li Yi believe that loongson will be more > suitable for loongson graphics than lsdc in the long run. > > loongson.ko = LSDC + LoongGPU + encoders driver + vbios/DT ... > > v6 -> v7: > 1) Add prime support, self-sharing is works. sharing buffer with etnaviv > is also tested, and its works with limitation. > 2) Implement buffer objects tracking with list_head. > 3) S3(sleep to RAM) is tested on ls3a5000+ls7a2000 evb and it works. > 4) Rewrite lsdc_bo_move, since ttm core stop allocating resources > during BO creation. Patch V1 ~ V6 of this series no longer works > on latest kernel. Thus, we send V7 to revival them. > > v7 -> v8: > 1) Zero a compile warnnings on 32-bit platform, compile with W=1 > 2) Revise lsdc_bo_gpu_offset() and minor cleanup > 3) Pageflip tested on the virtual terminal with following commands > > modetest -M loongson -s 32:1920x1080 -v > modetest -M loongson -s 34:1920x1080 -v -F tiles > >It works like a charm, when running pageflip test with dual screnn >configuration, another two additional bo created by the modetest >emerged, VRAM usage up to 40+MB, well we have at least 64MB, still >enough. > ># cat bos > >bo[]: size: 8112kB VRAM >bo[0001]: size: 16kB VRAM >bo[0002]: size: 16kB VRAM >bo[0003]: size:16208kB VRAM >bo[0004]: size: 8112kB VRAM >bo[0005]: size: 8112kB VRAM > > v8 -> v9: > 1) Select I2C and I2C_ALGOBIT in Kconfig and should depend on MMU. > 2) Using pci_get_domain_bus_and_slot to get the GPU device. > 3) Other minor improvements. > > Those patches are tested on ls3a5000 + ls7a1000 CRB, ls3a5000 + ls7a2000 > evb, and lemote a1901 board(ls3a4000 + ls7a1000). On loongson mips CPU, > the write combine support should be enabled, to get a decent
Re: [PATCH] MAINTAINERS: Add Marijn Suijten as drm/msm reviewer
On Tue, Apr 11, 2023 at 3:46 PM Dmitry Baryshkov wrote: > > On 12/04/2023 01:43, Marijn Suijten wrote: > > As I get more and more active in the drm/msm space, yet sometimes miss > > out on patches (where I was involved in previous discussions), add > > myself as reviewer to make this involvement clear. > > > > Signed-off-by: Marijn Suijten > > --- > > > > Note that this is only a slight commitment from my part to look at > > patches arriving in this area, most notably on the DPU1 driver and only > > if day-to-day workload allows for it. > > I think Marijn does a good job of reviewing incoming patches in the > mentioned area. > > Acked-by: Dmitry Baryshkov Acked-by: Rob Clark > > > > > MAINTAINERS | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 04d7c816d46a..fd1b717c57d8 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -6536,6 +6536,7 @@ M: Rob Clark > > M: Abhinav Kumar > > M: Dmitry Baryshkov > > R: Sean Paul > > +R: Marijn Suijten > > L: linux-arm-...@vger.kernel.org > > L: dri-devel@lists.freedesktop.org > > L: freedr...@lists.freedesktop.org > > -- > With best wishes > Dmitry >
Re: [v1 1/2] drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel
Hi,
On Fri, May 19, 2023 at 1:02 AM Cong Yang
wrote:
>
> The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
> it seems that the touch can communicate successfully only when the RST
> signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
> let's set the default high for RST at boe_panel_add.
No, that doesn't work. There are no guarantees about the ordering of
the probe of the i2c_hid device and the panel and the order could
change from version to version of Linux. Also: deasserting this reset
early like this (before regulators are turned on) can cause leakage
since that will make the signal go high and the touchscreen can suck
current out of that line.
Is it possible to change the hardware to fix this and have separate
reset lines for the touchscreen and the panel?
For a long time, I have felt like we needed a better solution in Linux
for stuff like this, but I've never found a clean way to do it. We
really want the touchscreen to power on and off together with the
panel, where the panel is in charge and the touchscreen always powers
on after the panel and powers off before the panel. I can't promise
anything, but I can see if I can find some time to whip up a
prototype.
> @@ -1698,6 +1768,34 @@ static const struct panel_desc
> starry_qfh032011_53g_desc = {
> .init_cmds = starry_qfh032011_53g_init_cmd,
> };
>
> +static const struct drm_display_mode starry_himax83102_j02_default_mode = {
> + .clock = 161600,
> + .hdisplay = 1200,
> + .hsync_start = 1200 + 40,
> + .hsync_end = 1200 + 40 + 20,
> + .htotal = 1200 + 40 + 20 + 40,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 116,
> + .vsync_end = 1920 + 116 + 8,
> + .vtotal = 1920 + 116 + 8 + 12,
> + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct panel_desc starry_himax83102_j02_desc = {
> + .modes = _himax83102_j02_default_mode,
> + .bpc = 8,
> + .size = {
> + .width_mm = 141,
> + .height_mm = 226,
> + },
> + .lanes = 4,
> + .format = MIPI_DSI_FMT_RGB888,
> + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> + MIPI_DSI_MODE_LPM,
> + .init_cmds = starry_himax83102_j02_init_cmd,
> + .enable_gpio_init_value = 1,
> + .lp11_before_reset = true,
> +};
> static int boe_panel_get_modes(struct drm_panel *panel,
nit: put a blank line above.
> @@ -1871,6 +1969,9 @@ static const struct of_device_id boe_of_match[] = {
> { .compatible = "starry,2081101qfh032011-53g",
> .data = _qfh032011_53g_desc
> },
> + { .compatible = "starry,himax83102-j02",
> + .data = _himax83102_j02_desc
You need device tree bindings for the above compatible string.
Re: [PATCH] drm/radeon: fix possible division-by-zero errors
In practice this should never happen. Applied with some minor coding
style fixes.
Alex
On Fri, May 19, 2023 at 11:33 AM Nikita Zhandarovich
wrote:
>
> Function rv740_get_decoded_reference_divider() may return 0 due to
> unpredictable reference divider value calculated in
> radeon_atom_get_clock_dividers(). This will lead to
> division-by-zero error once that value is used as a divider
> in calculating 'clk_s'.
> While unlikely, this issue should nonetheless be prevented so add a
> sanity check for such cases by testing 'decoded_ref' value against 0.
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.
>
> Fixes: 66229b200598 ("drm/radeon/kms: add dpm support for rv7xx (v4)")
> Signed-off-by: Nikita Zhandarovich
>
> ---
> drivers/gpu/drm/radeon/cypress_dpm.c | 7 +--
> drivers/gpu/drm/radeon/ni_dpm.c | 7 +--
> drivers/gpu/drm/radeon/rv740_dpm.c | 7 +--
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
> b/drivers/gpu/drm/radeon/cypress_dpm.c
> index fdddbbaecbb7..3678b7e384e1 100644
> --- a/drivers/gpu/drm/radeon/cypress_dpm.c
> +++ b/drivers/gpu/drm/radeon/cypress_dpm.c
> @@ -555,10 +555,13 @@ static int cypress_populate_mclk_value(struct
> radeon_device *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, ,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = ss.percentage *
> (0x4000 * dividers.whole_fb_div + 0x800 *
> dividers.frac_fb_div) / (clk_s * 625);
>
> mpll_ss1 &= ~CLKV_MASK;
> diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
> index 672d2239293e..9ce3e5635efc 100644
> --- a/drivers/gpu/drm/radeon/ni_dpm.c
> +++ b/drivers/gpu/drm/radeon/ni_dpm.c
> @@ -2239,10 +2239,13 @@ static int ni_populate_mclk_value(struct
> radeon_device *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, ,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = ss.percentage *
> (0x4000 * dividers.whole_fb_div + 0x800 *
> dividers.frac_fb_div) / (clk_s * 625);
>
> mpll_ss1 &= ~CLKV_MASK;
> diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c
> b/drivers/gpu/drm/radeon/rv740_dpm.c
> index d57a3e1df8d6..ca76efa0f59d 100644
> --- a/drivers/gpu/drm/radeon/rv740_dpm.c
> +++ b/drivers/gpu/drm/radeon/rv740_dpm.c
> @@ -247,10 +247,13 @@ int rv740_populate_mclk_value(struct radeon_device
> *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, ,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = 0x4 * ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = 0x4 * ss.percentage *
> (dividers.whole_fb_div +
> (dividers.frac_fb_div / 8)) / (clk_s * 1);
>
> mpll_ss1 &= ~CLKV_MASK;
> --
> 2.25.1
>
Re: [PATCH v2] drm/msm/dpu: drop the regdma configuration
On 19/05/2023 20:03, Dmitry Baryshkov wrote: The regdma is currently not used by the current driver. We have no way to practically verify that the regdma is described correctly. Drop it now. Signed-off-by: Dmitry Baryshkov --- Changes since v1: - Restored dpu_msm8998_cfg.perf, incorrectly removed previously (Marijn) - Also dropped reg_dma pointer from struct dpu_kms (Marijn) Please ignore this, I forgot about https://patchwork.freedesktop.org/series/116782/ -- With best wishes Dmitry
[PATCH v4 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index f945ae3d9d06..d7d5d1dbee17 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -253,6 +253,7 @@ static const struct of_device_id
qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ }
--
2.40.1
[PATCH v4 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
From: Konrad Dybcio
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio
Acked-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index d7d5d1dbee17..e64c737724c4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -253,6 +253,7 @@ static const struct of_device_id
qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
--
2.40.1
[PATCH v4 09/12] drm/msm: mdss: Add SM6375 support
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..05648c910c68 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -580,6 +580,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = _data },
{ .compatible = "qcom,sm6115-mdss", .data = _data },
{ .compatible = "qcom,sm6350-mdss", .data = _data },
+ { .compatible = "qcom,sm6375-mdss", .data = _data },
{ .compatible = "qcom,sm8150-mdss", .data = _data },
{ .compatible = "qcom,sm8250-mdss", .data = _data },
{ .compatible = "qcom,sm8350-mdss", .data = _data },
--
2.40.1
[PATCH v4 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index ae09c627bc84..f945ae3d9d06 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,10 +251,10 @@ static const struct of_device_id
qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ }
};
--
2.40.1
[PATCH v4 07/12] drm/msm: mdss: Add SM6350 support
Add support for MDSS on SM6350.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
.highest_bank_bit = 2,
};
+static const struct msm_mdss_data sm6350_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = _data },
{ .compatible = "qcom,sc8280xp-mdss", .data = _data },
{ .compatible = "qcom,sm6115-mdss", .data = _data },
+ { .compatible = "qcom,sm6350-mdss", .data = _data },
{ .compatible = "qcom,sm8150-mdss", .data = _data },
{ .compatible = "qcom,sm8250-mdss", .data = _data },
{ .compatible = "qcom,sm8350-mdss", .data = _data },
--
2.40.1
[PATCH v4 05/12] dt-bindings: display/msm: Add SM6375 MDSS
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
1 file changed, 216 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index ..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@5e0 {
+compatible = "qcom,sm6375-mdss";
+reg = <0x05e0 0x1000>;
+reg-names = "mdss";
+
+power-domains = < MDSS_GDSC>;
+
+clocks = < GCC_DISP_AHB_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "ahb", "core";
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <_smmu 0x820 0x2>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@5e01000 {
+compatible = "qcom,sm6375-dpu";
+reg = <0x05e01000 0x8e030>,
+ <0x05eb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_ROT_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>,
+ < GCC_DISP_THROTTLE_CORE_CLK>;
+clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM6375_VDDCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+
+dsi@5e94000 {
+compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+reg = <0x05e94000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <4>;
+
+clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+ < DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ < DISP_CC_MDSS_PCLK0_CLK>,
+ < DISP_CC_MDSS_ESC0_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>;
+clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+assigned-clocks = < DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <
[PATCH v4 08/12] drm/msm/dpu: Add SM6375 support
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 156 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
new file mode 100644
index ..5085e7409ff6
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_9_SM6375_H
+#define _DPU_6_9_SM6375_H
+
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6375_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6375_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ _lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg sm6375_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ _dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6375_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x7, PINGPONG_SM8150_MASK, 0,
sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x0, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24,
INTF_SC7280_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_vbif_cfg sm6375_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x2008,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 520,
+ .max_bw_high = 620,
+ .min_core_ib = 250,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 160,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0x, 0x, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0x},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+
[PATCH v4 06/12] drm/msm/dpu: Add SM6350 support
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the fact that newer SoCs dropped the .fl (fill level)-based
logic and don't provide real values, resulting in all entries but
the last one being unused.
Signed-off-by: Konrad Dybcio
Reviewed-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 195 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index ..5d66a194155a
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ _dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x7, PINGPONG_SM8150_MASK, 0,
sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0,
sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35,
INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+
[PATCH v4 04/12] dt-bindings: display/msm: Add SM6350 MDSS
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +
1 file changed, 214 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index ..6674040d2172
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm6350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+items:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm6350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+power-domains = < MDSS_GDSC>;
+
+clocks = < GCC_DISP_AHB_CLK>,
+ < GCC_DISP_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "core";
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <_smmu 0x800 0x2>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm6350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_ROT_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus", "iface", "rot", "lut", "core",
+"vsync";
+
+assigned-clocks = < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>,
+ < DISP_CC_MDSS_ROT_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>;
+assigned-clock-rates = <3>,
+ <1920>,
+ <1920>,
+ <1920>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+operating-points-v2 = <_opp_table>;
+power-domains = < SM6350_CX>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+
+dsi@ae94000 {
+compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+reg = <0x0ae94000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <4>;
+
+clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+ < DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ < DISP_CC_MDSS_PCLK0_CLK>,
+ < DISP_CC_MDSS_ESC0_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_AXI_CLK>;
+clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+assigned-clocks = <
[PATCH v4 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375
Add the DSI host found on SM6375. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 6f367a1fabf8..f7dc05a65420 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -354,6 +355,7 @@ allOf: enum: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl then: properties: clocks: -- 2.40.1
[PATCH v4 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with the main exception being that the last one requires an additional throttle clock. It is not well understood yet, but failing to toggle it on makes the display hardware stall and not output any frames. Document SM6350 and SM6375 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 +- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 1fb8321d9ee8..630b11480496 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -13,7 +13,10 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: -const: qcom,sc7180-dpu +enum: + - qcom,sc7180-dpu + - qcom,sm6350-dpu + - qcom,sm6375-dpu reg: items: @@ -26,6 +29,7 @@ properties: - const: vbif clocks: +minItems: 6 items: - description: Display hf axi clock - description: Display ahb clock @@ -33,8 +37,10 @@ properties: - description: Display lut clock - description: Display core clock - description: Display vsync clock + - description: Display core throttle clock clock-names: +minItems: 6 items: - const: bus - const: iface @@ -42,6 +48,7 @@ properties: - const: lut - const: core - const: vsync + - const: throttle required: - compatible @@ -52,6 +59,20 @@ required: unevaluatedProperties: false +allOf: + - if: + properties: +compatible: + const: qcom,sm6375-dpu + +then: + properties: +clocks: + minItems: 7 + +clock-names: + minItems: 7 + examples: - | #include -- 2.40.1
[PATCH v4 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350
Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index e6c1ebfe8a32..6f367a1fabf8 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -285,6 +286,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: -- 2.40.1
[PATCH v4 00/12] SM63(50|75) DPU support
v3 -> v4: - Drop adding new QoS LUT entries - Add safe_lut_tbl for both SoCs Depends on: - https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/ v3: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v3-0-9837d6b35...@linaro.org v2 -> v3: - Don't duplicate qcm2290_lm_sblk - Use DEFAULT_DPU_LINE_WIDTH defines - Fix up sspp clk assignments for sm6350 - Add 6350-6375-common QoS data straight to the common file instead of moving it around after adding it - Fix up iommu compatible order before adding new entries - Reuse sm6350 msm_mdss_data for sm6375 - INTF_SC7180_MASK -> INTF_SC7280_MASK (enable HCTL) on 6375 - use double tabs in catalog headers - remove one unused entry in 6350 dpu_qos_lut_entry - add missing tear IRQs, drop INTF0 irq on 6375 - don't overduplicate DPU bindings, reuse 7180 - Pick up tags - Rebase on INTF_TE v4 and next-20230504 Depends on: - https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v4-0-27ce1a5ab...@somainline.org/ v2: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v2-0-5def73f50...@linaro.org v1 -> v2: - Rebase on the DPU catalog rework and INTF_TE - Fix QSEED(3L/4) discrepancies - Fixed DMA/cursor discrepancies for 6350 - No deduplication, that's gonna be handled in catalogrework 2: "the return of the catalogrework" - Split MDSS & DPU binding additions - Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework - Split MDSS and DPU additions - Pick up Rob's acks Depends on (and based on): https://lore.kernel.org/linux-arm-msm/20230411-dpu-intf-te-v2-0-ef76c877e...@somainline.org/T/#t v1: https://lore.kernel.org/linux-arm-msm/20230211122656.1479141-1-konrad.dyb...@linaro.org/ Signed-off-by: Konrad Dybcio --- Konrad Dybcio (12): dt-bindings: display/msm: dsi-controller-main: Add SM6350 dt-bindings: display/msm: dsi-controller-main: Add SM6375 dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 dt-bindings: display/msm: Add SM6350 MDSS dt-bindings: display/msm: Add SM6375 MDSS drm/msm/dpu: Add SM6350 support drm/msm: mdss: Add SM6350 support drm/msm/dpu: Add SM6375 support drm/msm: mdss: Add SM6375 support iommu/arm-smmu-qcom: Sort the compatible list alphabetically iommu/arm-smmu-qcom: Add SM6375 DPU compatible iommu/arm-smmu-qcom: Add SM6350 DPU compatible .../bindings/display/msm/dsi-controller-main.yaml | 4 + .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 ++ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 + drivers/gpu/drm/msm/msm_mdss.c | 10 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +- 11 files changed, 821 insertions(+), 3 deletions(-) --- base-commit: c437aff71b13c5ca77821ec1bab98ca7e18716d0 change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26 Best regards, -- Konrad Dybcio
[PATCH v5 3/3] MAINTAINERS: Add entry for Samsung S6D7AA0 LCD panel controller driver
Add myself as maintainer of the Samsung S6D7AA0 panel driver. Signed-off-by: Artur Weber --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 402e26d0cdbc..7cc2bfa4af6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6663,6 +6663,12 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6d27a1.yaml F: drivers/gpu/drm/panel/panel-samsung-s6d27a1.c +DRM DRIVER FOR SAMSUNG S6D7AA0 PANELS +M: Artur Weber +S: Maintained +F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml +F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c + DRM DRIVER FOR SITRONIX ST7703 PANELS M: Guido Günther R: Purism Kernel Team -- 2.40.1
[PATCH v5 2/3] drm/panel: Add Samsung S6D7AA0 panel controller driver
Initial driver for S6D7AA0-controlled panels. Currently, the following
panels are supported:
- S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0)
- S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015)
- S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015)
It should be possible to extend this driver to work with other panels
using this IC.
Tested-by: Nikita Travkin #ltl101at01
Signed-off-by: Artur Weber
---
Changed in v2:
- Removed unused panel_name property from desc struct
Changed in v4:
- Added LSL080AL03 and LTL101AT01 panels
- Added DSI-controlled backlight support for panels that support it
- Renamed command defines: CMD_* -> MCS_*
- Dropped s6d7aa0_bl_ctl_on (not universal across panels)
- Dropped MIPI_DSI_MODE_LPM flag
- Added vmipi-supply, renamed enable-supply to power-supply
Changed in v5:
- Changed compatible to avoid concatenating multiple model numbers
---
drivers/gpu/drm/panel/Kconfig | 7 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c | 585 ++
3 files changed, 593 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 2b9d6db7860b..203c0ef0bbfd 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -553,6 +553,13 @@ config DRM_PANEL_SAMSUNG_S6D27A1
This panel can be found in Samsung Galaxy Ace 2
GT-I8160 mobile phone.
+config DRM_PANEL_SAMSUNG_S6D7AA0
+ tristate "Samsung S6D7AA0 MIPI-DSI video mode panel controller"
+ depends on OF
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
config DRM_PANEL_SAMSUNG_S6E3HA2
tristate "Samsung S6E3HA2 DSI video mode panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index ff169781e82d..30cf553c8d1d 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) +=
panel-samsung-db7430.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
b/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
new file mode 100644
index ..f532aa018428
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung S6D7AA0 MIPI-DSI TFT LCD controller drm_panel driver.
+ *
+ * Copyright (C) 2022 Artur Weber
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* Manufacturer command set */
+#define MCS_BL_CTL 0xc3
+#define MCS_OTP_RELOAD 0xd0
+#define MCS_PASSWD10xf0
+#define MCS_PASSWD20xf1
+#define MCS_PASSWD30xfc
+
+struct s6d7aa0 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct gpio_desc *reset_gpio;
+ struct regulator_bulk_data supplies[2];
+ const struct s6d7aa0_panel_desc *desc;
+};
+
+struct s6d7aa0_panel_desc {
+ unsigned int panel_type;
+ int (*init_func)(struct s6d7aa0 *ctx);
+ int (*off_func)(struct s6d7aa0 *ctx);
+ const struct drm_display_mode drm_mode;
+ unsigned long mode_flags;
+ u32 bus_flags;
+ bool has_backlight;
+ bool use_passwd3;
+};
+
+enum s6d7aa0_panels {
+ S6D7AA0_PANEL_LSL080AL02,
+ S6D7AA0_PANEL_LSL080AL03,
+ S6D7AA0_PANEL_LTL101AT01,
+};
+
+static inline struct s6d7aa0 *panel_to_s6d7aa0(struct drm_panel *panel)
+{
+ return container_of(panel, struct s6d7aa0, panel);
+}
+
+static void s6d7aa0_reset(struct s6d7aa0 *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ msleep(50);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ msleep(50);
+}
+
+static int s6d7aa0_lock(struct s6d7aa0 *ctx, bool lock)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ int ret = 0;
+
+ if (lock) {
+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5);
+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5);
+ if (ctx->desc->use_passwd3)
+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a);
+ } else {
+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a);
+ mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a);
+ if (ctx->desc->use_passwd3)
+
[PATCH v5 1/3] dt-bindings: display: panel: Add Samsung S6D7AA0 LCD panel controller
Add bindings for the S6D7AA0 LCD panel controller, including the
S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
used in the Samsung Galaxy Tab A 8.0 and 9.7 2015.
Signed-off-by: Artur Weber
---
Changed in v2:
- Updated commit message
- Added reg to required properties
- Reordered required properties
Changed in v3:
- Fixed patch that didn't apply
Changed in v4:
- Added LSL080AL03, LTL101AT01 compatibles
- Added description to reset-gpios
- Added vmipi-supply, renamed enable-supply to power-supply
Changed in v5:
- Changed compatibles to avoid concatenating multiple model numbers
- Removed '|' from multiline descriptions
- Fixed license
---
.../display/panel/samsung,s6d7aa0.yaml| 70 +++
1 file changed, 70 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
new file mode 100644
index ..45a236d2cc70
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,s6d7aa0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S6D7AA0 MIPI-DSI LCD panel controller
+
+maintainers:
+ - Artur Weber
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ # 1280x800 LSL080AL02 panel
+ - samsung,lsl080al02
+ # 1024x768 LSL080AL03 panel
+ - samsung,lsl080al03
+ # 1024x768 LTL101AT01 panel
+ - samsung,ltl101at01
+ - const: samsung,s6d7aa0
+
+ reg: true
+
+ backlight:
+description:
+ Backlight to use for the panel. If this property is set on panels
+ that have DSI-based backlight control (LSL080AL03 and LTL101AT01),
+ it overrides the DSI-based backlight.
+
+ reset-gpios:
+description: Reset GPIO pin, usually GPIO_ACTIVE_LOW.
+
+ power-supply:
+description:
+ Main power supply for the panel; the exact voltage differs between
+ panels, and is usually somewhere around 3.3-5v.
+
+ vmipi-supply:
+description: VMIPI supply, usually 1.8v.
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+panel@0 {
+compatible = "samsung,lsl080al02", "samsung,s6d7aa0";
+reg = <0>;
+power-supply = <_3v3_supply>;
+reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+backlight = <>;
+};
+};
+
+...
--
2.40.1
[PATCH v5 0/3] Add Samsung S6D7AA0 panel controller driver
This patchset adds initial support for Samsung S6D7AA0-based panels. Currently, the following panels are supported: - S6D7AA0-LSL080AL02 (Samsung Galaxy Tab 3 8.0) - S6D7AA0-LSL080AL03 (Samsung Galaxy Tab A 8.0 2015) - S6D7AA0-LTL101AT01 (Samsung Galaxy Tab A 9.7 2015) Changed in v2: - Added commit messages for dt-bindings and MAINTAINERS entry commits - dt-bindings: Applied suggestions from Krzysztof Kozlowski - driver: Removed unused panel_name property from desc struct Changed in v3: - Correctly applied patch for dt-bindings Changed in v4: - Added support for LSL080AL03 and LTL101AT01 panels - Added DSI-controlled backlight support for panels that support it - Added vmipi-supply - Dropped s6d7aa0_bl_ctl_on function (not universal across all panels) - Removed MIPI_DSI_MODE_LPM flag Changed in v5: - Changed compatible to avoid concatenating compatibles - Removed '|' from multiline descriptions in DT schema - Fixed DT bindings license Tested-by: Nikita Travkin #ltl101at01 Signed-off-by: Artur Weber Artur Weber (3): dt-bindings: display: panel: Add Samsung S6D7AA0 LCD panel controller drm/panel: Add Samsung S6D7AA0 panel controller driver MAINTAINERS: Add entry for Samsung S6D7AA0 LCD panel controller driver .../display/panel/samsung,s6d7aa0.yaml| 71 +++ MAINTAINERS | 6 + drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c | 585 ++ 5 files changed, 670 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c base-commit: ab87f558dcfb2562c3497e89600dec798a446665 -- 2.40.1
[PATCH v2] drm/msm/dpu: drop the regdma configuration
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Restored dpu_msm8998_cfg.perf, incorrectly removed previously (Marijn)
- Also dropped reg_dma pointer from struct dpu_kms (Marijn)
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 2 -
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 2 -
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 -
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 2 -
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 2 -
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 2 -
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 -
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 2 -
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 2 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 40 ---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 18 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
14 files changed, 1 insertion(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 2b3ae84057df..02e9b26b49b0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -195,7 +195,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
.intf = msm8998_intf,
.vbif_count = ARRAY_SIZE(msm8998_vbif),
.vbif = msm8998_vbif,
- .reg_dma_count = 0,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index ceca741e93c9..63009435e258 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -193,8 +193,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
.intf = sdm845_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 282d410269ff..e17398f98734 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -220,8 +220,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
.intf = sm8150_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index c57400265f28..d32f939e9c00 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -198,8 +198,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.intf = sc8180x_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 2c40229ea515..f49fc1690b71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -228,8 +228,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
.vbif = sdm845_vbif,
.wb_count = ARRAY_SIZE(sm8250_wb),
.wb = sm8250_wb,
- .reg_dma_count = 1,
- .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 8799ed757119..0a273ba8cf4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -143,8 +143,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
.wb = sc7180_wb,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = _regdma,
.perf = _perf_data,
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
Re: [PATCH] drm/radeon: stop including swiotlb.h
Applied. Thanks! On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote: > > radeon does not need swiotlb.h, so stop including it. > > Signed-off-by: Christoph Hellwig > --- > drivers/gpu/drm/radeon/radeon_ttm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c > b/drivers/gpu/drm/radeon/radeon_ttm.c > index 2220cdf6a3f680..04df08356d553f 100644 > --- a/drivers/gpu/drm/radeon/radeon_ttm.c > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c > @@ -36,7 +36,6 @@ > #include > #include > #include > -#include > > #include > #include > -- > 2.39.2 >
Re: [PATCH] drm/amdgpu: stop including swiotlb.h
Applied. Thanks! On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote: > > amdgpu does not need swiotlb.h, so stop including it. > > Signed-off-by: Christoph Hellwig > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > index 2cd081cbf70621..385e04612e4e9b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -38,7 +38,6 @@ > #include > #include > #include > -#include > #include > #include > #include > -- > 2.39.2 >
Re: [PATCH v10 00/10] drm/hdcp: Pull HDCP auth/exchange/check into helpers
On 19/04/2023 18:43, Mark Yacoub wrote: Hi all, This is v10 of the HDCP patches. The patches are authored by Sean Paul. I rebased and addressed the review comments in v6-v10. Main change in v10 is handling the kernel test bot warnings. Patches 1-4 focus on moving the common HDCP helpers to common DRM. This introduces a slight change in the original intel flow as it splits the unique driver protocol from the generic implementation. Patches 5-7 split the HDCP flow on the i915 driver to make use of the common DRM helpers. Patches 8-10 implement HDCP on MSM driver. Thanks, -Mark Yacoub Sean Paul (10): drm/hdcp: Add drm_hdcp_atomic_check() drm/hdcp: Avoid changing crtc state in hdcp atomic check drm/hdcp: Update property value on content type and user changes drm/hdcp: Expand HDCP helper library for enable/disable/check drm/i915/hdcp: Consolidate HDCP setup/state cache drm/i915/hdcp: Retain hdcp_capable return codes drm/i915/hdcp: Use HDCP helpers for i915 dt-bindings: msm/dp: Add bindings for HDCP registers arm64: dts: qcom: sc7180: Add support for HDCP in dp-controller Dear i915 maintainers, I wanted to ping you regarding this patch series. If there are no comments for the series from you side, would it be possible to land Intel-specific and generic patches into drm-intel tree? We will continue working on the msm specific parts and merge them through the msm tree. drm/msm: Implement HDCP 1.x using the new drm HDCP helpers .../bindings/display/msm/dp-controller.yaml |7 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi |8 + drivers/gpu/drm/display/drm_hdcp_helper.c | 1224 + drivers/gpu/drm/i915/display/intel_atomic.c |8 +- drivers/gpu/drm/i915/display/intel_ddi.c | 32 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_types.h| 51 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 352 ++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 1060 +++--- drivers/gpu/drm/i915/display/intel_hdcp.h | 48 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 267 ++-- drivers/gpu/drm/msm/Kconfig |1 + drivers/gpu/drm/msm/Makefile |1 + drivers/gpu/drm/msm/dp/dp_catalog.c | 156 +++ drivers/gpu/drm/msm/dp/dp_catalog.h | 18 + drivers/gpu/drm/msm/dp/dp_debug.c | 46 +- drivers/gpu/drm/msm/dp/dp_debug.h | 11 +- drivers/gpu/drm/msm/dp/dp_display.c | 39 +- drivers/gpu/drm/msm/dp/dp_display.h |5 + drivers/gpu/drm/msm/dp/dp_drm.c | 39 +- drivers/gpu/drm/msm/dp/dp_drm.h |7 + drivers/gpu/drm/msm/dp/dp_hdcp.c | 389 ++ drivers/gpu/drm/msm/dp/dp_hdcp.h | 33 + drivers/gpu/drm/msm/dp/dp_parser.c| 14 + drivers/gpu/drm/msm/dp/dp_parser.h|4 + drivers/gpu/drm/msm/dp/dp_reg.h | 30 +- drivers/gpu/drm/msm/msm_atomic.c | 19 + include/drm/display/drm_hdcp.h| 296 include/drm/display/drm_hdcp_helper.h | 23 + 30 files changed, 2867 insertions(+), 1349 deletions(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.c create mode 100644 drivers/gpu/drm/msm/dp/dp_hdcp.h -- With best wishes Dmitry
Re: [PATCH v1 3/3] msm: skip the atomic commit of self refresh while PSR running
On 03/04/2023 19:11, Dmitry Baryshkov wrote: On Mon, 3 Apr 2023 at 15:01, Vinod Polimera wrote: On Fri, 31 Mar 2023 at 16:59, Vinod Polimera wrote: In certain CPU stress conditions, there can be a delay in scheduling commit work and it was observed that PSR commit from a different work queue was scheduled. Avoid these commits as display is already in PSR mode. Signed-off-by: Vinod Polimera --- drivers/gpu/drm/msm/msm_atomic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 645fe53..f8141bb 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -192,6 +192,9 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) new_crtc_state->mode_changed = true; state->allow_modeset = true; } + + if (old_crtc_state->self_refresh_active && new_crtc_state- self_refresh_active) + return -EINVAL; EINVAL here means that atomic_check will fail if both old and new states are in SR mode. For example, there might be a mode set for another CRTC (while keeping this one in SR mode). I don't think this is correct. We should skip/shortcut the commit, that's true. But I doubt that returning an error here is a proper way to do this. Please correct me if I'm wrong. If there is a modeset on same crtc with a different connector. The new_crtc_state will not have self_refresh_active set. Self_refresh_active is set from the helper library, which will duplicate the old_state and just adds self_refresh_active to true and active to false. so we can be confident that if we are checking for self_refresh_active status then it should be coming from the library call. Also the EINVAL is returned to the self_refresh library API and the function will be retired. Maybe I misunderstand you here. However, in this way EINVAL is returned to drm_atomic_check_only() and not to the SR code. Unless anybody objects, I'm going to drop this patch now. The issue should be solved in the framework itself. And self_refresh_active is cleared on every commit : https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/drm_atomic_state_helper.c#n158 And this means that this check will not trigger at all, if I'm not mistaken. You've added code to msm_atomic_check(), so drm_self_refresh_helper_alter_state() was not called (yet) and thus new_crtc_state->self_refresh_active is set to false, fresh after crtc's duplicate_state. -- With best wishes Dmitry -- With best wishes Dmitry
Re: [PATCH 1/2] dt-bindings: display: panel: add fannal,c3004
Hey Paulo, On Fri, May 19, 2023 at 04:24:55PM +0200, Paulo Pavacic wrote: > > Added fannal to vendor-prefixes and dt bindings for Fannal C3004. > Fannal C3004 is a 480x800 MIPI DSI Panel which requires > DCS initialization sequences with certain delays between certain > commands. > > Signed-off-by: Paulo Pavacic > --- > v3 changelog: > - renamed yml file > - refactored yml file to describe fannal,c3004 > - added matrix URI to MAINTAINERS > v2 changelog: > - revised driver title, now describes purpose > - revised description, now describes hw > - revised maintainers, now has only 1 mail > - removed diacritics from commit/commit author > - properties/compatible is now enum > - compatible using only lowercase > - revised dts example > - modified MAINTAINERS in this commit (instead of driver commit) > - dt_bindings_check checked yml > - checkpatch warning fixed > --- > .../bindings/display/panel/fannal,c3004.yaml | 75 +++ > .../devicetree/bindings/vendor-prefixes.yaml | 2 + > MAINTAINERS | 6 ++ > 3 files changed, 83 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml > > diff --git > a/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml > b/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml > new file mode 100644 > index ..a86b5ce02aa2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/panel/fannal,c3004.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/panel/fannal,c3004.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Fannal C3004 MIPI-DSI > + > +maintainers: > + - Paulo Pavacic > + > +description: | > + Fannal C3004 is a 480x800 panel which requires DSI DCS > + initialization sequences. > + > +allOf: > + - $ref: panel-common.yaml# > + > +properties: > + compatible: > +items: > + - const: fannal,c3004 > + > + reg: true Are there no restrictions on the number of reg entries? > + reset-gpios: true Can you put a blank line between properties please? > + > + vdd-supply: > +description: power supply voltage > + vddio-supply: > +description: power supply voltage for IO > + > + width-mm: > +description: physical panel width [mm] > + height-mm: > +description: physical panel height [mm] Here and for the supplies too. > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml > b/Documentation/devicetree/bindings/vendor-prefixes.yaml > index 82d39ab0231b..f962750f630a 100644 > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml > @@ -462,6 +462,8 @@ patternProperties: > description: Facebook >"^fairphone,.*": > description: Fairphone B.V. > + "^fannal,.*": > +description: Fannal Electronics Co., Ltd This needs to be split into a commit of its own. Thanks, Conor. >"^faraday,.*": > description: Faraday Technology Corporation >"^fastrax,.*": > diff --git a/MAINTAINERS b/MAINTAINERS > index 5c22c828ab46..62374c8424b9 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -6427,6 +6427,12 @@ T: git git://anongit.freedesktop.org/drm/drm-misc > F: Documentation/devicetree/bindings/display/panel/ebbg,ft8719.yaml > F: drivers/gpu/drm/panel/panel-ebbg-ft8719.c > > +DRM DRIVER FOR FANNAL C3004373132019A > +M: Paulo Pavacic > +S: Maintained > +C: matrix:r/mipi-dsi-bringup:matrix.org > +F: Documentation/devicetree/bindings/display/panel/panel-fannal,c3004.yaml > + > DRM DRIVER FOR FARADAY TVE200 TV ENCODER > M: Linus Walleij > S: Maintained > -- > 2.40.1 > signature.asc Description: PGP signature
[PATCH v2 1/2] bus: mhi: host: Add quirk framework and initial quirk
Some devices might require special handling due to flawed implementations
or other reasons. Implement a quirk framework to handle these situations.
Implement the first quirk in this framework -
MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE
The MHI spec indicates that the MHI device must initialize the
SOC_HW_VERSION register before the link to the MHI device is initialized.
The MHI host implementation uses this register as a quick check to see if
the device can be accessed early in the init process.
If an implementation is flawed, and does not properly initialize this
register, it may contain garbage data. In the case of PCIe, the value
0x has special meaning and can indicate that the link is down.
Such an implementation may cause MHI to believe the device cannot be
initialized.
Allow such controller to indicate that the host implementation should not
access this register, and handle the access accordingly during MHI init.
Change-Id: I3c8f38e1310f2065004dd6b5c2f0b9b04423205d
Signed-off-by: Jeffrey Hugo
Reviewed-by: Carl Vanderlip
Reviewed-by: Pranjal Ramajor Asha Kanojiya
---
drivers/bus/mhi/host/init.c | 13 +
include/linux/mhi.h | 18 ++
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
index f72fcb66f408..701cdf63b8da 100644
--- a/drivers/bus/mhi/host/init.c
+++ b/drivers/bus/mhi/host/init.c
@@ -891,6 +891,8 @@ static int parse_config(struct mhi_controller *mhi_cntrl,
if (config->m2_no_db)
mhi_cntrl->db_access &= ~MHI_PM_M2;
+ mhi_cntrl->quirks = config->quirks;
+
return 0;
error_ev_cfg:
@@ -982,10 +984,13 @@ int mhi_register_controller(struct mhi_controller
*mhi_cntrl,
}
/* Read the MHI device info */
- ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,
- SOC_HW_VERSION_OFFS, _info);
- if (ret)
- goto err_destroy_wq;
+ if (mhi_cntrl->quirks & MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE) {
+ soc_info = 0;
+ } else {
+ ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,
SOC_HW_VERSION_OFFS, _info);
+ if (ret)
+ goto err_destroy_wq;
+ }
mhi_cntrl->family_number = FIELD_GET(SOC_HW_VERSION_FAM_NUM_BMSK,
soc_info);
mhi_cntrl->device_number = FIELD_GET(SOC_HW_VERSION_DEV_NUM_BMSK,
soc_info);
diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index f6de4b6ecfc7..830df51528aa 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h
@@ -17,6 +17,20 @@
#define MHI_MAX_OEM_PK_HASH_SEGMENTS 16
+/*
+ * List of workarounds for devices that require behavior not specified in
+ * the standard.
+ */
+enum mhi_quirks {
+ /*
+* Some devices do not properly initialize the SOC_HW_VERSION register
+* in the BHI space. In some instances, the value is 0x which
+* may hold special meaning. In the case of such devices, do not read
+* the register.
+*/
+ MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE = BIT(0),
+};
+
struct mhi_chan;
struct mhi_event;
struct mhi_ctxt;
@@ -273,6 +287,7 @@ struct mhi_event_config {
* @event_cfg: Array of defined event rings
* @use_bounce_buf: Use a bounce buffer pool due to limited DDR access
* @m2_no_db: Host is not allowed to ring DB in M2 state
+ * @quirks: Workarounds for devices that require non-standard behavior
*/
struct mhi_controller_config {
u32 max_channels;
@@ -284,6 +299,7 @@ struct mhi_controller_config {
struct mhi_event_config *event_cfg;
bool use_bounce_buf;
bool m2_no_db;
+ u32 quirks;
};
/**
@@ -358,6 +374,7 @@ struct mhi_controller_config {
* @wake_set: Device wakeup set flag
* @irq_flags: irq flags passed to request_irq (optional)
* @mru: the default MRU for the MHI device
+ * @quirks: Workarounds for devices that require non-standard behavior
*
* Fields marked as (required) need to be populated by the controller driver
* before calling mhi_register_controller(). For the fields marked as
(optional)
@@ -452,6 +469,7 @@ struct mhi_controller {
bool wake_set;
unsigned long irq_flags;
u32 mru;
+ u32 quirks;
};
/**
--
2.40.1
[PATCH v2 2/2] accel/qaic: Add MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE
AIC100 does not initialize the SOC_HW_VERSION MHI register as expected.
Some instances of AIC100 are observed to have 0x in this register
which makes the controller think that the link is down and return an error
up to MHI. This results in a failed initialization.
Allow these cards to initialize by advertising
MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE in the MHI controller.
Change-Id: I62f31a063abf49e8f22ee2aa630d76babba83c8d
Signed-off-by: Jeffrey Hugo
Reviewed-by: Carl Vanderlip
Reviewed-by: Pranjal Ramajor Asha Kanojiya
---
drivers/accel/qaic/mhi_controller.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/accel/qaic/mhi_controller.c
b/drivers/accel/qaic/mhi_controller.c
index 5036e58e7235..2c85063d8cc6 100644
--- a/drivers/accel/qaic/mhi_controller.c
+++ b/drivers/accel/qaic/mhi_controller.c
@@ -400,6 +400,7 @@ static struct mhi_controller_config aic100_config = {
.event_cfg = aic100_events,
.use_bounce_buf = false,
.m2_no_db = false,
+ .quirks = MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE,
};
static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr,
u32 *out)
--
2.40.1
[PATCH v2 0/2] Add MHI quirk for QAIC
With the QAIC driver in -next, I'd like to suggest some MHI changes that specific to AIC100 devices, but perhaps provide a framework for other device oddities. AIC100 devices technically violate the MHI spec in two ways. Sadly, these issues comes from the device hardware, so host SW needs to work around them. Thie first issue, presented in this series, has to do with the SOC_HW_VERSION register. This register is suposed to be initialized by the hardware prior to the MHI being accessable by the host to contain a version string for the SoC of the device. This could be used by the host MHI controller software to identify and handle version to version changes. The AIC100 hardware does not initialize this register, and thus it contains garbage. This would not be much of a problem normally - the QAIC driver would just never use it. However the MHI stack uses this register as part of the init sequence and if the controller reports that the register is inaccessable then the init sequence fails. On some AIC100 cards, the garbage value ends up being 0x which is PCIe spec defined to be a special value indicating the access failed. The MHI controller cannot tell if that value is a PCIe link issue, or just garbage. QAIC needs a way to tell MHI not to use this register. Other buses have a quirk mechanism - a way to describe oddities in a particular implementation that have some kind of workaround. Since this seems to be the first need for such a thing in MHI, introduce a quirk framework. The second issue AIC100 has involves the PK Hash registers. A solution for this is expected to be proposed in the near future and is anticipated to make use of the quirk framework proposed here. With PK Hash, there are two oddities to handle. AIC100 does not initialize these registers until the SBL is running, which is later than the spec indicates, and in practice is after MHI reads/caches them. Also, AIC100 does not have enough registers defined to fully report the 5 PK Hash slots, so a custom reporting format is defined by the device. v2: -Fix build error -Fix typo in commit text Jeffrey Hugo (2): bus: mhi: host: Add quirk framework and initial quirk accel/qaic: Add MHI_QUIRK_SOC_HW_VERSION_UNRELIABLE drivers/accel/qaic/mhi_controller.c | 1 + drivers/bus/mhi/host/init.c | 13 + include/linux/mhi.h | 18 ++ 3 files changed, 28 insertions(+), 4 deletions(-) -- 2.40.1
