from:"Biju Das"

RE: [PATCH v3 4/5] drm/panfrost: devfreq: set opp to the recommended one to configure and enable regulator

2022-09-05 Thread Biju Das

Hi,

Thanks for the patch.

> Subject: [PATCH v3 4/5] drm/panfrost: devfreq: set opp to the recommended
> one to configure and enable regulator
> 
> devm_pm_opp_set_regulators() doesn't enable regulator, which make
> regulator framework switching it off during regulator_late_cleanup().

In that case, why not regulator_get()for 
Dynamic regulator(non fixed regulator)??

> 
> Call dev_pm_opp_set_opp() with the recommend OPP in
> panfrost_devfreq_init() to enable the regulator and avoid any switch off
> by regulator_late_cleanup().
> 
> Suggested-by: Viresh Kumar 
> Signed-off-by: Clément Péron 
> ---
>  drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> index 5110cd9b2425..67b242407156 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> @@ -131,6 +131,14 @@ int panfrost_devfreq_init(struct panfrost_device
> *pfdev)
>   return PTR_ERR(opp);
> 
>   panfrost_devfreq_profile.initial_freq = cur_freq;
> +
> + /* Setup and enable regulator */
> + ret = dev_pm_opp_set_opp(dev, opp);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "Couldn't set recommended OPP\n");
> + return ret;
> + }


FYI,
On RZ/G2L mali gpu, we have fixed regulator and
I was able to do GPU OPP transition without any issues previously.

root@smarc-rzg2l:~# cat /sys/class/devfreq/1184.gpu/trans_stat
 From  :   To
   :  5000  6250 1 12500 2 25000 
4 5   time(ms)
*  5000: 0 0 0 0 0 0
 0 1   144
   6250: 0 0 0 0 0 0
 0 0 0
  1: 0 0 0 0 0 0
 0 9   524
  12500: 0 0 9 0 0 0
 0 3  2544
  2: 0 0 011 0 0
 046  3304
  25000: 1 0 0 033 0
 0 0  7496
  4: 0 0 0 01619
 0 0  2024
  5: 1 0 0 1 815
35 0  4032
Total transition : 208

Cheers,
Biju

[PATCH v2 10/10] drm: rcar-du: Add rcar_du_lib_vsp_init()

2022-09-02 Thread Biju Das

RZ/G2L does not have plane registers as well as it uses different
CRTC. The below functions are SoC specific
 * rcar_du_crtc_finish_page_flip()
 * __rcar_du_plane_setup
 * __rcar_du_plane_atomic_check
All other function can be handled in common code. This patch introduces
rcar_du_lib_vsp_init() to share common_init, vsp_formats and vsp_plane_funcs().

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 157 +---
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 166 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  10 ++
 3 files changed, 178 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index fabb616d8853..d798d97b0dd4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -13,7 +13,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 #include 
@@ -85,34 +84,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-static const u32 rcar_du_vsp_formats[] = {
-   DRM_FORMAT_RGB332,
-   DRM_FORMAT_ARGB,
-   DRM_FORMAT_XRGB,
-   DRM_FORMAT_ARGB1555,
-   DRM_FORMAT_XRGB1555,
-   DRM_FORMAT_RGB565,
-   DRM_FORMAT_BGR888,
-   DRM_FORMAT_RGB888,
-   DRM_FORMAT_BGRA,
-   DRM_FORMAT_BGRX,
-   DRM_FORMAT_ARGB,
-   DRM_FORMAT_XRGB,
-   DRM_FORMAT_UYVY,
-   DRM_FORMAT_YUYV,
-   DRM_FORMAT_YVYU,
-   DRM_FORMAT_NV12,
-   DRM_FORMAT_NV21,
-   DRM_FORMAT_NV16,
-   DRM_FORMAT_NV61,
-   DRM_FORMAT_YUV420,
-   DRM_FORMAT_YVU420,
-   DRM_FORMAT_YUV422,
-   DRM_FORMAT_YVU422,
-   DRM_FORMAT_YUV444,
-   DRM_FORMAT_YVU444,
-};
-
 static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
 {
struct rcar_du_vsp_plane_state *state =
@@ -234,133 +205,9 @@ static const struct drm_plane_helper_funcs 
rcar_du_vsp_plane_helper_funcs = {
.atomic_update = rcar_du_vsp_plane_atomic_update,
 };
 
-static struct drm_plane_state *
-rcar_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane)
-{
-   struct rcar_du_vsp_plane_state *copy;
-
-   if (WARN_ON(!plane->state))
-   return NULL;
-
-   copy = kzalloc(sizeof(*copy), GFP_KERNEL);
-   if (copy == NULL)
-   return NULL;
-
-   __drm_atomic_helper_plane_duplicate_state(plane, >state);
-
-   return >state;
-}
-
-static void rcar_du_vsp_plane_atomic_destroy_state(struct drm_plane *plane,
-  struct drm_plane_state 
*state)
-{
-   __drm_atomic_helper_plane_destroy_state(state);
-   kfree(to_rcar_vsp_plane_state(state));
-}
-
-static void rcar_du_vsp_plane_reset(struct drm_plane *plane)
-{
-   struct rcar_du_vsp_plane_state *state;
-
-   if (plane->state) {
-   rcar_du_vsp_plane_atomic_destroy_state(plane, plane->state);
-   plane->state = NULL;
-   }
-
-   state = kzalloc(sizeof(*state), GFP_KERNEL);
-   if (state == NULL)
-   return;
-
-   __drm_atomic_helper_plane_reset(plane, >state);
-}
-
-static const struct drm_plane_funcs rcar_du_vsp_plane_funcs = {
-   .update_plane = drm_atomic_helper_update_plane,
-   .disable_plane = drm_atomic_helper_disable_plane,
-   .reset = rcar_du_vsp_plane_reset,
-   .destroy = drm_plane_cleanup,
-   .atomic_duplicate_state = rcar_du_vsp_plane_atomic_duplicate_state,
-   .atomic_destroy_state = rcar_du_vsp_plane_atomic_destroy_state,
-};
-
-static void rcar_du_vsp_cleanup(struct drm_device *dev, void *res)
-{
-   struct rcar_du_vsp *vsp = res;
-   unsigned int i;
-
-   for (i = 0; i < vsp->num_planes; ++i) {
-   struct rcar_du_vsp_plane *plane = >planes[i];
-
-   drm_plane_cleanup(>plane);
-   }
-
-   kfree(vsp->planes);
-
-   put_device(vsp->vsp);
-}
-
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs)
 {
-   struct rcar_du_device *rcdu = vsp->dev;
-   struct platform_device *pdev;
-   unsigned int num_crtcs = hweight32(crtcs);
-   unsigned int num_planes;
-   unsigned int i;
-   int ret;
-
-   /* Find the VSP device and initialize it. */
-   pdev = of_find_device_by_node(np);
-   if (!pdev)
-   return -ENXIO;
-
-   vsp->vsp = >dev;
-
-   ret = drmm_add_action_or_reset(>ddev, rcar_du_vsp_cleanup, vsp);
-   if (ret < 0)
-   return ret;
-
-   ret = vsp1_du_init(vsp->vsp);
-   if (ret < 0)
-   return ret;
-
-   num_planes = rcdu->info->num_rpf;
-
-   vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
-   if (!vs

[PATCH v2 09/10] drm: rcar-du: Move rcar_du_gem_prime_import_sg_table()

2022-09-02 Thread Biju Das

Move rcar_du_gem_prime_import_sg_table() to RCar DU KMS lib.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 47 ---
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  8 
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 46 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  7 
 4 files changed, 53 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 4b5511a20313..ae969f640bb6 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -11,8 +11,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -36,51 +34,6 @@
  * Frame buffer
  */
 
-static const struct drm_gem_object_funcs rcar_du_gem_funcs = {
-   .free = drm_gem_dma_object_free,
-   .print_info = drm_gem_dma_object_print_info,
-   .get_sg_table = drm_gem_dma_object_get_sg_table,
-   .vmap = drm_gem_dma_object_vmap,
-   .mmap = drm_gem_dma_object_mmap,
-   .vm_ops = _gem_dma_vm_ops,
-};
-
-struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
-   struct dma_buf_attachment *attach,
-   struct sg_table *sgt)
-{
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   struct drm_gem_dma_object *dma_obj;
-   struct drm_gem_object *gem_obj;
-   int ret;
-
-   if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
-   return drm_gem_dma_prime_import_sg_table(dev, attach, sgt);
-
-   /* Create a DMA GEM buffer. */
-   dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL);
-   if (!dma_obj)
-   return ERR_PTR(-ENOMEM);
-
-   gem_obj = _obj->base;
-   gem_obj->funcs = _du_gem_funcs;
-
-   drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
-   dma_obj->map_noncoherent = false;
-
-   ret = drm_gem_create_mmap_offset(gem_obj);
-   if (ret) {
-   drm_gem_object_release(gem_obj);
-   kfree(dma_obj);
-   return ERR_PTR(ret);
-   }
-
-   dma_obj->dma_addr = 0;
-   dma_obj->sgt = sgt;
-
-   return gem_obj;
-}
-
 static struct drm_framebuffer *
 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
  const struct drm_mode_fb_cmd2 *mode_cmd)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
index 821eac74077f..b47a9e464ef4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
@@ -12,16 +12,8 @@
 
 #include "rcar_du_kms_lib.h"
 
-struct dma_buf_attachment;
-struct drm_device;
-struct drm_gem_object;
 struct rcar_du_device;
-struct sg_table;
 
 int rcar_du_modeset_init(struct rcar_du_device *rcdu);
 
-struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
-   struct dma_buf_attachment *attach,
-   struct sg_table *sgt);
-
 #endif /* __RCAR_DU_KMS_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index 0a2b1c6c1ea6..6b912fed8a8b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -311,6 +312,51 @@ const struct rcar_du_format_info *rcar_du_format_info(u32 
fourcc)
  * Frame buffer
  */
 
+static const struct drm_gem_object_funcs rcar_du_gem_funcs = {
+   .free = drm_gem_dma_object_free,
+   .print_info = drm_gem_dma_object_print_info,
+   .get_sg_table = drm_gem_dma_object_get_sg_table,
+   .vmap = drm_gem_dma_object_vmap,
+   .mmap = drm_gem_dma_object_mmap,
+   .vm_ops = _gem_dma_vm_ops,
+};
+
+struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
+   struct dma_buf_attachment *attach,
+   struct sg_table *sgt)
+{
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   struct drm_gem_dma_object *dma_obj;
+   struct drm_gem_object *gem_obj;
+   int ret;
+
+   if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
+   return drm_gem_dma_prime_import_sg_table(dev, attach, sgt);
+
+   /* Create a DMA GEM buffer. */
+   dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL);
+   if (!dma_obj)
+   return ERR_PTR(-ENOMEM);
+
+   gem_obj = _obj->base;
+   gem_obj->funcs = _du_gem_funcs;
+
+   drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
+   dma_obj->map_noncoherent = false;
+
+   ret = drm_gem_create_mmap_offset(gem_obj);
+   if (ret) {
+   drm_gem_object_release(gem_obj);
+   kfree(dma_obj);
+

[PATCH v2 08/10] drm: rcar-du: Move rcar_du_dumb_create()

2022-09-02 Thread Biju Das

Move rcar_du_dumb_create() to RCar DU KMS lib.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 21 -
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  5 
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 28 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  7 ++
 4 files changed, 35 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 3141d447e979..4b5511a20313 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -81,27 +81,6 @@ struct drm_gem_object 
*rcar_du_gem_prime_import_sg_table(struct drm_device *dev,
return gem_obj;
 }
 
-int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
-   struct drm_mode_create_dumb *args)
-{
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-   unsigned int align;
-
-   /*
-* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
-* but the R8A7790 DU seems to require a 128 bytes pitch alignment.
-*/
-   if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
-   align = 128;
-   else
-   align = 16 * args->bpp / 8;
-
-   args->pitch = roundup(min_pitch, align);
-
-   return drm_gem_dma_dumb_create_internal(file, dev, args);
-}
-
 static struct drm_framebuffer *
 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
  const struct drm_mode_fb_cmd2 *mode_cmd)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
index 2d4b8e608989..821eac74077f 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
@@ -13,18 +13,13 @@
 #include "rcar_du_kms_lib.h"
 
 struct dma_buf_attachment;
-struct drm_file;
 struct drm_device;
 struct drm_gem_object;
-struct drm_mode_create_dumb;
 struct rcar_du_device;
 struct sg_table;
 
 int rcar_du_modeset_init(struct rcar_du_device *rcdu);
 
-int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
-   struct drm_mode_create_dumb *args);
-
 struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
struct dma_buf_attachment *attach,
struct sg_table *sgt);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index 97c526dae521..0a2b1c6c1ea6 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -7,10 +7,13 @@
  * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
  */
 
+#include 
 #include 
+#include 
 
 #include 
 
+#include "rcar_du_drv.h"
 #include "rcar_du_kms.h"
 #include "rcar_du_regs.h"
 
@@ -303,3 +306,28 @@ const struct rcar_du_format_info *rcar_du_format_info(u32 
fourcc)
 
return NULL;
 }
+
+/* 
-
+ * Frame buffer
+ */
+
+int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
+   struct drm_mode_create_dumb *args)
+{
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+   unsigned int align;
+
+   /*
+* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
+* but the R8A7790 DU seems to require a 128 bytes pitch alignment.
+*/
+   if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
+   align = 128;
+   else
+   align = 16 * args->bpp / 8;
+
+   args->pitch = roundup(min_pitch, align);
+
+   return drm_gem_dma_dumb_create_internal(file, dev, args);
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
index 674a38d24917..33f96e96f6a2 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
@@ -12,6 +12,10 @@
 
 #include 
 
+struct drm_device;
+struct drm_file;
+struct drm_mode_create_dumb;
+
 struct rcar_du_format_info {
u32 fourcc;
u32 v4l2;
@@ -24,4 +28,7 @@ struct rcar_du_format_info {
 
 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc);
 
+int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
+   struct drm_mode_create_dumb *args);
+
 #endif /* __RCAR_DU_KMS_LIB_H__ */
-- 
2.25.1

[PATCH v2 07/10] drm: rcar-du: Move vsp rcar_du_vsp_{map,unmap}_fb()

2022-09-02 Thread Biju Das

Move vsp rcar_du_vsp_{map,unmap}_fb() to RCar DU VSP lib.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 78 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 18 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 84 +++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 19 +
 4 files changed, 103 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index 870b72eda4da..fabb616d8853 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -11,11 +11,8 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
@@ -171,68 +168,6 @@ static void rcar_du_vsp_plane_setup(struct 
rcar_du_vsp_plane *plane)
  plane->index, );
 }
 
-int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
-  struct sg_table sg_tables[3])
-{
-   struct rcar_du_device *rcdu = vsp->dev;
-   unsigned int i, j;
-   int ret;
-
-   for (i = 0; i < fb->format->num_planes; ++i) {
-   struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);
-   struct sg_table *sgt = _tables[i];
-
-   if (gem->sgt) {
-   struct scatterlist *src;
-   struct scatterlist *dst;
-
-   /*
-* If the GEM buffer has a scatter gather table, it has
-* been imported from a dma-buf and has no physical
-* address as it might not be physically contiguous.
-* Copy the original scatter gather table to map it to
-* the VSP.
-*/
-   ret = sg_alloc_table(sgt, gem->sgt->orig_nents,
-GFP_KERNEL);
-   if (ret)
-   goto fail;
-
-   src = gem->sgt->sgl;
-   dst = sgt->sgl;
-   for (j = 0; j < gem->sgt->orig_nents; ++j) {
-   sg_set_page(dst, sg_page(src), src->length,
-   src->offset);
-   src = sg_next(src);
-   dst = sg_next(dst);
-   }
-   } else {
-   ret = dma_get_sgtable(rcdu->dev, sgt, gem->vaddr,
- gem->dma_addr, gem->base.size);
-   if (ret)
-   goto fail;
-   }
-
-   ret = vsp1_du_map_sg(vsp->vsp, sgt);
-   if (ret) {
-   sg_free_table(sgt);
-   goto fail;
-   }
-   }
-
-   return 0;
-
-fail:
-   while (i--) {
-   struct sg_table *sgt = _tables[i];
-
-   vsp1_du_unmap_sg(vsp->vsp, sgt);
-   sg_free_table(sgt);
-   }
-
-   return ret;
-}
-
 static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
struct drm_plane_state *state)
 {
@@ -254,19 +189,6 @@ static int rcar_du_vsp_plane_prepare_fb(struct drm_plane 
*plane,
return drm_gem_plane_helper_prepare_fb(plane, state);
 }
 
-void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
- struct sg_table sg_tables[3])
-{
-   unsigned int i;
-
-   for (i = 0; i < fb->format->num_planes; ++i) {
-   struct sg_table *sgt = _tables[i];
-
-   vsp1_du_unmap_sg(vsp->vsp, sgt);
-   sg_free_table(sgt);
-   }
-}
-
 static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
 struct drm_plane_state *state)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index b610e6b40304..4022ed014353 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -14,10 +14,7 @@
 
 #include "rcar_du_vsp_lib.h"
 
-struct drm_framebuffer;
 struct rcar_du_format_info;
-struct rcar_du_vsp;
-struct sg_table;
 
 struct rcar_du_vsp_plane {
struct drm_plane plane;
@@ -61,10 +58,6 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
-  struct sg_table sg_tables[3]);
-void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
-

[PATCH v2 06/10] drm: rcar-du: Move rcar_du_vsp_atomic_flush()

2022-09-02 Thread Biju Das

Move rcar_du_vsp_atomic_flush() to RCar DU vsp lib.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 13 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h |  2 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 14 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  2 ++
 4 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index 685e3e8f6ddb..870b72eda4da 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -88,19 +88,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
-{
-   struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
-   struct rcar_du_crtc_state *state;
-
-   state = to_rcar_crtc_state(crtc->crtc.state);
-   cfg.crc = state->crc;
-
-   rcar_du_writeback_setup(crtc, );
-
-   vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, );
-}
-
 static const u32 rcar_du_vsp_formats[] = {
DRM_FORMAT_RGB332,
DRM_FORMAT_ARGB,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 83a2f3e85860..b610e6b40304 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -61,7 +61,6 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
   struct sg_table sg_tables[3]);
 void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
@@ -74,7 +73,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
 struct drm_framebuffer *fb,
 struct sg_table sg_tables[3])
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index f6c0cae7c4af..89169dc7594a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -10,6 +10,7 @@
 #include 
 
 #include "rcar_du_drv.h"
+#include "rcar_du_writeback.h"
 
 void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
 {
@@ -20,3 +21,16 @@ void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
 {
vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
 }
+
+void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
+{
+   struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
+   struct rcar_du_crtc_state *state;
+
+   state = to_rcar_crtc_state(crtc->crtc.state);
+   cfg.crc = state->crc;
+
+   rcar_du_writeback_setup(crtc, );
+
+   vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, );
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index 8c22042d4a80..e8f16236be0a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -13,9 +13,11 @@
 #ifdef CONFIG_DRM_RCAR_VSP
 void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
+void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
+static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH v2 05/10] drm: rcar-du: Move rcar_du_vsp_atomic_begin()

2022-09-02 Thread Biju Das

Move rcar_du_vsp_atomic_begin() to RCar DU VSP lib.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 5 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 2 ++
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index bed3f2a3c4a5..685e3e8f6ddb 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -88,11 +88,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
-{
-   vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
-}
-
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
 {
struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 8fbfa86c93e0..83a2f3e85860 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -61,7 +61,6 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
   struct sg_table sg_tables[3]);
@@ -75,7 +74,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
 struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index e22d4e535268..f6c0cae7c4af 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -15,3 +15,8 @@ void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
 {
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL);
 }
+
+void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
+{
+   vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index d91c043bbced..8c22042d4a80 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -12,8 +12,10 @@
 
 #ifdef CONFIG_DRM_RCAR_VSP
 void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
+void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
+static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH v2 04/10] drm: rcar-du: Add vsp lib support

2022-09-02 Thread Biju Das

Add RCar DU vsp lib support by moving rcar_du_vsp_disable()
to the lib file so that same function can be used by both
RCar and RZ/G2L DU VSP drivers.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/Kconfig   |  5 +
 drivers/gpu/drm/rcar-du/Makefile  |  1 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  5 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h |  4 ++--
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 17 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 19 +++
 6 files changed, 44 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 369af45b5ff9..64d47d9f9131 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -76,3 +76,8 @@ config DRM_RCAR_LIB
bool
default y
depends on DRM_RCAR_DU
+
+config DRM_RCAR_VSP_LIB
+   bool
+   default y
+   depends on DRM_RCAR_VSP
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 3ce410300334..8fc924cf37a7 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -10,6 +10,7 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o \
  rcar_du_kms_lib.o
 
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
+rcar-du-drm-$(CONFIG_DRM_RCAR_VSP_LIB) += rcar_du_vsp_lib.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
 obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index e465aef41585..bed3f2a3c4a5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -88,11 +88,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
-{
-   vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL);
-}
-
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
 {
vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 67630f0b6599..8fbfa86c93e0 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -12,6 +12,8 @@
 
 #include 
 
+#include "rcar_du_vsp_lib.h"
+
 struct drm_framebuffer;
 struct rcar_du_format_info;
 struct rcar_du_vsp;
@@ -59,7 +61,6 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
@@ -74,7 +75,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
new file mode 100644
index ..e22d4e535268
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * R-Car Display Unit VSP-Based Compositor Lib
+ *
+ * Copyright (C) 2015-2022 Renesas Electronics Corporation
+ *
+ * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
+ */
+
+#include 
+
+#include "rcar_du_drv.h"
+
+void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
+{
+   vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL);
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
new file mode 100644
index ..d91c043bbced
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * R-Car Display Unit VSP-Based Compositor Lib
+ *
+ * Copyright (C) 2015-2022 Renesas Electronics Corporation
+ *
+ * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
+ */
+
+#ifndef __RCAR_DU_VSP_LIB_H__
+#define __RCAR_DU_VSP_LIB_H__
+
+#ifdef CONFIG_DRM_RCAR_VSP
+void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
+#else
+static inline void rcar_du_vsp_disable(struct rcar_du_

[PATCH v2 03/10] drm: rcar-du: Add kms lib support

2022-09-02 Thread Biju Das

Add RCar DU kms lib support by moving rcar_du_format_infos table and
rcar_du_format_infos() to the lib file to share the common code between
RCar and RZ/G2L DU KMS drivers.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/Makefile  |   3 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 290 
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  16 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 305 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  27 ++
 5 files changed, 336 insertions(+), 305 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 479c8eebba5a..3ce410300334 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,7 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
-rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o
+rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o \
+ rcar_du_kms_lib.o
 
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 8c2719efda2a..3141d447e979 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -32,296 +32,6 @@
 #include "rcar_du_vsp.h"
 #include "rcar_du_writeback.h"
 
-/* 
-
- * Format helpers
- */
-
-static const struct rcar_du_format_info rcar_du_format_infos[] = {
-   {
-   .fourcc = DRM_FORMAT_RGB565,
-   .v4l2 = V4L2_PIX_FMT_RGB565,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_ARGB1555,
-   .v4l2 = V4L2_PIX_FMT_ARGB555,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_XRGB1555,
-   .v4l2 = V4L2_PIX_FMT_XRGB555,
-   .bpp = 16,
-   .planes = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_XRGB,
-   .v4l2 = V4L2_PIX_FMT_XBGR32,
-   .bpp = 32,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_RGB888,
-   }, {
-   .fourcc = DRM_FORMAT_ARGB,
-   .v4l2 = V4L2_PIX_FMT_ABGR32,
-   .bpp = 32,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_ARGB,
-   }, {
-   .fourcc = DRM_FORMAT_UYVY,
-   .v4l2 = V4L2_PIX_FMT_UYVY,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_YUYV,
-   .v4l2 = V4L2_PIX_FMT_YUYV,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV12,
-   .v4l2 = V4L2_PIX_FMT_NV12M,
-   .bpp = 12,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV21,
-   .v4l2 = V4L2_PIX_FMT_NV21M,
-   .bpp = 12,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV16,
-   .v4l2 = V4L2_PIX_FMT_NV16M,
-   .bpp = 16,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   },
-   /*
-* The following formats are not supported on Gen2 and thus have no
-* associated .pnmr or .edf settings.
-*/
-   {
-   .fourcc = DRM_FORMAT_RGB332,
-   .v4l2 = V4L2_PIX_FMT_RGB332,
-   .bpp = 8,
-   .planes = 1,
-

[PATCH v2 02/10] drm: rcar-du: Add encoder lib support

2022-09-02 Thread Biju Das

Add RCar DU encoder lib support by moving rcar_du_encoder_count_ports()
and rcar_du_encoder_funcs to the lib file and added
rcar_du_encoder_funcs() to share the common code between RCar and
RZ/G2L DU encoder drivers.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
 * Fixed the warning reported by bot.
---
 drivers/gpu/drm/rcar-du/Kconfig   |   5 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 117 +--
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  14 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c | 138 ++
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h |  30 
 6 files changed, 180 insertions(+), 126 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 58ffb8c2443b..369af45b5ff9 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -71,3 +71,8 @@ config DRM_RCAR_WRITEBACK
bool
default y if ARM64
depends on DRM_RCAR_DU
+
+config DRM_RCAR_LIB
+   bool
+   default y
+   depends on DRM_RCAR_DU
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index b8f2c82651d9..479c8eebba5a 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,6 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
+rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c 
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index b1787be31e92..444cc956f692 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -2,7 +2,7 @@
 /*
  * R-Car Display Unit Encoder
  *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2022 Renesas Electronics Corporation
  *
  * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
  */
@@ -10,128 +10,17 @@
 #include 
 #include 
 
-#include 
-#include 
-#include 
-
 #include "rcar_du_drv.h"
 #include "rcar_du_encoder.h"
-#include "rcar_lvds.h"
 
 /* 
-
  * Encoder
  */
 
-static unsigned int rcar_du_encoder_count_ports(struct device_node *node)
-{
-   struct device_node *ports;
-   struct device_node *port;
-   unsigned int num_ports = 0;
-
-   ports = of_get_child_by_name(node, "ports");
-   if (!ports)
-   ports = of_node_get(node);
-
-   for_each_child_of_node(ports, port) {
-   if (of_node_name_eq(port, "port"))
-   num_ports++;
-   }
-
-   of_node_put(ports);
-
-   return num_ports;
-}
-
-static const struct drm_encoder_funcs rcar_du_encoder_funcs = {
-};
-
 int rcar_du_encoder_init(struct rcar_du_device *rcdu,
 enum rcar_du_output output,
 struct device_node *enc_node)
 {
-   struct rcar_du_encoder *renc;
-   struct drm_connector *connector;
-   struct drm_bridge *bridge;
-   int ret;
-
-   /*
-* Locate the DRM bridge from the DT node. For the DPAD outputs, if the
-* DT node has a single port, assume that it describes a panel and
-* create a panel bridge.
-*/
-   if ((output == RCAR_DU_OUTPUT_DPAD0 ||
-output == RCAR_DU_OUTPUT_DPAD1) &&
-   rcar_du_encoder_count_ports(enc_node) == 1) {
-   struct drm_panel *panel = of_drm_find_panel(enc_node);
-
-   if (IS_ERR(panel))
-   return PTR_ERR(panel);
-
-   bridge = devm_drm_panel_bridge_add_typed(rcdu->dev, panel,
-
DRM_MODE_CONNECTOR_DPI);
-   if (IS_ERR(bridge))
-   return PTR_ERR(bridge);
-   } else {
-   bridge = of_drm_find_bridge(enc_node);
-   if (!bridge)
-   return -EPROBE_DEFER;
-
-   if (output == RCAR_DU_OUTPUT_LVDS0 ||
-   output == RCAR_DU_OUTPUT_LVDS1)
-   rcdu->lvds[output - RCAR_DU_OUTPUT_LVDS0] = bridge;
-
-   if (output == RCAR_DU_OUTPUT_DSI0 ||
-   output == RCAR_DU_OUTPUT_DSI1)
-   rcdu->dsi[output - RCAR_DU_OUTPUT_DSI0] = bridge;
-   }
-
-   /*
-* Create and initialize the encoder. On Gen3, skip the LVDS1 output if
-* the LVDS1 encoder is used as a companion for LVDS0 in dual-link
-* mode, or any LVDS output if it isn't connec

[PATCH v2 01/10] drm: rcar-du: Add RZ/G2L reset and clocks to struct rcar_du_crtc

2022-09-02 Thread Biju Das

Add RZ/G2L reset and clocks to struct rcar_du_crtc, so that
we can share and optimize the common code between RCar and
RZ/G2L driver using RCar DU library.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rebased on drm-misc-next and DU-next.
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h 
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index d0f38a8b3561..d2164ee6e599 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
@@ -43,6 +43,8 @@ struct rcar_du_vsp;
  * @vsp: VSP feeding video to this CRTC
  * @vsp_pipe: index of the VSP pipeline feeding video to this CRTC
  * @writeback: the writeback connector
+ * @rzg2l_clocks: the bus, main and video clock
+ * @rstc: reset controller
  */
 struct rcar_du_crtc {
struct drm_crtc crtc;
@@ -73,6 +75,14 @@ struct rcar_du_crtc {
unsigned int sources_count;
 
struct drm_writeback_connector writeback;
+
+   /* RZ/G2L specific */
+   struct reset_control *rstc;
+   struct {
+   struct clk *aclk;
+   struct clk *pclk;
+   struct clk *dclk;
+   } rzg2l_clocks;
 };
 
 #define to_rcar_crtc(c)container_of(c, struct rcar_du_crtc, 
crtc)
-- 
2.25.1

[PATCH v2 00/10] Add RCar DU lib support

2022-09-02 Thread Biju Das

Both RZ/G2L and RCar display system uses similar hardware pipeline for
display ie, it uses FCPV, VSPD and DU. Both FCPV and VSPD are almost
similar, but DU there are some differences like it does not have
plane/group registers.

Since the pipeline and software architecture are similar, we can reuse the
DU code for RCar to RZ/G2L as well.

This patch series adds RCar DU lib support(Encoder, vsp and KMS) by moving
common codes with some trivial changes to the lib.

The subsequent patch series will add support for RZ/G2L DU.

Note:
 * This patch series is based on drm-misc-next and du-next
 * The KConfig and Make file depend upon [1]
[1] 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220829091901.641784-3-biju.das...@bp.renesas.com/

v1->v2:
 * Rebased on drm-misc-next and DU-next.
 * Fixed the warning reported by bot for patch#2.

Biju Das (10):
  drm: rcar-du: Add RZ/G2L reset and clocks to struct rcar_du_crtc
  drm: rcar-du: Add encoder lib support
  drm: rcar-du: Add kms lib support
  drm: rcar-du: Add vsp lib support
  drm: rcar-du: Move rcar_du_vsp_atomic_begin()
  drm: rcar-du: Move rcar_du_vsp_atomic_flush()
  drm: rcar-du: Move vsp rcar_du_vsp_{map,unmap}_fb()
  drm: rcar-du: Move rcar_du_dumb_create()
  drm: rcar-du: Move rcar_du_gem_prime_import_sg_table()
  drm: rcar-du: Add rcar_du_lib_vsp_init()

 drivers/gpu/drm/rcar-du/Kconfig   |  10 +
 drivers/gpu/drm/rcar-du/Makefile  |   4 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h|  10 +
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 117 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  14 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c | 138 +++
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h |  30 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 358 -
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  29 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 379 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  41 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 258 +---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h |  26 +-
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 286 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  52 +++
 15 files changed, 961 insertions(+), 791 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h

-- 
2.25.1

RE: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-30 Thread Biju Das

Hi Laurent and all,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> On Tue, Aug 30, 2022 at 08:22:08AM +, Biju Das wrote:
> > Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> > > On Mon, Aug 29, 2022 at 10:19:01AM +0100, Biju Das wrote:
> > > > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC.
> > > > It currently supports DSI video mode only.
> > > >
> > > > Signed-off-by: Biju Das 
> > > > Acked-by: Sam Ravnborg 
> > > > ---
> > > > v5->v6:
> > > >  * Updated commit description
> > > >  * Moved handling of arst and prst from rzg2l_mipi_dsi_startup-
> > > >runtime
> > > >PM suspend/resume handlers.
> > > >  * Max lane capability read at probe(), and enforced in
> > > >rzg2l_mipi_dsi_host_attach()
> > > >  * Simplified vich1ppsetr setting.
> > > >  * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
> > > >  * Fixed typo in probe error message(arst->rst).
> > > >  * Reordered DRM bridge initaization in probe()
> > > >  * Updated typo in e-mail address.
> > > > v4->v5:
> > > >  * Added Ack from Sam.
> > > >  * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
> > > >with drm_of_get_data_lanes_count_ep() in probe.
> > > > v3->v4:
> > > >  * Updated error handling in rzg2l_mipi_dsi_startup() and
> > > > rzg2l_mipi_dsi_atomic_enable()
> > > > v2->v3:
> > > >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr
> > > > function
> > > instead
> > > >of the memory pointer
> > > >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> > > >  * Removed unnecessary dbg message from
> > > > rzg2l_mipi_dsi_start_video()
> > > >  * DRM bridge parameter initialization moved to probe
> > > >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> > > >  * Inserted the missing blank lane after return in probe()
> > > >  * Added missing MODULE_DEVICE_TABLE
> > > >  * Added include linux/bits.h in header file
> > > >  * Fixed various macros in header file.
> > > >  * Reorder the make file for DSI, so that it is no more dependent
> > > >on RZ/G2L DU patch series.
> > > > v1->v2:
> > > >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> > > >  * Replaced link_mmio and phy_mmio with mmio in struct
> > > > rzg2l_mipi_dsi
> > > >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> > > >and rzg2l_mipi_dsi_link_write
> > > >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > > > RFC->v1:
> > > >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> > > >and dropped DRM as it is implied by DRM_BRIDGE
> > > >  * Used devm_reset_control_get_exclusive() for reset handle
> > > >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> > > >  * Added error check for pm, using pm_runtime_resume_and_get()
> > > > instead
> > > of
> > > >pm_runtime_get_sync()
> > > >  * Added check for unsupported formats in
> > > > rzg2l_mipi_dsi_host_attach()
> > > >  * Avoided read-modify-write stopping hsclock
> > > >  * Used devm_platform_ioremap_resource for resource allocation
> > > >  * Removed unnecessary assert call from probe and remove.
> > > >  * wrap the line after the PTR_ERR() in probe()
> > > >  * Updated reset failure messages in probe
> > > >  * Fixed the typo arstc->prstc
> > > >  * Made hex constants to lower case.
> > > > RFC:
> > > >  *
> > > > ---
> > > >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> > > >  drivers/gpu/drm/rcar-du/Makefile  |   2 +
> > > >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 703
> > > ++
> > > >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
> > > >  4 files changed, 864 insertions(+)  create mode 100644
> > > > drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> > > >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> > > >
> > > > diff --git a/drivers/gpu/drm/rcar-du/Kconfig
> > > > b/drivers/gpu/drm/rcar-du/Kconfig index c959e8c6b

RE: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-30 Thread Biju Das

Hi Laurent,

> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> On Tue, Aug 30, 2022 at 08:22:08AM +, Biju Das wrote:
> > Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> > > On Mon, Aug 29, 2022 at 10:19:01AM +0100, Biju Das wrote:
> > > > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC.
> > > > It currently supports DSI video mode only.
> > > >
> > > > Signed-off-by: Biju Das 
> > > > Acked-by: Sam Ravnborg 
> > > > ---
> > > > v5->v6:
> > > >  * Updated commit description
> > > >  * Moved handling of arst and prst from rzg2l_mipi_dsi_startup-
> > > >runtime
> > > >PM suspend/resume handlers.
> > > >  * Max lane capability read at probe(), and enforced in
> > > >rzg2l_mipi_dsi_host_attach()
> > > >  * Simplified vich1ppsetr setting.
> > > >  * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
> > > >  * Fixed typo in probe error message(arst->rst).
> > > >  * Reordered DRM bridge initaization in probe()
> > > >  * Updated typo in e-mail address.
> > > > v4->v5:
> > > >  * Added Ack from Sam.
> > > >  * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
> > > >with drm_of_get_data_lanes_count_ep() in probe.
> > > > v3->v4:
> > > >  * Updated error handling in rzg2l_mipi_dsi_startup() and
> > > > rzg2l_mipi_dsi_atomic_enable()
> > > > v2->v3:
> > > >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr
> > > > function
> > > instead
> > > >of the memory pointer
> > > >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> > > >  * Removed unnecessary dbg message from
> > > > rzg2l_mipi_dsi_start_video()
> > > >  * DRM bridge parameter initialization moved to probe
> > > >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> > > >  * Inserted the missing blank lane after return in probe()
> > > >  * Added missing MODULE_DEVICE_TABLE
> > > >  * Added include linux/bits.h in header file
> > > >  * Fixed various macros in header file.
> > > >  * Reorder the make file for DSI, so that it is no more dependent
> > > >on RZ/G2L DU patch series.
> > > > v1->v2:
> > > >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> > > >  * Replaced link_mmio and phy_mmio with mmio in struct
> > > > rzg2l_mipi_dsi
> > > >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> > > >and rzg2l_mipi_dsi_link_write
> > > >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > > > RFC->v1:
> > > >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> > > >and dropped DRM as it is implied by DRM_BRIDGE
> > > >  * Used devm_reset_control_get_exclusive() for reset handle
> > > >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> > > >  * Added error check for pm, using pm_runtime_resume_and_get()
> > > > instead
> > > of
> > > >pm_runtime_get_sync()
> > > >  * Added check for unsupported formats in
> > > > rzg2l_mipi_dsi_host_attach()
> > > >  * Avoided read-modify-write stopping hsclock
> > > >  * Used devm_platform_ioremap_resource for resource allocation
> > > >  * Removed unnecessary assert call from probe and remove.
> > > >  * wrap the line after the PTR_ERR() in probe()
> > > >  * Updated reset failure messages in probe
> > > >  * Fixed the typo arstc->prstc
> > > >  * Made hex constants to lower case.
> > > > RFC:
> > > >  *
> > > > ---
> > > >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> > > >  drivers/gpu/drm/rcar-du/Makefile  |   2 +
> > > >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 703
> > > ++
> > > >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
> > > >  4 files changed, 864 insertions(+)  create mode 100644
> > > > drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> > > >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> > > >
> > > > diff --git a/drivers/gpu/drm/rcar-du/Kconfig
> > > > b/drivers/gpu/drm/rcar-du/Kconfig index c959e8c6be7d..58ffb8c2443b
> > &g

RE: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-30 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Mon, Aug 29, 2022 at 10:19:01AM +0100, Biju Das wrote:
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It
> > currently supports DSI video mode only.
> >
> > Signed-off-by: Biju Das 
> > Acked-by: Sam Ravnborg 
> > ---
> > v5->v6:
> >  * Updated commit description
> >  * Moved handling of arst and prst from rzg2l_mipi_dsi_startup-
> >runtime
> >PM suspend/resume handlers.
> >  * Max lane capability read at probe(), and enforced in
> >rzg2l_mipi_dsi_host_attach()
> >  * Simplified vich1ppsetr setting.
> >  * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
> >  * Fixed typo in probe error message(arst->rst).
> >  * Reordered DRM bridge initaization in probe()
> >  * Updated typo in e-mail address.
> > v4->v5:
> >  * Added Ack from Sam.
> >  * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
> >with drm_of_get_data_lanes_count_ep() in probe.
> > v3->v4:
> >  * Updated error handling in rzg2l_mipi_dsi_startup() and
> > rzg2l_mipi_dsi_atomic_enable()
> > v2->v3:
> >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function
> instead
> >of the memory pointer
> >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> >  * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
> >  * DRM bridge parameter initialization moved to probe
> >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> >  * Inserted the missing blank lane after return in probe()
> >  * Added missing MODULE_DEVICE_TABLE
> >  * Added include linux/bits.h in header file
> >  * Fixed various macros in header file.
> >  * Reorder the make file for DSI, so that it is no more dependent
> >on RZ/G2L DU patch series.
> > v1->v2:
> >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> >  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> >and rzg2l_mipi_dsi_link_write
> >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > RFC->v1:
> >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> >and dropped DRM as it is implied by DRM_BRIDGE
> >  * Used devm_reset_control_get_exclusive() for reset handle
> >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> >  * Added error check for pm, using pm_runtime_resume_and_get() instead
> of
> >pm_runtime_get_sync()
> >  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> >  * Avoided read-modify-write stopping hsclock
> >  * Used devm_platform_ioremap_resource for resource allocation
> >  * Removed unnecessary assert call from probe and remove.
> >  * wrap the line after the PTR_ERR() in probe()
> >  * Updated reset failure messages in probe
> >  * Fixed the typo arstc->prstc
> >  * Made hex constants to lower case.
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> >  drivers/gpu/drm/rcar-du/Makefile  |   2 +
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 703
> ++
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
> >  4 files changed, 864 insertions(+)
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Kconfig
> > b/drivers/gpu/drm/rcar-du/Kconfig index c959e8c6be7d..58ffb8c2443b
> > 100644
> > --- a/drivers/gpu/drm/rcar-du/Kconfig
> > +++ b/drivers/gpu/drm/rcar-du/Kconfig
> > @@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
> > help
> >   Enable support for the R-Car Display Unit embedded MIPI DSI
> encoders.
> >
> > +config DRM_RZG2L_MIPI_DSI
> > +   tristate "RZ/G2L MIPI DSI Encoder Support"
> > +   depends on DRM_BRIDGE && OF
> > +   depends on ARCH_RENESAS || COMPILE_TEST
> > +   select DRM_MIPI_DSI
> > +   help
> > + Enable support for the RZ/G2L Display Unit embedded MIPI DSI
> encoders.
> > +
> >  config DRM_RCAR_VSP
> > bool "R-Car DU VSP Compositor Support" if ARM
> > default y if ARM64
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index 6f132325c8b7..b8f2c82651d9 100644
> >

RE: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-30 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> On Mon, Aug 29, 2022 at 04:26:02PM +, Biju Das wrote:
> > Hi Robert,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> > >
> > > Hey Biju,
> > >
> > > The patch does not apply on drm-misc-next, could you rebase it and
> > > submit the next version?
> >
> > I believe[1] is dependent on this patch series. Sorry for not making
> > it clear while sending this patch series out.
> >
> > I thought Laurent is going to give a pull request for RCar DU patches.
> 
> That's right. The patches apply fine to my branch.
> 
> > Based on that assumption, currently my environment is drm-tip +
> > 12 patches from[2], as [2] doesn't have all the latest patches from
> > drm-misc-next/drm-tip.
> >
> >
> > > Additionally it has a few 'checkpatch --strict' warnings.
> >
> > I got a review comment[3] to use (1 << 1) style instead of BIT macro.
> > Some of the warnings related to this.
> >
> > Laurent, any thoughts??
> 
> (1 << x) instead of BIT it correct when the field stores a value, not a
> single bit flag.

OK, then it is fine.

Cheers,
Biju

RE: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-29 Thread Biju Das

Hi Robert,

Thanks for the feedback.

> Subject: Re: [PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hey Biju,
> 
> The patch does not apply on drm-misc-next, could you rebase it and
> submit the next version?

I believe[1] is dependent on this patch series. Sorry for not
making it clear while sending this patch series out.

I thought Laurent is going to give a pull request for RCar DU patches.

Based on that assumption, currently my environment is drm-tip + 
12 patches from[2], as [2] doesn't have all the latest patches from
drm-misc-next/drm-tip.

[1] 
https://git.linuxtv.org/pinchartl/media.git/commit/drivers/gpu/drm/rcar-du?h=drm/du/next=2de250465c3ed5e13bfb5139d9a8c17105d3a1f1

[2] 
https://git.linuxtv.org/pinchartl/media.git/log/drivers/gpu/drm/rcar-du?h=drm/du/next

> 
> Additionally it has a few 'checkpatch --strict' warnings.

I got a review comment[3] to use (1 << 1) style instead of BIT macro.
Some of the warnings related to this.

[3]https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220328065115.11724-1-biju.das...@bp.renesas.com/

Laurent, any thoughts??

Cheers,
Biju

> 
> On Mon, 29 Aug 2022 at 11:19, Biju Das 
> wrote:
> >
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It
> > currently supports DSI video mode only.
> >
> > Signed-off-by: Biju Das 
> > Acked-by: Sam Ravnborg 
> > ---
> > v5->v6:
> >  * Updated commit description
> >  * Moved handling of arst and prst from rzg2l_mipi_dsi_startup-
> >runtime
> >PM suspend/resume handlers.
> >  * Max lane capability read at probe(), and enforced in
> >rzg2l_mipi_dsi_host_attach()
> >  * Simplified vich1ppsetr setting.
> >  * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
> >  * Fixed typo in probe error message(arst->rst).
> >  * Reordered DRM bridge initaization in probe()
> >  * Updated typo in e-mail address.
> > v4->v5:
> >  * Added Ack from Sam.
> >  * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
> >with drm_of_get_data_lanes_count_ep() in probe.
> > v3->v4:
> >  * Updated error handling in rzg2l_mipi_dsi_startup() and
> > rzg2l_mipi_dsi_atomic_enable()
> > v2->v3:
> >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function
> instead
> >of the memory pointer
> >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> >  * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
> >  * DRM bridge parameter initialization moved to probe
> >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> >  * Inserted the missing blank lane after return in probe()
> >  * Added missing MODULE_DEVICE_TABLE
> >  * Added include linux/bits.h in header file
> >  * Fixed various macros in header file.
> >  * Reorder the make file for DSI, so that it is no more dependent
> >on RZ/G2L DU patch series.
> > v1->v2:
> >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> >  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> >and rzg2l_mipi_dsi_link_write
> >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > RFC->v1:
> >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> >and dropped DRM as it is implied by DRM_BRIDGE
> >  * Used devm_reset_control_get_exclusive() for reset handle
> >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> >  * Added error check for pm, using pm_runtime_resume_and_get() instead
> of
> >pm_runtime_get_sync()
> >  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> >  * Avoided read-modify-write stopping hsclock
> >  * Used devm_platform_ioremap_resource for resource allocation
> >  * Removed unnecessary assert call from probe and remove.
> >  * wrap the line after the PTR_ERR() in probe()
> >  * Updated reset failure messages in probe
> >  * Fixed the typo arstc->prstc
> >  * Made hex constants to lower case.
> > RFC:
> >  *
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> > hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F2022011217461
> > 2.10773-23-biju.das.jz%40bp.renesas.com%2Fdata=05%7C01%7Cbiju.das
> > .jz%40bp.renesas.com%7C003e031f5e7f454bdfdf08da89d4d82d%7C53d82571da19
> > 47e49cb4625a166a4a2a%7C0%7C0%7C637973844501238222%7CUnknown%7CTWFpbGZs
> > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> > %7C3000%7C%7C%7Csdata=uNJMSsB3FHHDBnczS4jLEL8OADLe03K6gksF2aNn31k
> > %3Dreserved=0
> > ---
> >

[PATCH v6 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-29 Thread Biju Das

This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI video mode only.

Signed-off-by: Biju Das 
Acked-by: Sam Ravnborg 
---
v5->v6:
 * Updated commit description
 * Moved handling of arst and prst from rzg2l_mipi_dsi_startup->runtime
   PM suspend/resume handlers.
 * Max lane capability read at probe(), and enforced in
   rzg2l_mipi_dsi_host_attach()
 * Simplified vich1ppsetr setting.
 * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
 * Fixed typo in probe error message(arst->rst).
 * Reordered DRM bridge initaization in probe()
 * Updated typo in e-mail address.
v4->v5:
 * Added Ack from Sam.
 * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
   with drm_of_get_data_lanes_count_ep() in probe.
v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable()
v2->v3:
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Rework based on dt-binding change (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 703 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 4 files changed, 864 insertions(+)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index c959e8c6be7d..58ffb8c2443b 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
help
  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
 
+config DRM_RZG2L_MIPI_DSI
+   tristate "RZ/G2L MIPI DSI Encoder Support"
+   depends on DRM_BRIDGE && OF
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_MIPI_DSI
+   help
+ Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
+
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 6f132325c8b7..b8f2c82651d9 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -14,3 +14,5 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
+
+obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
new file mode 100644
index ..46a71e39e336
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
@@ -0,0 +1,703 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L MIPI DSI Encoder Driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rzg2l_mipi_dsi_regs.h"
+
+struct rzg2l

[PATCH v6 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-08-29 Thread Biju Das

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
---
v5->v6:
 * No change.
v4->v5:
 * No change.
v3->v4:
 * No change.
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
RFC->v1:
 * Added a ref to dsi-controller.yaml.
RFC:-
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..131d5b63ec4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
+  up to four data lanes.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+  - const: renesas,rzg2l-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: Sequence operation channel 0 interrupt
+  - description: Sequence operation channel 1 interrupt
+  - description: Video-Input operation channel 1 interrupt
+  - description: DSI Packet Receive interrupt
+  - description: DSI Fatal Error interrupt
+  - description: DSI D-PHY PPI interrupt
+  - description: Debug interrupt
+
+  interrupt-names:
+items:
+  - const: seq0
+  - const: seq1
+  - const: vin1
+  - const: rcv
+  - const: ferr
+  - const: ppi
+  - const: debug
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D-PHY Escape mode transmit clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+description: array of physical DSI data lane indexes.
+minItems: 1
+items:
+  - const: 1
+  - const: 2
+  - const: 3
+  - const: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+dsi0: dsi@1085 {
+compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
+reg = <0x1085 0x2>;
+interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+interrupt-names =

[PATCH v6 0/2] Add RZ/G2L DSI driver

2022-08-29 Thread Biju Das

This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI video mode only.

This unit supports MIPI Alliance Specification for Display Serial Interface 
(DSI)
Specification. This unit provides a solution for transmitting MIPI DSI compliant
digital video and packets. Normative References are below.
* MIPI Alliance Specification for Display Serial Interface Version 1.3.1
* MIPI Alliance Specification for D-PHY Version 2.1

The following are key features of this unit.

* 1 channel
* The number of Lane: 4-lane
* Support up to Full HD (1920 × 1080), 60 fps (RGB888)
* Maximum Bandwidth: 1.5 Gbps per lane
* Support Output Data Format: RGB666 / RGB888

v5->v6:
 * Updated commit description
 * Moved handling of arst and prst from rzg2l_mipi_dsi_startup->runtime
   PM suspend/resume handlers.
 * Max lane capability read at probe(), and enforced in
   rzg2l_mipi_dsi_host_attach()
 * Simplified vich1ppsetr setting.
 * Renamed hsclk_running_mode,hsclk_mode->is_clk_cont.
 * Fixed typo in probe error message(arst->rst).
 * Reordered DRM bridge initaization in probe()
 * Updated typo in e-mail address.
v4->v5:
 * Added Ack from Sam.
 * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
   with drm_of_get_data_lanes_count_ep() in probe.
v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable().
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
 * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added a ref to dsi-controller.yaml.
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/

Biju Das (2):
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver

 .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 703 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 5 files changed, 1046 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.25.1

RE: [PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format

2022-08-28 Thread Biju Das

Hi Laurent,

> Subject: Re: [PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format
> 
> Hi Biju,
> 
> On Sat, Aug 27, 2022 at 09:04:25AM +, Biju Das wrote:
> > Subject: Re: [PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format
> > > On Thu, Aug 25, 2022 at 11:39:05AM +0100, Biju Das wrote:
> > > > Replace use of struct rcar_du_format_info with %p4cc for printing
> > > > 4CC formats.
> > >
> > > The code change looks good, but doesn't match the commit message.
> > > You're not replacing usage of struct rcar_du_format_info. I propose
> > > the following commit message:
> > >
> > > Use the %p4cc format specifier to print 4CCs, which will provide a
> > > more readable message than the raw hex value.
> >
> > OK.
> >
> > > > Reported-by: Geert Uytterhoeven 
> > > > Signed-off-by: Biju Das 
> > > > ---
> > > >  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > > > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > > > index 21881fb5e84a..8c2719efda2a 100644
> > > > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > > > @@ -405,8 +405,8 @@ rcar_du_fb_create(struct drm_device *dev,
> > > > struct drm_file *file_priv,
> > > >
> > > > format = rcar_du_format_info(mode_cmd->pixel_format);
> > > > if (format == NULL) {
> > > > -   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
> > > > -   mode_cmd->pixel_format);
> > > > +   dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
> > > > +   _cmd->pixel_format);
> > > > return ERR_PTR(-EINVAL);
> > > > }
> > > >
> > >
> > > There are two other occurrences:
> > >
> > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > index 26b25ca58968..83631ee2fff1 100644
> > > --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > @@ -626,8 +626,8 @@ int __rcar_du_plane_atomic_check(struct
> > > drm_plane *plane,
> > >
> > >   *format = rcar_du_format_info(state->fb->format->format);
> > >   if (*format == NULL) {
> > > - dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
> > > - state->fb->format->format);
> > > + dev_dbg(dev->dev, "%s: unsupported format %p4cc\n",
> > > __func__,
> > > + >fb->format->format);
> > >   return -EINVAL;
> > >   }
> > >
> > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> > > b/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> > > index 25f50a297c11..8cd37d7b8ae2 100644
> > > --- a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> > > @@ -166,8 +166,8 @@ static int rcar_du_wb_enc_atomic_check(struct
> > > drm_encoder *encoder,
> > >
> > >   wb_state->format = rcar_du_format_info(fb->format->format);
> > >   if (wb_state->format == NULL) {
> > > - dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
> > > - fb->format->format);
> > > + dev_dbg(dev->dev, "%s: unsupported format %p4cc\n",
> > > __func__,
> > > + >format->format);
> > >   return -EINVAL;
> > >   }
> > >
> > > I can add these changes to the patch and update the commit message
> > > when applying if you're fine with that. In that case,
> >
> > I am ok with it.
> >
> > Is it possible for you to share the git tree with latest RCar DU
> changes?
> > so that I can rebase RCar DU lib and RZ/G2L DU work on top of that.
> >
> > Currently I am rebasing on top of drm_tip. Please let me know.
> 
> Sure. The tree is available at git://linuxtv.org/pinchartl/media.git,
> and my drm next branch for the DU driver is drm/du/next.

Thank you, Will rebase on drm/du/next

Cheers,
Biju

 
> > > Reviewed-by: Laurent Pinchart 
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v5 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-27 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v5 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Thu, Aug 25, 2022 at 02:42:29PM +0100, Biju Das wrote:
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It
> > currently supports DSI mode only.
> 
> What other modes than DSI are there ?

Currently it supports video mode only (video-input operation).

This mode is tested with DSI connected to ADV7535 bridge.

But lot of customers are asking for DSI panel support as well.
So going forward this driver needs to support DSI DCS commands
for supporting DSI panels.

> 
> > Signed-off-by: Biju Das 
> > Acked-by: Sam Ravnborg 
> > ---
> > v4->v5:
> >  * Added Ack from Sam.
> >  * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
> >with drm_of_get_data_lanes_count_ep() in probe.
> > v3->v4:
> >  * Updated error handling in rzg2l_mipi_dsi_startup() and
> > rzg2l_mipi_dsi_atomic_enable()
> > v2->v3:
> >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function
> instead
> >of the memory pointer
> >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> >  * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
> >  * DRM bridge parameter initialization moved to probe
> >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> >  * Inserted the missing blank lane after return in probe()
> >  * Added missing MODULE_DEVICE_TABLE
> >  * Added include linux/bits.h in header file
> >  * Fixed various macros in header file.
> >  * Reorder the make file for DSI, so that it is no more dependent
> >on RZ/G2L DU patch series.
> > v1->v2:
> >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> >  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> >and rzg2l_mipi_dsi_link_write
> >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > RFC->v1:
> >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> >and dropped DRM as it is implied by DRM_BRIDGE
> >  * Used devm_reset_control_get_exclusive() for reset handle
> >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> >  * Added error check for pm, using pm_runtime_resume_and_get() instead
> of
> >pm_runtime_get_sync()
> >  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> >  * Avoided read-modify-write stopping hsclock
> >  * Used devm_platform_ioremap_resource for resource allocation
> >  * Removed unnecessary assert call from probe and remove.
> >  * wrap the line after the PTR_ERR() in probe()
> >  * Updated reset failure messages in probe
> >  * Fixed the typo arstc->prstc
> >  * Made hex constants to lower case.
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> >  drivers/gpu/drm/rcar-du/Makefile  |   2 +
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690
> ++
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
> >  4 files changed, 851 insertions(+)
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Kconfig
> > b/drivers/gpu/drm/rcar-du/Kconfig index c959e8c6be7d..58ffb8c2443b
> > 100644
> > --- a/drivers/gpu/drm/rcar-du/Kconfig
> > +++ b/drivers/gpu/drm/rcar-du/Kconfig
> > @@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
> > help
> >   Enable support for the R-Car Display Unit embedded MIPI DSI
> encoders.
> >
> > +config DRM_RZG2L_MIPI_DSI
> > +   tristate "RZ/G2L MIPI DSI Encoder Support"
> > +   depends on DRM_BRIDGE && OF
> > +   depends on ARCH_RENESAS || COMPILE_TEST
> > +   select DRM_MIPI_DSI
> > +   help
> > + Enable support for the RZ/G2L Display Unit embedded MIPI DSI
> encoders.
> > +
> >  config DRM_RCAR_VSP
> > bool "R-Car DU VSP Compositor Support" if ARM
> > default y if ARM64
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index e7275b5e7ec8..14a3fa88cc0b 100644
> > --- a/drivers/gpu/drm/rcar-du/Makefile
> > +++ b/drivers/gpu/drm/rcar-du/Makefile
> > @@ -15,6 +15,8 @@ obj-$(CONFIG_DRM_RCAR_DW_HDMI)+=
> rcar_dw_hdmi.o
> >  obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
> >  obj-$(CONFI

RE: [PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format

2022-08-27 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Thu, Aug 25, 2022 at 11:39:05AM +0100, Biju Das wrote:
> > Replace use of struct rcar_du_format_info with %p4cc for printing 4CC
> > formats.
> 
> The code change looks good, but doesn't match the commit message. You're
> not replacing usage of struct rcar_du_format_info. I propose the
> following commit message:
> 
> Use the %p4cc format specifier to print 4CCs, which will provide a more
> readable message than the raw hex value.

OK.

> 
> > Reported-by: Geert Uytterhoeven 
> > Signed-off-by: Biju Das 
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index 21881fb5e84a..8c2719efda2a 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -405,8 +405,8 @@ rcar_du_fb_create(struct drm_device *dev, struct
> > drm_file *file_priv,
> >
> > format = rcar_du_format_info(mode_cmd->pixel_format);
> > if (format == NULL) {
> > -   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
> > -   mode_cmd->pixel_format);
> > +   dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
> > +   _cmd->pixel_format);
> > return ERR_PTR(-EINVAL);
> > }
> >
> 
> There are two other occurrences:
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> index 26b25ca58968..83631ee2fff1 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> @@ -626,8 +626,8 @@ int __rcar_du_plane_atomic_check(struct drm_plane
> *plane,
> 
>   *format = rcar_du_format_info(state->fb->format->format);
>   if (*format == NULL) {
> - dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
> - state->fb->format->format);
> + dev_dbg(dev->dev, "%s: unsupported format %p4cc\n",
> __func__,
> + >fb->format->format);
>   return -EINVAL;
>   }
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> b/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> index 25f50a297c11..8cd37d7b8ae2 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
> @@ -166,8 +166,8 @@ static int rcar_du_wb_enc_atomic_check(struct
> drm_encoder *encoder,
> 
>   wb_state->format = rcar_du_format_info(fb->format->format);
>   if (wb_state->format == NULL) {
> - dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
> - fb->format->format);
> + dev_dbg(dev->dev, "%s: unsupported format %p4cc\n",
> __func__,
> + >format->format);
>   return -EINVAL;
>   }
> 
> I can add these changes to the patch and update the commit message when
> applying if you're fine with that. In that case,

I am ok with it.

Is it possible for you to share the git tree with latest RCar DU changes?
so that I can rebase RCar DU lib and RZ/G2L DU work on top of that.

Currently I am rebasing on top of drm_tip. Please let me know.

Thanks and regards,
Biju

> 
> Reviewed-by: Laurent Pinchart 
>

[PATCH v5 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-08-25 Thread Biju Das

This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

Signed-off-by: Biju Das 
Acked-by: Sam Ravnborg 
---
v4->v5:
 * Added Ack from Sam.
 * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
   with drm_of_get_data_lanes_count_ep() in probe.
v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable()
v2->v3:
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Rework based on dt-binding change (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 4 files changed, 851 insertions(+)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index c959e8c6be7d..58ffb8c2443b 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
help
  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
 
+config DRM_RZG2L_MIPI_DSI
+   tristate "RZ/G2L MIPI DSI Encoder Support"
+   depends on DRM_BRIDGE && OF
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_MIPI_DSI
+   help
+ Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
+
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index e7275b5e7ec8..14a3fa88cc0b 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_DRM_RCAR_DW_HDMI)+= 
rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
+
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
 DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
new file mode 100644
index ..e0bdb5dc7036
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L MIPI DSI Encoder Driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rzg2l_mipi_dsi_regs.h"
+
+struct rzg2l_mipi_dsi {
+   struct device *dev;
+   void __iomem *mmio;
+
+   struct reset_control *rstc;
+   struct reset_control *arstc;
+   struct reset_control *prstc;
+
+   struct mipi_dsi_host host;
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+
+   struct clk *vclk;
+
+   enum mipi_dsi_pixel_format

[PATCH v5 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-08-25 Thread Biju Das

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
---
v4->v5:
 * No change.
v3->v4:
 * No change.
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
RFC->v1:
 * Added a ref to dsi-controller.yaml.
RFC:-
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..131d5b63ec4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
+  up to four data lanes.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+  - const: renesas,rzg2l-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: Sequence operation channel 0 interrupt
+  - description: Sequence operation channel 1 interrupt
+  - description: Video-Input operation channel 1 interrupt
+  - description: DSI Packet Receive interrupt
+  - description: DSI Fatal Error interrupt
+  - description: DSI D-PHY PPI interrupt
+  - description: Debug interrupt
+
+  interrupt-names:
+items:
+  - const: seq0
+  - const: seq1
+  - const: vin1
+  - const: rcv
+  - const: ferr
+  - const: ppi
+  - const: debug
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D-PHY Escape mode transmit clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+description: array of physical DSI data lane indexes.
+minItems: 1
+items:
+  - const: 1
+  - const: 2
+  - const: 3
+  - const: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+dsi0: dsi@1085 {
+compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
+reg = <0x1085 0x2>;
+interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+interrupt-names = "seq0", "seq1&q

[PATCH v5 0/2] Add RZ/G2L DSI driver

2022-08-25 Thread Biju Das

This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

This unit supports MIPI Alliance Specification for Display Serial Interface 
(DSI)
Specification. This unit provides a solution for transmitting MIPI DSI compliant
digital video and packets. Normative References are below.
* MIPI Alliance Specification for Display Serial Interface Version 1.3.1
* MIPI Alliance Specification for D-PHY Version 2.1

The following are key features of this unit.

* 1 channel
* The number of Lane: 4-lane
* Support up to Full HD (1920 × 1080), 60 fps (RGB888)
* Maximum Bandwidth: 1.5 Gbps per lane
* Support Output Data Format: RGB666 / RGB888

v4->v5:
 * Added Ack from Sam.
 * Added a trivial change, replaced rzg2l_mipi_dsi_parse_dt()
   with drm_of_get_data_lanes_count_ep() in probe.
v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable().
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
 * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added a ref to dsi-controller.yaml.
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/


Biju Das (2):
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver

 .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 5 files changed, 1033 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.25.1

[PATCH 2/2] drm: rcar-du: Use %p4cc to print 4CC format

2022-08-25 Thread Biju Das

Replace use of struct rcar_du_format_info with %p4cc for printing
4CC formats.

Reported-by: Geert Uytterhoeven 
Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 21881fb5e84a..8c2719efda2a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -405,8 +405,8 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file 
*file_priv,
 
format = rcar_du_format_info(mode_cmd->pixel_format);
if (format == NULL) {
-   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
-   mode_cmd->pixel_format);
+   dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
+   _cmd->pixel_format);
return ERR_PTR(-EINVAL);
}
 
-- 
2.25.1

[PATCH 1/2] drm: rcar-du: Drop unused encoder header files

2022-08-25 Thread Biju Das

Drop unused header files from rcar_du_encoder.c

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c 
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index 60d6be78323b..bfd5c087eb0a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -9,18 +9,13 @@
 
 #include 
 #include 
-#include 
 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include 
 
 #include "rcar_du_drv.h"
 #include "rcar_du_encoder.h"
-#include "rcar_du_kms.h"
 #include "rcar_lvds.h"
 
 /* 
-
-- 
2.25.1

RE: [PATCH v5 04/10] drm: rcar-du: Add rcar_du_lib_fb_create()

2022-08-24 Thread Biju Das

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v5 04/10] drm: rcar-du: Add rcar_du_lib_fb_create()
> 
> Hi Biju,
> 
> On Wed, Jul 27, 2022 at 6:08 PM Biju Das 
> wrote:
> > Move the common code from rcar_du_fb_create->rcar_du_lib_fb_create,
> > so that rzg2l_du_fb_create() can reuse the common code.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v5:
> >  * New patch
> 
> Thanks for your patch!
> 
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
> > @@ -392,3 +392,72 @@ int rcar_du_dumb_create(struct drm_file *file,
> > struct drm_device *dev,
> >
> > return drm_gem_cma_dumb_create_internal(file, dev, args);  }
> > +
> > +struct drm_framebuffer *
> > +rcar_du_lib_fb_create(struct drm_device *dev, struct drm_file
> *file_priv,
> > + const struct drm_mode_fb_cmd2 *mode_cmd) {
> > +   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
> > +   const struct rcar_du_format_info *format;
> > +   unsigned int chroma_pitch;
> > +   unsigned int max_pitch;
> > +   unsigned int align;
> > +   unsigned int i;
> > +
> > +   format = rcar_du_format_info(mode_cmd->pixel_format);
> > +   if (format == NULL) {
> > +   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
> 
> I know you're just moving code, but nowadays we do have "%p4cc", which
> takes a pointer to the fourcc value.

OK, will fix this in next version, if this change is ok to everyone.

Cheers,
Biju

> 
> > +   mode_cmd->pixel_format);
> > +   return ERR_PTR(-EINVAL);
> > +   }
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds

RE: [PATCH v2 1/4] drm: rcar-du: dsi: Properly stop video mode TX

2022-08-22 Thread Biju Das

Hi,

> Subject: Re: [PATCH v2 1/4] drm: rcar-du: dsi: Properly stop video mode
> TX
> 
> Hi,
> 
> On 22/08/2022 16:25, Biju Das wrote:
> > Hi Tomi,
> >
> > Thanks for the patch.
> >
> >> Subject: [PATCH v2 1/4] drm: rcar-du: dsi: Properly stop video mode
> >> TX
> >>
> >> From: Tomi Valkeinen 
> >>
> >> The driver does not explicitly stop the video mode transmission when
> >> disabling the output. While this doesn't seem to be causing any
> >> issues, lets follow the steps described in the documentation and add
> >> a
> >> rcar_mipi_dsi_stop_video() which stop the video mode transmission.
> >> This function will also be used in later patches to stop the video
> >> transmission even if the DSI IP is not shut down.
> >>
> >> Signed-off-by: Tomi Valkeinen
> >> 
> >> ---
> >>   drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 29
> +
> >>   1 file changed, 29 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> >> b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> >> index 62f7eb84ab01..7f2be490fcf8 100644
> >> --- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> >> +++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> >> @@ -542,6 +542,34 @@ static int rcar_mipi_dsi_start_video(struct
> >> rcar_mipi_dsi *dsi)
> >>return 0;
> >>   }
> >>
> >> +static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi) {
> >> +  u32 status;
> >> +  int ret;
> >> +
> >> +  /* Disable transmission in video mode. */
> >> +  rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO);
> >> +
> >> +  ret = read_poll_timeout(rcar_mipi_dsi_read, status,
> >> +  !(status & TXVMSR_ACT),
> >> +  2000, 10, false, dsi, TXVMSR);
> >> +  if (ret < 0) {
> >> +  dev_err(dsi->dev, "Failed to disable video transmission\n");
> >> +  return;
> >> +  }
> >> +
> >> +  /* Assert video FIFO clear. */
> >> +  rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR);
> >> +
> >> +  ret = read_poll_timeout(rcar_mipi_dsi_read, status,
> >> +  !(status & TXVMSR_VFRDY),
> >> +  2000, 10, false, dsi, TXVMSR);
> >> +  if (ret < 0) {
> >> +  dev_err(dsi->dev, "Failed to assert video FIFO clear\n");
> >> +  return;
> >
> > This return is not required.
> 
> That is true, but I'd personally rather keep it there. If the return is
> removed, I can imagine how easily one could add a new piece of code in
> the end of the function, not realizing that one also needs to add a
> return (the one above) so that the code works correctly.
> 
> It just feels a bit safer this way.

OK, I just thought of reducing number of lines and remove unwanted code
As return type is void.

if (ret < 0)
  dev_err(dsi->dev, "Failed to assert video FIFO clear\n");

Any way there is a review process which will capture the issue you mentioned.

I am ok with your statement.

Cheers,
Biju

RE: [PATCH v2 1/4] drm: rcar-du: dsi: Properly stop video mode TX

2022-08-22 Thread Biju Das

Hi Tomi,

Thanks for the patch.

> Subject: [PATCH v2 1/4] drm: rcar-du: dsi: Properly stop video mode TX
> 
> From: Tomi Valkeinen 
> 
> The driver does not explicitly stop the video mode transmission when
> disabling the output. While this doesn't seem to be causing any issues,
> lets follow the steps described in the documentation and add a
> rcar_mipi_dsi_stop_video() which stop the video mode transmission. This
> function will also be used in later patches to stop the video
> transmission even if the DSI IP is not shut down.
> 
> Signed-off-by: Tomi Valkeinen 
> ---
>  drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c | 29 +
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> index 62f7eb84ab01..7f2be490fcf8 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c
> @@ -542,6 +542,34 @@ static int rcar_mipi_dsi_start_video(struct
> rcar_mipi_dsi *dsi)
>   return 0;
>  }
> 
> +static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi) {
> + u32 status;
> + int ret;
> +
> + /* Disable transmission in video mode. */
> + rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO);
> +
> + ret = read_poll_timeout(rcar_mipi_dsi_read, status,
> + !(status & TXVMSR_ACT),
> + 2000, 10, false, dsi, TXVMSR);
> + if (ret < 0) {
> + dev_err(dsi->dev, "Failed to disable video transmission\n");
> + return;
> + }
> +
> + /* Assert video FIFO clear. */
> + rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR);
> +
> + ret = read_poll_timeout(rcar_mipi_dsi_read, status,
> + !(status & TXVMSR_VFRDY),
> + 2000, 10, false, dsi, TXVMSR);
> + if (ret < 0) {
> + dev_err(dsi->dev, "Failed to assert video FIFO clear\n");
> + return;

This return is not required.

Cheers,
Biju

> + }
> +}
> +
>  /* 
> -
>   * Bridge
>   */
> @@ -601,6 +629,7 @@ static void rcar_mipi_dsi_atomic_disable(struct
> drm_bridge *bridge,  {
>   struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
> 
> + rcar_mipi_dsi_stop_video(dsi);
>   rcar_mipi_dsi_shutdown(dsi);
>   rcar_mipi_dsi_clk_disable(dsi);
>  }
> --
> 2.34.1

RE: imx8mm lcdif->dsi->adv7535 no video, no errors

2022-08-05 Thread Biju Das

Hi Adam and all,

> Subject: Re: imx8mm lcdif->dsi->adv7535 no video, no errors
> 
> On Thu, Aug 4, 2022 at 9:52 AM Dave Stevenson
>  wrote:
> >
> > On Thu, 4 Aug 2022 at 13:51, Marco Felsch 
> wrote:
> > >
> > > Hi Dave,
> > >
> > > On 22-08-04, Dave Stevenson wrote:
> > > > Hi Marco
> > > >
> > > > On Thu, 4 Aug 2022 at 10:38, Marco Felsch
>  wrote:
> > > > >
> > > > > Hi Dave, Adam,
> > > > >
> > > > > On 22-08-03, Dave Stevenson wrote:
> > > > > > Hi Adam
> > > > > >
> > > > > > On Wed, 3 Aug 2022 at 12:03, Adam Ford 
> wrote:
> > > > >
> > > > > ...
> > > > >
> > > > > > > > Did managed to get access to the ADV7535 programming
> > > > > > > > guide? This is the black box here. Let me check if I can
> > > > > > > > provide you a link with our repo so you can test our
> current DSIM state if you want.
> > > > > > >
> > > > > > > I do have access to the programming guide, but it's under
> > > > > > > NDA, but I'll try to answer questions if I can.
> > > > > >
> > > > > > Not meaning to butt in, but I have datasheets for ADV7533 and
> > > > > > 7535 from previously looking at these chips.
> > > > >
> > > > > Thanks for stepping into :)
> > > > >
> > > > > > Mine fairly plainly states:
> > > > > > "The DSI receiver input supports DSI video mode operation
> > > > > > only, and specifically, only supports nonburst mode with sync
> pulses".
> > > > >
> > > > > I've read this also, and we are working in nonburst mode with
> > > > > sync pulses. I have no access to an MIPI-DSI analyzer therefore
> > > > > I can't verify it.
> > > > >
> > > > > > Non-burst mode meaning that the DSI pixel rate MUST be the
> > > > > > same as the HDMI pixel rate.
> > > > >
> > > > > On DSI side you don't have a pixel-clock instead there is bit-
> clock.
> > > >
> > > > You have an effective pixel clock, with a fixed conversion for the
> > > > configuration.
> > > >
> > > > DSI bit-clock * number of lanes / bits_per_pixel = pixel rate.
> > > > 891Mbit/s * 4 lanes / 24bpp = 148.5 Mpixels/s
> > >
> > > Okay, I just checked the bandwidth which must equal.
> > >
> > > > As noted elsewhere, the DSI is DDR, so the clock lane itself is
> > > > only running at 891 / 2 = 445.5MHz.
> > > >
> > > > > > Section 6.1.1 "DSI Input Modes" of
> > > > > > adv7533_hardware_user_s_guide is even more explicit about the
> > > > > > requirement of DSI timing matching
> > > > >
> > > > > Is it possible to share the key points of the requirements?
> > > >
> > > > "Specifically the ADV7533 supports the Non-Burst Mode with syncs.
> > > > This mode requires real time data generation as a pulse packet
> > > > received becomes a pulse generated. Therefore this mode requires a
> > > > continuous stream of data with correct video timing to avoid any
> > > > visual artifacts."
> > > >
> > > > LP mode is supported on data lanes. Clock lane must remain in HS
> mode.
> > > >
> > > > "... the goal is to accurately convey DPI-type timing over DSI.
> > > > This includes matching DPI pixel-transmission rates, and widths of
> > > > timing events."
> > >
> > > Thanks for sharing.
> > >
> > > > > > The NXP kernel switching down to an hs_clk of 445.5MHz would
> > > > > > therefore be correct for 720p operation.
> > > > >
> > > > > It should be absolute no difference if you work on 891MHz with 2
> > > > > lanes or on 445.5 MHz with 4 lanes. What must be ensured is that
> > > > > you need the minimum required bandwidth which is roughly:
> > > > > 1280*720*24*60 = 1.327 GBps.
> > > >
> > > > Has someone changed the number of lanes in use? I'd missed that if
> > > > so, but I'll agree that 891MHz over 2 lanes should work for
> 720p60.
> > >
> > > The ADV driver is changing it autom. but this logic is somehow odd
> > > and there was already a approach to stop the driver doing this.
> >
> > I'd missed that bit in the driver where it appears to drop to 3 lanes
> > for pixel clock < 8 via a mipi_dsi_detach and _attach. Quirky, but
> > probably the only way it can be achieved in the current framework.
> >
> > > To sync up: we have two problems:
> > >   1) The 720P mode with static DSI host configuration isn't working
> > >  without hacks.
> > >   2) The DSI link frequency should changed as soon as required
> > >  automatically. So we can provide all modes.
> > >
> > > I would concentrate on problem 1 first before moving on to the 2nd.
> >
> > If you change your link frequency, it may be worth trying a lower
> > resolution again such as 720x480 @ 60fps on 2 lanes. (720480@60 on 4
> > lanes is again listed as mandatory for using the timing generator).
> >
> > > > I have just noted that 720p59.94 at 24bpp on 4 lanes is listed as
> > > > one of the modes that is mandatory to use the timing generator
> > > > (reg 0x27 bit 7 = 1). On 2 lanes it is not required.
> > > > I don't know why it's referencing the 1000/1001 pixel clock rates
> > > > and not the base one, as it's only a base clock change with the
> > > > same timing (74.176MHz clock instead of 74.25MHz).
> > >
> > >

RE: imx8mm lcdif->dsi->adv7535 no video, no errors

2022-08-04 Thread Biju Das

Hi Adam,

> Subject: Re: imx8mm lcdif->dsi->adv7535 no video, no errors
> 
> On Thu, Aug 4, 2022 at 7:52 AM Marco Felsch 
> wrote:
> >
> > Hi Dave,
> >
> > On 22-08-04, Dave Stevenson wrote:
> > > Hi Marco
> > >
> > > On Thu, 4 Aug 2022 at 10:38, Marco Felsch 
> wrote:
> > > >
> > > > Hi Dave, Adam,
> > > >
> > > > On 22-08-03, Dave Stevenson wrote:
> > > > > Hi Adam
> > > > >
> > > > > On Wed, 3 Aug 2022 at 12:03, Adam Ford 
> wrote:
> > > >
> > > > ...
> > > >
> > > > > > > Did managed to get access to the ADV7535 programming guide?
> > > > > > > This is the black box here. Let me check if I can provide
> > > > > > > you a link with our repo so you can test our current DSIM
> state if you want.
> > > > > >
> > > > > > I do have access to the programming guide, but it's under NDA,
> > > > > > but I'll try to answer questions if I can.
> > > > >
> > > > > Not meaning to butt in, but I have datasheets for ADV7533 and
> > > > > 7535 from previously looking at these chips.
> > > >
> > > > Thanks for stepping into :)
> > > >
> > > > > Mine fairly plainly states:
> > > > > "The DSI receiver input supports DSI video mode operation only,
> > > > > and specifically, only supports nonburst mode with sync pulses".
> > > >
> > > > I've read this also, and we are working in nonburst mode with sync
> > > > pulses. I have no access to an MIPI-DSI analyzer therefore I can't
> > > > verify it.
> > > >
> > > > > Non-burst mode meaning that the DSI pixel rate MUST be the same
> > > > > as the HDMI pixel rate.
> > > >
> > > > On DSI side you don't have a pixel-clock instead there is bit-
> clock.
> > >
> > > You have an effective pixel clock, with a fixed conversion for the
> > > configuration.
> > >
> > > DSI bit-clock * number of lanes / bits_per_pixel = pixel rate.
> > > 891Mbit/s * 4 lanes / 24bpp = 148.5 Mpixels/s
> >
> > Okay, I just checked the bandwidth which must equal.
> >
> > > As noted elsewhere, the DSI is DDR, so the clock lane itself is only
> > > running at 891 / 2 = 445.5MHz.
> > >
> > > > > Section 6.1.1 "DSI Input Modes" of adv7533_hardware_user_s_guide
> > > > > is even more explicit about the requirement of DSI timing
> > > > > matching
> > > >
> > > > Is it possible to share the key points of the requirements?
> > >
> > > "Specifically the ADV7533 supports the Non-Burst Mode with syncs.
> > > This mode requires real time data generation as a pulse packet
> > > received becomes a pulse generated. Therefore this mode requires a
> > > continuous stream of data with correct video timing to avoid any
> > > visual artifacts."
> > >
> > > LP mode is supported on data lanes. Clock lane must remain in HS
> mode.
> > >
> > > "... the goal is to accurately convey DPI-type timing over DSI. This
> > > includes matching DPI pixel-transmission rates, and widths of timing
> > > events."
> >
> > Thanks for sharing.
> >
> > > > > The NXP kernel switching down to an hs_clk of 445.5MHz would
> > > > > therefore be correct for 720p operation.
> > > >
> > > > It should be absolute no difference if you work on 891MHz with 2
> > > > lanes or on 445.5 MHz with 4 lanes. What must be ensured is that
> > > > you need the minimum required bandwidth which is roughly:
> > > > 1280*720*24*60 = 1.327 GBps.
> > >
> > > Has someone changed the number of lanes in use? I'd missed that if
> > > so, but I'll agree that 891MHz over 2 lanes should work for 720p60.
> >
> > The ADV driver is changing it autom. but this logic is somehow odd and
> > there was already a approach to stop the driver doing this.
> >
> > To sync up: we have two problems:
> >   1) The 720P mode with static DSI host configuration isn't working
> >  without hacks.
> 
> can you share your hacks with me about getting 720p to work?  I've been
> struggling to get 720 to work.

I have problems with 720p working on 3 lanes. Then I switch to 4 lanes [1]
and it starts working on Renesas RZ/G2L SMARC EVK.

[1] 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220309151109.20957-2-biju.das...@bp.renesas.com/

Cheers,
Biju

[PATCH v5 10/10] drm: rcar-du: Add RZ/G2L DU Support

2022-07-27 Thread Biju Das

The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support blending of two picture layers and
raster operations (ROPs).

The DU part is similar to RCar like DU is connected to VSPD, so most of
the framework related functionality is based on RCar DU.

Signed-off-by: Biju Das 
---
v4->v5:
 * Started using RCar DU libs(kms, vsp and encoder)
 * Started using rcar_du_device, rcar_du_write, rcar_du_crtc,
   rcar_du_format_info and rcar_du_encoder.
v3->v4:
 * Removed rzg2l_du_group.h and struct rzg2l_du_group
 * Renamed __rzg2l_du_group_start_stop->rzg2l_du_start_stop
 * Removed rzg2l_du_group_restart
 * Updated rzg2l_du_crtc_set_display_timing
 * Removed mode_valid callback.
 * Updated rzg2l_du_crtc_create() parameters
 * Updated compatible
 * Removed RZG2L_DU_MAX_GROUPS
v3:
 * New patch after removing all the indirections and by adding
   new DRM driver.
---
 drivers/gpu/drm/rcar-du/Kconfig|  17 +-
 drivers/gpu/drm/rcar-du/Makefile   |  13 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c| 718 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h|  26 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c | 206 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h |  20 +
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c |  26 +
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h |  19 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c | 158 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h |  17 +
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h|  67 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c |  82 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h |  29 +
 13 files changed, 1396 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index f8e1341be5f8..c45416197a2b 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -11,6 +11,18 @@ config DRM_RCAR_DU
  Choose this option if you have an R-Car chipset.
  If M is selected the module will be called rcar-du-drm.
 
+config DRM_RZG2L_DU
+   tristate "DRM Support for RZ/G2L DU"
+   depends on DRM && OF
+   depends on ARM || ARM64
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_KMS_HELPER
+   select DRM_GEM_CMA_HELPER
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you have an RZ/G2L chipset.
+ If M is selected the module will be called rzg2l-du-drm.
+
 config DRM_RCAR_USE_CMM
bool "R-Car DU Color Management Module (CMM) Support"
depends on DRM_RCAR_DU
@@ -62,8 +74,9 @@ config DRM_RZG2L_MIPI_DSI
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
-   depends on DRM_RCAR_DU
+   depends on DRM_RCAR_DU || DRM_RZG2L_DU
depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+   depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && 
DRM_RZG2L_DU=m)
help
  Enable support to expose the R-Car VSP Compositor as KMS planes.
 
@@ -75,7 +88,7 @@ config DRM_RCAR_WRITEBACK
 config DRM_RCAR_LIB
bool
default y
-   depends on DRM_RCAR_DU
+   depends on DRM_RCAR_DU || DRM_RZG2L_DU
 
 config DRM_RCAR_VSP_LIB
bool
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index cee1f69926db..445ff4e7186f 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -19,6 +19,19 @@ obj-$(CONFIG_DRM_RCAR_DW_HDMI)   += 
rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
+rzg2l-du-drm-y := rzg2l_du_crtc.o \
+ rzg2l_du_drv.o \
+ rzg2l_du_encoder.o \
+ rzg2l_du_kms.o \
+
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o \
+  rcar_du_kms_lib.o
+
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP)+= rzg2l_du_vsp.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP_LIB)+= rcar_du_vsp_lib.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
+

[PATCH v5 05/10] drm: rcar-du: Add rcar_du_lib_mode_cfg_helper_fns()

2022-07-27 Thread Biju Das

Add rcar_du_lib_mode_cfg_helper_fns() in RCar DU kms lib to get the
pointer to rcar_du_mode_config_helper, so that both rcar_du_atomic_
commit_tail() and rcar_du_mode_config_helper can be reused by
rcar_du_modeset_init() and rzg2l_du_modeset_init().

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 44 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 56 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  3 ++
 3 files changed, 60 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 9d65a7d6d96e..ed8d14701178 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -64,52 +64,10 @@ static int rcar_du_atomic_check(struct drm_device *dev,
return rcar_du_atomic_check_planes(dev, state);
 }
 
-static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
-{
-   struct drm_device *dev = old_state->dev;
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   struct drm_crtc_state *crtc_state;
-   struct drm_crtc *crtc;
-   unsigned int i;
-
-   /*
-* Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
-* when starting the CRTCs.
-*/
-   rcdu->dpad1_source = -1;
-
-   for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
-   struct rcar_du_crtc_state *rcrtc_state =
-   to_rcar_crtc_state(crtc_state);
-   struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
-
-   if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
-   rcdu->dpad0_source = rcrtc->index;
-
-   if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
-   rcdu->dpad1_source = rcrtc->index;
-   }
-
-   /* Apply the atomic update. */
-   drm_atomic_helper_commit_modeset_disables(dev, old_state);
-   drm_atomic_helper_commit_planes(dev, old_state,
-   DRM_PLANE_COMMIT_ACTIVE_ONLY);
-   drm_atomic_helper_commit_modeset_enables(dev, old_state);
-
-   drm_atomic_helper_commit_hw_done(old_state);
-   drm_atomic_helper_wait_for_flip_done(dev, old_state);
-
-   drm_atomic_helper_cleanup_planes(dev, old_state);
-}
-
 /* 
-
  * Initialization
  */
 
-static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
-   .atomic_commit_tail = rcar_du_atomic_commit_tail,
-};
-
 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
.fb_create = rcar_du_fb_create,
.atomic_check = rcar_du_atomic_check,
@@ -415,7 +373,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
dev->mode_config.min_height = 0;
dev->mode_config.normalize_zpos = true;
dev->mode_config.funcs = _du_mode_config_funcs;
-   dev->mode_config.helper_private = _du_mode_config_helper;
+   dev->mode_config.helper_private = rcar_du_lib_mode_cfg_helper_fns();
 
if (rcdu->info->gen < 3) {
dev->mode_config.max_width = 4095;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index d8f778a7b6db..a1027436cfe3 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -461,3 +461,59 @@ rcar_du_lib_fb_create(struct drm_device *dev, struct 
drm_file *file_priv,
 
return drm_gem_fb_create(dev, file_priv, mode_cmd);
 }
+
+/* 
-
+ * Atomic Check and Update
+ */
+
+static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
+{
+   struct drm_device *dev = old_state->dev;
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   struct drm_crtc_state *crtc_state;
+   struct drm_crtc *crtc;
+   unsigned int i;
+
+   /*
+* Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
+* when starting the CRTCs.
+*/
+   rcdu->dpad1_source = -1;
+
+   for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
+   struct rcar_du_crtc_state *rcrtc_state =
+   to_rcar_crtc_state(crtc_state);
+   struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+   if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
+   rcdu->dpad0_source = rcrtc->index;
+
+   if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
+   rcdu->dpad1_source = rcrtc->index;
+   }
+
+   /* Apply the atomic update. */
+   drm_atomic_helper_commit_modeset_disables(dev, old_state);
+   drm_atomic_helper_commit_

[PATCH v5 06/10] drm: rcar-du: Move rcar_du_encoders_init()

2022-07-27 Thread Biju Das

RZ/G2L supports only DSI and DPI. Add rcar_du_encoders_init() to handle
the pointer to du_output_name(), so that we can share du_encoders_init()
between RCar and RZ/G2L kms drivers.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c |  92 +---
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 100 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |   6 ++
 3 files changed, 108 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index ed8d14701178..7586520e1871 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -74,95 +74,6 @@ static const struct drm_mode_config_funcs 
rcar_du_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
 };
 
-static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
-enum rcar_du_output output,
-struct of_endpoint *ep)
-{
-   struct device_node *entity;
-   int ret;
-
-   /* Locate the connected entity and initialize the encoder. */
-   entity = of_graph_get_remote_port_parent(ep->local_node);
-   if (!entity) {
-   dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
-   ep->local_node);
-   return -ENODEV;
-   }
-
-   if (!of_device_is_available(entity)) {
-   dev_dbg(rcdu->dev,
-   "connected entity %pOF is disabled, skipping\n",
-   entity);
-   of_node_put(entity);
-   return -ENODEV;
-   }
-
-   ret = rcar_du_encoder_init(rcdu, output, entity);
-   if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
-   dev_warn(rcdu->dev,
-"failed to initialize encoder %pOF on output %s (%d), 
skipping\n",
-entity, rcar_du_output_name(output), ret);
-
-   of_node_put(entity);
-
-   return ret;
-}
-
-static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
-{
-   struct device_node *np = rcdu->dev->of_node;
-   struct device_node *ep_node;
-   unsigned int num_encoders = 0;
-
-   /*
-* Iterate over the endpoints and create one encoder for each output
-* pipeline.
-*/
-   for_each_endpoint_of_node(np, ep_node) {
-   enum rcar_du_output output;
-   struct of_endpoint ep;
-   unsigned int i;
-   int ret;
-
-   ret = of_graph_parse_endpoint(ep_node, );
-   if (ret < 0) {
-   of_node_put(ep_node);
-   return ret;
-   }
-
-   /* Find the output route corresponding to the port number. */
-   for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
-   if (rcdu->info->routes[i].possible_crtcs &&
-   rcdu->info->routes[i].port == ep.port) {
-   output = i;
-   break;
-   }
-   }
-
-   if (i == RCAR_DU_OUTPUT_MAX) {
-   dev_warn(rcdu->dev,
-"port %u references unexisting output, 
skipping\n",
-ep.port);
-   continue;
-   }
-
-   /* Process the output pipeline. */
-   ret = rcar_du_encoders_init_one(rcdu, output, );
-   if (ret < 0) {
-   if (ret == -EPROBE_DEFER) {
-   of_node_put(ep_node);
-   return ret;
-   }
-
-   continue;
-   }
-
-   num_encoders++;
-   }
-
-   return num_encoders;
-}
-
 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
 {
/*
@@ -462,7 +373,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
}
 
/* Initialize the encoders. */
-   ret = rcar_du_encoders_init(rcdu);
+   ret = rcar_du_encoders_init(rcdu, rcar_du_output_name,
+   rcar_du_encoder_init);
if (ret < 0)
return ret;
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index a1027436cfe3..d41fee590ee4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -517,3 +517,103 @@ rcar_du_lib_mode_cfg_helper_fns(void)
 {
return _du_mode_config_helper;
 }
+
+static int
+rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
+ enum rcar_du_output output,
+ struct of_endpoint *ep,
+

[PATCH v5 07/10] drm: rcar-du: Move rcar_du_properties_init()

2022-07-27 Thread Biju Das

Move rcar_du_properties_init() to RCar DU kms lib, so that it can be
shared by both RCar and RZ/G2L kms drivers.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 16 
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 16 
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  2 ++
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 7586520e1871..b3ebe694be6e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -74,22 +74,6 @@ static const struct drm_mode_config_funcs 
rcar_du_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
 };
 
-static int rcar_du_properties_init(struct rcar_du_device *rcdu)
-{
-   /*
-* The color key is expressed as an RGB888 triplet stored in a 32-bit
-* integer in XRGB format. Bit 24 is used as a flag to disable (0)
-* or enable source color keying (1).
-*/
-   rcdu->props.colorkey =
-   drm_property_create_range(>ddev, 0, "colorkey",
- 0, 0x01ff);
-   if (rcdu->props.colorkey == NULL)
-   return -ENOMEM;
-
-   return 0;
-}
-
 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
 {
const struct device_node *np = rcdu->dev->of_node;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index d41fee590ee4..a56f3d6db321 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -617,3 +617,19 @@ int rcar_du_encoders_init(struct rcar_du_device *rcdu,
 
return num_encoders;
 }
+
+int rcar_du_properties_init(struct rcar_du_device *rcdu)
+{
+   /*
+* The color key is expressed as an RGB888 triplet stored in a 32-bit
+* integer in XRGB format. Bit 24 is used as a flag to disable (0)
+* or enable source color keying (1).
+*/
+   rcdu->props.colorkey =
+   drm_property_create_range(>ddev, 0, "colorkey",
+ 0, 0x01ff);
+   if (rcdu->props.colorkey == NULL)
+   return -ENOMEM;
+
+   return 0;
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
index 02d6ed5aa154..b04c42bbae5c 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
@@ -52,4 +52,6 @@ int rcar_du_encoders_init(struct rcar_du_device *rcdu,
 enum rcar_du_output output,
 struct device_node *enc_node));
 
+int rcar_du_properties_init(struct rcar_du_device *rcdu);
+
 #endif /* __RCAR_DU_KMS_LIB_H__ */
-- 
2.25.1

[PATCH v5 09/10] dt-bindings: display: Document Renesas RZ/G2L DU bindings

2022-07-27 Thread Biju Das

The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).

The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timings
− Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
− Supports Progressive
− Input data format (from VSPD): RGB888, RGB666
− Output data format: same as Input data format
− Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
− Supporting WXGA (1280 pixels x 800 lines) for Parallel Output

This patch document DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
---
v4->v5:
 * Added Rb tag from Rob.
v3->v4:
 * Changed compatible name from renesas,du-r9a07g044->renesas,r9a07g044-du
 * started using same compatible for RZ/G2{L,LC}
v3: New patch
---
 .../bindings/display/renesas,rzg2l-du.yaml| 124 ++
 1 file changed, 124 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml 
b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
new file mode 100644
index ..7626043debd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+  - Laurent Pinchart 
+  - Biju Das 
+
+description: |
+  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+  and RZ/V2L SoCs.
+
+properties:
+  compatible:
+enum:
+  - renesas,r9a07g044-du # RZ/G2{L,LC}
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Main clock
+  - description: Register access clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: aclk
+  - const: pclk
+  - const: vclk
+
+  resets:
+maxItems: 1
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+description: |
+  The connections to the DU output video ports are modeled using the OF
+  graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+  The number of ports and their assignment are model-dependent. Each port
+  shall have a single endpoint.
+
+patternProperties:
+  "^port@[0-1]$":
+$ref: /schemas/graph.yaml#/properties/port
+unevaluatedProperties: false
+
+required:
+  - port@0
+
+unevaluatedProperties: false
+
+  renesas,vsps:
+$ref: "/schemas/types.yaml#/definitions/phandle-array"
+items:
+  items:
+- description: phandle to VSP instance that serves the DU channel
+- description: Channel index identifying the LIF instance in that VSP
+description:
+  A list of phandle and channel index tuples to the VSPs that handle the
+  memory interfaces for the DU channels.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - power-domains
+  - ports
+  - renesas,vsps
+
+additionalProperties: false
+
+examples:
+  # RZ/G2L DU
+  - |
+#include 
+#include 
+
+display@1089 {
+compatible = "renesas,r9a07g044-du";
+reg = <0x1089 0x1>;
+interrupts = ;
+clocks = < CPG_MOD R9A07G044_LCDC_CLK_A>,
+ < CPG_MOD R9A07G044_LCDC_CLK_P>,
+ < CPG_MOD R9A07G044_LCDC_CLK_D>;
+clock-names = "aclk", "pclk", "vclk";
+resets = < R9A07G044_LCDC_RESET_N>;
+power-domains = <>;
+
+renesas,vsps = < 0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+port@1 {
+reg = <1>;
+endpoint {
+};
+};
+};
+};
+
+...
-- 
2.25.1

[PATCH v5 01/10] drm: rcar-du: Move rcar_du_vsp_plane_prepare_fb()

2022-07-27 Thread Biju Das

Move rcar_du_vsp_plane_prepare_fb() to RCar DU vsp lib so that
both RCar and RZ/G2L DU vsp drivers can share this function.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 21 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 21 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  7 +++
 3 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index d192c31a5fe1..72128915a2ff 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -124,27 +124,6 @@ static void rcar_du_vsp_plane_setup(struct 
rcar_du_vsp_plane *plane)
  plane->index, );
 }
 
-static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
-   struct drm_plane_state *state)
-{
-   struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
-   struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
-   int ret;
-
-   /*
-* There's no need to prepare (and unprepare) the framebuffer when the
-* plane is not visible, as it will not be displayed.
-*/
-   if (!state->visible)
-   return 0;
-
-   ret = rcar_du_vsp_map_fb(vsp, state->fb, rstate->sg_tables);
-   if (ret < 0)
-   return ret;
-
-   return drm_gem_plane_helper_prepare_fb(plane, state);
-}
-
 static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
 struct drm_plane_state *state)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index 80da12f1fe71..40d44bf521c0 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -147,6 +147,27 @@ int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct 
drm_framebuffer *fb,
return ret;
 }
 
+int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
+struct drm_plane_state *state)
+{
+   struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
+   struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
+   int ret;
+
+   /*
+* There's no need to prepare (and unprepare) the framebuffer when the
+* plane is not visible, as it will not be displayed.
+*/
+   if (!state->visible)
+   return 0;
+
+   ret = rcar_du_vsp_map_fb(vsp, state->fb, rstate->sg_tables);
+   if (ret < 0)
+   return ret;
+
+   return drm_gem_plane_helper_prepare_fb(plane, state);
+}
+
 void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
  struct sg_table sg_tables[3])
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index abfde19fd1a3..d79cdf7d7316 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -66,6 +66,8 @@ void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct 
drm_framebuffer *fb,
 int rcar_du_lib_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs,
 const struct drm_plane_helper_funcs 
*rcar_du_vsp_plane_helper_funcs);
+int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
+struct drm_plane_state *state);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
@@ -88,6 +90,11 @@ rcar_du_lib_vsp_init(struct rcar_du_vsp *vsp, struct 
device_node *np,
 {
return -ENXIO;
 }
+static inline int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
+  struct drm_plane_state *state)
+{
+   return -ENXIO;
+}
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH v5 08/10] drm: rcar-du: Add rcar_du_lib_vsps_init()

2022-07-27 Thread Biju Das

Add rcar_du_lib_vsps_init() to RCar DU kms lib to handle both
rcar_du_vsp_init() and rzg2l_du_vsp_init().

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 88 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 89 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  5 ++
 3 files changed, 95 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index b3ebe694be6e..73269b7e067e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -74,92 +74,6 @@ static const struct drm_mode_config_funcs 
rcar_du_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
 };
 
-static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
-{
-   const struct device_node *np = rcdu->dev->of_node;
-   const char *vsps_prop_name = "renesas,vsps";
-   struct of_phandle_args args;
-   struct {
-   struct device_node *np;
-   unsigned int crtcs_mask;
-   } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
-   unsigned int vsps_count = 0;
-   unsigned int cells;
-   unsigned int i;
-   int ret;
-
-   /*
-* First parse the DT vsps property to populate the list of VSPs. Each
-* entry contains a pointer to the VSP DT node and a bitmask of the
-* connected DU CRTCs.
-*/
-   ret = of_property_count_u32_elems(np, vsps_prop_name);
-   if (ret < 0) {
-   /* Backward compatibility with old DTBs. */
-   vsps_prop_name = "vsps";
-   ret = of_property_count_u32_elems(np, vsps_prop_name);
-   }
-   cells = ret / rcdu->num_crtcs - 1;
-   if (cells > 1)
-   return -EINVAL;
-
-   for (i = 0; i < rcdu->num_crtcs; ++i) {
-   unsigned int j;
-
-   ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
-  cells, i, );
-   if (ret < 0)
-   goto error;
-
-   /*
-* Add the VSP to the list or update the corresponding existing
-* entry if the VSP has already been added.
-*/
-   for (j = 0; j < vsps_count; ++j) {
-   if (vsps[j].np == args.np)
-   break;
-   }
-
-   if (j < vsps_count)
-   of_node_put(args.np);
-   else
-   vsps[vsps_count++].np = args.np;
-
-   vsps[j].crtcs_mask |= BIT(i);
-
-   /*
-* Store the VSP pointer and pipe index in the CRTC. If the
-* second cell of the 'renesas,vsps' specifier isn't present,
-* default to 0 to remain compatible with older DT bindings.
-*/
-   rcdu->crtcs[i].vsp = >vsps[j];
-   rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
-   }
-
-   /*
-* Then initialize all the VSPs from the node pointers and CRTCs bitmask
-* computed previously.
-*/
-   for (i = 0; i < vsps_count; ++i) {
-   struct rcar_du_vsp *vsp = >vsps[i];
-
-   vsp->index = i;
-   vsp->dev = rcdu;
-
-   ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
-   if (ret < 0)
-   goto error;
-   }
-
-   return 0;
-
-error:
-   for (i = 0; i < ARRAY_SIZE(vsps); ++i)
-   of_node_put(vsps[i].np);
-
-   return ret;
-}
-
 static int rcar_du_cmm_init(struct rcar_du_device *rcdu)
 {
const struct device_node *np = rcdu->dev->of_node;
@@ -331,7 +245,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 
/* Initialize the compositors. */
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
-   ret = rcar_du_vsps_init(rcdu);
+   ret = rcar_du_lib_vsps_init(rcdu, rcar_du_vsp_init);
if (ret < 0)
return ret;
}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index a56f3d6db321..c9fa4d1c78fd 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -633,3 +633,92 @@ int rcar_du_properties_init(struct rcar_du_device *rcdu)
 
return 0;
 }
+
+int rcar_du_lib_vsps_init(struct rcar_du_device *rcdu,
+ int (*rcar_du_vsp_init_fn)(struct rcar_du_vsp *vsp,
+struct device_node *np,
+unsigned int crtcs))
+{
+   const struct device_node *np = rcdu->dev->of_node;
+   const char *vsps_prop_name = "renesas

[PATCH v5 04/10] drm: rcar-du: Add rcar_du_lib_fb_create()

2022-07-27 Thread Biju Das

Move the common code from rcar_du_fb_create->rcar_du_lib_fb_create,
so that rzg2l_du_fb_create() can reuse the common code.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 64 +
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 69 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  4 ++
 3 files changed, 74 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index ea2b7d5f1c23..9d65a7d6d96e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -41,69 +41,7 @@ static struct drm_framebuffer *
 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
  const struct drm_mode_fb_cmd2 *mode_cmd)
 {
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   const struct rcar_du_format_info *format;
-   unsigned int chroma_pitch;
-   unsigned int max_pitch;
-   unsigned int align;
-   unsigned int i;
-
-   format = rcar_du_format_info(mode_cmd->pixel_format);
-   if (format == NULL) {
-   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
-   mode_cmd->pixel_format);
-   return ERR_PTR(-EINVAL);
-   }
-
-   if (rcdu->info->gen < 3) {
-   /*
-* On Gen2 the DU limits the pitch to 4095 pixels and requires
-* buffers to be aligned to a 16 pixels boundary (or 128 bytes
-* on some platforms).
-*/
-   unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
-
-   max_pitch = 4095 * bpp;
-
-   if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
-   align = 128;
-   else
-   align = 16 * bpp;
-   } else {
-   /*
-* On Gen3 the memory interface is handled by the VSP that
-* limits the pitch to 65535 bytes and has no alignment
-* constraint.
-*/
-   max_pitch = 65535;
-   align = 1;
-   }
-
-   if (mode_cmd->pitches[0] & (align - 1) ||
-   mode_cmd->pitches[0] > max_pitch) {
-   dev_dbg(dev->dev, "invalid pitch value %u\n",
-   mode_cmd->pitches[0]);
-   return ERR_PTR(-EINVAL);
-   }
-
-   /*
-* Calculate the chroma plane(s) pitch using the horizontal subsampling
-* factor. For semi-planar formats, the U and V planes are combined, the
-* pitch must thus be doubled.
-*/
-   chroma_pitch = mode_cmd->pitches[0] / format->hsub;
-   if (format->planes == 2)
-   chroma_pitch *= 2;
-
-   for (i = 1; i < format->planes; ++i) {
-   if (mode_cmd->pitches[i] != chroma_pitch) {
-   dev_dbg(dev->dev,
-   "luma and chroma pitches are not compatible\n");
-   return ERR_PTR(-EINVAL);
-   }
-   }
-
-   return drm_gem_fb_create(dev, file_priv, mode_cmd);
+   return rcar_du_lib_fb_create(dev, file_priv, mode_cmd);
 }
 
 /* 
-
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index 6461b99e08dc..d8f778a7b6db 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -392,3 +392,72 @@ int rcar_du_dumb_create(struct drm_file *file, struct 
drm_device *dev,
 
return drm_gem_cma_dumb_create_internal(file, dev, args);
 }
+
+struct drm_framebuffer *
+rcar_du_lib_fb_create(struct drm_device *dev, struct drm_file *file_priv,
+ const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   const struct rcar_du_format_info *format;
+   unsigned int chroma_pitch;
+   unsigned int max_pitch;
+   unsigned int align;
+   unsigned int i;
+
+   format = rcar_du_format_info(mode_cmd->pixel_format);
+   if (format == NULL) {
+   dev_dbg(dev->dev, "unsupported pixel format %08x\n",
+   mode_cmd->pixel_format);
+   return ERR_PTR(-EINVAL);
+   }
+
+   if (rcdu->info->gen < 3) {
+   /*
+* On Gen2 the DU limits the pitch to 4095 pixels and requires
+* buffers to be aligned to a 16 pixels boundary (or 128 bytes
+* on some platforms).
+*/
+   unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
+
+   max_pitch = 4095 * bpp;
+
+   if (rcar_du_needs(rcdu, RCAR_DU_QU

[PATCH v5 03/10] drm: rcar-du: Move rcar_du_vsp_plane_atomic_update()

2022-07-27 Thread Biju Das

Move rcar_du_vsp_plane_atomic_update() to RCar DU vsp lib so that
both RCar and RZ/G2L DU vsp drivers can share this function.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 51 ---
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 51 +++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  6 +++
 3 files changed, 57 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index c9090e581b12..aa63e2d19649 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -88,42 +88,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
-{
-   struct rcar_du_vsp_plane_state *state =
-   to_rcar_vsp_plane_state(plane->plane.state);
-   struct rcar_du_crtc *crtc = to_rcar_crtc(state->state.crtc);
-   struct drm_framebuffer *fb = plane->plane.state->fb;
-   const struct rcar_du_format_info *format;
-   struct vsp1_du_atomic_config cfg = {
-   .pixelformat = 0,
-   .pitch = fb->pitches[0],
-   .alpha = state->state.alpha >> 8,
-   .zpos = state->state.zpos,
-   };
-   unsigned int i;
-
-   cfg.src.left = state->state.src.x1 >> 16;
-   cfg.src.top = state->state.src.y1 >> 16;
-   cfg.src.width = drm_rect_width(>state.src) >> 16;
-   cfg.src.height = drm_rect_height(>state.src) >> 16;
-
-   cfg.dst.left = state->state.dst.x1;
-   cfg.dst.top = state->state.dst.y1;
-   cfg.dst.width = drm_rect_width(>state.dst);
-   cfg.dst.height = drm_rect_height(>state.dst);
-
-   for (i = 0; i < state->format->planes; ++i)
-   cfg.mem[i] = sg_dma_address(state->sg_tables[i].sgl)
-  + fb->offsets[i];
-
-   format = rcar_du_format_info(state->format->fourcc);
-   cfg.pixelformat = format->v4l2;
-
-   vsp1_du_atomic_update(plane->vsp->vsp, crtc->vsp_pipe,
- plane->index, );
-}
-
 static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
  struct drm_atomic_state *state)
 {
@@ -135,21 +99,6 @@ static int rcar_du_vsp_plane_atomic_check(struct drm_plane 
*plane,
>format);
 }
 
-static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
-   struct drm_atomic_state *state)
-{
-   struct drm_plane_state *old_state = 
drm_atomic_get_old_plane_state(state, plane);
-   struct drm_plane_state *new_state = 
drm_atomic_get_new_plane_state(state, plane);
-   struct rcar_du_vsp_plane *rplane = to_rcar_vsp_plane(plane);
-   struct rcar_du_crtc *crtc = to_rcar_crtc(old_state->crtc);
-
-   if (new_state->visible)
-   rcar_du_vsp_plane_setup(rplane);
-   else if (old_state->crtc)
-   vsp1_du_atomic_update(rplane->vsp->vsp, crtc->vsp_pipe,
- rplane->index, NULL);
-}
-
 static const struct drm_plane_helper_funcs rcar_du_vsp_plane_helper_funcs = {
.prepare_fb = rcar_du_vsp_plane_prepare_fb,
.cleanup_fb = rcar_du_vsp_plane_cleanup_fb,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index 9062837e68da..97f8ac22b582 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -85,6 +85,42 @@ static const u32 rcar_du_vsp_formats[] = {
DRM_FORMAT_YVU444,
 };
 
+static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
+{
+   struct rcar_du_vsp_plane_state *state =
+   to_rcar_vsp_plane_state(plane->plane.state);
+   struct rcar_du_crtc *crtc = to_rcar_crtc(state->state.crtc);
+   struct drm_framebuffer *fb = plane->plane.state->fb;
+   const struct rcar_du_format_info *format;
+   struct vsp1_du_atomic_config cfg = {
+   .pixelformat = 0,
+   .pitch = fb->pitches[0],
+   .alpha = state->state.alpha >> 8,
+   .zpos = state->state.zpos,
+   };
+   unsigned int i;
+
+   cfg.src.left = state->state.src.x1 >> 16;
+   cfg.src.top = state->state.src.y1 >> 16;
+   cfg.src.width = drm_rect_width(>state.src) >> 16;
+   cfg.src.height = drm_rect_height(>state.src) >> 16;
+
+   cfg.dst.left = state->state.dst.x1;
+   cfg.dst.top = state->state.dst.y1;
+   cfg.dst.width = drm_rect_width(>state.dst);
+   cfg.dst.height = drm_rect_height(>state.dst);
+
+   for (i = 0; i < state-

[PATCH v5 02/10] drm: rcar-du: Move rcar_du_vsp_plane_cleanup_fb()

2022-07-27 Thread Biju Das

Move rcar_du_vsp_plane_cleanup_fb() to RCar DU vsp lib so that
it can be shared by both RCar and RZ/G2L DU vsp drivers.

Signed-off-by: Biju Das 
---
v5:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 12 
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 12 
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  6 ++
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index 72128915a2ff..c9090e581b12 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -124,18 +124,6 @@ static void rcar_du_vsp_plane_setup(struct 
rcar_du_vsp_plane *plane)
  plane->index, );
 }
 
-static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
-struct drm_plane_state *state)
-{
-   struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
-   struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
-
-   if (!state->visible)
-   return;
-
-   rcar_du_vsp_unmap_fb(vsp, state->fb, rstate->sg_tables);
-}
-
 static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
  struct drm_atomic_state *state)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index 40d44bf521c0..9062837e68da 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -181,6 +181,18 @@ void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct 
drm_framebuffer *fb,
}
 }
 
+void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+   struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(state);
+   struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
+
+   if (!state->visible)
+   return;
+
+   rcar_du_vsp_unmap_fb(vsp, state->fb, rstate->sg_tables);
+}
+
 static struct drm_plane_state *
 rcar_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index d79cdf7d7316..094ada022fe5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -68,6 +68,8 @@ int rcar_du_lib_vsp_init(struct rcar_du_vsp *vsp, struct 
device_node *np,
 const struct drm_plane_helper_funcs 
*rcar_du_vsp_plane_helper_funcs);
 int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
 struct drm_plane_state *state);
+void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
+ struct drm_plane_state *state);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
@@ -95,6 +97,10 @@ static inline int rcar_du_vsp_plane_prepare_fb(struct 
drm_plane *plane,
 {
return -ENXIO;
 }
+static inline void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
+   struct drm_plane_state *state)
+{
+}
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH v5 00/10] Add RZ/G2L Display support

2022-07-27 Thread Biju Das

LINEAR
 UYVY:  LINEAR
 YUYV:  LINEAR
 YVYU:  LINEAR
 NV12:  LINEAR
 NV21:  LINEAR
 NV16:  LINEAR
 NV61:  LINEAR
 YU12:  LINEAR
 YV12:  LINEAR
 YU16:  LINEAR
 YV16:  LINEAR
 YU24:  LINEAR
 YV24:  LINEAR
38 alpha:
flags: range
values: 0 65535
value: 65535
39 zpos:
flags: range
values: 0 1
value: 1

Frame buffers:
id  sizepitch

Biju Das (10):
  drm: rcar-du: Move rcar_du_vsp_plane_prepare_fb()
  drm: rcar-du: Move rcar_du_vsp_plane_cleanup_fb()
  drm: rcar-du: Move rcar_du_vsp_plane_atomic_update()
  drm: rcar-du: Add rcar_du_lib_fb_create()
  drm: rcar-du: Add rcar_du_lib_mode_cfg_helper_fns()
  drm: rcar-du: Move rcar_du_encoders_init()
  drm: rcar-du: Move rcar_du_properties_init()
  drm: rcar-du: Add rcar_du_lib_vsps_init()
  dt-bindings: display: Document Renesas RZ/G2L DU bindings
  drm: rcar-du: Add RZ/G2L DU Support

 .../bindings/display/renesas,rzg2l-du.yaml| 124 +++
 drivers/gpu/drm/rcar-du/Kconfig   |  17 +-
 drivers/gpu/drm/rcar-du/Makefile  |  13 +
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 304 +---
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 330 
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  20 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  84 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c |  84 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  19 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c   | 718 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h   |  26 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c| 206 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h|  20 +
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c|  26 +
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h|  19 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c| 158 
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h|  17 +
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h   |  67 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c|  82 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h|  29 +
 20 files changed, 1978 insertions(+), 385 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h


base-commit: c90598c998da48a0499cb401c28d40e1f073733e
-- 
2.25.1

RE: [PATCH 02/10] drm: rcar-du: Add encoder lib support

2022-07-27 Thread Biju Das

Hi,

> Subject: Re: [PATCH 02/10] drm: rcar-du: Add encoder lib support
> 
> Hi Biju,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> wget
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross
> W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/rcar-du/
> 
> If you fix the issue, kindly add following tag where applicable
> Reported-by: kernel test robot 
> 
> All warnings (new ones prefixed by >>):
> 
> >> drivers/gpu/drm/rcar-du/rcar_du_encoder.c:20:5: warning: no previous
> >> prototype for 'rcar_du_encoder_init' [-Wmissing-prototypes]
>   20 | int rcar_du_encoder_init(struct rcar_du_device *rcdu,
>  | ^~~~

This warning message is because of the below header file 
change in rcar_du_encoder.c.

rcar_du_encoder.h-> "rcar_du_encoder_lib.h" 

Will fix this in next version, based on the feedback for the remaining
patches

Cheers,
Biju

> 
> vim +/rcar_du_encoder_init +20 drivers/gpu/drm/rcar-du/rcar_du_encoder.c
> 
> 4bf8e1962f91eed drivers/gpu/drm/rcar-du/rcar_du_lvds.cLaurent
> Pinchart 2013-06-19  15
> 6978f123776594b drivers/gpu/drm/rcar-du/rcar_du_encoder.c Laurent
> Pinchart 2013-06-15  16  /* 
> -
> 6978f123776594b drivers/gpu/drm/rcar-du/rcar_du_encoder.c Laurent
> Pinchart 2013-06-15  17   * Encoder
> 6978f123776594b drivers/gpu/drm/rcar-du/rcar_du_encoder.c Laurent
> Pinchart 2013-06-15  18   */
> 6978f123776594b drivers/gpu/drm/rcar-du/rcar_du_encoder.c Laurent
> Pinchart 2013-06-15  19 6978f123776594b drivers/gpu/drm/rcar-
> du/rcar_du_encoder.c Laurent Pinchart 2013-06-15 @20  int
> rcar_du_encoder_init(struct rcar_du_device *rcdu,
>

[PATCH 10/10] drm: rcar-du: Add rcar_du_lib_vsp_init()

2022-07-26 Thread Biju Das

RZ/G2L does not have plane registers as well as it uses different
CRTC. The below functions are SoC specific
 * rcar_du_crtc_finish_page_flip()
 * __rcar_du_plane_setup
 * __rcar_du_plane_atomic_check
All other function can be handled in common code. This patch introduces
rcar_du_lib_vsp_init() to share common_init, vsp_formats and vsp_plane_funcs().

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 151 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 155 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  10 ++
 3 files changed, 167 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index 18e16097cf53..03f032ef48ad 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -89,34 +89,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-static const u32 rcar_du_vsp_formats[] = {
-   DRM_FORMAT_RGB332,
-   DRM_FORMAT_ARGB,
-   DRM_FORMAT_XRGB,
-   DRM_FORMAT_ARGB1555,
-   DRM_FORMAT_XRGB1555,
-   DRM_FORMAT_RGB565,
-   DRM_FORMAT_BGR888,
-   DRM_FORMAT_RGB888,
-   DRM_FORMAT_BGRA,
-   DRM_FORMAT_BGRX,
-   DRM_FORMAT_ARGB,
-   DRM_FORMAT_XRGB,
-   DRM_FORMAT_UYVY,
-   DRM_FORMAT_YUYV,
-   DRM_FORMAT_YVYU,
-   DRM_FORMAT_NV12,
-   DRM_FORMAT_NV21,
-   DRM_FORMAT_NV16,
-   DRM_FORMAT_NV61,
-   DRM_FORMAT_YUV420,
-   DRM_FORMAT_YVU420,
-   DRM_FORMAT_YUV422,
-   DRM_FORMAT_YVU422,
-   DRM_FORMAT_YUV444,
-   DRM_FORMAT_YVU444,
-};
-
 static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
 {
struct rcar_du_vsp_plane_state *state =
@@ -219,128 +191,9 @@ static const struct drm_plane_helper_funcs 
rcar_du_vsp_plane_helper_funcs = {
.atomic_update = rcar_du_vsp_plane_atomic_update,
 };
 
-static struct drm_plane_state *
-rcar_du_vsp_plane_atomic_duplicate_state(struct drm_plane *plane)
-{
-   struct rcar_du_vsp_plane_state *copy;
-
-   if (WARN_ON(!plane->state))
-   return NULL;
-
-   copy = kzalloc(sizeof(*copy), GFP_KERNEL);
-   if (copy == NULL)
-   return NULL;
-
-   __drm_atomic_helper_plane_duplicate_state(plane, >state);
-
-   return >state;
-}
-
-static void rcar_du_vsp_plane_atomic_destroy_state(struct drm_plane *plane,
-  struct drm_plane_state 
*state)
-{
-   __drm_atomic_helper_plane_destroy_state(state);
-   kfree(to_rcar_vsp_plane_state(state));
-}
-
-static void rcar_du_vsp_plane_reset(struct drm_plane *plane)
-{
-   struct rcar_du_vsp_plane_state *state;
-
-   if (plane->state) {
-   rcar_du_vsp_plane_atomic_destroy_state(plane, plane->state);
-   plane->state = NULL;
-   }
-
-   state = kzalloc(sizeof(*state), GFP_KERNEL);
-   if (state == NULL)
-   return;
-
-   __drm_atomic_helper_plane_reset(plane, >state);
-}
-
-static const struct drm_plane_funcs rcar_du_vsp_plane_funcs = {
-   .update_plane = drm_atomic_helper_update_plane,
-   .disable_plane = drm_atomic_helper_disable_plane,
-   .reset = rcar_du_vsp_plane_reset,
-   .destroy = drm_plane_cleanup,
-   .atomic_duplicate_state = rcar_du_vsp_plane_atomic_duplicate_state,
-   .atomic_destroy_state = rcar_du_vsp_plane_atomic_destroy_state,
-};
-
-static void rcar_du_vsp_cleanup(struct drm_device *dev, void *res)
-{
-   struct rcar_du_vsp *vsp = res;
-   unsigned int i;
-
-   for (i = 0; i < vsp->num_planes; ++i) {
-   struct rcar_du_vsp_plane *plane = >planes[i];
-
-   drm_plane_cleanup(>plane);
-   }
-
-   kfree(vsp->planes);
-
-   put_device(vsp->vsp);
-}
-
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs)
 {
-   struct rcar_du_device *rcdu = vsp->dev;
-   struct platform_device *pdev;
-   unsigned int num_crtcs = hweight32(crtcs);
-   unsigned int num_planes;
-   unsigned int i;
-   int ret;
-
-   /* Find the VSP device and initialize it. */
-   pdev = of_find_device_by_node(np);
-   if (!pdev)
-   return -ENXIO;
-
-   vsp->vsp = >dev;
-
-   ret = drmm_add_action_or_reset(>ddev, rcar_du_vsp_cleanup, vsp);
-   if (ret < 0)
-   return ret;
-
-   ret = vsp1_du_init(vsp->vsp);
-   if (ret < 0)
-   return ret;
-
-   num_planes = rcdu->info->num_rpf;
-
-   vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
-   if (!vsp->planes)
-   return -ENOMEM;
-
-   for (i = 0; i < num_planes; ++i) {
-   enum drm_plane_type

[PATCH 07/10] drm: rcar-du: Move vsp rcar_du_vsp_{map,unmap}_fb()

2022-07-26 Thread Biju Das

Move vsp rcar_du_vsp_{map,unmap}_fb() to RCar DU VSP lib.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 75 ---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 15 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 75 +++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 15 +
 4 files changed, 90 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index becc587c5169..18e16097cf53 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -153,68 +153,6 @@ static void rcar_du_vsp_plane_setup(struct 
rcar_du_vsp_plane *plane)
  plane->index, );
 }
 
-int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
-  struct sg_table sg_tables[3])
-{
-   struct rcar_du_device *rcdu = vsp->dev;
-   unsigned int i, j;
-   int ret;
-
-   for (i = 0; i < fb->format->num_planes; ++i) {
-   struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
-   struct sg_table *sgt = _tables[i];
-
-   if (gem->sgt) {
-   struct scatterlist *src;
-   struct scatterlist *dst;
-
-   /*
-* If the GEM buffer has a scatter gather table, it has
-* been imported from a dma-buf and has no physical
-* address as it might not be physically contiguous.
-* Copy the original scatter gather table to map it to
-* the VSP.
-*/
-   ret = sg_alloc_table(sgt, gem->sgt->orig_nents,
-GFP_KERNEL);
-   if (ret)
-   goto fail;
-
-   src = gem->sgt->sgl;
-   dst = sgt->sgl;
-   for (j = 0; j < gem->sgt->orig_nents; ++j) {
-   sg_set_page(dst, sg_page(src), src->length,
-   src->offset);
-   src = sg_next(src);
-   dst = sg_next(dst);
-   }
-   } else {
-   ret = dma_get_sgtable(rcdu->dev, sgt, gem->vaddr,
- gem->paddr, gem->base.size);
-   if (ret)
-   goto fail;
-   }
-
-   ret = vsp1_du_map_sg(vsp->vsp, sgt);
-   if (ret) {
-   sg_free_table(sgt);
-   goto fail;
-   }
-   }
-
-   return 0;
-
-fail:
-   while (i--) {
-   struct sg_table *sgt = _tables[i];
-
-   vsp1_du_unmap_sg(vsp->vsp, sgt);
-   sg_free_table(sgt);
-   }
-
-   return ret;
-}
-
 static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane,
struct drm_plane_state *state)
 {
@@ -236,19 +174,6 @@ static int rcar_du_vsp_plane_prepare_fb(struct drm_plane 
*plane,
return drm_gem_plane_helper_prepare_fb(plane, state);
 }
 
-void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
- struct sg_table sg_tables[3])
-{
-   unsigned int i;
-
-   for (i = 0; i < fb->format->num_planes; ++i) {
-   struct sg_table *sgt = _tables[i];
-
-   vsp1_du_unmap_sg(vsp->vsp, sgt);
-   sg_free_table(sgt);
-   }
-}
-
 static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
 struct drm_plane_state *state)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 5bc539562255..a6ddeb6d57ea 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -16,10 +16,6 @@
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
-  struct sg_table sg_tables[3]);
-void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
- struct sg_table sg_tables[3]);
 #else
 static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
   struct device_node *np,
@@ -28,17 +24,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
-struct drm_fra

[PATCH 09/10] drm: rcar-du: Move rcar_du_gem_prime_import_sg_table()

2022-07-26 Thread Biju Das

Move rcar_du_gem_prime_import_sg_table() to RCar DU KMS lib.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 45 ---
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  4 --
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 45 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  4 ++
 4 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index c05a1925755f..ea2b7d5f1c23 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -37,51 +37,6 @@
  * Frame buffer
  */
 
-static const struct drm_gem_object_funcs rcar_du_gem_funcs = {
-   .free = drm_gem_cma_object_free,
-   .print_info = drm_gem_cma_object_print_info,
-   .get_sg_table = drm_gem_cma_object_get_sg_table,
-   .vmap = drm_gem_cma_object_vmap,
-   .mmap = drm_gem_cma_object_mmap,
-   .vm_ops = _gem_cma_vm_ops,
-};
-
-struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
-   struct dma_buf_attachment *attach,
-   struct sg_table *sgt)
-{
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   struct drm_gem_cma_object *cma_obj;
-   struct drm_gem_object *gem_obj;
-   int ret;
-
-   if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
-   return drm_gem_cma_prime_import_sg_table(dev, attach, sgt);
-
-   /* Create a CMA GEM buffer. */
-   cma_obj = kzalloc(sizeof(*cma_obj), GFP_KERNEL);
-   if (!cma_obj)
-   return ERR_PTR(-ENOMEM);
-
-   gem_obj = _obj->base;
-   gem_obj->funcs = _du_gem_funcs;
-
-   drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
-   cma_obj->map_noncoherent = false;
-
-   ret = drm_gem_create_mmap_offset(gem_obj);
-   if (ret) {
-   drm_gem_object_release(gem_obj);
-   kfree(cma_obj);
-   return ERR_PTR(ret);
-   }
-
-   cma_obj->paddr = 0;
-   cma_obj->sgt = sgt;
-
-   return gem_obj;
-}
-
 static struct drm_framebuffer *
 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
  const struct drm_mode_fb_cmd2 *mode_cmd)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
index e335a47ec72f..9bf7d94615ff 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
@@ -14,8 +14,4 @@
 
 int rcar_du_modeset_init(struct rcar_du_device *rcdu);
 
-struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
-   struct dma_buf_attachment *attach,
-   struct sg_table *sgt);
-
 #endif /* __RCAR_DU_KMS_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index cc86524a826a..6461b99e08dc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -327,6 +327,51 @@ const struct rcar_du_format_info *rcar_du_format_info(u32 
fourcc)
  * Frame buffer
  */
 
+static const struct drm_gem_object_funcs rcar_du_gem_funcs = {
+   .free = drm_gem_cma_object_free,
+   .print_info = drm_gem_cma_object_print_info,
+   .get_sg_table = drm_gem_cma_object_get_sg_table,
+   .vmap = drm_gem_cma_object_vmap,
+   .mmap = drm_gem_cma_object_mmap,
+   .vm_ops = _gem_cma_vm_ops,
+};
+
+struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
+   struct dma_buf_attachment *attach,
+   struct sg_table *sgt)
+{
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   struct drm_gem_cma_object *cma_obj;
+   struct drm_gem_object *gem_obj;
+   int ret;
+
+   if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
+   return drm_gem_cma_prime_import_sg_table(dev, attach, sgt);
+
+   /* Create a CMA GEM buffer. */
+   cma_obj = kzalloc(sizeof(*cma_obj), GFP_KERNEL);
+   if (!cma_obj)
+   return ERR_PTR(-ENOMEM);
+
+   gem_obj = _obj->base;
+   gem_obj->funcs = _du_gem_funcs;
+
+   drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
+   cma_obj->map_noncoherent = false;
+
+   ret = drm_gem_create_mmap_offset(gem_obj);
+   if (ret) {
+   drm_gem_object_release(gem_obj);
+   kfree(cma_obj);
+   return ERR_PTR(ret);
+   }
+
+   cma_obj->paddr = 0;
+   cma_obj->sgt = sgt;
+
+   return gem_obj;
+}
+
 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
struct drm_mode_create_dumb *args)
 {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
index 15505b51c849..5f45a369bb88 100644
--- a

[PATCH 08/10] drm: rcar-du: Move rcar_du_dumb_create()

2022-07-26 Thread Biju Das

Move rcar_du_dumb_create() to RCar DU KMS lib.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 21 ---
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  3 ---
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 25 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  3 +++
 4 files changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index b63808025578..c05a1925755f 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -82,27 +82,6 @@ struct drm_gem_object 
*rcar_du_gem_prime_import_sg_table(struct drm_device *dev,
return gem_obj;
 }
 
-int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
-   struct drm_mode_create_dumb *args)
-{
-   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-   unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-   unsigned int align;
-
-   /*
-* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
-* but the R8A7790 DU seems to require a 128 bytes pitch alignment.
-*/
-   if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
-   align = 128;
-   else
-   align = 16 * args->bpp / 8;
-
-   args->pitch = roundup(min_pitch, align);
-
-   return drm_gem_cma_dumb_create_internal(file, dev, args);
-}
-
 static struct drm_framebuffer *
 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
  const struct drm_mode_fb_cmd2 *mode_cmd)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
index 58a66dc355bf..e335a47ec72f 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.h
@@ -14,9 +14,6 @@
 
 int rcar_du_modeset_init(struct rcar_du_device *rcdu);
 
-int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
-   struct drm_mode_create_dumb *args);
-
 struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device 
*dev,
struct dma_buf_attachment *attach,
struct sg_table *sgt);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
index 40ccd8635c34..cc86524a826a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
@@ -322,3 +322,28 @@ const struct rcar_du_format_info *rcar_du_format_info(u32 
fourcc)
 
return NULL;
 }
+
+/* 
-
+ * Frame buffer
+ */
+
+int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
+   struct drm_mode_create_dumb *args)
+{
+   struct rcar_du_device *rcdu = to_rcar_du_device(dev);
+   unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+   unsigned int align;
+
+   /*
+* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
+* but the R8A7790 DU seems to require a 128 bytes pitch alignment.
+*/
+   if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
+   align = 128;
+   else
+   align = 16 * args->bpp / 8;
+
+   args->pitch = roundup(min_pitch, align);
+
+   return drm_gem_cma_dumb_create_internal(file, dev, args);
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
index 5fa488abb681..15505b51c849 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
@@ -32,4 +32,7 @@ struct rcar_du_format_info {
 
 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc);
 
+int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
+   struct drm_mode_create_dumb *args);
+
 #endif /* __RCAR_DU_KMS_LIB_H__ */
-- 
2.25.1

[PATCH 02/10] drm: rcar-du: Add encoder lib support

2022-07-26 Thread Biju Das

Add RCar DU encoder lib support by moving rcar_du_encoder_count_ports()
and rcar_du_encoder_funcs to the lib file and added
rcar_du_encoder_funcs() to share the common code between RCar and
RZ/G2L DU encoder drivers.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/Kconfig   |   5 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 120 +--
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  14 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c | 138 ++
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h |  30 
 6 files changed, 181 insertions(+), 128 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 3e59c7c213f5..684462c40ae3 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -71,3 +71,8 @@ config DRM_RCAR_WRITEBACK
bool
default y if ARM64
depends on DRM_RCAR_DU
+
+config DRM_RCAR_LIB
+   bool
+   default y
+   depends on DRM_RCAR_DU
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 14a3fa88cc0b..651da6a7ad67 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,6 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
+rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c 
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index 60d6be78323b..0aa3108d9483 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -2,137 +2,25 @@
 /*
  * R-Car Display Unit Encoder
  *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2022 Renesas Electronics Corporation
  *
  * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
  */
 
 #include 
 #include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
 
 #include "rcar_du_drv.h"
-#include "rcar_du_encoder.h"
-#include "rcar_du_kms.h"
-#include "rcar_lvds.h"
+#include "rcar_du_encoder_lib.h"
 
 /* 
-
  * Encoder
  */
 
-static unsigned int rcar_du_encoder_count_ports(struct device_node *node)
-{
-   struct device_node *ports;
-   struct device_node *port;
-   unsigned int num_ports = 0;
-
-   ports = of_get_child_by_name(node, "ports");
-   if (!ports)
-   ports = of_node_get(node);
-
-   for_each_child_of_node(ports, port) {
-   if (of_node_name_eq(port, "port"))
-   num_ports++;
-   }
-
-   of_node_put(ports);
-
-   return num_ports;
-}
-
-static const struct drm_encoder_funcs rcar_du_encoder_funcs = {
-};
-
 int rcar_du_encoder_init(struct rcar_du_device *rcdu,
 enum rcar_du_output output,
 struct device_node *enc_node)
 {
-   struct rcar_du_encoder *renc;
-   struct drm_connector *connector;
-   struct drm_bridge *bridge;
-   int ret;
-
-   /*
-* Locate the DRM bridge from the DT node. For the DPAD outputs, if the
-* DT node has a single port, assume that it describes a panel and
-* create a panel bridge.
-*/
-   if ((output == RCAR_DU_OUTPUT_DPAD0 ||
-output == RCAR_DU_OUTPUT_DPAD1) &&
-   rcar_du_encoder_count_ports(enc_node) == 1) {
-   struct drm_panel *panel = of_drm_find_panel(enc_node);
-
-   if (IS_ERR(panel))
-   return PTR_ERR(panel);
-
-   bridge = devm_drm_panel_bridge_add_typed(rcdu->dev, panel,
-
DRM_MODE_CONNECTOR_DPI);
-   if (IS_ERR(bridge))
-   return PTR_ERR(bridge);
-   } else {
-   bridge = of_drm_find_bridge(enc_node);
-   if (!bridge)
-   return -EPROBE_DEFER;
-
-   if (output == RCAR_DU_OUTPUT_LVDS0 ||
-   output == RCAR_DU_OUTPUT_LVDS1)
-   rcdu->lvds[output - RCAR_DU_OUTPUT_LVDS0] = bridge;
-   }
-
-   /*
-* Create and initialize the encoder. On Gen3, skip the LVDS1 output if
-* the LVDS1 encoder is used as a companion for LVDS0 in dual-link
-* mode, or any LVDS output if it isn't connected. The latter may happen
-* on D3 or E3 as the LVDS encoders are needed to provide the pixel
-* clock to the DU, even when the LVDS outputs are

[PATCH 06/10] drm: rcar-du: Move rcar_du_vsp_atomic_flush()

2022-07-26 Thread Biju Das

Move rcar_du_vsp_atomic_flush() to RCar DU vsp lib.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 13 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h |  2 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 13 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  2 ++
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index dfcdf9285512..becc587c5169 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -89,19 +89,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
-{
-   struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
-   struct rcar_du_crtc_state *state;
-
-   state = to_rcar_crtc_state(crtc->crtc.state);
-   cfg.crc = state->crc;
-
-   rcar_du_writeback_setup(crtc, );
-
-   vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, );
-}
-
 static const u32 rcar_du_vsp_formats[] = {
DRM_FORMAT_RGB332,
DRM_FORMAT_ARGB,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 842205b4e16e..5bc539562255 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -16,7 +16,6 @@
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
   struct sg_table sg_tables[3]);
 void rcar_du_vsp_unmap_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
@@ -29,7 +28,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
 struct drm_framebuffer *fb,
 struct sg_table sg_tables[3])
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index 116a50cb0f70..dc51368044c1 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -43,3 +43,16 @@ void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
 {
vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
 }
+
+void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
+{
+   struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
+   struct rcar_du_crtc_state *state;
+
+   state = to_rcar_crtc_state(crtc->crtc.state);
+   cfg.crc = state->crc;
+
+   rcar_du_writeback_setup(crtc, );
+
+   vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, );
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index 024ebd5f98aa..a2045c51c496 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -58,9 +58,11 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 #ifdef CONFIG_DRM_RCAR_VSP
 void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
+void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
+static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH 03/10] drm: rcar-du: Add kms lib support

2022-07-26 Thread Biju Das

Add RCar DU kms lib support by moving rcar_du_format_infos table and
rcar_du_format_infos() to the lib file to share the common code between
RCar and RZ/G2L DU KMS drivers.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/Makefile  |   3 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 290 ---
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  24 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 324 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  35 +++
 5 files changed, 363 insertions(+), 313 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 651da6a7ad67..bcded406b16c 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,7 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
-rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o
+rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o \
+ rcar_du_kms_lib.o
 
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 761451ee5263..b63808025578 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -33,296 +33,6 @@
 #include "rcar_du_vsp.h"
 #include "rcar_du_writeback.h"
 
-/* 
-
- * Format helpers
- */
-
-static const struct rcar_du_format_info rcar_du_format_infos[] = {
-   {
-   .fourcc = DRM_FORMAT_RGB565,
-   .v4l2 = V4L2_PIX_FMT_RGB565,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_ARGB1555,
-   .v4l2 = V4L2_PIX_FMT_ARGB555,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_XRGB1555,
-   .v4l2 = V4L2_PIX_FMT_XRGB555,
-   .bpp = 16,
-   .planes = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_XRGB,
-   .v4l2 = V4L2_PIX_FMT_XBGR32,
-   .bpp = 32,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_RGB888,
-   }, {
-   .fourcc = DRM_FORMAT_ARGB,
-   .v4l2 = V4L2_PIX_FMT_ABGR32,
-   .bpp = 32,
-   .planes = 1,
-   .hsub = 1,
-   .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
-   .edf = PnDDCR4_EDF_ARGB,
-   }, {
-   .fourcc = DRM_FORMAT_UYVY,
-   .v4l2 = V4L2_PIX_FMT_UYVY,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_YUYV,
-   .v4l2 = V4L2_PIX_FMT_YUYV,
-   .bpp = 16,
-   .planes = 1,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV12,
-   .v4l2 = V4L2_PIX_FMT_NV12M,
-   .bpp = 12,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV21,
-   .v4l2 = V4L2_PIX_FMT_NV21M,
-   .bpp = 12,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   }, {
-   .fourcc = DRM_FORMAT_NV16,
-   .v4l2 = V4L2_PIX_FMT_NV16M,
-   .bpp = 16,
-   .planes = 2,
-   .hsub = 2,
-   .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
-   .edf = PnDDCR4_EDF_NONE,
-   },
-   /*
-* The following formats are not supported on Gen2 and thus have no
-* associated .pnmr or .edf settings.
-*/
-   {
-   .fourcc = DRM_FORMAT_RGB332,
-   .v4l2 = V4L2_PIX_FMT_RGB332,
-   .bpp = 8,
-   .planes = 1,
-   .hsub = 1,
-   }, {
-   .fourcc =

[PATCH 01/10] drm: rcar-du: Add RZ/G2L reset and clocks to struct rcar_du_crtc

2022-07-26 Thread Biju Das

Add RZ/G2L reset and clocks to struct rcar_du_crtc, so that
we can share and optimize the common code between RCar and
RZ/G2L driver using RCar DU library.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h 
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index d0f38a8b3561..d2164ee6e599 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
@@ -43,6 +43,8 @@ struct rcar_du_vsp;
  * @vsp: VSP feeding video to this CRTC
  * @vsp_pipe: index of the VSP pipeline feeding video to this CRTC
  * @writeback: the writeback connector
+ * @rzg2l_clocks: the bus, main and video clock
+ * @rstc: reset controller
  */
 struct rcar_du_crtc {
struct drm_crtc crtc;
@@ -73,6 +75,14 @@ struct rcar_du_crtc {
unsigned int sources_count;
 
struct drm_writeback_connector writeback;
+
+   /* RZ/G2L specific */
+   struct reset_control *rstc;
+   struct {
+   struct clk *aclk;
+   struct clk *pclk;
+   struct clk *dclk;
+   } rzg2l_clocks;
 };
 
 #define to_rcar_crtc(c)container_of(c, struct rcar_du_crtc, 
crtc)
-- 
2.25.1

[PATCH 05/10] drm: rcar-du: Move rcar_du_vsp_atomic_begin()

2022-07-26 Thread Biju Das

Move rcar_du_vsp_atomic_begin() to RCar DU VSP lib.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 -
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 5 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 2 ++
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index b84d120b6ce0..dfcdf9285512 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -89,11 +89,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
-{
-   vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
-}
-
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc)
 {
struct vsp1_du_atomic_pipe_config cfg = { { 0, } };
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 04d1c1416b16..842205b4e16e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -16,7 +16,6 @@
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
   struct sg_table sg_tables[3]);
@@ -30,7 +29,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
 struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
index 045ec55e87f5..116a50cb0f70 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -38,3 +38,8 @@ void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
 {
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL);
 }
+
+void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
+{
+   vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
index 6c0aff046cdf..024ebd5f98aa 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h
@@ -57,8 +57,10 @@ to_rcar_vsp_plane_state(struct drm_plane_state *state)
 
 #ifdef CONFIG_DRM_RCAR_VSP
 void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
+void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 #else
 static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
+static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 #endif
 
 #endif /* __RCAR_DU_VSP_LIB_H__ */
-- 
2.25.1

[PATCH 04/10] drm: rcar-du: Add vsp lib support

2022-07-26 Thread Biju Das

Add RCar DU vsp lib support by moving rcar_du_vsp_disable()
to the lib file so that same function can be used by both
RCar and RZ/G2L DU VSP drivers.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/rcar-du/Kconfig   |  5 ++
 drivers/gpu/drm/rcar-du/Makefile  |  1 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  5 --
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 47 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 40 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h | 64 +++
 6 files changed, 111 insertions(+), 51 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 684462c40ae3..f8e1341be5f8 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -76,3 +76,8 @@ config DRM_RCAR_LIB
bool
default y
depends on DRM_RCAR_DU
+
+config DRM_RCAR_VSP_LIB
+   bool
+   default y
+   depends on DRM_RCAR_VSP
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index bcded406b16c..cee1f69926db 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -10,6 +10,7 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_LIB) += rcar_du_encoder_lib.o \
  rcar_du_kms_lib.o
 
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
+rcar-du-drm-$(CONFIG_DRM_RCAR_VSP_LIB) += rcar_du_vsp_lib.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
 obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index dbc68cdabcff..b84d120b6ce0 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -89,11 +89,6 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, );
 }
 
-void rcar_du_vsp_disable(struct rcar_du_crtc *crtc)
-{
-   vsp1_du_setup_lif(crtc->vsp->vsp, crtc->vsp_pipe, NULL);
-}
-
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc)
 {
vsp1_du_atomic_begin(crtc->vsp->vsp, crtc->vsp_pipe);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
index 67630f0b6599..04d1c1416b16 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h
@@ -10,56 +10,12 @@
 #ifndef __RCAR_DU_VSP_H__
 #define __RCAR_DU_VSP_H__
 
-#include 
-
-struct drm_framebuffer;
-struct rcar_du_format_info;
-struct rcar_du_vsp;
-struct sg_table;
-
-struct rcar_du_vsp_plane {
-   struct drm_plane plane;
-   struct rcar_du_vsp *vsp;
-   unsigned int index;
-};
-
-struct rcar_du_vsp {
-   unsigned int index;
-   struct device *vsp;
-   struct rcar_du_device *dev;
-   struct rcar_du_vsp_plane *planes;
-   unsigned int num_planes;
-};
-
-static inline struct rcar_du_vsp_plane *to_rcar_vsp_plane(struct drm_plane *p)
-{
-   return container_of(p, struct rcar_du_vsp_plane, plane);
-}
-
-/**
- * struct rcar_du_vsp_plane_state - Driver-specific plane state
- * @state: base DRM plane state
- * @format: information about the pixel format used by the plane
- * @sg_tables: scatter-gather tables for the frame buffer memory
- */
-struct rcar_du_vsp_plane_state {
-   struct drm_plane_state state;
-
-   const struct rcar_du_format_info *format;
-   struct sg_table sg_tables[3];
-};
-
-static inline struct rcar_du_vsp_plane_state *
-to_rcar_vsp_plane_state(struct drm_plane_state *state)
-{
-   return container_of(state, struct rcar_du_vsp_plane_state, state);
-}
+#include "rcar_du_vsp_lib.h"
 
 #ifdef CONFIG_DRM_RCAR_VSP
 int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 unsigned int crtcs);
 void rcar_du_vsp_enable(struct rcar_du_crtc *crtc);
-void rcar_du_vsp_disable(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc);
 void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc);
 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
@@ -74,7 +30,6 @@ static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp,
return -ENXIO;
 }
 static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { };
-static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { };
 static inline void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc) { };
 static inline int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
new file mode 100644
index ..045ec55e87f5
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+

[PATCH 00/10] Add RCar DU lib support

2022-07-26 Thread Biju Das

Adding RCar DU lib support(Encoder, vsp and KMS) proved that it can save
50% code saving on RZ/G2L compared to patch series [1].

The current patchset contains just movement of codes with some trivial changes.

The subsequent patch series will have more additions to vsp and kms library.
There is also plan to add library support for DU DRM and DU CRTC
(Not yet ready/tested), which will further increase the common code.

Current patch set + subsequent patch sets are tested on both RZ/G2M, RZ/G1N and
RZ/G2L.

[1] 
https://lore.kernel.org/linux-renesas-soc/os0pr01mb59226ce75483ad2b96833b3786...@os0pr01mb5922.jpnprd01.prod.outlook.com/T/#t

Biju Das (10):
  drm: rcar-du: Add RZ/G2L reset and clocks to struct rcar_du_crtc
  drm: rcar-du: Add encoder lib support
  drm: rcar-du: Add kms lib support
  drm: rcar-du: Add vsp lib support
  drm: rcar-du: Move rcar_du_vsp_atomic_begin()
  drm: rcar-du: Move rcar_du_vsp_atomic_flush()
  drm: rcar-du: Move vsp rcar_du_vsp_{map,unmap}_fb()
  drm: rcar-du: Move rcar_du_dumb_create()
  drm: rcar-du: Move rcar_du_gem_prime_import_sg_table()
  drm: rcar-du: Add rcar_du_lib_vsp_init()

 drivers/gpu/drm/rcar-du/Kconfig   |  10 +
 drivers/gpu/drm/rcar-du/Makefile  |   4 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h|  10 +
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 120 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  14 +-
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c | 138 ++
 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h |  30 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 356 
 drivers/gpu/drm/rcar-du/rcar_du_kms.h |  31 +-
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c | 394 ++
 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h |  42 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 249 +--
 drivers/gpu/drm/rcar-du/rcar_du_vsp.h |  66 +--
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c | 288 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h |  93 +
 15 files changed, 1020 insertions(+), 825 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_encoder_lib.h
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_kms_lib.h
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.c
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vsp_lib.h

-- 
2.25.1

RE: [PATCH v4 0/2] Add RZ/G2L Display support

2022-07-26 Thread Biju Das

t; 595659554e5631324e5632314e563136
> 4e563631595531325956313259553136
> 595631365955323459563234
> ff01
> 
> in_formats blob decoded:
>  RGB8:  LINEAR
>  AR12:  LINEAR
>  XR12:  LINEAR
>  AR15:  LINEAR
>      XR15:  LINEAR
>  RG16:  LINEAR
>  BG24:  LINEAR
>  RG24:  LINEAR
>  BA24:  LINEAR
>  BX24:  LINEAR
>  AR24:  LINEAR
>  XR24:  LINEAR
>  UYVY:  LINEAR
>  YUYV:  LINEAR
>  YVYU:  LINEAR
>  NV12:  LINEAR
>  NV21:  LINEAR
>  NV16:  LINEAR
>  NV61:  LINEAR
>  YU12:  LINEAR
>  YV12:  LINEAR
>  YU16:  LINEAR
>  YV16:  LINEAR
>  YU24:  LINEAR
>  YV24:  LINEAR
> 37 alpha:
> flags: range
> values: 0 65535
> value: 65535
> 38 zpos:
> flags: range
> values: 1 1
> value: 1
> 
> Frame buffers:
> id  sizepitch
> 
> 
> Biju Das (2):
>   dt-bindings: display: Document Renesas RZ/G2L DU bindings
>   drm: rcar-du: Add RZ/G2L DU Support
> 
>  .../bindings/display/renesas,rzg2l-du.yaml| 124 +++
>  drivers/gpu/drm/rcar-du/Kconfig   |  16 +-
>  drivers/gpu/drm/rcar-du/Makefile  |   9 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c   | 718 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h   | 100 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.c| 192 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.h|  99 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c| 114 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h|  29 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_kms.c| 756 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_kms.h|  43 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_regs.h   |  67 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c| 422 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h|  93 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c  | 250 ++
> drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h  |  42 +
>  16 files changed, 3073 insertions(+), 1 deletion(-)  create mode 100644
> Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h
> 
> --
> 2.25.1

RE: [PATCH v4 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-07-24 Thread Biju Das

Hi Sam,

Thanks for the feedback.

> Subject: Re: [PATCH v4 1/2] dt-bindings: display: bridge: Document
> RZ/G2L MIPI DSI TX bindings
> 
> Hi Biju,
> 
> On Fri, Jul 22, 2022 at 08:19:23PM +0100, Biju Das wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Rob Herring 
> > Reviewed-by: Laurent Pinchart 
> > Reviewed-by: Geert Uytterhoeven 
> > ---
> > v3->v4:
> >  * No change.
> > v2->v3:
> >  * Added Rb tag from Geert and Laurent
> >  * Fixed the typo "Receive" -> "transmit"
> >  * Added accepible values for data-lanes
> >  * Sorted Header file in the example
> >  * Added SoC specific compaible along with generic one.
> > v1->v2:
> >  * Added full path for dsi-controller.yaml
> >  * Modeled DSI + D-PHY as single block and updated reg property
> >  * Fixed typo D_PHY->D-PHY
> >  * Updated description
> >  * Added interrupts and interrupt-names and updated the example
> > RFC->v1:
> >  * Added a ref to dsi-controller.yaml.
> > RFC:-
> >  *
> > ---
> >  .../bindings/display/bridge/renesas,dsi.yaml  | 182
> > ++
> >  1 file changed, 182 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > new file mode 100644
> > index ..131d5b63ec4f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,182 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +title: Renesas RZ/G2L MIPI DSI Encoder
> > +
> > +maintainers:
> > +  - Biju Das 
> > +
> > +description: |
> > +  This binding describes the MIPI DSI encoder embedded in the Renesas
> > +  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
> > +with
> > +  up to four data lanes.
> > +
> > +allOf:
> > +  - $ref: /schemas/display/dsi-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +items:
> > +  - enum:
> > +  - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
> > +  - const: renesas,rzg2l-mipi-dsi
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +items:
> > +  - description: Sequence operation channel 0 interrupt
> > +  - description: Sequence operation channel 1 interrupt
> > +  - description: Video-Input operation channel 1 interrupt
> > +  - description: DSI Packet Receive interrupt
> > +  - description: DSI Fatal Error interrupt
> > +  - description: DSI D-PHY PPI interrupt
> > +  - description: Debug interrupt
> This is an awful lot of interrupts.
> Is this really individual interrupts or status bits in a single
> interrupt? If it is the latter then there should be only one interrupt
> defined.

It is individual interrupts.

As per the hw manual,  these interrupts have dedicated IRQ lines
as below.

dsi_int_seq0 174 SPI 142 IRQ 142 Level
dsi_int_seq1 175 SPI 143 IRQ 143 Level
dsi_int_vin1 176 SPI 144 IRQ 144 Level
dsi_int_rcv 177 SPI 145 IRQ 145 Level
dsi_int_ferr 178 SPI 146 IRQ 146 Level
dsi_int_ppi 179 SPI 147 IRQ 147 Level
dsi_int_debug 180 SPI 148 IRQ 148 Level

Cheers,
Biju

[PATCH v4 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-07-22 Thread Biju Das

This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

Signed-off-by: Biju Das 
---
v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable()
v2->v3:
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Rework based on dt-binding change (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 712 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 4 files changed, 873 insertions(+)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index f6e6a6d5d987..3e59c7c213f5 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
help
  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
 
+config DRM_RZG2L_MIPI_DSI
+   tristate "RZ/G2L MIPI DSI Encoder Support"
+   depends on DRM_BRIDGE && OF
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_MIPI_DSI
+   help
+ Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
+
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index e7275b5e7ec8..14a3fa88cc0b 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_DRM_RCAR_DW_HDMI)+= 
rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
+
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
 DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
new file mode 100644
index ..e81b7a64ea10
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L MIPI DSI Encoder Driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rzg2l_mipi_dsi_regs.h"
+
+struct rzg2l_mipi_dsi {
+   struct device *dev;
+   void __iomem *mmio;
+
+   struct reset_control *rstc;
+   struct reset_control *arstc;
+   struct reset_control *prstc;
+
+   struct mipi_dsi_host host;
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+
+   struct clk *vclk;
+
+   enum mipi_dsi_pixel_format format;
+   unsigned int num_data_lanes;
+   unsigned int lanes;
+   unsigned long mode_flags;
+};
+
+static inline struct rzg2l_mipi_dsi *
+bridge_to_rzg2l_mipi_dsi(str

[PATCH v4 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-07-22 Thread Biju Das

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
---
v3->v4:
 * No change.
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
RFC->v1:
 * Added a ref to dsi-controller.yaml.
RFC:-
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..131d5b63ec4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
+  up to four data lanes.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+  - const: renesas,rzg2l-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: Sequence operation channel 0 interrupt
+  - description: Sequence operation channel 1 interrupt
+  - description: Video-Input operation channel 1 interrupt
+  - description: DSI Packet Receive interrupt
+  - description: DSI Fatal Error interrupt
+  - description: DSI D-PHY PPI interrupt
+  - description: Debug interrupt
+
+  interrupt-names:
+items:
+  - const: seq0
+  - const: seq1
+  - const: vin1
+  - const: rcv
+  - const: ferr
+  - const: ppi
+  - const: debug
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D-PHY Escape mode transmit clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+description: array of physical DSI data lane indexes.
+minItems: 1
+items:
+  - const: 1
+  - const: 2
+  - const: 3
+  - const: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+dsi0: dsi@1085 {
+compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
+reg = <0x1085 0x2>;
+interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+interrupt-names = "seq0", "seq1", "vin

[PATCH v4 0/2] Add RZ/G2L DSI driver

2022-07-22 Thread Biju Das

This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

This unit supports MIPI Alliance Specification for Display Serial Interface 
(DSI)
Specification. This unit provides a solution for transmitting MIPI DSI compliant
digital video and packets. Normative References are below.
* MIPI Alliance Specification for Display Serial Interface Version 1.3.1
* MIPI Alliance Specification for D-PHY Version 2.1

The following are key features of this unit.

* 1 channel
* The number of Lane: 4-lane
* Support up to Full HD (1920 × 1080), 60 fps (RGB888)
* Maximum Bandwidth: 1.5 Gbps per lane
* Support Output Data Format: RGB666 / RGB888

v3->v4:
 * Updated error handling in rzg2l_mipi_dsi_startup() and 
rzg2l_mipi_dsi_atomic_enable().
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
 * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added a ref to dsi-controller.yaml.
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/

Biju Das (2):
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver

 .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 712 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 5 files changed, 1055 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.25.1

[PATCH v4 2/2] drm: rcar-du: Add RZ/G2L DU Support

2022-07-22 Thread Biju Das

The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support blending of two picture layers and
raster operations (ROPs).

The DU part is similar to RCar like DU is connected to VSPD, so most of
the framework related functionality is based on RCar DU.

Signed-off-by: Biju Das 
---
v3->v4:
 * Removed rzg2l_du_group.h and struct rzg2l_du_group
 * Renamed __rzg2l_du_group_start_stop->rzg2l_du_start_stop
 * Removed rzg2l_du_group_restart
 * Updated rzg2l_du_crtc_set_display_timing
 * Removed mode_valid callback.
 * Updated rzg2l_du_crtc_create() parameters
 * Updated compatible
 * Removed RZG2L_DU_MAX_GROUPS
v3:
 * New patch after removing all the indirections and by adding
   new DRM driver.
---
 drivers/gpu/drm/rcar-du/Kconfig  |  16 +-
 drivers/gpu/drm/rcar-du/Makefile |   9 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c  | 718 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h  | 100 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c   | 192 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h   |  99 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c   | 114 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h   |  29 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c   | 756 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h   |  43 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h  |  67 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c   | 422 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h   |  93 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c | 250 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h |  42 ++
 15 files changed, 2949 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 3e59c7c213f5..5fb00e8dc2e7 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -11,6 +11,19 @@ config DRM_RCAR_DU
  Choose this option if you have an R-Car chipset.
  If M is selected the module will be called rcar-du-drm.
 
+config DRM_RZG2L_DU
+   tristate "DRM Support for RZ/G2L DU"
+   depends on DRM && OF
+   depends on ARM || ARM64
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_KMS_HELPER
+   select DRM_GEM_CMA_HELPER
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you have an RZ/G2L chipset.
+ If M is selected the module will be called rzg2l-du-drm.
+
+
 config DRM_RCAR_USE_CMM
bool "R-Car DU Color Management Module (CMM) Support"
depends on DRM_RCAR_DU
@@ -62,8 +75,9 @@ config DRM_RZG2L_MIPI_DSI
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
-   depends on DRM_RCAR_DU
+   depends on DRM_RCAR_DU || DRM_RZG2L_DU
depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+   depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && 
DRM_RZG2L_DU=m)
help
  Enable support to expose the R-Car VSP Compositor as KMS planes.
 
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 14a3fa88cc0b..460ff9aeba6c 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,15 +6,24 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
+rzg2l-du-drm-y := rzg2l_du_crtc.o \
+ rzg2l_du_drv.o \
+ rzg2l_du_encoder.o \
+ rzg2l_du_kms.o \
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP)+= rzg2l_du_vsp.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rzg2l_du_writeback.o
+
 obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
 obj-$(CONFIG_DRM_RCAR_DU)  += rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)

[PATCH v4 1/2] dt-bindings: display: Document Renesas RZ/G2L DU bindings

2022-07-22 Thread Biju Das

The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).

The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timings
− Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
− Supports Progressive
− Input data format (from VSPD): RGB888, RGB666
− Output data format: same as Input data format
− Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
− Supporting WXGA (1280 pixels x 800 lines) for Parallel Output

This patch document DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das 
---
v3->v4:
 * Changed compatible name from renesas,du-r9a07g044->renesas,r9a07g044-du
 * started using same compatible for RZ/G2{L,LC}
v3: New patch
---
 .../bindings/display/renesas,rzg2l-du.yaml| 124 ++
 1 file changed, 124 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml 
b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
new file mode 100644
index ..7626043debd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+  - Laurent Pinchart 
+  - Biju Das 
+
+description: |
+  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+  and RZ/V2L SoCs.
+
+properties:
+  compatible:
+enum:
+  - renesas,r9a07g044-du # RZ/G2{L,LC}
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Main clock
+  - description: Register access clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: aclk
+  - const: pclk
+  - const: vclk
+
+  resets:
+maxItems: 1
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+description: |
+  The connections to the DU output video ports are modeled using the OF
+  graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+  The number of ports and their assignment are model-dependent. Each port
+  shall have a single endpoint.
+
+patternProperties:
+  "^port@[0-1]$":
+$ref: /schemas/graph.yaml#/properties/port
+unevaluatedProperties: false
+
+required:
+  - port@0
+
+unevaluatedProperties: false
+
+  renesas,vsps:
+$ref: "/schemas/types.yaml#/definitions/phandle-array"
+items:
+  items:
+- description: phandle to VSP instance that serves the DU channel
+- description: Channel index identifying the LIF instance in that VSP
+description:
+  A list of phandle and channel index tuples to the VSPs that handle the
+  memory interfaces for the DU channels.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - power-domains
+  - ports
+  - renesas,vsps
+
+additionalProperties: false
+
+examples:
+  # RZ/G2L DU
+  - |
+#include 
+#include 
+
+display@1089 {
+compatible = "renesas,r9a07g044-du";
+reg = <0x1089 0x1>;
+interrupts = ;
+clocks = < CPG_MOD R9A07G044_LCDC_CLK_A>,
+ < CPG_MOD R9A07G044_LCDC_CLK_P>,
+ < CPG_MOD R9A07G044_LCDC_CLK_D>;
+clock-names = "aclk", "pclk", "vclk";
+resets = < R9A07G044_LCDC_RESET_N>;
+power-domains = <>;
+
+renesas,vsps = < 0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+port@1 {
+reg = <1>;
+endpoint {
+};
+};
+};
+};
+
+...
-- 
2.25.1

[PATCH v4 0/2] Add RZ/G2L Display support

2022-07-22 Thread Biju Das

  010080005247423841523132
58523132415231355852313552473136
42473234524732344241323442583234
41523234585232345559565959555956
595659554e5631324e5632314e563136
4e563631595531325956313259553136
595631365955323459563234
ff01

in_formats blob decoded:
 RGB8:  LINEAR
 AR12:  LINEAR
 XR12:  LINEAR
 AR15:  LINEAR
 XR15:  LINEAR
 RG16:  LINEAR
 BG24:  LINEAR
 RG24:  LINEAR
 BA24:  LINEAR
 BX24:  LINEAR
 AR24:  LINEAR
 XR24:  LINEAR
 UYVY:  LINEAR
 YUYV:  LINEAR
 YVYU:  LINEAR
 NV12:  LINEAR
 NV21:  LINEAR
 NV16:  LINEAR
 NV61:  LINEAR
 YU12:  LINEAR
 YV12:  LINEAR
 YU16:  LINEAR
 YV16:  LINEAR
 YU24:  LINEAR
 YV24:  LINEAR
34 zpos:
flags: immutable range
values: 0 0
value: 0
35  0   0   0,0 0,0 0   0x0001
  formats: RGB8 AR12 XR12 AR15 XR15 RG16 BG24 RG24 BA24 BX24 AR24 XR24 UYVY 
YUYV YVYU NV12 NV21 NV16 NV61 YU12 YV12 YU16 YV16 YU24 YV24
  props:
8 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 0
17 FB_ID:
flags: object
value: 0
18 IN_FENCE_FD:
flags: signed range
values: -1 2147483647
value: -1
20 CRTC_ID:
flags: object
value: 0
13 CRTC_X:
flags: signed range
values: -2147483648 2147483647
value: 0
14 CRTC_Y:
flags: signed range
values: -2147483648 2147483647
value: 0
15 CRTC_W:
flags: range
values: 0 2147483647
value: 0
16 CRTC_H:
flags: range
values: 0 2147483647
value: 0
9 SRC_X:
flags: range
values: 0 4294967295
value: 0
10 SRC_Y:
flags: range
values: 0 4294967295
value: 0
11 SRC_W:
flags: range
values: 0 4294967295
value: 0
12 SRC_H:
flags: range
values: 0 4294967295
value: 0
30 IN_FORMATS:
flags: immutable blob
blobs:

value:
010019001800
010080005247423841523132
58523132415231355852313552473136
42473234524732344241323442583234
41523234585232345559565959555956
595659554e5631324e5632314e563136
4e563631595531325956313259553136
595631365955323459563234
ff01

in_formats blob decoded:
 RGB8:  LINEAR
 AR12:  LINEAR
 XR12:  LINEAR
 AR15:  LINEAR
 XR15:  LINEAR
 RG16:  LINEAR
 BG24:  LINEAR
 RG24:  LINEAR
 BA24:  LINEAR
 BX24:  LINEAR
 AR24:  LINEAR
 XR24:  LINEAR
 UYVY:  LINEAR
 YUYV:  LINEAR
 YVYU:  LINEAR
 NV12:  LINEAR
 NV21:  LINEAR
 NV16:  LINEAR
 NV61:  LINEAR
 YU12:  LINEAR
 YV12:  LINEAR
 YU16:  LINEAR
 YV16:  LINEAR
 YU24:  LINEAR
 YV24:  LINEAR
37 alpha:
flags: range
values: 0 65535
value: 65535
38 zpos:
flags: range
values: 1 1
value: 1

Frame bu

RE: [PATCH v3 0/2] Add RZ/G2L DSI driver

2022-07-14 Thread Biju Das

Hi David and Laurent,

Gentle Ping.

Are you happy with this series?

Cheers,
Biju


> Subject: RE: [PATCH v3 0/2] Add RZ/G2L DSI driver
> 
> Hi All,
> 
> Gentle ping.
> 
> Are you ok with this patch series? Please let me know.
> 
> Cheers,
> Biju
> 
> > Subject: [PATCH v3 0/2] Add RZ/G2L DSI driver
> >
> > This patch series aims to support the MIPI DSI encoder found in the
> > RZ/G2L SoC. It currently supports DSI mode only.
> >
> > This unit supports MIPI Alliance Specification for Display Serial
> > Interface
> > (DSI) Specification. This unit provides a solution for transmitting
> > MIPI DSI compliant digital video and packets. Normative References are
> below.
> > * MIPI Alliance Specification for Display Serial Interface Version
> > 1.3.1
> > * MIPI Alliance Specification for D-PHY Version 2.1
> >
> > The following are key features of this unit.
> >
> > * 1 channel
> > * The number of Lane: 4-lane
> > * Support up to Full HD (1920 × 1080), 60 fps (RGB888)
> > * Maximum Bandwidth: 1.5 Gbps per lane
> > * Support Output Data Format: RGB666 / RGB888
> >
> > v2->v3:
> >  * Added Rb tag from Geert and Laurent for the binding patch.
> >  * Fixed the typo "Receive" -> "transmit"
> >  * Added accepible values for data-lanes
> >  * Sorted Header file in the example
> >  * Added SoC specific compaible along with generic one.
> >  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function
> > instead
> >of the memory pointer
> >  * Fixed the comment in rzg2l_mipi_dsi_startup()
> >  * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
> >  * DRM bridge parameter initialization moved to probe
> >  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
> >  * Inserted the missing blank lane after return in probe()
> >  * Added missing MODULE_DEVICE_TABLE
> >  * Added include linux/bits.h in header file
> >  * Fixed various macros in header file.
> >  * Reorder the make file for DSI, so that it is no more dependent
> >on RZ/G2L DU patch series.
> > v1->v2:
> >  * Added full path for dsi-controller.yaml
> >  * Modeled DSI + D-PHY as single block and updated reg property
> >  * Fixed typo D_PHY->D-PHY
> >  * Updated description
> >  * Added interrupts and interrupt-names and updated the example
> >  * Driver rework based on dt-binding changes (DSI + D-PHY) as single
> > block
> >  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> >and rzg2l_mipi_dsi_link_write
> >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > RFC->v1:
> >  * Added a ref to dsi-controller.yaml.
> >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> >and dropped DRM as it is implied by DRM_BRIDGE
> >  * Used devm_reset_control_get_exclusive() for reset handle
> >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> >  * Added error check for pm, using pm_runtime_resume_and_get() instead
> of
> >pm_runtime_get_sync()
> >  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> >  * Avoided read-modify-write stopping hsclock
> >  * Used devm_platform_ioremap_resource for resource allocation
> >  * Removed unnecessary assert call from probe and remove.
> >  * wrap the line after the PTR_ERR() in probe()
> >  * Updated reset failure messages in probe
> >  * Fixed the typo arstc->prstc
> >  * Made hex constants to lower case.
> > RFC:
> >  *
> >
> > Biju Das (2):
> >   dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
> >   drm: rcar-du: Add RZ/G2L DSI driver
> >
> >  .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
> >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> >  drivers/gpu/drm/rcar-du/Makefile  |   2 +
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
> >  5 files changed, 1033 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> >
> > --
> > 2.25.1

RE: [PATCH v3 4/4] drm: rcar-du: Add RZ/G2L DU Support

2022-06-07 Thread Biju Das

Hi All,

Gentle ping. Are we happy with this patch?

I need to post next version based on some additions in the latest
HW manual. Before that, if there is any feedback I can incorporate
the same.

Please let me know.

Cheers,
Biju

> Subject: [PATCH v3 4/4] drm: rcar-du: Add RZ/G2L DU Support
> 
> The LCD controller is composed of Frame Compression Processor (FCPVD),
> Video Signal Processor (VSPD), and Display Unit (DU).
> 
> It has DPI/DSI interfaces and supports a maximum resolution of 1080p
> along with 2 RPFs to support blending of two picture layers and
> raster operations (ROPs).
> 
> The DU part is similar to RCar like DU is connected to VSPD, so most of
> the framework related functionality is based on RCar DU.
> 
> Signed-off-by: Biju Das 
> ---
> v3:
>  * New patch after removing all the indirections and by adding
>new DRM driver.
> ---
>  drivers/gpu/drm/rcar-du/Kconfig  |  16 +-
>  drivers/gpu/drm/rcar-du/Makefile |   9 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c  | 745 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h  | 104 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.c   | 192 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.h   | 102 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c   | 113 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h   |  29 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_group.h |  32 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_kms.c   | 782 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_kms.h   |  43 +
>  drivers/gpu/drm/rcar-du/rzg2l_du_regs.h  |  64 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c   | 420 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h   |  93 +++
>  drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c | 247 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h |  42 +
>  16 files changed, 3032 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_group.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h
> 
> diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-
> du/Kconfig
> index 3e59c7c213f5..5fb00e8dc2e7 100644
> --- a/drivers/gpu/drm/rcar-du/Kconfig
> +++ b/drivers/gpu/drm/rcar-du/Kconfig
> @@ -11,6 +11,19 @@ config DRM_RCAR_DU
> Choose this option if you have an R-Car chipset.
> If M is selected the module will be called rcar-du-drm.
> 
> +config DRM_RZG2L_DU
> + tristate "DRM Support for RZ/G2L DU"
> + depends on DRM && OF
> + depends on ARM || ARM64
> + depends on ARCH_RENESAS || COMPILE_TEST
> + select DRM_KMS_HELPER
> + select DRM_GEM_CMA_HELPER
> + select VIDEOMODE_HELPERS
> + help
> +   Choose this option if you have an RZ/G2L chipset.
> +   If M is selected the module will be called rzg2l-du-drm.
> +
> +
>  config DRM_RCAR_USE_CMM
>   bool "R-Car DU Color Management Module (CMM) Support"
>   depends on DRM_RCAR_DU
> @@ -62,8 +75,9 @@ config DRM_RZG2L_MIPI_DSI
>  config DRM_RCAR_VSP
>   bool "R-Car DU VSP Compositor Support" if ARM
>   default y if ARM64
> - depends on DRM_RCAR_DU
> + depends on DRM_RCAR_DU || DRM_RZG2L_DU
>   depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 &&
> DRM_RCAR_DU=m)
> + depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 &&
> DRM_RZG2L_DU=m)
>   help
> Enable support to expose the R-Car VSP Compositor as KMS planes.
> 
> diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-
> du/Makefile
> index 14a3fa88cc0b..460ff9aeba6c 100644
> --- a/drivers/gpu/drm/rcar-du/Makefile
> +++ b/drivers/gpu/drm/rcar-du/Makefile
> @@ -6,15 +6,24 @@ rcar-du-drm-y := rcar_du_crtc.o \
>rcar_du_kms.o \
>rcar_du_plane.o \
> 
> +rzg2l-du-drm-y := rzg2l_du_crtc.o \
> +   rzg2l_du_drv.o \
> +   rzg2l_du_encoder.o \
> +   rzg

RE: [PATCH v3 3/4] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

2022-06-07 Thread Biju Das

Hi All,

Gentle ping. Are we happy with this patch?

Since RZ/G2L is using separate drm driver,
I can drop this patch, if needed.

Please let me know.

Cheers,
Biju

> Subject: [PATCH v3 3/4] drm: rcar-du: Add num_rpf to struct
> rcar_du_device_info
> 
> Number of RPF's VSP is different on R-Car and RZ/G2L  R-Car Gen3 -> 5
> RPFs  R-Car Gen2 -> 4 RPFs  RZ/G2L -> 2 RPFs
> 
> Add num_rpf to struct rcar_du_device_info to support later SoC without
> any code changes.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Laurent Pinchart 
> ---
> v2->v3:
>  * Added Rb tag from Laurent.
>  * Fixed the comment "max num"->"num"
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +
> drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++  drivers/gpu/drm/rcar-
> du/rcar_du_vsp.c |  6 +-
>  3 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 957ea97541d5..1bc7325aa356 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -55,6 +55,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@ -
> 77,6 +78,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
>   .port = 1,
>   },
>   },
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@ -
> 104,6 +106,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
>   .port = 2,
>   },
>   },
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@ -
> 133,6 +136,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(1),
>  };
> 
> @@ -163,6 +167,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(1),
>  };
> 
> @@ -190,6 +195,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
>   },
>   },
>   .num_lvds = 2,
> + .num_rpf = 4,
>   .lvds_clk_mask =  BIT(1) | BIT(0),
>  };
> 
> @@ -220,6 +226,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(1),
>  };
> 
> @@ -272,6 +279,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
>   },
>   },
>   .num_lvds = 2,
> + .num_rpf = 4,
>  };
> 
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -297,6 +305,7
> @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@ -
> 317,6 +326,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
>   .port = 1,
>   },
>   },
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@ -
> 340,6 +350,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
>   .port = 1,
>   },
>   },
> + .num_rpf = 4,
>  };
> 
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@ -
> 373,6 +384,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(2) | BIT(1),
>  };
> 
> @@ -403,6 +415,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(1),
>  };
> 
> @@ -433,6 +446,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>   .dpll_mask =  BIT(1),
>  };
> 
> @@ -459,6 +473,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
>   },
>   },
>   .num_lvds = 1,
> + .num_rpf = 5,
>  };
> 
>  static const struct rcar_du_device_info rcar_du_r8a77

RE: [PATCH v3 0/2] Add RZ/G2L DSI driver

2022-05-31 Thread Biju Das

Hi All,

Gentle ping.

Are you ok with this patch series? Please let me know.

Cheers,
Biju

> Subject: [PATCH v3 0/2] Add RZ/G2L DSI driver
> 
> This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI mode only.
> 
> This unit supports MIPI Alliance Specification for Display Serial Interface
> (DSI) Specification. This unit provides a solution for transmitting MIPI
> DSI compliant digital video and packets. Normative References are below.
> * MIPI Alliance Specification for Display Serial Interface Version 1.3.1
> * MIPI Alliance Specification for D-PHY Version 2.1
> 
> The following are key features of this unit.
> 
> * 1 channel
> * The number of Lane: 4-lane
> * Support up to Full HD (1920 × 1080), 60 fps (RGB888)
> * Maximum Bandwidth: 1.5 Gbps per lane
> * Support Output Data Format: RGB666 / RGB888
> 
> v2->v3:
>  * Added Rb tag from Geert and Laurent for the binding patch.
>  * Fixed the typo "Receive" -> "transmit"
>  * Added accepible values for data-lanes
>  * Sorted Header file in the example
>  * Added SoC specific compaible along with generic one.
>  * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function
> instead
>of the memory pointer
>  * Fixed the comment in rzg2l_mipi_dsi_startup()
>  * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
>  * DRM bridge parameter initialization moved to probe
>  * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
>  * Inserted the missing blank lane after return in probe()
>  * Added missing MODULE_DEVICE_TABLE
>  * Added include linux/bits.h in header file
>  * Fixed various macros in header file.
>  * Reorder the make file for DSI, so that it is no more dependent
>on RZ/G2L DU patch series.
> v1->v2:
>  * Added full path for dsi-controller.yaml
>  * Modeled DSI + D-PHY as single block and updated reg property
>  * Fixed typo D_PHY->D-PHY
>  * Updated description
>  * Added interrupts and interrupt-names and updated the example
>  * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
>  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
>  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
>and rzg2l_mipi_dsi_link_write
>  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> RFC->v1:
>  * Added a ref to dsi-controller.yaml.
>  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
>and dropped DRM as it is implied by DRM_BRIDGE
>  * Used devm_reset_control_get_exclusive() for reset handle
>  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
>  * Added error check for pm, using pm_runtime_resume_and_get() instead of
>pm_runtime_get_sync()
>  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
>  * Avoided read-modify-write stopping hsclock
>  * Used devm_platform_ioremap_resource for resource allocation
>  * Removed unnecessary assert call from probe and remove.
>  * wrap the line after the PTR_ERR() in probe()
>  * Updated reset failure messages in probe
>  * Fixed the typo arstc->prstc
>  * Made hex constants to lower case.
> RFC:
>  *
> 
> Biju Das (2):
>   dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
>   drm: rcar-du: Add RZ/G2L DSI driver
> 
>  .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
>  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
>  drivers/gpu/drm/rcar-du/Makefile  |   2 +
>  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
>  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
>  5 files changed, 1033 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> 
> --
> 2.25.1

RE: [PATCH v2] drm: rcar-du: Fix Alpha blending issue on Gen3

2022-05-17 Thread Biju Das

Hi Kieran,

> Subject: Re: [PATCH v2] drm: rcar-du: Fix Alpha blending issue on Gen3
> 
> Quoting Biju Das (2022-04-26 09:41:57)
> > From: LUU HOAI 
> >
> > As per R-Car-Gen3_Common_OPC_Customer_Notifications_V30.1.pdf,
> > unexpected image output(such as incorrect colors or planes being
> > invisible) can happen on the below conditions, as PnALPHAR register is
> > not initialized by reset.
> >
> > When alpha blending (PpMRm.PpSPIM=0b101) is performed and:
> > •two Planes are enabled on any DUn (n=0,1,2,3)
> > oDSPRn= 0x 0031 or 0x 0013
> > •or DU0 and DU1 is used for display at the same time
> > oDSPR0= 0x 0001 and DSPR1= 0x 0003
> > oDSPR0= 0x 0003 and DSPR1= 0x 0001
> > •or DU2 and DU3(H3 Only) is used for display at the same time
> > oDSPR2= 0x 0001 and DSPR3= 0x 0003
> > oDSPR2= 0x 0003 and DSPR3= 0x 0001
> >
> > This patch set PnALPHAR register to 0 to avoid this issue.
> >
> > Signed-off-by: LUU HOAI 
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * Updated commit description
> >  * Updated the code comments
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > index f214a8b6cfd3..aa80c44dd8d7 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > @@ -510,6 +510,18 @@ static void
> > rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
> >
> > rcar_du_plane_write(rgrp, index, PnDDCR4,
> > state->format->edf | PnDDCR4_CODE);
> > +
> > +   /*
> > +* On Gen3, some DU channels have two planes, each being wired to
> a
> > +* separate VSPD instance. The DU can then blend two planes.
> While
> > +* this feature isn't used by the driver, issues related to alpha
> > +* blending (such as incorrect colors or planes being invisible)
> may
> > +* still occur if the PnALPHAR register has a stale value. Set
> the
> > +* register to 0 to avoid this.
> > +*/
> > +
> 
> Sounds reasonable.
> 
> > +   /* TODO: Check if alpha-blending should be disabled in PnMR.
> > + */
> 
> How will this be done? Do you have a specific test in mind to determine if
> it causes issues? Or does it need validating through the hardware teams?

It is TO DO activity and will be investigated later. After investigation, if it 
is no more required
Then will remove the above comment or if it is required will send a patch.

Cheers,
Biju

> 
> 
> 
> > +   rcar_du_plane_write(rgrp, index, PnALPHAR, 0);
> 
> 
> Reviewed-by: Kieran Bingham 
> 
> >  }
> >
> >  static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
> > --
> > 2.25.1
> >

[PATCH v2] drm: rcar-du: Fix Alpha blending issue on Gen3

2022-04-26 Thread Biju Das

From: LUU HOAI 

As per R-Car-Gen3_Common_OPC_Customer_Notifications_V30.1.pdf,
unexpected image output(such as incorrect colors or planes being
invisible) can happen on the below conditions, as PnALPHAR register
is not initialized by reset.

When alpha blending (PpMRm.PpSPIM=0b101) is performed and:
•two Planes are enabled on any DUn (n=0,1,2,3)
oDSPRn= 0x 0031 or 0x 0013
•or DU0 and DU1 is used for display at the same time
oDSPR0= 0x 0001 and DSPR1= 0x 0003
oDSPR0= 0x 0003 and DSPR1= 0x 0001
•or DU2 and DU3(H3 Only) is used for display at the same time
oDSPR2= 0x 0001 and DSPR3= 0x 0003
oDSPR2= 0x 0003 and DSPR3= 0x 0001

This patch set PnALPHAR register to 0 to avoid this issue.

Signed-off-by: LUU HOAI 
Signed-off-by: Biju Das 
---
v1->v2:
 * Updated commit description
 * Updated the code comments
---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c 
b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index f214a8b6cfd3..aa80c44dd8d7 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -510,6 +510,18 @@ static void rcar_du_plane_setup_format_gen3(struct 
rcar_du_group *rgrp,
 
rcar_du_plane_write(rgrp, index, PnDDCR4,
state->format->edf | PnDDCR4_CODE);
+
+   /*
+* On Gen3, some DU channels have two planes, each being wired to a
+* separate VSPD instance. The DU can then blend two planes. While
+* this feature isn't used by the driver, issues related to alpha
+* blending (such as incorrect colors or planes being invisible) may
+* still occur if the PnALPHAR register has a stale value. Set the
+* register to 0 to avoid this.
+*/
+
+   /* TODO: Check if alpha-blending should be disabled in PnMR. */
+   rcar_du_plane_write(rgrp, index, PnALPHAR, 0);
 }
 
 static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
-- 
2.25.1

RE: [PATCH] drm: rcar-du: Add setting to PnALPHAR register on Gen3

2022-04-25 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH] drm: rcar-du: Add setting to PnALPHAR register on
> Gen3
> 
> Hi Biju,
> 
> On Sun, Apr 24, 2022 at 04:12:08PM +, Biju Das wrote:
> > > Subject: Re: [PATCH] drm: rcar-du: Add setting to PnALPHAR register
> > > on Gen3 On Sat, Apr 23, 2022 at 08:37:28AM +0100, Biju Das wrote:
> > > > From: LUU HOAI 
> > > >
> > > > In Gen3, when Alpha blend is enabled in the PnMR register,
> > > > depending on the initial value of the PnALPHAR register, either
> > > > channel of DU might be black screen.
> > > > Therefore, this patch prevents the black screen by setting the
> > > > PnALPHAR register to all 0.
> > > >
> > > > In addition, PnALPHAR register will be released in the R-Car Gen3
> > > > Hardware Manual Rev 2.4 (Sep. 2021).
> > > >
> > > > Signed-off-by: LUU HOAI 
> > > > Signed-off-by: Biju Das 
> > > > ---
> > > > This patch is based on [1]
> > > > [1]
> > > >
> > > > Not sure this patches has to go with Fixes tag for stable??
> > > >
> > > > Tested the changes on RZ/G2M board
> > > >
> > > > root@hihope-rzg2m:/cip-test-scripts#  modetest -M rcar-du -w
> > > > 54:alpha:5 root@hihope-rzg2m:/cip-test-scripts# modetest -M
> > > > rcar-du
> > > -s "93@90:1024x768@AR24" -d -P "54@90:400x300+200+200@XR24"
> > > > setting mode 1024x768-75Hz@AR24 on connectors 93, crtc 90 testing
> > > > 400x300@XR24 overlay plane 54
> > > > ---
> > > >  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 6 ++
> > > >  1 file changed, 6 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > > b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > > index 5c1c7bb04f3f..aff39b9253f8 100644
> > > > --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > > > @@ -510,6 +510,12 @@ static void
> > > > rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
> > > >
> > > > rcar_du_plane_write(rgrp, index, PnDDCR4,
> > > > state->format->edf | PnDDCR4_CODE);
> > > > +
> > > > +   /* In Gen3, PnALPHAR register need to be set to 0
> > > > +* to avoid black screen issue when alpha blend is enable
> > > > +* on DU module
> > > > +*/
> > >
> > > Comments should start with /* on a line of its own, and you can also
> > > reflow the text to 80 columns:
> >
> > OK.
> >
> > >   /*
> > >* In Gen3, PnALPHAR register need to be set to 0 to avoid black
> screen
> > >* issue when alpha blend is enable on DU module.
> > >*/
> > >
> > > It would however be nicer to document the exact behaviour, but the
> > > latest version of the documentation I have access to is rev 2.3 and
> > > it lists PnALPHAR as not available on Gen3.
> >
> > I don't have access to rev 2.4, but I got access to
> > "R-Car-Gen3_Common_OPC_Customer_Notifications_V30.1.pdf"
> > where it is mentioned about this issue and solution for fix which is
> > inline with the patch from R-Car BSP.
> >
> > "The reason is that a register is not initialized by reset.
> > This could lead to output wrong image data of other plane or wrong
> > color set from BPOR (Background plane output register)."
> >
> > > Furthermore, is this really the right fix, shouldn't we instead
> > > avoid enabling alpha-blending in PnMR on Gen3 ?
> >
> > Avoid enabling alpha-blending in PnMR on Gen3, will it help here?
> 
> It's hard to tell without knowing the exact cause of the issue. Clearing
> PnALPHAR probably makes sense on Gen3 if the register exists,
> independently from disabling alpha blending in PnMR. It would be nice if
> the commit messsage could reference the issue described in R-Car-
> Gen3_Common_OPC_Customer_Notifications_V30.1.pdf. I would also expand the
> comment a little bit:
> 
>  /*
>   * On Gen3, some DU channels have two planes, each being wired to a
> separate
>   * VSPD instance. The DU can then blend two two planes. While this
> feature
>   * isn't used by the driver, issues related to alpha blending (such as
>   * incorrect colors or planes being invisible) may still occur if the
> PnALPHAR
>   * register has a stale value. Set the register to 0 to avoid this.
>   */

OK.

> 
> > Here the issue they mentioned as "register is not initialized by reset"
> >
> > > > +   rcar_du_plane_write(rgrp, index, PnALPHAR, 0x);
> 
> I'd write 0 instead of 0x to match the rest of the driver.
> 
> Would you mind sending a v2 with these changed and an expanded commit
> message ?

OK, Will send v2 with these changes.

Cheers,
Biju

> 
> > > >  }
> > > >
> > > >  static void rcar_du_plane_setup_format(struct rcar_du_group
> > > > *rgrp,
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v3 2/4] drm: rcar-du: Fix typo

2022-04-24 Thread Biju Das

Hi Laurent,

> Subject: Re: [PATCH v3 2/4] drm: rcar-du: Fix typo
> 
> Hello,
> 
> On Fri, Apr 22, 2022 at 09:38:00AM +, Biju Das wrote:
> > > Subject: Re: [PATCH v3 2/4] drm: rcar-du: Fix typo On Thu, Apr 21,
> > > 2022 at 6:31 PM Biju Das wrote:
> > > > Fix typo rcar_du_vsp.h->rcar_du_vsp.c
> > > >
> > > > Signed-off-by: Biju Das 
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > > > @@ -1,6 +1,6 @@
> > > >  // SPDX-License-Identifier: GPL-2.0+
> > > >  /*
> > > > - * rcar_du_vsp.h  --  R-Car Display Unit VSP-Based Compositor
> > > > + * rcar_du_vsp.c  --  R-Car Display Unit VSP-Based Compositor
> > >
> > > Perhaps drop the file name completely instead?
> >
> > Currently all the R-Car DU files have file name. May be A single patch
> > to remove all off them if we are planning to do.
> >
> > Laurent, please share your thoughts on this.
> 
> Geert has a point, the file names cause issues and don't add much value.
> Would you like to send a patch to drop them all, to replace this one ? I
> can also handle it myself if you prefer.

OK, I don't have any preference. I Just noticed that issue. Feel free to post 
the patch.

Cheers,
Biju

RE: [PATCH] drm: rcar-du: Add setting to PnALPHAR register on Gen3

2022-04-24 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH] drm: rcar-du: Add setting to PnALPHAR register on
> Gen3
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Sat, Apr 23, 2022 at 08:37:28AM +0100, Biju Das wrote:
> > From: LUU HOAI 
> >
> > In Gen3, when Alpha blend is enabled in the PnMR register, depending
> > on the initial value of the PnALPHAR register, either channel of DU
> > might be black screen.
> > Therefore, this patch prevents the black screen by setting the
> > PnALPHAR register to all 0.
> >
> > In addition, PnALPHAR register will be released in the R-Car Gen3
> > Hardware Manual Rev 2.4 (Sep. 2021).
> >
> > Signed-off-by: LUU HOAI 
> > Signed-off-by: Biju Das 
> > ---
> > This patch is based on [1]
> > [1]
> >
> > Not sure this patches has to go with Fixes tag for stable??
> >
> > Tested the changes on RZ/G2M board
> >
> > root@hihope-rzg2m:/cip-test-scripts#  modetest -M rcar-du -w
> > 54:alpha:5 root@hihope-rzg2m:/cip-test-scripts# modetest -M rcar-du
> -s "93@90:1024x768@AR24" -d -P "54@90:400x300+200+200@XR24"
> > setting mode 1024x768-75Hz@AR24 on connectors 93, crtc 90 testing
> > 400x300@XR24 overlay plane 54
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > index 5c1c7bb04f3f..aff39b9253f8 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> > @@ -510,6 +510,12 @@ static void
> > rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
> >
> > rcar_du_plane_write(rgrp, index, PnDDCR4,
> > state->format->edf | PnDDCR4_CODE);
> > +
> > +   /* In Gen3, PnALPHAR register need to be set to 0
> > +* to avoid black screen issue when alpha blend is enable
> > +* on DU module
> > +*/
> 
> Comments should start with /* on a line of its own, and you can also
> reflow the text to 80 columns:

OK.

> 
>   /*
>* In Gen3, PnALPHAR register need to be set to 0 to avoid black
> screen
>* issue when alpha blend is enable on DU module.
>*/
> 
> It would however be nicer to document the exact behaviour, but the latest
> version of the documentation I have access to is rev 2.3 and it lists
> PnALPHAR as not available on Gen3.

I don't have access to rev 2.4, but I got access to 
"R-Car-Gen3_Common_OPC_Customer_Notifications_V30.1.pdf" 
where it is mentioned about this issue and solution for fix
which is inline with the patch from R-Car BSP.

"The reason is that a register is not initialized by reset.
This could lead to output wrong image data of other plane or 
wrong color set from BPOR (Background plane output register)."

> 
> Furthermore, is this really the right fix, shouldn't we instead avoid
> enabling alpha-blending in PnMR on Gen3 ?

Avoid enabling alpha-blending in PnMR on Gen3, will it help here?

Here the issue they mentioned as "register is not initialized by reset"

Cheers,
Biju

> 
> > +   rcar_du_plane_write(rgrp, index, PnALPHAR, 0x);
> >  }
> >
> >  static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
> 
> --
> Regards,
> 
> Laurent Pinchart

[PATCH] drm: rcar-du: Add setting to PnALPHAR register on Gen3

2022-04-23 Thread Biju Das

From: LUU HOAI 

In Gen3, when Alpha blend is enabled in the PnMR register,
depending on the initial value of the PnALPHAR register,
either channel of DU might be black screen.
Therefore, this patch prevents the black screen by setting
the PnALPHAR register to all 0.

In addition, PnALPHAR register will be released in
the R-Car Gen3 Hardware Manual Rev 2.4 (Sep. 2021).

Signed-off-by: LUU HOAI 
Signed-off-by: Biju Das 
---
This patch is based on [1]
[1] 
https://github.com/renesas-rcar/linux-bsp/commit/fcb34fe338cbde0a64919430733541035f20a784

Not sure this patches has to go with Fixes tag for stable??

Tested the changes on RZ/G2M board

root@hihope-rzg2m:/cip-test-scripts#  modetest -M rcar-du -w 54:alpha:5
root@hihope-rzg2m:/cip-test-scripts# modetest -M rcar-du -s 
"93@90:1024x768@AR24" -d -P "54@90:400x300+200+200@XR24"
setting mode 1024x768-75Hz@AR24 on connectors 93, crtc 90
testing 400x300@XR24 overlay plane 54
---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c 
b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index 5c1c7bb04f3f..aff39b9253f8 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -510,6 +510,12 @@ static void rcar_du_plane_setup_format_gen3(struct 
rcar_du_group *rgrp,
 
rcar_du_plane_write(rgrp, index, PnDDCR4,
state->format->edf | PnDDCR4_CODE);
+
+   /* In Gen3, PnALPHAR register need to be set to 0
+* to avoid black screen issue when alpha blend is enable
+* on DU module
+*/
+   rcar_du_plane_write(rgrp, index, PnALPHAR, 0x);
 }
 
 static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
-- 
2.25.1

RE: [PATCH v3 2/4] drm: rcar-du: Fix typo

2022-04-22 Thread Biju Das

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 2/4] drm: rcar-du: Fix typo
> 
> Hi Biju,
> 
> On Thu, Apr 21, 2022 at 6:31 PM Biju Das 
> wrote:
> > Fix typo rcar_du_vsp.h->rcar_du_vsp.c
> >
> > Signed-off-by: Biju Das 
> 
> Thanks for your patch!
> 
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > @@ -1,6 +1,6 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> > - * rcar_du_vsp.h  --  R-Car Display Unit VSP-Based Compositor
> > + * rcar_du_vsp.c  --  R-Car Display Unit VSP-Based Compositor
> 
> Perhaps drop the file name completely instead?

Currently all the R-Car DU files have file name. May be
A single patch to remove all off them if we are planning to do.

Laurent, please share your thoughts on this.

Cheers,
Biju

RE: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L DU bindings

2022-04-22 Thread Biju Das

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> DU bindings
> 
> Hi Biju,
> 
> On Fri, Apr 22, 2022 at 10:11 AM Biju Das 
> wrote:
> > > Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas
> > > RZ/G2L DU bindings On Thu, Apr 21, 2022 at 6:31 PM Biju Das
> > > 
> > > wrote:
> > > > The RZ/G2L LCD controller is composed of Frame Compression
> > > > Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit
> (DU).
> > > >
> > > > The DU module supports the following hardware features − Display
> > > > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > > > timing master − Generates video timings − Selecting the polarity
> > > > of output DCLK, HSYNC, VSYNC, and DE − Supports Progressive −
> > > > Input data format (from VSPD): RGB888, RGB666 − Output data
> > > > format: same as Input data format − Supporting Full HD (1920
> > > > pixels x 1080 lines) for MIPI-DSI Output − Supporting WXGA (1280
> > > > pixels x 800 lines) for Parallel Output
> > > >
> > > > This patch document DU module found on RZ/G2L LCDC.
> > > >
> > > > Signed-off-by: Biju Das 
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.y
> > > > +++ aml
> > > > @@ -0,0 +1,159 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +
> > > > +title: Renesas RZ/G2L Display Unit (DU)
> > > > +
> > > > +maintainers:
> > > > +  - Laurent Pinchart 
> > > > +  - Biju Das 
> > > > +
> > > > +description: |
> > > > +  These DT bindings describe the Display Unit embedded in the
> > > > +Renesas RZ/G2L
> > > > +  and RZ/V2L SoCs.
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +enum:
> > > > +  - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > > > +  - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> > >
> > > Please use the format ",-" for new bindings.
> > >
> >
> > OK.
> >
> > > I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as
> > > the only difference is a wiring difference due to the limited number
> > > of pins on the RZ/G2LC package, as per your confirmation[1]?
> > > Hence please just use "renesas,r9a07g044-du".
> >
> > I cross checked HW manual, on the overview section(page 69) Supported
> > DU channels on various SoC's are as below
> >
> > RZ/{G2L,V2L}
> > − 1 channel MIPI DSI interface or 1channel parallel output interface
> > selectable,
> >
> > RZ/G2LC
> > − 1 channel MIPI DSI interface
> >
> > RZ/G2UL ( From RZ/G2UL hardware manual overview) − 1 channel parallel
> > output interface.
> >
> > >
> > > Do you want a family-specific compatible value ("rzg2l-"), as this
> > > IP block is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?
> >
> > May be will conclude after the above discussion??
> 
> I don't insist on family-specific compatible values here, as the DUs on
> RZ/G2UL and RZ/V2L may differ.
> But RZ/G2L and RZ/G2LC are identical otherwise...

OK, Will use

compatible:
items:
 - enum:
 - renesas,r9a07g044-du # RZ/G2{L,LC}
 - const: renesas,rzg2l-du

> 
> > > > +allOf:
> > > > +  - if:
> > > > +  properties:
> > > > +compatible:
> > > > +  contains:
> > > > +enum:
> > > > +  - renesas,du-r9a07g044c
> > > > +then:
> > > > +  properties:
> > > > +ports:
> > > > +  properties:
> > > > +port@0:
> > > > +  description: DSI 0
> > > > +  required:
> > > > +- port@0
> > > > +
> > > > +  - if:
> > > > +  properties:
> > > > +compatible:
> > > > +  contains:
> > > > +enum:
> > > > +  - renesas,du-r9a07g044l
> > > > +then:
> > > > +  properties:
> > > > +ports:
> > > > +  properties:
> > > > +port@0:
> > > > +  description: DPAD 0
> > > > +port@1:
> > > > +  description: DSI 0
> > > > +  required:
> > > > +- port@0
> > > > +- port@1
> > >
> > > Having different port numbers for the common DSI0 output indeed
> > > complicates matters ;-)
> >
> > But we could delete as per [1] for RZ/G2LC where it supports only DSI and
> [2] for RZ/G2UL where it supports only DPI, right?
> 
> Yes we can. But as the internal hardware is the same, I think we should
> keep the port numbers the same on RZ/G2L and RZ/G2LC.

OK, Will keep the same port number for both RZ/G2L and RZ/G2LC.

> 
> For RZ/V2L, you probably want to treat it exactly the same as RZ/G2L, i.e.,
> the same port numbering.

OK.

> 
> For RZ/G2UL, you can use a different numbering, assuming no family-specific
> compatible value is introduced.

OK.

Regards,
Biju

RE: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L DU bindings

2022-04-22 Thread Biju Das

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> DU bindings
> 
> Hi Biju,
> 
> On Thu, Apr 21, 2022 at 6:31 PM Biju Das 
> wrote:
> > The RZ/G2L LCD controller is composed of Frame Compression Processor
> > (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
> >
> > The DU module supports the following hardware features − Display
> > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > timing master − Generates video timings − Selecting the polarity of
> > output DCLK, HSYNC, VSYNC, and DE − Supports Progressive − Input data
> > format (from VSPD): RGB888, RGB666 − Output data format: same as Input
> > data format − Supporting Full HD (1920 pixels x 1080 lines) for
> > MIPI-DSI Output − Supporting WXGA (1280 pixels x 800 lines) for
> > Parallel Output
> >
> > This patch document DU module found on RZ/G2L LCDC.
> >
> > Signed-off-by: Biju Das 
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > @@ -0,0 +1,159 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L Display Unit (DU)
> > +
> > +maintainers:
> > +  - Laurent Pinchart 
> > +  - Biju Das 
> > +
> > +description: |
> > +  These DT bindings describe the Display Unit embedded in the Renesas
> > +RZ/G2L
> > +  and RZ/V2L SoCs.
> > +
> > +properties:
> > +  compatible:
> > +enum:
> > +  - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > +  - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> 
> Please use the format ",-" for new bindings.
> 

OK.

> I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as the
> only difference is a wiring difference due to the limited number of pins on
> the RZ/G2LC package, as per your confirmation[1]?
> Hence please just use "renesas,r9a07g044-du".

I cross checked HW manual, on the overview section(page 69) Supported
DU channels on various SoC's are as below

RZ/{G2L,V2L}
− 1 channel MIPI DSI interface or 1channel parallel output interface selectable,

RZ/G2LC
− 1 channel MIPI DSI interface

RZ/G2UL ( From RZ/G2UL hardware manual overview)
− 1 channel parallel output interface.

> 
> Do you want a family-specific compatible value ("rzg2l-"), as this IP block
> is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?

May be will conclude after the above discussion??

> 
> > +allOf:
> > +  - if:
> > +  properties:
> > +compatible:
> > +  contains:
> > +enum:
> > +  - renesas,du-r9a07g044c
> > +then:
> > +  properties:
> > +ports:
> > +  properties:
> > +port@0:
> > +  description: DSI 0
> > +  required:
> > +- port@0
> > +
> > +  - if:
> > +  properties:
> > +compatible:
> > +  contains:
> > +enum:
> > +  - renesas,du-r9a07g044l
> > +then:
> > +  properties:
> > +ports:
> > +  properties:
> > +port@0:
> > +  description: DPAD 0
> > +port@1:
> > +  description: DSI 0
> > +  required:
> > +- port@0
> > +- port@1
> 
> Having different port numbers for the common DSI0 output indeed complicates
> matters ;-)
> 

But we could delete as per [1] for RZ/G2LC where it supports only DSI and [2] 
for RZ/G2UL where it supports only DPI, right?

[1] 
https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi#L24

[2] 
https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g043.dtsi#L1000

Regards,
Biju

[PATCH v3 4/4] drm: rcar-du: Add RZ/G2L DU Support

2022-04-21 Thread Biju Das

The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support blending of two picture layers and
raster operations (ROPs).

The DU part is similar to RCar like DU is connected to VSPD, so most of
the framework related functionality is based on RCar DU.

Signed-off-by: Biju Das 
---
v3:
 * New patch after removing all the indirections and by adding
   new DRM driver.
---
 drivers/gpu/drm/rcar-du/Kconfig  |  16 +-
 drivers/gpu/drm/rcar-du/Makefile |   9 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c  | 745 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h  | 104 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c   | 192 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h   | 102 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c   | 113 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h   |  29 +
 drivers/gpu/drm/rcar-du/rzg2l_du_group.h |  32 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c   | 782 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h   |  43 +
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h  |  64 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c   | 420 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h   |  93 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c | 247 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h |  42 +
 16 files changed, 3032 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_group.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 3e59c7c213f5..5fb00e8dc2e7 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -11,6 +11,19 @@ config DRM_RCAR_DU
  Choose this option if you have an R-Car chipset.
  If M is selected the module will be called rcar-du-drm.
 
+config DRM_RZG2L_DU
+   tristate "DRM Support for RZ/G2L DU"
+   depends on DRM && OF
+   depends on ARM || ARM64
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_KMS_HELPER
+   select DRM_GEM_CMA_HELPER
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you have an RZ/G2L chipset.
+ If M is selected the module will be called rzg2l-du-drm.
+
+
 config DRM_RCAR_USE_CMM
bool "R-Car DU Color Management Module (CMM) Support"
depends on DRM_RCAR_DU
@@ -62,8 +75,9 @@ config DRM_RZG2L_MIPI_DSI
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
-   depends on DRM_RCAR_DU
+   depends on DRM_RCAR_DU || DRM_RZG2L_DU
depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+   depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && 
DRM_RZG2L_DU=m)
help
  Enable support to expose the R-Car VSP Compositor as KMS planes.
 
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 14a3fa88cc0b..460ff9aeba6c 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,15 +6,24 @@ rcar-du-drm-y := rcar_du_crtc.o \
 rcar_du_kms.o \
 rcar_du_plane.o \
 
+rzg2l-du-drm-y := rzg2l_du_crtc.o \
+ rzg2l_du_drv.o \
+ rzg2l_du_encoder.o \
+ rzg2l_du_kms.o \
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP)+= rzg2l_du_vsp.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rzg2l_du_writeback.o
+
 obj-$(CONFIG_DRM_RCAR_CMM) += rcar_cmm.o
 obj-$(CONFIG_DRM_RCAR_DU)  += rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o
 obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
 
 # 'remote-endpoint' is fixed up at run-time
diff --git a/drivers/gpu/

[PATCH v3 3/4] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

2022-04-21 Thread Biju Das

Number of RPF's VSP is different on R-Car and RZ/G2L
 R-Car Gen3 -> 5 RPFs
 R-Car Gen2 -> 4 RPFs
 RZ/G2L -> 2 RPFs

Add num_rpf to struct rcar_du_device_info to support later
SoC without any code changes.

Signed-off-by: Biju Das 
Reviewed-by: Laurent Pinchart 
---
v2->v3:
 * Added Rb tag from Laurent.
 * Fixed the comment "max num"->"num"
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c 
b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 957ea97541d5..1bc7325aa356 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -55,6 +55,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info 
= {
},
},
.num_lvds = 1,
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -77,6 +78,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info 
= {
.port = 1,
},
},
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -104,6 +106,7 @@ static const struct rcar_du_device_info 
rzg1_du_r8a77470_info = {
.port = 2,
},
},
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -133,6 +136,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a774a1_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(1),
 };
 
@@ -163,6 +167,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a774b1_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(1),
 };
 
@@ -190,6 +195,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a774c0_info = {
},
},
.num_lvds = 2,
+   .num_rpf = 4,
.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -220,6 +226,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a774e1_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(1),
 };
 
@@ -272,6 +279,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7790_info = {
},
},
.num_lvds = 2,
+   .num_rpf = 4,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -297,6 +305,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7791_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -317,6 +326,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7792_info = {
.port = 1,
},
},
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -340,6 +350,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7794_info = {
.port = 1,
},
},
+   .num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -373,6 +384,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7795_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(2) | BIT(1),
 };
 
@@ -403,6 +415,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7796_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(1),
 };
 
@@ -433,6 +446,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a77965_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
.dpll_mask =  BIT(1),
 };
 
@@ -459,6 +473,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a77970_info = {
},
},
.num_lvds = 1,
+   .num_rpf = 5,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -486,6 +501,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a7799x_info = {
},
},
.num_lvds = 2,
+   .num_rpf = 5,
.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -505,6 +521,7 @@ static const struct rcar_du_device_info 
rcar_du_r8a779a0_info = {
.port = 1,
},
},
+   .num_rpf = 5,
.dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h 
b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 101f42df86ea..83530721e373 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -69,6 +69,7 @@ struct rcar_du_output_routing {
  * @channels_mask: bit mask of available DU channels
  * @routes: array of CRTC to output routes, indexed by output 
(RCAR_DU_OUTPUT_*)
  * @num_lvds: number of internal

[PATCH v3 2/4] drm: rcar-du: Fix typo

2022-04-21 Thread Biju Das

Fix typo rcar_du_vsp.h->rcar_du_vsp.c

Signed-off-by: Biju Das 
---
v3:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index 8eb9b2b097ae..9c4d1d1be1d4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * rcar_du_vsp.h  --  R-Car Display Unit VSP-Based Compositor
+ * rcar_du_vsp.c  --  R-Car Display Unit VSP-Based Compositor
  *
  * Copyright (C) 2015 Renesas Electronics Corporation
  *
-- 
2.25.1

[PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L DU bindings

2022-04-21 Thread Biju Das

The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).

The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timings
− Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
− Supports Progressive
− Input data format (from VSPD): RGB888, RGB666
− Output data format: same as Input data format
− Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
− Supporting WXGA (1280 pixels x 800 lines) for Parallel Output

This patch document DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das 
---
 v3: New patch
---
 .../bindings/display/renesas,rzg2l-du.yaml| 159 ++
 1 file changed, 159 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml 
b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
new file mode 100644
index ..2ee2d713cef4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+  - Laurent Pinchart 
+  - Biju Das 
+
+description: |
+  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+  and RZ/V2L SoCs.
+
+properties:
+  compatible:
+enum:
+  - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
+  - renesas,du-r9a07g044l # for RZ/G2L compatible DU
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Main clock
+  - description: Register access clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: aclk
+  - const: pclk
+  - const: vclk
+
+  resets:
+maxItems: 1
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+description: |
+  The connections to the DU output video ports are modeled using the OF
+  graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+  The number of ports and their assignment are model-dependent. Each port
+  shall have a single endpoint.
+
+patternProperties:
+  "^port@[0-1]$":
+$ref: /schemas/graph.yaml#/properties/port
+unevaluatedProperties: false
+
+required:
+  - port@0
+
+unevaluatedProperties: false
+
+  renesas,vsps:
+$ref: "/schemas/types.yaml#/definitions/phandle-array"
+items:
+  items:
+- description: phandle to VSP instance that serves the DU channel
+- description: Channel index identifying the LIF instance in that VSP
+description:
+  A list of phandle and channel index tuples to the VSPs that handle the
+  memory interfaces for the DU channels.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - power-domains
+  - ports
+  - renesas,vsps
+
+allOf:
+  - if:
+  properties:
+compatible:
+  contains:
+enum:
+  - renesas,du-r9a07g044c
+then:
+  properties:
+ports:
+  properties:
+port@0:
+  description: DSI 0
+  required:
+- port@0
+
+  - if:
+  properties:
+compatible:
+  contains:
+enum:
+  - renesas,du-r9a07g044l
+then:
+  properties:
+ports:
+  properties:
+port@0:
+  description: DPAD 0
+port@1:
+  description: DSI 0
+  required:
+- port@0
+- port@1
+
+additionalProperties: false
+
+examples:
+  # RZ/G2L DU
+  - |
+#include 
+#include 
+
+display@1089 {
+compatible = "renesas,du-r9a07g044l";
+reg = <0x1089 0x1>;
+interrupts = ;
+clocks = < CPG_MOD R9A07G044_LCDC_CLK_A>,
+ < CPG_MOD R9A07G044_LCDC_CLK_P>,
+ < CPG_MOD R9A07G044_LCDC_CLK_D>;
+clock-names = "aclk", "pclk", "vclk";
+resets = < R9A07G044_LCDC_RESET_N>;
+power-domains = <>;
+
+renesas,vsps = < 0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+du_out_rgb: endpoint {
+};
+};
+port@1 {
+reg = <1>;
+du_out_dsi0: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+
+...
-- 
2.25.1

[PATCH v3 0/4] Add RZ/G2L Display support

2022-04-21 Thread Biju Das

RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.

This patch series aims to add basic display support on RZ/G2L SMARC EVK
platform. The output from DSI is connected to ADV7535.

The DU controller is similar to R-Car as it is connected to VSPD,
so most of code is based on R-Car with new CRTC/DRM driver specific to
RZ/G2L

V2->v3:
 * Added new bindings for RZ/G2L DU
 * Removed indirection and created new DRM driver based on R-Car DU
v1->v2:
 * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
 * Updated commit description for bindings
 * Removed LCDC references from bindings
 * Changed clock name from du.0->aclk from bindings
 * Changed reset name from du.0->du from bindings
 * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
 * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
 * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
 * Added forward declaration for struct reset_control

[1] 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220312084205.31462-2-biju.das...@bp.renesas.com/

RFC->v1:
 * Changed  minItems->maxItems for renesas,vsps.
 * Added RZ/G2L LCDC driver with special handling for CRTC reusing
   most of RCar DU code
 * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
RFC:
 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das...@bp.renesas.com/
 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das...@bp.renesas.com/
 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das...@bp.renesas.com/
 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-19-biju.das...@bp.renesas.com/

Biju Das (4):
  dt-bindings: display: Document Renesas RZ/G2L DU bindings
  drm: rcar-du: Fix typo
  drm: rcar-du: Add num_rpf to struct rcar_du_device_info
  drm: rcar-du: Add RZ/G2L DU Support

 .../bindings/display/renesas,rzg2l-du.yaml| 159 
 drivers/gpu/drm/rcar-du/Kconfig   |  16 +-
 drivers/gpu/drm/rcar-du/Makefile  |   9 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.c |  17 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |   2 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |   8 +-
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c   | 745 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h   | 104 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c| 192 +
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h| 102 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c| 113 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h|  29 +
 drivers/gpu/drm/rcar-du/rzg2l_du_group.h  |  32 +
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c| 782 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h|  43 +
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h   |  64 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c| 420 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h|  93 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c  | 247 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h  |  42 +
 20 files changed, 3212 insertions(+), 7 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_encoder.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_group.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_kms.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_vsp.h
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_writeback.h

-- 
2.25.1

[PATCH v3 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-04-20 Thread Biju Das

This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

Signed-off-by: Biju Das 
---
v2->v3:
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Rework based on dt-binding change (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 4 files changed, 851 insertions(+)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index f6e6a6d5d987..3e59c7c213f5 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -51,6 +51,14 @@ config DRM_RCAR_MIPI_DSI
help
  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
 
+config DRM_RZG2L_MIPI_DSI
+   tristate "RZ/G2L MIPI DSI Encoder Support"
+   depends on DRM_BRIDGE && OF
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_MIPI_DSI
+   help
+ Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
+
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index e7275b5e7ec8..14a3fa88cc0b 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_DRM_RCAR_DW_HDMI)+= 
rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
+
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
 DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
new file mode 100644
index ..8c3a26bc9624
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L MIPI DSI Encoder Driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rzg2l_mipi_dsi_regs.h"
+
+struct rzg2l_mipi_dsi {
+   struct device *dev;
+   void __iomem *mmio;
+
+   struct reset_control *rstc;
+   struct reset_control *arstc;
+   struct reset_control *prstc;
+
+   struct mipi_dsi_host host;
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+
+   struct clk *vclk;
+
+   enum mipi_dsi_pixel_format format;
+   unsigned int num_data_lanes;
+   unsigned int lanes;
+   unsigned long mode_flags;
+};
+
+static inline struct rzg2l_mipi_dsi *
+bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
+

[PATCH v3 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-04-20 Thread Biju Das

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
---
v2->v3:
 * Added Rb tag from Geert and Laurent
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
RFC->v1:
 * Added a ref to dsi-controller.yaml.
RFC:-
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..131d5b63ec4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
+  up to four data lanes.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+  - const: renesas,rzg2l-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: Sequence operation channel 0 interrupt
+  - description: Sequence operation channel 1 interrupt
+  - description: Video-Input operation channel 1 interrupt
+  - description: DSI Packet Receive interrupt
+  - description: DSI Fatal Error interrupt
+  - description: DSI D-PHY PPI interrupt
+  - description: Debug interrupt
+
+  interrupt-names:
+items:
+  - const: seq0
+  - const: seq1
+  - const: vin1
+  - const: rcv
+  - const: ferr
+  - const: ppi
+  - const: debug
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D-PHY Escape mode transmit clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+description: array of physical DSI data lane indexes.
+minItems: 1
+items:
+  - const: 1
+  - const: 2
+  - const: 3
+  - const: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+dsi0: dsi@1085 {
+compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
+reg = <0x1085 0x2>;
+interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+interrupt-names = "seq0", "seq1", "vin1", "rcv",
+

[PATCH v3 0/2] Add RZ/G2L DSI driver

2022-04-20 Thread Biju Das

This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

This unit supports MIPI Alliance Specification for Display Serial Interface 
(DSI) Specification. This unit provides a
solution for transmitting MIPI DSI compliant digital video and packets. 
Normative References are below.
* MIPI Alliance Specification for Display Serial Interface Version 1.3.1
* MIPI Alliance Specification for D-PHY Version 2.1

The following are key features of this unit.

* 1 channel
* The number of Lane: 4-lane
* Support up to Full HD (1920 × 1080), 60 fps (RGB888)
* Maximum Bandwidth: 1.5 Gbps per lane
* Support Output Data Format: RGB666 / RGB888

v2->v3:
 * Added Rb tag from Geert and Laurent for the binding patch.
 * Fixed the typo "Receive" -> "transmit"
 * Added accepible values for data-lanes
 * Sorted Header file in the example
 * Added SoC specific compaible along with generic one.
 * pass rzg2l_mipi_dsi pointer to {Link,Phy} register rd/wr function instead
   of the memory pointer
 * Fixed the comment in rzg2l_mipi_dsi_startup()
 * Removed unnecessary dbg message from rzg2l_mipi_dsi_start_video()
 * DRM bridge parameter initialization moved to probe
 * Replaced dev_dbg->dev_err in rzg2l_mipi_dsi_parse_dt()
 * Inserted the missing blank lane after return in probe()
 * Added missing MODULE_DEVICE_TABLE
 * Added include linux/bits.h in header file
 * Fixed various macros in header file.
 * Reorder the make file for DSI, so that it is no more dependent
   on RZ/G2L DU patch series.
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
 * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added a ref to dsi-controller.yaml.
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/

Biju Das (2):
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver

 .../bindings/display/bridge/renesas,dsi.yaml  | 182 +
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   2 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 690 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 151 
 5 files changed, 1033 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.25.1

RE: [PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

2022-04-20 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 5/7] drm: rcar-du: Factorise
> rcar_du_{atomic_check,modeset_init}
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:58PM +, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation. Factorise
> > rcar_du_{atomic_check, modeset_init} by adding struct
> > rcar_du_crtc_helper_funcs to struct rcar_du_device_info, so that it
> > can support RZ/G2L SoC without any code changes.
> 
> I'd like to go the other way around. Instead of adding a layer of
> indirection in the DU driver, could you create a new DRM driver, and share
> common code with the DU driver ?

OK will crate new DRM driver and avoid all the indirection in DU driver.

Regards,
Biju

> 
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
> > RFC->v1:
> >  * New patch
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 
> > drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
> >  3 files changed, 43 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index f6e234dafb72..0df1430b9664 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -34,6 +34,12 @@
> >   * Device Information
> >   */
> >
> > +static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
> > +   .du_planes_init = rcar_du_planes_init,
> > +   .du_crtc_create = rcar_du_crtc_create,
> > +   .du_atomic_check_planes = rcar_du_atomic_check_planes, };
> > +
> >  static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
> > .gen = 2,
> > .features = RCAR_DU_FEATURE_CRTC_IRQ @@ -58,6 +64,7 @@ static const
> > struct rcar_du_device_info rzg1_du_r8a7743_info = {
> > .num_rpf = 4,
> > .max_width = 4095,
> > .max_height = 2047,
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -83,6 +90,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> > .num_rpf = 4,
> > .max_width = 4095,
> > .max_height = 2047,
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -113,6 +121,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> > .num_rpf = 4,
> > .max_width = 4095,
> > .max_height = 2047,
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -146,6 +155,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> > .max_width = 8190,
> > .max_height = 8190,
> > .dpll_mask =  BIT(1),
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774b1_info = { @@
> > -179,6 +189,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> > .max_width = 8190,
> > .max_height = 8190,
> > .dpll_mask =  BIT(1),
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774c0_info = { @@
> > -209,6 +220,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> > .max_width = 8190,
> > .max_height = 8190,
> > .lvds_clk_mask =  BIT(1) | BIT(0),
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774e1_info = { @@
> > -242,6 +254,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> > .max_width = 8190,
> > .max_height = 8190,
> > .dpll_mask =  BIT(1),
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7779_info = { @@
> > -265,6 +278,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> > },
> > .max_width = 4095,
> > .max_height = 2047,
> > +   .fns = _crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -298,6 +312,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
>

RE: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

2022-04-20 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to
> rcar_du_common.c
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:57PM +, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation.
> >
> > Move rcar_du_output_name() to a new common file rcar_du_common.c, So
> > that the same function can be reused by RZ/G2L SoC later.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  New patch
> > ---
> >  drivers/gpu/drm/rcar-du/Makefile |  1 +
> >  drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c| 20 
> >  3 files changed, 31 insertions(+), 20 deletions(-)  create mode
> > 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index e7275b5e7ec8..331e12d65a6b 100644
> > --- a/drivers/gpu/drm/rcar-du/Makefile
> > +++ b/drivers/gpu/drm/rcar-du/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  rcar-du-drm-y := rcar_du_crtc.o \
> > +rcar_du_common.o \
> >  rcar_du_drv.o \
> >  rcar_du_encoder.o \
> >  rcar_du_group.o \
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > new file mode 100644
> > index ..f9f9908cda6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > @@ -0,0 +1,30 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * rcar_du_common.c  --  R-Car Display Unit Common
> > + *
> > + * Copyright (C) 2013-2022 Renesas Electronics Corporation
> > + *
> > + * Contact: Laurent Pinchart (laurent.pinch...@ideasonboard.com)
> > + */
> > +
> > +#include "rcar_du_drv.h"
> > +
> > +const char *rcar_du_output_name(enum rcar_du_output output) {
> > +   static const char * const names[] = {
> > +   [RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > +   [RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > +   [RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > +   [RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > +   [RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > +   [RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > +   [RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > +   [RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > +   [RCAR_DU_OUTPUT_TCON] = "TCON",
> > +   };
> > +
> > +   if (output >= ARRAY_SIZE(names) || !names[output])
> > +   return "UNKNOWN";
> > +
> > +   return names[output];
> > +}
> 
> As we have nothing else than this function in this file, how about moving
> it to rcar_du_drv.c instead, to avoid adding a new file ?

OK, since it is small change will add the same in rzg2l_du_drv.c file.

Cheers,
Biju

> You also need to add a declaration for rcar_du_output_name() in the
> appropriate header.
> 
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 4640c356a532..f6e234dafb72 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -591,26 +591,6 @@ static const struct of_device_id
> > rcar_du_of_table[] = {
> >
> >  MODULE_DEVICE_TABLE(of, rcar_du_of_table);
> >
> > -const char *rcar_du_output_name(enum rcar_du_output output) -{
> > -   static const char * const names[] = {
> > -   [RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > -   [RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > -   [RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > -   [RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > -   [RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > -   [RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > -   [RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > -   [RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > -   [RCAR_DU_OUTPUT_TCON] = "TCON",
> > -   };
> > -
> > -   if (output >= ARRAY_SIZE(names) || !names[output])
> > -   return "UNKNOWN";
> > -
> > -   return names[output];
> > -}
> > -
> >  /* -
> 
> >   * DRM operations
> >   */
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

2022-04-20 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to
> struct rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:56PM +, Biju Das wrote:
> > There are some differences related to max frame size supported by
> > different R-Car/RZ-G family of SoC's
> >
> > Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047 Max
> > frame size supported by R-Car Gen3 is 8190x8190 Max frame size
> > supported by RZ/G2L is 1920x1080
> >
> > Add max_width and max_height to struct rcar_du_device_info to support
> > later SoC without any code changes.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * No Change
> > RFC->V1:
> >  * No Change
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36
> > +++  drivers/gpu/drm/rcar-du/rcar_du_drv.h |
> > 4 +++  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +
> >  3 files changed, 46 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 1bc7325aa356..4640c356a532 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -56,6 +56,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> > },
> > .num_lvds = 1,
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -79,6 +81,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> > },
> > },
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -107,6 +111,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> > },
> > },
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -137,6 +143,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> > },
> > .num_lvds = 1,
> > .num_rpf = 5,
> > +   .max_width = 8190,
> > +   .max_height = 8190,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -168,6 +176,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> > },
> > .num_lvds = 1,
> > .num_rpf = 5,
> > +   .max_width = 8190,
> > +   .max_height = 8190,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -196,6 +206,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> > },
> > .num_lvds = 2,
> > .num_rpf = 4,
> > +   .max_width = 8190,
> > +   .max_height = 8190,
> > .lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -227,6 +239,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> > },
> > .num_lvds = 1,
> > .num_rpf = 5,
> > +   .max_width = 8190,
> > +   .max_height = 8190,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -249,6 +263,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> > .port = 1,
> > },
> > },
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -280,6 +296,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> > },
> > .num_lvds = 2,
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -306,6
> > +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> > },
> > .num_lvds = 1,
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -327,6 +347,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> > },
> > },
> > .num_rpf = 4,
> > +   .max_width = 4095,
> > +   .max_height = 2047,
> >  };
>

RE: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

2022-04-20 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct
> rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:55PM +, Biju Das wrote:
> > Number of RPF's VSP is different on R-Car and RZ/G2L  R-Car Gen3 -> 5
> > RPFs  R-Car Gen2 -> 4 RPFs  RZ/G2L -> 2 RPFs
> >
> > Add num_rpf to struct rcar_du_device_info to support later SoC without
> > any code changes.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
> > drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-
> >  3 files changed, 20 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 957ea97541d5..1bc7325aa356 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -55,6 +55,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -77,6 +78,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> > .port = 1,
> > },
> > },
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -104,6 +106,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> > .port = 2,
> > },
> > },
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -133,6 +136,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 5,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -163,6 +167,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 5,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -190,6 +195,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> > },
> > },
> > .num_lvds = 2,
> > +   .num_rpf = 4,
> > .lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -220,6 +226,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 5,
> > .dpll_mask =  BIT(1),
> >  };
> >
> > @@ -272,6 +279,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> > },
> > },
> > .num_lvds = 2,
> > +   .num_rpf = 4,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -297,6
> > +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -317,6 +326,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> > .port = 1,
> > },
> > },
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -340,6 +350,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> > .port = 1,
> > },
> > },
> > +   .num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -373,6 +384,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 5,
> > .dpll_mask =  BIT(2) | BIT(1),
> >  };
> >
> > @@ -403,6 +415,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> > },
> > },
> > .num_lvds = 1,
> > +   .num_rpf = 5,
> >

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

2022-04-20 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:54PM +, Biju Das wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> 
> Stupid question, but as this DU and the R-Car DU are completely different
> pieces of hardware, wouldn't a separate bindings file make sense ?

OK, will create separate bindings for RZ/G2L DU

Cheers,
Biju

> 
> The DT description in this patch looks good to me.
> 
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * Updated commit description.
> >  * Removed LCDC references
> >  * Changed clock name from du.0->aclk
> >  * Changed reset name from du.0->du
> > RFC->v1:
> >  * Changed  minItems->maxItems for renesas,vsps.
> > RFC:
> >
> > ---
> >  .../bindings/display/renesas,du.yaml  | 54 +++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > index 13efea574584..f560608bf4e8 100644
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >- renesas,du-r8a77990 # for R-Car E3 compatible DU
> >- renesas,du-r8a77995 # for R-Car D3 compatible DU
> >- renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +  - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> >
> >reg:
> >  maxItems: 1
> > @@ -824,6 +825,59 @@ allOf:
> >  - reset-names
> >  - renesas,vsps
> >
> > +  - if:
> > +  properties:
> > +compatible:
> > +  contains:
> > +enum:
> > +  - renesas,du-r9a07g044l
> > +then:
> > +  properties:
> > +clocks:
> > +  items:
> > +- description: Main clock
> > +- description: Register access clock
> > +- description: Video clock
> > +
> > +clock-names:
> > +  items:
> > +- const: aclk
> > +- const: pclk
> > +- const: vclk
> > +
> > +interrupts:
> > +  maxItems: 1
> > +
> > +resets:
> > +  maxItems: 1
> > +
> > +reset-names:
> > +  items:
> > +- const: du
> > +
> > +ports:
> > +  properties:
> > +port@0:
> > +  description: DPAD 0
> > +port@1:
> > +  description: DSI 0
> > +port@2: false
> > +port@3: false
> > +
> > +  required:
> > +- port@0
> > +- port@1
> > +
> > +renesas,vsps:
> > +  maxItems: 1
> > +
> > +  required:
> > +- clock-names
> > +- interrupts
> > +- resets
> > +- reset-names
> > +- renesas,vsps
> > +
> >  additionalProperties: false
> >
> >  examples:
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-04-19 Thread Biju Das

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L
> MIPI DSI TX bindings
> 
> Hi Biju,
> 
> On Mon, Mar 28, 2022 at 8:49 AM Biju Das 
> wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das 
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,175 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +title: Renesas RZ/G2L MIPI DSI Encoder
> > +
> > +maintainers:
> > +  - Biju Das 
> > +
> > +description: |
> > +  This binding describes the MIPI DSI encoder embedded in the Renesas
> > +  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
> > +with
> > +  up to four data lanes.
> > +
> > +allOf:
> > +  - $ref: /schemas/display/dsi-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +enum:
> > +  - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
> 
> Do you want to define SoC-specific compatible values, or can the IP
> revision be read from the hardware?

There is no IP revision register for DSI. "rzg2l-mipi-dsi" is generic
Compatible for both RZ/G2L and RZ/V2L.

So I can add SoC compatible for both these SoC's along with generic one.

Regards,
Biju

> 
> The rest LGTM (I'm no MIPI-DSI expert), so
> Reviewed-by: Geert Uytterhoeven 
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds

[PATCH] drm: bridge: adv7511: Enable DRM_BRIDGE_OP_HPD based on HPD interrupt

2022-04-19 Thread Biju Das

Connector detection using poll method won't work in case of bridge
attached to the encoder with the flag DRM_BRIDGE_ATTACH_NO_CONNECTOR, as
the code defaults to HPD.

Enable DRM_BRIDGE_OP_HPD based on HPD interrupt availability, so that
it will fall back to polling, if HPD is not available.

Signed-off-by: Biju Das 
---
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 668dcefbae17..b3f10c54e064 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -1292,8 +1292,10 @@ static int adv7511_probe(struct i2c_client *i2c, const 
struct i2c_device_id *id)
goto err_unregister_cec;
 
adv7511->bridge.funcs = _bridge_funcs;
-   adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
-   | DRM_BRIDGE_OP_HPD;
+   adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
+   if (adv7511->i2c_main->irq)
+   adv7511->bridge.ops |= DRM_BRIDGE_OP_HPD;
+
adv7511->bridge.of_node = dev->of_node;
adv7511->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 
-- 
2.25.1

RE: [PATCH v2 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-04-18 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/2] drm: rcar-du: Add RZ/G2L DSI driver
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Mon, Mar 28, 2022 at 07:51:15AM +0100, Biju Das wrote:
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It
> > currently supports DSI mode only.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * Rework based on dt-binding change (DSI + D-PHY) as single block
> >  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
> >  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
> >and rzg2l_mipi_dsi_link_write
> >  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> > RFC->v1:
> >  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
> >and dropped DRM as it is implied by DRM_BRIDGE
> >  * Used devm_reset_control_get_exclusive() for reset handle
> >  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
> >  * Added error check for pm, using pm_runtime_resume_and_get() instead of
> >pm_runtime_get_sync()
> >  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
> >  * Avoided read-modify-write stopping hsclock
> >  * Used devm_platform_ioremap_resource for resource allocation
> >  * Removed unnecessary assert call from probe and remove.
> >  * wrap the line after the PTR_ERR() in probe()
> >  * Updated reset failure messages in probe
> >  * Fixed the typo arstc->prstc
> >  * Made hex constants to lower case.
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
> >  drivers/gpu/drm/rcar-du/Makefile  |   1 +
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 686 ++
> >  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 
> >  4 files changed, 844 insertions(+)
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> >  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Kconfig
> > b/drivers/gpu/drm/rcar-du/Kconfig index e40fb0c53f9b..83d7d28214a0
> > 100644
> > --- a/drivers/gpu/drm/rcar-du/Kconfig
> > +++ b/drivers/gpu/drm/rcar-du/Kconfig
> > @@ -64,6 +64,14 @@ config DRM_RCAR_MIPI_DSI
> > help
> >   Enable support for the R-Car Display Unit embedded MIPI DSI
> encoders.
> >
> > +config DRM_RZG2L_MIPI_DSI
> > +   tristate "RZ/G2L MIPI DSI Encoder Support"
> > +   depends on DRM_BRIDGE && OF
> > +   depends on ARCH_RENESAS || COMPILE_TEST
> > +   select DRM_MIPI_DSI
> > +   help
> > + Enable support for the RZ/G2L Display Unit embedded MIPI DSI
> encoders.
> > +
> >  config DRM_RCAR_VSP
> > bool "R-Car DU VSP Compositor Support" if ARM
> > default y if ARM64
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index 01ba78e56b53..7fb4f8717fc4 100644
> > --- a/drivers/gpu/drm/rcar-du/Makefile
> > +++ b/drivers/gpu/drm/rcar-du/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_RCAR_LVDS)   += rcar_lvds.o
> >  obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
> >
> >  obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o
> > +obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
> >
> >  # 'remote-endpoint' is fixed up at run-time
> >  DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint diff --git
> > a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> > b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> > new file mode 100644
> > index ..3b785041ba5e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
> > @@ -0,0 +1,686 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * RZ/G2L MIPI DSI Encoder Driver
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corporation  */ #include
> > + #include  #include  #include
> > + #include  #include 
> > +#include  #include  #include
> > + #include  #include
> > + #include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "rzg2l_mipi_dsi_regs.h"
> > +
> > +struct rzg2l_mipi_dsi {
> > +   struct device *dev;
> > +   void __iomem *mmio;
> > +
> > +   struct reset_control *rstc;
> > +   struct reset_control *arstc;
> > +   struct reset_control *prstc;
> > +
> > +   struct mipi_dsi_hos

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-04-18 Thread Biju Das

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L
> MIPI DSI TX bindings
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Mon, Mar 28, 2022 at 07:49:30AM +0100, Biju Das wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das 
> > ---
> > v1->v2:
> >  * Added full path for dsi-controller.yaml
> >  * Modeled DSI + D-PHY as single block and updated reg property
> >  * Fixed typo D_PHY->D-PHY
> >  * Updated description
> >  * Added interrupts and interrupt-names and updated the example
> > RFC->v1:
> >  * Added a ref to dsi-controller.yaml.
> > RFC:-
> >  *
> > ---
> >  .../bindings/display/bridge/renesas,dsi.yaml  | 175
> > ++
> >  1 file changed, 175 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > new file mode 100644
> > index ..eebbf617c484
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,175 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> > +
> > +title: Renesas RZ/G2L MIPI DSI Encoder
> > +
> > +maintainers:
> > +  - Biju Das 
> > +
> > +description: |
> > +  This binding describes the MIPI DSI encoder embedded in the Renesas
> > +  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
> > +with
> > +  up to four data lanes.
> > +
> > +allOf:
> > +  - $ref: /schemas/display/dsi-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +enum:
> > +  - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +items:
> > +  - description: Sequence operation channel 0 interrupt
> > +  - description: Sequence operation channel 1 interrupt
> > +  - description: Video-Input operation channel 1 interrupt
> > +  - description: DSI Packet Receive interrupt
> > +  - description: DSI Fatal Error interrupt
> > +  - description: DSI D-PHY PPI interrupt
> > +  - description: Debug interrupt
> > +
> > +  interrupt-names:
> > +items:
> > +  - const: seq0
> > +  - const: seq1
> > +  - const: vin1
> > +  - const: rcv
> > +  - const: ferr
> > +  - const: ppi
> > +  - const: debug
> > +
> > +  clocks:
> > +items:
> > +  - description: DSI D-PHY PLL multiplied clock
> > +  - description: DSI D-PHY system clock
> > +  - description: DSI AXI bus clock
> > +  - description: DSI Register access clock
> > +  - description: DSI Video clock
> > +  - description: DSI D-PHY Escape mode Receive clock
> 
> Isn't this the escape mode *transmit* clock ?

Yep, There is a mismatch between clk document and hardware manual. 
I have reported this issue to HW team for fixing the clk document.

> 
> > +
> > +  clock-names:
> > +items:
> > +  - const: pllclk
> > +  - const: sysclk
> > +  - const: aclk
> > +  - const: pclk
> > +  - const: vclk
> > +  - const: lpclk
> > +
> > +  resets:
> > +items:
> > +  - description: MIPI_DSI_CMN_RSTB
> > +  - description: MIPI_DSI_ARESET_N
> > +  - description: MIPI_DSI_PRESET_N
> > +
> > +  reset-names:
> > +items:
> > +  - const: rst
> > +  - const: arst
> > +  - const: prst
> > +
> > +  power-domains:
> > +maxItems: 1
> > +
> > +  ports:
> > +$ref: /schemas/graph.yaml#/properties/ports
> > +
> > +properties:
> > +  port@0:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description: Parallel input port
> > +
> > +  port@1:
> > +$ref: /schemas/graph.yaml#/$defs/port-base
> > +unevaluatedProperties: false
> > +description: DSI output port
> > +
> > +properties:
> > +  endpoint:
> > +$ref: /schemas/media/video-interfaces.yaml#
> > +

RE: [PATCH v2 0/2] Add RZ/G2L DSI driver

2022-04-14 Thread Biju Das

Hi All,

Gentle ping. Are we happy with this patch series?
Please let me know.

Cheers,
Biju

> Subject: [PATCH v2 0/2] Add RZ/G2L DSI driver
> 
> This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI mode only.
> 
> This unit supports MIPI Alliance Specification for Display Serial
> Interface (DSI) Specification. This unit provides a solution for
> transmitting MIPI DSI compliant digital video and packets. Normative
> References are below.
> * MIPI Alliance Specification for Display Serial Interface Version 1.3.1
> * MIPI Alliance Specification for D-PHY Version 2.1
> 
> The following are key features of this unit.
> 
> * 1 channel
> * The number of Lane: 4-lane
> * Support up to Full HD (1920 × 1080), 60 fps (RGB888)
> * Maximum Bandwidth: 1.5 Gbps per lane
> * Support Output Data Format: RGB666 / RGB888
> 
> v1->v2:
>  * Added full path for dsi-controller.yaml
>  * Modeled DSI + D-PHY as single block and updated reg property
>  * Fixed typo D_PHY->D-PHY
>  * Updated description
>  * Added interrupts and interrupt-names and updated the example
>  * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
>  * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
>  * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
>and rzg2l_mipi_dsi_link_write
>  * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
> RFC->v1:
>  * Added a ref to dsi-controller.yaml.
>  * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
>and dropped DRM as it is implied by DRM_BRIDGE
>  * Used devm_reset_control_get_exclusive() for reset handle
>  * Removed bool hsclkmode from struct rzg2l_mipi_dsi
>  * Added error check for pm, using pm_runtime_resume_and_get() instead of
>pm_runtime_get_sync()
>  * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
>  * Avoided read-modify-write stopping hsclock
>  * Used devm_platform_ioremap_resource for resource allocation
>  * Removed unnecessary assert call from probe and remove.
>  * wrap the line after the PTR_ERR() in probe()
>  * Updated reset failure messages in probe
>  * Fixed the typo arstc->prstc
>  * Made hex constants to lower case.
> RFC:
>  *
> 
> Biju Das (2):
>   dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
>   drm: rcar-du: Add RZ/G2L DSI driver
> 
>  .../bindings/display/bridge/renesas,dsi.yaml  | 175 +
>  drivers/gpu/drm/rcar-du/Kconfig   |   8 +
>  drivers/gpu/drm/rcar-du/Makefile  |   1 +
>  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 686 ++
>  drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 
>  5 files changed, 1019 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> 
> --
> 2.17.1

RE: [PATCH v2 0/7] Add RZ/G2L Display support

2022-04-14 Thread Biju Das

Hi All,

Gentle ping, Are we happy with this patch series?

Cheers,
Biju

> Subject: [PATCH v2 0/7] Add RZ/G2L Display support
> 
> RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
> Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
> connected to Display parallel interface and MIPI link video interface.
> 
> This patch series aims to add basic display support on RZ/G2L SMARC EVK
> platform. The output from DSI is connected to ADV7535.
> 
> The DU controller is similar to R-Car as it is connected to VSPD, so
> reusing most of R-Car code with new CRTC driver specific to RZ/G2L
> 
> v1->v2:
>  * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
>  * Updated commit description for bindings
>  * Removed LCDC references from bindings
>  * Changed clock name from du.0->aclk from bindings
>  * Changed reset name from du.0->du from bindings
>  * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
>  * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
>  * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
>  * Added forward declaration for struct reset_control
> 
> [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220312084205.31462-
> 2-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=3zlHOfdKJ
> XLmDLGaMbbw%2BDUxQreKIEtvGUHNSuukDmg%3Dreserved=0
> 
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
>  * Added RZ/G2L LCDC driver with special handling for CRTC reusing
>most of RCar DU code
>  * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
> RFC:
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 18-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=SXadiMRg%
> 2Fw%2Fnt3R6K02Zke67CSFqIQtt34si2RCqyH0%3Dreserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 12-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=uRkp8himf
> 53knLtbWBxfRa4HGY3SxmyLT5FBrpmFtqg%3Dreserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 13-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=MQAEyp28C
> rxHTvdHtarXlO6j0CkpCXZuqVHcbNWkXYI%3Dreserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 19-
> biju.das.jz%40bp.renesas.com%2Fdata=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=1y%2Bd5Yb
> UoXnMZL97%2F4LTcG8IDtze%2FW%2BwzHRXBEbUgSw%3Dreserved=0
> 
> Biju Das (7):
>   dt-bindings: display: renesas,du: Document r9a07g044l bindings
>   drm: rcar-du: Add num_rpf to struct rcar_du_device_info
>   drm: rcar-du: Add max_width and max_height to struct
> rcar_du_device_info
>   drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c
>   drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}
>   drm: rcar-du: Factorise
> rcar_du_vsp{complete,enable,plane_atomic_check}
>   drm: rcar-du: Add RZ/G2L DU Support
> 
>  .../bindings/display/renesas,du.yaml  |  54 ++
>  drivers/gpu/drm/rcar-du/Kconfig   |  18 +-
>  drivers/gpu/drm/rcar-du/Makefile  |  13 +
>  drivers/gpu/drm/rcar-du/rcar_du_common.c  |  30 +
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.h|   8

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

2022-04-12 Thread Biju Das

Hi Geert,

Thanks for the feedback

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> On Wed, Mar 16, 2022 at 2:11 PM Biju Das 
> wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> >
> > Signed-off-by: Biju Das 
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >- renesas,du-r8a77990 # for R-Car E3 compatible DU
> >- renesas,du-r8a77995 # for R-Car D3 compatible DU
> >- renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +  - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> 
> "renesas,du-r9a07g044"? Both RZ/G2L and RZ/G2LC have an LCDC.
> I believe the lack of parallel data support on RZ/G2LC is just a
> limitation of the package?

From the block diagram 24-bit video data from DU is connected to both DSI and 
parallel interface.
However, SoC packaging wise RZ/G2LC supports only DSI interface.

RZ/G2L supports both DSI and parallel interface
RZ/G2LC supports only DSI interface

OK, we could use "renesas,du-r9a07g044" as well. 

Regards,
Biju

[PATCH v2 2/2] drm: rcar-du: Add RZ/G2L DSI driver

2022-03-28 Thread Biju Das

This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

Signed-off-by: Biju Das 
---
v1->v2:
 * Rework based on dt-binding change (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   1 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 686 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 
 4 files changed, 844 insertions(+)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index e40fb0c53f9b..83d7d28214a0 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -64,6 +64,14 @@ config DRM_RCAR_MIPI_DSI
help
  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
 
+config DRM_RZG2L_MIPI_DSI
+   tristate "RZ/G2L MIPI DSI Encoder Support"
+   depends on DRM_BRIDGE && OF
+   depends on ARCH_RENESAS || COMPILE_TEST
+   select DRM_MIPI_DSI
+   help
+ Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.
+
 config DRM_RCAR_VSP
bool "R-Car DU VSP Compositor Support" if ARM
default y if ARM64
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 01ba78e56b53..7fb4f8717fc4 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_RCAR_LVDS)   += rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)+= rcar_mipi_dsi.o
 
 obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o
+obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)   += rzg2l_mipi_dsi.o
 
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c 
b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
new file mode 100644
index ..3b785041ba5e
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
@@ -0,0 +1,686 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L MIPI DSI Encoder Driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rzg2l_mipi_dsi_regs.h"
+
+struct rzg2l_mipi_dsi {
+   struct device *dev;
+   void __iomem *mmio;
+
+   struct reset_control *rstc;
+   struct reset_control *arstc;
+   struct reset_control *prstc;
+
+   struct mipi_dsi_host host;
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+
+   struct clk *vclk;
+
+   enum mipi_dsi_pixel_format format;
+   unsigned int num_data_lanes;
+   unsigned int lanes;
+   unsigned long mode_flags;
+};
+
+static inline struct rzg2l_mipi_dsi *
+bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
+}
+
+static inline struct rzg2l_mipi_dsi *
+host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host)
+{
+   return container_of(host, struct rzg2l_mipi_dsi, host);
+}
+
+static void rzg2l_mipi_dsi_phy_write(void __iomem *mem, u32 reg, u32 data)
+{
+   iowrite32(data, mem + reg);
+}
+
+static void rzg2l_mipi_dsi_link_write(void __iomem *mem, u32 reg, u32 data)
+{
+   iowrite32(data, mem + LINK_REG_OFFSET + reg);
+}
+
+static u32 rzg2l_mipi_dsi_link_read(void __iomem *mem, u32 reg)
+{
+   return ioread32(mem + LINK_REG_OFFSET + reg);
+}
+
+/* 
-
+ * Hardware Setup
+ */
+
+

[PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-03-28 Thread Biju Das

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
---
v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
RFC->v1:
 * Added a ref to dsi-controller.yaml.
RFC:-
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 175 ++
 1 file changed, 175 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..eebbf617c484
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
+  up to four data lanes.
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+properties:
+  compatible:
+enum:
+  - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: Sequence operation channel 0 interrupt
+  - description: Sequence operation channel 1 interrupt
+  - description: Video-Input operation channel 1 interrupt
+  - description: DSI Packet Receive interrupt
+  - description: DSI Fatal Error interrupt
+  - description: DSI D-PHY PPI interrupt
+  - description: Debug interrupt
+
+  interrupt-names:
+items:
+  - const: seq0
+  - const: seq1
+  - const: vin1
+  - const: rcv
+  - const: ferr
+  - const: ppi
+  - const: debug
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D-PHY Escape mode Receive clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  power-domains:
+maxItems: 1
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+dsi0: dsi@1085 {
+compatible = "renesas,rzg2l-mipi-dsi";
+reg = <0x1085 0x2>;
+interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+interrupt-names = "seq0", "seq1", "vin1", "rcv",
+  "ferr", "ppi", "debug";
+clocks = < CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+resets = < R9A07G044_MIPI_DSI_CMN_RSTB

[PATCH v2 0/2] Add RZ/G2L DSI driver

2022-03-28 Thread Biju Das

This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.

This unit supports MIPI Alliance Specification for Display Serial Interface 
(DSI) Specification. This unit provides a
solution for transmitting MIPI DSI compliant digital video and packets. 
Normative References are below.
* MIPI Alliance Specification for Display Serial Interface Version 1.3.1
* MIPI Alliance Specification for D-PHY Version 2.1

The following are key features of this unit.

* 1 channel
* The number of Lane: 4-lane
* Support up to Full HD (1920 × 1080), 60 fps (RGB888)
* Maximum Bandwidth: 1.5 Gbps per lane
* Support Output Data Format: RGB666 / RGB888

v1->v2:
 * Added full path for dsi-controller.yaml
 * Modeled DSI + D-PHY as single block and updated reg property
 * Fixed typo D_PHY->D-PHY
 * Updated description
 * Added interrupts and interrupt-names and updated the example 
 * Driver rework based on dt-binding changes (DSI + D-PHY) as single block
 * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
 * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write
   and rzg2l_mipi_dsi_link_write
 * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
 * Added a ref to dsi-controller.yaml.
 * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
   and dropped DRM as it is implied by DRM_BRIDGE
 * Used devm_reset_control_get_exclusive() for reset handle
 * Removed bool hsclkmode from struct rzg2l_mipi_dsi
 * Added error check for pm, using pm_runtime_resume_and_get() instead of
   pm_runtime_get_sync()
 * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
 * Avoided read-modify-write stopping hsclock
 * Used devm_platform_ioremap_resource for resource allocation
 * Removed unnecessary assert call from probe and remove.
 * wrap the line after the PTR_ERR() in probe()
 * Updated reset failure messages in probe
 * Fixed the typo arstc->prstc
 * Made hex constants to lower case.
RFC:
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das...@bp.renesas.com/
 * 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-23-biju.das...@bp.renesas.com/

Biju Das (2):
  dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
  drm: rcar-du: Add RZ/G2L DSI driver

 .../bindings/display/bridge/renesas,dsi.yaml  | 175 +
 drivers/gpu/drm/rcar-du/Kconfig   |   8 +
 drivers/gpu/drm/rcar-du/Makefile  |   1 +
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c  | 686 ++
 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 
 5 files changed, 1019 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

-- 
2.17.1

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