Re: [PATCH v6,3/3] drm: mediatek: Add mt8186 dpi compatible to mtk_dpi.c
Hi, Xinlei:
On Wed, 2022-09-14 at 21:21 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Add the compatible because use edge_cfg_in_mmsys in mt8186.
>
> Signed-off-by: Xinlei Lee
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 6e02f02f163c..52bcc4114afd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -942,6 +942,24 @@ static const struct mtk_dpi_conf mt8183_conf = {
> .csc_enable_bit = CSC_ENABLE,
> };
>
> +static const struct mtk_dpi_conf mt8186_conf = {
> + .cal_factor = mt8183_calculate_factor,
> + .reg_h_fre_con = 0xe0,
> + .max_clock_khz = 15,
> + .output_fmts = mt8183_output_fmts,
> + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
> + .edge_cfg_in_mmsys = true,
According to the previous review, edge_cfg_in_mmsys is not necessary,
so mt8186_conf is identical to mt8192_conf.
Regards,
CK
> + .pixels_per_iter = 1,
> + .is_ck_de_pol = true,
> + .swap_input_support = true,
> + .support_direct_pin = true,
> + .dimension_mask = HPW_MASK,
> + .hvsize_mask = HSIZE_MASK,
> + .channel_swap_shift = CH_SWAP,
> + .yuv422_en_bit = YUV422_EN,
> + .csc_enable_bit = CSC_ENABLE,
> +};
> +
> static const struct mtk_dpi_conf mt8192_conf = {
> .cal_factor = mt8183_calculate_factor,
> .reg_h_fre_con = 0xe0,
> @@ -1092,6 +1110,9 @@ static const struct of_device_id
> mtk_dpi_of_ids[] = {
> { .compatible = "mediatek,mt8183-dpi",
> .data = _conf,
> },
> + { .compatible = "mediatek,mt8186-dpi",
> + .data = _conf,
> + },
> { .compatible = "mediatek,mt8192-dpi",
> .data = _conf,
> },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 546b79412815..3d32fbc66ac1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -646,6 +646,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8183-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8186-dpi",
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8192-dpi",
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8195-dp-intf",
Re: [PATCH v6,2/3] drm: mediatek: Adjust the dpi output format to MT8186
Hi, Xinlei:
On Wed, 2022-09-14 at 21:21 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Dpi output needs to adjust the output format to dual edge for MT8186.
> The bridge ic on MT8186 uses the output format of RGB888_dual_edge.
I think different sink ic may support different output format, so query
the sink information to decide which outout format.
> Due
> to hardware changes, we need to modify the output format
> corresponding
> to the mmsys register.
>
> Co-developed-by: Jitao Shi
> Signed-off-by: Jitao Shi
> Signed-off-by: Xinlei Lee
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delre...@collabora.com>
> Reviewed-by: Nís F. R. A. Prado
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index fb0b79704636..6e02f02f163c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> #include
> @@ -28,6 +29,7 @@
> #include "mtk_disp_drv.h"
> #include "mtk_dpi_regs.h"
> #include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
>
> enum mtk_dpi_out_bit_num {
> MTK_DPI_OUT_BIT_NUM_8BITS,
> @@ -58,6 +60,11 @@ enum mtk_dpi_out_color_format {
> MTK_DPI_COLOR_FORMAT_YCBCR_422
> };
>
> +enum mtk_dpi_out_format_con {
> + MTK_DPI_RGB888_DDR_CON,
> + MTK_DPI_RGB565_SDR_CON
> +};
> +
> struct mtk_dpi {
> struct drm_encoder encoder;
> struct drm_bridge bridge;
> @@ -80,6 +87,7 @@ struct mtk_dpi {
> struct pinctrl_state *pins_dpi;
> u32 output_fmt;
> int refcount;
> + struct device *mmsys_dev;
> };
>
> static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
> @@ -133,6 +141,7 @@ struct mtk_dpi_yc_limit {
> * @yuv422_en_bit: Enable bit of yuv422.
> * @csc_enable_bit: Enable bit of CSC.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output
> needs to be set in MMSYS.
> */
> struct mtk_dpi_conf {
> unsigned int (*cal_factor)(int clock);
> @@ -151,6 +160,7 @@ struct mtk_dpi_conf {
> u32 yuv422_en_bit;
> u32 csc_enable_bit;
> u32 pixels_per_iter;
> + bool edge_cfg_in_mmsys;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val,
> u32 mask)
> @@ -447,6 +457,8 @@ static void mtk_dpi_dual_edge(struct mtk_dpi
> *dpi)
> mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
>dpi->output_fmt ==
> MEDIA_BUS_FMT_RGB888_2X12_LE ?
>EDGE_SEL : 0, EDGE_SEL);
> + if (dpi->conf->edge_cfg_in_mmsys)
> + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev,
> MTK_DPI_RGB888_DDR_CON);
Why do you set a DPI driver defined value MTK_DPI_RGB888_DDR_CON into
mmsys driver? I think you should set a value which mmsys driver
understand.
Regards,
CK
> } else {
> mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> 0);
> }
> @@ -776,8 +788,10 @@ static int mtk_dpi_bind(struct device *dev,
> struct device *master, void *data)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
> struct drm_device *drm_dev = data;
> + struct mtk_drm_private *priv = drm_dev->dev_private;
> int ret;
>
> + dpi->mmsys_dev = priv->mmsys_dev;
> ret = drm_simple_encoder_init(drm_dev, >encoder,
> DRM_MODE_ENCODER_TMDS);
> if (ret) {
Re: [PATCH v5,2/2] drm: mediatek: Adjust the dpi output format to MT8186
Hi, Xinlei:
On Mon, 2022-09-05 at 21:34 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Dpi output needs to adjust the output format to dual edge for MT8186.
Separate this patch into two patches. One is adding edge_cfg_in_mmsys,
and another one is adding mt8186 dpi support.
I think the default value in mmsys (single edge) should work for some
display so that mmsys hardware use single edge for default value. So I
need you to describe more information why we need dual edge.
>
> Co-developed-by: Jitao Shi
> Signed-off-by: Jitao Shi
> Signed-off-by: Xinlei Lee
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delre...@collabora.com>
> Reviewed-by: Nílas F. R. A. Prado
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 31
> +
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 5
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
> 3 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 630a4e301ef6..ffe4a4b70a0f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -15,6 +15,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> #include
> @@ -30,6 +31,7 @@
> #include "mtk_disp_drv.h"
> #include "mtk_dpi_regs.h"
> #include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
>
> enum mtk_dpi_out_bit_num {
> MTK_DPI_OUT_BIT_NUM_8BITS,
> @@ -82,6 +84,7 @@ struct mtk_dpi {
> struct pinctrl_state *pins_dpi;
> u32 output_fmt;
> int refcount;
> + struct device *mmsys_dev;
> };
>
> static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
> @@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit {
> * @yuv422_en_bit: Enable bit of yuv422.
> * @csc_enable_bit: Enable bit of CSC.
> * @pixels_per_iter: Quantity of transferred pixels per iteration.
> + * @edge_cfg_in_mmsys: If the edge configuration for DPI's output
> needs to be set in MMSYS.
> */
> struct mtk_dpi_conf {
> unsigned int (*cal_factor)(int clock);
> @@ -153,6 +157,7 @@ struct mtk_dpi_conf {
> u32 yuv422_en_bit;
> u32 csc_enable_bit;
> u32 pixels_per_iter;
> + bool edge_cfg_in_mmsys;
> };
>
> static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val,
> u32 mask)
> @@ -449,6 +454,9 @@ static void mtk_dpi_dual_edge(struct mtk_dpi
> *dpi)
> mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
>dpi->output_fmt ==
> MEDIA_BUS_FMT_RGB888_2X12_LE ?
>EDGE_SEL : 0, EDGE_SEL);
> + if (dpi->conf->edge_cfg_in_mmsys)
> + mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev,
> DPI_RGB888_DDR_CON,
> + DPI_FORMAT_MASK);
> } else {
> mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
> 0);
> }
> @@ -778,8 +786,10 @@ static int mtk_dpi_bind(struct device *dev,
> struct device *master, void *data)
> {
> struct mtk_dpi *dpi = dev_get_drvdata(dev);
> struct drm_device *drm_dev = data;
> + struct mtk_drm_private *priv = drm_dev->dev_private;
> int ret;
>
> + dpi->mmsys_dev = priv->mmsys_dev;
> ret = drm_simple_encoder_init(drm_dev, >encoder,
> DRM_MODE_ENCODER_TMDS);
> if (ret) {
> @@ -930,6 +940,24 @@ static const struct mtk_dpi_conf mt8183_conf = {
> .csc_enable_bit = CSC_ENABLE,
> };
>
> +static const struct mtk_dpi_conf mt8186_conf = {
> + .cal_factor = mt8183_calculate_factor,
> + .reg_h_fre_con = 0xe0,
> + .max_clock_khz = 15,
> + .output_fmts = mt8183_output_fmts,
> + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
> + .edge_cfg_in_mmsys = true,
> + .pixels_per_iter = 1,
> + .is_ck_de_pol = true,
> + .swap_input_support = true,
> + .support_direct_pin = true,
> + .dimension_mask = HPW_MASK,
> + .hvsize_mask = HSIZE_MASK,
> + .channel_swap_shift = CH_SWAP,
> + .yuv422_en_bit = YUV422_EN,
> + .csc_enable_bit = CSC_ENABLE,
> +};
> +
> static const struct mtk_dpi_conf mt8192_conf = {
> .cal_factor = mt8183_calculate_factor,
> .reg_h_fre_con = 0xe0,
> @@ -1080,6 +1108,9 @@ static const struct of_device_id
> mtk_dpi_of_ids[] = {
> { .compatible = "mediatek,mt8183-dpi",
> .data = _conf,
> },
> + { .compatible = "mediatek,mt8186-dpi",
> + .data = _conf,
> + },
> { .compatible = "mediatek,mt8192-dpi",
> .data = _conf,
> },
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index 62bd4931b344..779e868ffb1a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -235,4 +235,9 @@
> #define MATRIX_SEL_RGB_TO_JPEG 0
> #define MATRIX_SEL_RGB_TO_BT601 2
>
> +/* Values for DPI configuration in MMSYS address space
Re: [PATCH v17 07/10] drm/mediatek: dp: Determine device of next_bridge
Hi, Bo-Chen: On Thu, 2022-09-01 at 12:41 +0800, Bo-Chen Chen wrote: > It's not necessary to have a next_bridge for DP device, so we add > this > patch to judge this. Reviewed-by: CK Hu > > Signed-off-by: Bo-Chen Chen > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index 136e13150281..e37c9185e4ec 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -1886,7 +1886,10 @@ static int mtk_dp_probe(struct platform_device > *pdev) >"failed to request dp irq > resource\n"); > > mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, > 1, 0); > - if (IS_ERR(mtk_dp->next_bridge)) > + if (IS_ERR(mtk_dp->next_bridge) && > + PTR_ERR(mtk_dp->next_bridge) == -ENODEV) > + mtk_dp->next_bridge = NULL; > + else if (IS_ERR(mtk_dp->next_bridge)) > return dev_err_probe(dev, PTR_ERR(mtk_dp->next_bridge), >"Failed to get bridge\n"); >
Re: [PATCH v1 1/4] dt-bindings: mediatek: modify VDOSYS0 device tree Documentations for MT8188
Hi, Nathan: On Mon, 2022-08-22 at 11:32 +0800, nathan.lu wrote: > From: Nathan Lu > > modify VDOSYS0 device tree Documentations for MT8188. > > Signed-off-by: Nathan Lu > --- > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 3 > ++- > .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + > .../bindings/display/mediatek/mediatek,postmask.yaml | 1 + > .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml| 2 Separate the display part to another patch for the maintainer it belong to. > ++ > .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + > 10 files changed, 12 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > index 6ad023eec193..f26f61069181 100644 > --- > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > +++ > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > @@ -30,6 +30,7 @@ properties: >- mediatek,mt8173-mmsys >- mediatek,mt8183-mmsys >- mediatek,mt8186-mmsys > + - mediatek,mt8188-mmsys >- mediatek,mt8192-mmsys >- mediatek,mt8195-mmsys >- mediatek,mt8365-mmsys > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > index d4d585485e7b..92741486c24d 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > @@ -31,6 +31,7 @@ properties: >- items: >- enum: >- mediatek,mt8186-disp-aal > + - mediatek,mt8188-disp-aal >- mediatek,mt8192-disp-aal >- mediatek,mt8195-disp-aal >- const: mediatek,mt8183-disp-aal > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y > aml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y > aml > index 63fb02014a56..fe444beff558 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y > aml > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y > aml > @@ -27,6 +27,7 @@ properties: >- const: mediatek,mt8192-disp-ccorr >- items: >- enum: > + - mediatek,mt8188-disp-ccorr >- mediatek,mt8195-disp-ccorr >- const: mediatek,mt8192-disp-ccorr >- items: > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > index d2f89ee7996f..62306c88f485 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > @@ -37,6 +37,7 @@ properties: >- enum: >- mediatek,mt8183-disp-color >- mediatek,mt8186-disp-color > + - mediatek,mt8188-disp-color >- mediatek,mt8192-disp-color >- mediatek,mt8195-disp-color >- const: mediatek,mt8173-disp-color > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. > yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. > yaml > index 8ad8187c02d1..5c7445c174e5 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. > yaml > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. > yaml > @@ -27,6 +27,7 @@ properties: >- items: >- enum: >- mediatek,mt8186-disp-dither > + - mediatek,mt8188-disp-dither >- mediatek,mt8192-disp-dither >- mediatek,mt8195-disp-dither >- const: mediatek,mt8183-disp-dither > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y > aml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y > aml > index a89ea0ea7542..3d6e20f6eb05 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y > aml > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y > aml > @@ -12,7 +12,7 @@ maintainers: > > description: | >Mediatek display gamma correction, namely GAMMA, provides a > nonlinear > - operation used to adjust luminance in
Re: [RFC PATCH 2/2] drm/mediatek: add mtk8195 hdmi display driver
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
> drivers/gpu/drm/mediatek/mtk_hdmi_common.c| 219 +-
> drivers/gpu/drm/mediatek/mtk_hdmi_common.h| 24 +-
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c| 1835
> +
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h| 26 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c| 530 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h| 20 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h | 329 +++
> 9 files changed, 2932 insertions(+), 62 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h
>
> diff --git a/drivers/gpu/drm/mediatek/Kconfig
> b/drivers/gpu/drm/mediatek/Kconfig
> index 0df75bceb74e..76cc402cbd75 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -31,3 +31,12 @@ config DRM_MEDIATEK_HDMI
> help
> DRM/KMS HDMI driver for Mediatek SoCs
[snip]
> +
> +static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter, struct
> i2c_msg *msgs,
> + int num)
> +{
> + struct mtk_hdmi_ddc *ddc = adapter->algo_data;
> + struct device *dev = adapter->dev.parent;
> + int ret;
> + int i;
> +
> + if (!ddc)
> + return -EINVAL;
> +
> + for (i = 0; i < num; i++) {
> + struct i2c_msg *msg = [i];
> +
> + if (msg->flags & I2C_M_RD)
> + ret = fg_ddc_data_read(ddc, msg->addr, msg-
> >buf[0],
> + (msg->len), >buf[0]);
> + else
> + ret = fg_ddc_data_write(ddc, msg->addr, msg-
> >buf[0],
> + (msg->len - 1),
> >buf[1]);
Why do you use msg->buf[1]? In mt8173 hdmi ddc driver,
mtk_hdmi_ddc_write_msg() just use msg->buf[0]. If using msg->buf[1] is
advance function, separate this advance function to another patch.
Regards,
CK
> +
> + if (ret <= 0)
> + goto xfer_end;
> + }
> +
> + return i;
> +
> +xfer_end:
> + dev_err(dev, "ddc failed! : %d\n", ret);
> + return ret;
> +}
> +
Re: [v1,2/3] drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c
Hi, Xinlei:
On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote:
> From: xinlei lee
>
> Add the compatible of mt8186-dsi because we use different cmdq
> addresses in mt8186.
Reviewed-by: CK Hu
>
> Signed-off-by: Xinlei Lee
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index e91b3ff..62af60d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1151,6 +1151,12 @@ static const struct mtk_dsi_driver_data
> mt8183_dsi_driver_data = {
> .has_size_ctl = true,
> };
>
> +static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
> + .reg_cmdq_off = 0xd00,
> + .has_shadow_ctl = true,
> + .has_size_ctl = true,
> +};
> +
> static const struct of_device_id mtk_dsi_of_match[] = {
> { .compatible = "mediatek,mt2701-dsi",
> .data = _dsi_driver_data },
> @@ -1158,6 +1164,8 @@ static const struct of_device_id
> mtk_dsi_of_match[] = {
> .data = _dsi_driver_data },
> { .compatible = "mediatek,mt8183-dsi",
> .data = _dsi_driver_data },
> + { .compatible = "mediatek,mt8186-dsi",
> + .data = _dsi_driver_data },
> { },
> };
> MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
Re: [v1, 1/3] dt-bindings: display: mediatek: dsi: add documentation for MT8186 SoC
Hi, Xinlei: On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote: > From: xinlei lee > > Add binding documentation for the MT8186 SoC. DPI has a yaml format document, so I would like DSI also has a yaml format document. Please send a patch to transfer DSI document to yaml, and then apply this patch to yaml document. Regards, CK > > Signed-off-by: Xinlei Lee > --- > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > index 36b0145..c82b8b2 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -7,7 +7,7 @@ channel output. > > Required properties: > - compatible: "mediatek,-dsi" > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > +- the supported chips are mt2701, mt7623, mt8167, mt8173, mt8183 and > mt8186. > - reg: Physical base address and length of the controller's > registers > - interrupts: The interrupt signal from the function block. > - clocks: device clocks
Re: [v1, 3/3] drm/mediatek: Move the getting bridge node function to mtk_dsi_bind
Hi, Xinlei:
On Thu, 2022-01-27 at 19:42 +0800, xinlei@mediatek.com wrote:
> From: xinlei lee
>
> The order of probe function for bridge drivers and dsi drivers is
> uncertain.
> To avoid the dsi probe cannot be executed, we place getting bridge
> node function in
> mtk_dsi_bind.
It seems this patch want to fix the same problem as [1]. Does [1] fix
your problem? If so, let's ignore this patch.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220127143623.123025-1-angelogioacchino.delre...@collabora.com/
Regards,
CK
>
> Signed-off-by:Xinlei Lee
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 29 +++-
> -
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 62af60d..a390f26 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -991,6 +991,21 @@ static int mtk_dsi_bind(struct device *dev,
> struct device *master, void *data)
> int ret;
> struct drm_device *drm = data;
> struct mtk_dsi *dsi = dev_get_drvdata(dev);
> + struct drm_panel *panel;
> +
> + ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> + , >next_bridge);
> + if (ret)
> + return ret;
> +
> + if (panel) {
> + dsi->next_bridge = devm_drm_panel_bridge_add(dev,
> panel);
> + if (IS_ERR(dsi->next_bridge)) {
> + ret = PTR_ERR(dsi->next_bridge);
> + dev_err(dev, "failed to add bridge: %d\n",
> ret);
> + return ret;
> + }
> + }
>
> ret = mtk_dsi_encoder_init(drm, dsi);
> if (ret)
> @@ -1016,7 +1031,6 @@ static int mtk_dsi_probe(struct platform_device
> *pdev)
> {
> struct mtk_dsi *dsi;
> struct device *dev = >dev;
> - struct drm_panel *panel;
> struct resource *regs;
> int irq_num;
> int ret;
> @@ -1033,19 +1047,6 @@ static int mtk_dsi_probe(struct
> platform_device *pdev)
> return ret;
> }
>
> - ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> - , >next_bridge);
> - if (ret)
> - goto err_unregister_host;
> -
> - if (panel) {
> - dsi->next_bridge = devm_drm_panel_bridge_add(dev,
> panel);
> - if (IS_ERR(dsi->next_bridge)) {
> - ret = PTR_ERR(dsi->next_bridge);
> - goto err_unregister_host;
> - }
> - }
> -
> dsi->driver_data = of_device_get_match_data(dev);
>
> dsi->engine_clk = devm_clk_get(dev, "engine");
Re: [RFC PATCH 2/2] drm/mediatek: add mtk8195 hdmi display driver
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
> drivers/gpu/drm/mediatek/mtk_hdmi_common.c| 219 +-
> drivers/gpu/drm/mediatek/mtk_hdmi_common.h| 24 +-
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c| 1835
> +
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h| 26 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c| 530 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h| 20 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h | 329 +++
> 9 files changed, 2932 insertions(+), 62 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h
>
>
[snip]
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> index f60b5b8bf99e..a58946d3848b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> @@ -25,12 +25,17 @@
>
> #include
>
> +//TODO: see what can be done here... :-/
> +#include "mtk_mt8195_hdmi_ddc.h"
> +#include "mtk_mt8195_hdmi.h"
> #include "mtk_cec.h"
> #include "mtk_hdmi.h"
>
> struct mtk_hdmi_conf {
> bool tz_disabled;
> bool cea_modes_only;
> + bool is_mt8195;
> + bool low_power;
> unsigned long max_mode_clock;
> };
>
> @@ -127,6 +132,17 @@ enum hdmi_aud_channel_swap_type {
> HDMI_AUD_SWAP_LR_STATUS,
> };
>
> +enum mtk_hdmi_clk_id_mt8195 {
> + MTK_MT8195_HDMI_CLK_UNIVPLL_D6D4,
> + MTK_MT8195_HDMI_CLK_MSDCPLL_D2,
> + MTK_MT8195_HDMI_CLK_HDMI_APB_SEL,
> + MTK_MT8195_HDMI_UNIVPLL_D4D8,
> + MTK_MT8195_HDIM_HDCP_SEL,
> + MTK_MT8195_HDMI_HDCP_24M_SEL,
> + MTK_MT8195_HDMI_VPP_SPLIT_HDMI,
> + MTK_MT8195_HDMI_CLK_COUNT,
> +};
> +
> enum mtk_hdmi_clk_id_mt8183 {
> MTK_MT8183_HDMI_CLK_HDMI_PIXEL,
> MTK_MT8183_HDMI_CLK_HDMI_PLL,
> @@ -136,6 +152,7 @@ enum mtk_hdmi_clk_id_mt8183 {
> };
>
> extern const char *const
> mtk_hdmi_clk_names_mt8183[MTK_MT8183_HDMI_CLK_COUNT];
> +extern const char *const
> mtk_hdmi_clk_names_mt8195[MTK_MT8195_HDMI_CLK_COUNT];
>
> enum hdmi_hpd_state {
> HDMI_PLUG_OUT = 0,
> @@ -160,7 +177,8 @@ struct mtk_hdmi {
> const struct mtk_hdmi_conf *conf;
> struct phy *phy;
> struct i2c_adapter *ddc_adpt;
> - struct clk *clk[MTK_MT8183_HDMI_CLK_COUNT];
> + //TODO: array size is max(MTK_MT8183_HDMI_CLK_COUNT,
> MTK_MT8195_HDMI_CLK_COUNT)... dynamically allocate instead?
> + struct clk *clk[MTK_MT8195_HDMI_CLK_COUNT];
> struct drm_display_mode mode;
> bool dvi_mode;
> struct regmap *sys_regmap;
> @@ -228,9 +246,13 @@ int mtk_drm_hdmi_probe(struct platform_device
> *pdev);
> int mtk_drm_hdmi_remove(struct platform_device *pdev);
>
> //TODO: do better than this? function pointers?
> +extern const struct drm_bridge_funcs mtk_mt8195_hdmi_bridge_funcs;
> extern const struct drm_bridge_funcs mtk_mt8183_hdmi_bridge_funcs;
> void mtk_hdmi_output_init_mt8183(struct mtk_hdmi *hdmi);
> +void mtk_hdmi_output_init_mt8195(struct mtk_hdmi *hdmi);
> +void mtk_hdmi_clk_disable_mt8195(struct mtk_hdmi *hdmi);
> void mtk_hdmi_clk_disable_mt8183(struct mtk_hdmi *hdmi);
> +void set_hdmi_codec_pdata_mt8195(struct hdmi_codec_pdata
> *codec_data);
> void set_hdmi_codec_pdata_mt8183(struct hdmi_codec_pdata
> *codec_data);
>
> #endif //_MTK_HDMI_COMMON_H
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> new file mode 100644
> index ..3fa928b79ed2
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> @@ -0,0 +1,1835 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre, SAS
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_mt8195_hdmi.h"
> +#include "mtk_hdmi_common.h"
> +#include "mtk_mt8195_hdmi_ddc.h"
> +#include "mtk_mt8195_hdmi_regs.h"
> +
> +#define RGB444_8bit BIT(0)
> +#define RGB444_10bit BIT(1)
> +#define RGB444_12bit BIT(2)
> +#define RGB444_16bit BIT(3)
> +
> +#define YCBCR444_8bit BIT(4)
> +#define YCBCR444_10bit BIT(5)
> +#define YCBCR444_12bit BIT(6)
> +#define YCBCR444_16bit BIT(7)
> +
> +#define YCBCR422_8bit_NO_SUPPORT BIT(8)
> +#define
Re: [PATCH v11 21/22] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
Hi, Nancy:
On Mon, 2022-01-10 at 16:46 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 36430f956b4f..e851c56f00b1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -190,6 +190,14 @@ static const enum mtk_ddp_comp_id
> mt8195_mtk_ddp_main[] = {
> DDP_COMPONENT_DP_INTF0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_ADAPTOR,
> + DDP_COMPONENT_MERGE5,
> + DDP_COMPONENT_DP_INTF1,
> +};
> +
> +static const int mt8195_vdosys1_mtk_cmdq_mbox[] = {-1, 0, -1};
What does this array mean? These number looks so magic.
Regards,
CK
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -254,6 +262,14 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys0_driver_data = {
> .mmsys_dev_num = 2,
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> + .ext_path = mt8195_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
> + .mmsys_id = 1,
> + .mmsys_dev_num = 2,
> + .mbox_index = mt8195_vdosys1_mtk_cmdq_mbox,
> +};
> +
> static const struct of_device_id mtk_drm_of_ids[] = {
> { .compatible = "mediatek,mt2701-mmsys",
> .data = _mmsys_driver_data},
> @@ -271,6 +287,8 @@ static const struct of_device_id mtk_drm_of_ids[]
> = {
> .data = _mmsys_driver_data},
> { .compatible = "mediatek,mt8195-vdosys0",
> .data = _vdosys0_driver_data},
> + { .compatible = "mediatek,mt8195-vdosys1",
> + .data = _vdosys1_driver_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
Re: [PATCH v1, 1/1] soc: mediatek: cmdq: add cmdq_pkt_poll_addr function
Hi, Yongqiang:
On Thu, 2022-01-20 at 15:43 +0800, Yongqiang Niu wrote:
> From: mtk18742
>
> add cmdq_pkt_poll_addr function in cmdq helper functions
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 39
>
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h| 2 ++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 3c8e4212d941..6c5cfb284140 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -344,6 +344,45 @@ int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16
> event)
> }
> EXPORT_SYMBOL(cmdq_pkt_set_event);
>
> +s32 cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, u32 value, u32 addr,
> u32 mask, u8 reg_gpr)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + s32 err;
> +
> + if (mask != 0x) {
> + inst.op = CMDQ_CODE_MASK;
> + inst.mask = ~mask;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + return err;
> +
> + addr = addr | 0x1;
> + }
> +
> + /* Move extra handle APB address to GPR */
> + inst.op = CMDQ_CODE_MOVE;
> + inst.value = addr;
> + inst.sop = reg_gpr;
> + inst.dst_t = 1;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + pr_err("%s fail append command move addr to reg
> err:%d",
> + __func__, err);
cmdq_pkt_assign() could assign a value to GPR, so remove this part.
> +
> + inst.op = CMDQ_CODE_POLL;
> + inst.value = value;
> + inst.sop = reg_gpr;
> + inst.dst_t = 1;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err != 0)
> + pr_err("%s fail append command poll err:%d",
> + __func__, err);
> +
> + return err;
> +}
> +EXPORT_SYMBOL(cmdq_pkt_poll_addr);
> +
> int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value)
> {
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 44365aab043c..a27329fd7c7f 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -54,6 +54,7 @@
> */
> enum cmdq_code {
> CMDQ_CODE_MASK = 0x02,
> + CMDQ_CODE_MOVE = 0x02,
> CMDQ_CODE_WRITE = 0x04,
> CMDQ_CODE_POLL = 0x08,
> CMDQ_CODE_JUMP = 0x10,
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index ac6b5f3cba95..28dc5ce0ff03 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -280,4 +280,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
> int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb
> cb,
>void *data);
>
Add comment for this function, parameters, and return value like other
interface.
Regards,
CK
> +s32 cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, u32 value, u32 addr,
> u32 mask, u8 reg_gpr);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v7 5/8] drm/mediatek: dpi: Add dpintf support
Hi, Guillaume:
On Fri, 2021-12-17 at 16:08 +0100, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> dpintf is the displayport interface hardware unit. This unit is
> similar
> to dpi and can reuse most of the code.
>
> This patch adds support for mt8195-dpintf to this dpi driver. Main
> differences are:
> - Some features/functional components are not available for dpintf
>which are now excluded from code execution once is_dpintf is set
> - dpintf can and needs to choose between different clockdividers
> based
>on the clockspeed. This is done by choosing a different clock
> parent.
> - There are two additional clocks that need to be managed. These are
>only set for dpintf and will be set to NULL if not supplied. The
>clk_* calls handle these as normal clocks then.
> - Some register contents differ slightly between the two components.
> To
>work around this I added register bits/masks with a DPINTF_ prefix
>and use them where different.
>
> Based on a separate driver for dpintf created by
> Jason-JH.Lin .
>
> Signed-off-by: Markus Schneider-Pargmann
> Signed-off-by: Guillaume Ranquet
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delre...@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 304
>
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 6 files changed, 299 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 4554e2de14309..fbc43ea4049b9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format {
> MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
> };
>
> +enum TVDPLL_CLK {
> + TVDPLL_PLL = 0,
> + TVDPLL_D2 = 2,
> + TVDPLL_D4 = 4,
> + TVDPLL_D8 = 8,
> + TVDPLL_D16 = 16,
> +};
> +
> struct mtk_dpi {
> struct drm_encoder encoder;
> struct drm_bridge bridge;
> @@ -71,8 +79,10 @@ struct mtk_dpi {
> void __iomem *regs;
> struct device *dev;
> struct clk *engine_clk;
> + struct clk *dpi_ck_cg;
> struct clk *pixel_clk;
> struct clk *tvd_clk;
> + struct clk *pclk_src[5];
> int irq;
> struct drm_display_mode mode;
> const struct mtk_dpi_conf *conf;
> @@ -125,6 +135,18 @@ struct mtk_dpi_conf {
> bool edge_sel_en;
> const u32 *output_fmts;
> u32 num_output_fmts;
> + bool is_ck_de_pol;
Seperate is_ck_de_pol to an independent patch.
> + bool is_dpintf;
Ditto for is_dpintf. And I would like change the name to what this
actually do.
> + bool csc_support;
Ditto for csc_support.
> + bool swap_input_support;
Ditto for swap_input_support.
> + // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
/* ... */
> (no shift)
> + u32 dimension_mask;
Ditto for dimension_mask.
> + // Mask used for HSIZE and VSIZE (no shift)
> + u32 hvsize_mask;
Ditto for hvsize_mask.
> + u32 channel_swap_shift;
Ditto for channel_swap_shift.
> + u32 yuv422_en_bit;
Ditto for yuv422_en_bit.
> + u32 csc_enable_bit;
Ditto for csc_enable_bit.
> + const struct mtk_dpi_yc_limit *limit;
Ditto for limit.
> };
>
>
> +
> +static const struct mtk_dpi_conf mt8195_dpintf_conf = {
> + .cal_factor = mt8195_dpintf_calculate_factor,
> + .output_fmts = mt8195_output_fmts,
> + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
> + .is_dpintf = true,
> + .csc_support = true,
For every SoC, csc_support is true. Why do we need csc_support?
Regards,
CK
> + .dimension_mask = DPINTF_HPW_MASK,
> + .hvsize_mask = DPINTF_HSIZE_MASK,
> + .channel_swap_shift = DPINTF_CH_SWAP,
> + .yuv422_en_bit = DPINTF_YUV422_EN,
> + .csc_enable_bit = DPINTF_CSC_ENABLE,
> + .limit = _dpintf_limit,
> };
>
>
Re: [RFC PATCH 2/2] drm/mediatek: add mtk8195 hdmi display driver
Hi, Guillaume:
On Mon, 2021-11-08 at 01:08 +0100, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
> Change-Id: I6399dec26cfe56a338c2ca96989cb7cbd14e292b
> ---
> drivers/gpu/drm/mediatek/Kconfig |9 +
> drivers/gpu/drm/mediatek/Makefile |2 +
> drivers/gpu/drm/mediatek/mtk_hdmi_common.c| 219 +-
> drivers/gpu/drm/mediatek/mtk_hdmi_common.h| 24 +-
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c| 1835
> +
> drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h| 26 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c| 530 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h| 20 +
> .../gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h | 329 +++
> 9 files changed, 2932 insertions(+), 62 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_ddc.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8195_hdmi_regs.h
>
> diff --git a/drivers/gpu/drm/mediatek/Kconfig
> b/drivers/gpu/drm/mediatek/Kconfig
> index 0df75bceb74e..76cc402cbd75 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -31,3 +31,12 @@ config DRM_MEDIATEK_HDMI
> help
> DRM/KMS HDMI driver for Mediatek SoCs
>
> +config DRM_MEDIATEK_HDMI_MT8195_SUSPEND_LOW_POWER
> + tristate "DRM HDMI SUSPEND LOW POWER Support for Mediatek
> mt8195 SoCs"
> + depends on DRM_MEDIATEK_HDMI
> + help
> + DRM/KMS HDMI SUSPEND_LOW_POWER for Mediatek SoCs.
> + Choose this option if you want to disable/enable
> + clock and power domain when platform enter suspend,
> + and this config depends on DRM_MEDIATEK_HDMI.
> +
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 107b6fbbdbf7..477c0648643c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -26,6 +26,8 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
> mtk_hdmi.o \
> mtk_hdmi_ddc.o \
> mtk_hdmi_common.o \
> + mtk_mt8195_hdmi.o \
> + mtk_mt8195_hdmi_ddc.o \
>
> obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> index 3c38a3e73920..19083be0978a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> @@ -1,5 +1,15 @@
> #include "mtk_hdmi_common.h"
>
> +const char *const
> mtk_hdmi_clk_names_mt8195[MTK_MT8195_HDMI_CLK_COUNT] = {
> + [MTK_MT8195_HDMI_CLK_UNIVPLL_D6D4] = "univpll_d6_d4",
> + [MTK_MT8195_HDMI_CLK_MSDCPLL_D2] = "msdcpll_d2",
> + [MTK_MT8195_HDMI_CLK_HDMI_APB_SEL] = "hdmi_apb_sel",
> + [MTK_MT8195_HDMI_UNIVPLL_D4D8] = "univpll_d4_d8",
> + [MTK_MT8195_HDIM_HDCP_SEL] = "hdcp_sel",
> + [MTK_MT8195_HDMI_HDCP_24M_SEL] = "hdcp24_sel",
> + [MTK_MT8195_HDMI_VPP_SPLIT_HDMI] = "split_hdmi",
> +};
> +
> const char * const
> mtk_hdmi_clk_names_mt8183[MTK_MT8183_HDMI_CLK_COUNT] = {
> [MTK_MT8183_HDMI_CLK_HDMI_PIXEL] = "pixel",
> [MTK_MT8183_HDMI_CLK_HDMI_PLL] = "pll",
> @@ -138,6 +148,18 @@ int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi
> *hdmi, u8 *buffer, size_t bufsz
> return err;
> }
>
> + if(hdmi->conf && hdmi->conf->is_mt8195) {
> + frame.colorimetry = hdmi->colorimtery;
> + //no need, since we cannot support other extended
> colorimetry?
> + if (frame.colorimetry == HDMI_COLORIMETRY_EXTENDED)
> + frame.extended_colorimetry = hdmi-
> >extended_colorimetry;
Separate colorimetry related part to an independent patch and use hdmi-
>conf->colorimetry_support instead of hdmi->conf->is_mt8195.
> +
> + /* quantiation range:limited or full */
> + if (frame.colorspace == HDMI_COLORSPACE_RGB)
> + frame.quantization_range = hdmi-
> >quantization_range;
> + else
> + frame.ycc_quantization_range = hdmi-
> >ycc_quantization_range;
> + }
> err = hdmi_avi_infoframe_pack(, buffer, bufsz);
>
> if (err < 0) {
> @@ -155,6 +177,11 @@ void mtk_hdmi_send_infoframe(struct mtk_hdmi
> *hdmi, u8 *buffer_spd, size_t bufsz
> mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd,
> "mediatek", "On-chip HDMI");
> }
>
> +static struct mtk_hdmi_ddc *hdmi_ddc_ctx_from_mtk_hdmi(struct
> mtk_hdmi *hdmi)
> +{
> + return container_of(hdmi->ddc_adpt, struct mtk_hdmi_ddc, adap);
> +}
> +
> int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
> struct platform_device *pdev, const
> char *const *clk_names, size_t num_clocks)
> {
> @@ -173,39 +200,41
Re: [PATCH v11 20/22] drm/mediatek: add drm ovl_adaptor sub driver for MT8195
Hi, Nancy:
On Mon, 2022-01-10 at 16:46 +0800, Nancy.Lin wrote:
> Add drm ovl_adaptor sub driver. Bring up ovl_adaptor sub driver if
> the component exists in the path.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 41 +++--
>
> 4 files changed, 62 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index fe2871aca859..62529a954b62 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -877,15 +877,13 @@ int mtk_drm_crtc_create(struct drm_device
> *drm_dev,
> node = priv->comp_node[comp_id];
> comp = >ddp_comp[comp_id];
>
> - if (!node) {
if (!node && comp_id != MTK_DISP_OVL_ADAPTOR)
> - dev_info(dev,
> - "Not creating crtc %d because
> component %d is disabled or missing\n",
> - crtc_i, comp_id);
> - return 0;
> - }
> -
> - if (!comp->dev) {
> - dev_err(dev, "Component %pOF not
> initialized\n", node);
> + /* Not all drm components have a DTS device node, such
> as ovl_adaptor,
> + * which is the drm bring up sub driver
> + */
> + if (!node && !comp->dev) {
> + dev_err(dev,
> + "Not creating crtc %d because component
> %d is disabled, missing or not initialized\n",
> + crtc_i, comp_id);
> return -ENODEV;
> }
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 26d197da41c0..ce40bab9c56b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -385,6 +385,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe
> = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
> + .clk_enable = mtk_ovl_adaptor_clk_enable,
> + .clk_disable = mtk_ovl_adaptor_clk_disable,
> + .config = mtk_ovl_adaptor_config,
> + .start = mtk_ovl_adaptor_start,
> + .stop = mtk_ovl_adaptor_stop,
> + .layer_nr = mtk_ovl_adaptor_layer_nr,
> + .layer_config = mtk_ovl_adaptor_layer_config,
> + .enable_vblank = mtk_ovl_adaptor_enable_vblank,
> + .disable_vblank = mtk_ovl_adaptor_disable_vblank,
> +};
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] =
> {
> [MTK_DISP_AAL] = "aal",
> [MTK_DISP_BLS] = "bls",
> @@ -398,6 +410,7 @@ static const char * const
> mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OD] = "od",
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> + [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
> [MTK_DISP_POSTMASK] = "postmask",
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_RDMA] = "rdma",
> @@ -443,6 +456,7 @@ static const struct mtk_ddp_comp_match
> mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0,
> _ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1,
> _ovl },
> [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2,
> _ovl },
> + [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR,
> 0, _ovl_adaptor },
> [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0,
> _postmask },
> [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0,
> NULL },
> [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1,
> NULL },
> @@ -548,12 +562,17 @@ int mtk_ddp_comp_init(struct device_node *node,
> struct mtk_ddp_comp *comp,
>
> comp->id = comp_id;
> comp->funcs = mtk_ddp_matches[comp_id].funcs;
> - comp_pdev = of_find_device_by_node(node);
> - if (!comp_pdev) {
> - DRM_INFO("Waiting for device %s\n", node->full_name);
> - return -EPROBE_DEFER;
> + /* Not all drm components have a DTS device node, such as
> ovl_adaptor,
> + * which is the drm bring up sub driver
> + */
> + if (node) {
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + DRM_INFO("Waiting for device %s\n", node-
> >full_name);
> + return -EPROBE_DEFER;
> + }
> + comp->dev = _pdev->dev;
> }
> - comp->dev = _pdev->dev;
>
> /* Only DMA capable components need the LARB property */
> if (type == MTK_DISP_OVL ||
> @@ -573,6 +592,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
>
Re: [PATCH v2] drm/mediatek: mtk_dsi: Avoid EPROBE_DEFER loop with external bridge
Hi, Angelo:
On Tue, 2022-01-04 at 10:59 +0100, AngeloGioacchino Del Regno wrote:
> DRM bridge drivers are now attaching their DSI device at probe time,
> which requires us to register our DSI host in order to let the bridge
> to probe: this recently started producing an endless -EPROBE_DEFER
> loop on some machines that are using external bridges, like the
> parade-ps8640, found on the ACER Chromebook R13.
>
> Now that the DSI hosts/devices probe sequence is documented, we can
> do adjustments to the mtk_dsi driver as to both fix now and make sure
> to avoid this situation in the future: for this, following what is
> documented in drm_bridge.c, move the mtk_dsi component_add() to the
> mtk_dsi_ops.attach callback and delete it in the detach callback;
> keeping in mind that we are registering a drm_bridge for our DSI,
> which is only used/attached if the DSI Host is bound, it wouldn't
> make sense to keep adding our bridge at probe time (as it would
> be useless to have it if mtk_dsi_ops.attach() fails!), so also move
> that one to the dsi host attach function (and remove it in detach).
This patch looks good to me, but please add 'Fixes' tag to note to
which patch this patch want to fix.
Regards,
CK
>
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delre...@collabora.com>
> Reviewed-by: Andrzej Hajda
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 167 +++--
>
> 1 file changed, 84 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..bced4c7d668e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -786,18 +786,101 @@ void mtk_dsi_ddp_stop(struct device *dev)
> mtk_dsi_poweroff(dsi);
> }
>
> +static int mtk_dsi_encoder_init(struct drm_device *drm, struct
> mtk_dsi *dsi)
> +{
> + int ret;
> +
> + ret = drm_simple_encoder_init(drm, >encoder,
> + DRM_MODE_ENCODER_DSI);
> + if (ret) {
> + DRM_ERROR("Failed to encoder init to drm\n");
> + return ret;
> + }
> +
> + dsi->encoder.possible_crtcs =
> mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev);
> +
> + ret = drm_bridge_attach(>encoder, >bridge, NULL,
> + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + if (ret)
> + goto err_cleanup_encoder;
> +
> + dsi->connector = drm_bridge_connector_init(drm, >encoder);
> + if (IS_ERR(dsi->connector)) {
> + DRM_ERROR("Unable to create bridge connector\n");
> + ret = PTR_ERR(dsi->connector);
> + goto err_cleanup_encoder;
> + }
> + drm_connector_attach_encoder(dsi->connector, >encoder);
> +
> + return 0;
> +
> +err_cleanup_encoder:
> + drm_encoder_cleanup(>encoder);
> + return ret;
> +}
> +
> +static int mtk_dsi_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + int ret;
> + struct drm_device *drm = data;
> + struct mtk_dsi *dsi = dev_get_drvdata(dev);
> +
> + ret = mtk_dsi_encoder_init(drm, dsi);
> + if (ret)
> + return ret;
> +
> + return device_reset_optional(dev);
> +}
> +
> +static void mtk_dsi_unbind(struct device *dev, struct device
> *master,
> +void *data)
> +{
> + struct mtk_dsi *dsi = dev_get_drvdata(dev);
> +
> + drm_encoder_cleanup(>encoder);
> +}
> +
> +static const struct component_ops mtk_dsi_component_ops = {
> + .bind = mtk_dsi_bind,
> + .unbind = mtk_dsi_unbind,
> +};
> +
> static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
> struct mipi_dsi_device *device)
> {
> struct mtk_dsi *dsi = host_to_dsi(host);
> + struct device *dev = host->dev;
> + int ret;
>
> dsi->lanes = device->lanes;
> dsi->format = device->format;
> dsi->mode_flags = device->mode_flags;
> + dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0,
> 0);
> + if (IS_ERR(dsi->next_bridge))
> + return PTR_ERR(dsi->next_bridge);
> +
> + drm_bridge_add(>bridge);
> +
> + ret = component_add(host->dev, _dsi_component_ops);
> + if (ret) {
> + DRM_ERROR("failed to add dsi_host component: %d\n",
> ret);
> + drm_bridge_remove(>bridge);
> + return ret;
> + }
>
> return 0;
> }
>
> +static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
> +struct mipi_dsi_device *device)
> +{
> + struct mtk_dsi *dsi = host_to_dsi(host);
> +
> + component_del(host->dev, _dsi_component_ops);
> + drm_bridge_remove(>bridge);
> + return 0;
> +}
> +
> static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
> {
> int ret;
> @@ -938,73 +1021,14 @@ static ssize_t mtk_dsi_host_transfer(struct
> mipi_dsi_host *host,
>
> static const struct mipi_dsi_host_ops mtk_dsi_ops = {
> .attach =
Re: [PATCH v10 19/22] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
Hi, Nancy:
On Wed, 2021-12-08 at 10:44 +0800, Nancy.Lin wrote:
> MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
> The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
> only one drm driver register as the drm device.
> Each drm driver binds its own component. The last bind drm driver
> allocates and registers the drm device to drm core.
> Each crtc path is created with the corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 24 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 300 ++--
>
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 10 +-
> 4 files changed, 246 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index d661edf7e0fe..fe2871aca859 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -847,21 +847,28 @@ static int mtk_drm_crtc_init_comp_planes(struct
> drm_device *drm_dev,
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> - const enum mtk_ddp_comp_id *path, unsigned int
> path_len)
> + const enum mtk_ddp_comp_id *path, unsigned int
> path_len,
> + int priv_data_index)
> {
> struct mtk_drm_private *priv = drm_dev->dev_private;
> struct device *dev = drm_dev->dev;
> struct mtk_drm_crtc *mtk_crtc;
> unsigned int num_comp_planes = 0;
> - int pipe = priv->num_pipes;
> int ret;
> int i;
> bool has_ctm = false;
> uint gamma_lut_size = 0;
> + struct drm_crtc *tmp;
> + int crtc_i = 0;
>
> if (!path)
> return 0;
>
> + priv = priv->all_drm_private[priv_data_index];
> +
> + drm_for_each_crtc(tmp, drm_dev)
> + crtc_i++;
> +
> for (i = 0; i < path_len; i++) {
> enum mtk_ddp_comp_id comp_id = path[i];
> struct device_node *node;
> @@ -873,7 +880,7 @@ int mtk_drm_crtc_create(struct drm_device
> *drm_dev,
> if (!node) {
> dev_info(dev,
>"Not creating crtc %d because
> component %d is disabled or missing\n",
> - pipe, comp_id);
> + crtc_i, comp_id);
> return 0;
> }
>
> @@ -926,29 +933,28 @@ int mtk_drm_crtc_create(struct drm_device
> *drm_dev,
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc,
> i,
> - pipe);
> + crtc_i);
> if (ret)
> return ret;
> }
>
> - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
> + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
> if (ret < 0)
> return ret;
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(_crtc->base,
> gamma_lut_size);
> drm_crtc_enable_color_mgmt(_crtc->base, 0, has_ctm,
> gamma_lut_size);
> - priv->num_pipes++;
> mutex_init(_crtc->hw_lock);
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + i = (priv->data->mbox_index) ? priv->data-
> >mbox_index[drm_crtc_index(_crtc->base)] : 0;
> mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
> mtk_crtc->cmdq_client.client.tx_block = false;
> mtk_crtc->cmdq_client.client.knows_txdone = true;
> mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
> mtk_crtc->cmdq_client.chan =
> - mbox_request_channel(_crtc-
> >cmdq_client.client,
> - drm_crtc_index(_crtc-
> >base));
> + mbox_request_channel(_crtc-
> >cmdq_client.client, i);
I really do not understand how does i work. Could you give an example
of the i value for mt8173 crtc0, mt8173 crtc1, and all mt8195 crtcs.
> if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
> dev_dbg(dev, "mtk_crtc %d failed to create mailbox
> client, writing register by CPU now\n",
> drm_crtc_index(_crtc->base));
> @@ -958,7 +964,7 @@ int mtk_drm_crtc_create(struct drm_device
> *drm_dev,
> if (mtk_crtc->cmdq_client.chan) {
> ret = of_property_read_u32_index(priv->mutex_node,
>"mediatek,gce-events",
> - drm_crtc_index(_cr
> tc->base),
> + i,
>_crtc-
> >cmdq_event);
> if (ret) {
> dev_dbg(dev, "mtk_crtc %d failed to get
> mediatek,gce-events property\n",
>
[snip]
>
> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
>
Re: [PATCH v10 15/22] drm/mediatek: add display merge async reset control
Hi, Nancy: On Wed, 2021-12-08 at 10:44 +0800, Nancy.Lin wrote: > Add merge async reset control in mtk_merge_stop. Async hw doesn't do > self > reset on each sof signal(start of frame), so need to reset the async > to > clear the hw status for the next merge start. Reviewed-by: CK Hu > > Signed-off-by: Nancy.Lin > --- > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > index 9dca145cfb71..177473fa8160 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > > #include "mtk_drm_ddp_comp.h" > @@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev) > struct mtk_disp_merge *priv = dev_get_drvdata(dev); > > mtk_merge_stop_cmdq(dev, NULL); > + > + if (priv->async_clk) > + device_reset_optional(dev); > } > > void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt > *cmdq_pkt)
Re: [PATCH v7 7/8] drm/mediatek: Add mt8195 DisplayPort driver
Hi, Guillaume:
This is a big patch, so I give you some comment first, and I would
continue to review this patch.
On Fri, 2021-12-17 at 16:08 +0100, Guillaume Ranquet wrote:
> From: Markus Schneider-Pargmann
>
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports the mt8195, the external DisplayPort units. It offers
> hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with
> up
> to 4 lanes.
>
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
>
> This driver is based on an initial version by
> Jason-JH.Lin .
>
> Signed-off-by: Markus Schneider-Pargmann
> Signed-off-by: Guillaume Ranquet
> Reported-by: kernel test robot
> ---
> drivers/gpu/drm/mediatek/Kconfig |7 +
> drivers/gpu/drm/mediatek/Makefile |2 +
> drivers/gpu/drm/mediatek/mtk_dp.c | 3028
>
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 568 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c |1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h |1 +
> 6 files changed, 3607 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h
>
> diff --git a/drivers/gpu/drm/mediatek/Kconfig
> b/drivers/gpu/drm/mediatek/Kconfig
> index 2976d21e9a34a..029b94c716131 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -28,3 +28,10 @@ config DRM_MEDIATEK_HDMI
> select PHY_MTK_HDMI
> help
> DRM/KMS HDMI driver for Mediatek SoCs
> +
> +config MTK_DPTX_SUPPORT
> + tristate "DRM DPTX Support for Mediatek SoCs"
> + depends on DRM_MEDIATEK
> + select PHY_MTK_DP
> + help
> + DRM/KMS Display Port driver for Mediatek SoCs.
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 29098d7c8307c..d86a6406055e6 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -21,3 +21,5 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
> mtk_hdmi_ddc.o
>
> obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +
> +obj-$(CONFIG_MTK_DPTX_SUPPORT) += mtk_dp.o
>
[snip]
> +
> +enum mtk_dp_train_state {
> + MTK_DP_TRAIN_STATE_STARTUP = 0,
> + MTK_DP_TRAIN_STATE_CHECKCAP,
> + MTK_DP_TRAIN_STATE_CHECKEDID,
> + MTK_DP_TRAIN_STATE_TRAINING_PRE,
> + MTK_DP_TRAIN_STATE_TRAINING,
> + MTK_DP_TRAIN_STATE_CHECKTIMING,
> + MTK_DP_TRAIN_STATE_NORMAL,
> + MTK_DP_TRAIN_STATE_POWERSAVE,
Never be this state, so remove it.
> + MTK_DP_TRAIN_STATE_DPIDLE,
> +};
> +
> +struct mtk_dp_timings {
> + struct videomode vm;
> +
> + u16 htotal;
> + u16 vtotal;
> + u8 frame_rate;
> + u32 pix_rate_khz;
> +};
> +
> +struct mtk_dp_train_info {
> + bool tps3;
> + bool tps4;
> + bool sink_ssc;
> + bool cable_plugged_in;
> + bool cable_state_change;
> + bool cr_done;
> + bool eq_done;
> +
> + // link_rate is in multiple of 0.27Gbps
> + int link_rate;
> + int lane_count;
> +
> + int irq_status;
> + int check_cap_count;
> +};
> +
>
[snip]
>
> +
> +static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp)
> +{
> + u32 irq_status = mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_35D0) &
> + SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK;
> +
> + if (irq_status) {
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8,
> irq_status,
> +SW_IRQ_CLR_DP_TRANS_P0_MASK);
SW_IRQ_CLR_DP_TRANS_P0_MASK is already set, so this setting is
redundant, so remove this.
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8, 0,
> +SW_IRQ_CLR_DP_TRANS_P0_MASK);
> + }
> +
> + return irq_status;
> +}
> +
> +static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
> +{
> + u8 irq_status = (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) &
> + IRQ_STATUS_DP_TRANS_P0_MASK) >>
> + IRQ_STATUS_DP_TRANS_P0_SHIFT;
> +
> + if (irq_status) {
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
> irq_status,
> +IRQ_CLR_DP_TRANS_P0_MASK);
IRQ_CLR_DP_TRANS_P0_MASK is already set, so this setting is redundant,
so remove this.
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418, 0,
> +IRQ_CLR_DP_TRANS_P0_MASK);
> + }
> +
> + return irq_status;
> +}
> +
> +static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
> +{
> + u32 val = 0;
> +
> + if (!enable)
> + val = IRQ_MASK_DP_TRANS_P0_DISC_IRQ |
Re: [PATCH v3 12/15] drm/mediatek: add display MDP RDMA support for MT8195
Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin
> ---
[snip]
> +
> +#define MDP_RDMA_EN0x000
> +#define FLD_ROT_ENABLEREG_FLD(1, 0)
I would like the bitwise definition has one more indent than the byte
definition.
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10BREG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define FLD_PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBERREG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIGREG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMATREG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORMREG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WBREG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WPREG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLDREG_FLD(15, 17)
> +#define FLD_TARGET_LINE_ENREG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SELREG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_00xf00
> +#define FLD_SRC_BASE_0REG_FLD(32, 0)
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +
[snip]
> +
> +static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt
> *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int pre_ultra_h = 156;
> + unsigned int pre_ultra_l = 104;
Give the reason why this value. You could refer to merge [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210819022327.13040-13-jason-jh@mediatek.com/
> + unsigned int reg_mask;
> + unsigned int reg_val;
> + unsigned int reg;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, 1) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_ULTRA_EN, 0) |
> + REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> +REG_FLD_MASK(FLD_COMMAND_DIV) |
> +REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> +REG_FLD_MASK(FLD_ULTRA_EN) |
> +REG_FLD_MASK(FLD_PRE_ULTRA_EN) |
> +REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> +
Re: [PATCH v8 12/13] drm/mediatek: add MERGE support for mediatek-drm
Hi, Jason:
On Thu, 2021-08-19 at 10:23 +0800, jason-jh.lin wrote:
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin
> ---
[snip]
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> + int ret = 0;
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + pr_err("merge clk prepare enable failed\n");
> +
> + if (priv->async_clk) {
This checking is redundant.
> + ret = clk_prepare_enable(priv->async_clk);
> + if (ret)
> + pr_err("async clk prepare enable failed\n");
> + }
> +
> + return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->async_clk)
Ditto.
Regards,
CK
> + clk_disable_unprepare(priv->async_clk);
> +
> + clk_disable_unprepare(priv->clk);
> +}
> +
Re: [RFC PATCH 1/5] dt-bindings: mediatek,dpi: Add mt8195 dpintf
Hi, Markus: On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote: > DP_INTF is similar to the actual dpi. They differ in some points > regarding registers and what needs to be set but the function blocks > itself are similar in design. > > Signed-off-by: Markus Schneider-Pargmann > --- > .../display/mediatek/mediatek,dpi.yaml| 48 --- > 1 file changed, 42 insertions(+), 6 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > index dd2896a40ff0..de4bdacd83ac 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > @@ -4,7 +4,7 @@ > $id: > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml*__;Iw!!CTRNKA9wMg0ARbw!z5TyPvbq3ZLHjRPscOHigUMlikjhtJMFrEQqemcjQZa4NaXBE9tzMnDFMa1qYg$ > > $schema: > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!z5TyPvbq3ZLHjRPscOHigUMlikjhtJMFrEQqemcjQZa4NaXBE9tzMnAjuBCxsg$ > > > -title: mediatek DPI Controller Device Tree Bindings > +title: mediatek DPI/DP_INTF Controller Device Tree Bindings > > maintainers: >- CK Hu > @@ -13,7 +13,8 @@ maintainers: > description: | >The Mediatek DPI function block is a sink of the display subsystem and >provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel > - output bus. > + output bus. The Mediatek DP_INTF is a similar function block that is > + connected to the (embedded) display port function block. > > properties: >compatible: > @@ -23,6 +24,7 @@ properties: >- mediatek,mt8173-dpi >- mediatek,mt8183-dpi >- mediatek,mt8192-dpi > + - mediatek,mt8195-dpintf I've reviewed the modification in driver, it seems that dpintf is almost the same as dpi. Why use the name "dpintf"? I could accept this name only it's defined by hardware data sheet. Regards, CK > >reg: > maxItems: 1 > @@ -37,10 +39,11 @@ properties: >- description: DPI PLL > >clock-names: > -items: > - - const: pixel > - - const: engine > - - const: pll > +description: > + For dpi clocks pixel, engine and pll are required. For dpintf pixel, > pll, > + pll_d2, pll_d4, pll_d8, pll_d16, hf_fmm, hf_fdp are required. > +minItems: 3 > +maxItems: 8 > >pinctrl-0: true >pinctrl-1: true > @@ -64,6 +67,39 @@ required: >- clock-names >- port > > +allOf: > + - if: > + properties: > +compatible: > + contains: > +enum: > + - mediatek,mt8195-dpintf > +then: > + properties: > +clocks: > + minItems: 8 > + maxItems: 8 > +clock-names: > + items: > +- const: pixel > +- const: pll > +- const: pll_d2 > +- const: pll_d4 > +- const: pll_d8 > +- const: pll_d16 > +- const: hf_fmm > +- const: hf_fdp > +else: > + properties: > +clocks: > + minItems: 3 > + maxItems: 3 > +clock-names: > + items: > +- const: pixel > +- const: engine > +- const: pll > + > additionalProperties: false > > examples:
Re: [RFC PATCH 5/5] drm/mediatek: Add mt8195 DisplayPort driver
Hi, Markus: On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote: > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports both functional units on the mt8195, the embedded > DisplayPort as well as the external DisplayPort units. It offers > hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up > to 4 lanes. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > --- > drivers/gpu/drm/mediatek/Kconfig |7 + > drivers/gpu/drm/mediatek/Makefile |2 + > drivers/gpu/drm/mediatek/mtk_dp.c | 3025 > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 3095 + > 4 files changed, 6129 insertions(+) > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h > > diff --git a/drivers/gpu/drm/mediatek/Kconfig > b/drivers/gpu/drm/mediatek/Kconfig > index 2976d21e9a34..d81eb3521c1c 100644 > --- a/drivers/gpu/drm/mediatek/Kconfig > +++ b/drivers/gpu/drm/mediatek/Kconfig > @@ -28,3 +28,10 @@ config DRM_MEDIATEK_HDMI > select PHY_MTK_HDMI > help > DRM/KMS HDMI driver for Mediatek SoCs > + > +config MTK_DPTX_SUPPORT > + tristate "DRM DPTX Support for Mediatek SoCs" > + depends on DRM_MEDIATEK > + select GENERIC_PHY Why select GENERIC_PHY? If this is a phy driver, place this driver in drivers/phy/mediatek/ Regards, CK > + help > + DRM/KMS Display Port driver for Mediatek SoCs. > diff --git a/drivers/gpu/drm/mediatek/Makefile > b/drivers/gpu/drm/mediatek/Makefile > index dc54a7a69005..6b9d148ab7fe 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -20,3 +20,5 @@ mediatek-drm-hdmi-objs := mtk_cec.o \ > mtk_hdmi_ddc.o >
Re: [RFC PATCH 2/5] drm/mediatek: dpi: Add dpintf support
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> dpintf is the displayport interface hardware unit. This unit is similar
> to dpi and can reuse most of the code.
>
> This patch adds support for mt8195-dpintf to this dpi driver. Main
> differences are:
> - Some features/functional components are not available for dpintf
>which are now excluded from code execution once is_dpintf is set
> - dpintf can and needs to choose between different clockdividers based
>on the clockspeed. This is done by choosing a different clock parent.
> - There are two additional clocks that need to be managed. These are
>only set for dpintf and will be set to NULL if not supplied. The
>clk_* calls handle these as normal clocks then.
> - Some register contents differ slightly between the two components. To
>work around this I added register bits/masks with a DPINTF_ prefix
>and use them where different.
>
> Based on a separate driver for dpintf created by
> Jason-JH.Lin .
>
> Signed-off-by: Markus Schneider-Pargmann
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 282
> drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 +
> 2 files changed, 247 insertions(+), 47 deletions(-)
>
[snip]
>
> +static void mtk_dpi_set_pixel_clk_parent(struct mtk_dpi *dpi,
> + unsigned int factor)
> +{
> + struct clk *new_parent;
> +
> + switch (factor) {
> + case 16:
> + new_parent = dpi->tvd_clks[MTK_DPI_TVDPLL_D16].clk;
> + break;
> + case 8:
> + new_parent = dpi->tvd_clks[MTK_DPI_TVDPLL_D8].clk;
> + break;
> + case 4:
> + new_parent = dpi->tvd_clks[MTK_DPI_TVDPLL_D4].clk;
> + break;
> + case 2:
> + new_parent = dpi->tvd_clks[MTK_DPI_TVDPLL_D2].clk;
> + break;
> + default:
> + new_parent = NULL;
> + }
> + if (new_parent)
> + clk_set_parent(dpi->pixel_clk, new_parent);
I prefer that dpi->pixel_clk provide set_rate() interface, and let clock
driver to control the parent of dpi->pixel_clk.
Regards,
CK
> +}
> +
> static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> struct drm_display_mode *mode)
> {
> @@ -465,6 +568,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> drm_display_mode_to_videomode(mode, );
> pll_rate = vm.pixelclock * factor;
>
> + mtk_dpi_set_pixel_clk_parent(dpi, factor);
> +
> dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> pll_rate, vm.pixelclock);
>
Re: [RFC PATCH 5/5] drm/mediatek: Add mt8195 DisplayPort driver
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
>
> It supports both functional units on the mt8195, the embedded
> DisplayPort as well as the external DisplayPort units. It offers
> hot-plug-detection, audio up to 8 channels, and DisplayPort 1.4 with up
> to 4 lanes.
>
> This driver is based on an initial version by
> Jason-JH.Lin .
>
> Signed-off-by: Markus Schneider-Pargmann
> ---
[snip]
> +
> +static const struct of_device_id mtk_dp_of_match[] = {
> + {
> + .compatible = "mediatek,mt8195-dp_tx",
Where is the binding document of "mediatek,mt8195-dp_tx"?
> + .data = _dp_driver_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-edp_tx",
Where is the binding document of "mediatek,mt8195-edp_tx"?
> + .data = _edp_driver_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
> +
> +struct platform_driver mtk_dp_driver = {
> + .probe = mtk_dp_probe,
> + .remove = mtk_dp_remove,
> + .driver = {
> + .name = "mediatek-drm-dp",
> + .of_match_table = mtk_dp_of_match,
> + .pm = _dp_pm_ops,
> + },
> +};
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> new file mode 100644
> index ..83afc79d98ff
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -0,0 +1,3095 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre
> + */
> +#ifndef _MTK_DP_REG_H_
> +#define _MTK_DP_REG_H_
> +
> +#define MTK_DP_SIP_CONTROL_AARCH32 0x82000523
> +# define MTK_DP_SIP_ATF_VIDEO_UNMUTE 0x20
> +# define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE 0x21
> +# define MTK_DP_SIP_ATF_REG_WRITE 0x22
> +# define MTK_DP_SIP_ATF_REG_READ 0x23
> +# define MTK_DP_SIP_ATF_CMD_COUNT 0x24
> +
> +#define TOP_OFFSET 0x2000
> +#define ENC0_OFFSET 0x3000
> +#define ENC1_OFFSET 0x3200
> +#define TRANS_OFFSET 0x3400
> +#define AUX_OFFSET 0x3600
> +#define SEC_OFFSET 0x4000
> +
> +#define MTK_DP_HPD_DISCONNECTBIT(1)
> +#define MTK_DP_HPD_CONNECT BIT(2)
> +#define MTK_DP_HPD_INTERRUPT BIT(3)
> +
> +#define MTK_DP_ENC0_P0_3000 (ENC0_OFFSET + 0x000)
> +# define LANE_NUM_DP_ENC0_P0_MASK 0x3
> +# define LANE_NUM_DP_ENC0_P0_SHIFT 0
> +# define VIDEO_MUTE_SW_DP_ENC0_P0_MASK 0x4
> +# define VIDEO_MUTE_SW_DP_ENC0_P0_SHIFT2
> +# define VIDEO_MUTE_SEL_DP_ENC0_P0_MASK0x8
> +# define VIDEO_MUTE_SEL_DP_ENC0_P0_SHIFT 3
> +# define ENHANCED_FRAME_EN_DP_ENC0_P0_MASK 0x10
> +# define ENHANCED_FRAME_EN_DP_ENC0_P0_SHIFT4
> +# define HDCP_FRAME_EN_DP_ENC0_P0_MASK 0x20
> +# define HDCP_FRAME_EN_DP_ENC0_P0_SHIFT5
> +# define IDP_EN_DP_ENC0_P0_MASK0x40
Remove useless definition.
Regards,
CK.
> +# define IDP_EN_DP_ENC0_P0_SHIFT 6
> +# define BS_SYMBOL_CNT_RESET_DP_ENC0_P0_MASK 0x80
> +# define BS_SYMBOL_CNT_RESET_DP_ENC0_P0_SHIFT 7
> +# define MIXER_DUMMY_DATA_DP_ENC0_P0_MASK 0xff00
> +# define MIXER_DUMMY_DATA_DP_ENC0_P0_SHIFT 8
> +
> +
> +#endif /*_MTK_DP_REG_H_*/
Re: [PATCH v2 14/14] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
Hi, Nancy:
On Thu, 2021-07-22 at 17:45 +0800, Nancy.Lin wrote:
> Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
> multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
> up two drm drivers, only one drm driver register as the drm device.
> Each drm driver binds its own component. The first bind drm driver
> will allocate the drm device, and the last bind drm driver registers
> the drm device to drm core. Each crtc path is created with the
> corresponding drm driver data.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 378
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +-
> 7 files changed, 356 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 768c282d2d63..829570308761 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -4,6 +4,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -106,6 +107,9 @@ void mtk_merge_stop(struct device *dev)
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> mtk_ddp_write(NULL, 0x0, >cmdq_reg, priv->regs,
> DISP_REG_MERGE_CTRL);
> +
> + if (priv->async_clk)
> + device_reset_optional(dev);
Move this to the merge patch [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729170737.21424-7-jason-jh@mediatek.com/
> }
>
> static int mtk_merge_check_params(struct mtk_merge_config_struct
> *merge_config)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 40df2c823187..3324fa1a9e8c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -737,21 +737,28 @@ static int mtk_drm_crtc_init_comp_planes(struct
> drm_device *drm_dev,
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> - const enum mtk_ddp_comp_id *path, unsigned int path_len)
> + const enum mtk_ddp_comp_id *path, unsigned int path_len,
> + int priv_data_index)
> {
> struct mtk_drm_private *priv = drm_dev->dev_private;
> struct device *dev = drm_dev->dev;
> struct mtk_drm_crtc *mtk_crtc;
> unsigned int num_comp_planes = 0;
> - int pipe = priv->num_pipes;
> int ret;
> int i;
> bool has_ctm = false;
> uint gamma_lut_size = 0;
> + struct drm_crtc *tmp;
> + int crtc_i = 0;
>
> if (!path)
> return 0;
>
> + priv = priv->all_drm_private[priv_data_index];
> +
> + drm_for_each_crtc(tmp, drm_dev)
> + crtc_i++;
> +
> for (i = 0; i < path_len; i++) {
> enum mtk_ddp_comp_id comp_id = path[i];
> struct device_node *node;
> @@ -760,7 +767,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> if (!node) {
> dev_info(dev,
>"Not creating crtc %d because component %d is
> disabled or missing\n",
> - pipe, comp_id);
> + crtc_i, comp_id);
> return 0;
> }
> }
> @@ -816,19 +823,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
> - pipe);
> + crtc_i);
> if (ret)
> return ret;
> }
>
> - ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
> + ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
> if (ret < 0)
> return ret;
>
> if (gamma_lut_size)
> drm_mode_crtc_set_gamma_size(_crtc->base, gamma_lut_size);
> drm_crtc_enable_color_mgmt(_crtc->base, 0, has_ctm, gamma_lut_size);
> - priv->num_pipes++;
> mutex_init(_crtc->hw_lock);
>
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 66d1cf03dfe8..0646fafffd8b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -31,7 +31,8 @@
> void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> - unsigned int path_len);
> + unsigned int path_len,
> + int
Re: [PATCH v3 2/2] dt-bindings: mediatek: add force_dsi_end_without_null for dsi
Hi, Jitao: On Mon, 2021-07-26 at 10:11 +0800, Jitao Shi wrote: > Some bridge chip will shift screen when the dsi data does't ent at > the same time in line. > > Signed-off-by: Jitao Shi > --- > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 > 1 file changed, 4 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > index 8238a86686be..1c2f53f3ac3d 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -19,6 +19,10 @@ Required properties: >Documentation/devicetree/bindings/graph.txt. This port should be connected >to the input port of an attached DSI panel or DSI-to-eDP encoder chip. > > +Optional properties: > +- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the > + packets on lanes aligned at the end. > + I think you should add this property in [1] because this limitation is ANX7625's limitation. [1] Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml Regards, CK > MIPI TX Configuration Module > >
Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin 於 2021年7月17日 週六 下午5:04寫道：
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics conversion in the
> > > external
> > > display path. It handles multiple HDR input types and performs tone
> > > mapping, color space/color format conversion, and then combines
> > > different layers, output the required HDR or SDR signal to the
> > > subsequent display path.
> > >
> > > Signed-off-by: Nancy.Lin
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_ethdr.c| 537
> > >
> > > drivers/gpu/drm/mediatek/mtk_ethdr.h| 20 +
> > > 8 files changed, 584 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> > >
> > > +
> > > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer =
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + if (idx < 4)
> > > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx),
> > > >cmdq_base,
> > > + mixer->regs, MIX_SRC_CON,
> > > BIT(idx));
> > > +}
> > > +
> > > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > > +struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer =
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + switch (idx) {
> > > + case 0:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, >cmdq_base,
> > > + mixer->regs, MIX_L0_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 1:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, >cmdq_base,
> > > + mixer->regs, MIX_L1_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 2:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, >cmdq_base,
> > > + mixer->regs, MIX_L2_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 3:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, >cmdq_base,
> > > + mixer->regs, MIX_L3_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + default:
> > > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > > + break;
> > > + }
> >
> > Why not just
> >
> >mtk_ddp_write_mask(cmdq_pkt, 0, >cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> >
>
> There are two modes in Mixer.
> 1. Background relay mode: all layers off
> 2. Normal mix mode: at least one layer on
> The timing of the two modes is different, so keep using the normal mix
> mode.
> Just set the layer region to 0 when the layer off.
layer_on() and layer_off() does different things. Comparing before turn
on a layer with after turn on->off a layer, the register setting are
different. I would like just restore the register.
Regards,
CK
>
> > > +}
> > > +
Re: [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
> layers. The four layers are blending at the EHTDR module next to it.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c| 655 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h| 1 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +
> 10 files changed, 1453 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index fcce08710cef..70b53487ab0c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_ethdr.o
> + mtk_ethdr.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 7227ffbc3eae..f5d35007b84d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> +unsigned int h, unsigned int vrefresh,
> +unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
> +
> int mtk_ethdr_clk_enable(struct device *dev);
> void mtk_ethdr_clk_disable(struct device *dev);
> void mtk_ethdr_config(struct device *dev, unsigned int w,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index ..8ec80e1887e0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,655 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_ethdr.h"
> +
> +#define DISP_MERGE_ENABLE0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_100x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_120x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_240x70
> +#define DISP_MERGE_CFG_250x74
> +#define DISP_MERGE_CFG_260x78
> +#define DISP_MERGE_CFG_270x7c
> +#define DISP_MERGE_MUTE_00xf00
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
> +#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
> +#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
> +#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> +
Re: [PATCH] drm/mediatek: mtk-dpi: Set out_fmt from config if not the last bridge
Hi, Hsin-yi:
On Mon, 2021-07-12 at 17:46 +0800, Hsin-Yi Wang wrote:
> atomic_get_output_bus_fmts() is only called when the bridge is the last
> element in the bridge chain.
>
> If mtk-dpi is not the last bridge, the format of output_bus_cfg is
> MEDIA_BUS_FMT_FIXED, and mtk_dpi_dual_edge() will fail to write correct
> value to regs.
Reviewed-by: CK Hu
>
> Fixes: ec8747c52434 ("drm/mediatek: dpi: Add bus format negotiation")
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index bced555648b01..25c565f9179cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -610,6 +610,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge
> *bridge,
>
> out_bus_format = bridge_state->output_bus_cfg.format;
>
> + if (out_bus_format == MEDIA_BUS_FMT_FIXED)
> + if (dpi->conf->num_output_fmts)
> + out_bus_format = dpi->conf->output_fmts[0];
> +
> dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
> bridge_state->input_bus_cfg.format,
> bridge_state->output_bus_cfg.format);
Re: [PATCH] drm/mediatek: dpi: fix NULL dereference in mtk_dpi_bridge_atomic_check
Hi, Frank:
On Mon, 2021-07-12 at 10:07 +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> bridge->driver_private is not set (NULL) so use bridge_to_dpi(bridge)
> like it's done in bridge_atomic_get_output_bus_fmts
Reviewed-by: CK Hu
>
> Fixes: ec8747c52434 ("drm/mediatek: dpi: Add bus format negotiation")
> Signed-off-by: Frank Wunderlich
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index bced555648b0..a2eca1f66984 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -605,7 +605,7 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge
> *bridge,
> struct drm_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> {
> - struct mtk_dpi *dpi = bridge->driver_private;
> + struct mtk_dpi *dpi = bridge_to_dpi(bridge);
> unsigned int out_bus_format;
>
> out_bus_format = bridge_state->output_bus_cfg.format;
Re: [PATCH] drm/mediatek: clear pending flag when cmdq packet is done.
Hi, Hsin-yi:
On Thu, 2021-04-22 at 19:10 +0800, Hsin-Yi Wang wrote:
> From: CK Hu
>
> In cmdq mode, packet may be flushed before it is executed, so
> the pending flag should be cleared after cmdq packet is done.
>
> Signed-off-by: CK Hu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +---
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> 2 files changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 40df2c823187..051bf0eb00d3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -224,6 +224,45 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct
> drm_crtc *crtc,
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> static void ddp_cmdq_cb(struct cmdq_cb_data data)
> {
> + struct cmdq_pkt *pkt = (struct cmdq_pkt *)data.data;
> + struct mtk_drm_crtc *mtk_crtc = (struct mtk_drm_crtc *)pkt->crtc;
> + struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
> + unsigned int i;
> +
> + if (data.sta == CMDQ_CB_ERROR)
I prefer use standard error status instead of proprietary one, so I send
a patch [1]. I would like this patch depend on [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210314233323.23377-2-chunkuang...@kernel.org/
> + goto destroy_pkt;
> +
> + if (state->pending_config) {
> + state->pending_config = false;
> + }
> +
> + if (mtk_crtc->pending_planes) {
> + for (i = 0; i < mtk_crtc->layer_nr; i++) {
> + struct drm_plane *plane = _crtc->planes[i];
> + struct mtk_plane_state *plane_state;
> +
> + plane_state = to_mtk_plane_state(plane->state);
> +
> + if (plane_state->pending.config)
> + plane_state->pending.config = false;
> + }
> + mtk_crtc->pending_planes = false;
> + }
> +
> + if (mtk_crtc->pending_async_planes) {
> + for (i = 0; i < mtk_crtc->layer_nr; i++) {
> + struct drm_plane *plane = _crtc->planes[i];
> + struct mtk_plane_state *plane_state;
> +
> + plane_state = to_mtk_plane_state(plane->state);
> +
> + if (plane_state->pending.async_config)
> + plane_state->pending.async_config = false;
> + }
> + mtk_crtc->pending_async_planes = false;
> + }
> +
> +destroy_pkt:
> cmdq_pkt_destroy(data.data);
> }
> #endif
> @@ -377,8 +416,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
> state->pending_height,
> state->pending_vrefresh, 0,
> cmdq_handle);
> -
> - state->pending_config = false;
> + if (!cmdq_handle)
> + state->pending_config = false;
> }
>
> if (mtk_crtc->pending_planes) {
> @@ -398,9 +437,11 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
> mtk_ddp_comp_layer_config(comp, local_layer,
> plane_state,
> cmdq_handle);
> - plane_state->pending.config = false;
> + if (!cmdq_handle)
> + plane_state->pending.config = false;
> }
> - mtk_crtc->pending_planes = false;
> + if (!cmdq_handle)
> + mtk_crtc->pending_planes = false;
> }
>
> if (mtk_crtc->pending_async_planes) {
> @@ -420,9 +461,11 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
> mtk_ddp_comp_layer_config(comp, local_layer,
> plane_state,
> cmdq_handle);
> - plane_state->pending.async_config = false;
> + if (!cmdq_handle)
> + plane_state->pending.async_config = false;
> }
> - mtk_crtc->pending_async_planes = false;
> + if (!cmdq_handle)
> + mtk_crtc->pending_async_planes = false;
> }
> }
>
> @@ -475,6 +518,7 @@ static void mtk_drm_crtc_update_config(struct
> mtk_drm_crtc *mtk_crtc,
>
Re: [PATCH v1, 3/3] drm/mediatek: gamma set with cmdq
Hi, Yongqiang:
On Mon, 2021-04-12 at 16:45 +0800, Yongqiang Niu wrote:
> On Mon, 2021-04-12 at 16:28 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> > > gamma lut set in vsync active will caused display flash issue
> > > set gamma lut with cmdq
> >
> > In MT8173, it's ok to set gammma out of vblank period. Why do you
> > setting gamma in vblank in this patch?
> >
> > Regards,
> > CK
> >
>
> mtk drm driver code has changed many since mt8173, there is no one test
> this in the newest version for mt8173.
>
> and this issue is random.
> https://partnerissuetracker.corp.google.com/u/1/issues/153842418
>
> and not all platform will set gamma lut.
> some project platform will not set gamma lut from chrome os
> (crhome os set gamma lut may be with some special panel, like AUO
> B116XTN02.3 in
> https://partnerissuetracker.corp.google.com/u/1/issues/153842418
> )
>
I could not see the page in partnelissuetracker, If this patch fix some
bug, describe the bug in commit message. It's better that information
include how to reproduce this bug and what kind of error happen. More
information would help us to understand why setting in vblank would fix
this bug.
Regards,
CK
> > >
> > > Signed-off-by: Yongqiang Niu
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 ++--
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 ---
> > > drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 11 ++-
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 +---
> > > 5 files changed, 28 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > index 64b4528..c8e178e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > @@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int
> > > w,
> > > mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> > > DISP_AAL_SIZE);
> > > }
> > >
> > > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> > > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt)
> > > {
> > > struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> > >
> > > if (aal->data && aal->data->has_gamma)
> > > - mtk_gamma_set_common(aal->regs, state);
> > > + mtk_gamma_set_common(aal->regs, >cmdq_reg, state,
> > > cmdq_pkt);
> > > }
> > >
> > > void mtk_aal_start(struct device *dev)
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > index 86c3068..c2e7dcb 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > @@ -14,7 +14,7 @@
> > > void mtk_aal_config(struct device *dev, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt);
> > > void mtk_aal_start(struct device *dev);
> > > void mtk_aal_stop(struct device *dev);
> > >
> > > @@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct
> > > cmdq_client_reg *cmdq_reg,
> > > void mtk_gamma_config(struct device *dev, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > > -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state
> > > *state);
> > > +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt);
> > > +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > + struct drm_crtc_state *state, struct cmdq_pkt
> > > *cmdq_pkt);
> > > void mtk_gamma_start(struct device *dev);
> > >
Re: [PATCH v1] drm/mediatek: adjust rdma fifo threshold calculate formula
Hi, Yongqiang: On Mon, 2021-04-12 at 15:25 +0800, Yongqiang Niu wrote: > the orginal formula will caused rdma fifo threshold config overflow > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaad..8c9371b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -167,7 +167,7 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* output threshold to 6 microseconds with 7/6 overhead to >* account for blanking, and with a pixel depth of 4 bytes: >*/ > - threshold = width * height * vrefresh * 4 * 7 / 100; > + threshold = rdma_fifo_size * 7 / 10; It's better to set threshold by width and height, but it seems that no one could come out a solution for all SoC. I could just accept this solution, but I need some addition comment for this solution. How do you decide 7/10? In the future, another may need to modify this value and he need to know why you use 7/10. If you just choose it at random, just tell us that you just randomly choose it. Regards, CK > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v1, 3/3] drm/mediatek: gamma set with cmdq
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> gamma lut set in vsync active will caused display flash issue
> set gamma lut with cmdq
In MT8173, it's ok to set gammma out of vblank period. Why do you
setting gamma in vblank in this patch?
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 ++--
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 11 ++-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 +---
> 5 files changed, 28 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> index 64b4528..c8e178e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> @@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int w,
> mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> DISP_AAL_SIZE);
> }
>
> -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_aal *aal = dev_get_drvdata(dev);
>
> if (aal->data && aal->data->has_gamma)
> - mtk_gamma_set_common(aal->regs, state);
> + mtk_gamma_set_common(aal->regs, >cmdq_reg, state,
> cmdq_pkt);
> }
>
> void mtk_aal_start(struct device *dev)
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 86c3068..c2e7dcb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -14,7 +14,7 @@
> void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> struct cmdq_pkt *cmdq_pkt);
> void mtk_aal_start(struct device *dev);
> void mtk_aal_stop(struct device *dev);
>
> @@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct
> cmdq_client_reg *cmdq_reg,
> void mtk_gamma_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct
> cmdq_pkt *cmdq_pkt);
> +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> + struct drm_crtc_state *state, struct cmdq_pkt
> *cmdq_pkt);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 3ebf91e..99a4ff3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -55,7 +55,8 @@ void mtk_gamma_clk_disable(struct device *dev)
> clk_disable_unprepare(gamma->clk);
> }
>
> -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> + struct drm_crtc_state *state, struct cmdq_pkt
> *cmdq_pkt)
> {
> unsigned int i, reg;
> struct drm_color_lut *lut;
> @@ -65,23 +66,23 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state)
> if (state->gamma_lut) {
> reg = readl(regs + DISP_GAMMA_CFG);
> reg = reg | GAMMA_LUT_EN;
> - writel(reg, regs + DISP_GAMMA_CFG);
> + mtk_ddp_write(cmdq_pkt, reg, cmdq_reg, regs, DISP_GAMMA_CFG);
> lut_base = regs + DISP_GAMMA_LUT;
> lut = (struct drm_color_lut *)state->gamma_lut->data;
> for (i = 0; i < MTK_LUT_SIZE; i++) {
> word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
> (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
> ((lut[i].blue >> 6) & LUT_10BIT_MASK);
> - writel(word, (lut_base + i * 4));
> + mtk_ddp_write(cmdq_pkt, word, cmdq_reg, regs, (lut_base
> + i * 4));
> }
> }
> }
>
> -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct
> cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
>
> -
Re: [PATCH v1, 1/3] drm/mediatek: Separate aal module
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> mt8183 aal has no gamma function
Separate this patch to two patch: one is add has_gamma config in aal.
another one is add mt8183 aal support.
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_aal.c | 167
>
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 39 +--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 187 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a..29098d7 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -mediatek-drm-y := mtk_disp_ccorr.o \
> +mediatek-drm-y := mtk_disp_aal.o \
> + mtk_disp_ccorr.o \
> mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> new file mode 100644
> index 000..64b4528
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_AAL_EN 0x
> +#define AAL_EN BIT(0)
> +#define DISP_AAL_SIZE0x0030
> +
> +
> +struct mtk_disp_aal_data {
> + bool has_gamma;
> +};
> +
> +/**
> + * struct mtk_disp_aal - DISP_AAL driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_aal {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_aal_data *data;
> +};
> +
> +int mtk_aal_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(aal->clk);
> +}
> +
> +void mtk_aal_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(aal->clk);
> +}
> +
> +void mtk_aal_config(struct device *dev, unsigned int w,
> +unsigned int h, unsigned int vrefresh,
> +unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> DISP_AAL_SIZE);
> +}
> +
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + if (aal->data && aal->data->has_gamma)
> + mtk_gamma_set_common(aal->regs, state);
> +}
> +
> +void mtk_aal_start(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + writel(AAL_EN, aal->regs + DISP_AAL_EN);
> +}
> +
> +void mtk_aal_stop(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, aal->regs + DISP_AAL_EN);
> +}
> +
> +static int mtk_disp_aal_bind(struct device *dev, struct device *master,
> +void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_aal_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_aal_component_ops = {
> + .bind = mtk_disp_aal_bind,
> + .unbind = mtk_disp_aal_unbind,
> +};
> +
> +static int mtk_disp_aal_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + struct mtk_disp_aal *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get aal clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap aal\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, >cmdq_reg, 0);
> + if (ret)
> +
Re: [PATCH 3/3] drm/mediatek: dpi: add bus format negociation
Hi, Jitao:
On Tue, 2021-03-30 at 23:53 +0800, Jitao Shi wrote:
> Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
> the possible output and input formats for the current mode and monitor,
> and use the negotiated formats in a basic atomic_check callback.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 96
> --
> 1 file changed, 91 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 87bb27649c4c..4e45d1b01b0c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -81,6 +81,8 @@ struct mtk_dpi {
> struct pinctrl *pinctrl;
> struct pinctrl_state *pins_gpio;
> struct pinctrl_state *pins_dpi;
> + unsigned int in_bus_format;
> + unsigned int out_bus_format;
Why do you keep these two value? You does not use them.
> bool ddr_edge_sel;
> int refcount;
> };
> @@ -534,6 +536,92 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> return 0;
> }
>
> +#define MAX_OUTPUT_SEL_FORMATS 2
> +
> +static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge
> *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + unsigned int *num_output_fmts)
> +{
> + struct drm_display_mode *mode = _state->mode;
> + u32 *output_fmts;
> + struct mtk_dpi *dpi = bridge_to_dpi(bridge);
> +
> + *num_output_fmts = 0;
> +
> + output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
> + GFP_KERNEL);
> + if (!output_fmts)
> + return NULL;
> +
> + /* Default 8bit RGB fallback */
> + if (dpi->conf->dual_edge) {
> + output_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
> + output_fmts[1] = MEDIA_BUS_FMT_RGB888_2X12_BE;
So mt8183 does not support MEDIA_BUS_FMT_RGB888_1X24?
> + *num_output_fmts = 2;
> + } else {
> + output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> + *num_output_fmts = 1;
> + }
> +
> + return output_fmts;
> +}
> +
> +#define MAX_INPUT_SEL_FORMATS1
> +
> +static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge
> *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + u32 output_fmt,
> + unsigned int *num_input_fmts)
> +{
> + u32 *input_fmts;
> +
> + *num_input_fmts = 0;
> +
> + input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> + GFP_KERNEL);
> + if (!input_fmts)
> + return NULL;
> +
> + *num_input_fmts = 1;
> + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> +
> + return input_fmts;
> +}
> +
> +static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
> +struct drm_bridge_state *bridge_state,
> +struct drm_crtc_state *crtc_state,
> +struct drm_connector_state *conn_state)
> +{
> + struct mtk_dpi *dpi = bridge->driver_private;
> +
> + dpi->out_bus_format = bridge_state->output_bus_cfg.format;
> +
> + dpi->in_bus_format = bridge_state->input_bus_cfg.format;
> +
> + dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
> + bridge_state->input_bus_cfg.format,
> + bridge_state->output_bus_cfg.format);
> +
> + if (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE ||
> + dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_BE) {
I think you could remove this 'if' checking.
Regards,
CK.
> + dpi->ddr_edge_sel =
> + (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ?
> + true : false;
> + }
> +
> + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
> + dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
> + dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
> + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
> +
> + return 0;
> +}
> +
> static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
>enum drm_bridge_attach_flags flags)
> {
> @@ -572,6 +660,9 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs
> = {
> .mode_set = mtk_dpi_bridge_mode_set,
> .disable = mtk_dpi_bridge_disable,
> .enable = mtk_dpi_bridge_enable,
> + .atomic_check = mtk_dpi_bridge_atomic_check,
> + .atomic_get_output_bus_fmts =
Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> add support for mediatek SOC MT8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 42 +++
> 4 files changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 141cb36b9c07b..3a53ebc4e1724 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data
> mt8183_ccorr_driver_data = {
> .matrix_bits = 10,
> };
>
> +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
> + .matrix_bits = 11,
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> { .compatible = "mediatek,mt8183-disp-ccorr",
> .data = _ccorr_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 961f87f8d4d15..e266baae586c4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data
> mt8183_ovl_2l_driver_data = {
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> + .smi_id_en = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> + .smi_id_en = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = _ovl_driver_data},
> @@ -464,6 +480,10 @@ static const struct of_device_id
> mtk_disp_ovl_driver_dt_match[] = {
> .data = _ovl_driver_data},
> { .compatible = "mediatek,mt8183-disp-ovl-2l",
> .data = _ovl_2l_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ovl",
> + .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ovl-2l",
> + .data = _ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8cf..f123fc00a3935 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data
> mt8183_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = _rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id
> mtk_disp_rdma_driver_dt_match[] = {
> .data = _rdma_driver_data},
> { .compatible = "mediatek,mt8183-disp-rdma",
> .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8192-disp-rdma",
> + .data = _rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b013d56d27773..6df551055630c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] =
> {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_POSTMASK0,
>
Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++-
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6c86673a835c3..141cb36b9c07b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -30,7 +30,7 @@
> #define DISP_CCORR_COEF_40x0090
>
> struct mtk_disp_ccorr_data {
> - u32 reserved;
> + u32 matrix_bits;
> };
>
> /**
> @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev)
> writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> }
>
> -/* Converts a DRM S31.32 value to the HW S1.10 format. */
> -static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +/* Converts a DRM S31.32 value to the HW S1.n format. */
> +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> {
> u16 r;
>
> /* Sign bit. */
> - r = in & BIT_ULL(63) ? BIT(11) : 0;
> + r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
>
> if ((in & GENMASK_ULL(62, 33)) > 0) {
> - /* identity value 0x1 -> 0x400, */
> + /* identity value 0x1 -> 0x400(mt8183), */
> + /* identity value 0x1 -> 0x800(mt8192), */
> /* if bigger this, set it to max 0x7ff. */
> - r |= GENMASK(10, 0);
> + r |= GENMASK(n, 0);
> } else {
> - /* take the 11 most important bits. */
> - r |= (in >> 22) & GENMASK(10, 0);
> + /* take the n+1 most important bits. */
> + r |= (in >> (32 - n)) & GENMASK(n, 0);
> }
>
> return r;
> @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> uint16_t coeffs[9] = { 0 };
> int i;
> struct cmdq_pkt *cmdq_pkt = NULL;
> + u32 matrix_bits = ccorr->data->matrix_bits;
>
> if (!blob)
> return;
> @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> input = ctm->matrix;
>
> for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
>
> mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
> @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
> + .matrix_bits = 10,
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8183-disp-ccorr"},
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
___
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dri-devel@lists.freedesktop.org
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Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 73 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index b6c4e73031ca6..0a84ae53eb72a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -64,6 +64,12 @@
>
> #define AAL_EN BIT(0)
>
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x)(((x) & 0x7) << 28)
> #define DITHER_OVFLW_BIT_R(x)(((x) & 0x7) << 24)
> @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev)
> writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> }
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const
> mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX]
> = {
> - [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL, 0, _aal },
> - [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL, 1, _aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, _ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, _color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, _color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER,0, _dither },
> - [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
> - [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
> - [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
> - [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
> - [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
> - [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
> - [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,
Re: [PATCH v5 6/8] drm/mediatek: add matrix_bits private data for ccorr
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 34 ---
> 1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6c86673a835c3..fb86f3a8b3a18 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -29,8 +29,10 @@
> #define DISP_CCORR_COEF_30x008C
> #define DISP_CCORR_COEF_40x0090
>
> +#define CCORR_MATRIX_BITS10
> +
> struct mtk_disp_ccorr_data {
> - u32 reserved;
> + u32 matrix_bits;
> };
>
> /**
> @@ -85,21 +87,22 @@ void mtk_ccorr_stop(struct device *dev)
> writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> }
>
> -/* Converts a DRM S31.32 value to the HW S1.10 format. */
> -static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +/* Converts a DRM S31.32 value to the HW S1.n format. */
> +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> {
> u16 r;
>
> /* Sign bit. */
> - r = in & BIT_ULL(63) ? BIT(11) : 0;
> + r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
>
> if ((in & GENMASK_ULL(62, 33)) > 0) {
> - /* identity value 0x1 -> 0x400, */
> + /* identity value 0x1 -> 0x400(mt8183), */
> + /* identity value 0x1 -> 0x800(mt8192), */
> /* if bigger this, set it to max 0x7ff. */
> - r |= GENMASK(10, 0);
> + r |= GENMASK(n, 0);
> } else {
> - /* take the 11 most important bits. */
> - r |= (in >> 22) & GENMASK(10, 0);
> + /* take the n+1 most important bits. */
> + r |= (in >> (32 - n)) & GENMASK(n, 0);
> }
>
> return r;
> @@ -114,6 +117,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> uint16_t coeffs[9] = { 0 };
> int i;
> struct cmdq_pkt *cmdq_pkt = NULL;
> + u32 matrix_bits;
>
> if (!blob)
> return;
> @@ -121,8 +125,13 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> ctm = (struct drm_color_ctm *)blob->data;
> input = ctm->matrix;
>
> + if (ccorr->data)
ccorr->data is always true, isn't it?
> + matrix_bits = ccorr->data->matrix_bits;
> + else
> + matrix_bits = CCORR_MATRIX_BITS;
> +
> for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
>
> mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
> @@ -199,8 +208,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
> + .matrix_bits = CCORR_MATRIX_BITS,
Drop CCORR_MATRIX_BITS and use 10 here.
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8183-disp-ccorr"},
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
___
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Re: [PATCH v5 5/8] drm/mediatek: Fix ccorr size config
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Fix setting to follow hardware datasheet. The original error setting
> affects mt8192 display.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6ee2431e6b843..6c86673a835c3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w,
> {
> struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, ccorr->regs,
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, ccorr->regs,
> DISP_CCORR_SIZE);
> mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, >cmdq_reg, ccorr->regs,
> DISP_CCORR_CFG);
___
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Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> ccorr ctm matrix bits will be different in mt8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 236 insertions(+), 96 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 13a0eafabf9c0..f119bef6d6e66 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -mediatek-drm-y := mtk_disp_color.o \
> +mediatek-drm-y := mtk_disp_ccorr.o \
> + mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_postmask.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> new file mode 100644
> index 0..6ee2431e6b843
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_CCORR_EN0x
> +#define CCORR_EN BIT(0)
> +#define DISP_CCORR_CFG 0x0020
> +#define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIPBIT(3)
> +#define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_00x0080
> +#define DISP_CCORR_COEF_10x0084
> +#define DISP_CCORR_COEF_20x0088
> +#define DISP_CCORR_COEF_30x008C
> +#define DISP_CCORR_COEF_40x0090
> +
> +struct mtk_disp_ccorr_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_ccorr - DISP_CCORR driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_ccorr {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_ccorr_data*data;
> +};
> +
> +int mtk_ccorr_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(ccorr->clk);
> +}
> +
> +void mtk_ccorr_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(ccorr->clk);
> +}
> +
> +void mtk_ccorr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, ccorr->regs,
> + DISP_CCORR_SIZE);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, >cmdq_reg, ccorr->regs,
> + DISP_CCORR_CFG);
> +}
> +
> +void mtk_ccorr_start(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
> +}
> +
> +void mtk_ccorr_stop(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> +}
> +
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x10
Re: [PATCH v5 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
It looks like that postmask driver could be placed in mtk_drm_ddp_comp.c
and this patch would much smaller.
Regards,
CK
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 149 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 204 insertions(+), 31 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index b64674b944860..13a0eafabf9c0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cdb0383f99061..06d4d4e1c0d05 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_postmask_clk_enable(struct device *dev);
> +void mtk_postmask_clk_disable(struct device *dev);
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_postmask_start(struct device *dev);
> +void mtk_postmask_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0..5a109fee6b238
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> +};
> +
> +int mtk_postmask_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(postmask->clk);
> +}
> +
> +void mtk_postmask_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(postmask->clk);
> +}
> +
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg,
> postmask->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + postmask->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_postmask_unbind(struct device *dev, struct
Re: [PATCH v4 7/8] soc: mediatek: add mtk mutex support for MT8192
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 35
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index 718a41beb6afb..dfd9806d5a001 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -39,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8192_MUTEX_MOD_DISP_OVL0 0
> +#define MT8192_MUTEX_MOD_DISP_OVL0_2L1
> +#define MT8192_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8192_MUTEX_MOD_DISP_COLOR0 4
> +#define MT8192_MUTEX_MOD_DISP_CCORR0 5
> +#define MT8192_MUTEX_MOD_DISP_AAL0 6
> +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
> +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
> +#define MT8192_MUTEX_MOD_DISP_DITHER09
> +#define MT8192_MUTEX_MOD_DISP_OVL2_2L16
> +#define MT8192_MUTEX_MOD_DISP_RDMA4 17
> +
> #define MT8183_MUTEX_MOD_DISP_RDMA0 0
> #define MT8183_MUTEX_MOD_DISP_RDMA1 1
> #define MT8183_MUTEX_MOD_DISP_OVL0 9
> @@ -214,6 +226,20 @@ static const unsigned int
> mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
> + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -275,6 +301,13 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> + .mutex_mod = mt8192_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8192-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
___
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Re: [PATCH v4 6/8] drm/mediatek: add matrix bits private data for ccorr
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> matrix bits of mt8183 is 12
> matrix bits of mt8192 is 13
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 0c68090eb1e92..1c7163a12f3b1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -31,8 +31,10 @@
> #define DISP_CCORR_COEF_30x008C
> #define DISP_CCORR_COEF_40x0090
>
> +#define CCORR_MATRIX_BITS12
> +
> struct mtk_disp_ccorr_data {
> - u32 reserved;
> + u32 matrix_bits;
> };
>
> /**
> @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> uint16_t coeffs[9] = { 0 };
> int i;
> struct cmdq_pkt *cmdq_pkt = NULL;
> + u32 matrix_bits;
>
> if (!blob)
> return;
> @@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> ctm = (struct drm_color_ctm *)blob->data;
> input = ctm->matrix;
>
> - for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + if (ccorr->data)
> + matrix_bits = ccorr->data->matrix_bits;
> + else
> + matrix_bits = CCORR_MATRIX_BITS;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
> coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> + if (matrix_bits > CCORR_MATRIX_BITS)
> + coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);
I think format of MT8192 ccorr coeffs is s1.11, after
mtk_ctm_s31_32_to_s1_10(), you lose one bit precision. So modify
mtk_ctm_s31_32_to_s1_10() to get maximum precision.
Regards,
CK
> + }
>
> mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
> @@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
> + .matrix_bits = CCORR_MATRIX_BITS,
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8183-disp-ccorr"},
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
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Re: [PATCH v4 2/8] drm/mediatek: add component POSTMASK
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
> On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > This patch add component POSTMASK,
> > >
> > > Signed-off-by: Yongqiang Niu
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile| 1 +
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > 7 files changed, 186 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > > b/drivers/gpu/drm/mediatek/Makefile
> > > index b64674b944860..13a0eafabf9c0 100644
> > > --- a/drivers/gpu/drm/mediatek/Makefile
> > > +++ b/drivers/gpu/drm/mediatek/Makefile
> > > @@ -3,6 +3,7 @@
> > > mediatek-drm-y := mtk_disp_color.o \
> > > mtk_disp_gamma.o \
> > > mtk_disp_ovl.o \
> > > + mtk_disp_postmask.o \
> > > mtk_disp_rdma.o \
> > > mtk_drm_crtc.o \
> > > mtk_drm_ddp_comp.o \
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > index 02191010699f8..d74e85db3fcdf 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> > > drm_crtc_state *state);
> > > void mtk_gamma_start(struct device *dev);
> > > void mtk_gamma_stop(struct device *dev);
> > >
> > > +int mtk_postmask_clk_enable(struct device *dev);
> > > +void mtk_postmask_clk_disable(struct device *dev);
> > > +void mtk_postmask_config(struct device *dev, unsigned int w,
> > > + unsigned int h, unsigned int vrefresh,
> > > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > +void mtk_postmask_start(struct device *dev);
> > > +void mtk_postmask_stop(struct device *dev);
> > > +
> > > void mtk_ovl_bgclr_in_on(struct device *dev);
> > > void mtk_ovl_bgclr_in_off(struct device *dev);
> > > void mtk_ovl_bypass_shadow(struct device *dev);
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> > > b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> > > new file mode 100644
> > > index 0..d640cef9c15a4
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> > > @@ -0,0 +1,161 @@
> > > +/*
> > > + * SPDX-License-Identifier:
> > > + *
> > > + * Copyright (c) 2020 MediaTek Inc.
> >
> > 2021
> >
> > > + */
> > > +
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +
> > > +#include "mtk_disp_drv.h"
> > > +#include "mtk_drm_crtc.h"
> > > +#include "mtk_drm_ddp_comp.h"
> > > +
> > > +#define DISP_POSTMASK_EN 0x
> > > +#define POSTMASK_EN BIT(0)
> > > +#define DISP_POSTMASK_CFG0x0020
> > > +#define POSTMASK_RELAY_MODE BIT(0)
> > > +#define DISP_POSTMASK_SIZE 0x0030
> > > +
> > > +struct mtk_disp_postmask_data {
> > > + u32 reserved;
> > > +};
> >
> > Useless, so remove.
> >
> > > +
> > > +/**
> > > + * struct mtk_disp_postmask - DISP_postmask driver structure
> > > + * @ddp_comp - structure containing type enum and hardware resources
> > > + * @crtc - associated crtc to report irq events to
> > > + */
> > > +struct mtk_disp_postmask {
> > > + struct clk *clk;
> > > + void __iomem *regs;
> > > + struct cmdq_client_reg cmdq_reg;
> > > + const struct mtk_disp_postmask_data *d
Re: [PATCH v4 4/8] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index da7e38a28759b..961f87f8d4d15 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -24,6 +24,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE0x0020
> #define DISP_REG_OVL_DATAPATH_CON0x0024
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data {
> unsigned int gmc_bits;
> unsigned int layer_nr;
> bool fmt_rgb565_is_0;
> + bool smi_id_en;
> };
>
> /**
> @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev)
> {
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
> }
>
> @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev)
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> +
> }
>
> void mtk_ovl_config(struct device *dev, unsigned int w,
___
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Re: [PATCH v4 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 186 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index b64674b944860..13a0eafabf9c0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 02191010699f8..d74e85db3fcdf 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_postmask_clk_enable(struct device *dev);
> +void mtk_postmask_clk_disable(struct device *dev);
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_postmask_start(struct device *dev);
> +void mtk_postmask_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0..d640cef9c15a4
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,161 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
2021
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
Useless, so remove.
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
> +int mtk_postmask_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(postmask->clk);
> +}
> +
> +void mtk_postmask_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(postmask->clk);
> +}
> +
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg,
> postmask->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + postmask->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + return 0;
> +}
> +
> +static void
Re: [PATCH v12 6/8] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ac2cb25620357..6c8f246380a74 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,6 +53,7 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
>
> #define LUT_10BIT_MASK 0x03ff
> @@ -314,9 +315,19 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> + bool enable = (bpc == 5 || bpc == 6);
I strongly believe that dither function in dither is identical to the
one in gamma and od, and in mtk_dither_set_common(), 'bpc >=
MTK_MIN_BPC' is valid, so I believe we need not to limit bpc to 5 or 6.
But we should consider the case that bpc is invalid in
mtk_dither_set_common(). Invalid case in gamma and od use different way
to process. For gamma, dither is default relay mode, so invalid bpc
would do nothing in mtk_dither_set_common() and result in relay mode.
For od, it set to relay mode first, them invalid bpc would do nothing in
mtk_dither_set_common() and result in relay mode. I would like dither,
gamma and od to process invalid bpc in the same way. One solution is to
set relay mode in mtk_dither_set_common() for invalid bpc.
Regards,
CK
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> + if (enable) {
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc,
> + DISP_DITHER_CFG, DITHER_ENGINE_EN,
> + cmdq_pkt);
> + } else {
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg,
> + priv->regs, DISP_DITHER_CFG);
> + }
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> + DISP_DITHER_SIZE);
> }
>
> static void mtk_dither_start(struct device *dev)
___
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Re: [PATCH v12 7/8] soc: mediatek: add mtk mutex support for MT8183
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..718a41beb6afb 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_MUTEX0_MOD0 0x30
> +#define MT8183_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static con
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
> wrote:
> >
> > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > > > Hi, Hsin-Yi:
> > > > >
> > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > > > From: Yongqiang Niu
> > > > > >
> > > > > > for 5 or 6 bpc panel, we need enable dither function
> > > > > > to improve the display quality
> > > > > >
> > > > > > Signed-off-by: Yongqiang Niu
> > > > > > Signed-off-by: Hsin-Yi Wang
> > > > > > ---
> > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44
> > > > > > -
> > > > > > 1 file changed, 43 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > index 8173f709272be..e85625704d611 100644
> > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > @@ -53,7 +53,9 @@
> > > > > > #define DITHER_EN BIT(0)
> > > > > > #define DISP_DITHER_CFG0x0020
> > > > > > #define DITHER_RELAY_MODE BIT(0)
> > > > > > +#define DITHER_ENGINE_EN BIT(1)
> > > > > > #define DISP_DITHER_SIZE 0x0030
> > > > > > +#define DITHER_REG(idx)(0x100 +
> > > > > > (idx) * 4)
> > > > > >
> > > > > > #define LUT_10BIT_MASK 0x03ff
> > > > > >
> > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device
> > > > > > *dev, unsigned int w,
> > > > > > {
> > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > > > >
> > > > > > + bool enable = false;
> > > > > > +
> > > > > > + /* default value for dither reg 5 to 14 */
> > > > > > + const u32 dither_setting[] = {
> > > > > > + 0x, /* 5 */
> > > > > > + 0x3002, /* 6 */
> > > > > > + 0x, /* 7 */
> > > > > > + 0x, /* 8 */
> > > > > > + 0x, /* 9 */
> > > > > > + 0x, /* 10 */
> > > > > > + 0x, /* 11 */
> > > > > > + 0x0011, /* 12 */
> > > > > > + 0x, /* 13 */
> > > > > > + 0x, /* 14 */
> > > > >
> > > > > Could you explain what is this?
> > > >
> > > > this is dither 5 to dither 14 setting
> > > > this will be useless, we just need set dither 5 and dither 7 like
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > > > other value is same with hardware default value.
> > > >
> > > >
> > > > >
> > > > > > + };
> > > > > > +
> > > > > > + if (bpc == 5 || bpc == 6) {
> > > > > > + enable = true;
> > > > > > + mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > > + DITHER_NEW_BIT_MODE,
> > > > > > + >cmdq_reg, priv->regs,
> > > > > > DITHER_REG(15));
> > > > > > + mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > >
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > for 5 or 6 bpc panel, we need enable dither function
> > > to improve the display quality
> > >
> > > Signed-off-by: Yongqiang Niu
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> > > 1 file changed, 43 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index 8173f709272be..e85625704d611 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -53,7 +53,9 @@
> > > #define DITHER_ENBIT(0)
> > > #define DISP_DITHER_CFG 0x0020
> > > #define DITHER_RELAY_MODEBIT(0)
> > > +#define DITHER_ENGINE_EN BIT(1)
> > > #define DISP_DITHER_SIZE 0x0030
> > > +#define DITHER_REG(idx) (0x100 + (idx) * 4)
> > >
> > > #define LUT_10BIT_MASK 0x03ff
> > >
> > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev,
> > > unsigned int w,
> > > {
> > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > >
> > > + bool enable = false;
> > > +
> > > + /* default value for dither reg 5 to 14 */
> > > + const u32 dither_setting[] = {
> > > + 0x, /* 5 */
> > > + 0x3002, /* 6 */
> > > + 0x, /* 7 */
> > > + 0x, /* 8 */
> > > + 0x, /* 9 */
> > > + 0x, /* 10 */
> > > + 0x, /* 11 */
> > > + 0x0011, /* 12 */
> > > + 0x, /* 13 */
> > > + 0x, /* 14 */
> >
> > Could you explain what is this?
>
> this is dither 5 to dither 14 setting
> this will be useless, we just need set dither 5 and dither 7 like
> mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> other value is same with hardware default value.
>
>
> >
> > > + };
> > > +
> > > + if (bpc == 5 || bpc == 6) {
> > > + enable = true;
> > > + mtk_ddp_write(cmdq_pkt,
> > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > + DITHER_NEW_BIT_MODE,
> > > + >cmdq_reg, priv->regs, DITHER_REG(15));
> > > + mtk_ddp_write(cmdq_pkt,
> > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> >
> > This result in 0x50505050, but previous version is 0x50504040, so this
> > version is correct and previous version is incorrect?
>
> the new version set r g b 3 channel same, seams more reasonable
>
>
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15,
DISP_DITHER_16 is identical to mtk_dither_set(), so call
mtk_dither_set() instead of duplication here.
Regards,
CK
> >
> > Regards,
> > CK
> >
> > > + >cmdq_reg, priv->regs, DITHER_REG(16));
> > > + }
> > > +
> > > +
> > > + if (enable) {
> > > + u32 idx;
> > > +
> > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> > > >cmdq_reg, priv->regs,
> > > + DITHER_REG(idx + 5));
> > > + }
> > > +
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> > > DISP_DITHER_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> > > DISP_DITHER_CFG);
> > > +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> > > DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > > }
> > >
> > > static void mtk_dither_start(struct device *dev)
> >
> >
>
>
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Re: [PATCH v11 3/9] drm/mediatek: add RDMA fifo size error handle
Hi, Hsin-Yi: On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add RDMA fifo size error handle > rdma fifo size will not always bigger than the calculated threshold > if that case happened, we need set fifo size as the threshold > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index b84004394970f..04b9542010b00 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* account for blanking, and with a pixel depth of 4 bytes: >*/ > threshold = width * height * vrefresh * 4 * 7 / 100; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; > + Please see the discussion in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6-git-send-email-yongqiang@mediatek.com/ Regards, CK > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 8/9] soc: mediatek: add mtk mutex support for MT8183
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..b348f962f82a4 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_DISP_MUTEX0_MOD0 0x30
> +#define MT8183_DISP_MUTEX0_SOF0 0x2c
Modify 'DISP_MUTEX' to 'MUTEX'
Regards,
CK
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
>
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8173f709272be..e85625704d611 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,7 +53,9 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
> +#define DITHER_REG(idx) (0x100 + (idx) * 4)
>
> #define LUT_10BIT_MASK 0x03ff
>
> @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> + bool enable = false;
> +
> + /* default value for dither reg 5 to 14 */
> + const u32 dither_setting[] = {
> + 0x, /* 5 */
> + 0x3002, /* 6 */
> + 0x, /* 7 */
> + 0x, /* 8 */
> + 0x, /* 9 */
> + 0x, /* 10 */
> + 0x, /* 11 */
> + 0x0011, /* 12 */
> + 0x, /* 13 */
> + 0x, /* 14 */
Could you explain what is this?
> + };
> +
> + if (bpc == 5 || bpc == 6) {
> + enable = true;
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_NEW_BIT_MODE,
> + >cmdq_reg, priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
This result in 0x50505050, but previous version is 0x50504040, so this
version is correct and previous version is incorrect?
Regards,
CK
> + >cmdq_reg, priv->regs, DITHER_REG(16));
> + }
> +
> +
> + if (enable) {
> + u32 idx;
> +
> + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> >cmdq_reg, priv->regs,
> + DITHER_REG(idx + 5));
> + }
> +
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct device *dev)
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Re: [PATCH v11 4/9] drm/mediatek: add mtk_dither_set_common() function
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
> Current implementation of mtk_dither_set() cast dev data to
> struct mtk_ddp_comp_dev. But other devices with different dev data
> would also call this function.
>
> Separate necessary parameters out so other device components (dither,
> gamma) can call this function.
Reviewed-by: CK Hu
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 46d199b7b4a29..c50d5fc9fd349 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_color_start(struct device *dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG,
> +struct cmdq_pkt *cmdq_pkt);
> +
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 7b5293429426d..53d25823a37cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG, struct cmdq_pkt
> *cmdq_pkt)
> +{
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - >cmdq_reg, priv->regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - >cmdq_reg, priv->regs, DISP_DITHER_16);
> - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, >cmdq_reg,
> priv->regs, CFG);
> + cmdq_reg, regs, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
> }
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc, CFG, cmdq_pkt);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > Modify the title's prefix to 'soc: mediatek:'
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > Add DDP support for MT8183 SoC.
> > >
> > > Signed-off-by: Yongqiang Niu
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/soc/mediatek/mtk-mutex.c | 50
> > > 1 file changed, 50 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > b/drivers/soc/mediatek/mtk-mutex.c
> > > index f531b119da7a9..f64e9c33e85ad 100644
> > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > @@ -14,6 +14,8 @@
> > >
> > > #define MT2701_MUTEX0_MOD0 0x2c
> > > #define MT2701_MUTEX0_SOF0 0x30
> > > +#define MT8183_DISP_MUTEX0_MOD0 0x30
> > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c
> >
> > Modify 'DISP_MUTEX' to 'MUTEX'
> >
> > >
> > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> > > #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> > > @@ -37,6 +39,18 @@
> > > #define MT8167_MUTEX_MOD_DISP_DITHER 15
> > > #define MT8167_MUTEX_MOD_DISP_UFOE 16
> > >
> > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> > > +#define MT8183_MUTEX_MOD_DISP_DITHER017
> > > +
> > > #define MT8173_MUTEX_MOD_DISP_OVL0 11
> > > #define MT8173_MUTEX_MOD_DISP_OVL1 12
> > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> > > @@ -87,6 +101,12 @@
> > > #define MT2712_MUTEX_SOF_DSI36
> > > #define MT8167_MUTEX_SOF_DPI02
> > > #define MT8167_MUTEX_SOF_DPI13
> > > +#define MT8183_MUTEX_SOF_DSI01
> > > +#define MT8183_MUTEX_SOF_DPI02
> > > +
> > > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > > +#define MT8183_MUTEX_EOF_DSI0
> > > (MT8183_MUTEX_SOF_DSI0 << 6)
> > > +#define MT8183_MUTEX_EOF_DPI0
> > > (MT8183_MUTEX_SOF_DPI0 << 6)
> > >
>
> Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred.
I prefer to move comment to mt8183_mutex_sof.
>
> > > struct mtk_mutex {
> > > int id;
> > > @@ -181,6 +201,20 @@ static const unsigned int
> > > mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> > > };
> > >
> > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > > +};
> > > +
> > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > > @@ -198,6 +232,12 @@ static const unsigne
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
>
> Modify the title's prefix to 'soc: mediatek:'
Modify more, the title should be 'soc: mediatek: add mtk mutex support
for MT8183'
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu
> >
> > Add DDP support for MT8183 SoC.
> >
> > Signed-off-by: Yongqiang Niu
> > Signed-off-by: Hsin-Yi Wang
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 50
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index f531b119da7a9..f64e9c33e85ad 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -14,6 +14,8 @@
> >
> > #define MT2701_MUTEX0_MOD0 0x2c
> > #define MT2701_MUTEX0_SOF0 0x30
> > +#define MT8183_DISP_MUTEX0_MOD00x30
> > +#define MT8183_DISP_MUTEX0_SOF00x2c
>
> Modify 'DISP_MUTEX' to 'MUTEX'
>
> >
> > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> > @@ -37,6 +39,18 @@
> > #define MT8167_MUTEX_MOD_DISP_DITHER 15
> > #define MT8167_MUTEX_MOD_DISP_UFOE 16
> >
> > +#define MT8183_MUTEX_MOD_DISP_RDMA00
> > +#define MT8183_MUTEX_MOD_DISP_RDMA11
> > +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
> > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
> > +#define MT8183_MUTEX_MOD_DISP_WDMA012
> > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> > +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
> > +
> > #define MT8173_MUTEX_MOD_DISP_OVL0 11
> > #define MT8173_MUTEX_MOD_DISP_OVL1 12
> > #define MT8173_MUTEX_MOD_DISP_RDMA013
> > @@ -87,6 +101,12 @@
> > #define MT2712_MUTEX_SOF_DSI3 6
> > #define MT8167_MUTEX_SOF_DPI0 2
> > #define MT8167_MUTEX_SOF_DPI1 3
> > +#define MT8183_MUTEX_SOF_DSI0 1
> > +#define MT8183_MUTEX_SOF_DPI0 2
> > +
> > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0
> > << 6)
> > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0
> > << 6)
> >
> > struct mtk_mutex {
> > int id;
> > @@ -181,6 +201,20 @@ static const unsigned int
> > mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> > };
> >
> > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > +};
> > +
> > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > @@ -198,6 +232,12 @@ static const unsigned int
> > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> > };
> >
> > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>
> According to discussion in [1], add comment for the odd EOF setting.
>
> [1]
> https://patchwork.k
Re: [PATCH v10 9/9] drm/mediatek: add support for mediatek SOC MT8183
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> 1. add ovl private data
> 2. add rdma private data
> 3. add gamma privte data
> 4. add main and external path module for crtc create
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 45 +++
> 4 files changed, 70 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index c98fe284265d0..93ad76a2dda5e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -179,6 +179,7 @@ static const struct mtk_disp_gamma_data
> mt8173_gamma_driver_data = {
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = _gamma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-gamma"},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 1c295c58a5e82..da7e38a28759b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data
> mt8173_ovl_driver_data = {
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = _ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = _ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 04b9542010b00..29fa5f3a05c30 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,11 +355,17 @@ static const struct mtk_disp_rdma_data
> mt8173_rdma_driver_data = {
> .fifo_size = SZ_8K,
> };
>
> +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = _rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = _rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 279d3e6f11563..486e73e675ad5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] =
> {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L1,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data
> mt8173
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
Hi, Hsin-Yi:
Modify the title's prefix to 'soc: mediatek:'
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add DDP support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..f64e9c33e85ad 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_DISP_MUTEX0_MOD0 0x30
> +#define MT8183_DISP_MUTEX0_SOF0 0x2c
Modify 'DISP_MUTEX' to 'MUTEX'
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,12 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +201,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +232,12 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
According to discussion in [1], add comment for the odd EOF setting.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang@mediatek.com/
Regards,
CK.
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
>
Re: [PATCH v10 7/9] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 37 -
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8173f709272be..ee54505412dcd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,7 +53,9 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
> +#define DITHER_REG(idx) (0x100 + (idx) * 4)
>
> #define LUT_10BIT_MASK 0x03ff
>
> @@ -313,8 +315,41 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> + bool enable = true;
> +
> + const u32 dither_setting[] = {
> + 0x, /* 5 */
> + 0x3002, /* 6 */
> + 0x, /* 7 */
> + 0x, /* 8 */
> + 0x, /* 9 */
> + 0x, /* 10 */
> + 0x, /* 11 */
> + 0x0011, /* 12 */
> + 0x, /* 13 */
> + 0x, /* 14 */
Could you explain what is this?
> + };
> +
> + if (bpc == 6) {
> + mtk_ddp_write(cmdq_pkt, 0x4041, >cmdq_reg,
> priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x40404040, >cmdq_reg,
> priv->regs, DITHER_REG(16));
> + } else if (bpc == 5) {
> + mtk_ddp_write(cmdq_pkt, 0x5051, >cmdq_reg,
> priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x50504040, >cmdq_reg,
> priv->regs, DITHER_REG(16));
This looks very similar to the code in mtk_dither_set(), could you
symbolize this magic number like mtk_dither_set()?
Regards,
CK
> + } else {
> + enable = false;
> + }
> +
> + if (enable) {
> + u32 idx;
> +
> + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> >cmdq_reg, priv->regs,
> + DITHER_REG(idx + 5));
> + }
> +
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct device *dev)
___
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Re: [PATCH v10 6/9] drm/mediatek: add has_dither private data for gamma
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Not all SoC has dither function in gamma module.
> Add private data to control this function setting.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index b5a499d7e472c..c98fe284265d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -25,7 +25,7 @@
> #define LUT_10BIT_MASK 0x03ff
>
> struct mtk_disp_gamma_data {
> - u32 reserved;
> + bool has_dither;
> };
>
> /**
> @@ -91,7 +91,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w,
>
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, gamma->regs,
> DISP_GAMMA_SIZE);
> - mtk_dither_set_common(gamma->regs, >cmdq_reg, bpc,
> DISP_GAMMA_CFG, cmdq_pkt);
> + if (gamma->data && gamma->data->has_dither)
> + mtk_dither_set_common(gamma->regs, >cmdq_reg, bpc,
> DISP_GAMMA_CFG, cmdq_pkt);
> }
>
> void mtk_gamma_start(struct device *dev)
> @@ -171,8 +172,13 @@ static int mtk_disp_gamma_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
> + .has_dither = true,
> +};
> +
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-gamma"},
> + { .compatible = "mediatek,mt8173-disp-gamma",
> + .data = _gamma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
___
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Re: [PATCH v10 5/9] drm/mediatek: separate gamma module
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 ++
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 188
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 ++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 214 insertions(+), 61 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 01d06332f7679..b64674b944860 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> mediatek-drm-y := mtk_disp_color.o \
> + mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index c50d5fc9fd349..c1e658b490b6c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -27,6 +27,16 @@ void mtk_dpi_stop(struct device *dev);
> void mtk_dsi_ddp_start(struct device *dev);
> void mtk_dsi_ddp_stop(struct device *dev);
>
> +int mtk_gamma_clk_enable(struct device *dev);
> +void mtk_gamma_clk_disable(struct device *dev);
> +void mtk_gamma_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> +void mtk_gamma_start(struct device *dev);
> +void mtk_gamma_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> new file mode 100644
> index 0..b5a499d7e472c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -0,0 +1,188 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_GAMMA_EN0x
> +#define GAMMA_EN BIT(0)
> +#define DISP_GAMMA_CFG 0x0020
> +#define GAMMA_LUT_EN BIT(1)
> +#define DISP_GAMMA_SIZE 0x0030
> +#define DISP_GAMMA_LUT 0x0700
> +
> +#define LUT_10BIT_MASK 0x03ff
> +
> +struct mtk_disp_gamma_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_gamma - DISP_GAMMA driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_gamma {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_gamma_data *data;
> +};
> +
> +int mtk_gamma_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(gamma->clk);
> +}
> +
> +void mtk_gamma_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(gamma->clk);
> +}
> +
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> +{
> + unsigned int i, reg;
> + struct drm_color_lut *lut;
> + void __iomem *lut_base;
> + u32 word;
> +
> + if (state->gamma_lut) {
> + reg = readl(regs + DISP_GAMMA_CFG);
> + reg = reg | GAMMA_LUT_EN;
> + writel(reg, regs + DISP_GAMMA_CFG);
> + lut_base = regs + DISP_GAMMA_LUT;
> + lut = (struct drm_color_lut *)state->gamma_lut->dat
Re: [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function
On Thu, 2021-01-28 at 13:09 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 12:39 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > There may be data structure other than mtk_ddp_comp_dev that would call
> > > mtk_dither_set(), so use regs as parameter instead of device.
> >
> > You does not change the interface of mtk_dither_set(). You move the
> > common part in mtk_dither_set() to a new function which could be called
> > by another caller.
> >
> > Regards,
> > CK.
> >
> Current mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But
> mtk_disp_gamma in next patch would also call this function. But it's
> dev data is struct mtk_disp_gamma, which is different, so we can't
> cast to mtk_ddp_comp_dev. I separate the necessary parameters (regs,
> cmdq_reg) out, so both component dither and gamma can both call this
> separated function.
I know this. This patch looks good to me but the description would
confuse me.From the description, it seems that you modify the interface
of mtk_dither_set(). So please modify the description to be more clear.
Regards,
CK
>
> This is similar to the mtk_gamma_set_common() in the next patch, which
> gamma and aal both used.
>
> > >
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> > > 2 files changed, 20 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > index 46d199b7b4a29..c50d5fc9fd349 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int
> > > w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > void mtk_color_start(struct device *dev);
> > >
> > > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > +unsigned int bpc, unsigned int CFG,
> > > +struct cmdq_pkt *cmdq_pkt);
> > > +
> > > void mtk_dpi_start(struct device *dev);
> > > void mtk_dpi_stop(struct device *dev);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index 7b5293429426d..53d25823a37cc 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> > > clk_disable_unprepare(priv->clk);
> > > }
> > >
> > > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > > - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> > > -{
> > > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > >
> > > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > +unsigned int bpc, unsigned int CFG, struct
> > > cmdq_pkt *cmdq_pkt)
> > > +{
> > > /* If bpc equal to 0, the dithering function didn't be enabled */
> > > if (bpc == 0)
> > > return;
> > >
> > > if (bpc >= MTK_MIN_BPC) {
> > > - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> > > DISP_DITHER_5);
> > > - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> > > DISP_DITHER_7);
> > > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> > > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> > > mtk_ddp_write(cmdq_pkt,
> > > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > > DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > DITHER_NEW_BIT_MODE,
> > > - >cmdq_reg, priv->regs, DISP_DITHER_15);
> > > + cmdq_reg, regs, DISP_DITHER_15);
> > > mtk_ddp_write(cmdq_pkt,
> > > DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > > DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc)
Re: [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> There may be data structure other than mtk_ddp_comp_dev that would call
> mtk_dither_set(), so use regs as parameter instead of device.
You does not change the interface of mtk_dither_set(). You move the
common part in mtk_dither_set() to a new function which could be called
by another caller.
Regards,
CK.
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 46d199b7b4a29..c50d5fc9fd349 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_color_start(struct device *dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG,
> +struct cmdq_pkt *cmdq_pkt);
> +
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 7b5293429426d..53d25823a37cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG, struct cmdq_pkt
> *cmdq_pkt)
> +{
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - >cmdq_reg, priv->regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - >cmdq_reg, priv->regs, DISP_DITHER_16);
> - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, >cmdq_reg,
> priv->regs, CFG);
> + cmdq_reg, regs, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
> }
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc, CFG, cmdq_pkt);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
___
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Re: [PATCH v10 3/9] drm/mediatek: add RDMA fifo size error handle
Hi, Hsin-Yi: On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add RDMA fifo size error handle > rdma fifo size will not always bigger than the calculated threshold > if that case happened, we need set fifo size as the threshold > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index b84004394970f..04b9542010b00 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* account for blanking, and with a pixel depth of 4 bytes: >*/ > threshold = width * height * vrefresh * 4 * 7 / 100; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; Please see the discussion in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6-git-send-email-yongqiang@mediatek.com/ Regards, CK > + > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/mediatek: dsi: Use IRQF_TRIGGER_NONE for dsi irq trigger type
+ Chun-Kuang, Philipp:
This mail has been sent to dri devel and linux mediatek, but why it does
not exist in mail lists?
Regards,
CK
On Thu, 2020-12-24 at 17:54 +0800, Huijuan Xie wrote:
> The interrupt trigger is already set by OF. When do devm_request_irq()
> in driver, please use IRQF_TRIGGER_NONE and don't specify trigger type
> again.
>
> Signed-off-by: Huijuan Xie
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 4a188a9..1d62489 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1128,9 +1128,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> goto err_unregister_host;
> }
>
> - irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
> ret = devm_request_irq(>dev, irq_num, mtk_dsi_irq,
> -IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
> +IRQF_TRIGGER_NONE, dev_name(>dev), dsi);
> if (ret) {
> dev_err(>dev, "failed to request mediatek dsi irq\n");
> goto err_unregister_host;
___
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Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema
Hi, Chunfeng:
On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: fix binding check warning of reg in example
> ---
> .../display/mediatek/mediatek,hdmi.txt| 17 +---
> .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++
> 2 files changed, 91 insertions(+), 16 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> index 7b124242b0c5..edac18951a75 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> @@ -50,22 +50,7 @@ Required properties:
>
> HDMI PHY
>
> -
> -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> -output and drives the HDMI pads.
> -
> -Required properties:
> -- compatible: "mediatek,-hdmi-phy"
> -- reg: Physical base address and length of the module's registers
> -- clocks: PLL reference clock
> -- clock-names: must contain "pll_ref"
> -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> -- #phy-cells: must be <0>
> -- #clock-cells: must be <0>
> -
> -Optional properties:
> -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +See phy/mediatek,hdmi-phy.yaml
>
> Example:
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> new file mode 100644
> index ..77df50204606
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> +
> +maintainers:
> + - CK Hu
I think you should remove "CK Hu " and add latest
mediatek drm maintainer:
DRM DRIVERS FOR MEDIATEK
M: Chun-Kuang Hu
M: Philipp Zabel
L: dri-devel@lists.freedesktop.org
S: Supported
F: Documentation/devicetree/bindings/display/mediatek/
F: drivers/gpu/drm/mediatek/
Regards,
CK
> + - Chunfeng Yun
> +
> +description: |
> + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> + output and drives the HDMI pads.
> +
> +properties:
> + $nodename:
> +pattern: "^hdmi-phy@[0-9a-f]+$"
> +
> + compatible:
> +enum:
> + - mediatek,mt2701-hdmi-phy
> + - mediatek,mt8173-hdmi-phy
> +
> + reg:
> +maxItems: 1
> +
> + clocks:
> +items:
> + - description: PLL reference clock
> +
> + clock-names:
> +items:
> + - const: pll_ref
> +
> + clock-output-names:
> +items:
> + - const: hdmitx_dig_cts
> +
> + "#phy-cells":
> +const: 0
> +
> + "#clock-cells":
> +const: 0
> +
> + mediatek,ibias:
> +description:
> + TX DRV bias current for < 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0xa
> +
> + mediatek,ibias_up:
> +description:
> + TX DRV bias current for >= 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0x1c
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - clock-output-names
> + - "#phy-cells"
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +hdmi_phy: hdmi-phy@10209100 {
> +compatible = "mediatek,mt8173-hdmi-phy";
> +reg = <0x10209100 0x24>;
> +clocks = < CLK_APMIXED_HDMI_REF>;
> +clock-names = "pll_ref";
> +clock-output-names = "hdmitx_dig_cts";
> +mediatek,ibias = <0xa>;
> +mediatek,ibias_up = <0x1c>;
> +#clock-cells = <0>;
> +#phy-cells = <0>;
> +};
> +
> +...
___
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Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Matthias: On Thu, 2020-03-26 at 16:45 +0100, Matthias Brugger wrote: > > On 26/03/2020 15:51, CK Hu wrote: > > Hi, Matthias: > > > > On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote: > >> Hi CK, > >> > >> On 26/03/2020 00:05, CK Hu wrote: > >>> Hi, Matthias: > >>> > >>> On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote: > >>>> > >>>> On 11/03/2020 17:53, Enric Balletbo i Serra wrote: > >>>>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions > >>>>> to > >>>>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > >>>>> Those functions will allow DRM driver and others to control the data > >>>>> path routing. > >>>>> > >>>>> Signed-off-by: Enric Balletbo i Serra > >>>>> Reviewed-by: Matthias Brugger > >>>>> Reviewed-by: CK Hu > >>>>> Acked-by: CK Hu > >>>> > >>>> This patch does not apply against v5.6-rc1. > >>>> Please rebase as this is a quite big patch and it won't be easy to do > >>>> that by hand. > >>> > >>> I think this patch depends on [1] which has been acked by me and I have > >>> not picked it. The simple way is that you pick [1] first and then pick > >>> this series. > >>> > >>> [1] > >>> https://patchwork.kernel.org/patch/11406227/ > >>> > >> > >> You would need to provide a stable tag for me that I can merge into my > >> tree. You > >> can also try to merge my for-next [1] which has the newest version from > >> Enric. > >> If you see any merge conflict, then we have to do something about it :) > >> > >> Regards, > >> Matthias > >> > >> [1] > >> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next > >> > > > > You have applied this series, so I would not apply other patches which > > would conflict with this series. After this series land on main stream > > (wish it happen in this merge window), I would rebase other patch on > > main stream. > > > > I haven't (yet) send the pull request. If you want to bring in your patches in > v5.7 as well we can find a solution to that. Shall I provide you with a stable > branch which you can merge? This way you can add all your patches in the pull > request as well and we don't have to wait for v5.8 to get things into > mainline. > > Let me know and I'll provide you with a stable branch. > Other drm patches is not in a hurry, for now I don't need a stable branch. If I need one, I would tell you, thanks. Regards, CK > Regards, > Matthias > > > Regards, > > CK > > > >>> Regards, > >>> CK > >>> > >>>> > >>>> Regards, > >>>> Matthias > >>>> > >>>>> --- > >>>>> > >>>>> Changes in v12: None > >>>>> Changes in v10: > >>>>> - Select CONFIG_MTK_MMSYS (CK) > >>>>> - Pass device pointer of mmsys device instead of config regs (CK) > >>>>> > >>>>> Changes in v9: > >>>>> - Introduced a new patch to move routing control into mmsys driver. > >>>>> - Removed the patch to use regmap as is not needed anymore. > >>>>> > >>>>> Changes in v8: None > >>>>> Changes in v7: None > >>>>> > >>>>> drivers/gpu/drm/mediatek/Kconfig| 1 + > >>>>> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > >>>>> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 -- > >>>>> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > >>>>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > >>>>> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > >>>>> drivers/soc/mediatek/mtk-mmsys.c| 279 > >>>>> include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > >>>>> 8 files changed, 316 insertions(+), 282 deletions(-) > >>>>> create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > >>>>> > >>>>> diff --git a/drivers/gpu/drm/mediatek/Kconfig > >>>>> b/drivers/gpu/drm/mediatek/Kconfig > >>>>> index fa
Re: [RESEND PATCH v6 00/17] add drm support for MT8183
Hi, Yongqiang: In [1], Matthias has applied below series to fix mmsys driver probe problem. Please base on that series to resend your patches. soc / drm: mediatek: Fix mediatek-drm device probingsoc / drm: mediatek: Move routing control to mmsys device clk / soc: mediatek: Move mt8173 MMSYS to platform driver dt-bindings: mediatek: Update mmsys binding to reflect it is a system controllerdrm/mediatek: Omit warning on probe defers [1] https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next Regards, CK On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote: > This series are based on 5.5-rc1 and provid 17 patch > to support mediatek SOC MT8183 > > Change since v5 > - fix reviewed issue in v5 > base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 > > Change since v4 > - fix reviewed issue in v4 > > Change since v3 > - fix reviewed issue in v3 > - fix type error in v3 > - fix conflict with iommu patch > > Change since v2 > - fix reviewed issue in v2 > - add mutex node into dts file > > Changes since v1: > - fix reviewed issue in v1 > - add dts for mt8183 display nodes > - adjust display clock control flow in patch 22 > - add vmap support for mediatek drm in patch 23 > - fix page offset issue for mmap function in patch 24 > - enable allow_fb_modifiers for mediatek drm in patch 25 > > Yongqiang Niu (17): > dt-bindings: mediatek: add rdma_fifo_size description for mt8183 > display > arm64: dts: add display nodes for mt8183 > drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in > drm/mediatek: make sout select function format same with select input > drm/mediatek: add mmsys private data for ddp path config > drm/mediatek: add private data for rdma1 to dpi0 connection > drm/mediatek: add private data for rdma1 to dsi0 connection > drm/mediatek: move rdma sout from mtk_ddp_mout_en into > mtk_ddp_sout_sel > drm/mediatek: add connection from OVL0 to OVL_2L0 > drm/mediatek: add connection from RDMA0 to COLOR0 > drm/mediatek: add connection from RDMA1 to DSI0 > drm/mediatek: add connection from OVL_2L0 to RDMA0 > drm/mediatek: add connection from OVL_2L1 to RDMA1 > drm/mediatek: add connection from DITHER0 to DSI0 > drm/mediatek: add connection from RDMA0 to DSI0 > drm/mediatek: add fifo_size into rdma private data > drm/mediatek: add support for mediatek SOC MT8183 > > .../bindings/display/mediatek/mediatek,disp.txt| 13 + > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 +++ > drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 18 ++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 4 + > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 288 > - > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 49 > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 + > 9 files changed, 435 insertions(+), 70 deletions(-) > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Matthias: On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote: > Hi CK, > > On 26/03/2020 00:05, CK Hu wrote: > > Hi, Matthias: > > > > On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote: > >> > >> On 11/03/2020 17:53, Enric Balletbo i Serra wrote: > >>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > >>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > >>> Those functions will allow DRM driver and others to control the data > >>> path routing. > >>> > >>> Signed-off-by: Enric Balletbo i Serra > >>> Reviewed-by: Matthias Brugger > >>> Reviewed-by: CK Hu > >>> Acked-by: CK Hu > >> > >> This patch does not apply against v5.6-rc1. > >> Please rebase as this is a quite big patch and it won't be easy to do that > >> by hand. > > > > I think this patch depends on [1] which has been acked by me and I have > > not picked it. The simple way is that you pick [1] first and then pick > > this series. > > > > [1] > > https://patchwork.kernel.org/patch/11406227/ > > > > You would need to provide a stable tag for me that I can merge into my tree. > You > can also try to merge my for-next [1] which has the newest version from Enric. > If you see any merge conflict, then we have to do something about it :) > > Regards, > Matthias > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next > You have applied this series, so I would not apply other patches which would conflict with this series. After this series land on main stream (wish it happen in this merge window), I would rebase other patch on main stream. Regards, CK > > Regards, > > CK > > > >> > >> Regards, > >> Matthias > >> > >>> --- > >>> > >>> Changes in v12: None > >>> Changes in v10: > >>> - Select CONFIG_MTK_MMSYS (CK) > >>> - Pass device pointer of mmsys device instead of config regs (CK) > >>> > >>> Changes in v9: > >>> - Introduced a new patch to move routing control into mmsys driver. > >>> - Removed the patch to use regmap as is not needed anymore. > >>> > >>> Changes in v8: None > >>> Changes in v7: None > >>> > >>> drivers/gpu/drm/mediatek/Kconfig| 1 + > >>> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > >>> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 -- > >>> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > >>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > >>> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > >>> drivers/soc/mediatek/mtk-mmsys.c| 279 > >>> include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > >>> 8 files changed, 316 insertions(+), 282 deletions(-) > >>> create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > >>> > >>> diff --git a/drivers/gpu/drm/mediatek/Kconfig > >>> b/drivers/gpu/drm/mediatek/Kconfig > >>> index fa5ffc4fe823..c420f5a3d33b 100644 > >>> --- a/drivers/gpu/drm/mediatek/Kconfig > >>> +++ b/drivers/gpu/drm/mediatek/Kconfig > >>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK > >>> select DRM_MIPI_DSI > >>> select DRM_PANEL > >>> select MEMORY > >>> + select MTK_MMSYS > >>> select MTK_SMI > >>> select VIDEOMODE_HELPERS > >>> help > >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > >>> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > >>> index 0e05683d7b53..579a5a5d4472 100644 > >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > >>> @@ -6,6 +6,7 @@ > >>> #include > >>> #include > >>> #include > >>> +#include > >>> > >>> #include > >>> #include > >>> @@ -28,7 +29,7 @@ > >>> * @enabled: records whether crtc_enable succeeded > >>> * @planes: array of 4 drm_plane structures, one for each overlay plane > >>> * @pending_planes: whether any plane has pending changes to be applied > >>> - * @config_regs: memory mapped mmsys configuration register space > >>> + * @mmsys_dev: pointer to the mmsys device for configuration registers > >>
Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Matthias:
On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
>
> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
> > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> > Those functions will allow DRM driver and others to control the data
> > path routing.
> >
> > Signed-off-by: Enric Balletbo i Serra
> > Reviewed-by: Matthias Brugger
> > Reviewed-by: CK Hu
> > Acked-by: CK Hu
>
> This patch does not apply against v5.6-rc1.
> Please rebase as this is a quite big patch and it won't be easy to do that by
> hand.
I think this patch depends on [1] which has been acked by me and I have
not picked it. The simple way is that you pick [1] first and then pick
this series.
[1]
https://patchwork.kernel.org/patch/11406227/
Regards,
CK
>
> Regards,
> Matthias
>
> > ---
> >
> > Changes in v12: None
> > Changes in v10:
> > - Select CONFIG_MTK_MMSYS (CK)
> > - Pass device pointer of mmsys device instead of config regs (CK)
> >
> > Changes in v9:
> > - Introduced a new patch to move routing control into mmsys driver.
> > - Removed the patch to use regmap as is not needed anymore.
> >
> > Changes in v8: None
> > Changes in v7: None
> >
> > drivers/gpu/drm/mediatek/Kconfig| 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 --
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 -
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
> > drivers/soc/mediatek/mtk-mmsys.c| 279
> > include/linux/soc/mediatek/mtk-mmsys.h | 20 ++
> > 8 files changed, 316 insertions(+), 282 deletions(-)
> > create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Kconfig
> > b/drivers/gpu/drm/mediatek/Kconfig
> > index fa5ffc4fe823..c420f5a3d33b 100644
> > --- a/drivers/gpu/drm/mediatek/Kconfig
> > +++ b/drivers/gpu/drm/mediatek/Kconfig
> > @@ -11,6 +11,7 @@ config DRM_MEDIATEK
> > select DRM_MIPI_DSI
> > select DRM_PANEL
> > select MEMORY
> > + select MTK_MMSYS
> > select MTK_SMI
> > select VIDEOMODE_HELPERS
> > help
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 0e05683d7b53..579a5a5d4472 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -6,6 +6,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include
> > #include
> > @@ -28,7 +29,7 @@
> > * @enabled: records whether crtc_enable succeeded
> > * @planes: array of 4 drm_plane structures, one for each overlay plane
> > * @pending_planes: whether any plane has pending changes to be applied
> > - * @config_regs: memory mapped mmsys configuration register space
> > + * @mmsys_dev: pointer to the mmsys device for configuration registers
> > * @mutex: handle to one of the ten disp_mutex streams
> > * @ddp_comp_nr: number of components in ddp_comp
> > * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this
> > crtc
> > @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
> > u32 cmdq_event;
> > #endif
> >
> > - void __iomem*config_regs;
> > + struct device *mmsys_dev;
> > struct mtk_disp_mutex *mutex;
> > unsigned intddp_comp_nr;
> > struct mtk_ddp_comp **ddp_comp;
> > @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> > *mtk_crtc)
> > }
> >
> > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> > - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> > -mtk_crtc->ddp_comp[i]->id,
> > -mtk_crtc->ddp_comp[i + 1]->id);
> > + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> > + mtk_crtc->ddp_comp[i]->id,
> > + mtk_crtc->ddp_comp[i + 1]->id);
> > mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> > mtk_crtc->ddp_comp[i]->id);
> > }
> > @@ -355,9 +356,9 @@ static
Re: [PATCH] drm/mediatek: Remove debug messages for function calls
Hi, Enric:
On Wed, 2020-02-26 at 12:27 +0100, Enric Balletbo i Serra wrote:
> Equivalent information can be nowadays obtained using function tracer.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
Acked-by: CK Hu
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 --
> 2 files changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index a236499123aa..882c690d3f13 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -192,7 +192,6 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc
> *mtk_crtc)
> int ret;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
> if (ret) {
> @@ -212,7 +211,6 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc
> *mtk_crtc)
> {
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
> }
> @@ -257,7 +255,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> int ret;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> if (WARN_ON(!crtc->state))
> return -EINVAL;
>
> @@ -298,7 +295,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> goto err_mutex_unprepare;
> }
>
> - DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
>mtk_crtc->ddp_comp[i]->id,
> @@ -348,7 +344,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
> *mtk_crtc)
> struct drm_crtc *crtc = _crtc->base;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
> if (i == 1)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 17f118ee0e57..4934834977b3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -570,7 +570,6 @@ static int mtk_drm_sys_suspend(struct device *dev)
> int ret;
>
> ret = drm_mode_config_helper_suspend(drm);
> - DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
>
> return ret;
> }
> @@ -582,7 +581,6 @@ static int mtk_drm_sys_resume(struct device *dev)
> int ret;
>
> ret = drm_mode_config_helper_resume(drm);
> - DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
>
> return ret;
> }
___
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Re: [SPAM][PATCH] drm/mediatek: Remove debug messages for function calls
Hi, Enric:
On Wed, 2020-02-26 at 12:27 +0100, Enric Balletbo i Serra wrote:
> Equivalent information can be nowadays obtained using function tracer.
>
Acked-by: CK Hu
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 5 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 --
> 2 files changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index a236499123aa..882c690d3f13 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -192,7 +192,6 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc
> *mtk_crtc)
> int ret;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
> if (ret) {
> @@ -212,7 +211,6 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc
> *mtk_crtc)
> {
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
> }
> @@ -257,7 +255,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> int ret;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> if (WARN_ON(!crtc->state))
> return -EINVAL;
>
> @@ -298,7 +295,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> goto err_mutex_unprepare;
> }
>
> - DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
>mtk_crtc->ddp_comp[i]->id,
> @@ -348,7 +344,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
> *mtk_crtc)
> struct drm_crtc *crtc = _crtc->base;
> int i;
>
> - DRM_DEBUG_DRIVER("%s\n", __func__);
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
> mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
> if (i == 1)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 17f118ee0e57..4934834977b3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -570,7 +570,6 @@ static int mtk_drm_sys_suspend(struct device *dev)
> int ret;
>
> ret = drm_mode_config_helper_suspend(drm);
> - DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
>
> return ret;
> }
> @@ -582,7 +581,6 @@ static int mtk_drm_sys_resume(struct device *dev)
> int ret;
>
> ret = drm_mode_config_helper_resume(drm);
> - DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
>
> return ret;
> }
___
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[GIT PULL] mediatek drm next for 5.7
Hi, Dave & Daniel: This include MT8183 DPI support. And I change my email address to "Chun-Kuang Hu ", so I would use it afterward. Regards, CK The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: https://github.com/ckhu-mediatek/linux.git-tags.git tags/mediatek-drm-next-5.7 for you to fetch changes up to 93e97f715b24114169d18654e09c646fd9e14979: MAINTAINERS: Update Chun-Kuang Hu's email address (2020-03-09 09:23:47 +0800) Mediatek DRM Next for Linux 5.7 Chun-Kuang Hu (1): MAINTAINERS: Update Chun-Kuang Hu's email address Jitao Shi (2): dt-bindings: display: mediatek: update dpi supported chips drm/mediatek: add mt8183 dpi clock factor .../bindings/display/mediatek/mediatek,dpi.txt | 1 + MAINTAINERS| 2 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++ 3 files changed, 20 insertions(+), 1 deletion(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 5/5] soc / drm: mediatek: Fix mediatek-drm device probing
On Wed, 2020-03-11 at 14:26 +0100, Matthias Brugger wrote: > > On 11/03/2020 12:56, Enric Balletbo i Serra wrote: > > In the actual implementation the same compatible string > > "mediatek,-mmsys" is used to bind the clock drivers > > (drivers/soc/mediatek) as well as to the gpu driver > > (drivers/gpu/drm/mediatek/mtk_drm_drv.c). This ends with the problem > > that the only probed driver is the clock driver and there is no display > > at all. > > > > In any case having the same compatible string for two drivers is not > > correct and should be fixed. To fix this, and maintain backward > > compatibility, we can consider that the mmsys driver is the top-level > > entry point for the multimedia subsystem, so is not a pure clock > > controller but a system controller, and the drm driver is instantiated > > by that MMSYS driver. > > > > Signed-off-by: Enric Balletbo i Serra > > Reviewed-by: CK Hu > > Same here. Acked-by: CK Hu ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device
On Wed, 2020-03-11 at 14:25 +0100, Matthias Brugger wrote: > > On 11/03/2020 14:07, CK Hu wrote: > > Hi, Enric: > > > > On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote: > >> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > >> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > >> Those functions will allow DRM driver and others to control the data > >> path routing. > >> > > > > Reviewed-by: CK Hu > > > > If I remember correctly you are OK me taking the patch through the SoC tree, > right? > > In this case I'd need a Acked-by tag. Not a big deal, just trying to remeber > the > tag policy in the linux kernel :) > > Regards, > Matthias > Acked-by: CK Hu > >> Signed-off-by: Enric Balletbo i Serra > >> Reviewed-by: Matthias Brugger > >> --- > >> > >> Changes in v11: None > >> Changes in v10: > >> - Select CONFIG_MTK_MMSYS (CK) > >> - Pass device pointer of mmsys device instead of config regs (CK) > >> > >> Changes in v9: > >> - Introduced a new patch to move routing control into mmsys driver. > >> - Removed the patch to use regmap as is not needed anymore. > >> > >> Changes in v8: None > >> Changes in v7: None > >> > >> drivers/gpu/drm/mediatek/Kconfig| 1 + > >> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > >> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 -- > >> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > >> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > >> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > >> drivers/soc/mediatek/mtk-mmsys.c| 279 > >> include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > >> 8 files changed, 316 insertions(+), 282 deletions(-) > >> create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > >> > > > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Enric: On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote: > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > Those functions will allow DRM driver and others to control the data > path routing. > Reviewed-by: CK Hu > Signed-off-by: Enric Balletbo i Serra > Reviewed-by: Matthias Brugger > --- > > Changes in v11: None > Changes in v10: > - Select CONFIG_MTK_MMSYS (CK) > - Pass device pointer of mmsys device instead of config regs (CK) > > Changes in v9: > - Introduced a new patch to move routing control into mmsys driver. > - Removed the patch to use regmap as is not needed anymore. > > Changes in v8: None > Changes in v7: None > > drivers/gpu/drm/mediatek/Kconfig| 1 + > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 -- > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > drivers/soc/mediatek/mtk-mmsys.c| 279 > include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > 8 files changed, 316 insertions(+), 282 deletions(-) > create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver
Hi, Enric: On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote: > From: Matthias Brugger > > There is no strong reason for this to use CLK_OF_DECLARE instead of > being a platform driver. Plus, MMSYS provides clocks but also a shared > register space for the mediatek-drm and the mediatek-mdp > driver. So move the MMSYS clocks to a new platform driver and also > create a new MMSYS platform driver in drivers/soc/mediatek that > instantiates the clock driver. > Reviewed-by: CK Hu > Signed-off-by: Matthias Brugger > Signed-off-by: Enric Balletbo i Serra > --- > > Changes in v11: > - Leave the clocks part in drivers/clk (clk-mt8173-mm) > - Instantiate the clock driver from the mtk-mmsys driver. > - Add default config option to not break anything. > - Removed the Reviewed-by CK tag as changed the organization. > > Changes in v10: > - Renamed to be generic mtk-mmsys > - Add driver data support to be able to support diferent SoCs > > Changes in v9: > - Move mmsys to drivers/soc/mediatek (CK) > > Changes in v8: > - Be a builtin_platform_driver like other mediatek mmsys drivers. > > Changes in v7: > - Free clk_data->clks as well > - Get rid of private data structure > > drivers/clk/mediatek/Kconfig | 7 ++ > drivers/clk/mediatek/Makefile| 1 + > drivers/clk/mediatek/clk-mt8173-mm.c | 146 +++ > drivers/clk/mediatek/clk-mt8173.c| 104 --- > drivers/soc/mediatek/Kconfig | 8 ++ > drivers/soc/mediatek/Makefile| 1 + > drivers/soc/mediatek/mtk-mmsys.c | 50 + > 7 files changed, 213 insertions(+), 104 deletions(-) > create mode 100644 drivers/clk/mediatek/clk-mt8173-mm.c > create mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing
Hi, Enric: I'm confused this is v11 or v12. For v12, you've lost some 'Acked-by' and 'Reviewed-by' tag. Regards, CK On Wed, 2020-03-11 at 12:56 +0100, Enric Balletbo i Serra wrote: > Dear all, > > These patches are intended to solve an old standing issue on some > Mediatek devices (mt8173, mt2701 and mt2712 are affected by this issue). > > Up to now both drivers, clock and drm are probed with the same device tree > compatible. But only the first driver gets probed, which in effect breaks > graphics on those devices. > > The MMSYS (Multimedia subsystem) in Mediatek SoCs has some registers to > control clock gates (which is used in the clk driver) and some registers > to set the routing and enable the differnet blocks of the display > and MDP (Media Data Path) subsystem. On this series the clk driver is > not a pure clock controller but a system controller that can provide > access to the shared registers between the different drivers that need > it (mediatek-drm and mediatek-mdp). Hence the MMSYS clk driver was moved > to drivers/soc/mediatek and is the entry point (parent) which will trigger > the probe of the corresponding mediatek-drm driver. > > **IMPORTANT** This series only fixes the issue on mt8173 to make it > simple and as is the only platform I can test. Similar changes should be > applied for mt2701 and mt2712 to have display working. > > These patches apply on top of linux-next. > > For reference, here are the links to the old discussions: > * v10: https://patchwork.kernel.org/project/linux-mediatek/list/?series=248505 > * v9: https://patchwork.kernel.org/project/linux-clk/list/?series=247591 > * v8: https://patchwork.kernel.org/project/linux-mediatek/list/?series=244891 > * v7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=241217 > * v6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 > * v5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=44063 > * v4: > * https://patchwork.kernel.org/patch/10530871/ > * https://patchwork.kernel.org/patch/10530883/ > * https://patchwork.kernel.org/patch/10530885/ > * https://patchwork.kernel.org/patch/10530911/ > * https://patchwork.kernel.org/patch/10530913/ > * v3: > * https://patchwork.kernel.org/patch/10367857/ > * https://patchwork.kernel.org/patch/10367861/ > * https://patchwork.kernel.org/patch/10367877/ > * https://patchwork.kernel.org/patch/10367875/ > * https://patchwork.kernel.org/patch/10367885/ > * https://patchwork.kernel.org/patch/10367883/ > * https://patchwork.kernel.org/patch/10367889/ > * https://patchwork.kernel.org/patch/10367907/ > * https://patchwork.kernel.org/patch/10367909/ > * https://patchwork.kernel.org/patch/10367905/ > * v2: No relevant discussion, see v3 > * v1: > * https://patchwork.kernel.org/patch/10016497/ > * https://patchwork.kernel.org/patch/10016499/ > * https://patchwork.kernel.org/patch/10016505/ > * https://patchwork.kernel.org/patch/10016507/ > > Best regards, > Enric > > Changes in v11: > - Leave the clocks part in drivers/clk (clk-mt8173-mm) > - Instantiate the clock driver from the mtk-mmsys driver. > - Add default config option to not break anything. > - Removed the Reviewed-by CK tag as changed the organization. > > Changes in v10: > - Update the binding documentation for the mmsys system controller. > - Renamed to be generic mtk-mmsys > - Add driver data support to be able to support diferent SoCs > - Select CONFIG_MTK_MMSYS (CK) > - Pass device pointer of mmsys device instead of config regs (CK) > - Match driver data to get display routing. > > Changes in v9: > - Move mmsys to drivers/soc/mediatek (CK) > - Introduced a new patch to move routing control into mmsys driver. > - Removed the patch to use regmap as is not needed anymore. > - Do not move the display routing from the drm driver (CK) > > Changes in v8: > - Be a builtin_platform_driver like other mediatek mmsys drivers. > - New patch introduced in this series. > > Changes in v7: > - Free clk_data->clks as well > - Get rid of private data structure > > Enric Balletbo i Serra (3): > dt-bindings: mediatek: Update mmsys binding to reflect it is a system > controller > soc / drm: mediatek: Move routing control to mmsys device > soc / drm: mediatek: Fix mediatek-drm device probing > > Matthias Brugger (2): > drm/mediatek: Omit warning on probe defers > clk / soc: mediatek: Move mt8173 MMSYS to platform driver > > .../bindings/arm/mediatek/mediatek,mmsys.txt | 7 +- > drivers/clk/mediatek/Kconfig | 7 + > drivers/clk/mediatek/Makefile | 1 + > drivers/clk/mediatek/clk-mt8173-mm.c | 146 > drivers/clk/mediatek/clk-mt8173.c | 104 -- > drivers/gpu/drm/mediatek/Kconfig | 1 + > drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 +- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 5 +-
Re: [PATCH 10/22] drm/mediatek: Use simple encoder
Hi, Thomas:
On Thu, 2020-03-05 at 16:59 +0100, Thomas Zimmermann wrote:
> The mediatak driver uses empty implementations for its encoders. Replace
> the code with the generic simple encoder.
>
Acked-by: CK Hu
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 14 +++---
> 2 files changed, 6 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 14fbe1c09ce9..9c90c58e5acd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -20,6 +20,7 @@
> #include
> #include
> #include
> +#include
>
> #include "mtk_dpi_regs.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -509,15 +510,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> return 0;
> }
>
> -static void mtk_dpi_encoder_destroy(struct drm_encoder *encoder)
> -{
> - drm_encoder_cleanup(encoder);
> -}
> -
> -static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = {
> - .destroy = mtk_dpi_encoder_destroy,
> -};
> -
> static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
> const struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode)
> @@ -596,8 +588,8 @@ static int mtk_dpi_bind(struct device *dev, struct device
> *master, void *data)
> return ret;
> }
>
> - ret = drm_encoder_init(drm_dev, >encoder, _dpi_encoder_funcs,
> -DRM_MODE_ENCODER_TMDS, NULL);
> + ret = drm_simple_encoder_init(drm_dev, >encoder,
> + DRM_MODE_ENCODER_TMDS);
> if (ret) {
> dev_err(dev, "Failed to initialize decoder: %d\n", ret);
> goto err_unregister;
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 0ede69830a9d..a9a25087112f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -22,6 +22,7 @@
> #include
> #include
> #include
> +#include
>
> #include "mtk_drm_ddp_comp.h"
>
> @@ -787,15 +788,6 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
> dsi->enabled = false;
> }
>
> -static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
> -{
> - drm_encoder_cleanup(encoder);
> -}
> -
> -static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
> - .destroy = mtk_dsi_encoder_destroy,
> -};
> -
> static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
> const struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode)
> @@ -888,8 +880,8 @@ static int mtk_dsi_create_conn_enc(struct drm_device
> *drm, struct mtk_dsi *dsi)
> {
> int ret;
>
> - ret = drm_encoder_init(drm, >encoder, _dsi_encoder_funcs,
> -DRM_MODE_ENCODER_DSI, NULL);
> + ret = drm_simple_encoder_init(drm, >encoder,
> + DRM_MODE_ENCODER_DSI);
> if (ret) {
> DRM_ERROR("Failed to encoder init to drm\n");
> return ret;
___
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Re: [PATCH v5 12/13] soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
Hi, Dennis:
On Sun, 2020-03-08 at 18:52 +0800, Dennis YC Hsieh wrote:
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
> drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
> include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
> include/linux/soc/mediatek/mtk-cmdq.h| 5 +++--
> 4 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 7daaabc26eb1..a065b3a412cf 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -488,7 +488,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc
> *mtk_crtc)
> if (mtk_crtc->cmdq_client) {
> cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> - cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
> mtk_crtc_ddp_config(crtc, cmdq_handle);
> cmdq_pkt_finalize(cmdq_handle);
> cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index bb5be20fc70a..ec5637d43254 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -296,15 +296,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16
> high_addr_reg_idx,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_s_value);
>
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
> {
> struct cmdq_instruction inst = { {0} };
> + u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> inst.op = CMDQ_CODE_WFE;
> - inst.value = CMDQ_WFE_OPTION;
> + inst.value = CMDQ_WFE_OPTION | clear_option;
> inst.event = event;
>
> return cmdq_pkt_append_command(pkt, inst);
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 3f6bc0dfd5da..42d2a30e6a70 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -27,8 +27,7 @@
> * bit 16-27: update value
> * bit 31: 1 - update, 0 - no update
> */
> -#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE |
> CMDQ_WFE_WAIT | \
> - CMDQ_WFE_WAIT_VALUE)
> +#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT |
> CMDQ_WFE_WAIT_VALUE)
>
> /** cmdq event maximum */
> #define CMDQ_MAX_EVENT 0x3ff
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 1a6c56f3bec1..d63749440697 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -152,11 +152,12 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16
> high_addr_reg_idx,
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @event: the desired event type to "wait and CLEAR"
> + * @event: the desired event type to wait
> + * @clear: clear event or not after event arrive
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
>
> /**
> * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
___
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Re: [PATCH v5 11/13] soc: mediatek: cmdq: add jump function
Hi, Dennis:
On Sun, 2020-03-08 at 18:52 +0800, Dennis YC Hsieh wrote:
> Add jump function so that client can jump to any address which
> contains instruction.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +
> include/linux/soc/mediatek/mtk-cmdq.h | 11 +++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 59bc1164b411..bb5be20fc70a 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -13,6 +13,7 @@
> #define CMDQ_POLL_ENABLE_MASKBIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_REG_TYPE1
> +#define CMDQ_JUMP_RELATIVE 1
>
> struct cmdq_instruction {
> union {
> @@ -372,6 +373,18 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx,
> u32 value)
> }
> EXPORT_SYMBOL(cmdq_pkt_assign);
>
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + inst.op = CMDQ_CODE_JUMP;
> + inst.offset = CMDQ_JUMP_RELATIVE;
> + inst.value = addr >>
> + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_jump);
> +
> int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 99e77155f967..1a6c56f3bec1 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -213,6 +213,17 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> */
> int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
>
> +/**
> + * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE
> + *to execute an instruction that change current thread PC to
> + *a physical address which should contains more instruction.
> + * @pkt:the CMDQ packet
> + * @addr: physical address of target instruction buffer
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
> +
> /**
> * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
> * @pkt: the CMDQ packet
___
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Re: [PATCH] MAINTAINERS: Update Chun-Kuang Hu's email address
On Sun, 2020-03-08 at 12:52 +0800, Chun-Kuang Hu wrote: > Update my email address to @kernel.org > Applied to mediatek-drm-next-5.7 [1]. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.7 Regards, CK > Signed-off-by: Chun-Kuang Hu > --- > MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 38fe2f3f7b6f..dceaeebce52a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5607,7 +5607,7 @@ F: include/uapi/drm/lima_drm.h > T: git git://anongit.freedesktop.org/drm/drm-misc > > DRM DRIVERS FOR MEDIATEK > -M: CK Hu > +M: Chun-Kuang Hu > M: Philipp Zabel > L: dri-devel@lists.freedesktop.org > S: Supported ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[GIT PULL] mediatek drm fixes for 5.6
Hi, Dave & Daniel: This include OVL, cursor, and gce fixup. Regards, CK The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: https://github.com/ckhu-mediatek/linux.git-tags.git tags/mediatek-drm-fixes-5.6 for you to fetch changes up to 3d2ed431b8f39483477bc3c3a2aefbc9778ffe12: drm/mediatek: Handle component type MTK_DISP_OVL_2L correctly (2020-02-25 13:02:22 +0800) Mediatek DRM Fixes for Linux 5.6 Bibby Hsieh (4): drm/mediatek: Add plane check in async_check function drm/mediatek: Add fb swap in async_update drm/mediatek: Move gce event property to mutex device node drm/mediatek: Make sure previous message done or be aborted before send Evan Benn (1): drm/mediatek: Find the cursor plane instead of hard coding it Phong LE (1): drm/mediatek: Handle component type MTK_DISP_OVL_2L correctly Sean Paul (1): drm/mediatek: Ensure the cursor plane is on top of other overlays drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 30 +++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c| 7 +++ 3 files changed, 28 insertions(+), 10 deletions(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 12/13] soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
> drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
> include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
> include/linux/soc/mediatek/mtk-cmdq.h| 5 +++--
> 4 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 7daaabc26eb1..4916a7f75d23 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -488,7 +488,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc
> *mtk_crtc)
> if (mtk_crtc->cmdq_client) {
> cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> - cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, true);
There is always clear event before wait event, so there is no need to
clear event after event is waited. So this should be
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
Regards,
CK
> mtk_crtc_ddp_config(crtc, cmdq_handle);
> cmdq_pkt_finalize(cmdq_handle);
> cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index f27c67034880..4f767198d0fc 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -295,15 +295,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16
> high_addr_reg_idx,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_s_value);
>
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
> {
> struct cmdq_instruction inst = { {0} };
> + u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> inst.op = CMDQ_CODE_WFE;
> - inst.value = CMDQ_WFE_OPTION;
> + inst.value = CMDQ_WFE_OPTION | clear_option;
> inst.event = event;
>
> return cmdq_pkt_append_command(pkt, inst);
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 3f6bc0dfd5da..42d2a30e6a70 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -27,8 +27,7 @@
> * bit 16-27: update value
> * bit 31: 1 - update, 0 - no update
> */
> -#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE |
> CMDQ_WFE_WAIT | \
> - CMDQ_WFE_WAIT_VALUE)
> +#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT |
> CMDQ_WFE_WAIT_VALUE)
>
> /** cmdq event maximum */
> #define CMDQ_MAX_EVENT 0x3ff
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 1a6c56f3bec1..d63749440697 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -152,11 +152,12 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16
> high_addr_reg_idx,
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @event: the desired event type to "wait and CLEAR"
> + * @event: the desired event type to wait
> + * @clear: clear event or not after event arrive
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
>
> /**
> * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
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Re: [PATCH v4 02/13] mailbox: cmdq: variablize address shift in platform
Hi, Dennis:
On Wed, 2020-03-04 at 10:32 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> > Some gce hardware shift pc and end address in register to support
> > large dram addressing.
> > Implement gce address shift when write or read pc and end register.
> > And add shift bit in platform definition.
> >
> > Signed-off-by: Dennis YC Hsieh
> > ---
> > drivers/mailbox/mtk-cmdq-mailbox.c | 61 ++--
> > drivers/soc/mediatek/mtk-cmdq-helper.c | 3 +-
> > include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> > 3 files changed, 50 insertions(+), 16 deletions(-)
> >
>
> [snip]
>
> >
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index de20e6cba83b..2e1bc513569b 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -291,7 +291,8 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> >
> > /* JUMP to end */
> > inst.op = CMDQ_CODE_JUMP;
> > - inst.value = CMDQ_JUMP_PASS;
> > + inst.value = CMDQ_JUMP_PASS >>
> > + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
>
> Why not just cmdq_mbox_shift(pkt->cl->chan) ?
Sorry, the type of pkt->cl is 'void *', so you need to cast it.
Reviewed-by: CK Hu
>
> Regards,
> CK
>
> > err = cmdq_pkt_append_command(pkt, inst);
> >
> > return err;
> > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> > b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > index a4dc45fbec0a..dfe5b2eb85cc 100644
> > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > @@ -88,4 +88,6 @@ struct cmdq_pkt {
> > void*cl;
> > };
> >
> > +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> > +
> > #endif /* __MTK_CMDQ_MAILBOX_H__ */
>
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Re: [PATCH v4 11/13] soc: mediatek: cmdq: add jump function
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Add jump function so that client can jump to any address which
> contains instruction.
>
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 12
> include/linux/soc/mediatek/mtk-cmdq.h | 11 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 59bc1164b411..f27c67034880 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -372,6 +372,18 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx,
> u32 value)
> }
> EXPORT_SYMBOL(cmdq_pkt_assign);
>
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + inst.op = CMDQ_CODE_JUMP;
> + inst.offset = 1;
Symbolize the value '1'.
Regards,
CK
> + inst.value = addr >>
> + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_jump);
> +
> int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 99e77155f967..1a6c56f3bec1 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -213,6 +213,17 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> */
> int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
>
> +/**
> + * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE
> + *to execute an instruction that change current thread PC to
> + *a physical address which should contains more instruction.
> + * @pkt:the CMDQ packet
> + * @addr: physical address of target instruction buffer
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
> +
> /**
> * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
> * @pkt: the CMDQ packet
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Re: [PATCH v4 10/13] soc: mediatek: cmdq: export finalize function
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Export finalize function to client which helps append eoc and jump
> command to pkt. Let client decide call finalize or not.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
> drivers/soc/mediatek/mtk-cmdq-helper.c | 7 ++-
> include/linux/soc/mediatek/mtk-cmdq.h | 8
> 3 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 0dfcd1787e65..7daaabc26eb1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -490,6 +490,7 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc
> *mtk_crtc)
> cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> mtk_crtc_ddp_config(crtc, cmdq_handle);
> + cmdq_pkt_finalize(cmdq_handle);
> cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
> }
> #endif
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index a9ebbabb7439..59bc1164b411 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -372,7 +372,7 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx,
> u32 value)
> }
> EXPORT_SYMBOL(cmdq_pkt_assign);
>
> -static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> +int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction inst = { {0} };
> int err;
> @@ -392,6 +392,7 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
>
> return err;
> }
> +EXPORT_SYMBOL(cmdq_pkt_finalize);
>
> static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data)
> {
> @@ -426,10 +427,6 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> unsigned long flags = 0;
> struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
>
> - err = cmdq_pkt_finalize(pkt);
> - if (err < 0)
> - return err;
> -
> pkt->cb.cb = cb;
> pkt->cb.data = data;
> pkt->async_cb.cb = cmdq_pkt_flush_async_cb;
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index fec292aac83c..99e77155f967 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -213,6 +213,14 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> */
> int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
>
> +/**
> + * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
> + * @pkt: the CMDQ packet
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
> +
> /**
> * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
> * packet and call back at the end of done packet
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Re: [PATCH v4 05/13] soc: mediatek: cmdq: return send msg error code
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Return error code to client if send message fail,
> so that client has chance to error handling.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> Fixes: 576f1b4bc802 ("soc: mediatek: Add Mediatek CMDQ helper")
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 2e1bc513569b..98f23ba3ba47 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -351,7 +351,9 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> spin_unlock_irqrestore(>lock, flags);
> }
>
> - mbox_send_message(client->chan, pkt);
> + err = mbox_send_message(client->chan, pkt);
> + if (err < 0)
> + return err;
> /* We can send next packet immediately, so just call txdone. */
> mbox_client_txdone(client->chan, 0);
>
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Re: [PATCH v4 04/13] mailbox: mediatek: cmdq: clear task in channel before shutdown
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Do success callback in channel when shutdown. For those task not finish,
> callback with error code thus client has chance to cleanup or reset.
>
Reviewed-by: CK Hu
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9994ac9426d6..b56d340c8982 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan,
> void *data)
>
> if (list_empty(>task_busy_list)) {
> WARN_ON(clk_enable(cmdq->clock) < 0);
> + /*
> + * The thread reset will clear thread related register to 0,
> + * including pc, end, priority, irq, suspend and enable. Thus
> + * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
> + * thread and make it running.
> + */
> WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
>
> writel(task->pa_base >> cmdq->shift_pa,
> @@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
>
> static void cmdq_mbox_shutdown(struct mbox_chan *chan)
> {
> + struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
> + struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
> + struct cmdq_task *task, *tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(>chan->lock, flags);
> + if (list_empty(>task_busy_list))
> + goto done;
> +
> + WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> +
> + /* make sure executed tasks have success callback */
> + cmdq_thread_irq_handler(cmdq, thread);
> + if (list_empty(>task_busy_list))
> + goto done;
> +
> + list_for_each_entry_safe(task, tmp, >task_busy_list,
> + list_entry) {
> + cmdq_task_exec_done(task, CMDQ_CB_ERROR);
> + kfree(task);
> + }
> +
> + cmdq_thread_disable(cmdq, thread);
> + clk_disable(cmdq->clock);
> +done:
> + /*
> + * The thread->task_busy_list empty means thread already disable. The
> + * cmdq_mbox_send_data() always reset thread which clear disable and
> + * suspend statue when first pkt send to channel, so there is no need
> + * to do any operation here, only unlock and leave.
> + */
> + spin_unlock_irqrestore(>chan->lock, flags);
> }
>
> static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
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Re: [PATCH v4 02/13] mailbox: cmdq: variablize address shift in platform
Hi, Dennis:
On Tue, 2020-03-03 at 18:58 +0800, Dennis YC Hsieh wrote:
> Some gce hardware shift pc and end address in register to support
> large dram addressing.
> Implement gce address shift when write or read pc and end register.
> And add shift bit in platform definition.
>
> Signed-off-by: Dennis YC Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 61 ++--
> drivers/soc/mediatek/mtk-cmdq-helper.c | 3 +-
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> 3 files changed, 50 insertions(+), 16 deletions(-)
>
[snip]
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index de20e6cba83b..2e1bc513569b 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -291,7 +291,8 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
>
> /* JUMP to end */
> inst.op = CMDQ_CODE_JUMP;
> - inst.value = CMDQ_JUMP_PASS;
> + inst.value = CMDQ_JUMP_PASS >>
> + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
Why not just cmdq_mbox_shift(pkt->cl->chan) ?
Regards,
CK
> err = cmdq_pkt_append_command(pkt, inst);
>
> return err;
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index a4dc45fbec0a..dfe5b2eb85cc 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -88,4 +88,6 @@ struct cmdq_pkt {
> void*cl;
> };
>
> +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> +
> #endif /* __MTK_CMDQ_MAILBOX_H__ */
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Re: [PATCH v10 3/5] soc: mediatek: Move mt8173 MMSYS to platform driver
Hi, Matthias:
On Thu, 2020-02-27 at 19:22 +0100, Matthias Brugger wrote:
>
> On 27/02/2020 19:21, Matthias Brugger wrote:
> >
> >
> > On 27/02/2020 19:08, Enric Balletbo i Serra wrote:
> >> From: Matthias Brugger
> >>
> >> There is no strong reason for this to use CLK_OF_DECLARE instead of
> >> being a platform driver. Plus, this driver provides clocks but also
> >> a shared register space for the mediatek-drm and the mediatek-mdp
> >> driver. So move to drivers/soc/mediatek as a platform driver.
> >>
> >> Signed-off-by: Matthias Brugger
> >> Signed-off-by: Enric Balletbo i Serra
> >> ---
> >
> > regarding the merge strategy, I propose that CK takes it through his tree
> > and
> > provides a stable branch in case I'll need to put some patches on top of the
> > drivers/soc part.
> >
>
> Sorry, that was meant for 4/5 not this patch.
>
> > Makes sense?
There are many dependencies in this series, so I would like to apply
this series to a tree together. I think mmsys driver is major of this
series, and this series does not conflict with Mediatek DRM tree now, so
I would like to apply this series to soc tree. How do you think?
Regards,
CK
> >
> > Regards,
> > Matthias
> >
> >>
> >> Changes in v10:
> >> - Renamed to be generic mtk-mmsys
> >> - Add driver data support to be able to support diferent SoCs
> >>
> >> Changes in v9:
> >> - Move mmsys to drivers/soc/mediatek (CK)
> >>
> >> Changes in v8:
> >> - Be a builtin_platform_driver like other mediatek mmsys drivers.
> >>
> >> Changes in v7:
> >> - Free clk_data->clks as well
> >> - Get rid of private data structure
> >>
> >> drivers/clk/mediatek/clk-mt8173.c | 104
> >> drivers/soc/mediatek/Kconfig | 7 ++
> >> drivers/soc/mediatek/Makefile | 1 +
> >> drivers/soc/mediatek/mtk-mmsys.c | 154 ++
> >> 4 files changed, 162 insertions(+), 104 deletions(-)
> >> create mode 100644 drivers/soc/mediatek/mtk-mmsys.c
> >>
> >> diff --git a/drivers/clk/mediatek/clk-mt8173.c
> >> b/drivers/clk/mediatek/clk-mt8173.c
> >> index 537a7f49b0f7..8f898ac476c0 100644
> >> --- a/drivers/clk/mediatek/clk-mt8173.c
> >> +++ b/drivers/clk/mediatek/clk-mt8173.c
> >> @@ -753,93 +753,6 @@ static const struct mtk_gate img_clks[] __initconst =
> >> {
> >>GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
> >> };
> >>
> >> -static const struct mtk_gate_regs mm0_cg_regs __initconst = {
> >> - .set_ofs = 0x0104,
> >> - .clr_ofs = 0x0108,
> >> - .sta_ofs = 0x0100,
> >> -};
> >> -
> >> -static const struct mtk_gate_regs mm1_cg_regs __initconst = {
> >> - .set_ofs = 0x0114,
> >> - .clr_ofs = 0x0118,
> >> - .sta_ofs = 0x0110,
> >> -};
> >> -
> >> -#define GATE_MM0(_id, _name, _parent, _shift) { \
> >> - .id = _id, \
> >> - .name = _name, \
> >> - .parent_name = _parent, \
> >> - .regs = _cg_regs, \
> >> - .shift = _shift,\
> >> - .ops = _clk_gate_ops_setclr,\
> >> - }
> >> -
> >> -#define GATE_MM1(_id, _name, _parent, _shift) { \
> >> - .id = _id, \
> >> - .name = _name, \
> >> - .parent_name = _parent, \
> >> - .regs = _cg_regs, \
> >> - .shift = _shift,\
> >> - .ops = _clk_gate_ops_setclr,\
> >> - }
> >> -
> >> -static const struct mtk_gate mm_clks[] __initconst = {
> >> - /* MM0 */
> >> - GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> >> - GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> >> - GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
> >> - GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
> >> - GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
> >> - GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
> >> - GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
> >> - GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
> >> - GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
> >> - GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
> >> - GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
> >> - GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
> >> - GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
> >> - GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
> >> - GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
> >> - GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
> >> - GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
> >> - GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
> >> - GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
> >> -
Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Enric:
On Mon, 2020-03-02 at 12:01 +0100, Enric Balletbo i Serra wrote:
> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> Those functions will allow DRM driver and others to control the data
> path routing.
>
Reviewed-by: CK Hu
But what is the base of this series? When I apply this patch to 5.6-rc1,
some error happen, the apply --reject result is
In drivers/gpu/drm/mediatek/mtk_drm_crtc.c.rej
diff a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c(rejected hunks)
@@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
*mtk_crtc)
}
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
- mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
-mtk_crtc->ddp_comp[i]->id,
-mtk_crtc->ddp_comp[i + 1]->id);
+ mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
+ mtk_crtc->ddp_comp[i]->id,
+ mtk_crtc->ddp_comp[i + 1]->id);
mtk_disp_mutex_add_comp(mtk_crtc->mutex,
mtk_crtc->ddp_comp[i]->id);
}
I's trivial for me to fix this conflicts, so you have better to notice
what is the base of this series in cover latter.
Regards,
CK
> Signed-off-by: Enric Balletbo i Serra
> Reviewed-by: Matthias Brugger
> ---
>
> Changes in v11:
> - Select CONFIG_MTK_MMSYS (CK)
> - Pass device pointer of mmsys device instead of config regs (CK)
>
> Changes in v10:
> - Introduced a new patch to move routing control into mmsys driver.
> - Removed the patch to use regmap as is not needed anymore.
>
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
>
> drivers/gpu/drm/mediatek/Kconfig| 1 +
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 --
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
> drivers/soc/mediatek/mtk-mmsys.c| 277
> include/linux/soc/mediatek/mtk-mmsys.h | 20 ++
> 8 files changed, 314 insertions(+), 282 deletions(-)
> create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
>
> diff --git a/drivers/gpu/drm/mediatek/Kconfig
> b/drivers/gpu/drm/mediatek/Kconfig
> index fa5ffc4fe823..c420f5a3d33b 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
> select DRM_MIPI_DSI
> select DRM_PANEL
> select MEMORY
> + select MTK_MMSYS
> select MTK_SMI
> select VIDEOMODE_HELPERS
> help
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index fd4042de12f2..f63a885e063c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -28,7 +29,7 @@
> * @enabled: records whether crtc_enable succeeded
> * @planes: array of 4 drm_plane structures, one for each overlay plane
> * @pending_planes: whether any plane has pending changes to be applied
> - * @config_regs: memory mapped mmsys configuration register space
> + * @mmsys_dev: pointer to the mmsys device for configuration registers
> * @mutex: handle to one of the ten disp_mutex streams
> * @ddp_comp_nr: number of components in ddp_comp
> * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
> u32 cmdq_event;
> #endif
>
> - void __iomem*config_regs;
> + struct device *mmsys_dev;
> struct mtk_disp_mutex *mutex;
> unsigned intddp_comp_nr;
> struct mtk_ddp_comp **ddp_comp;
> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> - mtk_crtc->ddp_comp[i]->id,
> - mtk_crtc->ddp_comp[i + 1]->id);
> + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> + mtk_crtc->ddp_comp[i]->id,
> +
Re: [PATCH v10 5/5] soc / drm: mediatek: Fix mediatek-drm device probing
Hi, Enric:
On Thu, 2020-02-27 at 19:08 +0100, Enric Balletbo i Serra wrote:
> In the actual implementation the same compatible string
> "mediatek,-mmsys" is used to bind the clock drivers
> (drivers/soc/mediatek) as well as to the gpu driver
> (drivers/gpu/drm/mediatek/mtk_drm_drv.c). This ends with the problem
> that the only probed driver is the clock driver and there is no display
> at all.
>
> In any case having the same compatible string for two drivers is not
> correct and should be fixed. To fix this, and maintain backward
> compatibility, we can consider that the mmsys driver is the top-level
> entry point for the multimedia subsystem, so is not a pure clock
> controller but a system controller, and the drm driver is instantiated
> by that MMSYS driver.
Reviewed-by: CK Hu
>
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Match driver data to get display routing.
>
> Changes in v9:
> - Do not move the display routing from the drm driver (CK)
>
> Changes in v8:
> - New patch introduced in this series.
>
> Changes in v7: None
>
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 31 --
> drivers/soc/mediatek/mtk-mmsys.c | 6 +
> 2 files changed, 25 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 02011d3168df..29252fc0aab7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -422,9 +422,21 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] =
> {
> { }
> };
>
> +static const struct of_device_id mtk_drm_of_ids[] = {
> + { .compatible = "mediatek,mt2701-mmsys",
> + .data = _mmsys_driver_data},
> + { .compatible = "mediatek,mt2712-mmsys",
> + .data = _mmsys_driver_data},
> + { .compatible = "mediatek,mt8173-mmsys",
> + .data = _mmsys_driver_data},
> + { }
> +};
> +
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = >dev;
> + struct device_node *phandle = dev->parent->of_node;
> + const struct of_device_id *of_id;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> @@ -443,8 +455,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> + of_id = of_match_node(mtk_drm_of_ids, phandle);
> + if (!of_id)
> + return -ENODEV;
> +
> + private->data = of_id->data;
> +
> /* Iterate over sibling DISP function blocks */
> - for_each_child_of_node(dev->of_node->parent, node) {
> + for_each_child_of_node(phandle->parent, node) {
> const struct of_device_id *of_id;
> enum mtk_ddp_comp_type comp_type;
> int comp_id;
> @@ -576,22 +594,11 @@ static int mtk_drm_sys_resume(struct device *dev)
> static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
>mtk_drm_sys_resume);
>
> -static const struct of_device_id mtk_drm_of_ids[] = {
> - { .compatible = "mediatek,mt2701-mmsys",
> - .data = _mmsys_driver_data},
> - { .compatible = "mediatek,mt2712-mmsys",
> - .data = _mmsys_driver_data},
> - { .compatible = "mediatek,mt8173-mmsys",
> - .data = _mmsys_driver_data},
> - { }
> -};
> -
> static struct platform_driver mtk_drm_platform_driver = {
> .probe = mtk_drm_probe,
> .remove = mtk_drm_remove,
> .driver = {
> .name = "mediatek-drm",
> - .of_match_table = mtk_drm_of_ids,
> .pm = _drm_pm_ops,
> },
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index a8a98777064e..d99c8beb2ed2 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -377,6 +377,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> const struct mtk_mmsys_driver_data *data;
> struct clk_onecell_data *clk_data;
> struct device *dev = >dev;
> + struct platform_device *drm;
> void __iomem *config_regs;
> struct resource *mem;
> int ret;
> @@ -407,6 +408,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> + drm = platform_device_register_data(>dev, "mediatek-drm",
> + PLATFORM_DEVID_NONE, NULL, 0);
> + if (IS_ERR(drm))
> + return PTR_ERR(drm);
> +
> return 0;
> }
>
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Re: [PATCH v10 4/5] soc / drm: mediatek: Move routing control to mmsys device
Hi, Enric:
On Thu, 2020-02-27 at 19:08 +0100, Enric Balletbo i Serra wrote:
> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> Those functions will allow DRM driver and others to control the data
> path routing.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Introduced a new patch to move routing control into mmsys driver.
> - Removed the patch to use regmap as is not needed anymore.
>
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
>
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 13 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 --
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 13 +-
> drivers/soc/mediatek/mtk-mmsys.c| 275
> include/linux/soc/mediatek/mtk-mmsys.h | 19 ++
> 6 files changed, 306 insertions(+), 277 deletions(-)
> create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index fd4042de12f2..3c89449bea6e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -6,6 +6,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> *mtk_crtc)
> }
>
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> - mtk_crtc->ddp_comp[i]->id,
> - mtk_crtc->ddp_comp[i + 1]->id);
> + mtk_mmsys_ddp_connect(mtk_crtc->config_regs,
> + mtk_crtc->ddp_comp[i]->id,
> + mtk_crtc->ddp_comp[i + 1]->id);
When CONFIG_MTK_MMSYS is not enable, this would built fail. So make some
modification in Kconfig.
> mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> mtk_crtc->ddp_comp[i]->id);
> }
> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
> *mtk_crtc)
> mtk_crtc->ddp_comp[i]->id);
> mtk_disp_mutex_disable(mtk_crtc->mutex);
> for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> - mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> - mtk_crtc->ddp_comp[i]->id,
> - mtk_crtc->ddp_comp[i + 1]->id);
> + mtk_mmsys_ddp_disconnect(mtk_crtc->config_regs,
> + mtk_crtc->ddp_comp[i]->id,
> + mtk_crtc->ddp_comp[i + 1]->id);
> mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
> mtk_crtc->ddp_comp[i]->id);
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index b885f60f474c..014c1bbe1df2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -13,26 +13,6 @@
> #include "mtk_drm_ddp.h"
> #include "mtk_drm_ddp_comp.h"
>
[snip]
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> new file mode 100644
> index ..02fd86e62a8d
> --- /dev/null
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MMSYS_H
> +#define __MTK_MMSYS_H
> +
> +enum mtk_ddp_comp_id;
> +
> +void mtk_mmsys_ddp_connect(void __iomem *config_regs,
I prefer the first parameter to be 'struct device *dev' which is the
device pointer of mmsys device. and mmsys driver could use this pointer
to get its register address.
Regards,
CK
> +enum mtk_ddp_comp_id cur,
> +enum mtk_ddp_comp_id next);
> +
> +void mtk_mmsys_ddp_disconnect(void __iomem *config_regs,
> + enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next);
> +
> +#endif /* __MTK_MMSYS_H */
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Re: [PATCH v10 3/5] soc: mediatek: Move mt8173 MMSYS to platform driver
Hi, Enric:
On Thu, 2020-02-27 at 19:08 +0100, Enric Balletbo i Serra wrote:
> From: Matthias Brugger
>
> There is no strong reason for this to use CLK_OF_DECLARE instead of
> being a platform driver. Plus, this driver provides clocks but also
> a shared register space for the mediatek-drm and the mediatek-mdp
> driver. So move to drivers/soc/mediatek as a platform driver.
>
Reviewed-by: CK Hu
> Signed-off-by: Matthias Brugger
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Renamed to be generic mtk-mmsys
> - Add driver data support to be able to support diferent SoCs
>
> Changes in v9:
> - Move mmsys to drivers/soc/mediatek (CK)
>
> Changes in v8:
> - Be a builtin_platform_driver like other mediatek mmsys drivers.
>
> Changes in v7:
> - Free clk_data->clks as well
> - Get rid of private data structure
>
> drivers/clk/mediatek/clk-mt8173.c | 104
> drivers/soc/mediatek/Kconfig | 7 ++
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 154 ++
> 4 files changed, 162 insertions(+), 104 deletions(-)
> create mode 100644 drivers/soc/mediatek/mtk-mmsys.c
>
> diff --git a/drivers/clk/mediatek/clk-mt8173.c
> b/drivers/clk/mediatek/clk-mt8173.c
> index 537a7f49b0f7..8f898ac476c0 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -753,93 +753,6 @@ static const struct mtk_gate img_clks[] __initconst = {
> GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
> };
>
> -static const struct mtk_gate_regs mm0_cg_regs __initconst = {
> - .set_ofs = 0x0104,
> - .clr_ofs = 0x0108,
> - .sta_ofs = 0x0100,
> -};
> -
> -static const struct mtk_gate_regs mm1_cg_regs __initconst = {
> - .set_ofs = 0x0114,
> - .clr_ofs = 0x0118,
> - .sta_ofs = 0x0110,
> -};
> -
> -#define GATE_MM0(_id, _name, _parent, _shift) { \
> - .id = _id, \
> - .name = _name, \
> - .parent_name = _parent, \
> - .regs = _cg_regs, \
> - .shift = _shift,\
> - .ops = _clk_gate_ops_setclr,\
> - }
> -
> -#define GATE_MM1(_id, _name, _parent, _shift) { \
> - .id = _id, \
> - .name = _name, \
> - .parent_name = _parent, \
> - .regs = _cg_regs, \
> - .shift = _shift,\
> - .ops = _clk_gate_ops_setclr,\
> - }
> -
> -static const struct mtk_gate mm_clks[] __initconst = {
> - /* MM0 */
> - GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> - GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> - GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
> - GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
> - GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
> - GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
> - GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
> - GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
> - GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
> - GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
> - GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
> - GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
> - GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
> - GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
> - GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
> - GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
> - GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
> - GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
> - GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
> - GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
> - GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
>
Re: [PATCH v10 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller
Hi, Enric:
On Thu, 2020-02-27 at 19:08 +0100, Enric Balletbo i Serra wrote:
> The mmsys system controller is not only a pure clock controller, so
> update the binding documentation to reflect that apart from providing
> clocks, it also provides routing and miscellaneous control registers.
>
Reviewed-by: CK Hu
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v10:
> - Update the binding documentation for the mmsys system controller.
>
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
>
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt| 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> index 301eefbe1618..8d6a9d98e7a6 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> @@ -1,7 +1,8 @@
> Mediatek mmsys controller
>
>
> -The Mediatek mmsys controller provides various clocks to the system.
> +The Mediatek mmsys system controller provides clock control, routing control,
> +and miscellaneous control in mmsys partition.
>
> Required Properties:
>
> @@ -15,13 +16,13 @@ Required Properties:
> - "mediatek,mt8183-mmsys", "syscon"
> - #clock-cells: Must be 1
>
> -The mmsys controller uses the common clk binding from
> +For the clock control, the mmsys controller uses the common clk binding from
> Documentation/devicetree/bindings/clock/clock-bindings.txt
> The available clocks are defined in dt-bindings/clock/mt*-clk.h.
>
> Example:
>
> -mmsys: clock-controller@1400 {
> +mmsys: syscon@1400 {
> compatible = "mediatek,mt8173-mmsys", "syscon";
> reg = <0 0x1400 0 0x1000>;
> #clock-cells = <1>;
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Re: [PATCH v9 1/4] drm/mediatek: Use regmap for register access
Hi, Enric:
On Thu, 2020-02-27 at 09:45 +0100, Enric Balletbo i Serra wrote:
> Hi CK,
>
> On 27/2/20 2:10, CK Hu wrote:
> > Hi, Enric:
> >
> > On Wed, 2020-02-26 at 11:54 +0100, Enric Balletbo i Serra wrote:
> >> From: Matthias Brugger
> >>
> >> The mmsys memory space is shared between the drm and the
> >> clk driver. Use regmap to access it.
> >
> > Once there is a mmsys driver and clock control is moved into mmsys
> > driver, I think we should also move routing control into mmsys driver
> > and we could drop this patch.
> >
>
> Do you want me do this in this series or later?
I would like you to do it in this series. If you move routing control to
mmsys driver, you need not to use regmap any more. What you need to move
is what you modify in this patch. mmsys may provide mtk_mmsys_connect()
and mtk_mmsys_disconnect() function to replace
mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). DRM
driver need not to map mmsys's register and just keep mmsys device
pointer. You could move routing control after clock control has been
moved.
Regards,
CK
>
> Thanks,
> Enric
>
> > Regards,
> > CK
> >
> >>
> >> Signed-off-by: Matthias Brugger
> >> Reviewed-by: Philipp Zabel
> >> Reviewed-by: CK Hu
> >> Signed-off-by: Enric Balletbo i Serra
> >> ---
> >>
> >> Changes in v9: None
> >> Changes in v8:
> >> - Select REGMAP and MFD_SYSCON (Randy Dunlap)
> >>
> >> Changes in v7:
> >> - Add R-by from CK
> >>
> >> drivers/gpu/drm/mediatek/Kconfig| 2 +
> >> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +-
> >> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50 +++--
> >> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 4 +-
> >> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 13 ++-
> >> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
> >> 6 files changed, 32 insertions(+), 43 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/mediatek/Kconfig
> >> b/drivers/gpu/drm/mediatek/Kconfig
> >> index fa5ffc4fe823..89e18a473cb5 100644
> >> --- a/drivers/gpu/drm/mediatek/Kconfig
> >> +++ b/drivers/gpu/drm/mediatek/Kconfig
> >> @@ -10,8 +10,10 @@ config DRM_MEDIATEK
> >>select DRM_KMS_HELPER
> >>select DRM_MIPI_DSI
> >>select DRM_PANEL
> >> + select MFD_SYSCON
> >>select MEMORY
> >>select MTK_SMI
> >> + select REGMAP
> >>select VIDEOMODE_HELPERS
> >>help
> >> Choose this option if you have a Mediatek SoCs.
> >> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >> index 5ee74d7ce35c..a236499123aa 100644
> >> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >> @@ -28,7 +28,7 @@
> >> * @enabled: records whether crtc_enable succeeded
> >> * @planes: array of 4 drm_plane structures, one for each overlay plane
> >> * @pending_planes: whether any plane has pending changes to be applied
> >> - * @config_regs: memory mapped mmsys configuration register space
> >> + * @config_regs: regmap mapped mmsys configuration register space
> >> * @mutex: handle to one of the ten disp_mutex streams
> >> * @ddp_comp_nr: number of components in ddp_comp
> >> * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this
> >> crtc
> >> @@ -50,7 +50,7 @@ struct mtk_drm_crtc {
> >>u32 cmdq_event;
> >> #endif
> >>
> >> - void __iomem*config_regs;
> >> + struct regmap *config_regs;
> >>struct mtk_disp_mutex *mutex;
> >>unsigned intddp_comp_nr;
> >>struct mtk_ddp_comp **ddp_comp;
> >> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >> index 13035c906035..302753744cc6 100644
> >> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >> @@ -383,61 +383,53 @@ static unsigned int mtk_ddp_sel_in(enum
> >> mtk_ddp_comp_id cur,
> >>return value;
> >> }
> >>
> >> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> >> +static void mtk_ddp_sout_sel(struct regmap *config_regs,
> >> enum mtk_ddp_comp_id c
