[PATCH libdrm] tests/amdgpu: minor fix for dispatch/draw test
1. clear cmd buffer
2. make amdgpu_memcpy_dispatch_test static
3. tab/space fix
Change-Id: Idf55f8881f66458b585092eccb55b6042520e4ad
Signed-off-by: Flora Cui
---
tests/amdgpu/basic_tests.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index a364f67..2d47269 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -2177,6 +2177,7 @@ static void
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
_cmd, (void **)_cmd,
_address_cmd, _cmd);
CU_ASSERT_EQUAL(r, 0);
+ memset(ptr_cmd, 0, bo_cmd_size);
r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2227,7 +2228,7 @@ static void
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
ptr_cmd[i++] = 1;
while (i & 7)
- ptr_cmd[i++] = 0x1000; /* type3 nop packet */
+ ptr_cmd[i++] = 0x1000; /* type3 nop packet */
resources[0] = bo_dst;
resources[1] = bo_shader;
@@ -2283,9 +2284,9 @@ static void
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
CU_ASSERT_EQUAL(r, 0);
}
-void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
-uint32_t ip_type,
-uint32_t ring)
+static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
+ uint32_t ip_type,
+ uint32_t ring)
{
amdgpu_context_handle context_handle;
amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
@@ -2313,6 +2314,7 @@ void amdgpu_memcpy_dispatch_test(amdgpu_device_handle
device_handle,
_cmd, (void **)_cmd,
_address_cmd, _cmd);
CU_ASSERT_EQUAL(r, 0);
+ memset(ptr_cmd, 0, bo_cmd_size);
r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2371,7 +2373,7 @@ void amdgpu_memcpy_dispatch_test(amdgpu_device_handle
device_handle,
ptr_cmd[i++] = 1;
while (i & 7)
- ptr_cmd[i++] = 0x1000; /* type3 nop packet */
+ ptr_cmd[i++] = 0x1000; /* type3 nop packet */
resources[0] = bo_shader;
resources[1] = bo_src;
@@ -2799,7 +2801,8 @@ void amdgpu_memset_draw(amdgpu_device_handle
device_handle,
AMDGPU_GEM_DOMAIN_GTT, 0,
_cmd, (void **)_cmd,
_address_cmd, _cmd);
-CU_ASSERT_EQUAL(r, 0);
+ CU_ASSERT_EQUAL(r, 0);
+ memset(ptr_cmd, 0, bo_cmd_size);
r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2828,7 +2831,7 @@ void amdgpu_memset_draw(amdgpu_device_handle
device_handle,
i += amdgpu_draw_draw(ptr_cmd + i);
while (i & 7)
- ptr_cmd[i++] = 0x1000; /* type3 nop packet */
+ ptr_cmd[i++] = 0x1000; /* type3 nop packet */
resources[0] = bo_dst;
resources[1] = bo_shader_ps;
@@ -2952,6 +2955,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle
device_handle,
_cmd, (void **)_cmd,
_address_cmd, _cmd);
CU_ASSERT_EQUAL(r, 0);
+ memset(ptr_cmd, 0, bo_cmd_size);
r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2999,7 +3003,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle
device_handle,
i += amdgpu_draw_draw(ptr_cmd + i);
while (i & 7)
- ptr_cmd[i++] = 0x1000; /* type3 nop packet */
+ ptr_cmd[i++] = 0x1000; /* type3 nop packet */
resources[0] = bo_dst;
resources[1] = bo_src;
--
2.7.4
___
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dri-devel@lists.freedesktop.org
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[PATCH libdrm 1/4] tests/amdgpu: add memset dispatch test
add memset dispatch test for gfx9
v2: disable dispatch test for other ASICs
Change-Id: I55a410a4ea0a6d19d1aca1f172e1dfcbbd1112fa
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 273 -
2 files changed, 276 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf4409..35324cb 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -436,6 +436,11 @@ static void amdgpu_disable_suites()
if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency
Test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+
+ /* This test was ran on GFX9 only */
+ if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+ if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test",
CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
}
/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index dbae4d5..fe6db09 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
+static void amdgpu_dispatch_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -70,6 +71,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
+ { "Dispatch Test", amdgpu_dispatch_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -117,6 +119,7 @@ CU_TestInfo basic_tests[] = {
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
+#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
/* Packet 3 types */
#definePACKET3_NOP 0x10
@@ -245,8 +248,11 @@ CU_TestInfo basic_tests[] = {
#definePACKET3_SET_SH_REG_START
0x2c00
#definePACKET3_DISPATCH_DIRECT 0x15
-
-
+#define PACKET3_EVENT_WRITE0x46
+#define PACKET3_ACQUIRE_MEM0x58
+#define PACKET3_SET_CONTEXT_REG0x69
+#define PACKET3_SET_UCONFIG_REG0x79
+#define PACKET3_DRAW_INDEX_AUTO0x2D
/* gfx 8 */
#define mmCOMPUTE_PGM_LO
0x2e0c
#define mmCOMPUTE_PGM_RSRC1
0x2e12
@@ -286,6 +292,25 @@ static uint32_t shader_bin[] = {
#define CODE_OFFSET 512
#define DATA_OFFSET 1024
+enum cs_type {
+ CS_BUFFERCLEAR,
+};
+
+static const uint32_t bufferclear_cs_shader_gfx9[] = {
+0xD1FD, 0x04010C08, 0x7E020204, 0x7E040205,
+0x7E060206, 0x7E080207, 0xE01C2000, 0x8100,
+0xBF81
+};
+
+static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
+ {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
+ {0x2e13, 0x0090}, //{ mmCOMPUTE_PGM_RSRC2, 0x0090 },
+ {0x2e07, 0x0040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x0040 },
+ {0x2e08, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x0001 },
+ {0x2e09, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x0001 }
+};
+
+static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
@@ -1883,3 +1908,247 @@ static void amdgpu_sync_dependency_test(void)
free(ibs_request.dependencies);
}
+
+static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
+ int cs_type)
+{
+ uint32_t shader_size;
+ const uint32_t *shader;
+
+ switch (cs_type) {
+ case CS_BUFFERCLEAR:
+ shader = bufferclear_cs_shader_gfx9;
+ shader_size = sizeof(bufferclear_cs_shader_gfx9);
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ memcpy(ptr, shader, shader_size);
+ return 0;
+}
+
[PATCH libdrm 4/4] tests/amdgpu: add memcpy draw test
add memcpy draw test for gfx9
Change-Id: Ib80e55b1ab7aa556c4b5adfdd39aedf7d58ba628
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/basic_tests.c | 264 +++--
1 file changed, 253 insertions(+), 11 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 0ba6199..a364f67 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -343,7 +343,8 @@ static const uint32_t preamblecache_gfx9[] = {
};
enum ps_type {
- PS_CONST
+ PS_CONST,
+ PS_TEX
};
static const uint32_t ps_const_shader_gfx9[] = {
@@ -391,6 +392,49 @@ static const uint32_t ps_const_context_reg_gfx9[][2] = {
{0xA1C5, 0x0004}, //{ mmSPI_SHADER_COL_FORMAT, 0x0004 }
};
+static const uint32_t ps_tex_shader_gfx9[] = {
+0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD418,
+0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
+0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD296,
+0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
+0x0100, 0xBF81
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
+0x000B
+};
+
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
+{{ 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001890, 0x
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001801, 0x0002
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001803, 0x0302
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001803, 0x0502
},
+ { 0xD296, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x0100
},
+ { 0xD295, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x0100
},
+ { 0xD294, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x0100
},
+ { 0xD297, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x0100
},
+ { 0xD298, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x0100
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC400180F, 0x05040302 }
+}
+};
+
+static const uint32_t ps_tex_sh_registers_gfx9[][2] = {
+{0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
+{0x2C0B, 0x0018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x0018 }
+};
+
+static const uint32_t ps_tex_context_reg_gfx9[][2] = {
+{0xA1B4, 0x0002}, //{ mmSPI_PS_INPUT_ADDR, 0x0002 },
+{0xA1B6, 0x0001}, //{ mmSPI_PS_IN_CONTROL, 0x0001 },
+{0xA08F, 0x000F}, //{ mmCB_SHADER_MASK, 0x000F },
+{0xA203, 0x0010}, //{ mmDB_SHADER_CONTROL, 0x0010 },
+{0xA1C4, 0x}, //{ mmSPI_SHADER_Z_FORMAT, 0x },
+{0xA1B8, 0x}, //{ mmSPI_BARYC_CNTL, 0x /* Always
0 for now */},
+{0xA1C5, 0x0004}, //{ mmSPI_SHADER_COL_FORMAT, 0x0004 }
+};
+
static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
0x7E000B00, 0x02F3, 0xD042000A, 0x00010100,
0x7E020202, 0x7E040200, 0x02F3, 0x7E060206,
@@ -2425,6 +2469,13 @@ static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int
ps_type)
patchinfo_code_size =
ps_const_shader_patchinfo_code_size_gfx9;
patchcode_offset =
ps_const_shader_patchinfo_offset_gfx9;
break;
+ case PS_TEX:
+ shader = ps_tex_shader_gfx9;
+ shader_size = sizeof(ps_tex_shader_gfx9);
+ patchinfo_code = (const uint32_t
*)ps_tex_shader_patchinfo_code_gfx9;
+ patchinfo_code_size =
ps_tex_shader_patchinfo_code_size_gfx9;
+ patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9;
+ break;
default:
return -1;
break;
@@ -2578,7 +2629,9 @@ static int
amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
return i;
}
-static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, uint64_t
shader_addr)
+static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
+ int ps_type,
+ uint64_t shader_addr)
{
int i = 0;
@@ -2625,7 +2678,13 @@ static int
amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, uint64_t shader
ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
ptr[i++] = 0x50;
- i += 4;
+ i += 2;
+ if (ps_type == PS_CONST) {
+ i += 2;
+ } else if (ps_type == PS_TEX) {
+ ptr[i++] = 0x3f80;
+ ptr[i++] = 0x3f80;
+ }
ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
ptr[i++] = 0x54;
@@ -2634,17 +2693,26 @@ static int
amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, uint64_t shader
return i;
}
-static int
[PATCH libdrm 3/4] tests/amdgpu: add memset draw test
add memset draw test for gfx9
Change-Id: I3a1f2460ec0917e29ce1a891200eeaa1a0565fda
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 554 +
2 files changed, 559 insertions(+)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 35324cb..0b870de 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -441,6 +441,11 @@ static void amdgpu_disable_suites()
if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test",
CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+
+ /* This test was ran on GFX9 only */
+ if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+ if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test",
CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
}
/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2f559f4..0ba6199 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -50,6 +50,7 @@ static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
static void amdgpu_dispatch_test(void);
+static void amdgpu_draw_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -72,6 +73,7 @@ CU_TestInfo basic_tests[] = {
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
{ "Dispatch Test", amdgpu_dispatch_test },
+ { "Draw Test", amdgpu_draw_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -318,6 +320,99 @@ static const uint32_t buffercopy_cs_shader_gfx9[] = {
0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF81
};
+static const uint32_t preamblecache_gfx9[] = {
+ 0xc0026900, 0x81, 0x8000, 0x40004000, 0xc0026900, 0x8c, 0xaa99,
0x0,
+ 0xc0026900, 0x90, 0x8000, 0x40004000, 0xc0026900, 0x94, 0x8000,
0x40004000,
+ 0xc0026900, 0xb4, 0x0, 0x3f80, 0xc0016900, 0x103, 0x0,
+ 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+ 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+ 0xc0016900, 0x2d5, 0x1, 0xc0016900, 0x2dc, 0x0,
+ 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5,
0x0, 0x0,
+ 0xc0056900, 0x2f9, 0x5, 0x3f80, 0x3f80, 0x3f80, 0x3f80,
+ 0xc0026900, 0x311, 0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
+ 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+ 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
+ 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0xc0026900, 0x204, 0x9, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+ 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0x, 0x,
+ 0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+ 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900,
0x2243, 0x0,
+ 0xc0017900, 0x248, 0x, 0xc0017900, 0x249, 0x0, 0xc0017900,
0x24a, 0x0,
+ 0xc0017900, 0x24b, 0x0
+};
+
+enum ps_type {
+ PS_CONST
+};
+
+static const uint32_t ps_const_shader_gfx9[] = {
+0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+0xD296, 0x00020300, 0xD2960001, 0x00020702,
+0xC4001C0F, 0x0100, 0xBF81
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
+{{ 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001890, 0x
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001801, 0x
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001803, 0x0100
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC4001803, 0x0300
},
+ { 0xD296, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x0100
},
+ { 0xD295, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x0100
},
+ { 0xD294, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x0100
},
+ { 0xD297, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x0100
},
+ { 0xD298, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x0100
},
+ { 0xBF80, 0xBF80, 0xBF80, 0xBF80, 0xC400180F, 0x03020100 }
+}
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
+0x0004
+};
+
+static const uint32_t ps_num_sh_registers_gfx9 = 2;
+
+static const uint32_t ps_const_sh_registers_gfx9[][2] =
[PATCH libdrm 2/4] tests/amdgpu: add memcpy dispatch test
add memcpy dispatch test for gfx9
Change-Id: Ic9b280db2ced21b15e228c1c4c217836ab3f44a8
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/basic_tests.c | 163 -
1 file changed, 161 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index fe6db09..2f559f4 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -294,6 +294,7 @@ static uint32_t shader_bin[] = {
enum cs_type {
CS_BUFFERCLEAR,
+ CS_BUFFERCOPY
};
static const uint32_t bufferclear_cs_shader_gfx9[] = {
@@ -312,6 +313,11 @@ static const uint32_t
bufferclear_cs_shader_registers_gfx9[][2] = {
static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
+static const uint32_t buffercopy_cs_shader_gfx9[] = {
+0xD1FD, 0x04010C08, 0xE00C2000, 0x8100,
+0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF81
+};
+
int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
uint64_t mapping_flags, amdgpu_bo_handle *bo, void
**cpu,
@@ -1920,6 +1926,10 @@ static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
shader = bufferclear_cs_shader_gfx9;
shader_size = sizeof(bufferclear_cs_shader_gfx9);
break;
+ case CS_BUFFERCOPY:
+ shader = buffercopy_cs_shader_gfx9;
+ shader_size = sizeof(buffercopy_cs_shader_gfx9);
+ break;
default:
return -1;
break;
@@ -2134,6 +2144,151 @@ static void
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
CU_ASSERT_EQUAL(r, 0);
}
+void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
+uint32_t ip_type,
+uint32_t ring)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
+ volatile unsigned char *ptr_dst;
+ void *ptr_shader;
+ unsigned char *ptr_src;
+ uint32_t *ptr_cmd;
+ uint64_t mc_address_src, mc_address_dst, mc_address_shader,
mc_address_cmd;
+ amdgpu_va_handle va_src, va_dst, va_shader, va_cmd;
+ int i, r;
+ int bo_dst_size = 16384;
+ int bo_shader_size = 4096;
+ int bo_cmd_size = 4096;
+ struct amdgpu_cs_request ibs_request = {0};
+ struct amdgpu_cs_ib_info ib_info= {0};
+ uint32_t expired;
+ amdgpu_bo_list_handle bo_list;
+ struct amdgpu_cs_fence fence_status = {0};
+
+ r = amdgpu_cs_ctx_create(device_handle, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _cmd, (void **)_cmd,
+ _address_cmd, _cmd);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _shader, _shader,
+ _address_shader, _shader);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _src, (void **)_src,
+ _address_src, _src);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _dst, (void **)_dst,
+ _address_dst, _dst);
+ CU_ASSERT_EQUAL(r, 0);
+
+ memset(ptr_src, 0x55, bo_dst_size);
+
+ i = 0;
+ i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
+
+ /* Issue commands to set cu mask used in current dispatch */
+ i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
+
+ /* Writes shader state to HW */
+ i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
+
+ /* Write constant data */
+ /* Writes the texture resource constants data to the SGPRs */
+ ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+ ptr_cmd[i++] = 0x240;
+ ptr_cmd[i++] = mc_address_src;
+ ptr_cmd[i++] = (mc_address_src >> 32) | 0x10;
+ ptr_cmd[i++] = 0x400;
+ ptr_cmd[i++] = 0x74fac;
+
+ /* Writes the UAV constant data to the SGPRs. */
+ ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+ ptr_cmd[i++] =
Re: [PATCH v2] tests/amdgpu: add deadlock test for sdma
Hi Alex,
could you help to submit this patch upstream?
在 3/6/2019 4:08 PM, Christian König 写道:
> Am 06.03.19 um 07:37 schrieb Cui, Flora:
>> deadlock test for sdma will cause gpu recoverty.
>> disable the test for now until GPU reset recovery could survive at least
>> 1000 times test.
>>
>> v2: add modprobe parameter
>>
>> Change-Id: I9adac63c62db22107345eddb30e7d81a1bda838c
>> Signed-off-by: Flora Cui
>
> Acked-by: Christian König
>
>> ---
>> tests/amdgpu/amdgpu_test.c | 4 ++
>> tests/amdgpu/deadlock_tests.c | 103
>> +-
>> 2 files changed, 106 insertions(+), 1 deletion(-)
>>
>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>> index ebf4409..38b8a68 100644
>> --- a/tests/amdgpu/amdgpu_test.c
>> +++ b/tests/amdgpu/amdgpu_test.c
>> @@ -426,6 +426,10 @@ static void amdgpu_disable_suites()
>> "compute ring block test (set
>> amdgpu.lockup_timeout=50)", CU_FALSE))
>> fprintf(stderr, "test deactivation failed - %s\n",
>> CU_get_error_msg());
>> + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
>> + "sdma ring block test (set
>> amdgpu.lockup_timeout=50)", CU_FALSE))
>> + fprintf(stderr, "test deactivation failed - %s\n",
>> CU_get_error_msg());
>> +
>> if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
>> fprintf(stderr, "test deactivation failed - %s\n",
>> CU_get_error_msg());
>> diff --git a/tests/amdgpu/deadlock_tests.c
>> b/tests/amdgpu/deadlock_tests.c
>> index a6c2635..91368c1 100644
>> --- a/tests/amdgpu/deadlock_tests.c
>> +++ b/tests/amdgpu/deadlock_tests.c
>> @@ -96,6 +96,9 @@
>> #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
>> +#define SDMA_PKT_HEADER_OP(x) (x & 0xff)
>> +#define SDMA_OP_POLL_REGMEM 8
>> +
>> static amdgpu_device_handle device_handle;
>> static uint32_t major_version;
>> static uint32_t minor_version;
>> @@ -110,6 +113,7 @@ static void amdgpu_deadlock_gfx(void);
>> static void amdgpu_deadlock_compute(void);
>> static void amdgpu_illegal_reg_access();
>> static void amdgpu_illegal_mem_access();
>> +static void amdgpu_deadlock_sdma(void);
>> CU_BOOL suite_deadlock_tests_enable(void)
>> {
>> @@ -171,6 +175,7 @@ int suite_deadlock_tests_clean(void)
>> CU_TestInfo deadlock_tests[] = {
>> { "gfx ring block test (set amdgpu.lockup_timeout=50)",
>> amdgpu_deadlock_gfx },
>> { "compute ring block test (set amdgpu.lockup_timeout=50)",
>> amdgpu_deadlock_compute },
>> + { "sdma ring block test (set amdgpu.lockup_timeout=50)",
>> amdgpu_deadlock_sdma },
>> { "illegal reg access test", amdgpu_illegal_reg_access },
>> { "illegal mem access test (set amdgpu.vm_fault_stop=2)",
>> amdgpu_illegal_mem_access },
>> CU_TEST_INFO_NULL,
>> @@ -260,7 +265,6 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
>> ibs_request.ibs = _info;
>> ibs_request.resources = bo_list;
>> ibs_request.fence_info.handle = NULL;
>> -
>> for (i = 0; i < 200; i++) {
>> r = amdgpu_cs_submit(context_handle, 0,_request, 1);
>> CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
>> @@ -291,6 +295,103 @@ static void amdgpu_deadlock_helper(unsigned
>> ip_type)
>> CU_ASSERT_EQUAL(r, 0);
>> }
>> +static void amdgpu_deadlock_sdma(void)
>> +{
>> + amdgpu_context_handle context_handle;
>> + amdgpu_bo_handle ib_result_handle;
>> + void *ib_result_cpu;
>> + uint64_t ib_result_mc_address;
>> + struct amdgpu_cs_request ibs_request;
>> + struct amdgpu_cs_ib_info ib_info;
>> + struct amdgpu_cs_fence fence_status;
>> + uint32_t expired;
>> + int i, r;
>> + amdgpu_bo_list_handle bo_list;
>> + amdgpu_va_handle va_handle;
>> + struct drm_amdgpu_info_hw_ip info;
>> + uint32_t ring_id;
>> +
>> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0,
>> );
>> + CU_ASSERT_EQUAL(r, 0);
>> +
>> + r = amdgpu_cs_ctx_create(device_handle, _handle);
>> + CU_ASSERT_EQUAL(r, 0);
>> +
>> + for (ring_id = 0; (1 << ring_id) & info.available_rings;
>> ring_id++) {
>> + r = pthread_create(_thread, NULL, write_mem_address,
>> NULL);
>> +
[PATCH v2] tests/amdgpu: add deadlock test for sdma
deadlock test for sdma will cause gpu recoverty.
disable the test for now until GPU reset recovery could survive at least
1000 times test.
v2: add modprobe parameter
Change-Id: I9adac63c62db22107345eddb30e7d81a1bda838c
Signed-off-by: Flora Cui
---
tests/amdgpu/amdgpu_test.c| 4 ++
tests/amdgpu/deadlock_tests.c | 103 +-
2 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf4409..38b8a68 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -426,6 +426,10 @@ static void amdgpu_disable_suites()
"compute ring block test (set
amdgpu.lockup_timeout=50)", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
+ "sdma ring block test (set
amdgpu.lockup_timeout=50)", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index a6c2635..91368c1 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -96,6 +96,9 @@
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
0x54f
+#define SDMA_PKT_HEADER_OP(x) (x & 0xff)
+#define SDMA_OP_POLL_REGMEM 8
+
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
@@ -110,6 +113,7 @@ static void amdgpu_deadlock_gfx(void);
static void amdgpu_deadlock_compute(void);
static void amdgpu_illegal_reg_access();
static void amdgpu_illegal_mem_access();
+static void amdgpu_deadlock_sdma(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
@@ -171,6 +175,7 @@ int suite_deadlock_tests_clean(void)
CU_TestInfo deadlock_tests[] = {
{ "gfx ring block test (set amdgpu.lockup_timeout=50)",
amdgpu_deadlock_gfx },
{ "compute ring block test (set amdgpu.lockup_timeout=50)",
amdgpu_deadlock_compute },
+ { "sdma ring block test (set amdgpu.lockup_timeout=50)",
amdgpu_deadlock_sdma },
{ "illegal reg access test", amdgpu_illegal_reg_access },
{ "illegal mem access test (set amdgpu.vm_fault_stop=2)",
amdgpu_illegal_mem_access },
CU_TEST_INFO_NULL,
@@ -260,7 +265,6 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
ibs_request.ibs = _info;
ibs_request.resources = bo_list;
ibs_request.fence_info.handle = NULL;
-
for (i = 0; i < 200; i++) {
r = amdgpu_cs_submit(context_handle, 0,_request, 1);
CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
@@ -291,6 +295,103 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
CU_ASSERT_EQUAL(r, 0);
}
+static void amdgpu_deadlock_sdma(void)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_ib_info ib_info;
+ struct amdgpu_cs_fence fence_status;
+ uint32_t expired;
+ int i, r;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ struct drm_amdgpu_info_hw_ip info;
+ uint32_t ring_id;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, );
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_create(device_handle, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+ r = pthread_create(_thread, NULL, write_mem_address,
NULL);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ?
AMDGPU_VM_MTYPE_UC : 0,
+ _result_handle,
_result_cpu,
+
_result_mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+ _list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = ib_result_cpu;
+ i = 0;
+
+ ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ (0 << 26) | /* WAIT_REG_MEM */
+ (4 << 28) | /* != */
+ (1 << 31); /* memory */
+ ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffc;
+ ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0x;
+ ptr[i++] = 0x; /*
[PATCH libdrm] tests/amdgpu: add deadlock test for sdma
deadlock test for sdma will cause gpu recoverty.
disable the test for now until GPU reset recovery could survive at least
1000 times test.
Change-Id: I9adac63c62db22107345eddb30e7d81a1bda838c
Signed-off-by: Flora Cui
---
tests/amdgpu/amdgpu_test.c| 4 ++
tests/amdgpu/deadlock_tests.c | 103 +-
2 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf4409..5119455 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -426,6 +426,10 @@ static void amdgpu_disable_suites()
"compute ring block test (set
amdgpu.lockup_timeout=50)", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
+ "sdma ring block test", CU_FALSE))
+ fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
+
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index a6c2635..be917b1 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -96,6 +96,9 @@
#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
0x54f
+#define SDMA_PKT_HEADER_OP(x) (x & 0xff)
+#define SDMA_OP_POLL_REGMEM 8
+
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
@@ -110,6 +113,7 @@ static void amdgpu_deadlock_gfx(void);
static void amdgpu_deadlock_compute(void);
static void amdgpu_illegal_reg_access();
static void amdgpu_illegal_mem_access();
+static void amdgpu_deadlock_sdma(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
@@ -171,6 +175,7 @@ int suite_deadlock_tests_clean(void)
CU_TestInfo deadlock_tests[] = {
{ "gfx ring block test (set amdgpu.lockup_timeout=50)",
amdgpu_deadlock_gfx },
{ "compute ring block test (set amdgpu.lockup_timeout=50)",
amdgpu_deadlock_compute },
+ { "sdma ring block test", amdgpu_deadlock_sdma },
{ "illegal reg access test", amdgpu_illegal_reg_access },
{ "illegal mem access test (set amdgpu.vm_fault_stop=2)",
amdgpu_illegal_mem_access },
CU_TEST_INFO_NULL,
@@ -260,7 +265,6 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
ibs_request.ibs = _info;
ibs_request.resources = bo_list;
ibs_request.fence_info.handle = NULL;
-
for (i = 0; i < 200; i++) {
r = amdgpu_cs_submit(context_handle, 0,_request, 1);
CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
@@ -291,6 +295,103 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
CU_ASSERT_EQUAL(r, 0);
}
+static void amdgpu_deadlock_sdma(void)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_ib_info ib_info;
+ struct amdgpu_cs_fence fence_status;
+ uint32_t expired;
+ int i, r;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ struct drm_amdgpu_info_hw_ip info;
+ uint32_t ring_id;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, );
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_create(device_handle, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+ r = pthread_create(_thread, NULL, write_mem_address,
NULL);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ?
AMDGPU_VM_MTYPE_UC : 0,
+ _result_handle,
_result_cpu,
+
_result_mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+ _list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = ib_result_cpu;
+ i = 0;
+
+ ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ (0 << 26) | /* WAIT_REG_MEM */
+ (4 << 28) | /* != */
+ (1 << 31); /* memory */
+ ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffc;
+ ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0x;
+ ptr[i++] = 0x; /* reference value */
+ ptr[i++] = 0x; /* and mask */
+
[PATCH libdrm 1/2] tests/amdgpu: add memset dispatch test
add memset dispatch test for gfx9
Change-Id: If607fbd9c6e49ca830a662adc24fe6b1e2a25bfb
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/basic_tests.c | 215 -
1 file changed, 213 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index dbae4d5..d4b0faf 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
+static void amdgpu_dispatch_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -70,6 +71,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
+ { "Dispatch Test", amdgpu_dispatch_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -117,6 +119,7 @@ CU_TestInfo basic_tests[] = {
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
+#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
/* Packet 3 types */
#definePACKET3_NOP 0x10
@@ -245,8 +248,8 @@ CU_TestInfo basic_tests[] = {
#definePACKET3_SET_SH_REG_START
0x2c00
#definePACKET3_DISPATCH_DIRECT 0x15
-
-
+#define PACKET3_EVENT_WRITE0x46
+#define PACKET3_ACQUIRE_MEM0x58
/* gfx 8 */
#define mmCOMPUTE_PGM_LO
0x2e0c
#define mmCOMPUTE_PGM_RSRC1
0x2e12
@@ -286,6 +289,21 @@ static uint32_t shader_bin[] = {
#define CODE_OFFSET 512
#define DATA_OFFSET 1024
+static const uint32_t bufferclear_cs_shader_gfx9[] = {
+0xD1FD, 0x04010C08, 0x7E020204, 0x7E040205,
+0x7E060206, 0x7E080207, 0xE01C2000, 0x8100,
+0xBF81
+};
+
+static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
+ {0x2E12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
+ {0x2E13, 0x0090}, //{ mmCOMPUTE_PGM_RSRC2, 0x0090 },
+ {0x2E07, 0x0040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x0040 },
+ {0x2E08, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x0001 },
+ {0x2E09, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x0001 }
+};
+
+static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
@@ -1883,3 +1901,196 @@ static void amdgpu_sync_dependency_test(void)
free(ibs_request.dependencies);
}
+
+static int amdgpu_dispatch_init(uint32_t ip_type,
+ uint32_t version,
+ uint32_t *ptr)
+{
+ int i = 0;
+
+ /* Write context control and load shadowing register if necessary */
+ if (ip_type == AMDGPU_HW_IP_GFX) {
+ ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
+ ptr[i++] = 0x8000;
+ ptr[i++] = 0x8000;
+ }
+
+ /* Issue commands to set default compute state. */
+ /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
+ ptr[i++] = 0x204;
+ i += 3;
+ /* clear mmCOMPUTE_RESOURCE_LIMITS */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x215;
+ ptr[i++] = 0;
+ /* clear mmCOMPUTE_TMPRING_SIZE */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x218;
+ ptr[i++] = 0;
+
+ return i;
+}
+
+static int amdgpu_dispatch_write_cumask(uint32_t ip_type,
+ uint32_t version,
+ uint32_t *ptr)
+{
+ int i = 0;
+
+ /* Issue commands to set cu mask used in current dispatch */
+ /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 -
mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
+ ptr[i++] = 0x216;
+ ptr[i++] = 0x;
+ ptr[i++] = 0x;
+ /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 -
mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
+ ptr[i++] = 0x219;
+ ptr[i++] = 0x;
+ ptr[i++] = 0x;
+
+ return i;
+}
+
+static int amdgpu_dispatch_write2hw(uint32_t
[PATCH libdrm 2/2] tests/amdgpu: add memcpy dispatch test
add memcpy dispatch test for gfx9
Change-Id: If433434c5378f3b318209d4e28c19d7ce9cff1a2
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/basic_tests.c | 129 +
1 file changed, 129 insertions(+)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index d4b0faf..9d2cc95 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -305,6 +305,11 @@ static const uint32_t
bufferclear_cs_shader_registers_gfx9[][2] = {
static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
+static const uint32_t buffercopy_cs_shader_gfx9[] = {
+0xD1FD, 0x04010C08, 0xE00C2000, 0x8100,
+0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF81
+};
+
int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
uint64_t mapping_flags, amdgpu_bo_handle *bo, void
**cpu,
@@ -2084,6 +2089,128 @@ static void amdgpu_memset_dispatch_test(uint32_t
ip_type)
r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader,
bo_shader_size);
CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_memcpy_dispatch_test(uint32_t ip_type)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle bo_src, bo_dst, bo_shader, resources[3];
+ volatile unsigned char *ptr_dst;
+ void *ptr_shader;
+ void *ptr_src;
+ uint64_t mc_address_src, mc_address_dst, mc_address_shader;
+ amdgpu_va_handle va_src, va_dst, va_shader;
+ int i, j, r;
+ uint32_t *ptr;
+ int bo_dst_size = 16384;
+ int bo_shader_size = 4096;
+ struct amdgpu_cs_request ibs_request = {0};
+ struct amdgpu_cs_ib_info ib_info= {0};
+ uint32_t version, ring_id;
+ struct drm_amdgpu_info_hw_ip info;
+
+ r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, );
+ CU_ASSERT_EQUAL(r, 0);
+
+ version = info.hw_ip_version_major;
+ if (version != 9) {
+ printf("\tSkip...memcpy dispatch test is only supported with
gfx9\n");
+ return;
+ }
+
+ ptr = calloc(256, sizeof(*ptr));
+ CU_ASSERT_NOT_EQUAL(ptr, NULL);
+
+ r = amdgpu_cs_ctx_create(device_handle, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _shader, _shader,
+ _address_shader, _shader);
+ CU_ASSERT_EQUAL(r, 0);
+
+ memcpy(ptr_shader, buffercopy_cs_shader_gfx9,
sizeof(buffercopy_cs_shader_gfx9));
+
+ for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _src, _src,
+ _address_src, _src);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _dst, _dst,
+ _address_dst, _dst);
+ CU_ASSERT_EQUAL(r, 0);
+
+ memset(ptr_src, 0x55, bo_dst_size);
+
+ i = 0;
+ i += amdgpu_dispatch_init(ip_type, version, ptr + i);
+
+ /* Issue commands to set cu mask used in current dispatch */
+ i += amdgpu_dispatch_write_cumask(ip_type, version, ptr + i);
+
+ /* Writes shader state to HW */
+ i += amdgpu_dispatch_write2hw(ip_type, version, ptr + i,
mc_address_shader);
+
+ /* Write constant data */
+ /* Writes the texture resource constants data to the SGPRs */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+ ptr[i++] = 0x240;
+ ptr[i++] = mc_address_src;
+ ptr[i++] = (mc_address_src > 32) | 0x10;
+ ptr[i++] = 0x400;
+ ptr[i++] = 0x74fac;
+ /* Writes the UAV constant data to the SGPRs. */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+ ptr[i++] = 0x244;
+ ptr[i++] = mc_address_dst;
+ ptr[i++] = (mc_address_dst > 32) | 0x10;
+ ptr[i++] = 0x400;
+ ptr[i++] = 0x74fac;
+
+ /* dispatch direct command */
+ ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
+ ptr[i++] = 0x10;
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+ ptr[i++] = 1;
+
+ while (i & 7)
RE: [PATCH libdrm] tests/amdgpu: add dispatch test
OK. I'll prepare the patch base on master once the tests are finished.
-Original Message-
From: Alex Deucher
Sent: Saturday, February 23, 2019 4:55 AM
To: Zhang, Hawking
Cc: Cui, Flora ; amd-...@lists.freedesktop.org;
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH libdrm] tests/amdgpu: add dispatch test
On Mon, Feb 18, 2019 at 9:26 PM Zhang, Hawking wrote:
>
> Although the shader is simple enough, please work with CQE to test it on all
> gfx9 ASICs before push it.
>
> The patch is Reviewed-by: Hawking Zhang
Please make sure this patch gets upstream as well. It doesn't seem to apply
cleanly as is.
Alex
>
> Regards,
> Hawking
> -Original Message-
> From: amd-gfx On Behalf Of
> Cui, Flora
> Sent: 2019年2月18日 12:56
> To: amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Cui, Flora
> Subject: [PATCH libdrm] tests/amdgpu: add dispatch test
>
> From: Flora Cui
>
> Change-Id: I6f5dfa4379cb21c41c68757fae0105527a03e54f
> Signed-off-by: Flora Cui
> ---
> tests/amdgpu/basic_tests.c | 175
> -
> 1 file changed, 173 insertions(+), 2 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index d79859a..649c5a4 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void); static void
> amdgpu_semaphore_test(void); static void
> amdgpu_sync_dependency_test(void);
> static void amdgpu_bo_eviction_test(void);
> +static void amdgpu_memset_dispatch_test(void);
> static void amdgpu_direct_gma_test(void);
>
> static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
> @@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = {
> { "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
> { "SW semaphore Test", amdgpu_semaphore_test },
> { "Sync dependency Test", amdgpu_sync_dependency_test },
> + { "Memset dispatch Test", amdgpu_memset_dispatch_test },
> { "Direct GMA", amdgpu_direct_gma_test },
> CU_TEST_INFO_NULL,
> };
> @@ -119,6 +121,7 @@ CU_TestInfo basic_tests[] = {
> #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
> (((op) & 0xFF) << 8) | \
> ((n) & 0x3FFF) << 16)
> +#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
>
> /* Packet 3 types */
> #definePACKET3_NOP 0x10
> @@ -247,8 +250,8 @@ CU_TestInfo basic_tests[] = {
> #definePACKET3_SET_SH_REG_START
> 0x2c00
>
> #definePACKET3_DISPATCH_DIRECT 0x15
> -
> -
> +#define PACKET3_EVENT_WRITE0x46
> +#define PACKET3_ACQUIRE_MEM0x58
> /* gfx 8 */
> #define mmCOMPUTE_PGM_LO
>0x2e0c
> #define mmCOMPUTE_PGM_RSRC1
>0x2e12
> @@ -1945,6 +1948,174 @@ static void amdgpu_sync_dependency_test(void)
> free(ibs_request.dependencies); }
>
> +static const uint32_t bufferclear_cs_shader_gfx9[] = {
> +0xD1FD, 0x04010C08, 0x7E020204, 0x7E040205,
> +0x7E060206, 0x7E080207, 0xE01C2000, 0x8100,
> +0xBF81
> +};
> +static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
> + {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041
> },
> + {0x2e13, 0x0090}, //{ mmCOMPUTE_PGM_RSRC2, 0x0090
> },
> + {0x2e07, 0x0040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x0040 },
> + {0x2e08, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x0001 },
> + {0x2e09, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x0001 }
> +};
> +static void amdgpu_memset_dispatch_gfx_test_gfx9()
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle bo_dst, bo_shader, resources[2];
> + volatile unsigned char *ptr_dst;
> + void *ptr_shader;
> + uint64_t mc_address_dst, mc_address_shader;
> + amdgpu_va_handle va_dst, va_shader;
> + int i, j, r;
> + uint32_t *ptr;
> + int bo_dst_size = 16384;
> + struct amdgpu_cs_request ibs_request;
> + struct amdgpu_cs_ib_info ib_info;
> +
> + ptr = calloc(256, sizeof(*ptr));
> + CU_ASSERT_NOT_EQUAL(ptr, NULL);
> + memset(ptr, 0, 256);
> +
> + r = amdgpu_cs_ctx_create(device_handle, _handle);
> + CU_
[PATCH libdrm] tests/amdgpu: add dispatch test
From: Flora Cui
Change-Id: I6f5dfa4379cb21c41c68757fae0105527a03e54f
Signed-off-by: Flora Cui
---
tests/amdgpu/basic_tests.c | 175 -
1 file changed, 173 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index d79859a..649c5a4 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void);
static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
+static void amdgpu_memset_dispatch_test(void);
static void amdgpu_direct_gma_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
@@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = {
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
+ { "Memset dispatch Test", amdgpu_memset_dispatch_test },
{ "Direct GMA", amdgpu_direct_gma_test },
CU_TEST_INFO_NULL,
};
@@ -119,6 +121,7 @@ CU_TestInfo basic_tests[] = {
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
+#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
/* Packet 3 types */
#definePACKET3_NOP 0x10
@@ -247,8 +250,8 @@ CU_TestInfo basic_tests[] = {
#definePACKET3_SET_SH_REG_START
0x2c00
#definePACKET3_DISPATCH_DIRECT 0x15
-
-
+#define PACKET3_EVENT_WRITE0x46
+#define PACKET3_ACQUIRE_MEM0x58
/* gfx 8 */
#define mmCOMPUTE_PGM_LO
0x2e0c
#define mmCOMPUTE_PGM_RSRC1
0x2e12
@@ -1945,6 +1948,174 @@ static void amdgpu_sync_dependency_test(void)
free(ibs_request.dependencies);
}
+static const uint32_t bufferclear_cs_shader_gfx9[] =
+{
+0xD1FD, 0x04010C08, 0x7E020204, 0x7E040205,
+0x7E060206, 0x7E080207, 0xE01C2000, 0x8100,
+0xBF81
+};
+static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
+ {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
+ {0x2e13, 0x0090}, //{ mmCOMPUTE_PGM_RSRC2, 0x0090 },
+ {0x2e07, 0x0040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x0040 },
+ {0x2e08, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x0001 },
+ {0x2e09, 0x0001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x0001 }
+};
+static void amdgpu_memset_dispatch_gfx_test_gfx9()
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle bo_dst, bo_shader, resources[2];
+ volatile unsigned char *ptr_dst;
+ void *ptr_shader;
+ uint64_t mc_address_dst, mc_address_shader;
+ amdgpu_va_handle va_dst, va_shader;
+ int i, j, r;
+ uint32_t *ptr;
+ int bo_dst_size = 16384;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_ib_info ib_info;
+
+ ptr = calloc(256, sizeof(*ptr));
+ CU_ASSERT_NOT_EQUAL(ptr, NULL);
+ memset(ptr, 0, 256);
+
+ r = amdgpu_cs_ctx_create(device_handle, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _shader, _shader,
+ _address_shader, _shader);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+ AMDGPU_GEM_DOMAIN_VRAM, 0,
+ _dst, _dst,
+ _address_dst, _dst);
+ CU_ASSERT_EQUAL(r, 0);
+
+ memcpy(ptr_shader, bufferclear_cs_shader_gfx9,
sizeof(bufferclear_cs_shader_gfx9));
+
+ i = 0;
+ ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
+ ptr[i++] = 0x8000;
+ ptr[i++] = 0x8000;
+
+ /* Issue commands to set default compute state. */
+ /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
+ ptr[i++] = 0x204;
+ ptr[i++] = 0;
+ ptr[i++] = 0;
+ ptr[i++] = 0;
+ /* clear mmCOMPUTE_RESOURCE_LIMITS */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x215;
+ ptr[i++] = 0;
+ /* clear mmCOMPUTE_TMPRING_SIZE */
+ ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+ ptr[i++] = 0x218;
+ ptr[i++] = 0;
+
+ /* Issue commands to set cu mask used in current dispatch */
+ /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1
