[PATCH] drm/panel: ili9341: fix optional regulator handling

[Daniel Mack]

If the optional regulator lookup fails, reset the pointer to NULL.
Other functions such as mipi_dbi_poweron_reset_conditional() only do
a NULL pointer check and will otherwise dereference the error pointer.

Fixes: 5a04227326b04c15 ("drm/panel: Add ilitek ili9341 panel driver")
Signed-off-by: Daniel Mack 
---
 drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c 
b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
index 2c3378a259b1..e1542451ef9d 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
@@ -612,8 +612,10 @@ static int ili9341_dbi_probe(struct spi_device *spi, 
struct gpio_desc *dc,
int ret;
 
vcc = devm_regulator_get_optional(dev, "vcc");
-   if (IS_ERR(vcc))
+   if (IS_ERR(vcc)) {
dev_err(dev, "get optional vcc failed\n");
+   vcc = NULL;
+   }
 
dbidev = devm_drm_dev_alloc(dev, _dbi_driver,
struct mipi_dbi_dev, drm);
-- 
2.35.1

[PATCH RESEND v10 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
Reviewed-by: Rob Herring 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index ..7e7a8362b951
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.31.1

Re: [PATCH v8 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

On 10/15/21 16:59, Daniel Mack wrote:
> This is v3 of the series.

Ups, sorry. Ignore this one. I meant to resend a different version of
this series.


My apologies,
Daniel



> 
> Changelog:
> 
> v2 -> v3:
>   * Turn Documentation into yaml format
> 
> v3 -> v4:
>   * Fix reference error in yaml file
> 
> v4 -> v5:
>   * More yaml file documentation fixes
> 
> v5 -> v6:
>   * More yaml file documentation fixes
> 
> v6 -> v7:
>   * Fix ordering of patches
> 
> v7 -> v8:
>   * More yaml file documentation fixes
> 
> Daniel Mack (2):
>   dt-bindings: display: add bindings for newhaven,1.8-128160EF
>   drm/tiny: add driver for newhaven,1.8-128160EF
> 
>  .../display/panel/ilitek,ili9163.yaml | 69 +++
>  drivers/gpu/drm/tiny/Kconfig  |  13 +
>  drivers/gpu/drm/tiny/Makefile |   1 +
>  drivers/gpu/drm/tiny/ili9163.c| 224 ++
>  4 files changed, 307 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
>  create mode 100644 drivers/gpu/drm/tiny/ili9163.c
> 

[PATCH v8 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v8 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

v7 -> v8:
* More yaml file documentation fixes

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml | 69 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

[PATCH v8 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..7e7a8362b9513
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

[PATCH RESEND v10 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v10 of the series.

Resending without changes.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

v7 -> v8:
* More yaml file documentation fixes

v8 -> v9:
* Addressed some minor issues pointed out by Thomas Zimmermann
* Rebased

v9 -> v10:
* Re-apply the yaml file in favour of the txt file

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml |  69 ++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.31.1

[PATCH RESEND v10 2/2] drm/tiny: add driver for newhaven, 1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
Acked-by: Thomas Zimmermann 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index d46f95d9196d..ca2d9255548b 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -67,6 +67,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select BACKLIGHT_CLASS_DEVICE
+   select DRM_KMS_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DBI
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 9cc847e756da..c96c663c3499 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_CIRRUS_QEMU)   += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_DRM_SIMPLEDRM)+= simpledrm.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index ..b0953e1aa3ed
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   DRM_DEBUG_KMS("\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MV;
+   break;
+   case 180:
+   addr_mode = 0;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MY | ILI9163_MADCTL_MV;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_fu

[PATCH v10 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
Acked-by: Thomas Zimmermann 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index d46f95d9196d..ca2d9255548b 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -67,6 +67,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select BACKLIGHT_CLASS_DEVICE
+   select DRM_KMS_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DBI
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 9cc847e756da..c96c663c3499 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_CIRRUS_QEMU)   += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_DRM_SIMPLEDRM)+= simpledrm.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index ..b0953e1aa3ed
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   DRM_DEBUG_KMS("\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MV;
+   break;
+   case 180:
+   addr_mode = 0;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MY | ILI9163_MADCTL_MV;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_fu

[PATCH v10 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
Reviewed-by: Rob Herring 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index ..7e7a8362b951
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.31.1

[PATCH v10 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v10 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

v7 -> v8:
* More yaml file documentation fixes

v8 -> v9:
* Addressed some minor issues pointed out by Thomas Zimmermann
* Rebased

v9 -> v10:
* Re-apply the yaml file in favour of the txt file

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml |  69 ++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.31.1

Re: [PATCH v9 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

Hi Sam,

On 9/1/21 4:20 PM, Sam Ravnborg wrote:
> Hi Daniel,
> 
> On Wed, Sep 01, 2021 at 12:30:38PM +0200, Daniel Mack wrote:
>> This is v9 of the series.
>>
>> Changelog:
>>
>> v2 -> v3:
>>  * Turn Documentation into yaml format
> 
> ...
> 
>> Daniel Mack (2):
>>   dt-bindings: display: add bindings for newhaven,1.8-128160EF
>>   drm/tiny: add driver for newhaven,1.8-128160EF
>>
>>  .../bindings/display/ilitek,ili9163.txt   |  27 +++
> 
> Despite the changelog the patch contains a .txt file.
> Did you push the right patchset?

Meh, you're right. Something went wrong in the rebase.
Thanks for spotting this! Will send a v10 in a minute!


Daniel

[PATCH v9 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v9 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

v7 -> v8:
* More yaml file documentation fixes

v8 -> v9:
* Addressed some minor issues pointed out by Thomas Zimmermann
    * Rebased

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../bindings/display/ilitek,ili9163.txt   |  27 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 265 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9163.txt
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.31.1

[PATCH v9 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
Reviewed-by: Rob Herring 
---
 .../bindings/display/ilitek,ili9163.txt   | 27 +++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9163.txt

diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9163.txt 
b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
new file mode 100644
index ..fee119991c14
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
@@ -0,0 +1,27 @@
+Ilitek ILI9163 display panels
+
+This binding is for display panels using an Ilitek ILI9163 controller in SPI
+mode.
+
+Required properties:
+- compatible:  "newhaven,1.8-128160EF", "ilitek,ili9163"
+- dc-gpios:D/C pin
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation:panel rotation in degrees counter clockwise (0,90,180,270)
+- backlight:   phandle of the backlight device attached to the panel
+
+Example:
+   display@0{
+   compatible = "newhaven,1.8-128160EF", "ilitek,ili9163"
+   reg = <0>;
+   spi-max-frequency = <3200>;
+   dc-gpios = < 9 GPIO_ACTIVE_HIGH>;
+   reset-gpios = < 8 GPIO_ACTIVE_HIGH>;
+   rotation = <270>;
+   backlight = <>;
+   };
-- 
2.31.1

[PATCH v9 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
Acked-by: Thomas Zimmermann 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index d46f95d9196d..ca2d9255548b 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -67,6 +67,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select BACKLIGHT_CLASS_DEVICE
+   select DRM_KMS_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DBI
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 9cc847e756da..c96c663c3499 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_CIRRUS_QEMU)   += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_DRM_SIMPLEDRM)+= simpledrm.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index ..b0953e1aa3ed
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   DRM_DEBUG_KMS("\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MV;
+   break;
+   case 180:
+   addr_mode = 0;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MY | ILI9163_MADCTL_MV;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_fu

[PATCH v8 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..7e7a8362b9513
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v8 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v8 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

v7 -> v8:
* More yaml file documentation fixes

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml | 69 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v7 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v7 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

v6 -> v7:
* Fix ordering of patches

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml | 69 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v7 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..fe612851e399a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

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[PATCH v5 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v6 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

v5 -> v6:
* More yaml file documentation fixes

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml | 69 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v6 2/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..fe612851e399a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

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[PATCH v6 1/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v5 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..fbb12e46493b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

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[PATCH v5 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

v4 -> v5:
* More yaml file documentation fixes

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../display/panel/ilitek,ili9163.yaml | 69 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 307 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v5 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v5 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../display/panel/ilitek,ili9163.yaml | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
new file mode 100644
index 0..fbb12e46493b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9163.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0 {
+compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.30.2

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[PATCH v4 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v4 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../bindings/display/ilitek,ili9163.yaml  | 70 +++
 1 file changed, 70 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml

diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
new file mode 100644
index 0..b98c6b871b790
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ilitek,ili9163.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - ilitek,ili9163
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0{
+compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.29.2

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[PATCH v4 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

v3 -> v4:
* Fix reference error in yaml file

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../bindings/display/ilitek,ili9163.yaml  |  70 ++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 308 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v3 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_simple_display_pipe_funcs ili9163_pipe_funcs = {
+   .enable = yx240qv29_e

[PATCH v3 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../bindings/display/ilitek,ili9163.yaml  | 70 +++
 1 file changed, 70 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml

diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml 
b/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
new file mode 100644
index 0..edf1f925bc0cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ilitek,ili9486.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9163 display panels device tree bindings
+
+maintainers:
+  - Daniel Mack 
+
+description:
+  This binding is for display panels using an Ilitek ILI9163 controller in SPI
+  mode.
+
+allOf:
+  - $ref: panel/panel-common.yaml#
+
+properties:
+  compatible:
+items:
+  - enum:
+  - newhaven,1.8-128160EF
+  - ilitek,ili9163
+  - const: ilitek,ili9163
+
+  spi-max-frequency:
+maximum: 3200
+
+  dc-gpios:
+maxItems: 1
+description: Display data/command selection (D/CX)
+
+  backlight: true
+  reg: true
+  reset-gpios: true
+  rotation: true
+
+required:
+  - compatible
+  - reg
+  - dc-gpios
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+backlight: backlight {
+compatible = "gpio-backlight";
+gpios = < 22 GPIO_ACTIVE_HIGH>;
+};
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+display@0{
+compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486";
+reg = <0>;
+spi-max-frequency = <3200>;
+dc-gpios = < 24 GPIO_ACTIVE_HIGH>;
+reset-gpios = < 25 GPIO_ACTIVE_HIGH>;
+rotation = <180>;
+backlight = <>;
+};
+};
+
+...
-- 
2.29.2

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[PATCH v3 0/2] gpu: drm: add driver for ili9361 panel

[Daniel Mack]

This is v3 of the series.

Changelog:

v2 -> v3:
* Turn Documentation into yaml format

Daniel Mack (2):
  dt-bindings: display: add bindings for newhaven,1.8-128160EF
  drm/tiny: add driver for newhaven,1.8-128160EF

 .../bindings/display/ilitek,ili9163.yaml  |  70 ++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 308 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/ilitek,ili9163.yaml
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

-- 
2.29.2

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[PATCH v2 2/2] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
Acked-by: Daniel Vetter 
---
v2:

* Address comments from Thomas Zimmermann
* Split patch in DT and implementation part

 drivers/gpu/drm/tiny/Kconfig   |  13 ++
 drivers/gpu/drm/tiny/Makefile  |   1 +
 drivers/gpu/drm/tiny/ili9163.c | 224 +
 3 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..6fa9e59b69321
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   drm_dbg_kms(>drm, "\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /* Frame Rate */
+   mipi_dbi_command(dbi, ILI9163_FRMCTR1, 0x0a, 0x14);
+
+   /* Power Control */
+   mipi_dbi_command(dbi, ILI9163_PWCTRL1, 0x0a, 0x00);
+   mipi_dbi_command(dbi, ILI9163_PWCTRL2, 0x02);
+
+   /* VCOM */
+   mipi_dbi_command(dbi, ILI9163_VMCTRL1, 0x2f, 0x3e);
+   mipi_dbi_command(dbi, ILI9163_VMCTRL2, 0x40);
+
+   /* Memory Access Control */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 
MIPI_DCS_PIXEL_FMT_16BIT);
+
+   mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+   msleep(100);
+
+   mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+   msleep(100);
+
+out_enable:
+   switch (dbidev->rotation) {
+   default:
+   addr_mode = 0;
+   break;
+   case 90:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MX;
+   break;
+   case 180:
+   addr_mode = ILI9163_MADCTL_MX | ILI9163_MADCTL_MY;
+   break;
+   case 270:
+   addr_mode = ILI9163_MADCTL_MV | ILI9163_MADCTL_MY;
+   break;
+   }
+   addr_mode |= ILI9163_MADCTL_BGR;
+   mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
+   mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
+out_exit:
+   drm_dev_exit(idx);
+}
+
+static const struct drm_

[PATCH v2 1/2] dt-bindings: display: add bindings for newhaven, 1.8-128160EF

[Daniel Mack]

This adds documentation for a new ILI9163 based, SPI connected display.

Signed-off-by: Daniel Mack 
---
 .../bindings/display/ilitek,ili9163.txt   | 27 +++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9163.txt

diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9163.txt 
b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
new file mode 100644
index 0..fee119991c14e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
@@ -0,0 +1,27 @@
+Ilitek ILI9163 display panels
+
+This binding is for display panels using an Ilitek ILI9163 controller in SPI
+mode.
+
+Required properties:
+- compatible:  "newhaven,1.8-128160EF", "ilitek,ili9163"
+- dc-gpios:D/C pin
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation:panel rotation in degrees counter clockwise (0,90,180,270)
+- backlight:   phandle of the backlight device attached to the panel
+
+Example:
+   display@0{
+   compatible = "newhaven,1.8-128160EF", "ilitek,ili9163"
+   reg = <0>;
+   spi-max-frequency = <3200>;
+   dc-gpios = < 9 GPIO_ACTIVE_HIGH>;
+   reset-gpios = < 8 GPIO_ACTIVE_HIGH>;
+   rotation = <270>;
+   backlight = <>;
+   };
-- 
2.29.2

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Re: [PATCH] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

Hi,

Thanks for the review!

On 2/12/21 8:13 AM, Thomas Zimmermann wrote:
> thanks for the driver. I only have some minor comments
> 
> Am 11.02.21 um 10:50 schrieb Daniel Mack:
>> +#define ILI9163_MADCTL_BGR    BIT(3)
>> +#define ILI9163_MADCTL_MV    BIT(5)
>> +#define ILI9163_MADCTL_MX    BIT(6)
>> +#define ILI9163_MADCTL_MY    BIT(7)
> 
> The indention is inconsistent. Or maybe it's just my email client.

Yes, the latter :)

Addressed the rest of your remarks. Will send a v2.


Thanks,
Daniel
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[PATCH] drm/tiny: add driver for newhaven,1.8-128160EF

[Daniel Mack]

This patch adds support for Newhaven's NHD-1.8-128160EF display, featuring
an Ilitek ILI9163 controller.

Signed-off-by: Daniel Mack 
---
 .../bindings/display/ilitek,ili9163.txt   |  27 +++
 drivers/gpu/drm/tiny/Kconfig  |  13 +
 drivers/gpu/drm/tiny/Makefile |   1 +
 drivers/gpu/drm/tiny/ili9163.c| 224 ++
 4 files changed, 265 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9163.txt
 create mode 100644 drivers/gpu/drm/tiny/ili9163.c

diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9163.txt 
b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
new file mode 100644
index 0..fee119991c14e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9163.txt
@@ -0,0 +1,27 @@
+Ilitek ILI9163 display panels
+
+This binding is for display panels using an Ilitek ILI9163 controller in SPI
+mode.
+
+Required properties:
+- compatible:  "newhaven,1.8-128160EF", "ilitek,ili9163"
+- dc-gpios:D/C pin
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation:panel rotation in degrees counter clockwise (0,90,180,270)
+- backlight:   phandle of the backlight device attached to the panel
+
+Example:
+   display@0{
+   compatible = "newhaven,1.8-128160EF", "ilitek,ili9163"
+   reg = <0>;
+   spi-max-frequency = <3200>;
+   dc-gpios = < 9 GPIO_ACTIVE_HIGH>;
+   reset-gpios = < 8 GPIO_ACTIVE_HIGH>;
+   rotation = <270>;
+   backlight = <>;
+   };
diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 2b6414f0fa759..9de0c0eeea6f5 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -41,6 +41,19 @@ config TINYDRM_HX8357D
 
  If M is selected the module will be called hx8357d.
 
+config TINYDRM_ILI9163
+   tristate "DRM support for ILI9163 display panels"
+   depends on DRM && SPI
+   select DRM_KMS_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DBI
+   select BACKLIGHT_CLASS_DEVICE
+   help
+ DRM driver for the following Ilitek ILI9163 panels:
+ * NHD-1.8-128160EF 128x160 TFT
+
+ If M is selected the module will be called ili9163.
+
 config TINYDRM_ILI9225
tristate "DRM support for ILI9225 display panels"
depends on DRM && SPI
diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
index 6ae4e9e5a35fb..78016b2ed11b5 100644
--- a/drivers/gpu/drm/tiny/Makefile
+++ b/drivers/gpu/drm/tiny/Makefile
@@ -3,6 +3,7 @@
 obj-$(CONFIG_DRM_CIRRUS_QEMU)  += cirrus.o
 obj-$(CONFIG_DRM_GM12U320) += gm12u320.o
 obj-$(CONFIG_TINYDRM_HX8357D)  += hx8357d.o
+obj-$(CONFIG_TINYDRM_ILI9163)  += ili9163.o
 obj-$(CONFIG_TINYDRM_ILI9225)  += ili9225.o
 obj-$(CONFIG_TINYDRM_ILI9341)  += ili9341.o
 obj-$(CONFIG_TINYDRM_ILI9486)  += ili9486.o
diff --git a/drivers/gpu/drm/tiny/ili9163.c b/drivers/gpu/drm/tiny/ili9163.c
new file mode 100644
index 0..9f90ea9556c4d
--- /dev/null
+++ b/drivers/gpu/drm/tiny/ili9163.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ILI9163_FRMCTR10xb1
+
+#define ILI9163_PWCTRL10xc0
+#define ILI9163_PWCTRL20xc1
+#define ILI9163_VMCTRL10xc5
+#define ILI9163_VMCTRL20xc7
+#define ILI9163_PWCTRLA0xcb
+#define ILI9163_PWCTRLB0xcf
+
+#define ILI9163_EN3GAM 0xf2
+
+#define ILI9163_MADCTL_BGR BIT(3)
+#define ILI9163_MADCTL_MV  BIT(5)
+#define ILI9163_MADCTL_MX  BIT(6)
+#define ILI9163_MADCTL_MY  BIT(7)
+
+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
+struct drm_crtc_state *crtc_state,
+struct drm_plane_state *plane_state)
+{
+   struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+   struct mipi_dbi *dbi = >dbi;
+   u8 addr_mode;
+   int ret, idx;
+
+   if (!drm_dev_enter(pipe->crtc.dev, ))
+   return;
+
+   DRM_DEBUG_KMS("\n");
+
+   ret = mipi_dbi_poweron_conditional_reset(dbidev);
+   if (ret < 0)
+   goto out_exit;
+   if (ret == 1)
+   goto out_enable;
+
+   /* Gamma */
+   mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x04);
+   mipi_dbi_command(dbi, ILI9163_EN3GAM, 0x00);
+
+   /

Re: [PATCH v8] backlight: lms283gf05: Convert to GPIO descriptors

[Daniel Mack]

Hi Linus,

On 10/1/2021 1:09 pm, Linus Walleij wrote:
> This converts the lms283gf05 backlight driver to use GPIO
> descriptors and switches the single PXA Palm Z2 device
> over to defining these.
> 
> Since the platform data was only used to convey GPIO
> information we can delete the platform data header.
> 
> Notice that we define the proper active low semantics in
> the board file GPIO descriptor table (active low) and
> assert the reset line by bringing it to "1" (asserted).
> 
> Cc: Marek Vasut 
> Cc: Daniel Mack 
> Cc: Haojian Zhuang 
> Cc: Robert Jarzmik 
> Reviewed-by: Daniel Thompson 

Reviewed-by: Daniel Mack 

Thanks for working on this! The PXA tree is usually maintained by
Robert, but I haven't heard from him in a while.

Maybe this patch can go through some broader ARM tree like Arnd's (cc'ed)?


Daniel


> Signed-off-by: Linus Walleij 
> ---
> ChangeLog v7->v8:
> - Rebase onto v5.11-rc1
> - I wonder why this never seems to get merged...?
> ChangeLog v6->v7:
> - Rebase onto v5.10-rc1
> ChangeLog v5->v6:
> - Rebase onto v5.9-rc1
> ChangeLog v4->v5:
> - Rebase on v5.8-rc1
> - Collected Daniel's Reviewed-by tag.
> ChangeLog v3->v4:
> - Check IS_ERR() on the returned GPIO descriptor.
> - Unconditionally set consumer name since the API tolerates NULL.
> ChangeLog v2->v3:
> - Fix a use-before-allocated bug discovered by compile tests.
> - Remove unused ret variable as autobuilders complained.
> ChangeLog v1->v2:
> - Bring up the GPIO de-asserted in probe()
> 
> Marek: I saw this was written by you, are you regularly
> testing the Z2 device?
> ---
>  arch/arm/mach-pxa/z2.c   | 12 +---
>  drivers/video/backlight/lms283gf05.c | 43 +++-
>  include/linux/spi/lms283gf05.h   | 16 ---
>  3 files changed, 25 insertions(+), 46 deletions(-)
>  delete mode 100644 include/linux/spi/lms283gf05.h
> 
> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> index 21fd76bb09cd..89eb5243c85f 100644
> --- a/arch/arm/mach-pxa/z2.c
> +++ b/arch/arm/mach-pxa/z2.c
> @@ -20,7 +20,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
>  #include 
>  #include 
> @@ -578,8 +577,13 @@ static struct pxa2xx_spi_chip lms283_chip_info = {
>   .gpio_cs= GPIO88_ZIPITZ2_LCD_CS,
>  };
>  
> -static const struct lms283gf05_pdata lms283_pdata = {
> - .reset_gpio = GPIO19_ZIPITZ2_LCD_RESET,
> +static struct gpiod_lookup_table lms283_gpio_table = {
> + .dev_id = "spi2.0", /* SPI bus 2 chip select 0 */
> + .table = {
> + GPIO_LOOKUP("gpio-pxa", GPIO19_ZIPITZ2_LCD_RESET,
> + "reset", GPIO_ACTIVE_LOW),
> + { },
> + },
>  };
>  
>  static struct spi_board_info spi_board_info[] __initdata = {
> @@ -595,7 +599,6 @@ static struct spi_board_info spi_board_info[] __initdata 
> = {
>  {
>   .modalias   = "lms283gf05",
>   .controller_data= _chip_info,
> - .platform_data  = _pdata,
>   .max_speed_hz   = 40,
>   .bus_num= 2,
>   .chip_select= 0,
> @@ -615,6 +618,7 @@ static void __init z2_spi_init(void)
>  {
>   pxa2xx_set_spi_info(1, _ssp1_master_info);
>   pxa2xx_set_spi_info(2, _ssp2_master_info);
> + gpiod_add_lookup_table(_gpio_table);
>   spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
>  }
>  #else
> diff --git a/drivers/video/backlight/lms283gf05.c 
> b/drivers/video/backlight/lms283gf05.c
> index 0e45685bcc1c..36856962ed83 100644
> --- a/drivers/video/backlight/lms283gf05.c
> +++ b/drivers/video/backlight/lms283gf05.c
> @@ -9,16 +9,16 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
>  #include 
>  
>  #include 
> -#include 
>  #include 
>  
>  struct lms283gf05_state {
>   struct spi_device   *spi;
>   struct lcd_device   *ld;
> + struct gpio_desc*reset;
>  };
>  
>  struct lms283gf05_seq {
> @@ -90,13 +90,13 @@ static const struct lms283gf05_seq disp_pdwnseq[] = {
>  };
>  
>  
> -static void lms283gf05_reset(unsigned long gpio, bool inverted)
> +static void lms283gf05_reset(struct gpio_desc *gpiod)
>  {
> - gpio_set_value(gpio, !inverted);
> + gpiod_set_value(gpiod, 0); /* De-asserted */
>   mdelay(100);
> - gpio_set_value(gpio, inverted);
> + gpiod_set_value(gpiod, 1); /* Asserted */
>   mdelay(20);
> - gpio_set_value(gpio, !inverted);
> + gpiod_set_value(gpiod, 0); /* De-asserted */
>   mdelay(20)

Re: [PATCH -next] video: fbdev: pxafb: Fix "WARNING: invalid free of devm_ allocated data"

[Daniel Mack]

On 16/11/2018 12:02 PM, YueHaibing wrote:

'info->modes' got allocated with devm_kcalloc in of_get_pxafb_display.

This gives this error message:
   ./drivers/video/fbdev/pxafb.c:2238:2-7: WARNING: invalid free of devm_ 
allocated data

Signed-off-by: YueHaibing 


Oh, yes. Thanks for spotting this!

Could you please add these lines to the patch and resubmit?


Fixes: c8f96304ec8b4 ("video: fbdev: pxafb: switch to devm_* API")
Cc: sta...@kernel.org [v4.19+]
Reviewed-by: Daniel Mack 





---
  drivers/video/fbdev/pxafb.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/video/fbdev/pxafb.c b/drivers/video/fbdev/pxafb.c
index bbed039..d59c8a5 100644
--- a/drivers/video/fbdev/pxafb.c
+++ b/drivers/video/fbdev/pxafb.c
@@ -2234,10 +2234,8 @@ static struct pxafb_mach_info 
*of_pxafb_of_mach_info(struct device *dev)
if (!info)
return ERR_PTR(-ENOMEM);
ret = of_get_pxafb_mode_info(dev, info);
-   if (ret) {
-   kfree(info->modes);
+   if (ret)
return ERR_PTR(ret);
-   }
  
  	/*

 * On purpose, neither lccrX registers nor video memory size can be



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Re: [PATCH 1/4] video: fbdev: pxafb: clear allocated memory for video modes

[Daniel Mack]

On Tuesday, July 24, 2018 05:03 PM, Bartlomiej Zolnierkiewicz wrote:

On Monday, July 09, 2018 07:12:50 AM Daniel Mack wrote:



Should I resend with Robert's Reviewed-bys again? I'd like to get this
merged for 4.19 if possible.


No need for resend, I added Robert's tags while applying your patches.


Great, thank you!

Daniel
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[PATCH RESEND 2/2] drm/msm/adreno: Add power management functions for system sleep

[Daniel Mack]

When a msm8016 based system is woken up from suspend, the firmware in
the adreno device hangs.

[   83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: 
fsr=0x202, iova=0x, fsynr=0x2, cb=1
[   85.853633] msm 1a0.mdss: A306: hangcheck detected gpu lockup rb 0!
[   85.853661] msm 1a0.mdss: A306: completed fence: 370
[   85.859073] msm 1a0.mdss: A306: submitted fence: 372
[   85.865113] msm 1a0.mdss: A306: hangcheck recover!

Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume
as sleep ops.

Signed-off-by: Daniel Mack 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 05022ea2a007..12d87ccdec53 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -357,6 +357,7 @@ static int adreno_suspend(struct device *dev)
 #endif
 
 static const struct dev_pm_ops adreno_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 };
 
-- 
2.14.3

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[PATCH RESEND 1/2] drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()

[Daniel Mack]

To make suspend and resume work on msm8916 platforms, call into the generic
helpers and preserve the state across suspends.

Signed-off-by: Daniel Mack 
---
I've sent these two small patches twice already in May, but I haven't
gotten any feedback, not sure why.

We're using these on a number of prototypes and they seem to do work
just fine.

 drivers/gpu/drm/msm/msm_drv.c | 9 +
 drivers/gpu/drm/msm/msm_drv.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0a3ea3034e39..cdbe9249bff2 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -907,16 +907,25 @@ static struct drm_driver msm_driver = {
 static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
drm_kms_helper_poll_disable(ddev);
 
+   priv->pm_state = drm_atomic_helper_suspend(ddev);
+   if (IS_ERR(priv->pm_state)) {
+   drm_kms_helper_poll_enable(ddev);
+   return PTR_ERR(priv->pm_state);
+   }
+
return 0;
 }
 
 static int msm_pm_resume(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
+   drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
 
return 0;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 0a653dd2e618..459d06a1ab9f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -155,6 +155,7 @@ struct msm_drm_private {
struct shrinker shrinker;
 
struct msm_vblank_ctrl vblank_ctrl;
+   struct drm_atomic_state *pm_state;
 };
 
 struct msm_format {
-- 
2.14.3

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[PATCH RESEND 1/2] drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()

[Daniel Mack]

To make suspend and resume work on msm8916 platforms, call into the generic
helpers and preserve the state across suspends.

Signed-off-by: Daniel Mack 
---
 drivers/gpu/drm/msm/msm_drv.c | 9 +
 drivers/gpu/drm/msm/msm_drv.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0a3ea3034e39..cdbe9249bff2 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -907,16 +907,25 @@ static struct drm_driver msm_driver = {
 static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
drm_kms_helper_poll_disable(ddev);
 
+   priv->pm_state = drm_atomic_helper_suspend(ddev);
+   if (IS_ERR(priv->pm_state)) {
+   drm_kms_helper_poll_enable(ddev);
+   return PTR_ERR(priv->pm_state);
+   }
+
return 0;
 }
 
 static int msm_pm_resume(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
+   drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
 
return 0;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 0a653dd2e618..459d06a1ab9f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -155,6 +155,7 @@ struct msm_drm_private {
struct shrinker shrinker;
 
struct msm_vblank_ctrl vblank_ctrl;
+   struct drm_atomic_state *pm_state;
 };
 
 struct msm_format {
-- 
2.14.3

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[PATCH RESEND 2/2] drm/msm/adreno: Add power management functions for system sleep

[Daniel Mack]

When a msm8016 based system is woken up from suspend, the firmware in
the adreno device hangs.

[   83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: 
fsr=0x202, iova=0x, fsynr=0x2, cb=1
[   85.853633] msm 1a0.mdss: A306: hangcheck detected gpu lockup rb 0!
[   85.853661] msm 1a0.mdss: A306: completed fence: 370
[   85.859073] msm 1a0.mdss: A306: submitted fence: 372
[   85.865113] msm 1a0.mdss: A306: hangcheck recover!

Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume
as sleep ops.

Signed-off-by: Daniel Mack 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 05022ea2a007..12d87ccdec53 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -357,6 +357,7 @@ static int adreno_suspend(struct device *dev)
 #endif
 
 static const struct dev_pm_ops adreno_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 };
 
-- 
2.14.3

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[PATCH 1/2] drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()

[Daniel Mack]

To make suspend and resume work on msm8916 platforms, call into the generic
helpers and preserve the state across suspends.

Signed-off-by: Daniel Mack <dan...@zonque.org>
---
 drivers/gpu/drm/msm/msm_drv.c | 9 +
 drivers/gpu/drm/msm/msm_drv.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0a3ea3034e39..cdbe9249bff2 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -907,16 +907,25 @@ static struct drm_driver msm_driver = {
 static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
drm_kms_helper_poll_disable(ddev);
 
+   priv->pm_state = drm_atomic_helper_suspend(ddev);
+   if (IS_ERR(priv->pm_state)) {
+   drm_kms_helper_poll_enable(ddev);
+   return PTR_ERR(priv->pm_state);
+   }
+
return 0;
 }
 
 static int msm_pm_resume(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
+   struct msm_drm_private *priv = ddev->dev_private;
 
+   drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
 
return 0;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 0a653dd2e618..459d06a1ab9f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -155,6 +155,7 @@ struct msm_drm_private {
struct shrinker shrinker;
 
struct msm_vblank_ctrl vblank_ctrl;
+   struct drm_atomic_state *pm_state;
 };
 
 struct msm_format {
-- 
2.14.3

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[PATCH 2/2] drm/msm/adreno: Add power management functions for system sleep

[Daniel Mack]

When a msm8016 based system is woken up from suspend, the firmware in
the adreno device hangs.

[   83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: 
fsr=0x202, iova=0x, fsynr=0x2, cb=1
[   85.853633] msm 1a0.mdss: A306: hangcheck detected gpu lockup rb 0!
[   85.853661] msm 1a0.mdss: A306: completed fence: 370
[   85.859073] msm 1a0.mdss: A306: submitted fence: 372
[   85.865113] msm 1a0.mdss: A306: hangcheck recover!

Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume
as sleep ops.

Signed-off-by: Daniel Mack <dan...@zonque.org>
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 05022ea2a007..12d87ccdec53 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -357,6 +357,7 @@ static int adreno_suspend(struct device *dev)
 #endif
 
 static const struct dev_pm_ops adreno_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 };
 
-- 
2.14.3

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[PATCH RESEND 2/2] drm/msm: use correct aspace pointer in msm_gem_put_iova()

[Daniel Mack]

Even though msm_gem_put_iova() is currently a NOP function, the caller
should pass in the address space pointer it used to obtain the object.

Other call sites were changed in 8bdcd949bbe7e ("drm/msm: pass
address-space to _get_iova() and friends"), but this one seems to have
been forgotten.

Signed-off-by: Daniel Mack <dan...@zonque.org>
Cc: Rob Clark <robdcl...@gmail.com>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index c9b14948dc25..f844ca1f8e5a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1059,9 +1059,10 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host 
*msm_host, int size)
 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
 {
struct drm_device *dev = msm_host->dev;
+   struct msm_drm_private *priv = dev->dev_private;
 
if (msm_host->tx_gem_obj) {
-   msm_gem_put_iova(msm_host->tx_gem_obj, 0);
+   msm_gem_put_iova(msm_host->tx_gem_obj, priv->kms->aspace);
drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
msm_host->tx_gem_obj = NULL;
}
-- 
2.14.3

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[PATCH RESEND 1/2] drm/msm: remove unbalanced mutex unlock

[Daniel Mack]

This regression stems from 0e08270a1f01 ("drm/msm: Separate locking of
buffer resources from struct_mutex").

Signed-off-by: Daniel Mack <dan...@zonque.org>
Cc: Sushmita Susheelendra <ssush...@codeaurora.org>
Cc: Rob Clark <rcl...@redhat.com>
Fixes: 0e08270a1f01 ("drm/msm: Separate locking of buffer resources from 
struct_mutex")
---
I'm resending these two patches as I got no reply last time.

 drivers/gpu/drm/msm/dsi/dsi_host.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..27637d8a99ff 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -994,7 +994,6 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, 
int size)
 
ret = msm_gem_get_iova(msm_host->tx_gem_obj,
priv->kms->aspace, );
-   mutex_unlock(>struct_mutex);
if (ret) {
pr_err("%s: failed to get iova, %d\n", __func__, ret);
return ret;
-- 
2.14.3

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Re: [PATCH RESEND 1/2] drm/msm: remove unbalanced mutex unlock

[Daniel Mack]

On Thursday, May 03, 2018 02:24 PM, Rob Clark wrote:
> On Thu, May 3, 2018 at 8:00 AM, Daniel Mack <dan...@zonque.org> wrote:
>> This regression stems from 0e08270a1f01 ("drm/msm: Separate locking of
>> buffer resources from struct_mutex").
>>
>> Signed-off-by: Daniel Mack <dan...@zonque.org>
>> Cc: Sushmita Susheelendra <ssush...@codeaurora.org>
>> Cc: Rob Clark <rcl...@redhat.com>
>> Fixes: 0e08270a1f01 ("drm/msm: Separate locking of buffer resources from 
>> struct_mutex")
>> ---
>> I'm resending these two patches as I got no reply last time.
> 
> I've applied these two to msm-next.  Sorry I missed them before...
> for some reason they don't seem to show up in the dri-devel
> patchworks[1]

No problem, and thanks for applying them :)


Daniel


> 
> BR,
> -R
> 
> [1] https://patchwork.freedesktop.org/project/dri-devel/series/
> 
>>
>>  drivers/gpu/drm/msm/dsi/dsi_host.c | 1 -
>>  1 file changed, 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 0f7324a686ca..27637d8a99ff 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -994,7 +994,6 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host 
>> *msm_host, int size)
>>
>> ret = msm_gem_get_iova(msm_host->tx_gem_obj,
>> priv->kms->aspace, );
>> -   mutex_unlock(>struct_mutex);
>> if (ret) {
>> pr_err("%s: failed to get iova, %d\n", __func__, 
>> ret);
>> return ret;
>> --
>> 2.14.3
>>

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Re: GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

On Wednesday, April 18, 2018 10:06 AM, Archit Taneja wrote:
> On Tuesday 17 April 2018 05:51 PM, Daniel Mack wrote:
> Thanks for debugging this so thoroughly.
> 
>> It shows an underlying problem in the msm driver's clock components
>> though, because without this patch, the clocks will be effectively
>> slightly off from what was requested. For instance, when
>> gcc_mdss_byte0_clk is configured to 5625 Hz by the msm drm driver,
>> the clk core will let the DSI PLL recalculate its actual rate which is
>> 56246337 Hz. Hence, clk_set_rate() will always end up fiddling with the
>> knobs of that clock provider. That's what happens every time DSI
>> commands are sent, and that causes the image to flicker.
> 
> If I understood right, the main cause of the flicker is that we always
> end up re-locking/reconfiguring the DSI PLL every time we send a command
> (since dsi_link_clk_enable() is called in msm_dsi_host_xfer_prepare())?
> The re-configuration results in a glitch on the DSI clock, which is
> probably unacceptable for DSI Video mode transfer, especially for panels
> that don't have their own timing generators, which rely entirely on
> DSI clock lanes for scanning out the pixel data.
> 
> According to you, the reason why the reconfiguration happens is because
> the DSI PLL was never set exactly to 56.25 Mhz in the first place, and
> the core clock framework notices a difference in the requested rate and 
> the current rate (56.246 Mhz), and goes ahead to configure the PLL
> again when it's not needed. And this was averted in the downstream
> patch you mentioned as a side affect?

Yes, exactly.

>> The same problem applies to other clocks too. dsi0vco_clk for example
>> will be 449970703 rather than the requested 45000 etc.
>>
> 
> One easy way to get around this would be to not try to set the clock
> rates every time we try to send a command. We just enable/disable them.

Yes, that could work as well, but how about rounding the rates in the
callback that exists for that purpose? We're off by a fraction of a
permille only, after all.


Thanks,
Daniel
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Re: GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

On Wednesday, April 18, 2018 10:53 AM, Archit Taneja wrote:
> On Wednesday 18 April 2018 01:58 PM, Daniel Mack wrote:
>> On Wednesday, April 18, 2018 10:06 AM, Archit Taneja wrote:

>>> One easy way to get around this would be to not try to set the clock
>>> rates every time we try to send a command. We just enable/disable them.
>>
>> Yes, that could work as well, but how about rounding the rates in the
>> callback that exists for that purpose? We're off by a fraction of a
>> permille only, after all.
> 
> Sorry, forgot to respond to that in your last mail. I wasn't fully
> clear about how we'd do it.
> 
> Do you mean that we call clk_round_rate() on the byte and pixel
> clocks in dsi_link_clk_enable_6g() after we set the rates?

No, before. AFAIU, the clk core calls into the clock provider's
.round_rate() callback if it exists to determine the exact rate that it
is about to set. With this, the driver can return a rate that it
actually supports.

The MSM PLL driver currently only clamps the values in that callback,
but it could be smarter than that and return the closest rate to the
desired rate they can actually generate. The calculations based on the
various registers in dsi_pll_{14,28}nm_clk_recalc_rate() beat me though,
so it's not immediately clear how to get the math right to implement
that properly.


Thanks,
Daniel
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Re: GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

(cc Stephen)

Hi Archit,

On Monday, April 16, 2018 07:06 PM, Daniel Mack wrote:
> On Monday, April 09, 2018 03:08 PM, Archit Taneja wrote:
>>>> You could comment out the pm_runtime_put_sync() calls in
>>>> drivers/gpu/drm/msm/dsi/dsi_host.c, in case some registers got
>>>> reset during put_sync and weren't restored correctly after get_sync().
>>>
>>> That was my first suspicion too, but unfortunately, that's not the culprit.
>>> I think it would be good to comment out the put_sync() calls in
>> drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c and 
>> drivers/gpu/drm/msm/msm_drv.c too, since there is a parent-child 
>> hierarchy between DSI
>> and the top level MDSS block. Commenting out the put_syncs() just
>> in put_sync() might still result in the MDSS GDSC to switch off.
> 
> I spent some more time debugging this today and it turns out that
> calling into dsi_link_clk_enable() from msm_dsi_host_xfer_prepare() is
> already causing the drop-outs, even when no command buffers, DMA
> transfers etc. are involved. I then drilled further down and it showed
> that at least
> 
>   clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
> 
> in dsi_link_clk_enable_6g() one of the culprits. If I don't touch the
> clocks anymore after the initialization is done, everything is fine.

Okay, I finally found the bits between the two trees that make the
difference. It's a downstream patch that is included in the Linaro 4.9
branch but that's missing upstream and in their 4.14 branch:


https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/commit/?h=release/qcomlt-4.9=4ce2d6108d

What this patch does as a side-effect is that is sets the clock's actual
rate to the requested rate (core->rate = core->new_rate), and that fixes
the problem I'm seeing.

It shows an underlying problem in the msm driver's clock components
though, because without this patch, the clocks will be effectively
slightly off from what was requested. For instance, when
gcc_mdss_byte0_clk is configured to 5625 Hz by the msm drm driver,
the clk core will let the DSI PLL recalculate its actual rate which is
56246337 Hz. Hence, clk_set_rate() will always end up fiddling with the
knobs of that clock provider. That's what happens every time DSI
commands are sent, and that causes the image to flicker.

The same problem applies to other clocks too. dsi0vco_clk for example
will be 449970703 rather than the requested 45000 etc.

I guess a way to fix this properly would be to use
msm_dsi_pll_helper_clk_round_rate() to actually round the rates, but I'm
not sure.


Thanks,
Daniel
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Re: GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

Hi Archit,

On Monday, April 09, 2018 03:08 PM, Archit Taneja wrote:
>>> You could comment out the pm_runtime_put_sync() calls in
>>> drivers/gpu/drm/msm/dsi/dsi_host.c, in case some registers got
>>> reset during put_sync and weren't restored correctly after get_sync().
>>
>> That was my first suspicion too, but unfortunately, that's not the culprit.
>> I think it would be good to comment out the put_sync() calls in
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c and 
> drivers/gpu/drm/msm/msm_drv.c too, since there is a parent-child 
> hierarchy between DSI
> and the top level MDSS block. Commenting out the put_syncs() just
> in put_sync() might still result in the MDSS GDSC to switch off.

I spent some more time debugging this today and it turns out that
calling into dsi_link_clk_enable() from msm_dsi_host_xfer_prepare() is
already causing the drop-outs, even when no command buffers, DMA
transfers etc. are involved. I then drilled further down and it showed
that at least

  clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);

in dsi_link_clk_enable_6g() one of the culprits. If I don't touch the
clocks anymore after the initialization is done, everything is fine.

That rules out all other components such as GPU and IOMMU, but I still
don't grok what's going on, because I can't see a big difference in the
relevant clock functions in the dsi driver and the clock drivers between
4.9 and 4.14.

Any idea? I'll do some more debugging tomorrow.


Thanks,
Daniel
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Re: GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

Hi Archit,

Thanks a lot for your reply.

On Friday, April 06, 2018 01:25 PM, Archit Taneja wrote:
> On Thursday 05 April 2018 08:28 PM, Daniel Mack wrote:
>> I'm having issues with the GPU/DRM drivers on a msm8916 based platform
>> which is very similar to the DragonBoard 410c. In my setup, a DSI
>> display is directly connected to the SoC, and the video link is stable.
>>
>> However, when the host sends DCS commands down to the DSI panel (for
>> instance to set the backlight brightness), the image drops out, most of
>> the time only in terms of a short flicker, but sometimes it will
>> completely kill the image. In the latter case, only restarting the
>> Wayland compositor in userspace helps. This is also quite reproducible;
>> sending a NOP command once a second would give a visual flicker in 90%
>> of the cases, and it needs at most a minute to make the screen turn black.
>>
>> The interesting thing is that this used to work in a v4.9 based version,
>> but it broke somewhere on the way to v4.14. Unfortunately, the platform
>> does not boot a vanilla kernel, so I can't really bisect this. We
>> currently depend on the Linaro downstream patches which can be found here:
> 
> The major change that happened between qcomlt-4.9 and qcomlt-4.14 from a 
> DSI point of view was probably the addition of runtime PM support.
> 
> The register configurations that are responsible for interleaving DCS
> commands while video mode is still on should be the same.

Yeah, I think so too. I compared a lot of code but couldn't really find
anything either. At least, the command buffer contents and lengths are
identical.

> You could comment out the pm_runtime_put_sync() calls in
> drivers/gpu/drm/msm/dsi/dsi_host.c, in case some registers got
> reset during put_sync and weren't restored correctly after get_sync().

That was my first suspicion too, but unfortunately, that's not the culprit.

> Does your device initialize a splash screen in the bootloader?

It does, but that's the case for either of the two kernels. Do you think
that matters? And as you mention it - I'm building the driver as module,
because when built into the kernel, the msm driver fails to initialize
the hardware, and the console is flooded with the following message:

[   63.356837] dsi_err_worker: status=4

> You could also compare the reg dumps between 4.9 and 4.14 by enabling
> the config CONFIG_DRM_MSM_REGISTER_LOGGING and check if there are
> any register configuration differences between the two.

I did that, and there a quite a number of changes, mostly because the
KMS bits have changed a lot. Given that I'm not too familiar with this
driver stack, I'm not sure what exactly to look at.

> One (rather unlikely) possibility I can think of is if somehow the
> buffers used to send/receive DCS commands aren't mapped/unmapped
> correctly. There have been some msm_gem changes, and the IOMMU driver
> is new. That's the main reason why I'm wondering if the contents of the
> DCS buffers somehow got corrupt.

That may well be, but I can't really see what's wrong in that area.
Which iommu driver are you referring to, exactly?

> Is the panel initialized using DCS
> commands too?

Yes, and that works. The thing is that the commands do in fact reach the
panel and cause the desired effect, it's just that as a side effect, the
display very likely drops out when a command is sent. The registers that
are modified through msm_writel() by and between
msm_dsi_host_xfer_prepare() and msm_dsi_host_xfer_restore() are exactly
the same though. So it must be that some other part (the GPU or the
KMS?) doesn't like the fact that the DSI core mangles with the hardware
state in some way.

What hardware are all these changes developed and tested on, btw? I
guess it might be worth looking into differences between these platforms
and my own.


Again, thanks!
Daniel
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GPU/DRM issue with DSI commands on msm 8916

[Daniel Mack]

Hi,

I'm having issues with the GPU/DRM drivers on a msm8916 based platform
which is very similar to the DragonBoard 410c. In my setup, a DSI
display is directly connected to the SoC, and the video link is stable.

However, when the host sends DCS commands down to the DSI panel (for
instance to set the backlight brightness), the image drops out, most of
the time only in terms of a short flicker, but sometimes it will
completely kill the image. In the latter case, only restarting the
Wayland compositor in userspace helps. This is also quite reproducible;
sending a NOP command once a second would give a visual flicker in 90%
of the cases, and it needs at most a minute to make the screen turn black.

The interesting thing is that this used to work in a v4.9 based version,
but it broke somewhere on the way to v4.14. Unfortunately, the platform
does not boot a vanilla kernel, so I can't really bisect this. We
currently depend on the Linaro downstream patches which can be found here:


http://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=release/qcomlt-4.9

http://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=release/qcomlt-4.14

I've looked at the development that has happened in the area for some
time now, but I can't really pin-point any specific commit. Also, I
cherry-picked most of the patches to these drivers that came in after
v4.14, but that didn't help either.

Has this has been observed before? A pointer what to investigate on
would be very much appreciated. If there is any more information I can
provide, please let me know.


Thanks,
Daniel
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[PATCH 1/2] drm/msm: remove unbalanced mutex unlock

[Daniel Mack]

This regression stems from 0e08270a1f01 ("drm/msm: Separate locking of
buffer resources from struct_mutex").

Signed-off-by: Daniel Mack <dan...@zonque.org>
Cc: Sushmita Susheelendra <ssush...@codeaurora.org>
Cc: Rob Clark <rcl...@redhat.com>
Fixes: 0e08270a1f01 ("drm/msm: Separate locking of buffer resources from 
struct_mutex")
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..27637d8a99ff 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -994,7 +994,6 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, 
int size)
 
ret = msm_gem_get_iova(msm_host->tx_gem_obj,
priv->kms->aspace, );
-   mutex_unlock(>struct_mutex);
if (ret) {
pr_err("%s: failed to get iova, %d\n", __func__, ret);
return ret;
-- 
2.14.3

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[PATCH 2/2] drm/msm: use correct aspace pointer in msm_gem_put_iova()

[Daniel Mack]

Even though msm_gem_put_iova() is currently a NOP function, the caller
should pass in the address space pointer it used to obtain the object.

Other call sites were changed in 8bdcd949bbe7e ("drm/msm: pass
address-space to _get_iova() and friends"), but this one seems to have
been forgotten.

Signed-off-by: Daniel Mack <dan...@zonque.org>
Cc: Rob Clark <robdcl...@gmail.com>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index c9b14948dc25..f844ca1f8e5a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1059,9 +1059,10 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host 
*msm_host, int size)
 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
 {
struct drm_device *dev = msm_host->dev;
+   struct msm_drm_private *priv = dev->dev_private;
 
if (msm_host->tx_gem_obj) {
-   msm_gem_put_iova(msm_host->tx_gem_obj, 0);
+   msm_gem_put_iova(msm_host->tx_gem_obj, priv->kms->aspace);
drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
msm_host->tx_gem_obj = NULL;
}
-- 
2.14.3

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hot CPU with 3.6.0-rc7+ and intel graphic

[Daniel Mack]

On 27.09.2012 17:42, Toralf F?rster wrote:
> I'm observing a high CPU usage at my ThinkPad T420 (i5-2540M CPU), w/
> integrated intel graphic.
> 
> Powertop-2.1 shows that the GPU is always at 100%, although I've defined
> these settings :
> $> cat /etc/modprobe.d/i915.conf
> options i915 i915_enable_rc6=7 lvds_downclock=0
> 
> Kernel 3.5.4 works fine, I don't see any differences in dmesg output.

Could you try to bisect this problem?


Daniel

Re: hot CPU with 3.6.0-rc7+ and intel graphic

[Daniel Mack]

On 27.09.2012 17:42, Toralf Förster wrote:
 I'm observing a high CPU usage at my ThinkPad T420 (i5-2540M CPU), w/
 integrated intel graphic.
 
 Powertop-2.1 shows that the GPU is always at 100%, although I've defined
 these settings :
 $ cat /etc/modprobe.d/i915.conf
 options i915 i915_enable_rc6=7 lvds_downclock=0
 
 Kernel 3.5.4 works fine, I don't see any differences in dmesg output.

Could you try to bisect this problem?


Daniel


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Strange effect with i915 backlight controller

[Daniel Mack]

On 11/14/2011 11:39 AM, Takashi Iwai wrote:
> OK, then perhaps a better fix is to change the check to be equivalent
> with pineview, as you mentioned in the original post.  The handling of
> bit 0 for old chips was lost during the refactoring of backlight code
> since 2.6.37.
> 
> Does the patch below work for you?
> 
> The only concern by this fix is that it changes the max value.  If
> apps expect some certain (e.g. recorded) value, it may screw up.  But
> I don't expect this would happen with sane apps.

Works perfectly - let's ship it :)


Thanks again,
Daniel


> ===
> From: Takashi Iwai 
> Subject: drm/i915: Fix invalid backpanel values for GEN3 or older chips
> 
> While refactoring of backlight control code in commit [a95735569:
> drm/i915: Refactor panel backlight controls], the handling of the bit
> 0 of duty-cycle was gone except for pineview.  This resulted in invalid
> register values for old chips like 915GM.  When the bit 0 is set, the
> backlight is turned off suddenly.
> 
> This patch changes the bit-0 check by replacing with the condition of
> gen < 4 (pineview is included in this condition, too).
> 
> Reported-by: Daniel Mack 
> Signed-off-by: Takashi Iwai 
> ---
>  drivers/gpu/drm/i915/intel_panel.c |8 +++-
>  1 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index 499d4c0..737d00f 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -178,12 +178,10 @@ u32 intel_panel_get_max_backlight(struct drm_device 
> *dev)
>   if (HAS_PCH_SPLIT(dev)) {
>   max >>= 16;
>   } else {
> - if (IS_PINEVIEW(dev)) {
> + if (INTEL_INFO(dev)->gen < 4) {
>   max >>= 17;
>   } else {
>   max >>= 16;
> - if (INTEL_INFO(dev)->gen < 4)
> - max &= ~1;
>   }
>  
>   if (is_backlight_combination_mode(dev))
> @@ -203,7 +201,7 @@ u32 intel_panel_get_backlight(struct drm_device *dev)
>   val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
>   } else {
>   val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> - if (IS_PINEVIEW(dev))
> + if (INTEL_INFO(dev)->gen < 4)
>   val >>= 1;
>  
>   if (is_backlight_combination_mode(dev)) {
> @@ -246,7 +244,7 @@ static void intel_panel_actually_set_backlight(struct 
> drm_device *dev, u32 level
>   }
>  
>   tmp = I915_READ(BLC_PWM_CTL);
> - if (IS_PINEVIEW(dev)) {
> + if (INTEL_INFO(dev)->gen < 4) {
>   tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
>   level <<= 1;
>   } else

Re: Strange effect with i915 backlight controller

[Daniel Mack]

On 11/14/2011 11:39 AM, Takashi Iwai wrote:
 OK, then perhaps a better fix is to change the check to be equivalent
 with pineview, as you mentioned in the original post.  The handling of
 bit 0 for old chips was lost during the refactoring of backlight code
 since 2.6.37.
 
 Does the patch below work for you?
 
 The only concern by this fix is that it changes the max value.  If
 apps expect some certain (e.g. recorded) value, it may screw up.  But
 I don't expect this would happen with sane apps.

Works perfectly - let's ship it :)


Thanks again,
Daniel


 ===
 From: Takashi Iwai ti...@suse.de
 Subject: drm/i915: Fix invalid backpanel values for GEN3 or older chips
 
 While refactoring of backlight control code in commit [a95735569:
 drm/i915: Refactor panel backlight controls], the handling of the bit
 0 of duty-cycle was gone except for pineview.  This resulted in invalid
 register values for old chips like 915GM.  When the bit 0 is set, the
 backlight is turned off suddenly.
 
 This patch changes the bit-0 check by replacing with the condition of
 gen  4 (pineview is included in this condition, too).
 
 Reported-by: Daniel Mack zon...@gmail.com
 Signed-off-by: Takashi Iwai ti...@suse.de
 ---
  drivers/gpu/drm/i915/intel_panel.c |8 +++-
  1 files changed, 3 insertions(+), 5 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/intel_panel.c 
 b/drivers/gpu/drm/i915/intel_panel.c
 index 499d4c0..737d00f 100644
 --- a/drivers/gpu/drm/i915/intel_panel.c
 +++ b/drivers/gpu/drm/i915/intel_panel.c
 @@ -178,12 +178,10 @@ u32 intel_panel_get_max_backlight(struct drm_device 
 *dev)
   if (HAS_PCH_SPLIT(dev)) {
   max = 16;
   } else {
 - if (IS_PINEVIEW(dev)) {
 + if (INTEL_INFO(dev)-gen  4) {
   max = 17;
   } else {
   max = 16;
 - if (INTEL_INFO(dev)-gen  4)
 - max = ~1;
   }
  
   if (is_backlight_combination_mode(dev))
 @@ -203,7 +201,7 @@ u32 intel_panel_get_backlight(struct drm_device *dev)
   val = I915_READ(BLC_PWM_CPU_CTL)  BACKLIGHT_DUTY_CYCLE_MASK;
   } else {
   val = I915_READ(BLC_PWM_CTL)  BACKLIGHT_DUTY_CYCLE_MASK;
 - if (IS_PINEVIEW(dev))
 + if (INTEL_INFO(dev)-gen  4)
   val = 1;
  
   if (is_backlight_combination_mode(dev)) {
 @@ -246,7 +244,7 @@ static void intel_panel_actually_set_backlight(struct 
 drm_device *dev, u32 level
   }
  
   tmp = I915_READ(BLC_PWM_CTL);
 - if (IS_PINEVIEW(dev)) {
 + if (INTEL_INFO(dev)-gen  4) {
   tmp = ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
   level = 1;
   } else

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Strange effect with i915 backlight controller

[Daniel Mack]

On 11/14/2011 11:39 AM, Takashi Iwai wrote:
> [Added Chris to Cc]
> 
> At Sun, 13 Nov 2011 17:24:09 +0100,
> Daniel Mack wrote:
>>
>> Hi Takashi,
>>
>> On 11/10/2011 04:39 PM, Takashi Iwai wrote:
>>> At Thu, 10 Nov 2011 16:11:29 +0100,
>>> Daniel Mack wrote:
>>>>
>>>> On 11/08/2011 01:57 AM, Daniel Mack wrote:
>>>>> Didn't get any response yet, hence copying LKML for a broader audience.
>>>>
>>>> Nobody, really?
>>>>
>>>> This is a rather annoying regression, as touching the brightness keys
>>>> appearantly switches off the whole machine. I'm sure this is trivial to
>>>> fix, I just don't have the insight of this driver and the chipset.
>>>
>>> I vaguely remember that the bit 0 is invalid on some old chips.
>>> Maybe 915GM is one of them, as it's gen3?  If so, the patch like below
>>> may work.
>>
>> Thank you for looking into this.
>>
>>> ---
>>> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
>>> b/drivers/gpu/drm/i915/intel_panel.c
>>> index 499d4c0..be952d1 100644
>>> --- a/drivers/gpu/drm/i915/intel_panel.c
>>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>>> @@ -249,8 +249,11 @@ static void intel_panel_actually_set_backlight(struct 
>>> drm_device *dev, u32 level
>>> if (IS_PINEVIEW(dev)) {
>>> tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
>>> level <<= 1;
>>> -   } else
>>> +   } else {
>>> tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
>>> +   if (INTEL_INFO(dev)->gen < 4)
>>> +   tmp &= ~1;
>>> +   }
>>> I915_WRITE(BLC_PWM_CTL, tmp | level);
>>>  }
>>>  
>>
>> This seems to be the right intention, but the value you want to modify
>> under this condition is 'level', not 'tmp'.
> 
> Ah, of course.  Sorry for that.
> 
>> With this amendment of your
>> patch, things work perfectly fine here.
> 
> OK, then perhaps a better fix is to change the check to be equivalent
> with pineview, as you mentioned in the original post.  The handling of
> bit 0 for old chips was lost during the refactoring of backlight code
> since 2.6.37.
> 
> Does the patch below work for you?

Will test, but I only have occasional access to the machine, so this
will have to wait for some days.

> The only concern by this fix is that it changes the max value.  If
> apps expect some certain (e.g. recorded) value, it may screw up.  But
> I don't expect this would happen with sane apps.

I don't think so either.


Thanks,
Daniel

Re: Strange effect with i915 backlight controller

[Daniel Mack]

On 11/14/2011 11:39 AM, Takashi Iwai wrote:
 [Added Chris to Cc]
 
 At Sun, 13 Nov 2011 17:24:09 +0100,
 Daniel Mack wrote:

 Hi Takashi,

 On 11/10/2011 04:39 PM, Takashi Iwai wrote:
 At Thu, 10 Nov 2011 16:11:29 +0100,
 Daniel Mack wrote:

 On 11/08/2011 01:57 AM, Daniel Mack wrote:
 Didn't get any response yet, hence copying LKML for a broader audience.

 Nobody, really?

 This is a rather annoying regression, as touching the brightness keys
 appearantly switches off the whole machine. I'm sure this is trivial to
 fix, I just don't have the insight of this driver and the chipset.

 I vaguely remember that the bit 0 is invalid on some old chips.
 Maybe 915GM is one of them, as it's gen3?  If so, the patch like below
 may work.

 Thank you for looking into this.

 ---
 diff --git a/drivers/gpu/drm/i915/intel_panel.c 
 b/drivers/gpu/drm/i915/intel_panel.c
 index 499d4c0..be952d1 100644
 --- a/drivers/gpu/drm/i915/intel_panel.c
 +++ b/drivers/gpu/drm/i915/intel_panel.c
 @@ -249,8 +249,11 @@ static void intel_panel_actually_set_backlight(struct 
 drm_device *dev, u32 level
 if (IS_PINEVIEW(dev)) {
 tmp = ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
 level = 1;
 -   } else
 +   } else {
 tmp = ~BACKLIGHT_DUTY_CYCLE_MASK;
 +   if (INTEL_INFO(dev)-gen  4)
 +   tmp = ~1;
 +   }
 I915_WRITE(BLC_PWM_CTL, tmp | level);
  }
  

 This seems to be the right intention, but the value you want to modify
 under this condition is 'level', not 'tmp'.
 
 Ah, of course.  Sorry for that.
 
 With this amendment of your
 patch, things work perfectly fine here.
 
 OK, then perhaps a better fix is to change the check to be equivalent
 with pineview, as you mentioned in the original post.  The handling of
 bit 0 for old chips was lost during the refactoring of backlight code
 since 2.6.37.
 
 Does the patch below work for you?

Will test, but I only have occasional access to the machine, so this
will have to wait for some days.

 The only concern by this fix is that it changes the max value.  If
 apps expect some certain (e.g. recorded) value, it may screw up.  But
 I don't expect this would happen with sane apps.

I don't think so either.


Thanks,
Daniel
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Strange effect with i915 backlight controller

[Daniel Mack]

Hi Takashi,

On 11/10/2011 04:39 PM, Takashi Iwai wrote:
> At Thu, 10 Nov 2011 16:11:29 +0100,
> Daniel Mack wrote:
>>
>> On 11/08/2011 01:57 AM, Daniel Mack wrote:
>>> Didn't get any response yet, hence copying LKML for a broader audience.
>>
>> Nobody, really?
>>
>> This is a rather annoying regression, as touching the brightness keys
>> appearantly switches off the whole machine. I'm sure this is trivial to
>> fix, I just don't have the insight of this driver and the chipset.
> 
> I vaguely remember that the bit 0 is invalid on some old chips.
> Maybe 915GM is one of them, as it's gen3?  If so, the patch like below
> may work.

Thank you for looking into this.

> ---
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index 499d4c0..be952d1 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -249,8 +249,11 @@ static void intel_panel_actually_set_backlight(struct 
> drm_device *dev, u32 level
>   if (IS_PINEVIEW(dev)) {
>   tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
>   level <<= 1;
> - } else
> + } else {
>   tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
> + if (INTEL_INFO(dev)->gen < 4)
> + tmp &= ~1;
> + }
>   I915_WRITE(BLC_PWM_CTL, tmp | level);
>  }
>  

This seems to be the right intention, but the value you want to modify
under this condition is 'level', not 'tmp'. With this amendment of your
patch, things work perfectly fine here.

You can add my

  Reported-and-tested-by: Daniel Mack 

and please Cc: stable so we get this to the users asap.


Thanks!

Daniel

Re: Strange effect with i915 backlight controller

[Daniel Mack]

Hi Takashi,

On 11/10/2011 04:39 PM, Takashi Iwai wrote:
 At Thu, 10 Nov 2011 16:11:29 +0100,
 Daniel Mack wrote:

 On 11/08/2011 01:57 AM, Daniel Mack wrote:
 Didn't get any response yet, hence copying LKML for a broader audience.

 Nobody, really?

 This is a rather annoying regression, as touching the brightness keys
 appearantly switches off the whole machine. I'm sure this is trivial to
 fix, I just don't have the insight of this driver and the chipset.
 
 I vaguely remember that the bit 0 is invalid on some old chips.
 Maybe 915GM is one of them, as it's gen3?  If so, the patch like below
 may work.

Thank you for looking into this.

 ---
 diff --git a/drivers/gpu/drm/i915/intel_panel.c 
 b/drivers/gpu/drm/i915/intel_panel.c
 index 499d4c0..be952d1 100644
 --- a/drivers/gpu/drm/i915/intel_panel.c
 +++ b/drivers/gpu/drm/i915/intel_panel.c
 @@ -249,8 +249,11 @@ static void intel_panel_actually_set_backlight(struct 
 drm_device *dev, u32 level
   if (IS_PINEVIEW(dev)) {
   tmp = ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
   level = 1;
 - } else
 + } else {
   tmp = ~BACKLIGHT_DUTY_CYCLE_MASK;
 + if (INTEL_INFO(dev)-gen  4)
 + tmp = ~1;
 + }
   I915_WRITE(BLC_PWM_CTL, tmp | level);
  }
  

This seems to be the right intention, but the value you want to modify
under this condition is 'level', not 'tmp'. With this amendment of your
patch, things work perfectly fine here.

You can add my

  Reported-and-tested-by: Daniel Mack zon...@gmail.com

and please Cc: stable so we get this to the users asap.


Thanks!

Daniel
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Strange effect with i915 backlight controller

[Daniel Mack]

On 11/08/2011 01:57 AM, Daniel Mack wrote:
> Didn't get any response yet, hence copying LKML for a broader audience.

Nobody, really?

This is a rather annoying regression, as touching the brightness keys
appearantly switches off the whole machine. I'm sure this is trivial to
fix, I just don't have the insight of this driver and the chipset.

Any pointer greatly appreciated, and I can test patches.


Thanks,
Daniel



> 
> On 11/04/2011 03:36 PM, Daniel Mack wrote:
>> I'm facing a bug on a Samsung X20 notebook which features an i915
>> chipset (output of 'lspci -v' attached).
>>
>> The effect is that setting the backlight to odd values causes the value
>> to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook
>> (I don't recall which model it was).
>>
>> So this will turn the backlight to full brightness:
>>
>> # cat /sys/class/backlight/intel_backlight/max_brightness
>> 29750
>> # echo 29750 > /sys/class/backlight/intel_backlight/brightness
>>
>> However, writing 29749 will turn the display backlight off, and 29748
>> appears to be the next valid lower value.
>>
>> It seems like the IS_PINEVIEW() branch in
>> drivers/gpu/drm/i915/intel_panel.c:intel_panel_actually_set_backlight()
>> could do the right thing, but this code is written for an entirely
>> different model, right?
>>
>> I can reproduce this on 3.0 and 3.1 vanilla as well as with the current
>> mainline git.
>>
>> Let me know if there is any patch that I can test.
>>
>>
>> Thanks,
>> Daniel
> 

Re: Strange effect with i915 backlight controller

[Daniel Mack]

On 11/08/2011 01:57 AM, Daniel Mack wrote:
 Didn't get any response yet, hence copying LKML for a broader audience.

Nobody, really?

This is a rather annoying regression, as touching the brightness keys
appearantly switches off the whole machine. I'm sure this is trivial to
fix, I just don't have the insight of this driver and the chipset.

Any pointer greatly appreciated, and I can test patches.


Thanks,
Daniel



 
 On 11/04/2011 03:36 PM, Daniel Mack wrote:
 I'm facing a bug on a Samsung X20 notebook which features an i915
 chipset (output of 'lspci -v' attached).

 The effect is that setting the backlight to odd values causes the value
 to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook
 (I don't recall which model it was).

 So this will turn the backlight to full brightness:

 # cat /sys/class/backlight/intel_backlight/max_brightness
 29750
 # echo 29750  /sys/class/backlight/intel_backlight/brightness

 However, writing 29749 will turn the display backlight off, and 29748
 appears to be the next valid lower value.

 It seems like the IS_PINEVIEW() branch in
 drivers/gpu/drm/i915/intel_panel.c:intel_panel_actually_set_backlight()
 could do the right thing, but this code is written for an entirely
 different model, right?

 I can reproduce this on 3.0 and 3.1 vanilla as well as with the current
 mainline git.

 Let me know if there is any patch that I can test.


 Thanks,
 Daniel
 

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Strange effect with i915 backlight controller

[Daniel Mack]

Didn't get any response yet, hence copying LKML for a broader audience.


On 11/04/2011 03:36 PM, Daniel Mack wrote:
> I'm facing a bug on a Samsung X20 notebook which features an i915
> chipset (output of 'lspci -v' attached).
>
> The effect is that setting the backlight to odd values causes the value
> to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook
> (I don't recall which model it was).
>
> So this will turn the backlight to full brightness:
>
> # cat /sys/class/backlight/intel_backlight/max_brightness
> 29750
> # echo 29750 > /sys/class/backlight/intel_backlight/brightness
>
> However, writing 29749 will turn the display backlight off, and 29748
> appears to be the next valid lower value.
>
> It seems like the IS_PINEVIEW() branch in
> drivers/gpu/drm/i915/intel_panel.c:intel_panel_actually_set_backlight()
> could do the right thing, but this code is written for an entirely
> different model, right?
>
> I can reproduce this on 3.0 and 3.1 vanilla as well as with the current
> mainline git.
>
> Let me know if there is any patch that I can test.
>
>
> Thanks,
> Daniel

-- next part --
An embedded and charset-unspecified text was scrubbed...
Name: lspci-v-x20.txt
URL: 
<http://lists.freedesktop.org/archives/dri-devel/attachments/2008/3891ab5d/attachment-0001.txt>

Re: Strange effect with i915 backlight controller

[Daniel Mack]

Didn't get any response yet, hence copying LKML for a broader audience.


On 11/04/2011 03:36 PM, Daniel Mack wrote:

I'm facing a bug on a Samsung X20 notebook which features an i915
chipset (output of 'lspci -v' attached).

The effect is that setting the backlight to odd values causes the value
to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook
(I don't recall which model it was).

So this will turn the backlight to full brightness:

# cat /sys/class/backlight/intel_backlight/max_brightness
29750
# echo 29750  /sys/class/backlight/intel_backlight/brightness

However, writing 29749 will turn the display backlight off, and 29748
appears to be the next valid lower value.

It seems like the IS_PINEVIEW() branch in
drivers/gpu/drm/i915/intel_panel.c:intel_panel_actually_set_backlight()
could do the right thing, but this code is written for an entirely
different model, right?

I can reproduce this on 3.0 and 3.1 vanilla as well as with the current
mainline git.

Let me know if there is any patch that I can test.


Thanks,
Daniel


00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express 
Processor to DRAM Controller (rev 03)
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, fast devsel, latency 0
Capabilities: [e0] Vendor Specific Information: Len=09 ?
Kernel driver in use: agpgart-intel

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML 
Express Graphics Controller (rev 03) (prog-if 00 [VGA controller])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, fast devsel, latency 0, IRQ 16
Memory at b008 (32-bit, non-prefetchable) [size=512K]
I/O ports at 1800 [size=8]
Memory at c000 (32-bit, prefetchable) [size=256M]
Memory at b000 (32-bit, non-prefetchable) [size=256K]
Expansion ROM at unassigned [disabled]
Capabilities: [d0] Power Management version 2
Kernel driver in use: i915
Kernel modules: intelfb, i915

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express 
Graphics Controller (rev 03)
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: fast devsel
Memory at 4200 (32-bit, non-prefetchable) [disabled] [size=512K]
Capabilities: [d0] Power Management version 2

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI 
Express Port 1 (rev 03) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 3000-3fff
Memory behind bridge: b400-b7ff
Prefetchable memory behind bridge: d000-d3ff
Capabilities: [40] Express Root Port (Slot+), MSI 00
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Capabilities: [90] Subsystem: Samsung Electronics Co Ltd Device c01a
Capabilities: [a0] Power Management version 2
Capabilities: [100] Virtual Channel
Capabilities: [180] Root Complex Link
Kernel driver in use: pcieport
Kernel modules: shpchp

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #1 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 23
I/O ports at 1820 [size=32]
Kernel driver in use: uhci_hcd

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #2 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 19
I/O ports at 1840 [size=32]
Kernel driver in use: uhci_hcd

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #3 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 18
I/O ports at 1860 [size=32]
Kernel driver in use: uhci_hcd

00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #4 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 16
I/O ports at 1880 [size=32]
Kernel driver in use: uhci_hcd

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 23
Memory at b004 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Debug port: BAR=1 offset=00a0
Kernel driver in use: ehci_hcd

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile

Strange effect with i915 backlight controller

[Daniel Mack]

Hi,

I'm facing a bug on a Samsung X20 notebook which features an i915 
chipset (output of 'lspci -v' attached).

The effect is that setting the backlight to odd values causes the value 
to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook 
(I don't recall which model it was).

So this will turn the backlight to full brightness:

# cat /sys/class/backlight/intel_backlight/max_brightness
29750
# echo 29750 > /sys/class/backlight/intel_backlight/brightness

However, writing 29749 will turn the display backlight off, and 29748 
appears to be the next valid lower value.

It seems like the IS_PINEVIEW() branch in 
drivers/gpu/drm/i915/intel_panel.c: intel_panel_actually_set_backlight() 
could do the right thing, but this code is written for an entirely 
different model, right?

I can reproduce this on 3.0 and 3.1 vanilla as well as with the current 
mainline git.

Let me know if there is any patch that I can test.


Thanks,
Daniel
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URL: 

Strange effect with i915 backlight controller

[Daniel Mack]

Hi,

I'm facing a bug on a Samsung X20 notebook which features an i915 
chipset (output of 'lspci -v' attached).


The effect is that setting the backlight to odd values causes the value 
to be misinterpreted. Harald Hoyer (cc:) had the same thing on a Netbook 
(I don't recall which model it was).


So this will turn the backlight to full brightness:

# cat /sys/class/backlight/intel_backlight/max_brightness
29750
# echo 29750  /sys/class/backlight/intel_backlight/brightness

However, writing 29749 will turn the display backlight off, and 29748 
appears to be the next valid lower value.


It seems like the IS_PINEVIEW() branch in 
drivers/gpu/drm/i915/intel_panel.c: intel_panel_actually_set_backlight() 
could do the right thing, but this code is written for an entirely 
different model, right?


I can reproduce this on 3.0 and 3.1 vanilla as well as with the current 
mainline git.


Let me know if there is any patch that I can test.


Thanks,
Daniel
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express 
Processor to DRAM Controller (rev 03)
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, fast devsel, latency 0
Capabilities: [e0] Vendor Specific Information: Len=09 ?
Kernel driver in use: agpgart-intel

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML 
Express Graphics Controller (rev 03) (prog-if 00 [VGA controller])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, fast devsel, latency 0, IRQ 16
Memory at b008 (32-bit, non-prefetchable) [size=512K]
I/O ports at 1800 [size=8]
Memory at c000 (32-bit, prefetchable) [size=256M]
Memory at b000 (32-bit, non-prefetchable) [size=256K]
Expansion ROM at unassigned [disabled]
Capabilities: [d0] Power Management version 2
Kernel driver in use: i915
Kernel modules: intelfb, i915

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express 
Graphics Controller (rev 03)
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: fast devsel
Memory at 4200 (32-bit, non-prefetchable) [disabled] [size=512K]
Capabilities: [d0] Power Management version 2

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI 
Express Port 1 (rev 03) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 3000-3fff
Memory behind bridge: b400-b7ff
Prefetchable memory behind bridge: d000-d3ff
Capabilities: [40] Express Root Port (Slot+), MSI 00
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Capabilities: [90] Subsystem: Samsung Electronics Co Ltd Device c01a
Capabilities: [a0] Power Management version 2
Capabilities: [100] Virtual Channel
Capabilities: [180] Root Complex Link
Kernel driver in use: pcieport
Kernel modules: shpchp

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #1 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 23
I/O ports at 1820 [size=32]
Kernel driver in use: uhci_hcd

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #2 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 19
I/O ports at 1840 [size=32]
Kernel driver in use: uhci_hcd

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #3 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 18
I/O ports at 1860 [size=32]
Kernel driver in use: uhci_hcd

00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB UHCI #4 (rev 03) (prog-if 00 [UHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 16
I/O ports at 1880 [size=32]
Kernel driver in use: uhci_hcd

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) 
USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: Samsung Electronics Co Ltd Device c01a
Flags: bus master, medium devsel, latency 0, IRQ 23
Memory at b004 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Debug port: BAR=1 offset=00a0
Kernel driver in use: ehci_hcd

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d3) (prog-if 
01 [Subtractive decode])
Flags: bus master, fast devsel, latency