[PATCH] drm/mediatek: DP HPD Detect with debounce

[Jitao Shi]

DP Spec 1.4a 3.3 requires dp detect the hpd with debounce.

Upstream implementations should implement HPD signal de-bouncing on
an external connection. A period of 100ms should be used for
detecting an HPD connect event (i.e., the event, “HPD high,” is
confirmed only after HPD has been continuously asserted for 100ms).
Care should be taken to not implement de-bouncing on an IRQ_HPD and
on a downstream device-generated pair of HPD disconnect/reconnect
events (typically HPD shall be de-asserted for more than 2ms, but
less than 100ms in this case). To cover these cases, HPD de-bounce
should be implemented only after HPD low has been detected for 100ms.
 Timing requirements in this Standard related to the detection of
HPD high are to be interpreted as applying from the completion of an
implementation-dependent de-bounce period.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dp.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c 
b/drivers/gpu/drm/mediatek/mtk_dp.c
index a256d55346a2..05f401a024a4 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -193,6 +193,8 @@ struct mtk_dp {
struct mutex eld_lock;
u8 connector_eld[MAX_ELD_BYTES];
struct drm_connector *conn;
+   bool need_debounce;
+   struct timer_list debounce_timer;
 };
 
 enum mtk_dp_sdp_type {
@@ -2217,6 +2219,9 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void 
*dev)
if (event < 0)
return IRQ_HANDLED;
 
+   if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
+   msleep(100);
+
if (mtk_dp->drm_dev) {
dev_info(mtk_dp->dev, "drm_helper_hpd_irq_event\n");
drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
@@ -2296,6 +2301,14 @@ static irqreturn_t mtk_dp_hpd_isr_handler(struct mtk_dp 
*mtk_dp)
mtk_dp->train_state = MTK_DP_TRAIN_STATE_STARTUP;
}
train_info->cable_state_change = true;
+
+   if (train_info->cable_state_change) {
+   if (!train_info->cable_plugged_in) {
+   mod_timer(_dp->debounce_timer, jiffies + 
msecs_to_jiffies(100) - 1);
+   mtk_dp->need_debounce = false;
+   }
+   }
+
return IRQ_WAKE_THREAD;
 }
 
@@ -2903,6 +2916,13 @@ static int mtk_dp_register_audio_driver(struct device 
*dev)
return 0;
 }
 
+static void mtk_dp_debounce_timer(struct timer_list *t)
+{
+   struct mtk_dp *mtk_dp = from_timer(mtk_dp, t, debounce_timer);
+
+   mtk_dp->need_debounce = true;
+}
+
 static int mtk_dp_probe(struct platform_device *pdev)
 {
struct mtk_dp *mtk_dp;
@@ -2990,6 +3010,9 @@ static int mtk_dp_probe(struct platform_device *pdev)
else
mtk_dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
 
+   mtk_dp->need_debounce = true;
+   timer_setup(_dp->debounce_timer, mtk_dp_debounce_timer, 0);
+
mtk_dp->bridge.ops =
DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
drm_bridge_add(_dp->bridge);
@@ -3008,6 +3031,7 @@ static int mtk_dp_remove(struct platform_device *pdev)
 
mtk_dp_video_mute(mtk_dp, true);
mtk_dp_audio_mute(mtk_dp, true);
+   del_timer_sync(_dp->debounce_timer);
 
pm_runtime_disable(>dev);
 
-- 
2.12.5

[PATCH v3 1/2] drm/panel: panel-boe-tv101wum-nl6: tune the power sequence to avoid leakage

[Jitao Shi]

"auo,kd101n80-45na" 2st LCD SPEC update, need to modify the timing
between IOVCC and mipi data.
The 2st version of SPEC modifies the timing requirements from IOVCC to
Mipi Data. IOVCC is now required to take precedence over MIPI DATA,
otherwise there is a risk of leakage. It is recommended that the time
for MIPI to enter LP11 be postponed after IOVCC (delay20ms).

Signed-off-by: Jitao Shi 
Change-Id: Ic5212e2145a7dbf2efef9e5585904a93e1bc5a28
---
 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 88 +++---
 include/drm/panel_boe_tv101wum_nl6.h   | 28 
 2 files changed, 94 insertions(+), 22 deletions(-)
 create mode 100644 include/drm/panel_boe_tv101wum_nl6.h

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index db9d0b86d542..02efee06c430 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -49,7 +49,7 @@ struct boe_panel {
struct regulator *avee;
struct regulator *avdd;
struct gpio_desc *enable_gpio;
-
+   int powered_refcnt;
bool prepared;
 };
 
@@ -488,19 +488,15 @@ static int boe_panel_enter_sleep_mode(struct boe_panel 
*boe)
return 0;
 }
 
-static int boe_panel_unprepare(struct drm_panel *panel)
+static int boe_panel_power_off(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
-   int ret;
 
-   if (!boe->prepared)
-   return 0;
+   if (WARN_ON(boe->powered_refcnt == 0))
+   return -EINVAL;
 
-   ret = boe_panel_enter_sleep_mode(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
-   }
+   if (--boe->powered_refcnt != 0)
+   return 0;
 
msleep(150);
 
@@ -520,17 +516,45 @@ static int boe_panel_unprepare(struct drm_panel *panel)
regulator_disable(boe->pp1800);
}
 
+   return 0;
+}
+
+int panel_unprepare_power(struct drm_panel *panel)
+{
+   if (of_device_is_compatible(panel->dev->of_node, "auo,kd101n80-45na"))
+   return boe_panel_power_off(panel);
+
+   return 0;
+}
+EXPORT_SYMBOL(panel_unprepare_power);
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   if (!boe->prepared)
+   return 0;
+
+   ret = boe_panel_enter_sleep_mode(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
+   return ret;
+   }
+
+   boe_panel_power_off(panel);
+
boe->prepared = false;
 
return 0;
 }
 
-static int boe_panel_prepare(struct drm_panel *panel)
+static int boe_panel_power_on(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
int ret;
 
-   if (boe->prepared)
+   if (++boe->powered_refcnt != 1)
return 0;
 
gpiod_set_value(boe->enable_gpio, 0);
@@ -558,18 +582,8 @@ static int boe_panel_prepare(struct drm_panel *panel)
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(6000, 1);
 
-   ret = boe_panel_init_dcs_cmd(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to init panel: %d\n", ret);
-   goto poweroff;
-   }
-
-   boe->prepared = true;
-
return 0;
 
-poweroff:
-   regulator_disable(boe->avee);
 poweroffavdd:
regulator_disable(boe->avdd);
 poweroff1v8:
@@ -580,6 +594,36 @@ static int boe_panel_prepare(struct drm_panel *panel)
return ret;
 }
 
+int panel_prepare_power(struct drm_panel *panel)
+{
+   if (of_device_is_compatible(panel->dev->of_node, "auo,kd101n80-45na"))
+   return boe_panel_power_on(panel);
+
+   return 0;
+}
+EXPORT_SYMBOL(panel_prepare_power);
+
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   boe_panel_power_on(panel);
+
+   if (boe->prepared)
+   return 0;
+
+   ret = boe_panel_init_dcs_cmd(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to init panel: %d\n", ret);
+   return ret;
+   }
+
+   boe->prepared = true;
+
+   return 0;
+}
+
 static int boe_panel_enable(struct drm_panel *panel)
 {
msleep(130);
diff --git a/include/drm/panel_boe_tv101wum_nl6.h 
b/include/drm/panel_boe_tv101wum_nl6.h
new file mode 100644
index ..72abe3eb7840
--- /dev/null
+++ b/include/drm/panel_boe_tv101wum_nl6.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#ifndef __PANEL_BOE_TV101WUM_NL6_H__
+#define __PANEL_B

[PATCH v3 2/2] drm/mediatek: control panel's power before MIPI LP11

[Jitao Shi]

"auo,kd101n80-45na" requires the panel's IOVDD take precedence over
MIPI DATA. Otherwise there is a risk of leakage.

Signed-off-by: Jitao Shi 
Change-Id: I2da6179dea7e15bc5a53fe36db200b6c04f4d551
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 28 ++--
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 93b40c245f00..9fff0c483139 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,7 +24,7 @@
 #include 
 #include 
 #include 
-
+#include 
 #include "mtk_disp_drv.h"
 #include "mtk_drm_ddp_comp.h"
 
@@ -185,6 +185,7 @@ struct mtk_dsi {
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
struct drm_connector *connector;
+   struct drm_panel *panel;
struct phy *phy;
 
void __iomem *regs;
@@ -619,10 +620,16 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
  dsi->lanes);
 
+   if (dsi->panel) {
+   if (panel_prepare_power(dsi->panel)) {
+   DRM_INFO("can't prepare power the panel\n");
+   goto err_refcount;
+   }
+   }
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
if (ret < 0) {
dev_err(dev, "Failed to set data rate: %d\n", ret);
-   goto err_refcount;
+   goto err_prepare_power;
}
 
phy_power_on(dsi->phy);
@@ -665,6 +672,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->engine_clk);
 err_phy_power_off:
phy_power_off(dsi->phy);
+err_prepare_power:
+   if (dsi->panel) {
+   if (panel_unprepare_power(dsi->panel))
+   DRM_INFO("Can't unprepare power the panel\n");
+   }
 err_refcount:
dsi->refcount--;
return ret;
@@ -698,6 +710,11 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->digital_clk);
 
phy_power_off(dsi->phy);
+
+   if (dsi->panel) {
+   if (panel_unprepare_power(dsi->panel))
+   DRM_INFO("Can't unprepare power the panel\n");
+   }
 }
 
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
@@ -1001,7 +1018,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 {
struct mtk_dsi *dsi;
struct device *dev = >dev;
-   struct drm_panel *panel;
struct resource *regs;
int irq_num;
int ret;
@@ -1019,12 +1035,12 @@ static int mtk_dsi_probe(struct platform_device *pdev)
}
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
- , >next_bridge);
+ >panel, >next_bridge);
if (ret)
goto err_unregister_host;
 
-   if (panel) {
-   dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
+   if (dsi->panel) {
+   dsi->next_bridge = devm_drm_panel_bridge_add(dev, dsi->panel);
if (IS_ERR(dsi->next_bridge)) {
ret = PTR_ERR(dsi->next_bridge);
goto err_unregister_host;
-- 
2.12.5

[PATCH v3 0/2] seperate panel power control from panel prepare/unprepare

[Jitao Shi]

Changes since v2:
 - Panel driver panel-boe-tv101wum-nl6.c provides the power sequence apis.
 - The apis are called before dsi poweron and after dsi poweroff.

Changes since v1:
 - Fix null point when dsi next bridge isn't a panel.
 - "dsi mmsys reset" is implement by
   https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355

Jitao Shi (2):
  drm/panel: panel-boe-tv101wum-nl6: tune the power sequence to avoid
leakage
  drm/mediatek: control panel's power before MIPI LP11

 drivers/gpu/drm/mediatek/mtk_dsi.c | 28 ++--
 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 88 +++---
 include/drm/panel_boe_tv101wum_nl6.h   | 28 
 3 files changed, 116 insertions(+), 28 deletions(-)
 create mode 100644 include/drm/panel_boe_tv101wum_nl6.h

-- 
2.12.5

Re: [PATCH v7 1/3] drm/dsi: transer dsi hs packet aligned

[Jitao Shi]

Hi sirs

Pls help to review this change.

Best Regards
Jitao.

On Tue, 2021-10-05 at 07:53 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2021年9月16日 週四 上午6:31寫道：
> > 
> > Some DSI devices reqire the hs packet starting and ending
> > at same time on all dsi lanes. So use a flag to those devices.
> > 
> 
> Reviewed-by: Chun-Kuang Hu 
> 
> > Signed-off-by: Jitao Shi 
> > ---
> >  include/drm/drm_mipi_dsi.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/include/drm/drm_mipi_dsi.h
> > b/include/drm/drm_mipi_dsi.h
> > index af7ba8071eb0..8e8563792682 100644
> > --- a/include/drm/drm_mipi_dsi.h
> > +++ b/include/drm/drm_mipi_dsi.h
> > @@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
> >   * @lp_rate: maximum lane frequency for low power mode in hertz,
> > this should
> >   * be set to the real limits of the hardware, zero is only
> > accepted for
> >   * legacy drivers
> > + * @hs_packet_end_aligned: transfer dsi hs packet ending aligned
> >   */
> >  struct mipi_dsi_device {
> > struct mipi_dsi_host *host;
> > @@ -189,6 +190,7 @@ struct mipi_dsi_device {
> > unsigned long mode_flags;
> > unsigned long hs_rate;
> > unsigned long lp_rate;
> > +   bool hs_packet_end_aligned;
> >  };
> > 
> >  #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
> > --
> > 2.25.1

Re: [PATCH v7 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Jitao Shi]

Hi Xin,

Please help to review the changes in anx7625.c

On Thu, 2021-09-16 at 06:31 +0800, Jitao Shi wrote:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
> 
> Signed-off-by: Jitao Shi 
> ---
>  drivers/gpu/drm/bridge/analogix/anx7625.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c
> b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 14d73fb1dd15..d76fb63fa9f7 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct
> anx7625_data *ctx)
>   MIPI_DSI_MODE_VIDEO_SYNC_PULSE  |
>   MIPI_DSI_MODE_NO_EOT_PACKET |
>   MIPI_DSI_MODE_VIDEO_HSE;
> + dsi->hs_packet_end_aligned = true;
>  
>   if (mipi_dsi_attach(dsi) < 0) {
>   DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");

[PATCH v7 2/3] drm/mediatek: implment the dsi hs packets aligned

[Jitao Shi]

Some dsi devices require the packets on lanes aligned at the end,
or the screen will shift or scroll.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 93b40c245f00..9d72e6dce0bf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool hs_packet_end_aligned;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->hs_packet_end_aligned) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -793,6 +802,7 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
dsi->lanes = device->lanes;
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;
+   dsi->hs_packet_end_aligned = device->hs_packet_end_aligned;
 
return 0;
 }
-- 
2.25.1

[PATCH v7 3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift

[Jitao Shi]

This device requires the packets on lanes aligned at the end to fix
screen shift or scroll.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 14d73fb1dd15..d76fb63fa9f7 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
MIPI_DSI_MODE_VIDEO_SYNC_PULSE  |
MIPI_DSI_MODE_NO_EOT_PACKET |
MIPI_DSI_MODE_VIDEO_HSE;
+   dsi->hs_packet_end_aligned = true;
 
if (mipi_dsi_attach(dsi) < 0) {
DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
-- 
2.25.1

[PATCH v7 1/3] drm/dsi: transer dsi hs packet aligned

[Jitao Shi]

Some DSI devices reqire the hs packet starting and ending
at same time on all dsi lanes. So use a flag to those devices.

Signed-off-by: Jitao Shi 
---
 include/drm/drm_mipi_dsi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index af7ba8071eb0..8e8563792682 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
  * @lp_rate: maximum lane frequency for low power mode in hertz, this should
  * be set to the real limits of the hardware, zero is only accepted for
  * legacy drivers
+ * @hs_packet_end_aligned: transfer dsi hs packet ending aligned
  */
 struct mipi_dsi_device {
struct mipi_dsi_host *host;
@@ -189,6 +190,7 @@ struct mipi_dsi_device {
unsigned long mode_flags;
unsigned long hs_rate;
unsigned long lp_rate;
+   bool hs_packet_end_aligned;
 };
 
 #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
-- 
2.25.1

[PATCH v7 0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

Changes since v6:
 - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the 
dsi aligned.
 - Config the "hs_packet_end_aligned" in ANX7725 .attach().

Changes since v5:
 - Search the anx7625 compatible as flag to control dsi output aligned.

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" 
before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".

 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".

Jitao Shi (3):
  drm/dsi: transer dsi hs packet aligned
  drm/mediatek: implment the dsi hs packets aligned
  drm/bridge: anx7625: config hs packets end aligned to avoid screen
shift

 drivers/gpu/drm/bridge/analogix/anx7625.c |  1 +
 drivers/gpu/drm/mediatek/mtk_dsi.c| 10 ++
 include/drm/drm_mipi_dsi.h|  2 ++
 3 files changed, 13 insertions(+)

-- 
2.25.1

[PATCH v6 1/1] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

The bridge chip ANX7625 requires the packets on lanes aligned at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..033234d51e86 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   if (dsi->next_bridge)
+   dsi->force_dsi_end_without_null = 
of_device_is_compatible(dsi->next_bridge->of_node,
+ 
"analogix,anx7625");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
2.25.1

[PATCH v6 0/1] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

Changes since v5:
 - Remvoe the anx7625 devicetree change. Use the compatible string intead.

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" 
before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".

 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".

Jitao Shi (1):
  drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid
screen shift

 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

-- 
2.25.1

[PATCH v2 3/3] drm/mediatek: fine tune the dsi panel's power sequence

[Jitao Shi]

Add the drm_panel_prepare_power and drm_panel_unprepare_power control.
Turn on panel power(drm_panel_prepare_power) and control before dsi
enable. And then dsi enable, send dcs cmd in drm_panel_prepare, last
turn on backlight.

Most dsi panels, have five steps when poweron.

1. turn on dsi signal to LP11   --> dsi host's action
2. turn on the power supplies,  --> panel's action
3. send the DCS  cmd to panel   --> panel's action
4. start send video stream  --> dsi host's action
5. turn on backlight.   --> panel's action

we put "turn on the power supplies" and "send the DCS  cmd to panel" in
panel_prepare. And "turn on backlight" in panel_enable.

But some other panels has a special poweron sequence as the following.

1. turn on the power supplies,  --> panel's action
2. turn on dsi signal to LP11   --> dsi host's action
3. send the DCS  cmd to panel   --> panel's action
4. start send video stream  --> dsi host's action
5. turn on backlight.   --> panel's action

panel's actions are divided into three parts.

So I add a new api "drm_panel_prepare_power/rm_panel_unprepare_power" to
control the sequence.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..24f89a1dd421 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -184,6 +184,7 @@ struct mtk_dsi {
struct drm_encoder encoder;
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
+   struct drm_panel *panel;
struct drm_connector *connector;
struct phy *phy;
 
@@ -619,10 +620,18 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
  dsi->lanes);
 
+   if (dsi->panel) {
+   ret = panel_bridge_prepare_power(dsi->next_bridge)
+   if (ret) {
+   DRM_INFO("can't prepare power the panel\n");
+   goto err_refcount;
+   }
+   }
+
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
if (ret < 0) {
dev_err(dev, "Failed to set data rate: %d\n", ret);
-   goto err_refcount;
+   goto err_prepare_power;
}
 
phy_power_on(dsi->phy);
@@ -665,6 +674,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->engine_clk);
 err_phy_power_off:
phy_power_off(dsi->phy);
+err_prepare_power:
+   if (dsi->panel) {
+   if (panel_bridge_unprepare_power(dsi->next_bridge))
+   dev_err(dev, "Can't unprepare power the panel\n");
+   }
 err_refcount:
dsi->refcount--;
return ret;
@@ -698,6 +712,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->digital_clk);
 
phy_power_off(dsi->phy);
+
+   if (dsi->panel) {
+   ret = panel_bridge_unprepare_power(dsi->next_bridge);
+   if (ret)
+   dev_err(dev, "Can't unprepare power the panel 
ret:%d\n", ret);
+   }
 }
 
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
@@ -1001,7 +1021,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 {
struct mtk_dsi *dsi;
struct device *dev = >dev;
-   struct drm_panel *panel;
struct resource *regs;
int irq_num;
int ret;
@@ -1019,12 +1038,12 @@ static int mtk_dsi_probe(struct platform_device *pdev)
}
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
- , >next_bridge);
+ >panel, >next_bridge);
if (ret)
goto err_unregister_host;
 
-   if (panel) {
-   dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
+   if (dsi->panel) {
+   dsi->next_bridge = devm_drm_panel_bridge_add(dev, dsi->panel);
if (IS_ERR(dsi->next_bridge)) {
ret = PTR_ERR(dsi->next_bridge);
goto err_unregister_host;
-- 
2.25.1

[PATCH v2 2/3] drm/panel: boe-tv101wum-n16 seperate the panel power control

[Jitao Shi]

Seperate the panel power control from prepare/unprepare.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 72 +--
 1 file changed, 50 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index db9d0b86d542..dc49079a74d1 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -50,6 +50,7 @@ struct boe_panel {
struct regulator *avdd;
struct gpio_desc *enable_gpio;
 
+   bool prepared_power;
bool prepared;
 };
 
@@ -488,22 +489,13 @@ static int boe_panel_enter_sleep_mode(struct boe_panel 
*boe)
return 0;
 }
 
-static int boe_panel_unprepare(struct drm_panel *panel)
+static int boe_panel_unprepare_power(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
-   int ret;
 
-   if (!boe->prepared)
+   if (!boe->prepared_power)
return 0;
 
-   ret = boe_panel_enter_sleep_mode(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
-   }
-
-   msleep(150);
-
if (boe->desc->discharge_on_disable) {
regulator_disable(boe->avee);
regulator_disable(boe->avdd);
@@ -512,6 +504,7 @@ static int boe_panel_unprepare(struct drm_panel *panel)
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
} else {
+   msleep(150);
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(500, 1000);
regulator_disable(boe->avee);
@@ -520,17 +513,39 @@ static int boe_panel_unprepare(struct drm_panel *panel)
regulator_disable(boe->pp1800);
}
 
+   boe->prepared_power = false;
+
+   return 0;
+}
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   if (!boe->prepared)
+   return 0;
+
+   if (!boe->desc->discharge_on_disable) {
+   ret = boe_panel_enter_sleep_mode(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n",
+   ret);
+   return ret;
+   }
+   }
+
boe->prepared = false;
 
return 0;
 }
 
-static int boe_panel_prepare(struct drm_panel *panel)
+static int boe_panel_prepare_power(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
int ret;
 
-   if (boe->prepared)
+   if (boe->prepared_power)
return 0;
 
gpiod_set_value(boe->enable_gpio, 0);
@@ -558,18 +573,10 @@ static int boe_panel_prepare(struct drm_panel *panel)
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(6000, 1);
 
-   ret = boe_panel_init_dcs_cmd(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to init panel: %d\n", ret);
-   goto poweroff;
-   }
-
-   boe->prepared = true;
+   boe->prepared_power = true;
 
return 0;
 
-poweroff:
-   regulator_disable(boe->avee);
 poweroffavdd:
regulator_disable(boe->avdd);
 poweroff1v8:
@@ -580,6 +587,25 @@ static int boe_panel_prepare(struct drm_panel *panel)
return ret;
 }
 
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   if (boe->prepared)
+   return 0;
+
+   ret = boe_panel_init_dcs_cmd(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to init panel: %d\n", ret);
+   return ret;
+   }
+
+   boe->prepared = true;
+
+   return 0;
+}
+
 static int boe_panel_enable(struct drm_panel *panel)
 {
msleep(130);
@@ -749,7 +775,9 @@ static int boe_panel_get_modes(struct drm_panel *panel,
 
 static const struct drm_panel_funcs boe_panel_funcs = {
.unprepare = boe_panel_unprepare,
+   .unprepare_power = boe_panel_unprepare_power,
.prepare = boe_panel_prepare,
+   .prepare_power = boe_panel_prepare_power,
.enable = boe_panel_enable,
.get_modes = boe_panel_get_modes,
 };
-- 
2.25.1

[PATCH v2 1/3] drm/panel: seperate panel power control from panel prepare/unprepare

[Jitao Shi]

Some dsi panels require the dsi lanes keeping low before panel power
on. So seperate the panel power control and the communication with panel.

And put the power control in drm_panel_prepare_power and
drm_panel_unprepare_power. Put the communication with panel in
drm_panel_prepare and drm_panel_unprepare.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/bridge/panel.c | 17 +++
 drivers/gpu/drm/drm_panel.c| 38 ++
 include/drm/drm_bridge.h   |  2 ++
 include/drm/drm_panel.h| 17 +++
 4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index c916f4b8907e..3a846ac8e24c 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -137,6 +137,23 @@ static int panel_bridge_get_modes(struct drm_bridge 
*bridge,
return drm_panel_get_modes(panel_bridge->panel, connector);
 }
 
+int panel_bridge_prepare_power(struct drm_bridge *bridge)
+{
+   struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+   return drm_panel_prepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_prepare_power);
+
+int panel_bridge_unprepare_power(struct drm_bridge *bridge)
+{
+struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+return drm_panel_unprepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_unprepare_power);
+
+
 static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index f634371c717a..7bb5185db17d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -115,6 +115,24 @@ int drm_panel_prepare(struct drm_panel *panel)
 }
 EXPORT_SYMBOL(drm_panel_prepare);
 
+/**
+ * drm_panel_prepare_power - power on a panel's power
+ * @panel: DRM panel
+ *
+ * Calling this function will enable power and deassert any reset signals to
+ * the panel.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_prepare_power(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->prepare_power)
+   return panel->funcs->prepare_power(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_prepare_power);
+
 /**
  * drm_panel_unprepare - power off a panel
  * @panel: DRM panel
@@ -138,6 +156,26 @@ int drm_panel_unprepare(struct drm_panel *panel)
 }
 EXPORT_SYMBOL(drm_panel_unprepare);
 
+/**
+ * drm_panel_unprepare_power - power off a panel
+ * @panel: DRM panel
+ *
+ * Calling this function will completely power off a panel (assert the panel's
+ * reset, turn off power supplies, ...). After this function has completed, it
+ * is usually no longer possible to communicate with the panel until another
+ * call to drm_panel_prepare_power and drm_panel_prepare().
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_unprepare_power(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->unprepare_power)
+   return panel->funcs->unprepare_power(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_unprepare_power);
+
 /**
  * drm_panel_enable - enable a panel
  * @panel: DRM panel
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index 2195daa289d2..cc94c9da47d8 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -892,6 +892,8 @@ struct drm_bridge *devm_drm_panel_bridge_add_typed(struct 
device *dev,
   struct drm_panel *panel,
   u32 connector_type);
 struct drm_connector *drm_panel_bridge_connector(struct drm_bridge *bridge);
+int panel_bridge_prepare_power(struct drm_bridge *bridge);
+int panel_bridge_unprepare_power(struct drm_bridge *bridge);
 #endif
 
 #endif
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 33605c3f0eba..48e83712ad44 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -68,6 +68,13 @@ enum drm_panel_orientation;
  * functionality to enable/disable backlight.
  */
 struct drm_panel_funcs {
+   /**
+* @prepare_power:
+*
+* Turn on panel power.
+*/
+   int (*prepare_power)(struct drm_panel *panel);
+
/**
 * @prepare:
 *
@@ -115,6 +122,13 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel,
 struct drm_connector *connector);
 
+   /**
+* @unprepare_power:
+*
+* Turn off panel_power.
+*/
+   int (*unprepare_power)(struct drm_panel *panel);
+
/**
 * @get_timings:
 *
@@ -180,6 +194,9 @@ void drm_panel_init(struct drm_panel *panel, s

[PATCH v2 0/3] seperate panel power control from panel prepare/unprepare

[Jitao Shi]

Changes since v1:
 - Fix null point when dsi next bridge isn't a panel.
 - "dsi mmsys reset" is implement by
   https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355

Jitao Shi (3):
  drm/panel: seperate panel power control from panel prepare/unprepare
  drm/panel: boe-tv101wum-n16 seperate the panel power control
  drm/mediatek: fine tune the dsi panel's power sequence

 drivers/gpu/drm/bridge/panel.c| 17 +
 drivers/gpu/drm/drm_panel.c   | 38 ++
 drivers/gpu/drm/mediatek/mtk_dsi.c| 29 ++--
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 72 +--
 include/drm/drm_bridge.h  |  2 +
 include/drm/drm_panel.h   | 17 +
 6 files changed, 148 insertions(+), 27 deletions(-)

-- 
2.25.1

[PATCH v5 2/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

The bridge chip ANX7625 requires the packets on lanes aligned at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..4735e0092ffe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   if (dsi->next_bridge)
+   dsi->force_dsi_end_without_null = 
of_property_read_bool(dsi->next_bridge->of_node,
+   
"force_dsi_end_without_null");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
2.25.1

[PATCH v5 0/2] force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

Changes since v4:
 - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" 
before
   "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".

 - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".


Jitao Shi (2):
  dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null
  drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid
screen shift

 .../bindings/display/bridge/analogix,anx7625.yaml   |  6 ++
 drivers/gpu/drm/mediatek/mtk_dsi.c  | 13 +
 2 files changed, 19 insertions(+)

-- 
2.25.1

[PATCH v5 1/2] dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null

[Jitao Shi]

The force_dsi_end_without_null requires the dsi host ent at
the same time in line.

Signed-off-by: Jitao Shi 
---
 .../bindings/display/bridge/analogix,anx7625.yaml   | 6 ++
 1 file changed, 6 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml 
b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
index ab48ab2f4240..8b868a6a3d60 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
@@ -43,6 +43,11 @@ properties:
   vdd33-supply:
 description: Regulator that provides the supply 3.3V power.
 
+  force_dsi_end_without_null:
+description: |
+  Requires the dsi host send the dsi packets on all lanes aligned
+  at the end.
+
   ports:
 $ref: /schemas/graph.yaml#/properties/ports
 
@@ -87,6 +92,7 @@ examples:
 vdd10-supply = <_mipibrdg>;
 vdd18-supply = <_mipibrdg>;
 vdd33-supply = <_mipibrdg>;
+force_dsi_end_without_null;
 
 ports {
 #address-cells = <1>;
-- 
2.25.1

[PATCH v4 2/2] dt-bindings: mediatek: add force_dsi_end_without_null

[Jitao Shi]

The force_dsi_end_without_null requires the dsi host ent at
the same time in line.

Signed-off-by: Jitao Shi 
---
 .../bindings/display/bridge/analogix,anx7625.yaml   | 6 ++
 1 file changed, 6 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml 
b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
index ab48ab2f4240..8b868a6a3d60 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
@@ -43,6 +43,11 @@ properties:
   vdd33-supply:
 description: Regulator that provides the supply 3.3V power.
 
+  force_dsi_end_without_null:
+description: |
+  Requires the dsi host send the dsi packets on all lanes aligned
+  at the end.
+
   ports:
 $ref: /schemas/graph.yaml#/properties/ports
 
@@ -87,6 +92,7 @@ examples:
 vdd10-supply = <_mipibrdg>;
 vdd18-supply = <_mipibrdg>;
 vdd33-supply = <_mipibrdg>;
+force_dsi_end_without_null;
 
 ports {
 #address-cells = <1>;
-- 
2.25.1

[PATCH v4 1/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

The bridge chip ANX7625 requires the packets on lanes aligned at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..4735e0092ffe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   if (dsi->next_bridge)
+   dsi->force_dsi_end_without_null = 
of_property_read_bool(dsi->next_bridge->of_node,
+   
"force_dsi_end_without_null");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
2.25.1

[PATCH v3 1/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

The bridge chip ANX7625 requires the packets on lanes aligned at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..4735e0092ffe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   if (dsi->next_bridge)
+   dsi->force_dsi_end_without_null = 
of_property_read_bool(dsi->next_bridge->of_node,
+   
"force_dsi_end_without_null");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
2.25.1

[PATCH v3 2/2] dt-bindings: mediatek: add force_dsi_end_without_null for dsi

[Jitao Shi]

Some bridge chip will shift screen when the dsi data does't ent at
the same time in line.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index 8238a86686be..1c2f53f3ac3d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -19,6 +19,10 @@ Required properties:
   Documentation/devicetree/bindings/graph.txt. This port should be connected
   to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
 
+Optional properties:
+- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the
+  packets on lanes aligned at the end.
+
 MIPI TX Configuration Module
 
 
-- 
2.25.1

[PATCH v2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift

[Jitao Shi]

The bridge chip "ANX7625" requires the packets on lanes to aligne at the end,
or ANX7625 will shift the screen.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ae403c67cbd9..4735e0092ffe 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   if (dsi->next_bridge)
+   dsi->force_dsi_end_without_null = 
of_property_read_bool(dsi->next_bridge->of_node,
+   
"force_dsi_end_without_null");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
2.25.1

Re: [PATCH 4/4] drm/mediatek: add dsi module reset driver

[Jitao Shi]

On Sat, 2021-04-24 at 07:50 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2021年4月20日 週二 下午9:26寫道：
> >
> > Reset dsi HW to default when power on. Prevent the setting differet
> > between bootloader and kernel.
> >
> > Signed-off-by: Jitao Shi 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 36 +-
> >  1 file changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 455fe582c6b5..113438ddd4cc 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -7,10 +7,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  #include 
> >  #include 
> > @@ -143,6 +145,8 @@
> >  #define DATA_0 (0xff << 16)
> >  #define DATA_1 (0xff << 24)
> >
> > +#define MMSYS_SW_RST_DSI_B BIT(25)
> > +
> >  #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
> >
> >  #define MTK_DSI_HOST_IS_READ(type) \
> > @@ -186,7 +190,8 @@ struct mtk_dsi {
> > struct drm_bridge *next_bridge;
> > struct drm_connector *connector;
> > struct phy *phy;
> > -
> > +   struct regmap *mmsys_sw_rst_b;
> > +   u32 sw_rst_b;
> > void __iomem *regs;
> >
> > struct clk *engine_clk;
> > @@ -272,6 +277,16 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
> > mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
> >  }
> >
> > +static void mtk_dsi_reset_all(struct mtk_dsi *dsi)
> > +{
> > +   regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
> > +  MMSYS_SW_RST_DSI_B, 0);
> > +   usleep_range(1000, 1100);
> > +
> > +   regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
> > +  MMSYS_SW_RST_DSI_B, MMSYS_SW_RST_DSI_B);
> > +}
> > +
> >  static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
> >  {
> > mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
> > @@ -985,6 +1000,8 @@ static int mtk_dsi_bind(struct device *dev, struct 
> > device *master, void *data)
> >
> > ret = mtk_dsi_encoder_init(drm, dsi);
> >
> > +   mtk_dsi_reset_all(dsi);
> > +
> > return ret;
> >  }
> >
> > @@ -1007,6 +1024,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> > struct device *dev = >dev;
> > struct drm_panel *panel;
> > struct resource *regs;
> > +   struct regmap *regmap;
> > int irq_num;
> > int ret;
> >
> > @@ -1022,6 +1040,22 @@ static int mtk_dsi_probe(struct platform_device 
> > *pdev)
> > return ret;
> > }
> >
> > +   regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
> > +"mediatek,syscon-dsi");
> > +   ret = of_property_read_u32_index(dev->of_node, 
> > "mediatek,syscon-dsi", 1,
> > +>sw_rst_b);
> > +
> > +   if (IS_ERR(regmap))
> > +   ret = PTR_ERR(regmap);
> > +
> > +   if (ret) {
> > +   ret = PTR_ERR(regmap);
> > +   dev_err(dev, "Failed to get mmsys registers: %d\n", ret);
> > +   return ret;
> > +   }
> > +
> > +   dsi->mmsys_sw_rst_b = regmap;
> > +
> 
> It looks like that mtk-mmsys is the reset controller and mtk-dsi is
> reset consumer. Please refer to [1], [2] to implement.
> 
> [1] https://www.kernel.org/doc/html/latest/driver-api/reset.html
> [2] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/reset/reset.txt?h=v5.12-rc8
> 
> Regards,
> Chun-Kuang.
> 

Thanks, I'll fix next version.

> > ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> >   , >next_bridge);
> > if (ret)
> > --
> > 2.25.1
> > ___
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 3/4] drm/mediatek: fine tune the dsi panel's power sequence

[Jitao Shi]

On Sat, 2021-04-24 at 00:36 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2021年4月20日 週二 下午9:26寫道：
> >
> > Add the drm_panel_prepare_power and drm_panel_unprepare_power control.
> > Turn on panel power(drm_panel_prepare_power) and control before dsi
> > enable. And then dsi enable, send dcs cmd in drm_panel_prepare, last
> > turn on backlight.
> 
> Please describe WHY do you need this patch? Fix any bug?

Most panels, have five steps when poweron.

1. turn on dsi signal to LP11   --> dsi host's action
2. turn on the power supplies,  --> panel's action
3. send the DCS  cmd to panel   --> panel's action
4. start send video stream  --> dsi host's action
5. turn on backlight.   --> panel's action

we put "turn on the power supplies" and "send the DCS  cmd to panel" in
panel_prepare. And "turn on backlight" in panel_enable.

But some other panels has a special poweron sequence as the following.

1. turn on the power supplies,  --> panel's action
2. turn on dsi signal to LP11   --> dsi host's action
3. send the DCS  cmd to panel   --> panel's action
4. start send video stream  --> dsi host's action
5. turn on backlight.   --> panel's action

panel's actions are divided into three parts.

So I add a new api "drm_panel_prepare_power/rm_panel_unprepare_power" to
control the sequence.


Best Regards
Jitao

> 
> >
> > Signed-off-by: Jitao Shi 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++--
> >  1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index a1ff152ef468..455fe582c6b5 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -615,10 +615,13 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * 
> > bit_per_pixel,
> >   dsi->lanes);
> >
> > +   if (panel_bridge_prepare_power(dsi->next_bridge))
> 
> ret = panel_bridge_prepare_power(dsi->next_bridge);
> if (ret)
> 
> > +   DRM_INFO("can't prepare power the panel\n");
> 
> I think you should goto err_refcount;

Thanks for your review. I'll fix it next patch.

> 
> > +
> > ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> > if (ret < 0) {
> > dev_err(dev, "Failed to set data rate: %d\n", ret);
> > -   goto err_refcount;
> > +   goto err_prepare_power;
> > }
> >
> > phy_power_on(dsi->phy);
> > @@ -661,7 +664,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> > clk_disable_unprepare(dsi->engine_clk);
> >  err_phy_power_off:
> > phy_power_off(dsi->phy);
> > -err_refcount:
> > +err_prepare_power:
> > +   if (panel_bridge_unprepare_power(dsi->next_bridge))
> 
> ret = panel_bridge_unprepare_power(dsi->next_bridge);
> 
> > +   DRM_INFO("Can't unprepare power the panel\n");
> > dsi->refcount--;
> > return ret;
> >  }
> > @@ -694,6 +699,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> > clk_disable_unprepare(dsi->digital_clk);
> >
> > phy_power_off(dsi->phy);
> > +
> > +   if (panel_bridge_unprepare_power(dsi->next_bridge))
> 
> ret = panel_bridge_unprepare_power(dsi->next_bridge);
> 
> > +   DRM_INFO("Can't unprepare power the panel\n");
> >  }
> >
> >  static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
> > --
> > 2.25.1
> > ___
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 3/4] drm/mediatek: fine tune the dsi panel's power sequence

[Jitao Shi]

Add the drm_panel_prepare_power and drm_panel_unprepare_power control.
Turn on panel power(drm_panel_prepare_power) and control before dsi
enable. And then dsi enable, send dcs cmd in drm_panel_prepare, last
turn on backlight.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index a1ff152ef468..455fe582c6b5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -615,10 +615,13 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
  dsi->lanes);
 
+   if (panel_bridge_prepare_power(dsi->next_bridge))
+   DRM_INFO("can't prepare power the panel\n");
+
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
if (ret < 0) {
dev_err(dev, "Failed to set data rate: %d\n", ret);
-   goto err_refcount;
+   goto err_prepare_power;
}
 
phy_power_on(dsi->phy);
@@ -661,7 +664,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->engine_clk);
 err_phy_power_off:
phy_power_off(dsi->phy);
-err_refcount:
+err_prepare_power:
+   if (panel_bridge_unprepare_power(dsi->next_bridge))
+   DRM_INFO("Can't unprepare power the panel\n");
dsi->refcount--;
return ret;
 }
@@ -694,6 +699,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
clk_disable_unprepare(dsi->digital_clk);
 
phy_power_off(dsi->phy);
+
+   if (panel_bridge_unprepare_power(dsi->next_bridge))
+   DRM_INFO("Can't unprepare power the panel\n");
 }
 
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
-- 
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 1/4] drm/panel: seperate panel power control from panel prepare/unprepare

[Jitao Shi]

Some dsi panels require the dsi lanes keeping low before panel power
on. So seperate the panel power control and the communication with panel.

And put the power control in drm_panel_prepare_power and
drm_panel_unprepare_power. Put the communication with panel in
drm_panel_prepare and drm_panel_unprepare.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/bridge/panel.c | 17 +++
 drivers/gpu/drm/drm_panel.c| 38 ++
 include/drm/drm_bridge.h   |  2 ++
 include/drm/drm_panel.h| 17 +++
 4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 0ddc37551194..a19c96e710fc 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -125,6 +125,23 @@ static int panel_bridge_get_modes(struct drm_bridge 
*bridge,
return drm_panel_get_modes(panel_bridge->panel, connector);
 }
 
+int panel_bridge_prepare_power(struct drm_bridge *bridge)
+{
+   struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+   return drm_panel_prepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_prepare_power);
+
+int panel_bridge_unprepare_power(struct drm_bridge *bridge)
+{
+struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+
+return drm_panel_unprepare_power(panel_bridge->panel);
+}
+EXPORT_SYMBOL(panel_bridge_unprepare_power);
+
+
 static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index f634371c717a..7bb5185db17d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -115,6 +115,24 @@ int drm_panel_prepare(struct drm_panel *panel)
 }
 EXPORT_SYMBOL(drm_panel_prepare);
 
+/**
+ * drm_panel_prepare_power - power on a panel's power
+ * @panel: DRM panel
+ *
+ * Calling this function will enable power and deassert any reset signals to
+ * the panel.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_prepare_power(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->prepare_power)
+   return panel->funcs->prepare_power(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_prepare_power);
+
 /**
  * drm_panel_unprepare - power off a panel
  * @panel: DRM panel
@@ -138,6 +156,26 @@ int drm_panel_unprepare(struct drm_panel *panel)
 }
 EXPORT_SYMBOL(drm_panel_unprepare);
 
+/**
+ * drm_panel_unprepare_power - power off a panel
+ * @panel: DRM panel
+ *
+ * Calling this function will completely power off a panel (assert the panel's
+ * reset, turn off power supplies, ...). After this function has completed, it
+ * is usually no longer possible to communicate with the panel until another
+ * call to drm_panel_prepare_power and drm_panel_prepare().
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_panel_unprepare_power(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->unprepare_power)
+   return panel->funcs->unprepare_power(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+EXPORT_SYMBOL(drm_panel_unprepare_power);
+
 /**
  * drm_panel_enable - enable a panel
  * @panel: DRM panel
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index 2195daa289d2..cc94c9da47d8 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -892,6 +892,8 @@ struct drm_bridge *devm_drm_panel_bridge_add_typed(struct 
device *dev,
   struct drm_panel *panel,
   u32 connector_type);
 struct drm_connector *drm_panel_bridge_connector(struct drm_bridge *bridge);
+int panel_bridge_prepare_power(struct drm_bridge *bridge);
+int panel_bridge_unprepare_power(struct drm_bridge *bridge);
 #endif
 
 #endif
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 33605c3f0eba..48e83712ad44 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -68,6 +68,13 @@ enum drm_panel_orientation;
  * functionality to enable/disable backlight.
  */
 struct drm_panel_funcs {
+   /**
+* @prepare_power:
+*
+* Turn on panel power.
+*/
+   int (*prepare_power)(struct drm_panel *panel);
+
/**
 * @prepare:
 *
@@ -115,6 +122,13 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel,
 struct drm_connector *connector);
 
+   /**
+* @unprepare_power:
+*
+* Turn off panel_power.
+*/
+   int (*unprepare_power)(struct drm_panel *panel);
+
/**
 * @get_timings:
 *
@@ -180,6 +194,9 @@ void drm_panel_init(struct drm_panel *panel, s

[PATCH 4/4] drm/mediatek: add dsi module reset driver

[Jitao Shi]

Reset dsi HW to default when power on. Prevent the setting differet
between bootloader and kernel.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 36 +-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 455fe582c6b5..113438ddd4cc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -7,10 +7,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -143,6 +145,8 @@
 #define DATA_0 (0xff << 16)
 #define DATA_1 (0xff << 24)
 
+#define MMSYS_SW_RST_DSI_B BIT(25)
+
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
 #define MTK_DSI_HOST_IS_READ(type) \
@@ -186,7 +190,8 @@ struct mtk_dsi {
struct drm_bridge *next_bridge;
struct drm_connector *connector;
struct phy *phy;
-
+   struct regmap *mmsys_sw_rst_b;
+   u32 sw_rst_b;
void __iomem *regs;
 
struct clk *engine_clk;
@@ -272,6 +277,16 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 }
 
+static void mtk_dsi_reset_all(struct mtk_dsi *dsi)
+{
+   regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
+  MMSYS_SW_RST_DSI_B, 0);
+   usleep_range(1000, 1100);
+
+   regmap_update_bits(dsi->mmsys_sw_rst_b, dsi->sw_rst_b,
+  MMSYS_SW_RST_DSI_B, MMSYS_SW_RST_DSI_B);
+}
+
 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
@@ -985,6 +1000,8 @@ static int mtk_dsi_bind(struct device *dev, struct device 
*master, void *data)
 
ret = mtk_dsi_encoder_init(drm, dsi);
 
+   mtk_dsi_reset_all(dsi);
+
return ret;
 }
 
@@ -1007,6 +1024,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct drm_panel *panel;
struct resource *regs;
+   struct regmap *regmap;
int irq_num;
int ret;
 
@@ -1022,6 +1040,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
 
+   regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+"mediatek,syscon-dsi");
+   ret = of_property_read_u32_index(dev->of_node, "mediatek,syscon-dsi", 1,
+>sw_rst_b);
+
+   if (IS_ERR(regmap))
+   ret = PTR_ERR(regmap);
+
+   if (ret) {
+   ret = PTR_ERR(regmap);
+   dev_err(dev, "Failed to get mmsys registers: %d\n", ret);
+   return ret;
+   }
+
+   dsi->mmsys_sw_rst_b = regmap;
+
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  , >next_bridge);
if (ret)
-- 
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[PATCH 2/4] drm/panel: boe-tv101wum-n16 seperate the panel power control

[Jitao Shi]

Seperate the panel power control from prepare/unprepare.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 72 +--
 1 file changed, 50 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index db9d0b86d542..dc49079a74d1 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -50,6 +50,7 @@ struct boe_panel {
struct regulator *avdd;
struct gpio_desc *enable_gpio;
 
+   bool prepared_power;
bool prepared;
 };
 
@@ -488,22 +489,13 @@ static int boe_panel_enter_sleep_mode(struct boe_panel 
*boe)
return 0;
 }
 
-static int boe_panel_unprepare(struct drm_panel *panel)
+static int boe_panel_unprepare_power(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
-   int ret;
 
-   if (!boe->prepared)
+   if (!boe->prepared_power)
return 0;
 
-   ret = boe_panel_enter_sleep_mode(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
-   }
-
-   msleep(150);
-
if (boe->desc->discharge_on_disable) {
regulator_disable(boe->avee);
regulator_disable(boe->avdd);
@@ -512,6 +504,7 @@ static int boe_panel_unprepare(struct drm_panel *panel)
usleep_range(5000, 7000);
regulator_disable(boe->pp1800);
} else {
+   msleep(150);
gpiod_set_value(boe->enable_gpio, 0);
usleep_range(500, 1000);
regulator_disable(boe->avee);
@@ -520,17 +513,39 @@ static int boe_panel_unprepare(struct drm_panel *panel)
regulator_disable(boe->pp1800);
}
 
+   boe->prepared_power = false;
+
+   return 0;
+}
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   if (!boe->prepared)
+   return 0;
+
+   if (!boe->desc->discharge_on_disable) {
+   ret = boe_panel_enter_sleep_mode(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n",
+   ret);
+   return ret;
+   }
+   }
+
boe->prepared = false;
 
return 0;
 }
 
-static int boe_panel_prepare(struct drm_panel *panel)
+static int boe_panel_prepare_power(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
int ret;
 
-   if (boe->prepared)
+   if (boe->prepared_power)
return 0;
 
gpiod_set_value(boe->enable_gpio, 0);
@@ -558,18 +573,10 @@ static int boe_panel_prepare(struct drm_panel *panel)
gpiod_set_value(boe->enable_gpio, 1);
usleep_range(6000, 1);
 
-   ret = boe_panel_init_dcs_cmd(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to init panel: %d\n", ret);
-   goto poweroff;
-   }
-
-   boe->prepared = true;
+   boe->prepared_power = true;
 
return 0;
 
-poweroff:
-   regulator_disable(boe->avee);
 poweroffavdd:
regulator_disable(boe->avdd);
 poweroff1v8:
@@ -580,6 +587,25 @@ static int boe_panel_prepare(struct drm_panel *panel)
return ret;
 }
 
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+   struct boe_panel *boe = to_boe_panel(panel);
+   int ret;
+
+   if (boe->prepared)
+   return 0;
+
+   ret = boe_panel_init_dcs_cmd(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to init panel: %d\n", ret);
+   return ret;
+   }
+
+   boe->prepared = true;
+
+   return 0;
+}
+
 static int boe_panel_enable(struct drm_panel *panel)
 {
msleep(130);
@@ -749,7 +775,9 @@ static int boe_panel_get_modes(struct drm_panel *panel,
 
 static const struct drm_panel_funcs boe_panel_funcs = {
.unprepare = boe_panel_unprepare,
+   .unprepare_power = boe_panel_unprepare_power,
.prepare = boe_panel_prepare,
+   .prepare_power = boe_panel_prepare_power,
.enable = boe_panel_enable,
.get_modes = boe_panel_get_modes,
 };
-- 
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[PATCH] drm/mediatek: force hsa hsa hfp packets multiple of line num to avoid screen shift

[Jitao Shi]

The bridge chip ANX7625 require the line packets ending at the sametime
or ANX7625 will shift the screen.

Change-Id: Ia324ad28fbff54140feedb9a1d6bfb2b246d0447
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index a1ff152ef468..e825a80862de 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,8 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   /* force dsi line end without dsi_null data */
+   bool force_dsi_end_without_null;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -495,6 +497,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
 
+   if (dsi->force_dsi_end_without_null) {
+   horizontal_sync_active_byte = 
roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+   horizontal_frontporch_byte = 
roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+   horizontal_backporch_byte = roundup(horizontal_backporch_byte, 
dsi->lanes) - 2;
+   horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 
2) % dsi->lanes;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -1091,6 +1100,9 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->bridge.of_node = dev->of_node;
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
+   dsi->force_dsi_end_without_null = of_property_read_bool(dev->of_node,
+   
"force_dsi_end_without_null");
+
drm_bridge_add(>bridge);
 
ret = component_add(>dev, _dsi_component_ops);
-- 
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[PATCH 1/3] drm/mediatek: dpi dual edge sample mode support

[Jitao Shi]

DPI can sample on falling, rising or both edge.
When DPI sample the data both rising and falling edge.
It can reduce half data io pins.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ccd681a2a4c2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -81,6 +81,7 @@ struct mtk_dpi {
struct pinctrl *pinctrl;
struct pinctrl_state *pins_gpio;
struct pinctrl_state *pins_dpi;
+   bool ddr_edge_sel;
int refcount;
 };
 
@@ -119,6 +120,7 @@ struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
bool edge_sel_en;
+   bool dual_edge;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -378,6 +380,15 @@ static void mtk_dpi_config_color_format(struct mtk_dpi 
*dpi,
}
 }
 
+static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
+{
+   if (dpi->conf->dual_edge) {
+   mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+   mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->ddr_edge_sel ? 
EDGE_SEL : 0, EDGE_SEL);
+   }
+}
+
 static void mtk_dpi_power_off(struct mtk_dpi *dpi)
 {
if (WARN_ON(dpi->refcount == 0))
@@ -516,6 +527,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
+   mtk_dpi_dual_edge(dpi);
mtk_dpi_config_disable_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
 
-- 
2.12.5
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[PATCH 0/3] mt8183 dpi supports dual edge

[Jitao Shi]

DPI can sample on falling, rising or both edge.
When DPI sample the data both rising and falling edge.
It can reduce half data io pins.

Jitao Shi (3):
  drm/mediatek: dpi dual edge sample mode support
  drm/mediatek: config mt8183 driver data to support dual edge sample
  drm/mediatek: dpi: add bus format negociation

 drivers/gpu/drm/mediatek/mtk_dpi.c | 109 +++--
 1 file changed, 104 insertions(+), 5 deletions(-)

-- 
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[PATCH 2/3] drm/mediatek: config mt8183 driver data to support dual edge sample

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ccd681a2a4c2..87bb27649c4c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -696,6 +696,7 @@ static const struct mtk_dpi_conf mt2701_conf = {
 static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .dual_edge = true,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
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[PATCH 3/3] drm/mediatek: dpi: add bus format negociation

[Jitao Shi]

Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
the possible output and input formats for the current mode and monitor,
and use the negotiated formats in a basic atomic_check callback.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 96 --
 1 file changed, 91 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 87bb27649c4c..4e45d1b01b0c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -81,6 +81,8 @@ struct mtk_dpi {
struct pinctrl *pinctrl;
struct pinctrl_state *pins_gpio;
struct pinctrl_state *pins_dpi;
+   unsigned int in_bus_format;
+   unsigned int out_bus_format;
bool ddr_edge_sel;
int refcount;
 };
@@ -534,6 +536,92 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
return 0;
 }
 
+#define MAX_OUTPUT_SEL_FORMATS 2
+
+static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge 
*bridge,
+   struct drm_bridge_state *bridge_state,
+   struct drm_crtc_state *crtc_state,
+   struct drm_connector_state *conn_state,
+   unsigned int *num_output_fmts)
+{
+   struct drm_display_mode *mode = _state->mode;
+   u32 *output_fmts;
+   struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+   *num_output_fmts = 0;
+
+   output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
+ GFP_KERNEL);
+   if (!output_fmts)
+   return NULL;
+
+   /* Default 8bit RGB fallback */
+   if (dpi->conf->dual_edge) {
+   output_fmts[0] =  MEDIA_BUS_FMT_RGB888_2X12_LE;
+   output_fmts[1] =  MEDIA_BUS_FMT_RGB888_2X12_BE;
+   *num_output_fmts = 2;
+   } else {
+   output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;
+   *num_output_fmts = 1;
+   }
+
+   return output_fmts;
+}
+
+#define MAX_INPUT_SEL_FORMATS  1
+
+static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+   struct drm_bridge_state *bridge_state,
+   struct drm_crtc_state *crtc_state,
+   struct drm_connector_state *conn_state,
+   u32 output_fmt,
+   unsigned int *num_input_fmts)
+{
+   u32 *input_fmts;
+
+   *num_input_fmts = 0;
+
+   input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
+GFP_KERNEL);
+   if (!input_fmts)
+   return NULL;
+
+   *num_input_fmts = 1;
+   input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+
+   return input_fmts;
+}
+
+static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
+  struct drm_bridge_state *bridge_state,
+  struct drm_crtc_state *crtc_state,
+  struct drm_connector_state *conn_state)
+{
+   struct mtk_dpi *dpi = bridge->driver_private;
+
+   dpi->out_bus_format = bridge_state->output_bus_cfg.format;
+
+   dpi->in_bus_format = bridge_state->input_bus_cfg.format;
+
+   dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
+   bridge_state->input_bus_cfg.format,
+   bridge_state->output_bus_cfg.format);
+
+   if (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE ||
+   dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_BE) {
+   dpi->ddr_edge_sel =
+   (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ?
+true : false;
+   }
+
+   dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
+   dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
+   dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
+   dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
+
+   return 0;
+}
+
 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
 enum drm_bridge_attach_flags flags)
 {
@@ -572,6 +660,9 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = 
{
.mode_set = mtk_dpi_bridge_mode_set,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
+   .atomic_check = mtk_dpi_bridge_atomic_check,
+   .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
+   .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
 };
 
 static void mtk_dpi_start(struct mtk_ddp_comp *comp)
@@ -621,11 +712,6 @@ static int mtk_dpi_bind(struct device *dev, struct device 
*master, void *data)
goto err_cleanup;
  

[PATCH v3 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..f6f71eb67ff1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,12 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
 };
 
+static const struct mtk_dpi_conf mt8192_conf = {
+   .cal_factor = mt8183_calculate_factor,
+   .reg_h_fre_con = 0xe0,
+   .max_clock_khz = 15,
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -837,6 +843,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
  .data = _conf,
},
+   { .compatible = "mediatek,mt8192-dpi",
+ .data = _conf,
+   },
{ },
 };
 
-- 
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[PATCH v3 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

[Jitao Shi]

Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 6cdb734c91a9..2f566f19e6e0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
   - mediatek,mt7623-dpi
   - mediatek,mt8173-dpi
   - mediatek,mt8183-dpi
+  - mediatek,mt8192-dpi
 
   reg:
 maxItems: 1
-- 
2.25.1
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[PATCH v3 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid

[Jitao Shi]

Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
 struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+   u32 max_clock_khz;
bool edge_sel_en;
 };
 
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge 
*bridge)
mtk_dpi_set_display_mode(dpi, >mode);
 }
 
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+   struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+   if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+   return MODE_CLOCK_HIGH;
+
+   return MODE_OK;
+}
+
 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+   .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
 };
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
 static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 30,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+   .max_clock_khz = 15,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 10,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
2.25.1
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[PATCH v3 0/3] Add check for max clock rate in mode_valid

[Jitao Shi]

Changes since v2:
 - add const struct drm_display_info *info in mtk_dpi_bridge_mode_valid

Jitao Shi (3):
  drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
  drm/mediatek: mtk_dpi: Add dpi config for mt8192
  dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

 .../display/mediatek/mediatek,dpi.yaml|  1 +
 drivers/gpu/drm/mediatek/mtk_dpi.c| 26 +++
 2 files changed, 27 insertions(+)

-- 
2.25.1
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[PATCH v2 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

[Jitao Shi]

Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 6cdb734c91a9..2f566f19e6e0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
   - mediatek,mt7623-dpi
   - mediatek,mt8173-dpi
   - mediatek,mt8183-dpi
+  - mediatek,mt8192-dpi
 
   reg:
 maxItems: 1
-- 
2.25.1
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[PATCH v2 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..f6f71eb67ff1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,12 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
 };
 
+static const struct mtk_dpi_conf mt8192_conf = {
+   .cal_factor = mt8183_calculate_factor,
+   .reg_h_fre_con = 0xe0,
+   .max_clock_khz = 15,
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -837,6 +843,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
  .data = _conf,
},
+   { .compatible = "mediatek,mt8192-dpi",
+ .data = _conf,
+   },
{ },
 };
 
-- 
2.25.1
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[PATCH v2 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid

[Jitao Shi]

Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
 struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+   u32 max_clock_khz;
bool edge_sel_en;
 };
 
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge 
*bridge)
mtk_dpi_set_display_mode(dpi, >mode);
 }
 
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+   struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+   if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+   return MODE_CLOCK_HIGH;
+
+   return MODE_OK;
+}
+
 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+   .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
 };
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
 static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 30,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+   .max_clock_khz = 15,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 10,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
2.25.1
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[PATCH v2 0/3] Add check for max clock rate in mode_valid

[Jitao Shi]

Changes since v1:
 - fix build err.

Jitao Shi (3):
  drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
  drm/mediatek: mtk_dpi: Add dpi config for mt8192
  dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

 .../display/mediatek/mediatek,dpi.yaml|  1 +
 drivers/gpu/drm/mediatek/mtk_dpi.c| 26 +++
 2 files changed, 27 insertions(+)

-- 
2.25.1
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[PATCH 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid

[Jitao Shi]

Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 52f11a63a330..ffa4a0f1989f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit {
 struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
+   u32 max_clock_khz;
bool edge_sel_en;
 };
 
@@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge 
*bridge)
mtk_dpi_set_display_mode(dpi, >mode);
 }
 
+static enum drm_mode_status
+mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode)
+{
+   struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+   if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz)
+   return MODE_CLOCK_HIGH;
+
+   return MODE_OK;
+}
+
 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
.attach = mtk_dpi_bridge_attach,
.mode_set = mtk_dpi_bridge_mode_set,
+   .mode_valid = mtk_dpi_bridge_mode_valid,
.disable = mtk_dpi_bridge_disable,
.enable = mtk_dpi_bridge_enable,
 };
@@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock)
 static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 30,
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
.cal_factor = mt2701_calculate_factor,
.reg_h_fre_con = 0xb0,
.edge_sel_en = true,
+   .max_clock_khz = 15,
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
+   .max_clock_khz = 10,
 };
 
 static int mtk_dpi_probe(struct platform_device *pdev)
-- 
2.25.1
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[PATCH 2/3] drm/mediatek: mtk_dpi: Add dpi config for mt8192

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ffa4a0f1989f..b7905f3f4d1b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -703,6 +703,13 @@ static const struct mtk_dpi_conf mt8183_conf = {
.max_clock_khz = 10,
 };
 
+static const struct mtk_dpi_conf mt8192_conf = {
+   .cal_factor = mt8183_calculate_factor,
+   .reg_h_fre_con = 0xe0,
+   .dual_edge = true,
+   .max_clock_khz = 15,
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -837,6 +844,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8183-dpi",
  .data = _conf,
},
+   { .compatible = "mediatek,mt8192-dpi",
+ .data = _conf,
+   },
{ },
 };
 
-- 
2.25.1
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[PATCH 3/3] dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

[Jitao Shi]

Add compatible "mediatek,mt8192-dpi" for the mt8192 dpi.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 6cdb734c91a9..2f566f19e6e0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -22,6 +22,7 @@ properties:
   - mediatek,mt7623-dpi
   - mediatek,mt8173-dpi
   - mediatek,mt8183-dpi
+  - mediatek,mt8192-dpi
 
   reg:
 maxItems: 1
-- 
2.25.1
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[PATCH 0/3] Add check for max clock rate in mode_valid

[Jitao Shi]

Jitao Shi (3):
  drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid
  drm/mediatek: mtk_dpi: Add dpi config for mt8192
  dt-bindings: mediatek,dpi: add mt8192 to mediatek,dpi

 .../display/mediatek/mediatek,dpi.yaml|  1 +
 drivers/gpu/drm/mediatek/mtk_dpi.c| 27 +++
 2 files changed, 28 insertions(+)

-- 
2.25.1
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[PATCH] drm/mediatek: fine tune the data lane trail by project dts

[Jitao Shi]

Some panels or bridges require customized hs_da_trail time.
So add a property in devicetree for this panels and bridges.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 8c70ec39bfe1..6e7092fa2fee 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,7 @@ struct mtk_dsi {
struct clk *hs_clk;
 
u32 data_rate;
+   u32 da_trail_delta;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
 timing->da_hs_prepare;
-   timing->da_hs_trail = timing->da_hs_prepare + 1;
+   timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
 
timing->ta_go = 4 * timing->lpx - 2;
timing->ta_sure = timing->lpx + 2;
@@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
goto err_unregister_host;
}
 
+   ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
+>da_trail_delta);
+   if (ret) {
+   dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n", 
ret);
+   dsi->da_trail_delta = 0;
+   }
+
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
-- 
2.12.5
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[PATCH v2 0/2] Fix EoTp flag

[Jitao Shi]

Changes since v1:
 - Seperate the line time as single patch.

Jitao Shi (2):
  drm/mediatek: dsi: Fix EoTp flag
  drm/mediatek: dsi: fine tune the line time cause by EOTp

 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

-- 
2.12.5
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[PATCH v2 2/2] drm/mediatek: dsi: fine tune the line time cause by EOTp

[Jitao Shi]

Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2bc46f2350f1..8c70ec39bfe1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -481,6 +481,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
  timing->da_hs_zero + timing->da_hs_exit + 3;
 
delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
+   delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0;
 
horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
horizontal_front_back_byte = horizontal_frontporch_byte + 
horizontal_backporch_byte;
-- 
2.12.5
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[PATCH v2 1/2] drm/mediatek: dsi: Fix EoTp flag

[Jitao Shi]

SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 65fd99c528af..2bc46f2350f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -401,8 +401,11 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
break;
}
 
-   tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
-   tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+   if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+   tmp_reg |= HSTX_CKLP_EN;
+
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   tmp_reg |= DIS_EOT;
 
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 }
-- 
2.12.5
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[PATCH] drm/mediatek: dsi: Fix EoTp flag

[Jitao Shi]

SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.

Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 65fd99c528af..8c70ec39bfe1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -401,8 +401,11 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
break;
}
 
-   tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
-   tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+   if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+   tmp_reg |= HSTX_CKLP_EN;
+
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   tmp_reg |= DIS_EOT;
 
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 }
@@ -478,6 +481,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
  timing->da_hs_zero + timing->da_hs_exit + 3;
 
delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
+   delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0;
 
horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
horizontal_front_back_byte = horizontal_frontporch_byte + 
horizontal_backporch_byte;
-- 
2.25.1
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[PATCH] drm/mediatek: dsi: Use IRQF_TRIGGER_NONE for dsi irq trigger type

[Jitao Shi]

The interrupt trigger is already set by OF. When do devm_request_irq()
in driver, please use IRQF_TRIGGER_NONE and don't specify trigger type
again.

Change-Id: Ie59d7bd9a44a130420890b169cc2e6fee3ad7633
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 4a188a942c38..1d6248930bdf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1128,9 +1128,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
goto err_unregister_host;
}
 
-   irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
ret = devm_request_irq(>dev, irq_num, mtk_dsi_irq,
-  IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
+  IRQF_TRIGGER_NONE, dev_name(>dev), dsi);
if (ret) {
dev_err(>dev, "failed to request mediatek dsi irq\n");
goto err_unregister_host;
-- 
2.12.5
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[PATCH v5 0/1] fix scrolling of panel with small hfp or hbp

[Jitao Shi]

Changes since v4:
 - Merge revert path and fixup patch to on patch

Changes since v3:
 - Revert v2, for v2 will cause some bridge ic no output. the cause
   the video linetime doesn't match display mode from get mode.
 - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte
   are > 0.

Jitao Shi (1):
  drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

 drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++---
 1 file changed, 25 insertions(+), 40 deletions(-)

-- 
2.12.5
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[PATCH v5 1/1] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.

if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++---
 1 file changed, 25 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80b7a082e874..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   u32 delta;
struct mtk_phy_timing *timing = >phy_timing;
 
struct videomode *vm = >vm;
@@ -466,50 +467,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-   horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
+   horizontal_backporch_byte =
+   (vm->hback_porch * dsi_tmp_buf_bpp - 10);
else
-   horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
-   dsi_tmp_buf_bpp;
+   horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
+   dsi_tmp_buf_bpp - 10);
 
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit;
-
-   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 18) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-
-   horizontal_backporch_byte =
-   horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+ timing->da_hs_zero + timing->da_hs_exit + 3;
+
+   delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+   if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+   data_phy_cycles * dsi->lanes + delta) {
+   horizontal_frontporch_byte =
+   vm->hfront_porch * dsi_tmp_buf_bpp -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hfront_porch /
+   (vm->hfront_porch + vm->hback_porch);
+
+   horizontal_backporch_byte =
+   horizontal_backporch_byte -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hback_porch /
+   (vm->hfront_porch + vm->hback_porch);
} else {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 12) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   horizontal_backporch_byte = horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+   DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+   horizontal_frontporch_byte = vm->hfr

Re: [v4 PATCH 0/2] fix scrolling of panel with small hfp or hbp

[Jitao Shi]

On Mon, 2020-10-12 at 23:22 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2020年10月10日 週六 下午3:09寫道：
> >
> > Changes since v3:
> >  - Revert v2, for v2 will cause some bridge ic no output. the cause
> >the video linetime doesn't match display mode from get mode.
> >  - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte
> >are > 0.
> 
> Because v2 is merged into mainline, I think you should merge 1/2 and
> 2/2 to one patch which fix the problem caused by v2.
> 
> Regards,
> Chun-Kuang.
> 

Thanks for your reviewing.
I'll update next version.

Best Regards
Jitao

> >
> > Jitao Shi (2):
> >   Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or
> > hbp"
> >   drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
> >
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 65 
> > +++---
> >  1 file changed, 25 insertions(+), 40 deletions(-)
> >
> > --
> > 2.12.5
> > ___
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

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[PATCH v4 2/2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.

if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 54 ++
 1 file changed, 19 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 16fd99dcdacf..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   u32 delta;
struct mtk_phy_timing *timing = >phy_timing;
 
struct videomode *vm = >vm;
@@ -475,42 +476,25 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
  timing->da_hs_zero + timing->da_hs_exit + 3;
 
-   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 18) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-
-   horizontal_backporch_byte =
-   horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+   delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+   if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+   data_phy_cycles * dsi->lanes + delta) {
+   horizontal_frontporch_byte =
+   vm->hfront_porch * dsi_tmp_buf_bpp -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hfront_porch /
+   (vm->hfront_porch + vm->hback_porch);
+
+   horizontal_backporch_byte =
+   horizontal_backporch_byte -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hback_porch /
+   (vm->hfront_porch + vm->hback_porch);
} else {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 12) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   horizontal_backporch_byte = horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+   DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+   horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
}
 
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
-- 
2.12.5
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[PATCH v4 1/2] Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or hbp"

[Jitao Shi]

This reverts commit 35bf948f1edbf507f6e57e0879fa6ea36d2d2930.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80b7a082e874..16fd99dcdacf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -466,13 +466,14 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-   horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
+   horizontal_backporch_byte =
+   (vm->hback_porch * dsi_tmp_buf_bpp - 10);
else
-   horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
-   dsi_tmp_buf_bpp;
+   horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
+   dsi_tmp_buf_bpp - 10);
 
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit;
+ timing->da_hs_zero + timing->da_hs_exit + 3;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-- 
2.12.5
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[v4 PATCH 0/2] fix scrolling of panel with small hfp or hbp

[Jitao Shi]

Changes since v3:
 - Revert v2, for v2 will cause some bridge ic no output. the cause
   the video linetime doesn't match display mode from get mode.
 - Make sure the horizontal_frontporch_byte and horizontal_backporch_byte
   are > 0.

Jitao Shi (2):
  Revert "drm/mediatek: dsi: Fix scrolling of panel with small hfp or
hbp"
  drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

 drivers/gpu/drm/mediatek/mtk_dsi.c | 65 +++---
 1 file changed, 25 insertions(+), 40 deletions(-)

-- 
2.12.5
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[v2 PATCH] dt-bindings: display: mediatek: convert the dpi bindings to yaml

[Jitao Shi]

Convert display/mediatek/mediatek,dpi.txt to display/mediatek/mediatek,dpi.yaml
and remove the old text bindings.

Signed-off-by: Jitao Shi 
---
 .../bindings/display/mediatek/mediatek,dpi.txt | 42 --
 .../bindings/display/mediatek/mediatek,dpi.yaml| 97 ++
 2 files changed, 97 insertions(+), 42 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
-  the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
-  Documentation/devicetree/bindings/graph.txt. This port should be connected
-  to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
-   compatible = "mediatek,mt8173-dpi";
-   reg = <0 0x1401d000 0 0x1000>;
-   interrupts = ;
-   clocks = < CLK_MM_DPI_PIXEL>,
-< CLK_MM_DPI_ENGINE>,
-< CLK_APMIXED_TVDPLL>;
-   clock-names = "pixel", "engine", "pll";
-   pinctrl-names = "default", "sleep";
-   pinctrl-0 = <_pin_func>;
-   pinctrl-1 = <_pin_idle>;
-
-   port {
-   dpi0_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-};
diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..4de08bc46fb3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+  - CK Hu 
+  - Jitao shi 
+
+description: |
+  The Mediatek DPI function block is a sink of the display subsystem and
+  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+  output bus.
+
+properties:
+  compatible:
+enum:
+  - mediatek,mt2701-dpi
+  - mediatek,mt8173-dpi
+  - mediatek,mt8183-dpi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Pixel Clock
+  - description: Engine Clock
+  - description: DPI PLL
+
+  clock-names:
+items:
+  - const: pixel
+  - const: engine
+  - const: pll
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+items:
+  - const: default
+  - const: sleep
+
+  port:
+type: object
+description:
+  Output port node with endpoint definitions as described in
+  Documentation/devicetree/bindings/graph.txt. This port should be 
connected
+  to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+  endpoint:
+type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0x1401d000 0x1000>;
+interrupts = ;
+clocks = < CLK_MM_DPI_PIXEL>,
+ < CLK_MM_DPI_ENGINE>,
+ < CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <_pin_func>;
+pinctrl-1 = <_pin_idle>;
+
+port {
+dpi0_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+...
-- 
2.12.5
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[v3 PATCH] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

Replace horizontal_backporch_byte with vm->hback_porch * bpp to aovid
flowing judgement negative number.

if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
data_phy_cycles * dsi->lanes + delta)

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 54 ++
 1 file changed, 19 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 16fd99dcdacf..f69ebeaf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -445,6 +445,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   u32 delta;
struct mtk_phy_timing *timing = >phy_timing;
 
struct videomode *vm = >vm;
@@ -475,42 +476,25 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
  timing->da_hs_zero + timing->da_hs_exit + 3;
 
-   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 18) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-
-   horizontal_backporch_byte =
-   horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 18) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+   delta = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ? 18 : 12;
+
+   if ((vm->hfront_porch * dsi_tmp_buf_bpp + horizontal_backporch_byte) >
+   data_phy_cycles * dsi->lanes + delta) {
+   horizontal_frontporch_byte =
+   vm->hfront_porch * dsi_tmp_buf_bpp -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hfront_porch /
+   (vm->hfront_porch + vm->hback_porch);
+
+   horizontal_backporch_byte =
+   horizontal_backporch_byte -
+   (data_phy_cycles * dsi->lanes + delta) *
+   vm->hback_porch /
+   (vm->hfront_porch + vm->hback_porch);
} else {
-   if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-   data_phy_cycles * dsi->lanes + 12) {
-   horizontal_frontporch_byte =
-   vm->hfront_porch * dsi_tmp_buf_bpp -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hfront_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   horizontal_backporch_byte = horizontal_backporch_byte -
-   (data_phy_cycles * dsi->lanes + 12) *
-   vm->hback_porch /
-   (vm->hfront_porch + vm->hback_porch);
-   } else {
-   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
-   horizontal_frontporch_byte = vm->hfront_porch *
-dsi_tmp_buf_bpp;
-   }
+   DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
+   horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
}
 
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
-- 
2.12.5
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Re: [PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

On Tue, 2020-08-18 at 07:42 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2020年8月17日 週一 下午9:07寫道：
> >
> > horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
> > So remove the wrong subtraction 10.
> >
> > Signed-off-by: Jitao Shi 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
> >  1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 270bf22c98fe..5d031e634571 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi 
> > *dsi)
> > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 
> > 10);
> 
> So this subtraction 10 is correct?
> 
> Regards,
> Chun-Kuang.
> 

Yes, It is right.

In the cea861 and dmt spec the mini hsync is 40 pixels.
So the vm->hsync_len * dsi_tmp_buf_bpp >= 120 > 10

Best Regards
jitao
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > -   horizontal_backporch_byte =
> > -   (vm->hback_porch * dsi_tmp_buf_bpp - 10);
> > +   horizontal_backporch_byte = vm->hback_porch * 
> > dsi_tmp_buf_bpp;
> > else
> > -   horizontal_backporch_byte = ((vm->hback_porch + 
> > vm->hsync_len) *
> > -   dsi_tmp_buf_bpp - 10);
> > +   horizontal_backporch_byte = (vm->hback_porch + 
> > vm->hsync_len) *
> > +   dsi_tmp_buf_bpp;
> >
> > data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > - timing->da_hs_zero + timing->da_hs_exit + 3;
> > + timing->da_hs_zero + timing->da_hs_exit;
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
> > --
> > 2.12.5
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

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[PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
So remove the wrong subtraction 10.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 270bf22c98fe..5d031e634571 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-   horizontal_backporch_byte =
-   (vm->hback_porch * dsi_tmp_buf_bpp - 10);
+   horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
else
-   horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
-   dsi_tmp_buf_bpp - 10);
+   horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
+   dsi_tmp_buf_bpp;
 
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit + 3;
+ timing->da_hs_zero + timing->da_hs_exit;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
-- 
2.12.5
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[PATCH] drm/panel: Fix auo, kd101n80-45na horizontal noise on edges of panel

[Jitao Shi]

Fine tune the HBP and HFP to avoid the dot noise on the left and right edges.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 48a164257d18..3edb33e61908 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -615,9 +615,9 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
 static const struct drm_display_mode auo_kd101n80_45na_default_mode = {
.clock = 157000,
.hdisplay = 1200,
-   .hsync_start = 1200 + 80,
-   .hsync_end = 1200 + 80 + 24,
-   .htotal = 1200 + 80 + 24 + 36,
+   .hsync_start = 1200 + 60,
+   .hsync_end = 1200 + 60 + 24,
+   .htotal = 1200 + 60 + 24 + 56,
.vdisplay = 1920,
.vsync_start = 1920 + 16,
.vsync_end = 1920 + 16 + 4,
-- 
2.25.1
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[v2 PATCH] drm/panel: auo, b116xw03: fix flash backlight when power on

[Jitao Shi]

Delay the backlight on to make sure the video stable.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/panel-simple.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 3ad828eaefe1..61781ffa7840 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -724,6 +724,7 @@ static const struct drm_display_mode auo_b116xw03_mode = {
.vsync_end = 768 + 10 + 12,
.vtotal = 768 + 10 + 12 + 6,
.vrefresh = 60,
+   .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 };
 
 static const struct panel_desc auo_b116xw03 = {
@@ -734,6 +735,12 @@ static const struct panel_desc auo_b116xw03 = {
.width = 256,
.height = 144,
},
+   .delay = {
+   .enable = 400,
+   },
+   .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
+   .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+   .connector_type = DRM_MODE_CONNECTOR_eDP,
 };
 
 static const struct drm_display_mode auo_b133xtn01_mode = {
-- 
2.25.1
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Re: [PATCH] drm/panel: auo,b116xw03: fix flash backlight when power on

[Jitao Shi]

On Sun, 2020-07-05 at 10:06 +0200, Sam Ravnborg wrote:
> Hi Jitao.
> 
> On Fri, Jul 03, 2020 at 05:51:13PM +0800, Jitao Shi wrote:
> > Delay the backlight on to make sure the video stable.
> > 
> > Signed-off-by: Jitao Shi 
> > ---
> >  drivers/gpu/drm/panel/panel-simple.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> > b/drivers/gpu/drm/panel/panel-simple.c
> > index 3ad828eaefe1..18f34f286d3d 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -734,6 +734,9 @@ static const struct panel_desc auo_b116xw03 = {
> > .width = 256,
> > .height = 144,
> > },
> > +   .delay = {
> > +   .enable = 400,
> > +   },
> >  };
> >  
> >  static const struct drm_display_mode auo_b133xtn01_mode = {
> 
> Patch did not apply to drm-misc-next.
> Please update - and when you do so also add:
> .bus_flags
> .bus_format
> .connector_type
> 
> So we have this panel properly defined.
> 
>   Sam

Thanks for your review.
I'll add those next version.

Jitao
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[PATCH] drm/panel: auo,b116xw03: fix flash backlight when power on

[Jitao Shi]

Delay the backlight on to make sure the video stable.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/panel-simple.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 3ad828eaefe1..18f34f286d3d 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -734,6 +734,9 @@ static const struct panel_desc auo_b116xw03 = {
.width = 256,
.height = 144,
},
+   .delay = {
+   .enable = 400,
+   },
 };
 
 static const struct drm_display_mode auo_b133xtn01_mode = {
-- 
2.25.1
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[PATCH v16 1/1] dt-bindings: display: mediatek: convert the dpi bindings to yaml

[Jitao Shi]

Convert display/mediatek/mediatek,dpi.txt to display/mediatek/mediatek,dpi.yaml
and remove the old text bindings.

Signed-off-by: Jitao Shi 
---
 .../display/mediatek/mediatek,dpi.txt | 42 
 .../display/mediatek/mediatek,dpi.yaml| 97 +++
 2 files changed, 97 insertions(+), 42 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
-  the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
-  Documentation/devicetree/bindings/graph.txt. This port should be connected
-  to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
-   compatible = "mediatek,mt8173-dpi";
-   reg = <0 0x1401d000 0 0x1000>;
-   interrupts = ;
-   clocks = < CLK_MM_DPI_PIXEL>,
-< CLK_MM_DPI_ENGINE>,
-< CLK_APMIXED_TVDPLL>;
-   clock-names = "pixel", "engine", "pll";
-   pinctrl-names = "default", "sleep";
-   pinctrl-0 = <_pin_func>;
-   pinctrl-1 = <_pin_idle>;
-
-   port {
-   dpi0_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-};
diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..860b719b5dc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+  - CK Hu 
+  - Jitao shi 
+
+description: |
+  The Mediatek DPI function block is a sink of the display subsystem and
+  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+  output bus.
+
+properties:
+  compatible:
+enum:
+  - mediatek,mt2701-dpi
+  - mediatek,mt8173-dpi
+  - mediatek,mt8183-dpi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Pixel Clock
+  - description: Engine Clock
+  - description: DPI PLL
+
+  clock-names:
+items:
+  - const: pixel
+  - const: engine
+  - const: pll
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+items:
+  - const: default
+  - const: sleep
+
+  port:
+type: object
+description:
+  Output port node with endpoint definitions as described in
+  Documentation/devicetree/bindings/graph.txt. This port should be 
connected
+  to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+  endpoint:
+type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0 0x1401d000 0 0x1000>;
+interrupts = ;
+clocks = < CLK_MM_DPI_PIXEL>,
+ < CLK_MM_DPI_ENGINE>,
+ < CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <_pin_func>;
+pinctrl-1 = <_pin_idle>;
+
+port {
+dpi0_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+...
-- 
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[PATCH v16 0/1] mt8183 dpi support pin mode swap

[Jitao Shi]

Changes since v15:
 - Fix YAML License to (GPL-2.0-only OR BSD-2-Clause).
 - "dt-bindings: display: mediatek: control dpi pins mode to avoid leakage"
   "drm/mediatek: set dpi pin mode to gpio low to avoid leakage current"
   applied v15. The links are https://patchwork.kernel.org/patch/11489545/
   https://patchwork.kernel.org/patch/11489577/

Changes since v14:
 - add "Acked-by" and "Reviewed-by"
 - change port@0 to port in yaml

Changes since v13:
 - move dpi dual edge patches to another series because it will have long time
   to implement the dual edge change base boris patches.
   https://patchwork.kernel.org/cover/11354279/

Changes since v12:
 - fix mediatek,dpi.yaml make_dt_binding_check errors.

Change since v11:
 - fine tune mediatek,dpi.yaml.
 - add Acked-by: Rob Herring .

Change since v10:
 - convert the 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
   to yaml format.
 - read the pclk-sample in endpoint.

Changes since v9:
 - rename pinctrl-names = "gpiomode", "dpimode" to "active", "idle".
 - fix some typo.

Changes since v8:
 - drop pclk-sample redefine in mediatek,dpi.txt
 - only get the gpiomode and dpimode when dpi->pinctrl is successful.

Changes since v7:
 - separate dt-bindings to independent patches.
 - move dpi dual edge to one patch.

Changes since v6:
 - change dual_edge to pclk-sample
 - remove dpi_pin_mode_swap and

Changes since v5:
 - fine tune the dt-bindings commit message.

Changes since v4:
 - move pin mode control and dual edge control to deveice tree.
 - update dt-bindings document for pin mode swap and dual edge control.

Changes since v3:
 - add dpi pin mode control when dpi on or off.
 - update dpi dual edge comment.

Changes since v2:
 - update dt-bindings document for mt8183 dpi.
 - separate dual edge modfication as independent patch.

Jitao Shi (1):
  dt-bindings: display: mediatek: convert the dpi bindings to yaml

 .../display/mediatek/mediatek,dpi.txt | 42 
 .../display/mediatek/mediatek,dpi.yaml| 97 +++
 2 files changed, 97 insertions(+), 42 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

-- 
2.25.1
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[PATCH] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp

[Jitao Shi]

If panel has too small hfp or hbp, horizontal_frontporch_byte or
horizontal_backporch_byte may become very small value or negative
value. This patch adjusts their values so that they are greater
than minimum value and keep total of them unchanged.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 0ede69830a9d..aebaafd90ceb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -148,6 +148,9 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
 
+#define MIN_HFP_BYTE   0x02
+#define MIN_HBP_BYTE   0x02
+
 struct mtk_phy_timing {
u32 lpx;
u32 da_hs_prepare;
@@ -450,6 +453,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
+   s32 signed_hfp_byte, signed_hbp_byte;
u32 dsi_tmp_buf_bpp, data_phy_cycles;
struct mtk_phy_timing *timing = >phy_timing;
 
@@ -519,6 +523,20 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
}
}
 
+   signed_hfp_byte = (s32)horizontal_frontporch_byte;
+   signed_hbp_byte = (s32)horizontal_backporch_byte;
+
+   if (signed_hfp_byte + signed_hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
+   DRM_WARN("Calculated hfp_byte and hbp_byte are too small, "
+"panel may not work properly.\n");
+   } else if (signed_hfp_byte < MIN_HFP_BYTE) {
+   horizontal_frontporch_byte = MIN_HFP_BYTE;
+   horizontal_backporch_byte -= MIN_HFP_BYTE - signed_hfp_byte;
+   } else if (signed_hbp_byte < MIN_HBP_BYTE) {
+   horizontal_frontporch_byte -= MIN_HBP_BYTE - signed_hbp_byte;
+   horizontal_backporch_byte = MIN_HBP_BYTE;
+   }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
-- 
2.25.1
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[PATCH v15 1/3] dt-bindings: display: mediatek: control dpi pins mode to avoid leakage

[Jitao Shi]

Add property "pinctrl-names" to swap pin mode between gpio and dpi mode. Set
the dpi pins to gpio mode and output-low to avoid leakage current when dpi
disabled.

Acked-by: Rob Herring 
Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Jitao Shi 
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
index 58914cf681b8..77def4456706 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
@@ -17,6 +17,9 @@ Required properties:
   Documentation/devicetree/bindings/graph.txt. This port should be connected
   to the input port of an attached HDMI or LVDS encoder chip.
 
+Optional properties:
+- pinctrl-names: Contain "default" and "sleep".
+
 Example:
 
 dpi0: dpi@1401d000 {
@@ -27,6 +30,9 @@ dpi0: dpi@1401d000 {
 < CLK_MM_DPI_ENGINE>,
 < CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_pin_func>;
+   pinctrl-1 = <_pin_idle>;
 
port {
dpi0_out: endpoint {
-- 
2.12.5
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[PATCH v15 0/3] mt8183 dpi support pin mode swap

[Jitao Shi]

Changes since v14:
 - add "Acked-by" and "Reviewed-by"
 - change port@0 to port in yaml

Changes since v13:
 - move dpi dual edge patches to another series because it will have long time
   to implement the dual edge change base boris patches.
   https://patchwork.kernel.org/cover/11354279/

Changes since v12:
 - fix mediatek,dpi.yaml make_dt_binding_check errors.

Change since v11:
 - fine tune mediatek,dpi.yaml.
 - add Acked-by: Rob Herring .

Change since v10:
 - convert the 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
   to yaml format.
 - read the pclk-sample in endpoint.

Changes since v9:
 - rename pinctrl-names = "gpiomode", "dpimode" to "active", "idle".
 - fix some typo.

Changes since v8:
 - drop pclk-sample redefine in mediatek,dpi.txt
 - only get the gpiomode and dpimode when dpi->pinctrl is successful.

Changes since v7:
 - separate dt-bindings to independent patches.
 - move dpi dual edge to one patch.

Changes since v6:
 - change dual_edge to pclk-sample
 - remove dpi_pin_mode_swap and

Changes since v5:
 - fine tune the dt-bindings commit message.

Changes since v4:
 - move pin mode control and dual edge control to deveice tree.
 - update dt-bindings document for pin mode swap and dual edge control.

Changes since v3:
 - add dpi pin mode control when dpi on or off.
 - update dpi dual edge comment.

Changes since v2:
 - update dt-bindings document for mt8183 dpi.
 - separate dual edge modfication as independent patch.

Jitao Shi (3):
  dt-bindings: display: mediatek: control dpi pins mode to avoid leakage
  dt-bindings: display: mediatek: convert the document format from txt
to yaml
  drm/mediatek: set dpi pin mode to gpio low to avoid leakage current

 .../bindings/display/mediatek/mediatek,dpi.txt | 36 
 .../bindings/display/mediatek/mediatek,dpi.yaml| 97 ++
 drivers/gpu/drm/mediatek/mtk_dpi.c | 31 +++
 3 files changed, 128 insertions(+), 36 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

-- 
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[PATCH v15 2/3] dt-bindings: display: mediatek: convert the document format from txt to yaml

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 .../bindings/display/mediatek/mediatek,dpi.txt | 42 --
 .../bindings/display/mediatek/mediatek,dpi.yaml| 97 ++
 2 files changed, 97 insertions(+), 42 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
-  the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
-  Documentation/devicetree/bindings/graph.txt. This port should be connected
-  to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
-   compatible = "mediatek,mt8173-dpi";
-   reg = <0 0x1401d000 0 0x1000>;
-   interrupts = ;
-   clocks = < CLK_MM_DPI_PIXEL>,
-< CLK_MM_DPI_ENGINE>,
-< CLK_APMIXED_TVDPLL>;
-   clock-names = "pixel", "engine", "pll";
-   pinctrl-names = "default", "sleep";
-   pinctrl-0 = <_pin_func>;
-   pinctrl-1 = <_pin_idle>;
-
-   port {
-   dpi0_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-};
diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..2c2d6a71cb8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+  - CK Hu 
+  - Jitao shi 
+
+description: |
+  The Mediatek DPI function block is a sink of the display subsystem and
+  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+  output bus.
+
+properties:
+  compatible:
+enum:
+  - mediatek,mt2701-dpi
+  - mediatek,mt8173-dpi
+  - mediatek,mt8183-dpi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Pixel Clock
+  - description: Engine Clock
+  - description: DPI PLL
+
+  clock-names:
+items:
+  - const: pixel
+  - const: engine
+  - const: pll
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+items:
+  - const: default
+  - const: sleep
+
+  port:
+type: object
+description:
+  Output port node with endpoint definitions as described in
+  Documentation/devicetree/bindings/graph.txt. This port should be 
connected
+  to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+  endpoint:
+type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0 0x1401d000 0 0x1000>;
+interrupts = ;
+clocks = < CLK_MM_DPI_PIXEL>,
+ < CLK_MM_DPI_ENGINE>,
+ < CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <_pin_func>;
+pinctrl-1 = <_pin_idle>;
+
+port {
+dpi0_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+...
-- 
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[PATCH v15 3/3] drm/mediatek: set dpi pin mode to gpio low to avoid leakage current

[Jitao Shi]

Config dpi pins mode to output and pull low when dpi is disabled.
Aovid leakage current from some dpi pins (Hsync Vsync DE ... ).

Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 087f5ce732e1..1e01254788d9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -10,7 +10,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 
@@ -74,6 +76,9 @@ struct mtk_dpi {
enum mtk_dpi_out_yc_map yc_map;
enum mtk_dpi_out_bit_num bit_num;
enum mtk_dpi_out_channel_swap channel_swap;
+   struct pinctrl *pinctrl;
+   struct pinctrl_state *pins_gpio;
+   struct pinctrl_state *pins_dpi;
int refcount;
 };
 
@@ -379,6 +384,9 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
if (--dpi->refcount != 0)
return;
 
+   if (dpi->pinctrl && dpi->pins_gpio)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
@@ -403,6 +411,9 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_pixel;
}
 
+   if (dpi->pinctrl && dpi->pins_dpi)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
+
mtk_dpi_enable(dpi);
return 0;
 
@@ -705,6 +716,26 @@ static int mtk_dpi_probe(struct platform_device *pdev)
dpi->dev = dev;
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
 
+   dpi->pinctrl = devm_pinctrl_get(>dev);
+   if (IS_ERR(dpi->pinctrl)) {
+   dpi->pinctrl = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl!\n");
+   }
+   if (dpi->pinctrl) {
+   dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
+   if (IS_ERR(dpi->pins_gpio)) {
+   dpi->pins_gpio = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl idle!\n");
+   }
+   if (dpi->pins_gpio)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
+   dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
+   if (IS_ERR(dpi->pins_dpi)) {
+   dpi->pins_dpi = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl active!\n");
+   }
+   }
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dpi->regs = devm_ioremap_resource(dev, mem);
if (IS_ERR(dpi->regs)) {
-- 
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[PATCH v6 4/4] drm/mediatek: config mipitx impedance with calibration data

[Jitao Shi]

Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 40 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  3 ++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 21 ++
 3 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e301af64809e..8cee2591e728 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -88,6 +88,44 @@ static const struct phy_ops mtk_mipi_tx_ops = {
.owner = THIS_MODULE,
 };
 
+static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
+{
+   struct nvmem_cell *cell;
+   size_t len;
+   u32 *buf;
+
+   cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
+   if (IS_ERR(cell)) {
+   dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
+   return;
+   }
+   buf = (u32 *)nvmem_cell_read(cell, );
+   nvmem_cell_put(cell);
+
+   if (IS_ERR(buf)) {
+   dev_info(mipi_tx->dev, "can't get data, ignore it\n");
+   return;
+   }
+
+   if (len < 3 * sizeof(u32)) {
+   dev_info(mipi_tx->dev, "invalid calibration data\n");
+   kfree(buf);
+   return;
+   }
+
+   mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
+  (buf[0] >> 11 & 0x1f);
+   mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
+  (buf[0] >> 1 & 0x1f);
+   mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
+  (buf[1] >> 22 & 0x1f);
+   mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
+  (buf[1] >> 12 & 0x1f);
+   mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
+  (buf[1] >> 2 & 0x1f);
+   kfree(buf);
+}
+
 static int mtk_mipi_tx_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -174,6 +212,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
 
mipi_tx->dev = dev;
 
+   mtk_mipi_tx_get_calibration_datal(mipi_tx);
+
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
   mipi_tx->pll);
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index eea44327fe9f..c76f07c3fdeb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -12,9 +12,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 struct mtk_mipitx_data {
const u32 mppll_preserve;
@@ -28,6 +30,7 @@ struct mtk_mipi_tx {
void __iomem *regs;
u32 data_rate;
u32 mipitx_drive;
+   u32 rt_code[5];
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index e4cc967750cb..9f3e55aeebb2 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -28,6 +28,7 @@
 #define MIPITX_PLL_CON40x003c
 #define RG_DSI_PLL_IBIAS   (3 << 10)
 
+#define MIPITX_D2P_RTCODE  0x0100
 #define MIPITX_D2_SW_CTL_EN0x0144
 #define MIPITX_D0_SW_CTL_EN0x0244
 #define MIPITX_CK_CKMODE_EN0x0328
@@ -108,6 +109,24 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+   int i, j;
+
+   for (i = 0; i < 5; i++) {
+   if ((mipi_tx->rt_code[i] & 0x1f) == 0)
+   mipi_tx->rt_code[i] |= 0x10;
+
+   if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
+   mipi_tx->rt_code[i] |= 0x10 << 5;
+
+   for (j = 0; j < 10; j++)
+   mtk_mipi_tx_update_bits(mipi_tx,
+   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+   1, mipi_tx->rt_code[i] >> j & 1);
+   }
+}
+
 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 {
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +149,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
(mipi_tx->mipitx_drive - 3000) / 200 << 6);
 
+   mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0
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[PATCH v6 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current

[Jitao Shi]

Add a property to control mipi tx drive current:
"drive-strength-microamp"

Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index a19a6cc375ed..d78b6d6d8fab 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -33,6 +33,10 @@ Required properties:
 - #clock-cells: must be <0>;
 - #phy-cells: must be <0>.
 
+Optional properties:
+- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
+  the step is 200.
+
 Example:
 
 mipi_tx0: mipi-dphy@10215000 {
@@ -42,6 +46,7 @@ mipi_tx0: mipi-dphy@10215000 {
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   drive-strength-microamp = <4600>;
 };
 
 dsi0: dsi@1401b000 {
-- 
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[PATCH v6 2/4] dt-bindings: display: mediatek: get mipitx calibration data from nvmem

[Jitao Shi]

Add properties to get get mipitx calibration data.

Reviewed-by: Chun-Kuang Hu 
Reviewed-by: Rob Herring 
Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index d78b6d6d8fab..8e4729de8c85 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -36,6 +36,9 @@ Required properties:
 Optional properties:
 - drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
   the step is 200.
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
+   unspecified default values shall be used.
+- nvmem-cell-names: Should be "calibration-data"
 
 Example:
 
@@ -47,6 +50,8 @@ mipi_tx0: mipi-dphy@10215000 {
#clock-cells = <0>;
#phy-cells = <0>;
drive-strength-microamp = <4600>;
+   nvmem-cells= <_tx_calibration>;
+   nvmem-cell-names = "calibration-data";
 };
 
 dsi0: dsi@1401b000 {
-- 
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[PATCH v6 0/4] Config mipi tx current and impedance

[Jitao Shi]

Changes since v5:
 - remove memset()
 - add return to remove "else"

Changes since v4:
 - add Reviewed-by:
 - move the get the calibration data code to probe.

Changes since v3:
 - refine drive-strength-microamp as from 3000 to 6000.

Changes since v2:
 - fix the title of commit message.
 - rename mipitx-current-drive to drive-strength-microamp

Changes since v1:
 - fix coding style.
 - change mtk_mipi_tx_config_calibration_data() to void

Jitao Shi (4):
  dt-bindings: display: mediatek: add property to control mipi tx drive
current
  dt-bindings: display: mediatek: get mipitx calibration data from nvmem
  drm/mediatek: add the mipitx driving control
  drm/mediatek: config mipitx impedance with calibration data

 .../display/mediatek/mediatek,dsi.txt | 10 
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 54 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  4 ++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 28 ++
 4 files changed, 96 insertions(+)

-- 
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[PATCH v6 3/4] drm/mediatek: add the mipitx driving control

[Jitao Shi]

Add a property in device tree to control the driving by different
board.

Reviewed-by: Chun-Kuang Hu 
Reviewed-by: Matthias Brugger 
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 14 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |  7 +++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e4d34484ecc8..e301af64809e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
return ret;
}
 
+   ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
+  _tx->mipitx_drive);
+   /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
+   if (ret < 0)
+   mipi_tx->mipitx_drive = 4600;
+
+   /* check the mipitx_drive valid */
+   if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
+   dev_warn(dev, "drive-strength-microamp is invalid %d, not in 
3000 ~ 6000\n",
+mipi_tx->mipitx_drive);
+   mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
+ 6000);
+   }
+
ref_clk_name = __clk_get_name(ref_clk);
 
ret = of_property_read_string(dev->of_node, "clock-output-names",
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 413f35d86219..eea44327fe9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
struct device *dev;
void __iomem *regs;
u32 data_rate;
+   u32 mipitx_drive;
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 91f08a351fd0..e4cc967750cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -17,6 +17,9 @@
 #define RG_DSI_BG_CORE_EN  BIT(7)
 #define RG_DSI_PAD_TIEL_SELBIT(8)
 
+#define MIPITX_VOLTAGE_SEL 0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL(0xf << 6)
+
 #define MIPITX_PLL_PWR 0x0028
 #define MIPITX_PLL_CON00x002c
 #define MIPITX_PLL_CON10x0030
@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
+   RG_DSI_HSTX_LDO_REF_SEL,
+   (mipi_tx->mipitx_drive - 3000) / 200 << 6);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0
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[PATCH v5 0/4] Config mipi tx current and impedance

[Jitao Shi]

Changes since v4:
 - add Reviewed-by:
 - move the get the calibration data code to probe.

Changes since v3:
 - refine drive-strength-microamp as from 3000 to 6000.

Changes since v2:
 - fix the title of commit message.
 - rename mipitx-current-drive to drive-strength-microamp

Changes since v1:
 - fix coding style.
 - change mtk_mipi_tx_config_calibration_data() to void

Jitao Shi (4):
  dt-bindings: display: mediatek: add property to control mipi tx drive
current
  dt-bindings: display: mediatek: get mipitx calibration data from nvmem
  drm/mediatek: add the mipitx driving control
  drm/mediatek: config mipitx impedance with calibration data

 .../display/mediatek/mediatek,dsi.txt | 10 
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 54 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  4 ++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 28 ++
 4 files changed, 96 insertions(+)

-- 
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[PATCH v5 4/4] drm/mediatek: config mipitx impedance with calibration data

[Jitao Shi]

Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 40 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  3 ++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 21 ++
 3 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e301af64809e..5e91fc2c1318 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -88,6 +88,44 @@ static const struct phy_ops mtk_mipi_tx_ops = {
.owner = THIS_MODULE,
 };
 
+static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
+{
+   struct nvmem_cell *cell;
+   size_t len;
+   u32 *buf;
+
+   memset(mipi_tx->rt_code, 0, sizeof(mipi_tx->rt_code));
+   cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
+   if (IS_ERR(cell)) {
+   dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
+   } else {
+   buf = (u32 *)nvmem_cell_read(cell, );
+   nvmem_cell_put(cell);
+
+   if (IS_ERR(buf)) {
+   dev_info(mipi_tx->dev, "can't get data, ignore it\n");
+   } else {
+   if (len < 3 * sizeof(u32)) {
+   dev_info(mipi_tx->dev, "invalid calibration 
data\n");
+   kfree(buf);
+   return;
+   }
+
+   mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
+  (buf[0] >> 11 & 0x1f);
+   mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
+  (buf[0] >> 1 & 0x1f);
+   mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
+  (buf[1] >> 22 & 0x1f);
+   mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
+  (buf[1] >> 12 & 0x1f);
+   mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
+  (buf[1] >> 2 & 0x1f);
+   kfree(buf);
+   }
+   }
+}
+
 static int mtk_mipi_tx_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -174,6 +212,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
 
mipi_tx->dev = dev;
 
+   mtk_mipi_tx_get_calibration_datal(mipi_tx);
+
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
   mipi_tx->pll);
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index eea44327fe9f..c76f07c3fdeb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -12,9 +12,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 
 struct mtk_mipitx_data {
const u32 mppll_preserve;
@@ -28,6 +30,7 @@ struct mtk_mipi_tx {
void __iomem *regs;
u32 data_rate;
u32 mipitx_drive;
+   u32 rt_code[5];
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index e4cc967750cb..9f3e55aeebb2 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -28,6 +28,7 @@
 #define MIPITX_PLL_CON40x003c
 #define RG_DSI_PLL_IBIAS   (3 << 10)
 
+#define MIPITX_D2P_RTCODE  0x0100
 #define MIPITX_D2_SW_CTL_EN0x0144
 #define MIPITX_D0_SW_CTL_EN0x0244
 #define MIPITX_CK_CKMODE_EN0x0328
@@ -108,6 +109,24 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+   int i, j;
+
+   for (i = 0; i < 5; i++) {
+   if ((mipi_tx->rt_code[i] & 0x1f) == 0)
+   mipi_tx->rt_code[i] |= 0x10;
+
+   if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
+   mipi_tx->rt_code[i] |= 0x10 << 5;
+
+   for (j = 0; j < 10; j++)
+   mtk_mipi_tx_update_bits(mipi_tx,
+   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+   1, mipi_tx->rt_code[i] >> j & 1);
+   }
+}
+
 static void mtk_mip

[PATCH v5 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current

[Jitao Shi]

Add a property to control mipi tx drive current:
"drive-strength-microamp"

Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index a19a6cc375ed..d78b6d6d8fab 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -33,6 +33,10 @@ Required properties:
 - #clock-cells: must be <0>;
 - #phy-cells: must be <0>.
 
+Optional properties:
+- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
+  the step is 200.
+
 Example:
 
 mipi_tx0: mipi-dphy@10215000 {
@@ -42,6 +46,7 @@ mipi_tx0: mipi-dphy@10215000 {
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   drive-strength-microamp = <4600>;
 };
 
 dsi0: dsi@1401b000 {
-- 
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[PATCH v5 3/4] drm/mediatek: add the mipitx driving control

[Jitao Shi]

Add a property in device tree to control the driving by different
board.

Reviewed-by: Chun-Kuang Hu 
Reviewed-by: Matthias Brugger 
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 14 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |  7 +++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e4d34484ecc8..e301af64809e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
return ret;
}
 
+   ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
+  _tx->mipitx_drive);
+   /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
+   if (ret < 0)
+   mipi_tx->mipitx_drive = 4600;
+
+   /* check the mipitx_drive valid */
+   if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
+   dev_warn(dev, "drive-strength-microamp is invalid %d, not in 
3000 ~ 6000\n",
+mipi_tx->mipitx_drive);
+   mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
+ 6000);
+   }
+
ref_clk_name = __clk_get_name(ref_clk);
 
ret = of_property_read_string(dev->of_node, "clock-output-names",
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 413f35d86219..eea44327fe9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
struct device *dev;
void __iomem *regs;
u32 data_rate;
+   u32 mipitx_drive;
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 91f08a351fd0..e4cc967750cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -17,6 +17,9 @@
 #define RG_DSI_BG_CORE_EN  BIT(7)
 #define RG_DSI_PAD_TIEL_SELBIT(8)
 
+#define MIPITX_VOLTAGE_SEL 0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL(0xf << 6)
+
 #define MIPITX_PLL_PWR 0x0028
 #define MIPITX_PLL_CON00x002c
 #define MIPITX_PLL_CON10x0030
@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
+   RG_DSI_HSTX_LDO_REF_SEL,
+   (mipi_tx->mipitx_drive - 3000) / 200 << 6);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
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[PATCH v5 2/4] dt-bindings: display: mediatek: get mipitx calibration data from nvmem

[Jitao Shi]

Add properties to get get mipitx calibration data.

Reviewed-by: Chun-Kuang Hu 
Reviewed-by: Rob Herring 
Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index d78b6d6d8fab..8e4729de8c85 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -36,6 +36,9 @@ Required properties:
 Optional properties:
 - drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
   the step is 200.
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
+   unspecified default values shall be used.
+- nvmem-cell-names: Should be "calibration-data"
 
 Example:
 
@@ -47,6 +50,8 @@ mipi_tx0: mipi-dphy@10215000 {
#clock-cells = <0>;
#phy-cells = <0>;
drive-strength-microamp = <4600>;
+   nvmem-cells= <_tx_calibration>;
+   nvmem-cell-names = "calibration-data";
 };
 
 dsi0: dsi@1401b000 {
-- 
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Re: [PATCH v4 4/4] drm/mediatek: config mipitx impedance with calibration data

[Jitao Shi]

On Sat, 2020-04-04 at 22:26 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
> 
> Jitao Shi  於 2020年3月31日 週二 下午4:28寫道：
> >
> > Read calibration data from nvmem, and config mipitx impedance with
> > calibration data to make sure their impedance are 100ohm.
> >
> > Signed-off-by: Jitao Shi 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++
> >  1 file changed, 57 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
> > b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > index e4cc967750cb..0f87cd3d1d7d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> > @@ -5,6 +5,8 @@
> >   */
> >
> >  #include "mtk_mipi_tx.h"
> > +#include 
> > +#include 
> >
> >  #define MIPITX_LANE_CON0x000c
> >  #define RG_DSI_CPHY_T1DRV_EN   BIT(0)
> > @@ -28,6 +30,7 @@
> >  #define MIPITX_PLL_CON40x003c
> >  #define RG_DSI_PLL_IBIAS   (3 << 10)
> >
> > +#define MIPITX_D2P_RTCODE  0x0100
> >  #define MIPITX_D2_SW_CTL_EN0x0144
> >  #define MIPITX_D0_SW_CTL_EN0x0244
> >  #define MIPITX_CK_CKMODE_EN0x0328
> > @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
> > .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
> >  };
> >
> > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx 
> > *mipi_tx)
> > +{
> > +   u32 *buf;
> > +   u32 rt_code[5];
> > +   int i, j;
> > +   struct nvmem_cell *cell;
> > +   struct device *dev = mipi_tx->dev;
> > +   size_t len;
> > +
> > +   cell = nvmem_cell_get(dev, "calibration-data");
> > +   if (IS_ERR(cell)) {
> > +   dev_info(dev, "nvmem_cell_get fail\n");
> > +   return;
> > +   }
> > +
> > +   buf = (u32 *)nvmem_cell_read(cell, );
> > +
> > +   nvmem_cell_put(cell);
> > +
> > +   if (IS_ERR(buf)) {
> > +   dev_info(dev, "can't get data\n");
> > +   return;
> > +   }
> > +
> > +   if (len < 3 * sizeof(u32)) {
> > +   dev_info(dev, "invalid calibration data\n");
> > +   kfree(buf);
> > +   return;
> > +   }
> > +
> > +   rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
> > +   rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
> > +   rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
> > +   rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
> > +   rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
> 
> Why not just save rt_code in nvmem and you don't need to translate here?
> If you need to do so, please add description for this.
> 
> Regards,
> Chun-Kuang.
> 

Hi Chun-Kuang,

The calibration data is flashed in rom when the IC FT test
And the data struct can't be stored again

Best Regards
JItao
> 
> > +
> > +   for (i = 0; i < 5; i++) {
> > +   if ((rt_code[i] & 0x1f) == 0)
> > +   rt_code[i] |= 0x10;
> > +
> > +   if ((rt_code[i] >> 5 & 0x1f) == 0)
> > +   rt_code[i] |= 0x10 << 5;
> > +
> > +   for (j = 0; j < 10; j++)
> > +   mtk_mipi_tx_update_bits(mipi_tx,
> > +   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
> > +   1, rt_code[i] >> j & 1);
> > +   }
> > +
> > +   kfree(buf);
> > +}
> > +
> >  static void mtk_mipi_tx_power_on_signal(struct phy *phy)
> >  {
> > struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
> > @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
> > RG_DSI_HSTX_LDO_REF_SEL,
> > (mipi_tx->mipitx_drive - 3000) / 200 << 6);
> >
> > +   mtk_mipi_tx_config_calibration_data(mipi_tx);
> > +
> > mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, 
> > DSI_CK_CKMODE_EN);
> >  }
> >
> > --
> > 2.21.0
> > ___
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[PATCH v14 0/3] mt8183 dpi support pin mode swap

[Jitao Shi]

Changes since v13:
 - move dpi dual edge patches to another series because it will have long time
   to implement the dual edge change base boris patches.
   https://patchwork.kernel.org/cover/11354279/

Changes since v12:
 - fix mediatek,dpi.yaml make_dt_binding_check errors.

Change since v11:
 - fine tune mediatek,dpi.yaml.
 - add Acked-by: Rob Herring .

Change since v10:
 - convert the 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
   to yaml format.
 - read the pclk-sample in endpoint.

Changes since v9:
 - rename pinctrl-names = "gpiomode", "dpimode" to "active", "idle".
 - fix some typo.

Changes since v8:
 - drop pclk-sample redefine in mediatek,dpi.txt
 - only get the gpiomode and dpimode when dpi->pinctrl is successful.

Changes since v7:
 - separate dt-bindings to independent patches.
 - move dpi dual edge to one patch.

Changes since v6:
 - change dual_edge to pclk-sample
 - remove dpi_pin_mode_swap and

Changes since v5:
 - fine tune the dt-bindings commit message.

Changes since v4:
 - move pin mode control and dual edge control to deveice tree.
 - update dt-bindings document for pin mode swap and dual edge control.

Changes since v3:
 - add dpi pin mode control when dpi on or off.
 - update dpi dual edge comment.

Changes since v2:
 - update dt-bindings document for mt8183 dpi.
 - separate dual edge modfication as independent patch.

Jitao Shi (3):
  dt-bindings: display: mediatek: control dpi pins mode to avoid leakage
  dt-bindings: display: mediatek: convert the document format from txt
to yaml
  drm/mediatek: set dpi pin mode to gpio low to avoid leakage current

 .../display/mediatek/mediatek,dpi.txt | 36 ---
 .../display/mediatek/mediatek,dpi.yaml| 97 +++
 drivers/gpu/drm/mediatek/mtk_dpi.c| 31 ++
 3 files changed, 128 insertions(+), 36 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

-- 
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[PATCH v14 2/3] dt-bindings: display: mediatek: convert the document format from txt to yaml

[Jitao Shi]

Signed-off-by: Jitao Shi 
---
 .../display/mediatek/mediatek,dpi.txt | 42 
 .../display/mediatek/mediatek,dpi.yaml| 97 +++
 2 files changed, 97 insertions(+), 42 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index 77def4456706..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,-dpi"
-  the supported chips are mt2701 , mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
-  Documentation/devicetree/bindings/graph.txt. This port should be connected
-  to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
-   compatible = "mediatek,mt8173-dpi";
-   reg = <0 0x1401d000 0 0x1000>;
-   interrupts = ;
-   clocks = < CLK_MM_DPI_PIXEL>,
-< CLK_MM_DPI_ENGINE>,
-< CLK_APMIXED_TVDPLL>;
-   clock-names = "pixel", "engine", "pll";
-   pinctrl-names = "default", "sleep";
-   pinctrl-0 = <_pin_func>;
-   pinctrl-1 = <_pin_idle>;
-
-   port {
-   dpi0_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-};
diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index ..effdaa96aec3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+  - CK Hu 
+  - Jitao shi 
+
+description: |
+  The Mediatek DPI function block is a sink of the display subsystem and
+  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+  output bus.
+
+properties:
+  compatible:
+enum:
+  - mediatek,mt2701-dpi
+  - mediatek,mt8173-dpi
+  - mediatek,mt8183-dpi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Pixel Clock
+  - description: Engine Clock
+  - description: DPI PLL
+
+  clock-names:
+items:
+  - const: pixel
+  - const: engine
+  - const: pll
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+items:
+  - const: default
+  - const: sleep
+
+  port@0:
+type: object
+description:
+  Output port node with endpoint definitions as described in
+  Documentation/devicetree/bindings/graph.txt. This port should be 
connected
+  to the input port of an attached HDMI or LVDS encoder chip.
+
+properties:
+  endpoint:
+type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - port@0
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+dpi0: dpi@1401d000 {
+compatible = "mediatek,mt8173-dpi";
+reg = <0 0x1401d000 0 0x1000>;
+interrupts = ;
+clocks = < CLK_MM_DPI_PIXEL>,
+ < CLK_MM_DPI_ENGINE>,
+ < CLK_APMIXED_TVDPLL>;
+clock-names = "pixel", "engine", "pll";
+pinctrl-names = "default", "sleep";
+pinctrl-0 = <_pin_func>;
+pinctrl-1 = <_pin_idle>;
+
+port@0 {
+dpi0_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+...
-- 
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[PATCH v14 3/3] drm/mediatek: set dpi pin mode to gpio low to avoid leakage current

[Jitao Shi]

Config dpi pins mode to output and pull low when dpi is disabled.
Aovid leakage current from some dpi pins (Hsync Vsync DE ... ).

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 31 ++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 087f5ce732e1..1e01254788d9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -10,7 +10,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 
@@ -74,6 +76,9 @@ struct mtk_dpi {
enum mtk_dpi_out_yc_map yc_map;
enum mtk_dpi_out_bit_num bit_num;
enum mtk_dpi_out_channel_swap channel_swap;
+   struct pinctrl *pinctrl;
+   struct pinctrl_state *pins_gpio;
+   struct pinctrl_state *pins_dpi;
int refcount;
 };
 
@@ -379,6 +384,9 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
if (--dpi->refcount != 0)
return;
 
+   if (dpi->pinctrl && dpi->pins_gpio)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
@@ -403,6 +411,9 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_pixel;
}
 
+   if (dpi->pinctrl && dpi->pins_dpi)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
+
mtk_dpi_enable(dpi);
return 0;
 
@@ -705,6 +716,26 @@ static int mtk_dpi_probe(struct platform_device *pdev)
dpi->dev = dev;
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
 
+   dpi->pinctrl = devm_pinctrl_get(>dev);
+   if (IS_ERR(dpi->pinctrl)) {
+   dpi->pinctrl = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl!\n");
+   }
+   if (dpi->pinctrl) {
+   dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
+   if (IS_ERR(dpi->pins_gpio)) {
+   dpi->pins_gpio = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl idle!\n");
+   }
+   if (dpi->pins_gpio)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
+   dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
+   if (IS_ERR(dpi->pins_dpi)) {
+   dpi->pins_dpi = NULL;
+   dev_dbg(>dev, "Cannot find pinctrl active!\n");
+   }
+   }
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dpi->regs = devm_ioremap_resource(dev, mem);
if (IS_ERR(dpi->regs)) {
-- 
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[PATCH v14 1/3] dt-bindings: display: mediatek: control dpi pins mode to avoid leakage

[Jitao Shi]

Add property "pinctrl-names" to swap pin mode between gpio and dpi mode. Set
the dpi pins to gpio mode and output-low to avoid leakage current when dpi
disabled.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.txt   | 6 ++
 1 file changed, 6 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
index 58914cf681b8..77def4456706 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
@@ -17,6 +17,9 @@ Required properties:
   Documentation/devicetree/bindings/graph.txt. This port should be connected
   to the input port of an attached HDMI or LVDS encoder chip.
 
+Optional properties:
+- pinctrl-names: Contain "default" and "sleep".
+
 Example:
 
 dpi0: dpi@1401d000 {
@@ -27,6 +30,9 @@ dpi0: dpi@1401d000 {
 < CLK_MM_DPI_ENGINE>,
 < CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_pin_func>;
+   pinctrl-1 = <_pin_idle>;
 
port {
dpi0_out: endpoint {
-- 
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[PATCH v4 0/4] Config mipi tx current and impedance

[Jitao Shi]

Changes since v3:
 - refine drive-strength-microamp as from 3000 to 6000.

Changes since v2:
 - fix the title of commit message.
 - rename mipitx-current-drive to drive-strength-microamp

Changes since v1:
 - fix coding style.
 - change mtk_mipi_tx_config_calibration_data() to void

Jitao Shi (4):
  dt-bindings: display: mediatek: add property to control mipi tx drive
current
  dt-bindings: display: mediatek: get mipitx calibration data from nvmem
  drm/mediatek: add the mipitx driving control
  drm/mediatek: config mipitx impedance with calibration data

 .../display/mediatek/mediatek,dsi.txt | 10 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 14 
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 64 +++
 4 files changed, 89 insertions(+)

-- 
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[PATCH v4 2/4] dt-bindings: display: mediatek: get mipitx calibration data from nvmem

[Jitao Shi]

Add properties to get get mipitx calibration data.

Reviewed-by: Rob Herring 
Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index d78b6d6d8fab..8e4729de8c85 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -36,6 +36,9 @@ Required properties:
 Optional properties:
 - drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
   the step is 200.
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
+   unspecified default values shall be used.
+- nvmem-cell-names: Should be "calibration-data"
 
 Example:
 
@@ -47,6 +50,8 @@ mipi_tx0: mipi-dphy@10215000 {
#clock-cells = <0>;
#phy-cells = <0>;
drive-strength-microamp = <4600>;
+   nvmem-cells= <_tx_calibration>;
+   nvmem-cell-names = "calibration-data";
 };
 
 dsi0: dsi@1401b000 {
-- 
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[PATCH v4 4/4] drm/mediatek: config mipitx impedance with calibration data

[Jitao Shi]

Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index e4cc967750cb..0f87cd3d1d7d 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
  */
 
 #include "mtk_mipi_tx.h"
+#include 
+#include 
 
 #define MIPITX_LANE_CON0x000c
 #define RG_DSI_CPHY_T1DRV_EN   BIT(0)
@@ -28,6 +30,7 @@
 #define MIPITX_PLL_CON40x003c
 #define RG_DSI_PLL_IBIAS   (3 << 10)
 
+#define MIPITX_D2P_RTCODE  0x0100
 #define MIPITX_D2_SW_CTL_EN0x0144
 #define MIPITX_D0_SW_CTL_EN0x0244
 #define MIPITX_CK_CKMODE_EN0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+   u32 *buf;
+   u32 rt_code[5];
+   int i, j;
+   struct nvmem_cell *cell;
+   struct device *dev = mipi_tx->dev;
+   size_t len;
+
+   cell = nvmem_cell_get(dev, "calibration-data");
+   if (IS_ERR(cell)) {
+   dev_info(dev, "nvmem_cell_get fail\n");
+   return;
+   }
+
+   buf = (u32 *)nvmem_cell_read(cell, );
+
+   nvmem_cell_put(cell);
+
+   if (IS_ERR(buf)) {
+   dev_info(dev, "can't get data\n");
+   return;
+   }
+
+   if (len < 3 * sizeof(u32)) {
+   dev_info(dev, "invalid calibration data\n");
+   kfree(buf);
+   return;
+   }
+
+   rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+   rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+   rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+   rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+   rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+   for (i = 0; i < 5; i++) {
+   if ((rt_code[i] & 0x1f) == 0)
+   rt_code[i] |= 0x10;
+
+   if ((rt_code[i] >> 5 & 0x1f) == 0)
+   rt_code[i] |= 0x10 << 5;
+
+   for (j = 0; j < 10; j++)
+   mtk_mipi_tx_update_bits(mipi_tx,
+   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+   1, rt_code[i] >> j & 1);
+   }
+
+   kfree(buf);
+}
+
 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 {
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
(mipi_tx->mipitx_drive - 3000) / 200 << 6);
 
+   mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
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[PATCH v4 3/4] drm/mediatek: add the mipitx driving control

[Jitao Shi]

Add a property in device tree to control the driving by different
board.

Reviewed-by: Matthias Brugger 
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 14 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c |  7 +++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e4d34484ecc8..e301af64809e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
return ret;
}
 
+   ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
+  _tx->mipitx_drive);
+   /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
+   if (ret < 0)
+   mipi_tx->mipitx_drive = 4600;
+
+   /* check the mipitx_drive valid */
+   if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
+   dev_warn(dev, "drive-strength-microamp is invalid %d, not in 
3000 ~ 6000\n",
+mipi_tx->mipitx_drive);
+   mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
+ 6000);
+   }
+
ref_clk_name = __clk_get_name(ref_clk);
 
ret = of_property_read_string(dev->of_node, "clock-output-names",
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 413f35d86219..eea44327fe9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
struct device *dev;
void __iomem *regs;
u32 data_rate;
+   u32 mipitx_drive;
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 91f08a351fd0..e4cc967750cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -17,6 +17,9 @@
 #define RG_DSI_BG_CORE_EN  BIT(7)
 #define RG_DSI_PAD_TIEL_SELBIT(8)
 
+#define MIPITX_VOLTAGE_SEL 0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL(0xf << 6)
+
 #define MIPITX_PLL_PWR 0x0028
 #define MIPITX_PLL_CON00x002c
 #define MIPITX_PLL_CON10x0030
@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
+   RG_DSI_HSTX_LDO_REF_SEL,
+   (mipi_tx->mipitx_drive - 3000) / 200 << 6);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0
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[PATCH v4 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current

[Jitao Shi]

Add a property to control mipi tx drive current:
"drive-strength-microamp"

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index a19a6cc375ed..d78b6d6d8fab 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -33,6 +33,10 @@ Required properties:
 - #clock-cells: must be <0>;
 - #phy-cells: must be <0>.
 
+Optional properties:
+- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
+  the step is 200.
+
 Example:
 
 mipi_tx0: mipi-dphy@10215000 {
@@ -42,6 +46,7 @@ mipi_tx0: mipi-dphy@10215000 {
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   drive-strength-microamp = <4600>;
 };
 
 dsi0: dsi@1401b000 {
-- 
2.21.0
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Re: [PATCH v3 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current

[Jitao Shi]

On Mon, 2020-03-23 at 16:00 -0600, Rob Herring wrote:
> On Wed, Mar 11, 2020 at 03:40:29PM +0800, Jitao Shi wrote:
> > Add a property to control mipi tx drive current:
> > "drive-strength-microamp"
> > 
> > Signed-off-by: Jitao Shi 
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > index a19a6cc375ed..d501f9ff4b1f 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > @@ -33,6 +33,9 @@ Required properties:
> >  - #clock-cells: must be <0>;
> >  - #phy-cells: must be <0>.
> >  
> > +Optional properties:
> > +- drive-strength-microamp: adjust driving current, should be 1 ~ 0xF
> 
> TBC, 1-0xf is in units of microamps? So a max drive strength of 15uA? 
> Seems a bit low.
> 

The minimum amp is 3000 macroamps,  step is 200macroamps.
So the drive current is 3000 + 200 * drive-strength-microamp amps.

I will update "drive-strength-microamp" define next version.

BR
Jitao
> > +
> >  Example:
> >  
> >  mipi_tx0: mipi-dphy@10215000 {
> > @@ -42,6 +45,7 @@ mipi_tx0: mipi-dphy@10215000 {
> > clock-output-names = "mipi_tx0_pll";
> > #clock-cells = <0>;
> > #phy-cells = <0>;
> > +   drive-strength-microamp = <0x8>;
> >  };
> >  
> >  dsi0: dsi@1401b000 {
> > -- 
> > 2.21.0


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[PATCH v3 0/4] Config mipi tx drive current and impedance

[Jitao Shi]

Changes since v2:
 - fix the title of commit message.
 - rename mipitx-current-drive to drive-strength-microamp

Changes since v1:
 - fix coding style.
 - change mtk_mipi_tx_config_calibration_data() to void

Jitao Shi (4):
  dt-bindings: display: mediatek: add property to control mipi tx drive
current
  dt-bindings: display: mediatek: get mipitx calibration data from nvmem
  drm/mediatek: add the mipitx driving control
  drm/mediatek: config mipitx impedance with calibration data

 .../display/mediatek/mediatek,dsi.txt |  9 +++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|  6 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 64 +++
 4 files changed, 80 insertions(+)

-- 
2.21.0
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[PATCH v3 4/4] drm/mediatek: config mipitx impedance with calibration data

[Jitao Shi]

Read calibration data from nvmem, and config mipitx impedance with
calibration data to make sure their impedance are 100ohm.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 124fdf95f1e5..878feeb7ac6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
  */
 
 #include "mtk_mipi_tx.h"
+#include 
+#include 
 
 #define MIPITX_LANE_CON0x000c
 #define RG_DSI_CPHY_T1DRV_EN   BIT(0)
@@ -28,6 +30,7 @@
 #define MIPITX_PLL_CON40x003c
 #define RG_DSI_PLL_IBIAS   (3 << 10)
 
+#define MIPITX_D2P_RTCODE  0x0100
 #define MIPITX_D2_SW_CTL_EN0x0144
 #define MIPITX_D0_SW_CTL_EN0x0244
 #define MIPITX_CK_CKMODE_EN0x0328
@@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+   u32 *buf;
+   u32 rt_code[5];
+   int i, j;
+   struct nvmem_cell *cell;
+   struct device *dev = mipi_tx->dev;
+   size_t len;
+
+   cell = nvmem_cell_get(dev, "calibration-data");
+   if (IS_ERR(cell)) {
+   dev_info(dev, "nvmem_cell_get fail\n");
+   return;
+   }
+
+   buf = (u32 *)nvmem_cell_read(cell, );
+
+   nvmem_cell_put(cell);
+
+   if (IS_ERR(buf)) {
+   dev_info(dev, "can't get data\n");
+   return;
+   }
+
+   if (len < 3 * sizeof(u32)) {
+   dev_info(dev, "invalid calibration data\n");
+   kfree(buf);
+   return;
+   }
+
+   rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f);
+   rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f);
+   rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f);
+   rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f);
+   rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f);
+
+   for (i = 0; i < 5; i++) {
+   if ((rt_code[i] & 0x1f) == 0)
+   rt_code[i] |= 0x10;
+
+   if ((rt_code[i] >> 5 & 0x1f) == 0)
+   rt_code[i] |= 0x10 << 5;
+
+   for (j = 0; j < 10; j++)
+   mtk_mipi_tx_update_bits(mipi_tx,
+   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+   1, rt_code[i] >> j & 1);
+   }
+
+   kfree(buf);
+}
+
 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 {
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
 
+   mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0
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[PATCH v3 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current

[Jitao Shi]

Add a property to control mipi tx drive current:
"drive-strength-microamp"

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index a19a6cc375ed..d501f9ff4b1f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -33,6 +33,9 @@ Required properties:
 - #clock-cells: must be <0>;
 - #phy-cells: must be <0>.
 
+Optional properties:
+- drive-strength-microamp: adjust driving current, should be 1 ~ 0xF
+
 Example:
 
 mipi_tx0: mipi-dphy@10215000 {
@@ -42,6 +45,7 @@ mipi_tx0: mipi-dphy@10215000 {
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   drive-strength-microamp = <0x8>;
 };
 
 dsi0: dsi@1401b000 {
-- 
2.21.0
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[PATCH v3 2/4] dt-bindings: display: mediatek: get mipitx calibration data from nvmem

[Jitao Shi]

Add properties to get get mipitx calibration data.

Signed-off-by: Jitao Shi 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt| 5 +
 1 file changed, 5 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index d501f9ff4b1f..b179293c43de 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -34,6 +34,9 @@ Required properties:
 - #phy-cells: must be <0>.
 
 Optional properties:
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
+   unspecified default values shall be used.
+- nvmem-cell-names: Should be "calibration-data"
 - drive-strength-microamp: adjust driving current, should be 1 ~ 0xF
 
 Example:
@@ -45,6 +48,8 @@ mipi_tx0: mipi-dphy@10215000 {
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   nvmem-cells= <_tx_calibration>;
+   nvmem-cell-names = "calibration-data";
drive-strength-microamp = <0x8>;
 };
 
-- 
2.21.0
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[PATCH v3 3/4] drm/mediatek: add the mipitx driving control

[Jitao Shi]

Add a property in device tree to control the driving by different
board.

Reviewed-by: Matthias Brugger 
Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 6 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 7 +++
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e4d34484ecc8..2a1ac4e97cbb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -125,6 +125,12 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
return ret;
}
 
+   ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
+  _tx->mipitx_drive);
+   /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
+   if (ret < 0)
+   mipi_tx->mipitx_drive = 0x8;
+
ref_clk_name = __clk_get_name(ref_clk);
 
ret = of_property_read_string(dev->of_node, "clock-output-names",
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 413f35d86219..eea44327fe9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
struct device *dev;
void __iomem *regs;
u32 data_rate;
+   u32 mipitx_drive;
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 91f08a351fd0..124fdf95f1e5 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -17,6 +17,9 @@
 #define RG_DSI_BG_CORE_EN  BIT(7)
 #define RG_DSI_PAD_TIEL_SELBIT(8)
 
+#define MIPITX_VOLTAGE_SEL 0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL(0xf << 6)
+
 #define MIPITX_PLL_PWR 0x0028
 #define MIPITX_PLL_CON00x002c
 #define MIPITX_PLL_CON10x0030
@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
+   RG_DSI_HSTX_LDO_REF_SEL,
+   mipi_tx->mipitx_drive << 6);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0
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