[PATCH v7 0/2] Add a Himax HX8837 display controller driver
Hi, please take a look at the patches chained to this messages and consider applying them. They add support for the controller that drives the panel on the OLPC XO laptops. Compared to v7, points risen in review by Laurent Pinchart have been addressed. Details in change log of patch 1/2. Tested on an OLPC XO-1.75 laptop. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Himax HX8837 is used to drive the LCD panel on OLPC platforms.
It controls the panel backlight and is able to refresh it when the LCD
controller (and the rest of the plaform) is powered off.
It also converts regular RGB color data from the LCDC so that it looks
reasonable on the OLPC LCD panel with a monochromatic layer on top of a
layer that can either reflect light (b/w sunlight readable mode) or light
pattern of red, green and blue pixels.
At this point, the driver is rather basic. The self-refresh mode is not
supported. There's no way of independently controlling the color swizzling,
antialiasing or b/w conversion, but it probably isn't too useful either.
There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
DRM, so this driver doesn't replace the other one yet.
Signed-off-by: Lubomir Rintel
---
Changes since v6:
(All also based on feedback from Sam Ravnborg)
- Drop selecting BACKLIGHT_LCD_SUPPORT
- Don't include drm/drm_print.h anymore
- Fix or clarify a couple of error messages
- Remove printing of info banner at end of probe()
Changes since v5:
(All based on feedback from Sam Ravnborg)
- Fix indentation in Kconfig
- Sort #includes
- Use a constant for max brightness instead of a literal
- Remove struct drm_panel from priv data
- Use dev_err() instead of DRM_ERROR
- Replace direct use of backlight props.brightness with
backlight_get_brightness()
- Document sentinels with { /* sentinel */ }
- Remove unsetting of panel->backlight
Changes since v3:
- Added this patch, in place of a driver derived from
drivers/staging/olpc_dcon. Compared to the previous one this
implements the bare minimum, without the fancy stuff such as
self-refresh that need more work/thinking.
drivers/gpu/drm/bridge/Kconfig| 12 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/himax-hx8837.c | 328 ++
3 files changed, 341 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6ca7b3c..9d753f55bcc05 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,18 @@ config DRM_DISPLAY_CONNECTOR
on ARM-based platforms. Saying Y here when this driver is not needed
will not cause any issue.
+config DRM_HIMAX_HX8837
+ tristate "HiMax HX8837 OLPC Display Controller"
+ depends on OF
+ depends on OLPC || ARCH_MMP || COMPILE_TEST
+ select DRM_KMS_HELPER
+ select BACKLIGHT_CLASS_DEVICE
+ help
+ Enable support for HiMax HX8837 Display Controller as found in the
+ OLPC XO laptops.
+
+ If your laptop doesn't have green ears, say "N"
+
config DRM_LONTIUM_LT9611
tristate "Lontium LT9611 DSI/HDMI bridge"
select SND_SOC_HDMI_CODEC if SND_SOC
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc76f8d6..1e27939d69d09 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
+obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c
b/drivers/gpu/drm/bridge/himax-hx8837.c
new file mode 100644
index 0..b97b71ba3f32e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/himax-hx8837.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * HiMax HX8837 Display Controller Driver
+ *
+ * Datasheet: http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define bridge_to_hx8837_priv(x) \
+ container_of(x, struct hx8837_priv, bridge)
+
+/* DCON registers */
+enum {
+ DCON_REG_ID = 0x00,
+ DCON_REG_MODE = 0x01,
+ DCON_REG_HRES = 0x02,
+ DCON_REG_HTOTAL = 0x03,
+ DCON_REG_HSYNC_WIDTH= 0x04,
+ DCON_REG_VRES = 0x05,
+ DCON_REG_VTOTAL = 0x06,
+ DCON_REG_VSYNC_WIDTH= 0x07,
+ DCON_REG_TIMEOUT= 0x08,
+ DCON_REG_SCAN_INT = 0x09,
+ DCON_REG_BRIGHT = 0x0a,
+ DCON_REG_MEM_OPT_A = 0x41,
+ DCON_REG_MEM_OPT_B = 0x42,
+};
+
+/* DCON_REG_MODE */
+enum {
+ MODE_PASSTHRU = BIT(0),
+ MODE_SLEEP = BIT(1),
+ MODE_SLEEP_AUTO = BIT(2),
+ MODE_BL_ENABLE = BIT(3),
+ MODE_BLANK = BIT(4),
+
[PATCH v7 1/2] dt-bindings: display: himax, hx8837: Add Himax HX8837 bindings
Himax HX8837 is a secondary display controller used to drive the panel
on OLPC platforms.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v6:
(All based on feedback from Laurent Pinchart)
- Add power supplies
- Make load/stat-gpios optional
- Fix whitespace errors
- Use decimal constants instead of hex in example where appropriate
- Terminate the bindings with "..." end-of-document marker
Changes since v4:
- Rob's Reviewed-by
Changes since v3:
- Moved to bindings/display/
- Added the ports
- Converted to YAML
- Removed Pavel's Ack, because the changes are substantial
Changes since v2:
- s/betweend/between/
Changes since v1:
- s/load-gpio/load-gpios/
- Use interrupt bindings instead of gpio for the IRQ
.../bindings/display/bridge/himax,hx8837.yaml | 108 ++
1 file changed, 108 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
new file mode 100644
index 0..e9e21a3447088
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2018,2019,2020,2021 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HX8837 Display Controller Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: himax,hx8837
+
+ reg:
+const: 0xd
+
+ load-gpios:
+maxItems: 1
+description: GPIO specifier of DCON_LOAD pin (active high)
+
+ stat-gpios:
+minItems: 2
+description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active high)
+
+ interrupts:
+maxItems: 1
+description: Interrupt specifier of DCON_IRQ pin (edge falling)
+
+ vddp18-supply:
+description: Regulator for 1.8V display interface I/O power.
+
+ vddm25-supply:
+description: Regulator for 2.5V SDRAM I/O power.
+
+ vdd33-supply:
+description: Regulator for 3.3V digital I/O power.
+
+ vddk18-supply:
+description: Regulator for 1.8V internal core power.
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ Video port connected to the panel.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lcd-controller@d {
+compatible = "himax,hx8837";
+reg = <0x0d>;
+stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
+ < 101 GPIO_ACTIVE_HIGH>;
+load-gpios = < 142 GPIO_ACTIVE_HIGH>;
+interrupts = < 124 IRQ_TYPE_EDGE_FALLING>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dcon_rgb_in: endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+dcon_gettl_out: endpoint {
+remote-endpoint = <_dettl_in>;
+};
+};
+};
+};
+};
+
+...
--
2.29.2
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Re: [PATCH v4 0/3] Generic USB Display driver
On Wed, Jan 20, 2021 at 06:00:30PM +0100, Noralf Trønnes wrote: > Hi, > > A while back I had the idea to turn a Raspberry Pi Zero into a $5 > USB to HDMI/SDTV/DSI/DPI display adapter. > > The reason for calling it 'Generic' is so anyone can make a USB > display/adapter against this driver, all that's needed is to add a USB > vid:pid. > > Unfortunately I've had some compounding health problems that have > severally limited the time I can spend in front of a computer. For this > reason I've decided to keep the gadget driver out-of-tree and focus on > getting the host driver merged first. > > See the wiki[1] for more information and images for the Raspberry Pi > Zero/4. > > One big change this time is that I've followed Peter Stuge's advice to > not let DRM stuff leak into the USB protocol. This has made the protocol > easier to understand just from reading the header file. > > Noralf. > > [1] https://github.com/notro/gud/wiki The patch set: Tested-by: Lubomir Rintel Works like a charm with this board [1], though it didn't impress the girls as much as I hoped. Code here [2], picture here [3]. [1] https://www.banggood.com/LILYGO-TTGO-T-Display-GD32-RISC-V-32-bit-Core-Minimal-Development-Board-1_14-IPS-p-1652870.html?rmmds=search_warehouse=CN [2] https://github.com/hackerspace/libopencm3-gf32v-examples/commit/7ef51b31b9 [3] https://people.freedesktop.org/~lkundrak/lilygo.jpeg Had to apply a fix for the drm_connector_enum_list[] ommission I mentioned elsewhere, and that I've now noticed you've noted previously. Take care Lubo > > > Noralf Trønnes (3): > drm/uapi: Add USB connector type > drm/probe-helper: Check epoch counter in output_poll_execute() > drm: Add Generic USB Display driver > > MAINTAINERS | 8 + > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile| 1 + > drivers/gpu/drm/drm_probe_helper.c | 7 +- > drivers/gpu/drm/gud/Kconfig | 14 + > drivers/gpu/drm/gud/Makefile| 4 + > drivers/gpu/drm/gud/gud_connector.c | 722 > drivers/gpu/drm/gud/gud_drv.c | 620 > drivers/gpu/drm/gud/gud_internal.h | 148 ++ > drivers/gpu/drm/gud/gud_pipe.c | 472 ++ > include/drm/gud.h | 356 ++ > include/uapi/drm/drm_mode.h | 1 + > 12 files changed, 2354 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/gud/Kconfig > create mode 100644 drivers/gpu/drm/gud/Makefile > create mode 100644 drivers/gpu/drm/gud/gud_connector.c > create mode 100644 drivers/gpu/drm/gud/gud_drv.c > create mode 100644 drivers/gpu/drm/gud/gud_internal.h > create mode 100644 drivers/gpu/drm/gud/gud_pipe.c > create mode 100644 include/drm/gud.h > > -- > 2.23.0 > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 0/3] Generic USB Display driver
On Wed, Jan 20, 2021 at 06:00:30PM +0100, Noralf Trønnes wrote: > Hi, > > A while back I had the idea to turn a Raspberry Pi Zero into a $5 > USB to HDMI/SDTV/DSI/DPI display adapter. > > The reason for calling it 'Generic' is so anyone can make a USB > display/adapter against this driver, all that's needed is to add a USB > vid:pid. > > Unfortunately I've had some compounding health problems that have > severally limited the time I can spend in front of a computer. For this > reason I've decided to keep the gadget driver out-of-tree and focus on > getting the host driver merged first. > > See the wiki[1] for more information and images for the Raspberry Pi > Zero/4. > > One big change this time is that I've followed Peter Stuge's advice to > not let DRM stuff leak into the USB protocol. This has made the protocol > easier to understand just from reading the header file. Welcome back! I'm happy to see this patch set back on track. I've now started putting together something that would work with GUD on Lilygo T-Display-GD32, but it blew up in my face immediately (I had CONFIG_DEBUG_SPINLOCK turned on): [ 42.064362] usb 1-1.2: new full-speed USB device number 6 using mv-ehci [ 42.228048] usb 1-1.2: New USB device found, idVendor=1d50, idProduct=614d, bcdDevice= 1.00 [ 42.236812] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 42.254298] usb 1-1.2: Product: LCD Display Interface [ 42.259771] usb 1-1.2: Manufacturer: Lubomir Rintel [ 42.266395] usb 1-1.2: SerialNumber: 3736030061294139 [ 42.284771] BUG: spinlock bad magic on CPU#0, kworker/0:0/5 [ 42.290394] 8<--- cut here --- [ 42.293415] Unable to handle kernel NULL pointer dereference at virtual address 031c [ 42.301417] pgd = e351f484 [ 42.304184] [031c] *pgd= [ 42.307826] Internal error: Oops: 15 [#1] PREEMPT SMP ARM [ 42.313250] Modules linked in: [ 42.316208] CPU: 0 PID: 5 Comm: kworker/0:0 Not tainted 5.11.0-rc4-00113-g8c3d05f1939a #1274 [ 42.324729] Hardware name: Marvell MMP3 [ 42.328540] Workqueue: usb_hub_wq hub_event [ 42.332759] PC is at spin_dump+0x5c/0x88 [ 42.336556] LR is at spin_dump+0x48/0x88 [ 42.340644] pc : []lr : []psr: 200f0193 [ 42.346895] sp : c810b910 ip : fp : c1107b40 [ 42.352039] r10: c005 r9 : r8 : 001f [ 42.357238] r7 : r6 : 0438 r5 : c14456f8 r4 : 0014 [ 42.363837] r3 : 044c r2 : c1091500 r1 : eefb8540 r0 : 002f [ 42.370351] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none [ 42.377456] Control: 10c5387d Table: 09f0806a DAC: 0051 [ 42.383286] Process kworker/0:0 (pid: 5, stack limit = 0xda2575c6) [ 42.389392] Stack: (0xc810b910 to 0xc810c000) [ 42.393801] b900: 0005 c14456f8 c14456f8 c058f244 [ 42.401916] b920: a00f0113 c018b1cc c14456f8 c058f244 a00f0113 c0c4e454 0001 [ 42.410117] b940: c058f244 0003 c9d1d800 ca01f000 7fff c058f244 200f0113 0001 [ 42.418267] b960: 0cc0 c810a000 0dc0 c1053148 0023 c9d1d814 c14456f8 [ 42.426399] b980: 0003 fcee162a 0cc0 c9d1d800 [ 42.434607] b9a0: ca01f000 c810a000 0014 c9d1d814 c14452e0 ca01f42c c0669f84 [ 42.442749] b9c0: c0668d98 0dc0 0dc0 c126dd90 0dc0 ca01f24c [ 42.450887] b9e0: 0410 c14456f8 ca01f000 fcee162a c9d1d800 [ 42.459087] ba00: 0001 ca01f000 ca01fac8 0002 c06965e0 [ 42.467220] ba20: c03027b0 c8001600 0001 c810a000 fcee162a fcee162a [ 42.475373] ba40: a00f0113 c9d25880 c0694894 a00f0113 c800 7820 fcee162a [ 42.483470] ba60: 0002 ca01f000 c9ae7800 c810a000 0001 c9d258c0 ca01fac8 [ 42.491685] ba80: 0002 c0694a14 0002 c0d68608 0001 c0186460 [ 42.499882] baa0: c9d65878 c9d25940 c0d51198 0001 36314752 34325241 [ 42.508038] bac0: 0001 c9ae7820 34325258 c9ae7800 c810a000 0022 c0c4e6b8 [ 42.516202] bae0: c98b1a00 fcee162a c9d65878 c9ae7820 c9d65878 c1446198 c9ae7800 c9d65800 [ 42.524347] bb00: 0001 c0d68618 ffed c07eae44 c07ead58 c9ae7820 c18004e0 [ 42.532534] bb20: c18004e8 c1446198 c14ab308 0022 c069f124 c9ae79cc 0001 [ 42.540557] bb40: c9ae78dc c14555b0 c9ae7820 c14ab308 c1446198 c069fba4 0001 [ 42.548847] bb60: c1800494 c14555b0 c069f5bc 0001 c069fb78 c810bbc4 [ 42.556874] bb80: c810a000 0001 c1800494 c14555b0 c069cefc c14555b0 c8a964e4 [ 42.565179] bba0: c8e90d58 fcee162a c9d65934 c9ae7820 c810a000 c9ae7820 c9ae7864 c069
[PATCH libdrm 0/3] tests/etnaviv_2d_test: some test improvements
Hi, patches chained to this message contains changes I've found useful when testing whether 2d rendering works well with the etnaviv driver on my platform. Perhaps they're useful enough for merging upstream. Thanks Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH libdrm 2/3] tests/etnaviv_2d_test: pick the 2D core
Run the test on a core capable of 2D rendering instead of hardcoding to
core zero.
Signed-off-by: Lubomir Rintel
---
tests/etnaviv/etnaviv_2d_test.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/tests/etnaviv/etnaviv_2d_test.c b/tests/etnaviv/etnaviv_2d_test.c
index eb9dfa59..a75a4a89 100644
--- a/tests/etnaviv/etnaviv_2d_test.c
+++ b/tests/etnaviv/etnaviv_2d_test.c
@@ -161,6 +161,8 @@ int main(int argc, char *argv[])
drmVersionPtr version;
int fd, ret = 0;
+ uint64_t feat;
+ int core = 0;
if (argc < 2) {
fprintf(stderr, "Usage: %s /dev/dri/\n", argv[0]);
@@ -190,13 +192,28 @@ int main(int argc, char *argv[])
goto out;
}
- /* TODO: we assume that core 0 is a 2D capable one */
- gpu = etna_gpu_new(dev, 0);
- if (!gpu) {
- perror("etna_gpu_new");
- ret = 3;
- goto out_device;
- }
+ do {
+ gpu = etna_gpu_new(dev, core);
+ if (!gpu) {
+ perror("etna_gpu_new");
+ ret = 3;
+ goto out_device;
+ }
+
+ if (etna_gpu_get_param(gpu, ETNA_GPU_FEATURES_0, )) {
+ perror("etna_gpu_get_param");
+ ret = 4;
+ goto out_device;
+ }
+
+ if ((feat & (1 << 9)) == 0) {
+ /* GPU not 2D capable. */
+ etna_gpu_del(gpu);
+ gpu = NULL;
+ }
+
+ core++;
+ } while (!gpu);
pipe = etna_pipe_new(gpu, ETNA_PIPE_2D);
if (!pipe) {
--
2.28.0
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[PATCH libdrm 1/3] tests/etnaviv_2d_test: explain the errors
Just so that it's obvious what failed and why.
Signed-off-by: Lubomir Rintel
---
tests/etnaviv/etnaviv_2d_test.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tests/etnaviv/etnaviv_2d_test.c b/tests/etnaviv/etnaviv_2d_test.c
index 8dd77b66..eb9dfa59 100644
--- a/tests/etnaviv/etnaviv_2d_test.c
+++ b/tests/etnaviv/etnaviv_2d_test.c
@@ -162,9 +162,16 @@ int main(int argc, char *argv[])
drmVersionPtr version;
int fd, ret = 0;
- fd = open(argv[1], O_RDWR);
- if (fd < 0)
+ if (argc < 2) {
+ fprintf(stderr, "Usage: %s /dev/dri/\n", argv[0]);
return 1;
+ }
+
+ fd = open(argv[1], O_RDWR);
+ if (fd < 0) {
+ perror(argv[1]);
+ return 1;
+ }
version = drmGetVersion(fd);
if (version) {
@@ -178,6 +185,7 @@ int main(int argc, char *argv[])
dev = etna_device_new(fd);
if (!dev) {
+ perror("etna_device_new");
ret = 2;
goto out;
}
@@ -185,18 +193,21 @@ int main(int argc, char *argv[])
/* TODO: we assume that core 0 is a 2D capable one */
gpu = etna_gpu_new(dev, 0);
if (!gpu) {
+ perror("etna_gpu_new");
ret = 3;
goto out_device;
}
pipe = etna_pipe_new(gpu, ETNA_PIPE_2D);
if (!pipe) {
+ perror("etna_pipe_new");
ret = 4;
goto out_gpu;
}
bmp = etna_bo_new(dev, bmp_size, ETNA_BO_UNCACHED);
if (!bmp) {
+ perror("etna_bo_new");
ret = 5;
goto out_pipe;
}
@@ -204,6 +215,7 @@ int main(int argc, char *argv[])
stream = etna_cmd_stream_new(pipe, 0x300, NULL, NULL);
if (!stream) {
+ perror("etna_cmd_stream_new");
ret = 6;
goto out_bo;
}
--
2.28.0
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[PATCH libdrm 3/3] tests/etnaviv_2d_test: check whether the rendering is correct
Instead of always dumping the rendered picture, check whether it matches
the expectations. This makes more sense for automated testing.
Retain the ability to dump the picture instead of checking it when a
file name is given as an argument. This also removes use of a hardcoded
file name in a world writable directory, which is an unsafe thing to
do anyway.
Signed-off-by: Lubomir Rintel
---
tests/etnaviv/etnaviv_2d_test.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/tests/etnaviv/etnaviv_2d_test.c b/tests/etnaviv/etnaviv_2d_test.c
index a75a4a89..9fcdae18 100644
--- a/tests/etnaviv/etnaviv_2d_test.c
+++ b/tests/etnaviv/etnaviv_2d_test.c
@@ -147,6 +147,27 @@ static void gen_cmd_stream(struct etna_cmd_stream *stream,
struct etna_bo *bmp,
etna_set_state(stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_PE2D);
}
+int etna_check_image(uint32_t *p, int width, int height)
+{
+ int i;
+ uint32_t expected;
+
+ for (i = 0; i < width * height; i++) {
+ if (i%8 < 4 && i%(width*8) < width*4 && i%width < 8*16 && i <
width*8*16)
+ expected = 0xff40ff40;
+ else
+ expected = 0x;
+
+ if (p[i] != expected) {
+ fprintf(stderr, "Offset %d: expected: 0x%08x, got:
0x%08x\n",
+ i, expected, p[i]);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
int main(int argc, char *argv[])
{
const int width = 256;
@@ -165,7 +186,7 @@ int main(int argc, char *argv[])
int core = 0;
if (argc < 2) {
- fprintf(stderr, "Usage: %s /dev/dri/\n", argv[0]);
+ fprintf(stderr, "Usage: %s /dev/dri/ []\n",
argv[0]);
return 1;
}
@@ -242,7 +263,11 @@ int main(int argc, char *argv[])
etna_cmd_stream_finish(stream);
- bmp_dump32(etna_bo_map(bmp), width, height, false, "/tmp/etna.bmp");
+ if (argc > 2)
+ bmp_dump32(etna_bo_map(bmp), width, height, false, argv[2]);
+
+ if (etna_check_image(etna_bo_map(bmp), width, height))
+ ret = 7;
etna_cmd_stream_del(stream);
--
2.28.0
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Re: [PATCH v6 1/2] dt-bindings: display: himax,hx8837: Add Himax HX8837 bindings
On Sun, Nov 01, 2020 at 06:39:22PM +0200, Laurent Pinchart wrote:
> Hi Lubomir,
>
> Thank you for the patch.
Thanks for the message. Some responses inline below.
> On Fri, Oct 30, 2020 at 04:07:59AM +0100, Lubomir Rintel wrote:
> > Himax HX8837 is a secondary display controller used to drive the panel
> > on OLPC platforms.
> >
> > Signed-off-by: Lubomir Rintel
> > Reviewed-by: Rob Herring
> >
> > ---
> > Changes since v4:
> > - Rob's Reviewed-by
> >
> > Changes since v3:
> > - Moved to bindings/display/
> > - Added the ports
> > - Converted to YAML
> > - Removed Pavel's Ack, because the changes are substantial
> >
> > Changes since v2:
> > - s/betweend/between/
> >
> > Changes since v1:
> > - s/load-gpio/load-gpios/
> > - Use interrupt bindings instead of gpio for the IRQ
> >
> > .../bindings/display/bridge/himax,hx8837.yaml | 96 +++
> > 1 file changed, 96 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > new file mode 100644
> > index 0..f5b0a00f5089d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > @@ -0,0 +1,96 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (C) 2018,2019,2020 Lubomir Rintel
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: HX8837 Display Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Lubomir Rintel
> > +
> > +properties:
> > + compatible:
> > +const: himax,hx8837
> > +
> > + reg:
> > +const: 0xd
> > +
> > + load-gpios:
> > +maxItems: 1
> > +description: GPIO specifier of DCON_LOAD pin (active high)
> > +
> > + stat-gpios:
> > +minItems: 2
> > +description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active
> > high)
> > +
> > + interrupts:
> > +maxItems: 1
> > +description: Interrupt specifier of DCON_IRQ pin (edge falling)
> > +
> > + ports:
> > +type: object
> > +
> > +properties:
> > + port@0:
> > +type: object
> > +description: |
> > + Video port for RGB input.
> > +
> > + port@1:
> > +type: object
> > +description: |
> > + Video port connected to the panel.
> > +
> > +required:
> > + - port@0
> > + - port@1
>
> No regulators ?
There are four.
On the OLPC platform they're controlled together by the EC.
I've added the supplies to the EC driver and looked into supporting them
properly in the driver and am finding it somehow tricky to do it properly.
I couldn't figure out what is the proper place to enable and disable the
regulators. Also drm_bridge_remove() just mercilessly tearing down the
bridge without ensuring it's not used anymore doesn't help us on driver
unbind.
I'm wondering if it's okay if I leave the driver without explicit
support for the power supplies for now, assuming that EC just takes
care of enabling the power and never disable it?
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - load-gpios
> > + - stat-gpios
>
> Do stat-gpios need to be mandatory ? The driver in patch 2/2 doesn't
> seem to use them, could we have boards where those signals are not
> connected to GPIOs ?
Perhaps not, in theory.
Pretty sure the OLPC machines are the only ones that utilize this
silicon though.
> > + - interrupts
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +
> > +i2c {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +
>
> Could you please avoid spaces or tabs at end of lines ? There are three
> other occurrences below.
Ugh, I was sure I ran checkpatch.pl, but apparently not.
Sorry for that.
> > +lcd-controller@d {
> > +compatible = "himax,hx8837";
> > +reg = <0x0d>;
> > +stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
> > +
Re: [PATCH v6 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Hello Sam,
thanks for your response.
On Sat, Oct 31, 2020 at 09:01:37AM +0100, Sam Ravnborg wrote:
> Hi Lubomir.
>
> On Fri, Oct 30, 2020 at 04:08:00AM +0100, Lubomir Rintel wrote:
> > Himax HX8837 is used to drive the LCD panel on OLPC platforms.
> >
> > It controls the panel backlight and is able to refresh it when the LCD
> > controller (and the rest of the plaform) is powered off.
> >
> > It also converts regular RGB color data from the LCDC so that it looks
> > reasonable on the OLPC LCD panel with a monochromatic layer on top of a
> > layer that can either reflect light (b/w sunlight readable mode) or light
> > pattern of red, green and blue pixels.
> >
> > At this point, the driver is rather basic. The self-refresh mode is not
> > supported. There's no way of independently controlling the color swizzling,
> > antialiasing or b/w conversion, but it probably isn't too useful either.
> >
> > There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
> > in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
> > DRM, so this driver doesn't replace the other one yet.
> >
> > Signed-off-by: Lubomir Rintel
> >
> > ---
> > Changes since v5:
> > (All based on feedback from Sam Ravnborg)
> > - Fix indentation in Kconfig
> > - Sort #includes
> > - Use a constant for max brightness instead of a literal
> > - Remove struct drm_panel from priv data
> > - Use dev_err() instead of DRM_ERROR
> > - Replace direct use of backlight props.brightness with
> > backlight_get_brightness()
> > - Document sentinels with { /* sentinel */ }
> > - Remove unsetting of panel->backlight
>
> Thanks, I missed a few things during the last round, so here is a few
> more comments. Only very trivial things but lets get them fixed before
> we add the driver to drm-misc-next.
>
> Sam
>
> >
> > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> > index ef91646441b16..881780719af7c 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR
> > on ARM-based platforms. Saying Y here when this driver is not needed
> > will not cause any issue.
> >
> > +config DRM_HIMAX_HX8837
> > + tristate "HiMax HX8837 OLPC Display Controller"
> > + depends on OF
> > + depends on OLPC || ARCH_MMP || COMPILE_TEST
> > + select DRM_KMS_HELPER
> > + select BACKLIGHT_LCD_SUPPORT
> Unknown symbol - "git grep BACKLIGHT_LCD_SUPPORT" only turned up one
> unrelated hit.
>
> > + select BACKLIGHT_CLASS_DEVICE
> Please use a depends - using select on a symbol with a prompt is always
> wrong. Yeah, I know you then need to enable backlight to see this
> driver. Sorry, but this is the best we can do now.
> Many other drivers can cope with depends here.
This results in a dependency loop:
drivers/video/fbdev/Kconfig:12:error: recursive dependency detected!
drivers/video/fbdev/Kconfig:12: symbol FB is selected by DRM_KMS_FB_HELPER
drivers/gpu/drm/Kconfig:80: symbol DRM_KMS_FB_HELPER depends on
DRM_KMS_HELPER
drivers/gpu/drm/Kconfig:74: symbol DRM_KMS_HELPER is selected by
DRM_HIMAX_HX8837
drivers/gpu/drm/bridge/Kconfig:51: symbol DRM_HIMAX_HX8837 depends on
BACKLIGHT_CLASS_DEVICE
drivers/video/backlight/Kconfig:143:symbol BACKLIGHT_CLASS_DEVICE is
selected by FB_BACKLIGHT
drivers/video/fbdev/Kconfig:187:symbol FB_BACKLIGHT depends on FB
Unfortunately I have no idea how to resolve it at the moment.
I suppose I can look further into it if necessary. Or is it okay if I
leave it at select BACKLIGHT_CLASS_DEVICE for now?
> > + help
> > + Enable support for HiMax HX8837 Display Controller as found in the
> > + OLPC XO laptops.
> > +
> > + If your laptop doesn't have green ears, say "N"
> I like this last comment :-)
>
> > +
> > config DRM_LONTIUM_LT9611
> > tristate "Lontium LT9611 DSI/HDMI bridge"
> > select SND_SOC_HDMI_CODEC if SND_SOC
> > diff --git a/drivers/gpu/drm/bridge/Makefile
> > b/drivers/gpu/drm/bridge/Makefile
> > index 2b3aff104e466..21f72df3260db 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -2,6 +2,7 @@
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> > obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> > obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
> > +obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
> > obj-$(CONFIG_DRM_LONTI
[PATCH v6 1/2] dt-bindings: display: himax, hx8837: Add Himax HX8837 bindings
Himax HX8837 is a secondary display controller used to drive the panel
on OLPC platforms.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v4:
- Rob's Reviewed-by
Changes since v3:
- Moved to bindings/display/
- Added the ports
- Converted to YAML
- Removed Pavel's Ack, because the changes are substantial
Changes since v2:
- s/betweend/between/
Changes since v1:
- s/load-gpio/load-gpios/
- Use interrupt bindings instead of gpio for the IRQ
.../bindings/display/bridge/himax,hx8837.yaml | 96 +++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
new file mode 100644
index 0..f5b0a00f5089d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2018,2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HX8837 Display Controller Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: himax,hx8837
+
+ reg:
+const: 0xd
+
+ load-gpios:
+maxItems: 1
+description: GPIO specifier of DCON_LOAD pin (active high)
+
+ stat-gpios:
+minItems: 2
+description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active high)
+
+ interrupts:
+maxItems: 1
+description: Interrupt specifier of DCON_IRQ pin (edge falling)
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ Video port connected to the panel.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - load-gpios
+ - stat-gpios
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lcd-controller@d {
+compatible = "himax,hx8837";
+reg = <0x0d>;
+stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
+ < 101 GPIO_ACTIVE_HIGH>;
+load-gpios = < 142 GPIO_ACTIVE_HIGH>;
+interrupts = < 124 IRQ_TYPE_EDGE_FALLING>;
+
+ports {
+#address-cells = <0x01>;
+#size-cells = <0x00>;
+
+port@0 {
+reg = <0x00>;
+dcon_rgb_in: endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <0x01>;
+dcon_gettl_out: endpoint {
+remote-endpoint = <_dettl_in>;
+};
+};
+};
+};
+};
--
2.28.0
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[PATCH v6 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Himax HX8837 is used to drive the LCD panel on OLPC platforms.
It controls the panel backlight and is able to refresh it when the LCD
controller (and the rest of the plaform) is powered off.
It also converts regular RGB color data from the LCDC so that it looks
reasonable on the OLPC LCD panel with a monochromatic layer on top of a
layer that can either reflect light (b/w sunlight readable mode) or light
pattern of red, green and blue pixels.
At this point, the driver is rather basic. The self-refresh mode is not
supported. There's no way of independently controlling the color swizzling,
antialiasing or b/w conversion, but it probably isn't too useful either.
There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
DRM, so this driver doesn't replace the other one yet.
Signed-off-by: Lubomir Rintel
---
Changes since v5:
(All based on feedback from Sam Ravnborg)
- Fix indentation in Kconfig
- Sort #includes
- Use a constant for max brightness instead of a literal
- Remove struct drm_panel from priv data
- Use dev_err() instead of DRM_ERROR
- Replace direct use of backlight props.brightness with
backlight_get_brightness()
- Document sentinels with { /* sentinel */ }
- Remove unsetting of panel->backlight
Changes since v3:
- Added this patch, in place of a driver derived from
drivers/staging/olpc_dcon. Compared to the previous one this
implements the bare minimum, without the fancy stuff such as
self-refresh that need more work/thinking.
drivers/gpu/drm/bridge/Kconfig| 13 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/himax-hx8837.c | 330 ++
3 files changed, 344 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index ef91646441b16..881780719af7c 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR
on ARM-based platforms. Saying Y here when this driver is not needed
will not cause any issue.
+config DRM_HIMAX_HX8837
+ tristate "HiMax HX8837 OLPC Display Controller"
+ depends on OF
+ depends on OLPC || ARCH_MMP || COMPILE_TEST
+ select DRM_KMS_HELPER
+ select BACKLIGHT_LCD_SUPPORT
+ select BACKLIGHT_CLASS_DEVICE
+ help
+ Enable support for HiMax HX8837 Display Controller as found in the
+ OLPC XO laptops.
+
+ If your laptop doesn't have green ears, say "N"
+
config DRM_LONTIUM_LT9611
tristate "Lontium LT9611 DSI/HDMI bridge"
select SND_SOC_HDMI_CODEC if SND_SOC
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 2b3aff104e466..21f72df3260db 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
+obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c
b/drivers/gpu/drm/bridge/himax-hx8837.c
new file mode 100644
index 0..f472e16cc331d
--- /dev/null
+++ b/drivers/gpu/drm/bridge/himax-hx8837.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * HiMax HX8837 Display Controller Driver
+ *
+ * Datasheet: http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define bridge_to_hx8837_priv(x) \
+ container_of(x, struct hx8837_priv, bridge)
+
+/* DCON registers */
+enum {
+ DCON_REG_ID = 0x00,
+ DCON_REG_MODE = 0x01,
+ DCON_REG_HRES = 0x02,
+ DCON_REG_HTOTAL = 0x03,
+ DCON_REG_HSYNC_WIDTH= 0x04,
+ DCON_REG_VRES = 0x05,
+ DCON_REG_VTOTAL = 0x06,
+ DCON_REG_VSYNC_WIDTH= 0x07,
+ DCON_REG_TIMEOUT= 0x08,
+ DCON_REG_SCAN_INT = 0x09,
+ DCON_REG_BRIGHT = 0x0a,
+ DCON_REG_MEM_OPT_A = 0x41,
+ DCON_REG_MEM_OPT_B = 0x42,
+};
+
+/* DCON_REG_MODE */
+enum {
+ MODE_PASSTHRU = BIT(0),
+ MODE_SLEEP = BIT(1),
+ MODE_SLEEP_AUTO = BIT(2),
+ MODE_BL_ENABLE = BIT(3),
+ MODE_BLANK = BIT(4),
+ MODE_CSWIZZLE = BIT(5),
+ MODE_COL_AA = BIT(6),
+ MODE_MONO_LUMA = BIT(7),
+ MODE_SCAN_INT = BIT(8),
+
Re: [RESEND PATCH v5 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Hello Sam, On Fri, Oct 16, 2020 at 10:07:34PM +0200, Sam Ravnborg wrote: > Hi Lubomir. > > On Sat, Sep 26, 2020 at 02:07:19AM +0200, Lubomir Rintel wrote: > > Himax HX8837 is used to drive the LCD panel on OLPC platforms. > > > > It controls the panel backlight and is able to refresh it when the LCD > > controller (and the rest of the plaform) is powered off. > > > > It also converts regular RGB color data from the LCDC so that it looks > > reasonable on the OLPC LCD panel with a monochromatic layer on top of a > > layer that can either reflect light (b/w sunlight readable mode) or light > > pattern of red, green and blue pixels. > > > > At this point, the driver is rather basic. The self-refresh mode is not > > supported. There's no way of independently controlling the color swizzling, > > antialiasing or b/w conversion, but it probably isn't too useful either. > > > > There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75 > > in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize > > DRM, so this driver doesn't replace the other one yet. > > > > Signed-off-by: Lubomir Rintel > > A little feedback follows. > > Sam > > > > > --- > > Changes since v3: > > - Added this patch, in place of a driver derived from > > drivers/staging/olpc_dcon. Compared to the previous one this > > implements the bare minimum, without the fancy stuff such as > > self-refresh that need more work/thinking. > > > > drivers/gpu/drm/bridge/Kconfig| 13 ++ > > drivers/gpu/drm/bridge/Makefile | 1 + > > drivers/gpu/drm/bridge/himax-hx8837.c | 325 ++ > > 3 files changed, 339 insertions(+) > > create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > > index ef91646441b16..6a923dd56c1d5 100644 > > --- a/drivers/gpu/drm/bridge/Kconfig > > +++ b/drivers/gpu/drm/bridge/Kconfig > > @@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR > > on ARM-based platforms. Saying Y here when this driver is not needed > > will not cause any issue. > > > > +config DRM_HIMAX_HX8837 > > +tristate "HiMax HX8837 OLPC Display Controller" > > + depends on OF > > + depends on OLPC || ARCH_MMP || COMPILE_TEST > > + select DRM_KMS_HELPER > > +select BACKLIGHT_LCD_SUPPORT > > +select BACKLIGHT_CLASS_DEVICE > > +help > > + Enable support for HiMax HX8837 Display Controller as found in > > the > > + OLPC XO laptops. > > + > > + If your laptop doesn't have green ears, say "N" > > There is a mixture of tabs and spaces for indent - use tabs only (and > tabs + 2 spaces for the help text). > > > > + > > config DRM_LONTIUM_LT9611 > > tristate "Lontium LT9611 DSI/HDMI bridge" > > select SND_SOC_HDMI_CODEC if SND_SOC > > diff --git a/drivers/gpu/drm/bridge/Makefile > > b/drivers/gpu/drm/bridge/Makefile > > index 2b3aff104e466..21f72df3260db 100644 > > --- a/drivers/gpu/drm/bridge/Makefile > > +++ b/drivers/gpu/drm/bridge/Makefile > > @@ -2,6 +2,7 @@ > > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o > > obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o > > obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o > > +obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o > Please add in alphabetical order. > > > obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o > > obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o > > obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += > > megachips-stdp-ge-b850v3-fw.o > > diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c > > b/drivers/gpu/drm/bridge/himax-hx8837.c > > new file mode 100644 > > index 0..1e97fcb8ce505 > > --- /dev/null > > +++ b/drivers/gpu/drm/bridge/himax-hx8837.c > > @@ -0,0 +1,325 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later > > +/* > > + * HiMax HX8837 Display Controller Driver > > + * > > + * Datasheet: > > http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf > > + * > > + * Copyright (C) 2020 Lubomir Rintel > > + */ > > + > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > In blocks are good but please add them in alphabetica
[RESEND PATCH v5 1/2] dt-bindings: display: himax, hx8837: Add Himax HX8837 bindings
Himax HX8837 is a secondary display controller used to drive the panel
on OLPC platforms.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v4:
- Rob's Reviewed-by
Changes since v3:
- Moved to bindings/display/
- Added the ports
- Converted to YAML
- Removed Pavel's Ack, because the changes are substantial
Changes since v2:
- s/betweend/between/
Changes since v1:
- s/load-gpio/load-gpios/
- Use interrupt bindings instead of gpio for the IRQ
.../bindings/display/bridge/himax,hx8837.yaml | 96 +++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
new file mode 100644
index 0..f5b0a00f5089d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2018,2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HX8837 Display Controller Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: himax,hx8837
+
+ reg:
+const: 0xd
+
+ load-gpios:
+maxItems: 1
+description: GPIO specifier of DCON_LOAD pin (active high)
+
+ stat-gpios:
+minItems: 2
+description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active high)
+
+ interrupts:
+maxItems: 1
+description: Interrupt specifier of DCON_IRQ pin (edge falling)
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ Video port connected to the panel.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - load-gpios
+ - stat-gpios
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lcd-controller@d {
+compatible = "himax,hx8837";
+reg = <0x0d>;
+stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
+ < 101 GPIO_ACTIVE_HIGH>;
+load-gpios = < 142 GPIO_ACTIVE_HIGH>;
+interrupts = < 124 IRQ_TYPE_EDGE_FALLING>;
+
+ports {
+#address-cells = <0x01>;
+#size-cells = <0x00>;
+
+port@0 {
+reg = <0x00>;
+dcon_rgb_in: endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <0x01>;
+dcon_gettl_out: endpoint {
+remote-endpoint = <_dettl_in>;
+};
+};
+};
+};
+};
--
2.26.2
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[RESEND PATCH v5 0/2] Add a Himax HX8837 display controller driver
Hi, please take a look at the patches chained to this messages and consider applying them. They add support for the controller that drives the panel on the OLPC XO laptops. The only change since the previous version is the Reviewed-by tag in DT bindings. Compared to v3 the bindings have been converted to YAML and the driver itself has been rewritten without any fancy features such as the self-refresh so that the bare minimum works before the rest can be figured out. Detailed change logs are in individual patches. Tested on an OLPC XO-1.75 laptop. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v5 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Himax HX8837 is used to drive the LCD panel on OLPC platforms.
It controls the panel backlight and is able to refresh it when the LCD
controller (and the rest of the plaform) is powered off.
It also converts regular RGB color data from the LCDC so that it looks
reasonable on the OLPC LCD panel with a monochromatic layer on top of a
layer that can either reflect light (b/w sunlight readable mode) or light
pattern of red, green and blue pixels.
At this point, the driver is rather basic. The self-refresh mode is not
supported. There's no way of independently controlling the color swizzling,
antialiasing or b/w conversion, but it probably isn't too useful either.
There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
DRM, so this driver doesn't replace the other one yet.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Added this patch, in place of a driver derived from
drivers/staging/olpc_dcon. Compared to the previous one this
implements the bare minimum, without the fancy stuff such as
self-refresh that need more work/thinking.
drivers/gpu/drm/bridge/Kconfig| 13 ++
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/himax-hx8837.c | 325 ++
3 files changed, 339 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index ef91646441b16..6a923dd56c1d5 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR
on ARM-based platforms. Saying Y here when this driver is not needed
will not cause any issue.
+config DRM_HIMAX_HX8837
+tristate "HiMax HX8837 OLPC Display Controller"
+ depends on OF
+ depends on OLPC || ARCH_MMP || COMPILE_TEST
+ select DRM_KMS_HELPER
+select BACKLIGHT_LCD_SUPPORT
+select BACKLIGHT_CLASS_DEVICE
+help
+ Enable support for HiMax HX8837 Display Controller as found in the
+ OLPC XO laptops.
+
+ If your laptop doesn't have green ears, say "N"
+
config DRM_LONTIUM_LT9611
tristate "Lontium LT9611 DSI/HDMI bridge"
select SND_SOC_HDMI_CODEC if SND_SOC
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 2b3aff104e466..21f72df3260db 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
+obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c
b/drivers/gpu/drm/bridge/himax-hx8837.c
new file mode 100644
index 0..1e97fcb8ce505
--- /dev/null
+++ b/drivers/gpu/drm/bridge/himax-hx8837.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * HiMax HX8837 Display Controller Driver
+ *
+ * Datasheet: http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define bridge_to_hx8837_priv(x) \
+ container_of(x, struct hx8837_priv, bridge)
+
+/* DCON registers */
+enum {
+ DCON_REG_ID = 0x00,
+ DCON_REG_MODE = 0x01,
+ DCON_REG_HRES = 0x02,
+ DCON_REG_HTOTAL = 0x03,
+ DCON_REG_HSYNC_WIDTH= 0x04,
+ DCON_REG_VRES = 0x05,
+ DCON_REG_VTOTAL = 0x06,
+ DCON_REG_VSYNC_WIDTH= 0x07,
+ DCON_REG_TIMEOUT= 0x08,
+ DCON_REG_SCAN_INT = 0x09,
+ DCON_REG_BRIGHT = 0x0a,
+ DCON_REG_MEM_OPT_A = 0x41,
+ DCON_REG_MEM_OPT_B = 0x42,
+};
+
+/* DCON_REG_MODE */
+enum {
+ MODE_PASSTHRU = BIT(0),
+ MODE_SLEEP = BIT(1),
+ MODE_SLEEP_AUTO = BIT(2),
+ MODE_BL_ENABLE = BIT(3),
+ MODE_BLANK = BIT(4),
+ MODE_CSWIZZLE = BIT(5),
+ MODE_COL_AA = BIT(6),
+ MODE_MONO_LUMA = BIT(7),
+ MODE_SCAN_INT = BIT(8),
+ MODE_CLOCKDIV = BIT(9),
+ MODE_DEBUG = BIT(14),
+ MODE_SELFTEST = BIT(15),
+};
+
+struct hx8837_priv {
+ struct regmap *regmap;
+ struct gpio_desc *load_gpio;
+
+ struct drm_bridge *panel_bridge;
+ struct drm_panel *panel;
+ struct drm_bridge bridge;
+};
+
+static int hx8837_bridge_attach(struct drm_bridge *bridge,
+
[PATCH v5 0/2] Add a Himax HX8837 display controller driver
Hi, please take a look at the patches chained to this messages and consider applying them. They add support for the controller that drives the panel on the OLPC XO laptops. The only change since the previous version is the Reviewed-by tag in DT bindings. Compared to v3 the bindings have been converted to YAML and the driver itself has been rewritten without any fancy features such as the self-refresh so that the bare minimum works before the rest can be figured out. Detailed change logs are in individual patches. Tested on an OLPC XO-1.75 laptop. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Himax HX8837 is used to drive the LCD panel on OLPC platforms.
It controls the panel backlight and is able to refresh it when the LCD
controller (and the rest of the plaform) is powered off.
It also converts regular RGB color data from the LCDC so that it looks
reasonable on the OLPC LCD panel with a monochromatic layer on top of a
layer that can either reflect light (b/w sunlight readable mode) or light
pattern of red, green and blue pixels.
At this point, the driver is rather basic. The self-refresh mode is not
supported. There's no way of independently controlling the color swizzling,
antialiasing or b/w conversion, but it probably isn't too useful either.
There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
DRM, so this driver doesn't replace the other one yet.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Added this patch, in place of a driver derived from
drivers/staging/olpc_dcon. Compared to the previous one this
implements the bare minimum, without the fancy stuff such as
self-refresh that need more work/thinking.
drivers/gpu/drm/bridge/Kconfig| 13 ++
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/himax-hx8837.c | 325 ++
3 files changed, 339 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 43271c21d3fce..df30d61c3fee1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR
on ARM-based platforms. Saying Y here when this driver is not needed
will not cause any issue.
+config DRM_HIMAX_HX8837
+tristate "HiMax HX8837 OLPC Display Controller"
+ depends on OF
+ depends on OLPC || ARCH_MMP || COMPILE_TEST
+ select DRM_KMS_HELPER
+select BACKLIGHT_LCD_SUPPORT
+select BACKLIGHT_CLASS_DEVICE
+help
+ Enable support for HiMax HX8837 Display Controller as found in the
+ OLPC XO laptops.
+
+ If your laptop doesn't have green ears, say "N"
+
config DRM_LVDS_CODEC
tristate "Transparent LVDS encoders and decoders support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index d63d4b7e43473..70d97c84382d5 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
+obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c
b/drivers/gpu/drm/bridge/himax-hx8837.c
new file mode 100644
index 0..1e97fcb8ce505
--- /dev/null
+++ b/drivers/gpu/drm/bridge/himax-hx8837.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * HiMax HX8837 Display Controller Driver
+ *
+ * Datasheet: http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define bridge_to_hx8837_priv(x) \
+ container_of(x, struct hx8837_priv, bridge)
+
+/* DCON registers */
+enum {
+ DCON_REG_ID = 0x00,
+ DCON_REG_MODE = 0x01,
+ DCON_REG_HRES = 0x02,
+ DCON_REG_HTOTAL = 0x03,
+ DCON_REG_HSYNC_WIDTH= 0x04,
+ DCON_REG_VRES = 0x05,
+ DCON_REG_VTOTAL = 0x06,
+ DCON_REG_VSYNC_WIDTH= 0x07,
+ DCON_REG_TIMEOUT= 0x08,
+ DCON_REG_SCAN_INT = 0x09,
+ DCON_REG_BRIGHT = 0x0a,
+ DCON_REG_MEM_OPT_A = 0x41,
+ DCON_REG_MEM_OPT_B = 0x42,
+};
+
+/* DCON_REG_MODE */
+enum {
+ MODE_PASSTHRU = BIT(0),
+ MODE_SLEEP = BIT(1),
+ MODE_SLEEP_AUTO = BIT(2),
+ MODE_BL_ENABLE = BIT(3),
+ MODE_BLANK = BIT(4),
+ MODE_CSWIZZLE = BIT(5),
+ MODE_COL_AA = BIT(6),
+ MODE_MONO_LUMA = BIT(7),
+ MODE_SCAN_INT = BIT(8),
+ MODE_CLOCKDIV = BIT(9),
+ MODE_DEBUG = BIT(14),
+ MODE_SELFTEST = BIT(15),
+};
+
+struct hx8837_priv {
+ struct regmap *regmap;
+ struct gpio_desc *load_gpio;
+
+ struct drm_bridge *panel_bridge;
+ struct drm_panel *panel;
+ struct drm_bridge bridge;
+};
+
+static int hx8837_bridge_attach(struct drm_bridge *bridge,
+
[PATCH v5 1/2] dt-bindings: display: himax, hx8837: Add Himax HX8837 bindings
Himax HX8837 is a secondary display controller used to drive the panel
on OLPC platforms.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v4:
- Rob's Reviewed-by
Changes since v3:
- Moved to bindings/display/
- Added the ports
- Converted to YAML
- Removed Pavel's Ack, because the changes are substantial
Changes since v2:
- s/betweend/between/
Changes since v1:
- s/load-gpio/load-gpios/
- Use interrupt bindings instead of gpio for the IRQ
.../bindings/display/bridge/himax,hx8837.yaml | 96 +++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
new file mode 100644
index 0..f5b0a00f5089d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2018,2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HX8837 Display Controller Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: himax,hx8837
+
+ reg:
+const: 0xd
+
+ load-gpios:
+maxItems: 1
+description: GPIO specifier of DCON_LOAD pin (active high)
+
+ stat-gpios:
+minItems: 2
+description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active high)
+
+ interrupts:
+maxItems: 1
+description: Interrupt specifier of DCON_IRQ pin (edge falling)
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ Video port connected to the panel.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - load-gpios
+ - stat-gpios
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lcd-controller@d {
+compatible = "himax,hx8837";
+reg = <0x0d>;
+stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
+ < 101 GPIO_ACTIVE_HIGH>;
+load-gpios = < 142 GPIO_ACTIVE_HIGH>;
+interrupts = < 124 IRQ_TYPE_EDGE_FALLING>;
+
+ports {
+#address-cells = <0x01>;
+#size-cells = <0x00>;
+
+port@0 {
+reg = <0x00>;
+dcon_rgb_in: endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <0x01>;
+dcon_gettl_out: endpoint {
+remote-endpoint = <_dettl_in>;
+};
+};
+};
+};
+};
--
2.26.2
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[PATCH v4 0/2] dt-bindings: display: himax,hx8837: Add Himax HX8837 bindings
(Re-sending the cover letter here, because I left the subject empty and the archive didn't pick it up. Sorry.) Hi, please take a look at the patches chained to this messages and consider applying them. They add support for the controller that drives the panel on the OLPC XO laptops. Compared to the previous version the bindings have been converted to YAML and the driver itself has been rewritten without any fancy features such as the self-refresh so that the bare minimum works before the rest can be figured out. Detailed change logs are in individual patches. Tested on an OLPC XO-1.75 laptop. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/2] drm/panel: simple: Add support for Innolux LS075AT011
This adds support for the Innolux LS075AT011 7.5" 1200x900 panel. There's
no public data sheet for the panel -- the values have been taken from Open
Firmware and the documentation for the display controller that drives
the panel and tested on the OLPC laptop.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/panel/panel-simple.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index cb6550d37e858..dfc69457ed2d4 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2121,6 +2121,30 @@ static const struct panel_desc innolux_g121x1_l03 = {
},
};
+static const struct display_timing innolux_ls075at011_timing = {
+ .pixelclock = { 5600, 5700, 5800 },
+ .hactive = { 1200, 1200, 1200 },
+ .hfront_porch = { 26, 26, 26 },
+ .hback_porch = { 24, 24, 24 },
+ .hsync_len = { 6, 6, 6 },
+ .vactive = { 900, 900, 900 },
+ .vfront_porch = { 4, 4, 4 },
+ .vback_porch = { 5, 5, 5 },
+ .vsync_len = { 3, 3, 3 },
+ .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
+};
+
+static const struct panel_desc innolux_ls075at011 = {
+ .timings = _ls075at011_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 152,
+ .height = 115,
+ },
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
/*
* Datasheet specifies that at 60 Hz refresh rate:
* - total horizontal time: { 1506, 1592, 1716 }
@@ -3907,6 +3931,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "innolux,g121x1-l03",
.data = _g121x1_l03,
+ }, {
+ .compatible = "innolux,ls075at011",
+ .data = _ls075at011,
}, {
.compatible = "innolux,n116bge",
.data = _n116bge,
--
2.26.2
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[PATCH v4 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver
Himax HX8837 is used to drive the LCD panel on OLPC platforms.
It controls the panel backlight and is able to refresh it when the LCD
controller (and the rest of the plaform) is powered off.
It also converts regular RGB color data from the LCDC so that it looks
reasonable on the OLPC LCD panel with a monochromatic layer on top of a
layer that can either reflect light (b/w sunlight readable mode) or light
pattern of red, green and blue pixels.
At this point, the driver is rather basic. The self-refresh mode is not
supported. There's no way of independently controlling the color swizzling,
antialiasing or b/w conversion, but it probably isn't too useful either.
There's another driver for the same hardware on OLPC XO-1.5 and XO-1.75
in drivers/staging/olpc_dcon. The display on that hardware doesn't utilize
DRM, so this driver doesn't replace the other one yet.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Added this patch, in place of a driver derived from
drivers/staging/olpc_dcon. Compared to the previous one this
implements the bare minimum, without the fancy stuff such as
self-refresh that need more work/thinking.
drivers/gpu/drm/bridge/Kconfig| 13 ++
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/himax-hx8837.c | 325 ++
3 files changed, 339 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/himax-hx8837.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 43271c21d3fce..df30d61c3fee1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,19 @@ config DRM_DISPLAY_CONNECTOR
on ARM-based platforms. Saying Y here when this driver is not needed
will not cause any issue.
+config DRM_HIMAX_HX8837
+tristate "HiMax HX8837 OLPC Display Controller"
+ depends on OF
+ depends on OLPC || ARCH_MMP || COMPILE_TEST
+ select DRM_KMS_HELPER
+select BACKLIGHT_LCD_SUPPORT
+select BACKLIGHT_CLASS_DEVICE
+help
+ Enable support for HiMax HX8837 Display Controller as found in the
+ OLPC XO laptops.
+
+ If your laptop doesn't have green ears, say "N"
+
config DRM_LVDS_CODEC
tristate "Transparent LVDS encoders and decoders support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index d63d4b7e43473..70d97c84382d5 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
+obj-$(CONFIG_DRM_HIMAX_HX8837) += himax-hx8837.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
diff --git a/drivers/gpu/drm/bridge/himax-hx8837.c
b/drivers/gpu/drm/bridge/himax-hx8837.c
new file mode 100644
index 0..1e97fcb8ce505
--- /dev/null
+++ b/drivers/gpu/drm/bridge/himax-hx8837.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * HiMax HX8837 Display Controller Driver
+ *
+ * Datasheet: http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define bridge_to_hx8837_priv(x) \
+ container_of(x, struct hx8837_priv, bridge)
+
+/* DCON registers */
+enum {
+ DCON_REG_ID = 0x00,
+ DCON_REG_MODE = 0x01,
+ DCON_REG_HRES = 0x02,
+ DCON_REG_HTOTAL = 0x03,
+ DCON_REG_HSYNC_WIDTH= 0x04,
+ DCON_REG_VRES = 0x05,
+ DCON_REG_VTOTAL = 0x06,
+ DCON_REG_VSYNC_WIDTH= 0x07,
+ DCON_REG_TIMEOUT= 0x08,
+ DCON_REG_SCAN_INT = 0x09,
+ DCON_REG_BRIGHT = 0x0a,
+ DCON_REG_MEM_OPT_A = 0x41,
+ DCON_REG_MEM_OPT_B = 0x42,
+};
+
+/* DCON_REG_MODE */
+enum {
+ MODE_PASSTHRU = BIT(0),
+ MODE_SLEEP = BIT(1),
+ MODE_SLEEP_AUTO = BIT(2),
+ MODE_BL_ENABLE = BIT(3),
+ MODE_BLANK = BIT(4),
+ MODE_CSWIZZLE = BIT(5),
+ MODE_COL_AA = BIT(6),
+ MODE_MONO_LUMA = BIT(7),
+ MODE_SCAN_INT = BIT(8),
+ MODE_CLOCKDIV = BIT(9),
+ MODE_DEBUG = BIT(14),
+ MODE_SELFTEST = BIT(15),
+};
+
+struct hx8837_priv {
+ struct regmap *regmap;
+ struct gpio_desc *load_gpio;
+
+ struct drm_bridge *panel_bridge;
+ struct drm_panel *panel;
+ struct drm_bridge bridge;
+};
+
+static int hx8837_bridge_attach(struct drm_bridge *bridge,
+
[PATCH 0/2] drm/panel: Add support for Innolux LS075AT011
Hi,
Please take a look at the patches chanied to this message and consider
applying them. They add description of the display panel found on OLPC
laptops to the simple panel driver.
There is no datasheet for the hardware and thus the timings were
determined on a best effort basis. The clock range is gotten from the
data sheet of the display controller [1] and the other timings are what
OLPC laptops actually use. The panel seems to cope with different sync
timings, but I'm not sure wherher there's any value in attempting to
figure out what range is actually permissible.
I could not figure out the right definitions for the connector and the
bus format. I'm not sure how necessary they are, but at least the
drm-panel driver insists on connector type being defined so I picked
LVDS because that seems to be used for internal laptop screens.
The signalling is not actually differential. It uses TTL levels with
data sampled on rising and falling clock edges; sort of like this (taken
from [1], P.20):
__
FSTH / \___
__
FCLK /\/\/\/\/
FD00 XXXXXXX
FD01 XXXXXXX
FD10 XXXXXXX
FD11 XXXXXXX
FD20 XXXXXXX
FD21 XXXXXXX
||||
data 1data 2 ...
(2x6bit) (2x6bit)
I believe the data just carries brightness because each pixel on the
panel has a fixed color; with the red, green and blue pixels organized
in a pattern [2]. (The HX8837 that drives the color does the conversion
from RGB).
Tested on an OLPC XO-1.75 laptop. XO-1 and XO-1.5 use the same hardware,
but their display controllers are not supported by DRM at the moment.
[1] http://wiki.laptop.org/images/0/09/DCON_datasheet_HX8837-A.pdf
[2] http://wiki.laptop.org/go/Display
Thank you!
Lubo
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Re: [PATCH 2/2] drm/panel: simple: Add Innolux N133HSE panel support
On Mon, May 11, 2020 at 09:47:08AM +0200, Sam Ravnborg wrote:
> Hi Richard.
>
> On Sat, May 09, 2020 at 01:18:34PM +0200, s...@48.io wrote:
> > From: Sean Cross
> >
> > The Innolux N133HSE panel is a 13.3" 1920x1080 panel that contains an
> > integrated backlight, and connects via eDP.
> >
> > It is used in the Kosagi Novena.
>
> Thanks for the patch.
>
>
> >
> > Signed-off-by: Sean Cross
> > Signed-off-by: Richard Marko
> > Cc: Shawn Guo
> > Cc: Fabio Estevam
> > Cc: Thierry Reding
> > To: dri-devel@lists.freedesktop.org
> > ---
> > drivers/gpu/drm/panel/panel-simple.c | 27 +++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
> > b/drivers/gpu/drm/panel/panel-simple.c
> > index 3ad828eaefe1..c8a93771d398 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -1906,6 +1906,30 @@ static const struct panel_desc innolux_n116bge = {
> > },
> > };
> >
> > +static const struct drm_display_mode innolux_n133hse_ea1_mode = {
> > + .clock = 138500,
> > + .hdisplay = 1920,
> > + .hsync_start = 1920 + 46,
> > + .hsync_end = 1920 + 46 + 30,
> > + .htotal = 1920 + 46 + 30 + 84,
> > + .vdisplay = 1080,
> > + .vsync_start = 1080 + 2,
> > + .vsync_end = 1080 + 2 + 4,
> > + .vtotal = 1080 + 2 + 4 + 26,
> > + .vrefresh = 60,
> > +};
> > +
> > +static const struct panel_desc innolux_n133hse_ea1 = {
> > + .modes = _n133hse_ea1_mode,
> > + .num_modes = 1,
> > + .bpc = 8,
> > + .size = {
> > + .width = 293,
> > + .height = 165,
> > + },
> > + .connector_type = DRM_MODE_CONNECTOR_eDP,
> Please include .bus_format and .bus_flags info too.
>
> We are relying more and more on this type of info so we need it to be
> present.
I am wondering which of the flags make sense for eDP and how the bus
format should be described?
Some eDP panels seems [1] to specify DRM_BUS_FLAG_DATA_MSB_TO_LSB and
DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, but I am not sure what sense they make
for packet data with embedded clock that eDP uses? (Unless, of course,
my understanding of eDP is entirely missing the point.)
This panel uses RGB888 data over two differential pairs. Would
format = MEDIA_BUS_FMT_RGB888_1X24 be appropriate?
[1] N133HSE-EA1 Datasheet
http://www.vslcd.com/specification/N133HSE-EA1.pdf
> Sam
Thank you,
Lubo
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[PATCH 1/2] dt-bindings: display: simple: add Innolux LS075AT011
Add the Innolux LS075AT011 7.5" (1200x900) color/reflective LCD panel to the panel-simple compatible list. This panel is used in the OLPC laptops. Signed-off-by: Lubomir Rintel --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 6dd59e59f..cad63a639e258 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -153,6 +153,8 @@ properties: - innolux,g121i1-l01 # Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel - innolux,g121x1-l03 +# Innolux LS075AT011 7.5" (1200x900) color/reflective LCD panel + - innolux,ls075at011 # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel - innolux,n116bge # InnoLux 15.6" WXGA TFT LCD panel -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 1/2] dt-bindings: display: himax, hx8837: Add Himax HX8837 bindings
Himax HX8837 is a secondary display controller used to drive the panel
on OLPC platforms.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Moved to bindings/display/
- Added the ports
- Converted to YAML
- Removed Pavel's Ack, because the changes are substantial
Changes since v2:
- s/betweend/between/
Changes since v1:
- s/load-gpio/load-gpios/
- Use interrupt bindings instead of gpio for the IRQ
.../bindings/display/bridge/himax,hx8837.yaml | 96 +++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
new file mode 100644
index 0..f5b0a00f5089d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2018,2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HX8837 Display Controller Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: himax,hx8837
+
+ reg:
+const: 0xd
+
+ load-gpios:
+maxItems: 1
+description: GPIO specifier of DCON_LOAD pin (active high)
+
+ stat-gpios:
+minItems: 2
+description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active high)
+
+ interrupts:
+maxItems: 1
+description: Interrupt specifier of DCON_IRQ pin (edge falling)
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ Video port connected to the panel.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - load-gpios
+ - stat-gpios
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lcd-controller@d {
+compatible = "himax,hx8837";
+reg = <0x0d>;
+stat-gpios = < 100 GPIO_ACTIVE_HIGH>,
+ < 101 GPIO_ACTIVE_HIGH>;
+load-gpios = < 142 GPIO_ACTIVE_HIGH>;
+interrupts = < 124 IRQ_TYPE_EDGE_FALLING>;
+
+ports {
+#address-cells = <0x01>;
+#size-cells = <0x00>;
+
+port@0 {
+reg = <0x00>;
+dcon_rgb_in: endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <0x01>;
+dcon_gettl_out: endpoint {
+remote-endpoint = <_dettl_in>;
+};
+};
+};
+};
+};
--
2.26.2
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Re: [PATCH v3 0/6] Generic USB Display driver
On Tue, Jul 14, 2020 at 09:03:14PM +0200, Noralf Trønnes wrote: > > > Den 14.07.2020 19.40, skrev Peter Stuge: > > Hi Noralf, > > > > Noralf Trønnes wrote: > >> I would like to keep the SET_BUFFER request since it will serve as a > >> syncing point between the host and the device. I'm no USB expert but I > >> assume that a bulk transfer can fail halfway through and result in the > >> next update starting where the previous one failed and thus writing > >> beyond the end of the display buffer. > > > > Transfers either succeed completely (possibly after many retries), > > time out (after zero or more transfered bytes) or fail catastrophically > > (e.g. from device disconnect). > > > > In all cases, the driver on the host knows/has available how many bytes > > were successfully transfered. > > > > I was thinking about the device, that it could get out of sync. Let's > say the host sends a 1k framebuffer and half of it gets transferred and > the rest fails for some reason. Lubomir's MCU implementation has an > endpoint max size of 64 bytes and a callback is called for each packet. Note that 64 bytes was chosen totally arbitrarily, without any thought. Perhaps the full frame of 1024 bytes would work just fine. I'm not familiar with USB at all. > If the 1k transfer fails at some point, will the device be able to > detect this and know that the next time the rx callback is called that > this is the start of a new framebuffer update? > > Noralf. Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 0/6] Generic USB Display driver
Hello, On 29 May 2020 Noralf Trønnes wrote: ... > This series adds a USB host driver and a device/gadget driver to achieve > that. > > The reason for calling it 'Generic' is so anyone can make a USB > display/adapter against this driver, all that's needed is to add a USB > vid:pid. I have done a microcontroller implementation hack just to see > how that would work out[1] (which unconvered a couple of bugs in the > host driver). ... This is actually very cool; finally a good way to drive the cheapo SPI/I2C displays from computers whose only means of expansion is USB with a little help from a microcontroller. I've actually had some success doing just that [1]. [1] https://assets.octodon.social/media_attachments/files/009/983/960/original/64ad8ea46c1b06c5.jpg I suppose you can add: Tested-by: Lubomir Rintel I've had to jump through some hoops though. My OLED display is a 128x64 SSD1306 [1] driven from the SPI bus. The frame buffer SRAM is normally scanned out in stripes of 8 vertical pixels called "pages". When the display is turned on its side, with "vertical addressing mode" and "segment remapping" enabled and bytes being sent LSB first, it appears linear -- it's easy to repaint the whole display from what is now the top left corner to the bottom right. This is very convenient for painting pixels as they come, without bufferring them or doing any conversions (assuming that memory and cpu cycles are at premium on MCUs). [1] https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf There doesn't seem a comfortable way to do partial redraws though. Would you find it objectionable if the device could indicate that needs full frames instead of just the damaged areas? Perhaps then the driver wouldn't even need to bother issuing GUD_DRM_USB_REQ_SET_BUFFER to displays dumb enough to be incapable of partial redraws and decompression. My work-in-progress code that works on STM32F103 (e.g. "Blue Pill" boards), or GD32VF103 (RISC-V "Polos Alef") is at [2]. The partial redraws that don't start from column zero or are not "page aligned" don't work correctly for the time being; X11 doesn't seem to care. [2] https://github.com/hackerspace/libopencm3-gf32v-examples/tree/lr/gd32v/examples/gd32v/f103/polos-alef/usb-display Thank you! Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 0/2] mfd: Add ENE KB3930 Embedded Controller driver
On Wed, Jun 17, 2020 at 10:58:28AM +0200, Lucas Stach wrote: > Hi Lubomir, > > Am Mittwoch, den 17.06.2020, 00:44 +0200 schrieb Lubomir Rintel: > > Hi, > > > > please consider applying the patches chained to this message. It's the > > fifth version of the driver for the ENE KB3930 Embedded Controller. > > > > This version is essentially a resend of v4. The only actual change is the > > addition of the Rob's Reviewed-by tag which I failed to do previously. > > Detailed change logs are in the individual patch descriptions. > > I don't think you wanted this to go to the etnaviv list and > maintainers, right? Indeed, a case of git send-email --embarass-yourself. Sorry about that and thanks for letting me know. Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 2/2] mfd: ene-kb3930: Add driver for ENE KB3930 Embedded Controller
This driver provides access to the EC RAM of said embedded controller
attached to the I2C bus as well as optionally supporting its slightly weird
power-off/restart protocol.
A particular implementation of the EC firmware can be identified by a
model byte. If this driver identifies the Dell Ariel platform, it
registers the appropriate cells.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Clarify that the power-off function is provided by this driver while
LEDS_ARIEL is necessary to drive the leds in Kconfig help text
- s/kb3930_power_off/kb3930_pm_power_off/, s/global_kb3930/kb3930_power_off/
- Don't fail with -EEXIST with more than one instance
- s/ret < 0/ret/ for devm_mfd_add_devices() return value
- Drop a \n between struct i2c_driver and module_i2c_driver()
Changes since v2:
- Sort the includes
- s/EC_MODEL_ID/EC_MODEL/
- Add a couple of clarifying comments
- Use #defines for values used in poweroff routine
- Remove priority from a restart notifier block
- s/priv/ddata/
- s/ec_ram/ram_regmap/ for the regmap name
- Fix the error handling when getting off gpios was not successful
- Remove a useless dev_info at the end of probe()
- Use i2c probe_new() callback, drop i2c_device_id
- Modify the logic in checking the model ID
drivers/mfd/Kconfig | 11 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/ene-kb3930.c | 211 +++
3 files changed, 223 insertions(+)
create mode 100644 drivers/mfd/ene-kb3930.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index a37d7d1713820..7569f1d1703e3 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -398,6 +398,17 @@ config MFD_DLN2
etc. must be enabled in order to use the functionality of
the device.
+config MFD_ENE_KB3930
+ tristate "ENE KB3930 Embedded Controller support"
+ depends on I2C
+ depends on MACH_MMP3_DT || COMPILE_TEST
+ select MFD_CORE
+ help
+ This adds support for the power-off functionality and access to
+ the registers that control LEDS and USB port power on ENE KB3930
+ Embedded Controller. To use the LED functionality LEDS_ARIEL must
+ be enabled.
+
config MFD_EXYNOS_LPASS
tristate "Samsung Exynos SoC Low Power Audio Subsystem"
depends on ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9367a92f795a6..11085a6968398 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_BCM2835)+= bcm2835-pm.o
obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
obj-$(CONFIG_MFD_BD9571MWV)+= bd9571mwv.o
obj-$(CONFIG_MFD_CROS_EC_DEV) += cros_ec_dev.o
+obj-$(CONFIG_MFD_ENE_KB3930) += ene-kb3930.o
obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o
obj-$(CONFIG_MFD_GATEWORKS_GSC)+= gateworks-gsc.o
diff --git a/drivers/mfd/ene-kb3930.c b/drivers/mfd/ene-kb3930.c
new file mode 100644
index 0..75eced148ce53
--- /dev/null
+++ b/drivers/mfd/ene-kb3930.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0-or-later
+/*
+ * ENE KB3930 Embedded Controller Driver
+ *
+ * Copyright (C) 2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* I2C registers that are multiplexing access to the EC RAM. */
+enum {
+ EC_DATA_IN = 0x00,
+ EC_RAM_OUT = 0x80,
+ EC_RAM_IN = 0x81,
+};
+
+/* EC RAM registers. */
+enum {
+ EC_MODEL= 0x30,
+ EC_VERSION_MAJ = 0x31,
+ EC_VERSION_MIN = 0x32,
+};
+
+struct kb3930 {
+ struct i2c_client *client;
+ struct regmap *ram_regmap;
+ struct gpio_descs *off_gpios;
+};
+
+struct kb3930 *kb3930_power_off;
+
+#define EC_GPIO_WAVE 0
+#define EC_GPIO_OFF_MODE 1
+
+#define EC_OFF_MODE_REBOOT 0
+#define EC_OFF_MODE_POWER 1
+
+static void kb3930_off(struct kb3930 *ddata, int off_mode)
+{
+ gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_OFF_MODE],
+ off_mode);
+
+ /*
+* The EC initiates a shutdown when it detects a 10 MHz wave,
inspecting the
+* other GPIO pin to decide whether it's supposed to turn the power off
or
+* reset the board.
+*/
+ while (1) {
+ mdelay(50);
+ gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_WAVE], 0);
+ mdelay(50);
+ gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_WAVE], 1);
+ }
+}
+
+static int kb3930_restart(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ kb3930_off(kb3930_power_off, EC_OFF_MODE_REBOOT);
+ return NOTIFY_DONE;
+}
+
+static void kb3930_pm_power_off(void)
+{
+ kb3930_off(kb3930_power_off, EC_OFF_MODE_POWER);
+}
+
+static struct notifier_block kb3930_restart_nb = {
+ .notifier_call = kb3930_restart,
+};
+
+st
[RESEND PATCH v2 1/4] drm/etnaviv: Fix error path on failure to enable bus clk
Since commit 65f037e8e908 ("drm/etnaviv: add support for slave interface
clock") the reg clock is enabled before the bus clock and we need to undo
its enablement on error.
Fixes: 65f037e8e908 ("drm/etnaviv: add support for slave interface clock")
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index a31eeff2b297a..c6dacfe3d321e 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1496,7 +1496,7 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
if (gpu->clk_bus) {
ret = clk_prepare_enable(gpu->clk_bus);
if (ret)
- return ret;
+ goto disable_clk_reg;
}
if (gpu->clk_core) {
@@ -1519,6 +1519,9 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
disable_clk_bus:
if (gpu->clk_bus)
clk_disable_unprepare(gpu->clk_bus);
+disable_clk_reg:
+ if (gpu->clk_reg)
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
--
2.26.2
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[PATCH v5 1/2] dt-bindings: mfd: Add ENE KB3930 Embedded Controller binding
Add binding document for the ENE KB3930 Embedded Controller.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v4:
- Collected Rob's Reviewed-by
Changes since v1:
- Addressed binding validation failure
.../devicetree/bindings/mfd/ene-kb3930.yaml | 55 +++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/ene-kb3930.yaml
diff --git a/Documentation/devicetree/bindings/mfd/ene-kb3930.yaml
b/Documentation/devicetree/bindings/mfd/ene-kb3930.yaml
new file mode 100644
index 0..005f5cb59ab12
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ene-kb3930.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/ene-kb3930.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ENE KB3930 Embedded Controller bindings
+
+description: |
+ This binding describes the ENE KB3930 Embedded Controller attached to a
+ I2C bus.
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+items:
+ - enum:
+- dell,wyse-ariel-ec # Dell Wyse Ariel board (3020)
+ - const: ene,kb3930
+ reg:
+maxItems: 1
+
+ off-gpios:
+description: GPIO used with the shutdown protocol on Ariel
+maxItems: 2
+
+ system-power-controller: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@58 {
+compatible = "dell,wyse-ariel-ec", "ene,kb3930";
+reg = <0x58>;
+system-power-controller;
+
+off-gpios = < 126 GPIO_ACTIVE_HIGH>,
+< 127 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+...
--
2.26.2
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[PATCH v5 0/2] mfd: Add ENE KB3930 Embedded Controller driver
Hi, please consider applying the patches chained to this message. It's the fifth version of the driver for the ENE KB3930 Embedded Controller. This version is essentially a resend of v4. The only actual change is the addition of the Rob's Reviewed-by tag which I failed to do previously. Detailed change logs are in the individual patch descriptions. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v2 3/4] drm/etnaviv: Make the "core" clock mandatory
It is always present. It was documented as mandatory prior to
commit 90aeca875f8a ("dt-bindings: display: Convert etnaviv to
json-schema").
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Add this patch
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index f303172c091db..798fdbc8ecdb5 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1796,7 +1796,7 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
if (IS_ERR(gpu->clk_bus))
return PTR_ERR(gpu->clk_bus);
- gpu->clk_core = devm_clk_get_optional(>dev, "core");
+ gpu->clk_core = devm_clk_get(>dev, "core");
DBG("clk_core: %p", gpu->clk_core);
if (IS_ERR(gpu->clk_core))
return PTR_ERR(gpu->clk_core);
--
2.26.2
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[RESEND PATCH v2 2/4] drm/etnaviv: Don't ignore errors on getting clocks
There might be good reasons why the getting a clock failed. To treat the
clocks as optional we're specifically only interested in ignoring -ENOENT,
and devm_clk_get_optional() does just that.
Note that this preserves the original behavior of all clocks being
optional. The binding document mandates the "bus" clock while the dove
machine only specifies "core".
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Fix the actual return value
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index c6dacfe3d321e..f303172c091db 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1786,26 +1786,26 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
}
/* Get Clocks: */
- gpu->clk_reg = devm_clk_get(>dev, "reg");
+ gpu->clk_reg = devm_clk_get_optional(>dev, "reg");
DBG("clk_reg: %p", gpu->clk_reg);
if (IS_ERR(gpu->clk_reg))
- gpu->clk_reg = NULL;
+ return PTR_ERR(gpu->clk_reg);
- gpu->clk_bus = devm_clk_get(>dev, "bus");
+ gpu->clk_bus = devm_clk_get_optional(>dev, "bus");
DBG("clk_bus: %p", gpu->clk_bus);
if (IS_ERR(gpu->clk_bus))
- gpu->clk_bus = NULL;
+ return PTR_ERR(gpu->clk_bus);
- gpu->clk_core = devm_clk_get(>dev, "core");
+ gpu->clk_core = devm_clk_get_optional(>dev, "core");
DBG("clk_core: %p", gpu->clk_core);
if (IS_ERR(gpu->clk_core))
- gpu->clk_core = NULL;
+ return PTR_ERR(gpu->clk_core);
gpu->base_rate_core = clk_get_rate(gpu->clk_core);
- gpu->clk_shader = devm_clk_get(>dev, "shader");
+ gpu->clk_shader = devm_clk_get_optional(>dev, "shader");
DBG("clk_shader: %p", gpu->clk_shader);
if (IS_ERR(gpu->clk_shader))
- gpu->clk_shader = NULL;
+ return PTR_ERR(gpu->clk_shader);
gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
/* TODO: figure out max mapped size */
--
2.26.2
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[RESEND PATCH v2 4/4] drm/etnaviv: Simplify clock enable/disable
All the NULL checks are pointless, clk_*() routines already deal with NULL
just fine.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ++-
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 798fdbc8ecdb5..fb37787449bb7 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1487,55 +1487,40 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu
*gpu)
{
int ret;
- if (gpu->clk_reg) {
- ret = clk_prepare_enable(gpu->clk_reg);
- if (ret)
- return ret;
- }
+ ret = clk_prepare_enable(gpu->clk_reg);
+ if (ret)
+ return ret;
- if (gpu->clk_bus) {
- ret = clk_prepare_enable(gpu->clk_bus);
- if (ret)
- goto disable_clk_reg;
- }
+ ret = clk_prepare_enable(gpu->clk_bus);
+ if (ret)
+ goto disable_clk_reg;
- if (gpu->clk_core) {
- ret = clk_prepare_enable(gpu->clk_core);
- if (ret)
- goto disable_clk_bus;
- }
+ ret = clk_prepare_enable(gpu->clk_core);
+ if (ret)
+ goto disable_clk_bus;
- if (gpu->clk_shader) {
- ret = clk_prepare_enable(gpu->clk_shader);
- if (ret)
- goto disable_clk_core;
- }
+ ret = clk_prepare_enable(gpu->clk_shader);
+ if (ret)
+ goto disable_clk_core;
return 0;
disable_clk_core:
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_core);
disable_clk_bus:
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_bus);
disable_clk_reg:
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
{
- if (gpu->clk_shader)
- clk_disable_unprepare(gpu->clk_shader);
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_shader);
+ clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_reg);
return 0;
}
--
2.26.2
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[RESEND PATCH v2 0/4] drm/etnaviv: Tidy up clocks handling
Hi, please consider applying patches that are chained to this message. They make getting/enabling the clocks in the etnaviv driver slightly nicer, first two also fix potential problems. Compared to v1, patch 2/4 was fixed and patch 3/4 was added. As it was pointed out in response to v1, the clocks documented as mandatory by the binding document are different from what the driver enforces. Moreover, there is no agreement on which clocks must be present in the device tree, so I'm leaving the binding document until it's cleared up. In any case, the "core" clock is always present so it's safe to make it mandatory and regardless of what ends up happening to the binding documentation, the other clocks can't be enforced without regressions. At most a comment or a warning could be added. I'm leaving it as it is. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 4/4] drm/etnaviv: Simplify clock enable/disable
All the NULL checks are pointless, clk_*() routines already deal with NULL
just fine.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ++-
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 798fdbc8ecdb..fb37787449bb 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1487,55 +1487,40 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu
*gpu)
{
int ret;
- if (gpu->clk_reg) {
- ret = clk_prepare_enable(gpu->clk_reg);
- if (ret)
- return ret;
- }
+ ret = clk_prepare_enable(gpu->clk_reg);
+ if (ret)
+ return ret;
- if (gpu->clk_bus) {
- ret = clk_prepare_enable(gpu->clk_bus);
- if (ret)
- goto disable_clk_reg;
- }
+ ret = clk_prepare_enable(gpu->clk_bus);
+ if (ret)
+ goto disable_clk_reg;
- if (gpu->clk_core) {
- ret = clk_prepare_enable(gpu->clk_core);
- if (ret)
- goto disable_clk_bus;
- }
+ ret = clk_prepare_enable(gpu->clk_core);
+ if (ret)
+ goto disable_clk_bus;
- if (gpu->clk_shader) {
- ret = clk_prepare_enable(gpu->clk_shader);
- if (ret)
- goto disable_clk_core;
- }
+ ret = clk_prepare_enable(gpu->clk_shader);
+ if (ret)
+ goto disable_clk_core;
return 0;
disable_clk_core:
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_core);
disable_clk_bus:
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_bus);
disable_clk_reg:
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
{
- if (gpu->clk_shader)
- clk_disable_unprepare(gpu->clk_shader);
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_shader);
+ clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_reg);
return 0;
}
--
2.26.2
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[PATCH v2 1/4] drm/etnaviv: Fix error path on failure to enable bus clk
Since commit 65f037e8e908 ("drm/etnaviv: add support for slave interface
clock") the reg clock is enabled before the bus clock and we need to undo
its enablement on error.
Fixes: 65f037e8e908 ("drm/etnaviv: add support for slave interface clock")
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index a31eeff2b297..c6dacfe3d321 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1496,7 +1496,7 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
if (gpu->clk_bus) {
ret = clk_prepare_enable(gpu->clk_bus);
if (ret)
- return ret;
+ goto disable_clk_reg;
}
if (gpu->clk_core) {
@@ -1519,6 +1519,9 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
disable_clk_bus:
if (gpu->clk_bus)
clk_disable_unprepare(gpu->clk_bus);
+disable_clk_reg:
+ if (gpu->clk_reg)
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
--
2.26.2
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[PATCH v2 0/4] drm/etnaviv: Tidy up clocks handling
Hi, please consider applying patches that are chained to this message. They make getting/enabling the clocks in the etnaviv driver slightly nicer, first two also fix potential problems. Compared to v1, patch 2/4 was fixed and patch 3/4 was added. As it was pointed out in response to v1, the clocks documented as mandatory by the binding document are different from what the driver enforces. Moreover, there is no agreement on which clocks must be present in the device tree, so I'm leaving the binding document until it's cleared up. In any case, the "core" clock is always present so it's safe to make it mandatory and regardless of what ends up happening to the binding documentation, the other clocks can't be enforced without regressions. At most a comment or a warning could be added. I'm leaving it as it is. Thank you Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 3/4] drm/etnaviv: Make the "core" clock mandatory
It is always present. It was documented as mandatory prior to
commit 90aeca875f8a ("dt-bindings: display: Convert etnaviv to
json-schema").
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Add this patch
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index f303172c091d..798fdbc8ecdb 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1796,7 +1796,7 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
if (IS_ERR(gpu->clk_bus))
return PTR_ERR(gpu->clk_bus);
- gpu->clk_core = devm_clk_get_optional(>dev, "core");
+ gpu->clk_core = devm_clk_get(>dev, "core");
DBG("clk_core: %p", gpu->clk_core);
if (IS_ERR(gpu->clk_core))
return PTR_ERR(gpu->clk_core);
--
2.26.2
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[PATCH v2 2/4] drm/etnaviv: Don't ignore errors on getting clocks
There might be good reasons why the getting a clock failed. To treat the
clocks as optional we're specifically only interested in ignoring -ENOENT,
and devm_clk_get_optional() does just that.
Note that this preserves the original behavior of all clocks being
optional. The binding document mandates the "bus" clock while the dove
machine only specifies "core".
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Fix the actual return value
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index c6dacfe3d321..f303172c091d 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1786,26 +1786,26 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
}
/* Get Clocks: */
- gpu->clk_reg = devm_clk_get(>dev, "reg");
+ gpu->clk_reg = devm_clk_get_optional(>dev, "reg");
DBG("clk_reg: %p", gpu->clk_reg);
if (IS_ERR(gpu->clk_reg))
- gpu->clk_reg = NULL;
+ return PTR_ERR(gpu->clk_reg);
- gpu->clk_bus = devm_clk_get(>dev, "bus");
+ gpu->clk_bus = devm_clk_get_optional(>dev, "bus");
DBG("clk_bus: %p", gpu->clk_bus);
if (IS_ERR(gpu->clk_bus))
- gpu->clk_bus = NULL;
+ return PTR_ERR(gpu->clk_bus);
- gpu->clk_core = devm_clk_get(>dev, "core");
+ gpu->clk_core = devm_clk_get_optional(>dev, "core");
DBG("clk_core: %p", gpu->clk_core);
if (IS_ERR(gpu->clk_core))
- gpu->clk_core = NULL;
+ return PTR_ERR(gpu->clk_core);
gpu->base_rate_core = clk_get_rate(gpu->clk_core);
- gpu->clk_shader = devm_clk_get(>dev, "shader");
+ gpu->clk_shader = devm_clk_get_optional(>dev, "shader");
DBG("clk_shader: %p", gpu->clk_shader);
if (IS_ERR(gpu->clk_shader))
- gpu->clk_shader = NULL;
+ return PTR_ERR(gpu->clk_shader);
gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
/* TODO: figure out max mapped size */
--
2.26.2
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Re: [PATCH 2/3] drm/etnaviv: Don't ignore errors on getting clocks
Cc += robh On Wed, May 20, 2020 at 04:04:39PM +0200, Lucas Stach wrote: > Am Mittwoch, den 20.05.2020, 15:38 +0200 schrieb Lubomir Rintel: > > On Thu, May 14, 2020 at 09:53:08AM +0100, Russell King - ARM Linux admin > > wrote: > > > On Thu, May 14, 2020 at 10:40:58AM +0200, Lucas Stach wrote: > > > > Am Donnerstag, den 14.05.2020, 09:27 +0100 schrieb Russell King - ARM > > > > Linux admin: > > > > > On Thu, May 14, 2020 at 10:18:02AM +0200, Lucas Stach wrote: > > > > > > Am Mittwoch, den 13.05.2020, 23:41 -0300 schrieb Fabio Estevam: > > > > > > > On Wed, May 13, 2020 at 2:09 PM Fabio Estevam > > > > > > > wrote: > > > > > > > > > > > > > > > The binding doc > > > > > > > > Documentation/devicetree/bindings/gpu/vivante,gc.yaml > > > > > > > > says that only the 'reg' clock could be optional, the others are > > > > > > > > required. > > > > > > > > > > > > > > arch/arm/boot/dts/dove.dtsi only uses the 'core' clock. > > > > > > > arch/arm/boot/dts/stm32mp157.dtsi uses 'bus' and 'core' > > > > > > > > > > > > > > Maybe the binding needs to be updated and it seems that using > > > > > > > devm_clk_get_optional() like you propose is safe. > > > > > > > > > > > > The binding is correct as-is. We want to require those clocks to be > > > > > > present, but the dove DT was added before the binding was > > > > > > finalized, so > > > > > > the driver still treats the clocks as optional to not break > > > > > > compatibility with old DTs. Maybe this warrants a comment in the > > > > > > code... > > > > > > > > > > The binding doc in mainline says: > > > > > > > > > > clocks: > > > > > items: > > > > > - description: AXI/master interface clock > > > > > - description: GPU core clock > > > > > - description: Shader clock (only required if GPU has feature > > > > > PIPE_3D) > > > > > - description: AHB/slave interface clock (only required if GPU > > > > > can gate slave interface independently) > > > > > minItems: 1 > > > > > maxItems: 4 > > > > > > > > > > clock-names: > > > > > items: > > > > > enum: [ bus, core, shader, reg ] > > > > > minItems: 1 > > > > > maxItems: 4 > > > > > > > > > > which looks correct to me - and means that Dove is compliant with > > > > > that. > > > > > > > > The YAML binding actually did loose something in translation here, > > > > which I didn't notice. Previously all those clocks were listed under > > > > "Required properties", with the exceptions listed in parenthesis. So > > > > the Dove GPU, which is a combined 2D/3D core should have axi, core and > > > > shader clocks specified. > > > > > > That may be your desire, but that is impossible without knowing that > > > (a) it has the clocks > > > (b) what those clocks are connected to > > > > > > I guess we could "make something up" but as DT is supposed to describe > > > hardware, I don't see how we can satisfy that and your requirement. > > > > > > The only thing that is known from the documentation is that there is > > > one clock for the GPU on Dove. > > > > Yes. This means that in fact "core" is the only required clock for all > > implementations of vivante,gc and the common binding needs to be updated > > to reflect that. I'll follow with a patch that does that, unless there > > are strong objections. > > > > If there are implementations that require different clock inputs, then they > > need to use additional compatible string for the particular flavor and the > > binding should have conditionals for them. Something like this: > > > > if: > > properties: > > compatible: > > contains: > > const: fsl,imx6sx-gpu > > then: > > properties: > > clocks: > > minItems: 4 > > The DT binding of a device should describe the hardware of the device, > not the specific integration into a SoC. I'm no
Re: [PATCH 2/3] drm/etnaviv: Don't ignore errors on getting clocks
On Thu, May 14, 2020 at 09:53:08AM +0100, Russell King - ARM Linux admin wrote: > On Thu, May 14, 2020 at 10:40:58AM +0200, Lucas Stach wrote: > > Am Donnerstag, den 14.05.2020, 09:27 +0100 schrieb Russell King - ARM Linux > > admin: > > > On Thu, May 14, 2020 at 10:18:02AM +0200, Lucas Stach wrote: > > > > Am Mittwoch, den 13.05.2020, 23:41 -0300 schrieb Fabio Estevam: > > > > > On Wed, May 13, 2020 at 2:09 PM Fabio Estevam > > > > > wrote: > > > > > > > > > > > The binding doc > > > > > > Documentation/devicetree/bindings/gpu/vivante,gc.yaml > > > > > > says that only the 'reg' clock could be optional, the others are > > > > > > required. > > > > > > > > > > arch/arm/boot/dts/dove.dtsi only uses the 'core' clock. > > > > > arch/arm/boot/dts/stm32mp157.dtsi uses 'bus' and 'core' > > > > > > > > > > Maybe the binding needs to be updated and it seems that using > > > > > devm_clk_get_optional() like you propose is safe. > > > > > > > > The binding is correct as-is. We want to require those clocks to be > > > > present, but the dove DT was added before the binding was finalized, so > > > > the driver still treats the clocks as optional to not break > > > > compatibility with old DTs. Maybe this warrants a comment in the > > > > code... > > > > > > The binding doc in mainline says: > > > > > > clocks: > > > items: > > > - description: AXI/master interface clock > > > - description: GPU core clock > > > - description: Shader clock (only required if GPU has feature > > > PIPE_3D) > > > - description: AHB/slave interface clock (only required if GPU can > > > gate slave interface independently) > > > minItems: 1 > > > maxItems: 4 > > > > > > clock-names: > > > items: > > > enum: [ bus, core, shader, reg ] > > > minItems: 1 > > > maxItems: 4 > > > > > > which looks correct to me - and means that Dove is compliant with that. > > > > The YAML binding actually did loose something in translation here, > > which I didn't notice. Previously all those clocks were listed under > > "Required properties", with the exceptions listed in parenthesis. So > > the Dove GPU, which is a combined 2D/3D core should have axi, core and > > shader clocks specified. > > That may be your desire, but that is impossible without knowing that > (a) it has the clocks > (b) what those clocks are connected to > > I guess we could "make something up" but as DT is supposed to describe > hardware, I don't see how we can satisfy that and your requirement. > > The only thing that is known from the documentation is that there is > one clock for the GPU on Dove. Yes. This means that in fact "core" is the only required clock for all implementations of vivante,gc and the common binding needs to be updated to reflect that. I'll follow with a patch that does that, unless there are strong objections. If there are implementations that require different clock inputs, then they need to use additional compatible string for the particular flavor and the binding should have conditionals for them. Something like this: if: properties: compatible: contains: const: fsl,imx6sx-gpu then: properties: clocks: minItems: 4 Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] drm/etnaviv: Simplify clock enable/disable
All the NULL checks are pointless, clk_*() routines already deal with NULL
just fine.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 53 ++-
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index e7dbb924f576..f5b95cb4f058 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1487,55 +1487,40 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu
*gpu)
{
int ret;
- if (gpu->clk_reg) {
- ret = clk_prepare_enable(gpu->clk_reg);
- if (ret)
- return ret;
- }
+ ret = clk_prepare_enable(gpu->clk_reg);
+ if (ret)
+ return ret;
- if (gpu->clk_bus) {
- ret = clk_prepare_enable(gpu->clk_bus);
- if (ret)
- goto disable_clk_reg;
- }
+ ret = clk_prepare_enable(gpu->clk_bus);
+ if (ret)
+ goto disable_clk_reg;
- if (gpu->clk_core) {
- ret = clk_prepare_enable(gpu->clk_core);
- if (ret)
- goto disable_clk_bus;
- }
+ ret = clk_prepare_enable(gpu->clk_core);
+ if (ret)
+ goto disable_clk_bus;
- if (gpu->clk_shader) {
- ret = clk_prepare_enable(gpu->clk_shader);
- if (ret)
- goto disable_clk_core;
- }
+ ret = clk_prepare_enable(gpu->clk_shader);
+ if (ret)
+ goto disable_clk_core;
return 0;
disable_clk_core:
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_core);
disable_clk_bus:
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_bus);
disable_clk_reg:
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
{
- if (gpu->clk_shader)
- clk_disable_unprepare(gpu->clk_shader);
- if (gpu->clk_core)
- clk_disable_unprepare(gpu->clk_core);
- if (gpu->clk_bus)
- clk_disable_unprepare(gpu->clk_bus);
- if (gpu->clk_reg)
- clk_disable_unprepare(gpu->clk_reg);
+ clk_disable_unprepare(gpu->clk_shader);
+ clk_disable_unprepare(gpu->clk_core);
+ clk_disable_unprepare(gpu->clk_bus);
+ clk_disable_unprepare(gpu->clk_reg);
return 0;
}
--
2.26.2
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[PATCH 1/3] drm/etnaviv: Fix error path on failure to enable bus clk
Since commit 65f037e8e908 ("drm/etnaviv: add support for slave interface
clock") the reg clock is enabled before the bus clock and we need to undo
its enablement on error.
Fixes: 65f037e8e908 ("drm/etnaviv: add support for slave interface clock")
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index a31eeff2b297..c6dacfe3d321 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1496,7 +1496,7 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
if (gpu->clk_bus) {
ret = clk_prepare_enable(gpu->clk_bus);
if (ret)
- return ret;
+ goto disable_clk_reg;
}
if (gpu->clk_core) {
@@ -1519,6 +1519,9 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
disable_clk_bus:
if (gpu->clk_bus)
clk_disable_unprepare(gpu->clk_bus);
+disable_clk_reg:
+ if (gpu->clk_reg)
+ clk_disable_unprepare(gpu->clk_reg);
return ret;
}
--
2.26.2
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[PATCH 2/3] drm/etnaviv: Don't ignore errors on getting clocks
There might be good reasons why the getting a clock failed. To treat the
clocks as optional we're specifically only interested in ignoring -ENOENT,
and devm_clk_get_optional() does just that.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index c6dacfe3d321..e7dbb924f576 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1786,26 +1786,26 @@ static int etnaviv_gpu_platform_probe(struct
platform_device *pdev)
}
/* Get Clocks: */
- gpu->clk_reg = devm_clk_get(>dev, "reg");
+ gpu->clk_reg = devm_clk_get_optional(>dev, "reg");
DBG("clk_reg: %p", gpu->clk_reg);
if (IS_ERR(gpu->clk_reg))
- gpu->clk_reg = NULL;
+ return err;
- gpu->clk_bus = devm_clk_get(>dev, "bus");
+ gpu->clk_bus = devm_clk_get_optional(>dev, "bus");
DBG("clk_bus: %p", gpu->clk_bus);
if (IS_ERR(gpu->clk_bus))
- gpu->clk_bus = NULL;
+ return err;
- gpu->clk_core = devm_clk_get(>dev, "core");
+ gpu->clk_core = devm_clk_get_optional(>dev, "core");
DBG("clk_core: %p", gpu->clk_core);
if (IS_ERR(gpu->clk_core))
- gpu->clk_core = NULL;
+ return err;
gpu->base_rate_core = clk_get_rate(gpu->clk_core);
- gpu->clk_shader = devm_clk_get(>dev, "shader");
+ gpu->clk_shader = devm_clk_get_optional(>dev, "shader");
DBG("clk_shader: %p", gpu->clk_shader);
if (IS_ERR(gpu->clk_shader))
- gpu->clk_shader = NULL;
+ return err;
gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
/* TODO: figure out max mapped size */
--
2.26.2
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[PATCH] drm/etnaviv: Fix the pm_domain lookup
On a GC860 (both 3D and 2D capable) GPU, kmscube crashes:
# strace -f ~lkundrak/src/kmscube/build/kmscube
...
ioctl(6, DRM_IOCTL_ETNAVIV_PM_QUERY_DOM, 0xbe92b720) = 0
ioctl(6, DRM_IOCTL_ETNAVIV_PM_QUERY_SIG ) = ?
+++ killed by SIGSEGV +++
Segmentation fault (core dumped)
And triggers an oops:
8<--- cut here ---
Unable to handle kernel NULL pointer dereference at virtual address
pgd = 40e2c0f7
[] *pgd=0df6d831, *pte=, *ppte=
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 346 Comm: kmscube Not tainted 5.7.0-rc4+ #792
Hardware name: Marvell MMP2 (Device Tree Support)
PC is at strncpy+0x14/0x30
LR is at etnaviv_pm_query_sig+0xd0/0x104
pc : []lr : []psr: 20010013
sp : c85f5e00 ip : c85f5eb5 fp : beb58748
r10: 004c r9 : ca6f9100 r8 : c85f5e6c
r7 : 0050 r6 : c85f5e6c r5 : 0001 r4 : c0b69ae8
r3 : c85f5e75 r2 : 003f r1 : r0 : c85f5e76
Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 0df70019 DAC: 0051
Process kmscube (pid: 346, stack limit = 0x816fba31)
Stack: (0xc85f5e00 to 0xc85f6000)
5e00: d90e6000 0020 c05d5b2c c85f5e6c c059ce90 c1003f88
5e20: c04c644b 004c c0b69610 c04c644b c85f5e6c 004b ca6f9100 c059d0bc
5e40: 0001 c0d53ee8 c85f5f18 0001 c85f5f50 c85f5e6c 004c c8454240
5e60: c05d5b2c 0051 0001
5e80:
5ea0: 0274 c011c3fc
5ec0: 0100 c0290434 5ebc5632 30e03501 5ebc5632 c8526600 0274 00100cca
5ee0: 0831 b64c5000 cdf72d90 c1003f88 c04c644b c8454240 beb58748
5f00: c8454240 0006 c85f4000 d90ecad8 001c01a0 c02d49ac b64c52cc 8007
5f20: da9d6dc0 d9aa4000 d9aa4040 0274 c011818c 0005 0e200080
5f40: 03e5 0100 cc78ac40
5f60: 0006 0007 c1009a98 b64c52cc c85f5fb0 c0118080 0080 c1003f88
5f80: 0001 beb58748 c04c644b 0036 c0100288 c85f4000 0036
5fa0: 001c01a0 c0100060 0001 beb58748 0006 c04c644b beb58748 004c
5fc0: 0001 beb58748 c04c644b 0036 beb58748 001bd688 beb58700 001c01a0
5fe0: b6f41f08 beb586d4 b6f2784c b6e16cec 80010010 0006
[] (strncpy) from [] (etnaviv_pm_query_sig+0xd0/0x104)
[] (etnaviv_pm_query_sig) from []
(drm_ioctl_kernel+0xb4/0xf8)
[] (drm_ioctl_kernel) from [] (drm_ioctl+0x1e8/0x3b8)
[] (drm_ioctl) from [] (ksys_ioctl+0xe0/0xaf0)
[] (ksys_ioctl) from [] (ret_fast_syscall+0x0/0x54)
Exception stack(0xc85f5fa8 to 0xc85f5ff0)
5fa0: 0001 beb58748 0006 c04c644b beb58748 004c
5fc0: 0001 beb58748 c04c644b 0036 beb58748 001bd688 beb58700 001c01a0
5fe0: b6f41f08 beb586d4 b6f2784c b6e16cec
Code: 012fff1e e2422001 e2403001 e080c002 (e5d12000)
---[ end trace 387aad33cd9c15ea ]---
Turns out that it's because pm_domain() returns a pointer outside any
any of the etnaviv_pm_domains. Unless I'm mistaken, the algorithm in
pm_domain() is entirely botched when GPU's features match more than one
domain. This tries to remedy it.
Tested with kmscube with mesa 20 on ome machine with GC860 and another
with GC2000 + GC300 pair.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
index e6795bafcbb9..9dc1bb4d4582 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -444,7 +444,6 @@ static unsigned int num_pm_domains(const struct etnaviv_gpu
*gpu)
static const struct etnaviv_pm_domain *pm_domain(const struct etnaviv_gpu *gpu,
unsigned int index)
{
- const struct etnaviv_pm_domain *domain = NULL;
unsigned int offset = 0, i;
for (i = 0; i < ARRAY_SIZE(doms_meta); i++) {
@@ -453,15 +452,15 @@ static const struct etnaviv_pm_domain *pm_domain(const
struct etnaviv_gpu *gpu,
if (!(gpu->identity.features & meta->feature))
continue;
- if (meta->nr_domains < (index - offset)) {
+ if (meta->nr_domains <= (index - offset)) {
offset += meta->nr_domains;
continue;
}
- domain = meta->domains + (index - offset);
+ return meta->domains + (index - offset);
}
- return domain;
+ return NULL;
}
int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
--
2.26.2
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[PATCH v5 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d3891386d671..7794ffccd325 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -187,6 +187,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.26.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v4:
- Removed the registration with the component framework and creation of
drm_encoder.
Changes since v3:
- Cosmetic changes; drop ch7033_encoder_destroy() and use
drm_encoder_cleanup() for drm_encoder_funcs.destroy callback
directly.
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 620 +++
3 files changed, 631 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9..0ebc72d62a5b 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f0..a844315feddb 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index ..f8675d82974b
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,620 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2b */
+enum {
+ SWAPS
[PATCH v5 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Fixed the example so that it validates
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index ..9f38f55fc990
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
+};
--
2.26.0
___
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[PATCH v5 0/3] drm: Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is another spin of a driver for CH7033. Compared to the previous submission, the integration with device component framework and creation of an encoder on component bind has been removed. This means that until the Armada driver won't work with this driver until it's adjusted to look up the bridges like the other drivers do. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 3/3] drm/bridge: chrontel-ch7033: Add a new driver
On Tue, Apr 21, 2020 at 02:54:12PM +0200, Daniel Vetter wrote: > On Tue, Mar 24, 2020 at 04:19:31PM +0100, Lubomir Rintel wrote: > > This is a driver for video encoder with VGA and DVI/HDMI outputs. > > > > There is no documentation for the chip -- the operation was guessed from > > what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names > > come from the ch7035 driver in Mediatek's GPL code dump. > > > > Only bare minimum is implemented -- no fancy stuff, such as scaling. That > > would only worsen our misery. We don't load the firmware and we don't need > > to even bother enabling the MCU. There are probably no distributable > > firmware images anyway. > > > > Just like the tda998x driver, this one uses the component framework and > > adds an encoder on component bind, so that it works with the Armada DRM > > driver. Thank you for your response. > Uh, can we instead pls land the patches for armada to switch over to of > bridge helpers. I honestly don't know -- it's not something I can do anything about. I didn't have any luck getting responses to my other patches for the Armada driver. > Iirc the big hold-up was that with direct bridge usage > instead of component framework, the drm driver wouldn't unload. But core > pm maintainers fixed device links to include driver unloading, and there > was a drm_bridge patch including armada patches to do all that. > > But somehow it didn't land. Iirc because Russell couldn't test them on > upstream somehow. This is what I've found [1]. It seems to include the device links work and switches over the komeda driver, not armada, from components to drm_bridge: [1] https://patchwork.kernel.org/cover/11262351/ I'm wondering if this is the patch set you're referring to? > Adding more special cases and bridge drivers that we have to convert isn't > going to make this any easier. No conversion would be necessary -- merely stripping the component/encoder parts once they're no longer necessary. The driver would still work just fine with drivers that don't utilize the component framework, juts as tda998x does. > This entire discussion happened in > > https://www.spinics.net/lists/dri-devel/msg201927.html > > Can't find the armada patches real quick, nor the drm_bridge patch. But > the core infrastructure hides behind. The core pm change has been added in > > commit e7dd40105aac9ba051e44ad711123bc53a5e4c71 > Author: Rafael J. Wysocki > Date: Fri Feb 1 01:59:42 2019 +0100 > > driver core: Add device link flag DL_FLAG_AUTOPROBE_CONSUMER Thank you Lubo > > Thanks, Daniel > > > > Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60, > > with VGA as well as DVI. > > > > Signed-off-by: Lubomir Rintel > > > > --- > > Changes since v3: > > - Cosmetic changes; drop ch7033_encoder_destroy() and use > > drm_encoder_cleanup() for drm_encoder_funcs.destroy callback > > directly. > > > > Changes since v1: > > - Sort the includes > > - Drop a useless model id read > > - Chain to the bridge-connector instead of dealing with the HPD/EDID > > readout machinery ourselves > > - Utilize regmap to access the registers > > > > drivers/gpu/drm/bridge/Kconfig | 10 + > > drivers/gpu/drm/bridge/Makefile | 1 + > > drivers/gpu/drm/bridge/chrontel-ch7033.c | 669 +++ > > 3 files changed, 680 insertions(+) > > create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c > > > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > > index aaed2347ace9d..0ebc72d62a5b2 100644 > > --- a/drivers/gpu/drm/bridge/Kconfig > > +++ b/drivers/gpu/drm/bridge/Kconfig > > @@ -27,6 +27,16 @@ config DRM_CDNS_DSI > > Support Cadence DPI to DSI bridge. This is an internal > > bridge and is meant to be directly embedded in a SoC. > > > > +config DRM_CHRONTEL_CH7033 > > + tristate "Chrontel CH7033 Video Encoder" > > + depends on OF > > + select DRM_KMS_HELPER > > + help > > + Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as > > + found in the Dell Wyse 3020 thin client. > > + > > + If in doubt, say "N". > > + > > config DRM_DISPLAY_CONNECTOR > > tristate "Display connector support" > > depends on OF > > diff --git a/drivers/gpu/drm/bridge/Makefile > > b/drivers/gpu/drm/bridge/Makefile > > index 6fb062b5b0f04..a844315feddb4 100644 > > --- a/drivers/gpu/drm/bridge/Makefile > > +++ b/drivers/gpu/drm/bridge/Makefile > > @@ -1,5 +
[RESEND PATCH v4 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Fixed the example so that it validates
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..9f38f55fc9904
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
+};
--
2.26.0
___
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[RESEND PATCH v4 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d3891386d6710..7794ffccd3258 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -187,6 +187,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.26.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v4 0/3] drm: Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is resend of v4 [1] of a driver for CH7033. Please consider enqueing it for 5.8. [1] https://lore.kernel.org/lkml/20200324151931.449985-1-lkund...@v3.sk/ Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v4 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Cosmetic changes; drop ch7033_encoder_destroy() and use
drm_encoder_cleanup() for drm_encoder_funcs.destroy callback
directly.
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 669 +++
3 files changed, 680 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9d..0ebc72d62a5b2 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f04..a844315feddb4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..f5cb2130684f7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/*
[PATCH v4 0/3] drm: Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is another spin of a driver for CH7033. Only cosmetic changes since the previous version [1]. Please take a look. [1] https://lore.kernel.org/lkml/20200314101627.336939-1-lkund...@v3.sk/ Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v3:
- Cosmetic changes; drop ch7033_encoder_destroy() and use
drm_encoder_cleanup() for drm_encoder_funcs.destroy callback
directly.
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 669 +++
3 files changed, 680 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9d..0ebc72d62a5b2 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f04..a844315feddb4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..f5cb2130684f7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/*
[PATCH v4 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Fixed the example so that it validates
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..9f38f55fc9904
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
+};
--
2.26.0.rc2
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a2da166df1bc7..0ab86d876f4d2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -185,6 +185,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.26.0.rc2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 675 +++
3 files changed, 686 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9d..0ebc72d62a5b2 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f04..a844315feddb4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..342b2e2bd2b1c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2b */
+enum {
+ SWAPS = GENMASK(7, 4),
+ VFMT= GENMASK(3, 0),
+};
+
+/* Page 0, Register 0x54 */
+enum {
+
[PATCH v3 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a2da166df1bc7..0ab86d876f4d2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -185,6 +185,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 0/3] drm: Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is a driver for CH7033 along with device tree binding docs. I'm hoping that it could perhaps make it into 5.7. Please take a look. The only change compared to the previous submission [1] is the fix in the DT bindings example discovered by the validation tool. [1] https://lore.kernel.org/lkml/20200307190800.142658-1-lkund...@v3.sk/ Tested to work well on MMP3-based Dell Wyse 3020. There's no datasheet or programming manual available. Thanks, Lubo In-Reply-To: ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Fixed the example so that it validates
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..9f38f55fc9904
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019,2020 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
+};
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v2 0/3] Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is a driver for CH7033 along with device tree binding docs. I'm hoping that it could perhaps make it into 5.7. Please take a look. Previous submission [1] contained the exact same patches as this one, but at that time they relied on Laurent's omapdrm/bridge/devel branch that has been merged since. [1] https://lore.kernel.org/lkml/20200221162743.14141-1-lkund...@v3.sk/ Tested to work well on MMP3-based Dell Wyse 3020. There's no datasheet or programming manual available. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v2 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 675 +++
3 files changed, 686 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9d..0ebc72d62a5b2 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f04..a844315feddb4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..342b2e2bd2b1c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2b */
+enum {
+ SWAPS = GENMASK(7, 4),
+ VFMT= GENMASK(3, 0),
+};
+
+/* Page 0, Register 0x54 */
+enum {
+
[RESEND PATCH v2 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index a2da166df1bc7..0ab86d876f4d2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -185,6 +185,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.24.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RESEND PATCH v2 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 86 +++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..dc97f34fbfe0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+dvi-connector {
+compatible = "dvi-connector";
+ddc-i2c-bus = <>;
+hpd-gpios = < 62 GPIO_ACTIVE_LOW>;
+digital;
+analog;
+
+port {
+dvi_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+encoder_out: port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
--
2.24.1
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[PATCH v2 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Sort the includes
- Drop a useless model id read
- Chain to the bridge-connector instead of dealing with the HPD/EDID
readout machinery ourselves
- Utilize regmap to access the registers
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 675 +++
3 files changed, 686 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index aaed2347ace9d..0ebc72d62a5b2 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DISPLAY_CONNECTOR
tristate "Display connector support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 6fb062b5b0f04..a844315feddb4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..342b2e2bd2b1c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019,2020 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2b */
+enum {
+ SWAPS = GENMASK(7, 4),
+ VFMT= GENMASK(3, 0),
+};
+
+/* Page 0, Register 0x54 */
+enum {
+
[PATCH v2 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring --- Changes since v1: - Collect Rob's ack Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ac4804d0a9917..9c31cb4844aea 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -179,6 +179,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.24.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 86 +++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..dc97f34fbfe0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+dvi-connector {
+compatible = "dvi-connector";
+ddc-i2c-bus = <>;
+hpd-gpios = < 62 GPIO_ACTIVE_LOW>;
+digital;
+analog;
+
+port {
+dvi_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+encoder_out: port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
--
2.24.1
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[PATCH v2 0/3] Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is a driver for CH7033 along with device tree binding docs. Since the initial submission, issues pointed out in Laurent Pinchart's review [1] were addressed. Details in individual patches' change log. At his suggestion, the driver has been made to use bridge/display-connector. This allowed removing some fat, but for the time being it means that the patches apply against Laurent's branch [2] instead of master or drm-next. [1] https://lore.kernel.org/lkml/20191220074914.249281-1-lkund...@v3.sk/ [2] omapdrm/bridge/devel branch (at d27b7b2098de5) of git://linuxtv.org/pinchartl/media.git Tested to work well on MMP3-based Dell Wyse 3020. There's no datasheet or programming manual available. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 3/3] drm/armada: add mmp2 and mmp3 support
MMP2 and MMP3 are mostly the same apart from MMP3 having the clock
select shifted one bit to the right, with an extra option to choose PLL3
as a clock source.
Data sheet for neither variant is available. James Cameron of OLPC kindly
provided some details about the LCD_SCLK_DIV register for MMP2.
MMP2 support was tested on with the internal panel on a OLPC XO 1.75
laptop, while the MMP3 support was tested on a Dell Wyse 3020 with a
Chrontel 7033 encoder driving a VGA and DVI display.
Link: https://lists.freedesktop.org/archives/dri-devel/2018-December/201021.html
Signed-off-by: Lubomir Rintel
---
Changes since v2:
- Added Armada 620 (MMP3) support
Changes since v1:
- Aligned with more recent Armada 510 support: using the same clock
names and allowing for more flexible pixel clock source selection.
drivers/gpu/drm/armada/Makefile | 1 +
drivers/gpu/drm/armada/armada_6x0.c | 178 +++
drivers/gpu/drm/armada/armada_crtc.c | 8 ++
drivers/gpu/drm/armada/armada_drm.h | 2 +
drivers/gpu/drm/armada/armada_hw.h | 17 +++
5 files changed, 206 insertions(+)
create mode 100644 drivers/gpu/drm/armada/armada_6x0.c
diff --git a/drivers/gpu/drm/armada/Makefile b/drivers/gpu/drm/armada/Makefile
index 9bc3c32137248..80f7315bb6d20 100644
--- a/drivers/gpu/drm/armada/Makefile
+++ b/drivers/gpu/drm/armada/Makefile
@@ -2,6 +2,7 @@
armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \
armada_gem.o armada_overlay.o armada_plane.o armada_trace.o
armada-y += armada_510.o
+armada-y += armada_6x0.o
armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
obj-$(CONFIG_DRM_ARMADA) := armada.o
diff --git a/drivers/gpu/drm/armada/armada_6x0.c
b/drivers/gpu/drm/armada/armada_6x0.c
new file mode 100644
index 0..2053da32abea6
--- /dev/null
+++ b/drivers/gpu/drm/armada/armada_6x0.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2012 Russell King
+ * Copyright (C) 2018,2019,2020 Lubomir Rintel
+ * Largely based on Armada 510 support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Support for Armada MMP2 and MMP3 variants
+ */
+#include
+#include
+#include
+#include "armada_crtc.h"
+#include "armada_drm.h"
+#include "armada_hw.h"
+
+struct armada6x0_variant_data {
+ struct clk *clks[5];
+ struct clk *sel_clk;
+};
+
+static int armada6x0_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
+{
+ struct armada6x0_variant_data *v;
+ struct property *prop;
+ struct clk *clk;
+ const char *s;
+ int idx;
+
+ v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);
+ if (!v)
+ return -ENOMEM;
+
+ dcrtc->variant_data = v;
+
+ of_property_for_each_string(dev->of_node, "clock-names", prop, s) {
+ if (!strcmp(s, "ext_ref_clk0"))
+ idx = 0;
+ else if (!strcmp(s, "ext_ref_clk1"))
+ idx = 1;
+ else if (!strcmp(s, "plldivider"))
+ idx = 2;
+ else if (!strcmp(s, "axibus"))
+ idx = 3;
+ else if (!strcmp(s, "pll3"))
+ idx = 4;
+ else
+ continue;
+
+ clk = devm_clk_get(dev, s);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
+ PTR_ERR(clk);
+ v->clks[idx] = clk;
+ }
+
+ return 0;
+}
+
+static const struct armada_clocking_params armada6x0_clocking = {
+ /* HDMI requires -0.6%..+0.5% */
+ .permillage_min = 0,
+ .permillage_max = 2000,
+ .settable = BIT(0) | BIT(1) | BIT(2),
+ .div_max = SCLK_610_INT_DIV_MASK,
+};
+
+/*
+ * This gets called with sclk = NULL to test whether the mode is
+ * supportable, and again with sclk != NULL to set the clocks up for
+ * that. The former can return an error, but the latter is expected
+ * not to.
+ */
+static int armada6x0_crtc_compute_clock(struct armada_crtc *dcrtc,
+ const struct drm_display_mode *mode, uint32_t *sclk,
+ const u32 clk_sels[], size_t num_clk_sels)
+{
+ struct armada6x0_variant_data *v = dcrtc->variant_data;
+ unsigned long desired_khz = mode->crtc_clock;
+ struct armada_clk_result res;
+ int ret, idx;
+
+ idx = armada_crtc_select_clock(dcrtc, , _clocking,
+ v->clks, ARRAY_SIZE(v->clks),
+ desired_khz);
+ if (idx < 0)
+ return idx;
+ if (idx >= num_clk_sels)
+ return -EINVAL;
+
+ ret = clk_prepare_ena
[PATCH v3 2/3] drm/armada: optionally enable the peripheral clock
It needs to be enabled (at least on MMP2) in order for the register
writes to LCDC to work.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/armada/armada_crtc.c | 7 +++
drivers/gpu/drm/armada/armada_crtc.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/armada/armada_crtc.c
b/drivers/gpu/drm/armada/armada_crtc.c
index da9ba8be8b097..0f343bf584c8c 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -772,6 +772,7 @@ static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
of_node_put(dcrtc->crtc.port);
+ clk_disable_unprepare(dcrtc->periphclk);
kfree(dcrtc);
}
@@ -928,6 +929,11 @@ static int armada_drm_crtc_create(struct drm_device *drm,
struct device *dev,
dcrtc->clk = ERR_PTR(-EINVAL);
dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
+ dcrtc->periphclk = devm_clk_get(dev, "periph");
+ if (IS_ERR(dcrtc->periphclk))
+ dcrtc->periphclk = NULL;
+ WARN_ON(clk_prepare_enable(dcrtc->periphclk));
+
endpoint = of_get_next_child(port, NULL);
of_property_read_u32(endpoint, "bus-width", _width);
of_node_put(endpoint);
@@ -1015,6 +1021,7 @@ static int armada_drm_crtc_create(struct drm_device *drm,
struct device *dev,
err_crtc_init:
primary->funcs->destroy(primary);
err_crtc:
+ clk_disable_unprepare(dcrtc->periphclk);
kfree(dcrtc);
return ret;
diff --git a/drivers/gpu/drm/armada/armada_crtc.h
b/drivers/gpu/drm/armada/armada_crtc.h
index b21267d1745f1..48fc974a65808 100644
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -39,6 +39,7 @@ struct armada_crtc {
void*variant_data;
unsignednum;
void __iomem*base;
+ struct clk *periphclk;
struct clk *clk;
struct {
uint32_tspu_v_h_total;
--
2.24.1
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[PATCH v3 0/3] drm/armada: make it work on MMP2 and MMP3
Hi, chained to this message are patches that are necessary to make the Armada DRM driver useful on MMP2 and MMP3. They apply on top of drm-armada-devel. The first two patches were previously sent separately, around a year ago or so. The v2 of the third one previosly only implemented only MMP2 support. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/3] drm/bridge: chrontel-ch7033: Add a new driver
Hello Laurent,
On Wed, 2020-01-08 at 17:20 +0200, Laurent Pinchart wrote:
> Hi Lubomir,
>
> Thank you for the patch.
>
> On Fri, Dec 20, 2019 at 08:49:14AM +0100, Lubomir Rintel wrote:
> > This is a driver for video encoder with VGA and DVI/HDMI outputs.
> >
> > There is no documentation for the chip -- the operation was guessed from
> > what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
> > come from the ch7035 driver in Mediatek's GPL code dump.
> >
> > Only bare minimum is implemented -- no fancy stuff, such as scaling. That
> > would only worsen our misery. We don't load the firmware and we don't need
> > to even bother enabling the MCU. There are probably no distributable
> > firmware images anyway.
> >
> > Just like the tda998x driver, this one uses the component framework and
> > adds an encoder on component bind, so that it works with the Armada DRM
> > driver.
>
> Any chance the Armada DRM driver could use of_drm_find_bridge() to avoid
> having to use the component framework everywhere ?
Thanks for the response.
I've brought this up previously and the Armada DRM maintainer pointed
out that drm_bridge_remove() is essentialy a surprise removal [1].
Unlike the component unbind, it doesn't let the crtc driver know that
the bridge is gone. Understandably, he wasn't too fond of the idea of
losing the ability to unload the bridge driver and not much has changed
since.
[1] https://www.spinics.net/lists/dri-devel/msg201927.html
This shouldn't be too much of a problem (other than extra LOC in the
driver), because the bridge is registered outside the component bind
path, therefore the drivers that choose not to use the component
framework can use just the bridge alone just fine.
Thank you
Lubo
> > Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
> > with VGA as well as DVI.
> >
> > Signed-off-by: Lubomir Rintel
> > ---
> > drivers/gpu/drm/bridge/Kconfig | 10 +
> > drivers/gpu/drm/bridge/Makefile | 1 +
> > drivers/gpu/drm/bridge/chrontel-ch7033.c | 722 +++
> > 3 files changed, 733 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
> >
> > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> > index 34362976cd6fd..9456ea968c5b7 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -37,6 +37,16 @@ config DRM_CDNS_DSI
> > Support Cadence DPI to DSI bridge. This is an internal
> > bridge and is meant to be directly embedded in a SoC.
> >
> > +config DRM_CHRONTEL_CH7033
> > + tristate "Chrontel CH7033 Video Encoder"
> > + depends on OF
> > + select DRM_KMS_HELPER
> > + help
> > + Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
> > + found in the Dell Wyse 3020 thin client.
> > +
> > + If in doubt, say "N".
> > +
> > config DRM_DUMB_VGA_DAC
> > tristate "Dumb VGA DAC Bridge support"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile
> > b/drivers/gpu/drm/bridge/Makefile
> > index 4934fcf5a6f82..74a9ab2f17468 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -1,6 +1,7 @@
> > # SPDX-License-Identifier: GPL-2.0
> > obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> > +obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
> > obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
> > obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
> > obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
> > megachips-stdpxxxx-ge-b850v3-fw.o
> > diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > new file mode 100644
> > index 0..a3b63984226a4
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> > @@ -0,0 +1,722 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Chrontel CH7033 Video Encoder Driver
> > + *
> > + * Copyright (C) 2019 Lubomir Rintel
> > + */
> > +
> > +#include
> > +#include
> > +#include
>
> Could you please sort these alphabetically ?
>
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Page 0, Register 0x07 */
> > +enum {
> > + DRI_PD = BIT(3),
> > + IO_PD = BIT(5),
[PATCH v3 1/3] drm/armada: add bus-width property to the output endpoint
This makes it possible to choose a different pixel format for the
endpoint. Modelled after what other LCD controllers use, including
marvell,pxa2xx-lcdc and atmel,hlcdc-display-controller and perhaps more.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/armada/armada_crtc.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/armada/armada_crtc.c
b/drivers/gpu/drm/armada/armada_crtc.c
index c2b92acd1e9ad..da9ba8be8b097 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -904,6 +904,8 @@ static int armada_drm_crtc_create(struct drm_device *drm,
struct device *dev,
struct armada_private *priv = drm->dev_private;
struct armada_crtc *dcrtc;
struct drm_plane *primary;
+ struct device_node *endpoint;
+ u32 bus_width = 24;
void __iomem *base;
int ret;
@@ -923,8 +925,31 @@ static int armada_drm_crtc_create(struct drm_device *drm,
struct device *dev,
dcrtc->variant = variant;
dcrtc->base = base;
dcrtc->num = drm->mode_config.num_crtc;
- dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
+ dcrtc->clk = ERR_PTR(-EINVAL);
dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
+
+ endpoint = of_get_next_child(port, NULL);
+ of_property_read_u32(endpoint, "bus-width", _width);
+ of_node_put(endpoint);
+
+ switch (bus_width) {
+ case 12:
+ dcrtc->cfg_dumb_ctrl = DUMB12_RGB444_0;
+ break;
+ case 16:
+ dcrtc->cfg_dumb_ctrl = DUMB16_RGB565_0;
+ break;
+ case 18:
+ dcrtc->cfg_dumb_ctrl = DUMB18_RGB666_0;
+ break;
+ case 24:
+ dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
+ break;
+ default:
+ DRM_ERROR("unsupported bus width: %d\n", bus_width);
+ return -EINVAL;
+ }
+
spin_lock_init(>irq_lock);
dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
--
2.24.1
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[PATCH 2/3] dt-bindings: display: Add Chrontel CH7033 Video Encoder binding
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
---
.../display/bridge/chrontel,ch7033.yaml | 86 +++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
new file mode 100644
index 0..f19b336a99c78
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2019 Lubomir Rintel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chrontel CH7033 Video Encoder Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel
+
+properties:
+ compatible:
+const: chrontel,ch7033
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for RGB input.
+
+ port@1:
+type: object
+description: |
+ DVI port, should be connected to a node compatible with the
+ dvi-connector binding.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+dvi-connector {
+compatible = "dvi-connector";
+ddc-i2c-bus = <>;
+hpd-gpios = < 62 GPIO_ACTIVE_LOW>;
+digital;
+analog;
+
+port {
+dvi_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+
+vga-dvi-encoder@76 {
+compatible = "chrontel,ch7033";
+reg = <0x76>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_rgb_out>;
+};
+};
+
+encoder_out: port@1 {
+reg = <1>;
+endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+};
+};
--
2.24.1
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Add support for Chrontel CH7033 VGA/DVI Encoder
Hi, chained to this message is a driver for CH7033 along with device tree binding docs. Tested to work well on MMP3-based Dell Wyse 3020, some tweaks might be needed for other configurations. There's not datasheet or programming manual available. Thanks, Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] drm/bridge: chrontel-ch7033: Add a new driver
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is implemented -- no fancy stuff, such as scaling. That
would only worsen our misery. We don't load the firmware and we don't need
to even bother enabling the MCU. There are probably no distributable
firmware images anyway.
Just like the tda998x driver, this one uses the component framework and
adds an encoder on component bind, so that it works with the Armada DRM
driver.
Tested with a handful of monitors ranging from 1024x768@75 to 1400x1050@60,
with VGA as well as DVI.
Signed-off-by: Lubomir Rintel
---
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/chrontel-ch7033.c | 722 +++
3 files changed, 733 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/chrontel-ch7033.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 34362976cd6fd..9456ea968c5b7 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -37,6 +37,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CHRONTEL_CH7033
+ tristate "Chrontel CH7033 Video Encoder"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Enable support for the Chrontel CH7033 VGA/DVI/HDMI Encoder, as
+ found in the Dell Wyse 3020 thin client.
+
+ If in doubt, say "N".
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf5a6f82..74a9ab2f17468 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) +=
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
new file mode 100644
index 0..a3b63984226a4
--- /dev/null
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -0,0 +1,722 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Chrontel CH7033 Video Encoder Driver
+ *
+ * Copyright (C) 2019 Lubomir Rintel
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Page 0, Register 0x07 */
+enum {
+ DRI_PD = BIT(3),
+ IO_PD = BIT(5),
+};
+
+/* Page 0, Register 0x08 */
+enum {
+ DRI_PDDRI = GENMASK(7, 4),
+ PDDAC = GENMASK(3, 1),
+ PANEN = BIT(0),
+};
+
+/* Page 0, Register 0x09 */
+enum {
+ DPD = BIT(7),
+ GCKOFF = BIT(6),
+ TV_BP = BIT(5),
+ SCLPD = BIT(4),
+ SDPD= BIT(3),
+ VGA_PD = BIT(2),
+ HDBKPD = BIT(1),
+ HDMI_PD = BIT(0),
+};
+
+/* Page 0, Register 0x0a */
+enum {
+ MEMINIT = BIT(7),
+ MEMIDLE = BIT(6),
+ MEMPD = BIT(5),
+ STOP= BIT(4),
+ LVDS_PD = BIT(3),
+ HD_DVIB = BIT(2),
+ HDCP_PD = BIT(1),
+ MCU_PD = BIT(0),
+};
+
+/* Page 0, Register 0x18 */
+enum {
+ IDF = GENMASK(7, 4),
+ INTEN = BIT(3),
+ SWAP= GENMASK(2, 0),
+};
+
+enum {
+ BYTE_SWAP_RGB = 0,
+ BYTE_SWAP_RBG = 1,
+ BYTE_SWAP_GRB = 2,
+ BYTE_SWAP_GBR = 3,
+ BYTE_SWAP_BRG = 4,
+ BYTE_SWAP_BGR = 5,
+};
+
+/* Page 0, Register 0x19 */
+enum {
+ HPO_I = BIT(5),
+ VPO_I = BIT(4),
+ DEPO_I = BIT(3),
+ CRYS_EN = BIT(2),
+ GCLKFREQ= GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2e */
+enum {
+ HFLIP = BIT(7),
+ VFLIP = BIT(6),
+ DEPO_O = BIT(5),
+ HPO_O = BIT(4),
+ VPO_O = BIT(3),
+ TE = GENMASK(2, 0),
+};
+
+/* Page 0, Register 0x2b */
+enum {
+ SWAPS = GENMASK(7, 4),
+ VFMT= GENMASK(3, 0),
+};
+
+/* Page 0, Register 0x54 */
+enum {
+ COMP_BP = BIT(7),
+ DAC_EN_T= BIT(6),
+ HWO_HDMI_HI = GENMASK(5, 3),
+ HOO_HDMI_HI = GENMASK(2, 0),
+};
+
+/* Page 0, Register
[PATCH 1/3] dt-bindings: Add vendor prefix for Chrontel, Inc.
Chrontel makes encoders for video displays and perhaps other stuff. Their web site is http://www.chrontel.com/. Signed-off-by: Lubomir Rintel --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6046f45558525..3b71a10eae19e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -179,6 +179,8 @@ patternProperties: description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": +description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": -- 2.24.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] pxa168fb: Fix the function used to release some memory in an error handling path
On Sat, 2019-08-31 at 12:00 +0200, Christophe JAILLET wrote:
> In the probe function, some resources are allocated using 'dma_alloc_wc()',
> they should be released with 'dma_free_wc()', not 'dma_free_coherent()'.
>
> We already use 'dma_free_wc()' in the remove function, but not in the
> error handling path of the probe function.
>
> Also, remove a useless 'PAGE_ALIGN()'. 'info->fix.smem_len' is already
> PAGE_ALIGNed.
>
> Fixes: 638772c7553f ("fb: add support of LCD display controller on pxa168/910
> (base layer)")
> Signed-off-by: Christophe JAILLET
Reviewed-by: Lubomir Rintel
Thanks,
Lubo
> ---
> The change about PAGE_ALIGN should probably be part of a separate commit.
> However, git history for this driver is really quiet. If you think it
> REALLY deserves a separate patch, either split it by yourself or axe this
> part of the patch. I won't bother resubmitting for this lonely cleanup.
> Hoping for your understanding.
> ---
> drivers/video/fbdev/pxa168fb.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/video/fbdev/pxa168fb.c b/drivers/video/fbdev/pxa168fb.c
> index 1410f476e135..1fc50fc0694b 100644
> --- a/drivers/video/fbdev/pxa168fb.c
> +++ b/drivers/video/fbdev/pxa168fb.c
> @@ -766,8 +766,8 @@ static int pxa168fb_probe(struct platform_device *pdev)
> failed_free_clk:
> clk_disable_unprepare(fbi->clk);
> failed_free_fbmem:
> - dma_free_coherent(fbi->dev, info->fix.smem_len,
> - info->screen_base, fbi->fb_start_dma);
> + dma_free_wc(fbi->dev, info->fix.smem_len,
> + info->screen_base, fbi->fb_start_dma);
> failed_free_info:
> kfree(info);
>
> @@ -801,7 +801,7 @@ static int pxa168fb_remove(struct platform_device *pdev)
>
> irq = platform_get_irq(pdev, 0);
>
> - dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
> + dma_free_wc(fbi->dev, info->fix.smem_len,
> info->screen_base, info->fix.smem_start);
>
> clk_disable_unprepare(fbi->clk);
[PATCH v4 1/5] dt-bindings: reserved-memory: Add binding for Armada framebuffer
This is the binding for memory that is set aside for allocation of Marvell
Armada framebuffer objects.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v2:
- Collected the Reviewed-by tag
Changes since v1:
- Moved from bindings/display/armada/
- Removed the marvell,dove-framebuffer string
- Added to the MAINTAINERS entry
.../marvell,armada-framebuffer.txt| 22 +++
MAINTAINERS | 1 +
2 files changed, 23 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
diff --git
a/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
b/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
new file mode 100644
index 0..ab243e2bad454
--- /dev/null
+++
b/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
@@ -0,0 +1,22 @@
+Marvell Armada framebuffer reserved memory
+==
+
+Memory set aside for allocation of Marvell Armada framebuffer objects.
+
+Required properties:
+
+ - compatible: must be "marvell,armada-framebuffer"
+
+Please refer to
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+for common reserved memory binding usage.
+
+Example:
+
+ reserved-memory {
+ display_reserved: framebuffer {
+ compatible = "marvell,armada-framebuffer";
+ size = <0x0200>;
+ alignment = <0x0200>;
+ no-map;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9cbcf167bdd08..3d824ecf96229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9621,6 +9621,7 @@ T:git
git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
F: drivers/gpu/drm/armada/
F: include/uapi/drm/armada_drm.h
F: Documentation/devicetree/bindings/display/armada/
+F:
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
MARVELL ARMADA 3700 PHY DRIVERS
M: Miquel Raynal
--
2.21.0
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[PATCH v4 5/5] dt-bindings: display: armada: Document bus-width property
This makes it possible to choose a different pixel format for the
endpoint. Modelled after what other LCD controllers use, including
marvell,pxa2xx-lcdc and atmel,hlcdc-display-controller and perhaps more.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v2:
- Collected the Reviewed-by tag
.../devicetree/bindings/display/marvell,armada-lcdc.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
index 0ea4cbe5a32ee..d1dadaaeee734 100644
--- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
+++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
@@ -25,6 +25,11 @@ Required child nodes:
- port: video output port with endpoints, as described by
Documentation/devicetree/bindings/graph.txt
+ The endpoints can optionally specify the following property:
+
+ - bus-width: recognized values are <12>, <16>, <18> and <24>, that
+select "rgb444", "rgb565", "rgb666" or "rgb888" pixel format
+respectively. Defaults to <24> if unspecified.
Example:
@@ -37,6 +42,7 @@ Example:
lcd0_port: port {
lcd0_rgb_out: endpoint {
+ bus-width = <24>;
remote-endpoint = <_rgb_in>;
};
};
--
2.21.0
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[PATCH v4 0/5] dt-bindings: improve the Armada DRM bindings
Hi, this is the fourth spin of a patch set that aims to complete the Armada DRM binding documentation. The only change from the last version is the addition of Reviewed-by tags. What is documented corresponds to the armada-devel branch of git://git.armlinux.org.uk/~rmk/linux-arm.git with these differencies: * Documentation of the bus-width property of the LCDC * The MMP2 compatible strings. Patches to the driver for the above were sent out separately. Lubo
[PATCH v4 2/5] dt-bindings: display: armada: Rename the binding doc file
Use a more generic name, since it will document more compatible LCD
controllers than just that of Dove. Also, there's no point putting it in
a separate directory.
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Choose a better name than armada/marvell-armada-drm.txt, since
there will be no display-subsystem master node and thus it will
only document just the LCDC.
.../{armada/marvell,dove-lcd.txt => marvell,armada-lcdc.txt}| 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/display/{armada/marvell,dove-lcd.txt
=> marvell,armada-lcdc.txt} (100%)
diff --git
a/Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
similarity index 100%
rename from
Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt
rename to Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d824ecf96229..d379acd4f69ce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9620,7 +9620,7 @@ T:git
git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
F: drivers/gpu/drm/armada/
F: include/uapi/drm/armada_drm.h
-F: Documentation/devicetree/bindings/display/armada/
+F: Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
F:
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
MARVELL ARMADA 3700 PHY DRIVERS
--
2.21.0
[PATCH v4 3/5] dt-bindings: display: armada: Improve the LCDC documentation
The port is a child, not a property. And should be accompanied by an
example. Plus a pair of cosmetic changes that don't seem to deserve a
separate commit.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v3:
- Actually collected the Reviewed-by tag
Changes since v2:
- Collected the Reviewed-by tag
Changes since v1:
- Minor adjustments to the commit message wording.
.../bindings/display/marvell,armada-lcdc.txt | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
index 46525ea3e646e..2606a8efc9568 100644
--- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
+++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
@@ -1,10 +1,11 @@
-Device Tree bindings for Armada DRM CRTC driver
+Marvell Armada LCD controller
+=
Required properties:
+
- compatible: value should be "marvell,dove-lcd".
- reg: base address and size of the LCD controller
- interrupts: single interrupt number for the LCD controller
- - port: video output port with endpoints, as described by graph.txt
Optional properties:
@@ -19,6 +20,11 @@ Note: all clocks are optional but at least one must be
specified.
Further clocks may be added in the future according to requirements of
different SoCs.
+Required child nodes:
+
+- port: video output port with endpoints, as described by
+ Documentation/devicetree/bindings/graph.txt
+
Example:
lcd0: lcd-controller@82 {
@@ -27,4 +33,10 @@ Example:
interrupts = <47>;
clocks = < 0>;
clock-names = "ext_ref_clk_1";
+
+ lcd0_port: port {
+ lcd0_rgb_out: endpoint {
+ remote-endpoint = <_rgb_in>;
+ };
+ };
};
--
2.21.0
[PATCH v4 4/5] dt-bindings: display: armada: Add more compatible strings
There's a generic compatible string and the driver will work on a MMP2 as well, using the same binding. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- Changes since v3: - Collected Rob's Reviewed-by tag Changes since v2: - Order marvell,armada-lcdc after the model-specific strings. Changes since v1: - Added marvell,armada-lcdc compatible string. .../devicetree/bindings/display/marvell,armada-lcdc.txt| 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt index 2606a8efc9568..0ea4cbe5a32ee 100644 --- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt +++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt @@ -3,7 +3,8 @@ Marvell Armada LCD controller Required properties: - - compatible: value should be "marvell,dove-lcd". + - compatible: value should be "marvell,dove-lcd" or "marvell,mmp2-lcd", + depending on the exact SoC model, along with "marvell,armada-lcdc" - reg: base address and size of the LCD controller - interrupts: single interrupt number for the LCD controller -- 2.21.0
[PATCH] backlight: tdo24m: Switch to SPDX header
The original license text had a typo ("publishhed") which would be
likely to confuse automated licensing auditing tools. Let's just switch
to SPDX instead of fixing the wording.
Signed-off-by: Lubomir Rintel
---
drivers/video/backlight/tdo24m.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/video/backlight/tdo24m.c b/drivers/video/backlight/tdo24m.c
index e4bd63e9db6b..8c84f168d8d1 100644
--- a/drivers/video/backlight/tdo24m.c
+++ b/drivers/video/backlight/tdo24m.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
*
* Copyright (C) 2008 Marvell International Ltd.
* Eric Miao
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
*/
#include
--
2.21.0
[PATCH] etnaviv: allow building on MMP
MMP2 has a GC860 core. Signed-off-by: Lubomir Rintel --- drivers/gpu/drm/etnaviv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig index 041a77e400d4..7616f695270f 100644 --- a/drivers/gpu/drm/etnaviv/Kconfig +++ b/drivers/gpu/drm/etnaviv/Kconfig @@ -2,7 +2,7 @@ config DRM_ETNAVIV tristate "ETNAVIV (DRM support for Vivante GPU IP cores)" depends on DRM - depends on ARCH_MXC || ARCH_DOVE || (ARM && COMPILE_TEST) + depends on ARCH_MXC || ARCH_DOVE || ARCH_MMP || (ARM && COMPILE_TEST) depends on MMU select SHMEM select SYNC_FILE -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] etnaviv: allow building on MMP
On Tue, 2019-04-16 at 18:01 +0200, Lubomir Rintel wrote: > MMP2 has a GC860 core. > > Signed-off-by: Lubomir Rintel > --- > drivers/gpu/drm/etnaviv/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig > index 041a77e400d4..7616f695270f 100644 > --- a/drivers/gpu/drm/etnaviv/Kconfig > +++ b/drivers/gpu/drm/etnaviv/Kconfig > @@ -2,7 +2,7 @@ > config DRM_ETNAVIV > tristate "ETNAVIV (DRM support for Vivante GPU IP cores)" > depends on DRM > - depends on ARCH_MXC || ARCH_DOVE || (ARM && COMPILE_TEST) > + depends on ARCH_MXC || ARCH_DOVE || ARCH_MMP || (ARM && COMPILE_TEST) > depends on MMU > select SHMEM > select SYNC_FILE Just noticed this is solved in 5.1. Please ignore this. Sorry for the noise. Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH libdrm] tests/util: Add armada-drm driver
This makes the test utilities work with the Armada driver without the
necessity of using the -M argument.
Signed-off-by: Lubomir Rintel
---
tests/util/kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/util/kms.c b/tests/util/kms.c
index 5af8bf20..dd1bbee3 100644
--- a/tests/util/kms.c
+++ b/tests/util/kms.c
@@ -146,6 +146,7 @@ static const char * const modules[] = {
"pl111",
"stm",
"sun4i-drm",
+ "armada-drm",
};
int util_open(const char *device, const char *module)
--
2.21.0
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[PATCH v3 3/5] dt-bindings: display: armada: Improve the LCDC documentation
The port is a child, not a property. And should be accompanied by an
example. Plus a pair of cosmetic changes that don't seem to deserve a
separate commit.
Signed-off-by: Lubomir Rintel
---
Changes since v2:
- Collected the Reviewed-by tag
Changes since v1:
- Minor adjustments to the commit message wording.
.../bindings/display/marvell,armada-lcdc.txt | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
index 46525ea3e646..2606a8efc956 100644
--- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
+++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
@@ -1,10 +1,11 @@
-Device Tree bindings for Armada DRM CRTC driver
+Marvell Armada LCD controller
+=
Required properties:
+
- compatible: value should be "marvell,dove-lcd".
- reg: base address and size of the LCD controller
- interrupts: single interrupt number for the LCD controller
- - port: video output port with endpoints, as described by graph.txt
Optional properties:
@@ -19,6 +20,11 @@ Note: all clocks are optional but at least one must be
specified.
Further clocks may be added in the future according to requirements of
different SoCs.
+Required child nodes:
+
+- port: video output port with endpoints, as described by
+ Documentation/devicetree/bindings/graph.txt
+
Example:
lcd0: lcd-controller@82 {
@@ -27,4 +33,10 @@ Example:
interrupts = <47>;
clocks = < 0>;
clock-names = "ext_ref_clk_1";
+
+ lcd0_port: port {
+ lcd0_rgb_out: endpoint {
+ remote-endpoint = <_rgb_in>;
+ };
+ };
};
--
2.20.1
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[PATCH v3 0/5] dt-bindings: improve the Armada DRM bindings
Hi, this is the third spin of a patch set that aims to complete the Armada DRM binding documentation. Apart from collecting the Review-by tags, the only change is the order of the compatible strings for the LCDC node. What is documented corresponds to the armada-devel branch of git://git.armlinux.org.uk/~rmk/linux-arm.git with these differencies: * Documentation of the bus-width property of the LCDC * The MMP2 compatible strings. Patches to the driver for the above were sent out separately. Lubo ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 4/5] dt-bindings: display: armada: Add more compatible strings
There's a generic compatible string and the driver will work on a MMP2 as well, using the same binding. Signed-off-by: Lubomir Rintel --- Changes since v2: - Order marvell,armada-lcdc after the model-specific strings. Changes since v1: - Added marvell,armada-lcdc compatible string. .../devicetree/bindings/display/marvell,armada-lcdc.txt| 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt index 2606a8efc956..0ea4cbe5a32e 100644 --- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt +++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt @@ -3,7 +3,8 @@ Marvell Armada LCD controller Required properties: - - compatible: value should be "marvell,dove-lcd". + - compatible: value should be "marvell,dove-lcd" or "marvell,mmp2-lcd", + depending on the exact SoC model, along with "marvell,armada-lcdc" - reg: base address and size of the LCD controller - interrupts: single interrupt number for the LCD controller -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 5/5] dt-bindings: display: armada: Document bus-width property
This makes it possible to choose a different pixel format for the
endpoint. Modelled after what other LCD controllers use, including
marvell,pxa2xx-lcdc and atmel,hlcdc-display-controller and perhaps more.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v2:
- Collected the Reviewed-by tag
.../devicetree/bindings/display/marvell,armada-lcdc.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
index 0ea4cbe5a32e..d1dadaaeee73 100644
--- a/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
+++ b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
@@ -25,6 +25,11 @@ Required child nodes:
- port: video output port with endpoints, as described by
Documentation/devicetree/bindings/graph.txt
+ The endpoints can optionally specify the following property:
+
+ - bus-width: recognized values are <12>, <16>, <18> and <24>, that
+select "rgb444", "rgb565", "rgb666" or "rgb888" pixel format
+respectively. Defaults to <24> if unspecified.
Example:
@@ -37,6 +42,7 @@ Example:
lcd0_port: port {
lcd0_rgb_out: endpoint {
+ bus-width = <24>;
remote-endpoint = <_rgb_in>;
};
};
--
2.20.1
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[PATCH v3 1/5] dt-bindings: reserved-memory: Add binding for Armada framebuffer
This is the binding for memory that is set aside for allocation of Marvell
Armada framebuffer objects.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v2:
- Collected the Reviewed-by tag
Changes since v1:
- Moved from bindings/display/armada/
- Removed the marvell,dove-framebuffer string
- Added to the MAINTAINERS entry
.../marvell,armada-framebuffer.txt| 22 +++
MAINTAINERS | 1 +
2 files changed, 23 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
diff --git
a/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
b/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
new file mode 100644
index ..ab243e2bad45
--- /dev/null
+++
b/Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
@@ -0,0 +1,22 @@
+Marvell Armada framebuffer reserved memory
+==
+
+Memory set aside for allocation of Marvell Armada framebuffer objects.
+
+Required properties:
+
+ - compatible: must be "marvell,armada-framebuffer"
+
+Please refer to
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+for common reserved memory binding usage.
+
+Example:
+
+ reserved-memory {
+ display_reserved: framebuffer {
+ compatible = "marvell,armada-framebuffer";
+ size = <0x0200>;
+ alignment = <0x0200>;
+ no-map;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index f3a5c97e3419..e71aa05fef29 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8967,6 +8967,7 @@ T:git
git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
F: drivers/gpu/drm/armada/
F: include/uapi/drm/armada_drm.h
F: Documentation/devicetree/bindings/display/armada/
+F:
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
MARVELL CRYPTO DRIVER
M: Boris Brezillon
--
2.20.1
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[PATCH v3 2/5] dt-bindings: display: armada: Rename the binding doc file
Use a more generic name, since it will document more compatible LCD
controllers than just that of Dove. Also, there's no point putting it in
a separate directory.
Signed-off-by: Lubomir Rintel
---
Changes since v1:
- Choose a better name than armada/marvell-armada-drm.txt, since
there will be no display-subsystem master node and thus it will
only document just the LCDC.
.../{armada/marvell,dove-lcd.txt => marvell,armada-lcdc.txt}| 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/display/{armada/marvell,dove-lcd.txt
=> marvell,armada-lcdc.txt} (100%)
diff --git
a/Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt
b/Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
similarity index 100%
rename from
Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt
rename to Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index e71aa05fef29..890cbd6e0b7b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8966,7 +8966,7 @@ T:git
git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
F: drivers/gpu/drm/armada/
F: include/uapi/drm/armada_drm.h
-F: Documentation/devicetree/bindings/display/armada/
+F: Documentation/devicetree/bindings/display/marvell,armada-lcdc.txt
F:
Documentation/devicetree/bindings/reserved-memory/marvell,armada-framebuffer.txt
MARVELL CRYPTO DRIVER
--
2.20.1
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