from:"Mark Yao"

Re: [PATCH 2/2] drm/rockchip: vop: add rk3126 vop support

2017-11-15 Thread Mark yao


On 2017年11月14日 19:27, Sandy Huang wrote:

RK3126 vop register layout is similar with rk3036, so some feature
can reuse with rk3036.

RK3126 support two overlay plane and one hwc plane, max output
resolution is 1080p. it support IOMMU, and its IOMMU same as
rk3288's

Signed-off-by: Sandy Huang <h...@rock-chips.com>


Looks good.

Reviewed-by:  Mark Yao <mark@rock-chips.com>


---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 30 +
  drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  6 ++
  2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 4a39049..2e4eea3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -149,6 +149,34 @@ static const struct vop_data rk3036_vop = {
.win_size = ARRAY_SIZE(rk3036_vop_win_data),
  };
  
+static const struct vop_win_phy rk3126_win1_data = {

+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
+   .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
+   .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
+   .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0x, 0),
+};
+
+static const struct vop_win_data rk3126_vop_win_data[] = {
+   { .base = 0x00, .phy = _win0_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x00, .phy = _win1_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_data rk3126_vop = {
+   .intr = _intr,
+   .common = _common,
+   .modeset = _modeset,
+   .output = _output,
+   .win = rk3126_vop_win_data,
+   .win_size = ARRAY_SIZE(rk3126_vop_win_data),
+};
+
  static const struct vop_scl_extension rk3288_win_full_scl_ext = {
.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
@@ -510,6 +538,8 @@ static const struct vop_data rk3328_vop = {
  static const struct of_device_id vop_driver_dt_match[] = {
{ .compatible = "rockchip,rk3036-vop",
  .data = _vop },
+   { .compatible = "rockchip,rk3126-vop",
+ .data = _vop },
{ .compatible = "rockchip,rk3288-vop",
  .data = _vop },
{ .compatible = "rockchip,rk3368-vop",
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 4a4799f..f81b510 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -878,4 +878,10 @@
  #define RK3036_HWC_LUT_ADDR   0x800
  /* rk3036 register definition end */
  
+/* rk3126 register definition */

+#define RK3126_WIN1_MST0x4c
+#define RK3126_WIN1_DSP_INFO   0x50
+#define RK3126_WIN1_DSP_ST 0x54
+/* rk3126 register definition end */
+
  #endif /* _ROCKCHIP_VOP_REG_H */


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Re: [PATCH 2/2] drm/rockchip: vop: add rk3126 vop support

2017-11-15 Thread Mark yao


On 2017年11月14日 19:27, Sandy Huang wrote:

RK3126 vop register layout is similar with rk3036, so some feature
can reuse with rk3036.

RK3126 support two overlay plane and one hwc plane, max output
resolution is 1080p. it support IOMMU, and its IOMMU same as
rk3288's

Signed-off-by: Sandy Huang <h...@rock-chips.com>


Looks good.
Reviewed-by:  Mark Yao <mark@rock-chips.com>


---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 30 +
  drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  6 ++
  2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 4a39049..2e4eea3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -149,6 +149,34 @@ static const struct vop_data rk3036_vop = {
.win_size = ARRAY_SIZE(rk3036_vop_win_data),
  };
  
+static const struct vop_win_phy rk3126_win1_data = {

+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
+   .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
+   .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
+   .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0x, 0),
+};
+
+static const struct vop_win_data rk3126_vop_win_data[] = {
+   { .base = 0x00, .phy = _win0_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x00, .phy = _win1_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_data rk3126_vop = {
+   .intr = _intr,
+   .common = _common,
+   .modeset = _modeset,
+   .output = _output,
+   .win = rk3126_vop_win_data,
+   .win_size = ARRAY_SIZE(rk3126_vop_win_data),
+};
+
  static const struct vop_scl_extension rk3288_win_full_scl_ext = {
.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
@@ -510,6 +538,8 @@ static const struct vop_data rk3328_vop = {
  static const struct of_device_id vop_driver_dt_match[] = {
{ .compatible = "rockchip,rk3036-vop",
  .data = _vop },
+   { .compatible = "rockchip,rk3126-vop",
+ .data = _vop },
{ .compatible = "rockchip,rk3288-vop",
  .data = _vop },
{ .compatible = "rockchip,rk3368-vop",
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 4a4799f..f81b510 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -878,4 +878,10 @@
  #define RK3036_HWC_LUT_ADDR   0x800
  /* rk3036 register definition end */
  
+/* rk3126 register definition */

+#define RK3126_WIN1_MST0x4c
+#define RK3126_WIN1_DSP_INFO   0x50
+#define RK3126_WIN1_DSP_ST 0x54
+/* rk3126 register definition end */
+
  #endif /* _ROCKCHIP_VOP_REG_H */


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[PATCH] MAINTAINERS: change maintainer for Rockchip drm drivers

2017-11-13 Thread Mark Yao

For personal reasons, Mark Yao will leave rockchip,
can not continue maintain drm/rockchip, Sandy Huang
will take over the drm/rockchip.

Cc: Sandy Huang <h...@rock-chips.com>
Cc: Heiko Stuebner <he...@sntech.de>

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0d77f22..31bf080 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4627,7 +4627,7 @@ F:
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
 F: Documentation/devicetree/bindings/display/renesas,du.txt
 
 DRM DRIVERS FOR ROCKCHIP
-M: Mark Yao <mark@rock-chips.com>
+M: Sandy Huang <h...@rock-chips.com>
 L: dri-devel@lists.freedesktop.org
 S: Maintained
 F: drivers/gpu/drm/rockchip/
-- 
2.7.4


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Re: [PATCH v6 10/10] drm/rockchip: dw_hdmi: Fix error handling path

2017-10-19 Thread Mark yao


On 2017年10月19日 11:48, Jeffy Chen wrote:

Add missing clk_disable_unprepare() in bind()'s error handling path and
unbind().

Also inline clk_prepare_enable() with bind().

Fixes: 12b9f204e804 ("drm: bridge/dw_hdmi: add rockchip rk3288 support")
Signed-off-by: Jeffy Chen<jeffy.c...@rock-chips.com>


Looks good for me
Acked-by: Mark Yao <mark@rock-chips.com>

Mark


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Re: [PATCH v6 07/10] drm/rockchip: inno_hdmi: Fix error handling path

2017-10-19 Thread Mark yao


On 2017年10月19日 11:48, Jeffy Chen wrote:

Add missing error handling in bind().

Fixes: 412d4ae6b7a5 ("drm/rockchip: hdmi: add Innosilicon HDMI support")
Signed-off-by: Jeffy Chen<jeffy.c...@rock-chips.com>


Looks good for me
Acked-by: Mark Yao <mark@rock-chips.com>

Mark


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Re: [PATCH v6 06/10] drm/rockchip: dw-mipi-dsi: Fix error handling path

2017-10-19 Thread Mark yao


On 2017年10月19日 11:48, Jeffy Chen wrote:

Add missing pm_runtime_disable() in bind()'s error handling path.

Also cleanup encoder & connector in unbind().

Fixes: 80a9a059d4e4 ("drm/rockchip/dsi: add dw-mipi power domain support")
Signed-off-by: Jeffy Chen<jeffy.c...@rock-chips.com>


Looks good for me
Acked-by: Mark Yao <mark@rock-chips.com>

Mark


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Re: [PATCH v6 05/10] drm/rockchip: analogix_dp: Add a sanity check for rockchip_drm_psr_register()

2017-10-19 Thread Mark yao


On 2017年10月19日 11:48, Jeffy Chen wrote:

The rockchip_drm_psr_register() can fail, so add a sanity check for that.

Also reorder the calls in unbind() to match bind().

Signed-off-by: Jeffy Chen<jeffy.c...@rock-chips.com>


Looks good for me
Acked-by: Mark Yao <mark@rock-chips.com>

Mark


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Re: [PATCH v6 02/10] drm/rockchip: analogix_dp: Remove unnecessary init code

2017-10-19 Thread Mark yao


On 2017年10月19日 11:48, Jeffy Chen wrote:

Remove unnecessary init code, since we would do it in the power_on()
callback.

Also move of parse code to probe().

Fixes: 9e32e16e9e98 ("drm: rockchip: dp: add rockchip platform dp driver")
Signed-off-by: Jeffy Chen <jeffy.c...@rock-chips.com>


Looks good for me
Acked-by: Mark Yao <mark@rock-chips.com>


---

Changes in v6: None
Changes in v5: None

  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 27 ++---
  1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 4d3f6ad0abdd..8cae5ad926cd 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -269,7 +269,7 @@ static struct drm_encoder_funcs rockchip_dp_encoder_funcs = 
{
.destroy = rockchip_dp_drm_encoder_destroy,
  };
  
-static int rockchip_dp_init(struct rockchip_dp_device *dp)

+static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
  {
struct device *dev = dp->dev;
struct device_node *np = dev->of_node;
@@ -303,19 +303,6 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
return PTR_ERR(dp->rst);
}
  
-	ret = clk_prepare_enable(dp->pclk);

-   if (ret < 0) {
-   DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
-   return ret;
-   }
-
-   ret = rockchip_dp_pre_init(dp);
-   if (ret < 0) {
-   DRM_DEV_ERROR(dp->dev, "failed to pre init %d\n", ret);
-   clk_disable_unprepare(dp->pclk);
-   return ret;
-   }
-
return 0;
  }
  
@@ -361,10 +348,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,

if (!dp_data)
return -ENODEV;
  
-	ret = rockchip_dp_init(dp);

-   if (ret < 0)
-   return ret;
-
dp->data = dp_data;
dp->drm_dev = drm_dev;
  
@@ -398,7 +381,6 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master,

rockchip_drm_psr_unregister(>encoder);
  
  	analogix_dp_unbind(dev, master, data);

-   clk_disable_unprepare(dp->pclk);
  }
  
  static const struct component_ops rockchip_dp_component_ops = {

@@ -414,7 +396,7 @@ static int rockchip_dp_probe(struct platform_device *pdev)
int ret;
  
  	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, , NULL);

-   if (ret)
+   if (ret < 0)
return ret;
  
  	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);

@@ -422,9 +404,12 @@ static int rockchip_dp_probe(struct platform_device *pdev)
return -ENOMEM;
  
  	dp->dev = dev;

-
dp->plat_data.panel = panel;
  
+	ret = rockchip_dp_of_probe(dp);

+   if (ret < 0)
+   return ret;
+
/*
 * We just use the drvdata until driver run into component
 * add function, and then we would set drvdata to null, so


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Re: [PATCH v2] drm/rockchip: Use an enum to identify Rockchip VOPs

2017-10-19 Thread Mark yao


On 2017年10月20日 01:46, Kristian Høgsberg wrote:

On Wed, Oct 18, 2017 at 5:49 PM, Mark yao <mark@rock-chips.com> wrote:

On 2017年10月19日 01:52, Brian Norris wrote:

Hi Kristian,

On Thu, Nov 03, 2016 at 12:46:48PM -0700, Kristian Högsberg wrote:

We used to call drm_of_encoder_active_endpoint_id() from
rockchip_dp_drm_encoder_atomic_check() to determine the endpoint for the
active encoder. However, the encoder isn't necessarily active at this
point or it may be connected to different crtc than what we're switching
to. Instead, look at the crtc from the drm_crtc_state.  This fixes wrong
colors when driving the eDP with the big VOP.  Further, we can identify
the type of VOP we're dealing with by just putting a VOP id enum in the
vop_data.


Unfortunately, vop iomux and vop data are not one-to-one correspondence.

Such as rk3288, vop big and vop little both use rk3288_vop data, if you use
vop data id will not be able
to distinguish between them.

What would you suggest then? We need this to be able to drive eDP from
the big VOP. We've been carrying this patch for quite a while and it
hasn't regressed neither rk3288 nor rk3399 boards.

Kristian


Mark


On way to test this is to use the modetest tool from libdrm:

$ modetest -M rockchip -s 32@28:2400x1600

which displays dark or black colors because we fail to look up the
endpoint and use default 0 (which is ROCKCHIP_OUT_MODE_P888) for big
VOP instead of RGB10 as required.


The display issue already be fixed, and your kernel seems old
See the patch: 
http://patchwork.freedesktop.org/patch/msgid/1495885416-22216-1-git-send-email-mark@rock-chips.com

Now eDP always set its outmode as ROCKCHIP_OUT_MODE_.

And on vop driver, force RGB10 to RGB888 if vop not support rgb10bit.
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:
/*
 * if vop is not support RGB10 output, need force RGB10 to RGB888.
 */
if (s->output_mode == ROCKCHIP_OUT_MODE_ &&
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
s->output_mode = ROCKCHIP_OUT_MODE_P888;

Thanks.


For reference,

$ modetest -M rockchip -s 32@25:2400x1600

drives the eDP from little VOP and displays correctly.

Signed-off-by: Kristian H. Kristensen <hoegsb...@chromium.org>
---
v2: Stripped chromeos annotations, fix compile errors for drivers I
didn't
compile when I first wrote the patch.

Do you plan to fix the errors Guenter pointed out and resend? This is
still causing conflicts between our ChromeOS kernel trees and upstream.

Also, please CC linux-rockchip on Rockchip-related patches. It's much
easier for me to find your work that way :)

Brian


drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 45
++---
   drivers/gpu/drm/rockchip/cdn-dp-core.c  | 19 +--
   drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 12 ---
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  7 
   drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++
   drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  4 +++
   6 files changed, 56 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 558a3bc..9ae4a9c 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -196,14 +196,16 @@ static void rockchip_dp_drm_encoder_enable(struct
drm_encoder *encoder)
 int ret;
 u32 val;
   - ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
encoder);
-   if (ret < 0)
-   return;
-
-   if (ret)
+   switch (vop_get_crtc_vop_id(encoder->crtc)) {
+   case RK3399_VOP_LIT:
 val = dp->data->lcdsel_lit;
-   else
+   break;
+   case RK3399_VOP_BIG:
 val = dp->data->lcdsel_big;
+   break;
+   default:
+   return;
+   }
 dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
   @@ -231,34 +233,23 @@ rockchip_dp_drm_encoder_atomic_check(struct
drm_encoder *encoder,
   struct drm_connector_state
*conn_state)
   {
 struct rockchip_crtc_state *s =
to_rockchip_crtc_state(crtc_state);
-   struct rockchip_dp_device *dp = to_dp(encoder);
-   int ret;
   - /*
-* The hardware IC designed that VOP must output the RGB10 video
-* format to eDP contoller, and if eDP panel only support RGB8,
-* then eDP contoller should cut down the video data, not via VOP
-* contoller, that's why we need to hardcode the VOP output mode
-* to RGA10 here.
-*/
-
-   ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
encoder);
-   if (ret < 0)
-   return 0;
-
-   switch (dp->data->chip_type) {
-   case RK3399_EDP:
+   switch (vop_get_crtc_vop_id(crtc_stat

Re: [PATCH v2] drm/rockchip: Use an enum to identify Rockchip VOPs

2017-10-18 Thread Mark yao


On 2017年10月19日 01:52, Brian Norris wrote:

Hi Kristian,

On Thu, Nov 03, 2016 at 12:46:48PM -0700, Kristian Högsberg wrote:

We used to call drm_of_encoder_active_endpoint_id() from
rockchip_dp_drm_encoder_atomic_check() to determine the endpoint for the
active encoder. However, the encoder isn't necessarily active at this
point or it may be connected to different crtc than what we're switching
to. Instead, look at the crtc from the drm_crtc_state.  This fixes wrong
colors when driving the eDP with the big VOP.  Further, we can identify
the type of VOP we're dealing with by just putting a VOP id enum in the
vop_data.


Unfortunately, vop iomux and vop data are not one-to-one correspondence.

Such as rk3288, vop big and vop little both use rk3288_vop data, if you use vop 
data id will not be able
to distinguish between them.

Mark


On way to test this is to use the modetest tool from libdrm:

   $ modetest -M rockchip -s 32@28:2400x1600

which displays dark or black colors because we fail to look up the
endpoint and use default 0 (which is ROCKCHIP_OUT_MODE_P888) for big
VOP instead of RGB10 as required.

For reference,

   $ modetest -M rockchip -s 32@25:2400x1600

drives the eDP from little VOP and displays correctly.

Signed-off-by: Kristian H. Kristensen 
---
v2: Stripped chromeos annotations, fix compile errors for drivers I didn't
compile when I first wrote the patch.

Do you plan to fix the errors Guenter pointed out and resend? This is
still causing conflicts between our ChromeOS kernel trees and upstream.

Also, please CC linux-rockchip on Rockchip-related patches. It's much
easier for me to find your work that way :)

Brian


drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 45 ++---
  drivers/gpu/drm/rockchip/cdn-dp-core.c  | 19 +--
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 12 ---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  7 
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  4 +++
  6 files changed, 56 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 558a3bc..9ae4a9c 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -196,14 +196,16 @@ static void rockchip_dp_drm_encoder_enable(struct 
drm_encoder *encoder)
int ret;
u32 val;
  
-	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);

-   if (ret < 0)
-   return;
-
-   if (ret)
+   switch (vop_get_crtc_vop_id(encoder->crtc)) {
+   case RK3399_VOP_LIT:
val = dp->data->lcdsel_lit;
-   else
+   break;
+   case RK3399_VOP_BIG:
val = dp->data->lcdsel_big;
+   break;
+   default:
+   return;
+   }
  
  	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
  
@@ -231,34 +233,23 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,

  struct drm_connector_state *conn_state)
  {
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
-   struct rockchip_dp_device *dp = to_dp(encoder);
-   int ret;
  
-	/*

-* The hardware IC designed that VOP must output the RGB10 video
-* format to eDP contoller, and if eDP panel only support RGB8,
-* then eDP contoller should cut down the video data, not via VOP
-* contoller, that's why we need to hardcode the VOP output mode
-* to RGA10 here.
-*/
-
-   ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
-   if (ret < 0)
-   return 0;
-
-   switch (dp->data->chip_type) {
-   case RK3399_EDP:
+   switch (vop_get_crtc_vop_id(crtc_state->crtc)) {
+   case RK3399_VOP_LIT:
/*
 * For RK3399, VOP Lit must code the out mode to RGB888,
 * VOP Big must code the out mode to RGB10.
 */
-   if (ret)
-   s->output_mode = ROCKCHIP_OUT_MODE_P888;
-   else
-   s->output_mode = ROCKCHIP_OUT_MODE_;
+   s->output_mode = ROCKCHIP_OUT_MODE_P888;
break;
-
default:
+   /*
+* The hardware IC designed that VOP must output the RGB10 video
+* format to eDP contoller, and if eDP panel only support RGB8,
+* then eDP contoller should cut down the video data, not via 
VOP
+* contoller, that's why we need to hardcode the VOP output mode
+* to RGA10 here.
+*/
s->output_mode = ROCKCHIP_OUT_MODE_;
break;
}
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c

Re: [PATCH v3 3/4] drm/rockchip: Add support for Rockchip Soc RGB output interface

2017-10-16 Thread Mark yao


On 2017年10月09日 16:06, Sandy Huang wrote:

Some Rockchip CRTCs, like rv1108, can directly output parallel and
serial RGB data to panel or conversion chip, so we add this driver to
probe encoder and connector.

Signed-off-by: Sandy Huang 
---
Changes in v3:
   update for rgb-mode move to panel node.
Changes in v2:
   1. add error log when probe failed;
   2. update name_to_output_mode() according to sean's suggest;
   3. Fix uninitialized use of ret.

  drivers/gpu/drm/rockchip/Kconfig|   9 +
  drivers/gpu/drm/rockchip/Makefile   |   1 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |   2 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
  drivers/gpu/drm/rockchip/rockchip_rgb.c | 343 
  5 files changed, 356 insertions(+)
  create mode 100644 drivers/gpu/drm/rockchip/rockchip_rgb.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0c31f0a..85c7cc5 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -8,6 +8,7 @@ config DRM_ROCKCHIP
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_RGB if ROCKCHIP_RGB
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
@@ -65,4 +66,12 @@ config ROCKCHIP_LVDS
  Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
  support LVDS, rgb, dual LVDS output mode. say Y to enable its
  driver.
+
+config ROCKCHIP_RGB
+   bool "Rockchip RGB support"


See the fix[0] for lvds,  RGB driver using pinctl also need "depends on 
PINCTRL".

[0]https://patchwork.kernel.org/patch/9987017/

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Re: [PATCH] drm/rockchip: add PINCTRL dependency for LVDS

2017-10-12 Thread Mark yao


On 2017年10月05日 20:09, Arnd Bergmann wrote:

The new driver fails to build when CONFIG_PINCTRL is disabled:

drivers/gpu/drm/rockchip/rockchip_lvds.c: In function 
'rockchip_lvds_grf_config':
drivers/gpu/drm/rockchip/rockchip_lvds.c:229:39: error: dereferencing pointer 
to incomplete type 'struct dev_pin_info'
if (lvds->pins && !IS_ERR(lvds->pins->default_state))

This adds the respective Kconfig dependency.

Fixes: 34cc0aa25456 ("drm/rockchip: Add support for Rockchip Soc LVDS")
Signed-off-by: Arnd Bergmann 


Pushed to drm-misc-next

Thanks
Mark

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Re: [PATCH v2 2/8] drm/rockchip/dsi: add dual mipi channel support

2017-09-27 Thread Mark yao


On 2017年09月26日 15:55, Nickey Yang wrote:

This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.

Signed-off-by: Nickey Yang <nickey.y...@rock-chips.com>


Hi Nickey
Can you rebase your patches to drm-misc-next, these patches would conflict to 
current drm-misc-next branch.

And please see my comment inline.

Mark Yao


---
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 390 
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   2 +
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   3 +
  4 files changed, 292 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index c933a3a..191037c 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -39,8 +39,58 @@
  #define RK3399_DSI1_SEL_VOP_LIT   BIT(4)
  
  /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */

-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
+#define RK3399_GRF_SOC_CON22   0x6258
+#define DPHY_TX0_TURNREQUEST_SET   ((0xf << 12) << 16)
+#define DPHY_TX0_TURNREQUEST_DISABLE   (0x0 << 12)
+#define DPHY_TX0_TURNREQUEST_ENABLE(0xf << 12)
+#define DPHY_TX0_TURNDISABLE_SET   ((0xf << 8) << 16)
+#define DPHY_TX0_TURNDISABLE_DISABLE   (0x0 << 8)
+#define DPHY_TX0_TURNDISABLE_ENABLE(0xf << 8)
+#define DPHY_TX0_FORCETXSTOPMODE_SET   ((0xf << 4) << 16)
+#define DPHY_TX0_FORCETXSTOPMODE_DISABLE   (0x0 << 4)
+#define DPHY_TX0_FORCETXSTOPMODE_ENABLE(0xf << 4)
+#define DPHY_TX0_FORCETRXMODE_SET  ((0xf << 0) << 16)
+#define DPHY_TX0_FORCETRXMODE_DISABLE  0x0
+#define DPHY_TX0_FORCETRXMODE_ENABLE   0xf
+#define RK3399_GRF_DSI_MODE((DPHY_TX0_TURNREQUEST_SET | \
+DPHY_TX0_TURNDISABLE_SET | \
+DPHY_TX0_FORCETXSTOPMODE_SET | 
\
+DPHY_TX0_FORCETRXMODE_SET) | \
+(DPHY_TX0_TURNREQUEST_DISABLE 
| \
+DPHY_TX0_TURNDISABLE_DISABLE | 
\
+
DPHY_TX0_FORCETXSTOPMODE_DISABLE | \
+DPHY_TX0_FORCETRXMODE_DISABLE))
+
+
+/* disable turndisable, forcetxstopmode, forcerxmode, enable */
+#define RK3399_GRF_SOC_CON23   0x625c
+#define DPHY_TX1RX1_TURNDISABLE_SET((0xf << 12) << 16)
+#define DPHY_TX1RX1_TURNDISABLE_DISABLE(0x0 << 12)
+#define DPHY_TX1RX1_TURNDISABLE_ENABLE (0xf << 12)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_SET((0xf << 8) << 16)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_DISABLE(0x0 << 8)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_ENABLE (0xf << 8)
+#define DPHY_TX1RX1_FORCERXMODE_SET((0xf << 4) << 16)
+#define DPHY_TX1RX1_FORCERXMODE_DISABLE(0x0 << 4)
+#define DPHY_TX1RX1_FORCERXMODE_ENABLE (0xf << 4)
+#define DPHY_TX1RX1_ENABLE_SET ((0xf << 0) << 16)
+#define DPHY_TX1RX1_ENABLE_DISABLE 0x0
+#define DPHY_TX1RX1_ENABLE_ENABLE  0xf
+#define RK3399_GRF_DSI1_MODE   ((DPHY_TX1RX1_TURNDISABLE_SET | 
\
+
DPHY_TX1RX1_FORCETXSTOPMODE_SET | \
+DPHY_TX1RX1_FORCERXMODE_SET | \
+DPHY_TX1RX1_ENABLE_SET) | \
+(DPHY_TX0_TURNREQUEST_DISABLE 
| \
+DPHY_TX0_TURNDISABLE_DISABLE | 
\
+
DPHY_TX0_FORCETXSTOPMODE_DISABLE | \
+DPHY_TX0_FORCETRXMODE_DISABLE))
+#define RK3399_GRF_DSI1_ENABLE ((DPHY_TX1RX1_ENABLE_SET | \
+ DPHY_TX1RX1_ENABLE_ENABLE))
+
+#define RK3399_GRF_SOC_CON24   0x6260
+#define RK3399_TXRX_MASTERSLAVEZ   BIT(7)
+#define RK3399_TXRX_ENABLECLK  BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
  
  #define DSI_VERSION			0x00

  #define DSI_PWR_UP0x04
@@ -304,6 +354,13 @@ struct dw_mipi_dsi_plat_data {
u32 grf_switch_reg;
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
+   u32 grf_dsi1_mode;
+   u32 grf_dsi1_enable;
+

Re: [PATCH v2 1/8] drm/rockchip/dsi: correct Feedback divider setting

2017-09-27 Thread Mark yao


On 2017年09月26日 15:55, Nickey Yang wrote:

This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
3、Make the previously configured Feedback divider(LSB)
factors effective
4、Add the definition of the MIPI PHY register.

Signed-off-by: Nickey Yang 
---
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 219 ++---
  1 file changed, 146 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9a20b9d..c933a3a 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -228,7 +228,7 @@
  #define LOW_PROGRAM_EN0
  #define HIGH_PROGRAM_EN   BIT(7)
  #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0xf)
  #define PLL_LOOP_DIV_EN   BIT(5)
  #define PLL_INPUT_DIV_EN  BIT(4)
  
@@ -254,6 +254,28 @@

  #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
  #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
  
+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10

+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
+#define PLL_LPF_AND_CP_CONTROL 0x12
+#define PLL_INPUT_DIVIDER_RATIO 0x17
+#define PLL_LOOP_DIVIDER_RATIO 0x18
+#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
+#define BANDGAP_AND_BIAS_CONTROL 0x20
+#define TERMINATION_RESISTER_CONTROL 0x21
+#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
+#define HS_RX_CONTROL_OF_LANE_0 0x44
+#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
+#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
+#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
+#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
+#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
+#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
+#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
+#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
+#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
+#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
+#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
+


Can you use tab to align the macro define, it looks not friendly with space 
here.


  enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -447,53 +469,79 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
return ret;
}
  
-	dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |

-VCO_RANGE_CON_SEL(vco) |
-VCO_IN_CAP_CON_LOW |
-REF_BIAS_CUR_SEL);
-
-   dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
-   dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
-LPF_RESISTORS_20_KOHM);
-
-   dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
-
-   dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
-LOW_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
-HIGH_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
-
-   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-BIASEXTR_SEL(BIASEXTR_127_7));
-   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-BANDGAP_SEL(BANDGAP_96_10));
-
-   dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
-BIAS_BLOCK_ON | BANDGAP_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
-SETRD_MAX | TER_RESISTORS_ON);
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
-SETRD_MAX | POWER_MANAGE |
-TER_RESISTORS_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
-   dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
-   dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
-
-   dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x71,
+   dw_mipi_dsi_phy_write(dsi,

Re: [PATCH v2 5/8] drm/rockchip/dsi: Use DRM_DEV_ERROR instead of dev_err

2017-09-27 Thread Mark yao


On 2017年09月26日 15:55, Nickey Yang wrote:

Rockchip driver has been moved to using the
DRM_DEV_ERROR log messages, so change all
instances of dev_err.

Signed-off-by: Nickey Yang 


Hi Nickey

Haneen Mohammed already send similar patch, and it was applied, see following 
patch on drm-misc-next
d8dd680 drm/rockchip: Replace dev_* with DRM_DEV_*

So this patch would be skipped.

Thanks.
Mark

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Re: [PATCH 7/7] drm/rockchip: Cocci spatch "vma_pages"

2017-09-26 Thread Mark yao


On 2017年09月26日 13:12, Daniel Vetter wrote:

On Thu, Sep 21, 2017 at 09:02:22AM +0800, Mark yao wrote:

On 2017年09月21日 06:29, Thomas Meyer wrote:

Use vma_pages function on vma object instead of explicit computation.
Found by coccinelle spatch "api/vma_pages.cocci"

Signed-off-by: Thomas Meyer <tho...@m3y3r.de>
---

Looks good for me:
Acked-by: Mark Yao <mark@rock-chips.com>

Once more a maintainer who acks a patch and doesn't push it. This is
really confusing, who exactly do you expect to handle this patch for you?

Please push to drm-misc-next (also for future patches), thanks.
-Daniel


Hi Daniel
I Saw the patch title is "[PATCH 7/7]", I guessed it's one of a series of 
patches and maybe it can pushed by series.

Ok, Pushed it to drm-misc-next.




diff -u -p a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -220,7 +220,7 @@ static int rockchip_drm_gem_object_mmap_
   {
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
unsigned int i, count = obj->size >> PAGE_SHIFT;
-   unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+   unsigned long user_count = vma_pages(vma);
unsigned long uaddr = vma->vm_start;
unsigned long offset = vma->vm_pgoff;
unsigned long end = user_count + offset;

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Re: [PATCH] drm/rockchip: Fix uninitialized use of ret

2017-09-20 Thread Mark yao


On 2017年09月21日 08:13, Sean Paul wrote:

If there are no children for lvds, ret is used uninitialized. This patch
initializes ret and returns an error if the port has no children.

Fixes: 34cc0aa25456 ("drm/rockchip: Add support for Rockchip Soc LVDS")
Cc: Mark Yao <mark@rock-chips.com>
Cc: Heiko Stuebner <he...@sntech.de>
Cc: Sandy Huang <h...@rock-chips.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-rockc...@lists.infradead.org
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
  drivers/gpu/drm/rockchip/rockchip_lvds.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c 
b/drivers/gpu/drm/rockchip/rockchip_lvds.c
index c5fbe533796c..0ce6205d8d80 100644
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
@@ -346,7 +346,7 @@ static int rockchip_lvds_bind(struct device *dev, struct 
device *master,
struct drm_connector *connector;
struct device_node *remote = NULL;
struct device_node  *port, *endpoint;
-   int ret;
+   int ret = 0, child_count = 0;
const char *name;
u32 endpoint_id;
  
@@ -358,13 +358,18 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,

return -EINVAL;
}
for_each_child_of_node(port, endpoint) {
+   child_count++;
of_property_read_u32(endpoint, "reg", _id);
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, endpoint_id,
  >panel, >bridge);
if (!ret)
break;
}
-   if (ret) {
+   if (!child_count) {
+   DRM_DEV_ERROR(dev, "lvds port does not have any children\n");
+   ret  = -EINVAL;


Double space on "ret  =", except this, looks good for me.
Reviewed-by: Mark Yao <mark@rock-chips.com>


+   goto err_put_port;
+   } else if (ret) {
DRM_DEV_ERROR(dev, "failed to find panel and bridge node\n");
ret  = -EPROBE_DEFER;
goto err_put_port;



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Re: [PATCH 7/7] drm/rockchip: Cocci spatch "vma_pages"

2017-09-20 Thread Mark yao


On 2017年09月21日 06:29, Thomas Meyer wrote:

Use vma_pages function on vma object instead of explicit computation.
Found by coccinelle spatch "api/vma_pages.cocci"

Signed-off-by: Thomas Meyer <tho...@m3y3r.de>
---

Looks good for me:
Acked-by: Mark Yao <mark@rock-chips.com>



diff -u -p a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -220,7 +220,7 @@ static int rockchip_drm_gem_object_mmap_
  {
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
unsigned int i, count = obj->size >> PAGE_SHIFT;
-   unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+   unsigned long user_count = vma_pages(vma);
unsigned long uaddr = vma->vm_start;
unsigned long offset = vma->vm_pgoff;
unsigned long end = user_count + offset;

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Re: [PATCH v2] drm/rockchip: Replace dev_* with DRM_DEV_*

2017-09-17 Thread Mark yao


On 2017年09月15日 16:36, Haneen Mohammed wrote:

This patch replace instances of dev_info/err/debug with
DRM_DEV_INFO/ERROR/WARN respectively inorder to use a drm-formatted
specific log messages. Issue corrected with the help of the following
Coccinelle script:

@r@
@@

(
-dev_info
+DRM_DEV_INFO
|
-dev_err
+DRM_DEV_ERROR
|
-dev_dbg
+DRM_DEV_DEBUG
)

Signed-off-by: Haneen Mohammed 

Hi Haneen

Pushed to drm-misc-next, Thanks for the patch.

Mark

---
Changes in v2:
  - Change patch title
  - Remove redundant print messages from DRM_DEV_*

  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 26 
  drivers/gpu/drm/rockchip/cdn-dp-reg.c   |  2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 86 ++---
  drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 19 +++---
  drivers/gpu/drm/rockchip/inno_hdmi.c| 14 ++--
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 12 ++--
  drivers/gpu/drm/rockchip/rockchip_drm_fb.c  |  8 ++-
  drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c   | 18 --
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 -
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  2 +-
  10 files changed, 121 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 9606121..4d3f6ad 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -88,7 +88,7 @@ static void analogix_dp_psr_set(struct drm_encoder *encoder, 
bool enabled)
if (!analogix_dp_psr_supported(dp->dev))
return;
  
-	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

+   DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
  
  	spin_lock_irqsave(>psr_lock, flags);

if (enabled)
@@ -110,7 +110,7 @@ static void analogix_dp_psr_work(struct work_struct *work)
ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
if (ret) {
-   dev_err(dp->dev, "line flag interrupt did not arrive\n");
+   DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
return;
}
  
@@ -140,13 +140,13 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
  
  	ret = clk_prepare_enable(dp->pclk);

if (ret < 0) {
-   dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
return ret;
}
  
  	ret = rockchip_dp_pre_init(dp);

if (ret < 0) {
-   dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
clk_disable_unprepare(dp->pclk);
return ret;
}
@@ -211,17 +211,17 @@ static void rockchip_dp_drm_encoder_enable(struct 
drm_encoder *encoder)
else
val = dp->data->lcdsel_big;
  
-	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

+   DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
  
  	ret = clk_prepare_enable(dp->grfclk);

if (ret < 0) {
-   dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
return;
}
  
  	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);

if (ret != 0)
-   dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
  
  	clk_disable_unprepare(dp->grfclk);

  }
@@ -277,7 +277,7 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
  
  	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");

if (IS_ERR(dp->grf)) {
-   dev_err(dev, "failed to get rockchip,grf property\n");
+   DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
return PTR_ERR(dp->grf);
}
  
@@ -287,31 +287,31 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)

} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
return -EPROBE_DEFER;
} else if (IS_ERR(dp->grfclk)) {
-   dev_err(dev, "failed to get grf clock\n");
+   DRM_DEV_ERROR(dev, "failed to get grf clock\n");
return PTR_ERR(dp->grfclk);
}
  
  	dp->pclk = devm_clk_get(dev, "pclk");

if (IS_ERR(dp->pclk)) {
-   dev_err(dev, "failed to get pclk property\n");
+   DRM_DEV_ERROR(dev, "failed to get pclk property\n");
return PTR_ERR(dp->pclk);
}
  
  	dp->rst = devm_reset_control_get(dev, "dp");

if (IS_ERR(dp->rst)) {
-   dev_err(dev, "failed to get dp reset control\n");
+   DRM_DEV_ERROR(dev,

Re: [PATCH] gpu: drm: rockchip: Replace dev_* with DRM_DEV_*

2017-09-15 Thread Mark yao


Change the tile to:
drm/rockchip: Replace dev_* with DRM_DEV_*

Thanks.
On 2017年09月15日 14:47, Haneen Mohammed wrote:

This patch replace instances of dev_info/err/debug with
DRM_DEV_INFO/ERROR/WARN respectively inorder to use a drm-formatted
specific log messages. Issue corrected with the help of the following
Coccinelle script:

@r@
@@

(
-dev_info
+DRM_DEV_INFO
|
-dev_err
+DRM_DEV_ERROR
|
-dev_dbg
+DRM_DEV_DEBUG
)

Signed-off-by: Haneen Mohammed 
---
  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 26 +++
  drivers/gpu/drm/rockchip/cdn-dp-reg.c   |  2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 90 ++---
  drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 19 +++---
  drivers/gpu/drm/rockchip/inno_hdmi.c| 14 ++--
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 12 ++--
  drivers/gpu/drm/rockchip/rockchip_drm_fb.c  |  8 ++-
  drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c   | 18 +++--
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 -
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  2 +-
  10 files changed, 125 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 
b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 9606121..4d3f6ad 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -88,7 +88,7 @@ static void analogix_dp_psr_set(struct drm_encoder *encoder, 
bool enabled)
if (!analogix_dp_psr_supported(dp->dev))
return;
  
-	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

+   DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
  
  	spin_lock_irqsave(>psr_lock, flags);

if (enabled)
@@ -110,7 +110,7 @@ static void analogix_dp_psr_work(struct work_struct *work)
ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
if (ret) {
-   dev_err(dp->dev, "line flag interrupt did not arrive\n");
+   DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
return;
}
  
@@ -140,13 +140,13 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
  
  	ret = clk_prepare_enable(dp->pclk);

if (ret < 0) {
-   dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
return ret;
}
  
  	ret = rockchip_dp_pre_init(dp);

if (ret < 0) {
-   dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
clk_disable_unprepare(dp->pclk);
return ret;
}
@@ -211,17 +211,17 @@ static void rockchip_dp_drm_encoder_enable(struct 
drm_encoder *encoder)
else
val = dp->data->lcdsel_big;
  
-	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

+   DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
  
  	ret = clk_prepare_enable(dp->grfclk);

if (ret < 0) {
-   dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
return;
}
  
  	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);

if (ret != 0)
-   dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+   DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
  
  	clk_disable_unprepare(dp->grfclk);

  }
@@ -277,7 +277,7 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
  
  	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");

if (IS_ERR(dp->grf)) {
-   dev_err(dev, "failed to get rockchip,grf property\n");
+   DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
return PTR_ERR(dp->grf);
}
  
@@ -287,31 +287,31 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)

} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
return -EPROBE_DEFER;
} else if (IS_ERR(dp->grfclk)) {
-   dev_err(dev, "failed to get grf clock\n");
+   DRM_DEV_ERROR(dev, "failed to get grf clock\n");
return PTR_ERR(dp->grfclk);
}
  
  	dp->pclk = devm_clk_get(dev, "pclk");

if (IS_ERR(dp->pclk)) {
-   dev_err(dev, "failed to get pclk property\n");
+   DRM_DEV_ERROR(dev, "failed to get pclk property\n");
return PTR_ERR(dp->pclk);
}
  
  	dp->rst = devm_reset_control_get(dev, "dp");

if (IS_ERR(dp->rst)) {
-   dev_err(dev, "failed to get dp reset control\n");
+   DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
return PTR_ERR(dp->rst);

Re: [PATCH v8 3/3] drm/rockchip: Add support for Rockchip Soc LVDS

2017-09-08 Thread Mark yao


On 2017年09月08日 14:12, Mark yao wrote:

On 2017年09月08日 13:04, Heiko Stuebner wrote:

Am Freitag, 8. September 2017, 09:23:09 CEST schrieb Mark yao:

On 2017年09月07日 20:09, Heiko Stübner wrote:

Hi Mark,

Am Donnerstag, 7. September 2017, 18:16:29 CEST schrieb Mark yao:

Looks good for me, so:
Reviewed-by: Mark Yao <mark@rock-chips.com>

I'd like to apply these lvds patches tomorrow if there is no more doubts.

Rob had some minor comments on v7 of the dt-binding, so you may want
to give him a bit more time to Ack the hopefully updated binding.

Rob already gave a Reviewed-by on v7 dt-binding, but maybe it has some doubts 
for his Ack.

Ok, let's wait some more time.

ah, I looked at v6 and found the comments, not v7 and v7 is not in my
archive because I likely accidentially deleted it.
So Sandy just forgot to carry over the Ack/Review tag. So I guess there is
no need to wait anymore and you just need to pick up Rob's tag from v7 then.


Right, Sandy forgot to carry those tag on new patchset, I will carry those tag:
Tested-by on v5, Reviewed-by on v6 and v7

Thanks.



Pushed patches 1+3 to drm-misc-next.

Best Regards
Mark


Heiko

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Re: [PATCH v8 3/3] drm/rockchip: Add support for Rockchip Soc LVDS

2017-09-08 Thread Mark yao


On 2017年09月08日 13:04, Heiko Stuebner wrote:

Am Freitag, 8. September 2017, 09:23:09 CEST schrieb Mark yao:

On 2017年09月07日 20:09, Heiko Stübner wrote:

Hi Mark,

Am Donnerstag, 7. September 2017, 18:16:29 CEST schrieb Mark yao:

Looks good for me, so:
Reviewed-by: Mark Yao <mark@rock-chips.com>

I'd like to apply these lvds patches tomorrow if there is no more doubts.

Rob had some minor comments on v7 of the dt-binding, so you may want
to give him a bit more time to Ack the hopefully updated binding.

Rob already gave a Reviewed-by on v7 dt-binding, but maybe it has some doubts 
for his Ack.

Ok, let's wait some more time.

ah, I looked at v6 and found the comments, not v7 and v7 is not in my
archive because I likely accidentially deleted it.
So Sandy just forgot to carry over the Ack/Review tag. So I guess there is
no need to wait anymore and you just need to pick up Rob's tag from v7 then.


Right, Sandy forgot to carry those tag on new patchset, I will carry those tag:
Tested-by on v5, Reviewed-by on v6 and v7

Thanks.



Heiko

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Re: [PATCH v8 3/3] drm/rockchip: Add support for Rockchip Soc LVDS

2017-09-07 Thread Mark yao


On 2017年09月07日 20:09, Heiko Stübner wrote:

Hi Mark,

Am Donnerstag, 7. September 2017, 18:16:29 CEST schrieb Mark yao:

Looks good for me, so:
Reviewed-by: Mark Yao <mark@rock-chips.com>

I'd like to apply these lvds patches tomorrow if there is no more doubts.

Rob had some minor comments on v7 of the dt-binding, so you may want
to give him a bit more time to Ack the hopefully updated binding.


Rob already gave a Reviewed-by on v7 dt-binding, but maybe it has some doubts 
for his Ack.

Ok, let's wait some more time.


Otherwise no doubts from me, just a reminder that you should take
patches 1+3 and I'll pick patch 2 with the dts changes after that.


Thanks
Heiko






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Re: [PATCH v8 3/3] drm/rockchip: Add support for Rockchip Soc LVDS

2017-09-07 Thread Mark yao


Hi Sandy

Looks good for me, so:
Reviewed-by: Mark Yao <mark@rock-chips.com>

I'd like to apply these lvds patches tomorrow if there is no more doubts.

Best Regards
Mark
On 2017年09月02日 19:28, Sandy Huang wrote:

This adds support for Rockchip soc lvds found on rk3288
Based on the patches from Mark yao and Heiko Stuebner.

Signed-off-by: Mark Yao <mark@rock-chips.com>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Sandy Huang <h...@rock-chips.com>
---
Change the Signed-off order

  drivers/gpu/drm/rockchip/Kconfig|   8 +
  drivers/gpu/drm/rockchip/Makefile   |   1 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |   2 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
  drivers/gpu/drm/rockchip/rockchip_lvds.c| 582 
  drivers/gpu/drm/rockchip/rockchip_lvds.h| 114 ++
  6 files changed, 708 insertions(+)
  create mode 100644 drivers/gpu/drm/rockchip/rockchip_lvds.c
  create mode 100644 drivers/gpu/drm/rockchip/rockchip_lvds.h

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index dcc539b..0c31f0a 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -57,4 +57,12 @@ config ROCKCHIP_INNO_HDMI
  for the Innosilicon HDMI driver. If you want to enable
  HDMI on RK3036 based SoC, you should select this option.
  
+config ROCKCHIP_LVDS

+   bool "Rockchip LVDS support"
+   depends on DRM_ROCKCHIP
+   help
+ Choose this option to enable support for Rockchip LVDS controllers.
+ Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
+ support LVDS, rgb, dual LVDS output mode. say Y to enable its
+ driver.
  endif
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index fa8dc9d..a881d2c 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -12,5 +12,6 @@ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o 
cdn-dp-reg.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
  rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
  
  obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index c41f48a..082c251 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -445,6 +445,8 @@ static int __init rockchip_drm_init(void)
  
  	num_rockchip_sub_drivers = 0;

ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
+   ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
+   CONFIG_ROCKCHIP_LVDS);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
CONFIG_ROCKCHIP_ANALOGIX_DP);
ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index c7e96b8..498dfbc 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -69,5 +69,6 @@ extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
  extern struct platform_driver dw_mipi_dsi_driver;
  extern struct platform_driver inno_hdmi_driver;
  extern struct platform_driver rockchip_dp_driver;
+extern struct platform_driver rockchip_lvds_driver;
  extern struct platform_driver vop_platform_driver;
  #endif /* _ROCKCHIP_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c 
b/drivers/gpu/drm/rockchip/rockchip_lvds.c
new file mode 100644
index 000..86d9a8c
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
@@ -0,0 +1,582 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author:
+ *  Mark Yao <mark@rock-chips.com>
+ *  Sandy Huang <h...@rock-chips.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+#include "rockchip_lvds.h"
+
+#define DISPLAY_OUTPUT_RGB 0
+#define DISPLAY_OUTPUT_LVDS1
+#define DISPLAY_OUTPUT_DUAL_LVDS   2
+
+#define connector_to_lvds(c) \
+   c

Re: [PATCH v7 1/3] dt-bindings: display: Add Document for Rockchip Soc LVDS

2017-08-29 Thread Mark yao


On 2017年08月23日 14:26, Sandy Huang wrote:

This patch add Document for Rockchip Soc RK3288 LVDS,
This based on the patches from Mark yao and Heiko Stuebner.

Signed-off-by: Sandy Huang <h...@rock-chips.com>
Signed-off-by: Mark yao <mark@rock-chips.com>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---

Looks good for me:

Reviewed-by: Mark Yao <mark@rock-chips.com>


Changes according to Rob Herring's review.

  .../bindings/display/rockchip/rockchip-lvds.txt| 99 ++
  1 file changed, 99 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
new file mode 100644
index 000..da6939e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
@@ -0,0 +1,99 @@
+Rockchip RK3288 LVDS interface
+
+
+Required properties:
+- compatible: matching the soc type, one of
+   - "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+   of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+   clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- avdd1v0-supply: regulator phandle for 1.0V analog power
+- avdd1v8-supply: regulator phandle for 1.8V analog power
+- avdd3v3-supply: regulator phandle for 3.3V analog power
+
+- rockchip,grf: phandle to the general register files syscon
+- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output 
interface
+
+Optional properties:
+- pinctrl-names: must contain a "lcdc" entry.
+- pinctrl-0: pin control group to be used for this controller.
+
+Required nodes:
+
+The lvds has two video ports as described by
+   Documentation/devicetree/bindings/media/video-interfaces.txt
+Their connections are modeled using the OF graph bindings specified in
+   Documentation/devicetree/bindings/graph.txt.
+
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
+
+the lvds panel described by
+   Documentation/devicetree/bindings/display/panel/simple-panel.txt
+
+Panel required properties:
+- ports for remote LVDS output
+
+Panel optional properties:
+- data-mapping: should be "vesa-24","jeida-24" or "jeida-18".
+This describes decribed by:
+   Documentation/devicetree/bindings/display/panel/panel-lvds.txt
+
+Example:
+
+lvds_panel: lvds-panel {
+   compatible = "auo,b101ean01";
+   enable-gpios = < 21 GPIO_ACTIVE_HIGH>;
+   data-mapping = "jeida-24";
+
+   ports {
+   panel_in_lvds: endpoint {
+   remote-endpoint = <_out_panel>;
+   };
+   };
+};
+
+For Rockchip RK3288:
+
+   lvds: lvds@ff96c000 {
+   compatible = "rockchip,rk3288-lvds";
+   rockchip,grf = <>;
+   reg = <0xff96c000 0x4000>;
+   clocks = < PCLK_LVDS_PHY>;
+   clock-names = "pclk_lvds";
+   pinctrl-names = "lcdc";
+   pinctrl-0 = <_ctl>;
+   avdd1v0-supply = <_lcd>;
+   avdd1v8-supply = <_lcd>;
+   avdd3v3-supply = <_33>;
+   rockchip,output = "rgb";
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   lvds_in: port@0 {
+   reg = <0>;
+
+   lvds_in_vopb: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_lvds>;
+   };
+   lvds_in_vopl: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = <_out_lvds>;
+   };
+   };
+
+   lvds_out: port@1 {
+   reg = <1>;
+
+   lvds_out_panel: endpoint {
+   remote-endpoint = <_in_lvds>;
+   };
+   };
+   };
+   };



--
Ｍark Yao


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Re: [PATCH v4 3/3] drm/rockchip: Add support for Rockchip Soc LVDS

2017-08-14 Thread Mark yao


Hi Sandy

On 2017年08月15日 08:56, Sandy Huang wrote:

This adds support for Rockchip soc lvds found on rk3288
Based on the patches from Mark yao and Heiko Stuebner

Signed-off-by: Sandy Huang <h...@rock-chips.com>
Signed-off-by: Mark yao <mark@rock-chips.com>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
  drivers/gpu/drm/rockchip/Kconfig|   9 +
  drivers/gpu/drm/rockchip/Makefile   |   1 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |   2 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
  drivers/gpu/drm/rockchip/rockchip_lvds.c| 652 
  drivers/gpu/drm/rockchip/rockchip_lvds.h| 109 +
  6 files changed, 774 insertions(+)
  create mode 100644 drivers/gpu/drm/rockchip/rockchip_lvds.c
  create mode 100644 drivers/gpu/drm/rockchip/rockchip_lvds.h

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 50c41c0..80672f4 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -59,3 +59,12 @@ config ROCKCHIP_INNO_HDMI
  This selects support for Rockchip SoC specific extensions
  for the Innosilicon HDMI driver. If you want to enable
  HDMI on RK3036 based SoC, you should select this option.
+
+config ROCKCHIP_LVDS
+   bool "Rockchip LVDS support"
+   depends on DRM_ROCKCHIP
+   help
+ Choose this option to enable support for Rockchip LVDS controllers.
+ Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
+ support LVDS, rgb, dual LVDS output mode. say Y to enable its
+ driver.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index fa8dc9d..a881d2c 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -12,5 +12,6 @@ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o 
cdn-dp-reg.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
  rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
  
  obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index c41f48a..082c251 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -445,6 +445,8 @@ static int __init rockchip_drm_init(void)
  
  	num_rockchip_sub_drivers = 0;

ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
+   ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
+   CONFIG_ROCKCHIP_LVDS);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
CONFIG_ROCKCHIP_ANALOGIX_DP);
ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index c7e96b8..498dfbc 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -69,5 +69,6 @@ extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
  extern struct platform_driver dw_mipi_dsi_driver;
  extern struct platform_driver inno_hdmi_driver;
  extern struct platform_driver rockchip_dp_driver;
+extern struct platform_driver rockchip_lvds_driver;
  extern struct platform_driver vop_platform_driver;
  #endif /* _ROCKCHIP_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c 
b/drivers/gpu/drm/rockchip/rockchip_lvds.c
new file mode 100644
index 000..532f2b6
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
@@ -0,0 +1,652 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author:
+ *  Mark Yao <mark@rock-chips.com>
+ *  Sandy huang <h...@rock-chips.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../drm_crtc_internal.h"
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+#include "rockchip_lvds.h"
+
+#define DISPLAY_OUTPUT_RGB 0
+#define DISPLAY_OUTPUT_LVDS1
+#define DISPLAY_OUTPUT_DUAL_LVDS   2
+
+#define connector_to_lvds(c) \
+   container_of(c, struct rockchip_lvds, connector)
+
+#define encoder_to_lvds(c) \
+   container_of(c, stru

Re: [PATCH v2] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY

2017-08-08 Thread Mark yao


On 2017年07月07日 23:47, Jose Abreu wrote:

Hi Archit,



Ping, Any update for this patch? Can it be landed?

This patch actually needed for rk3399 hdmi support

Best Regards
Mark


On 23-06-2017 10:36, Jose Abreu wrote:

Currently HDMI 2.0 PHYs do not have a default configuration function.

As *some* of the HDMI 2.0 PHYs have the same register layout as the 3D
PHYs we can provide the same default configuration function for both
and still let user overwrite this with custom configuration function
if needed.

If, for some reason, the PHY is custom or has a register different
register layout then custom configuration function *must* be provided
in order for the system to work correctly. As we prefer the pdata
provided configuration function over the internal one this change
will not make any impact in custom platforms.

This patch is based on today's drm-misc-next branch.

Signed-off-by: Jose Abreu <joab...@synopsys.com>
Tested-by: Mark Yao <mark@rock-chips.com>

This is needed for RK3399 support. Can you please apply it?

Best regards,
Jose Miguel Abreu


Cc: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
Cc: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: Andrzej Hajda <a.ha...@samsung.com>
Cc: Mark Yao <mark@rock-chips.com>
Cc: Carlos Palminha <palmi...@synopsys.com>
Cc: Heiko Stübner <he...@sntech.de>

Changes in v2:
- Rebased and refrased commit message
---

Hi All,

There as been a little confusion about dw-hdmi phys so I will expand a little 
bit
here so that I can base my decision about this patch and why does it only works
in some platforms.

First, if you read dw-hdmi.c code, you will see that there is an identification
register for the phy type being used. Unfortunatelly, this only states the phy 
type
and not the phy version.

Second, we have many HDMI 2.0 phys (so, same phy type: 0xf3) but, as you may 
have guessed,
HW team decided to change regbank between some versions.

Third and last, each phy in a SoC has unique characteristics, so each phy 
(event if
they are the same version) will have different PLL configuration parameters.

Given all this I managed to conclude that Mark's phy is still an HDMI 2.0 phy 
but with
the same register layout as previous 3D PHY's. I found at least 2 phys with the 
same
register layout and only 1 phy which has a different layout, so I think 
majority wins
here and we should let the default configuration function for HDMI 2.0 phys be 
the same
one as the 3D.

Short story: There is no way to correctly identify, at runtime, the phy version 
being
used by the controller so we can't provide a default configuration function. We 
can,
however assume that most of the HDMI 2.0 phys will have the 3D layout BUT each 
developer
must confirm that the layout in its SoC is the expected one and if not, provide 
a custom
configuration function.

Best regards,
Jose Miguel Abreu

  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ead1124..10c8d8c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2170,6 +2170,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
.name = "DWC HDMI 2.0 TX PHY",
.gen = 2,
.has_svsret = true,
+   .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
}, {
.type = DW_HDMI_PHY_VENDOR_PHY,
.name = "Vendor PHY",






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[PATCH v1.1] drm/rockchip: fix race with kms hotplug and fbdev

2017-08-01 Thread Mark Yao

According to the kerneldoc[0], should do fbdev setup before calling
drm_kms_helper_poll_init(), otherwise, Kms hotplug event may race
into fbdev helper initial, and fb_helper->dev may be NULL pointer,
that would cause the bug:
[0.735411] [0200] *pgd=f6ffe003, *pud=f6ffe003, 
*pmd=
[0.736156] Internal error: Oops: 9605 [#1] PREEMPT SMP
[0.736648] Modules linked in:
[0.736930] CPU: 2 PID: 20 Comm: kworker/2:0 Not tainted 4.4.41 #20
[0.737480] Hardware name: Rockchip RK3399 Board rev2 (BOX) (DT)
[0.738020] Workqueue: events cdn_dp_pd_event_work
[0.738447] task: ffc0f21f3100 ti: ffc0f2218000 task.ti: 
ffc0f2218000
[0.739109] PC is at mutex_lock+0x14/0x44
[0.739469] LR is at drm_fb_helper_hotplug_event+0x30/0x114
[0.756253] [] mutex_lock+0x14/0x44
[0.756260] [] drm_fb_helper_hotplug_event+0x30/0x114
[0.756271] [] rockchip_drm_output_poll_changed+0x18/0x20
[0.756280] [] drm_kms_helper_hotplug_event+0x28/0x34
[0.756286] [] cdn_dp_pd_event_work+0x394/0x3c4
[0.756295] [] process_one_work+0x218/0x3e0
[0.756302] [] worker_thread+0x2e8/0x404
[0.756308] [] kthread+0xe8/0xf0
[0.756316] [] ret_from_fork+0x10/0x40

[0]: https://01.org/linuxgraphics/gfx-docs/drm/gpu/drm-kms-helpers.html

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v1.1:
- According to the kerneldoc, fix the race bug in generic way.

 drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 848edcf..c41f48a 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -161,22 +161,21 @@ static int rockchip_drm_bind(struct device *dev)
 */
drm_dev->irq_enabled = true;
 
-   /* init kms poll for handling hpd */
-   drm_kms_helper_poll_init(drm_dev);
-
ret = rockchip_drm_fbdev_init(drm_dev);
if (ret)
-   goto err_kms_helper_poll_fini;
+   goto err_unbind_all;
+
+   /* init kms poll for handling hpd */
+   drm_kms_helper_poll_init(drm_dev);
 
ret = drm_dev_register(drm_dev, 0);
if (ret)
-   goto err_fbdev_fini;
+   goto err_kms_helper_poll_fini;
 
return 0;
-err_fbdev_fini:
-   rockchip_drm_fbdev_fini(drm_dev);
 err_kms_helper_poll_fini:
drm_kms_helper_poll_fini(drm_dev);
+   rockchip_drm_fbdev_fini(drm_dev);
 err_unbind_all:
component_unbind_all(dev, drm_dev);
 err_mode_config_cleanup:
-- 
1.9.1


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Re: [PATCH 6/6] drm/rockchip: fix race with kms hotplug and fbdev

2017-07-31 Thread Mark yao


On 2017年07月31日 20:28, Daniel Vetter wrote:

On Mon, Jul 31, 2017 at 1:57 PM, Emil Velikov <emil.l.veli...@gmail.com> wrote:

On 31 July 2017 at 10:50, Mark Yao <mark@rock-chips.com> wrote:

Since fb_helper is not a pointer on rockchip_drm_private, it's no
need to check pointer.

Kms hotplug event may race into fbdev helper initial, and fb_helper->dev
may be NULL pointer, that would cause the bug:

[0.735411] [0200] *pgd=f6ffe003, *pud=f6ffe003, 
*pmd=
[0.736156] Internal error: Oops: 9605 [#1] PREEMPT SMP
[0.736648] Modules linked in:
[0.736930] CPU: 2 PID: 20 Comm: kworker/2:0 Not tainted 4.4.41 #20
[0.737480] Hardware name: Rockchip RK3399 Board rev2 (BOX) (DT)
[0.738020] Workqueue: events cdn_dp_pd_event_work
[0.738447] task: ffc0f21f3100 ti: ffc0f2218000 task.ti: 
ffc0f2218000
[0.739109] PC is at mutex_lock+0x14/0x44
[0.739469] LR is at drm_fb_helper_hotplug_event+0x30/0x114
[0.756253] [] mutex_lock+0x14/0x44
[0.756260] [] drm_fb_helper_hotplug_event+0x30/0x114
[0.756271] [] rockchip_drm_output_poll_changed+0x18/0x20
[0.756280] [] drm_kms_helper_hotplug_event+0x28/0x34
[0.756286] [] cdn_dp_pd_event_work+0x394/0x3c4
[0.756295] [] process_one_work+0x218/0x3e0
[0.756302] [] worker_thread+0x2e8/0x404
[0.756308] [] kthread+0xe8/0xf0
[0.756316] [] ret_from_fork+0x10/0x40

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
index 81f9548..e6bd0f4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
@@ -170,7 +170,7 @@ static void rockchip_drm_output_poll_changed(struct 
drm_device *dev)
 struct rockchip_drm_private *private = dev->dev_private;
 struct drm_fb_helper *fb_helper = >fbdev_helper;

-   if (fb_helper)
+   if (fb_helper->dev)
 drm_fb_helper_hotplug_event(fb_helper);

Food for thought:

Quick grep shows that no other drivers have such a ->dev check. Does
this mean that either the issue is rockchip specific?
If not, one could look into resolving the problem directly in drm core.

Or at least update the other users, so they don't stumble upon the problem?

The fbdev helpers support already handling hotplug events before you
have finalized the fbdev setup. Please read the kerneldoc for the
various fbdev functions, they explain what you should be doing. This
hack here should indeed not be needed.
-Daniel


Hi Daniel

Right, the doc[0] already detail this:
It is possible, though perhaps somewhat tricky, to implement race-free 
hotplug detection using
the fbdev helpers. The drm_fb_helper_prepare() helper must be called first 
to initialize the
minimum required to make hotplug detection work.Drivers also need to make 
sure to properly
set up the drm_mode_config.funcs member. After calling 
drm_kms_helper_poll_init() it is safe to
enable interrupts and start processing hotplug events.

The problem is drm/rockchip do the wrong initial, call drm_kms_helper_poll_init 
before fbdev setup.

will fix it at next version.

[0]: 
https://01.org/linuxgraphics/gfx-docs/drm/gpu/drm-kms-helpers.html#fbdev-helper-functions-reference

Best regards.

--
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[PATCH 2/6] drm/rockchip: vop: fix iommu page fault when resume

2017-07-31 Thread Mark Yao

Iommu would get page fault with following path:
   vop_disable:
  1, disable all windows and set vop config done
  2, vop enter to standy, all windows not works, but their registers
 are not clean, when you read window's enable bit, may found the
 window is enable.

   vop_enable:
  1, memcpy(vop->regsbak, vop->regs, len)
 save current vop registers to vop->regsbak, then you can found
 window is enable on regsbak.
  2, VOP_WIN_SET(vop, win, gate, 1);
 force enable window gate, but gate and enable are on same
 hardware register, then window enable bit rewrite to vop hardware.
  3, vop power on, and vop might try to scan destroyed buffer,
 then iommu get page fault.

Move windows disable after vop regsbak restore, then vop regsbak mechanism
would keep tracing the modify, everything would be safe.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33 +
 1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 0bfd563..0b5fd75 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -495,7 +495,7 @@ static void vop_line_flag_irq_disable(struct vop *vop)
 static int vop_enable(struct drm_crtc *crtc)
 {
struct vop *vop = to_vop(crtc);
-   int ret;
+   int ret, i;
 
ret = pm_runtime_get_sync(vop->dev);
if (ret < 0) {
@@ -528,6 +528,20 @@ static int vop_enable(struct drm_crtc *crtc)
}
 
memcpy(vop->regs, vop->regsbak, vop->len);
+   /*
+* We need to make sure that all windows are disabled before we
+* enable the crtc. Otherwise we might try to scan from a destroyed
+* buffer later.
+*/
+   for (i = 0; i < vop->data->win_size; i++) {
+   struct vop_win *vop_win = >win[i];
+   const struct vop_win_data *win = vop_win->data;
+
+   spin_lock(>reg_lock);
+   VOP_WIN_SET(vop, win, enable, 0);
+   spin_unlock(>reg_lock);
+   }
+
vop_cfg_done(vop);
 
/*
@@ -561,28 +575,11 @@ static int vop_enable(struct drm_crtc *crtc)
 static void vop_crtc_disable(struct drm_crtc *crtc)
 {
struct vop *vop = to_vop(crtc);
-   int i;
 
WARN_ON(vop->event);
 
rockchip_drm_psr_deactivate(>crtc);
 
-   /*
-* We need to make sure that all windows are disabled before we
-* disable that crtc. Otherwise we might try to scan from a destroyed
-* buffer later.
-*/
-   for (i = 0; i < vop->data->win_size; i++) {
-   struct vop_win *vop_win = >win[i];
-   const struct vop_win_data *win = vop_win->data;
-
-   spin_lock(>reg_lock);
-   VOP_WIN_SET(vop, win, enable, 0);
-   spin_unlock(>reg_lock);
-   }
-
-   vop_cfg_done(vop);
-
drm_crtc_vblank_off(crtc);
 
/*
-- 
1.9.1


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[PATCH 4/6] drm/rockchip: vop: round_up pitches to word align

2017-07-31 Thread Mark Yao

VOP pitch register is word align, need align to word.

VOP_WIN0_VIR:
  bit[31:16] win0_vir_stride_uv
Number of words of Win0 uv Virtual width
  bit[15:0] win0_vir_width
Number of words of Win0 yrgb Virtual width
ARGB888 : win0_vir_width
RGB888 : (win0_vir_width*3/4) + (win0_vir_width%3)
RGB565 : ceil(win0_vir_width/2)
YUV : ceil(win0_vir_width/4)

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 0b5fd75..fa0d9f7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -756,7 +756,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
spin_lock(>reg_lock);
 
VOP_WIN_SET(vop, win, format, format);
-   VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
+   VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
if (is_yuv_support(fb->format->format)) {
int hsub = 
drm_format_horz_chroma_subsampling(fb->format->format);
@@ -770,7 +770,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
-   VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
+   VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
VOP_WIN_SET(vop, win, uv_mst, dma_addr);
}
 
-- 
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[PATCH 0/6] drm/rockchip: Some fixes

2017-07-31 Thread Mark Yao

Here are some fixes port from rockchip_linux project[0],

Tested on rk3399 and rk3288 board.

[0]: https://github.com/rockchip-linux/kernel

Mark Yao (6):
  drm/rockchip: vop: no need wait vblank on crtc enable
  drm/rockchip: vop: fix iommu page fault when resume
  drm/rockchip: vop: fix NV12 video display error
  drm/rockchip: vop: round_up pitches to word align
  drm/rockchip: vop: report error when check resource error
  drm/rockchip: fix race with kms hotplug and fbdev

 drivers/gpu/drm/rockchip/rockchip_drm_fb.c  |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 77 -
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  3 ++
 3 files changed, 24 insertions(+), 58 deletions(-)

-- 
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[PATCH 6/6] drm/rockchip: fix race with kms hotplug and fbdev

2017-07-31 Thread Mark Yao

Since fb_helper is not a pointer on rockchip_drm_private, it's no
need to check pointer.

Kms hotplug event may race into fbdev helper initial, and fb_helper->dev
may be NULL pointer, that would cause the bug:

[0.735411] [0200] *pgd=f6ffe003, *pud=f6ffe003, 
*pmd=
[0.736156] Internal error: Oops: 9605 [#1] PREEMPT SMP
[0.736648] Modules linked in:
[0.736930] CPU: 2 PID: 20 Comm: kworker/2:0 Not tainted 4.4.41 #20
[0.737480] Hardware name: Rockchip RK3399 Board rev2 (BOX) (DT)
[0.738020] Workqueue: events cdn_dp_pd_event_work
[0.738447] task: ffc0f21f3100 ti: ffc0f2218000 task.ti: 
ffc0f2218000
[0.739109] PC is at mutex_lock+0x14/0x44
[0.739469] LR is at drm_fb_helper_hotplug_event+0x30/0x114
[0.756253] [] mutex_lock+0x14/0x44
[0.756260] [] drm_fb_helper_hotplug_event+0x30/0x114
[0.756271] [] rockchip_drm_output_poll_changed+0x18/0x20
[0.756280] [] drm_kms_helper_hotplug_event+0x28/0x34
[0.756286] [] cdn_dp_pd_event_work+0x394/0x3c4
[0.756295] [] process_one_work+0x218/0x3e0
[0.756302] [] worker_thread+0x2e8/0x404
[0.756308] [] kthread+0xe8/0xf0
[0.756316] [] ret_from_fork+0x10/0x40

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
index 81f9548..e6bd0f4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
@@ -170,7 +170,7 @@ static void rockchip_drm_output_poll_changed(struct 
drm_device *dev)
struct rockchip_drm_private *private = dev->dev_private;
struct drm_fb_helper *fb_helper = >fbdev_helper;
 
-   if (fb_helper)
+   if (fb_helper->dev)
drm_fb_helper_hotplug_event(fb_helper);
 }
 
-- 
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[PATCH 3/6] drm/rockchip: vop: fix NV12 video display error

2017-07-31 Thread Mark Yao

fixup the scale calculation formula on the case
src_height == (dst_height/2).

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index af1091f..56bbd2e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -299,6 +299,9 @@ static inline uint16_t scl_get_bili_dn_vskip(int src_h, int 
dst_h,
 
act_height = (src_h + vskiplines - 1) / vskiplines;
 
+   if (act_height == dst_h)
+   return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
+
return GET_SCL_FT_BILI_DN(act_height, dst_h);
 }
 
-- 
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[PATCH 5/6] drm/rockchip: vop: report error when check resource error

2017-07-31 Thread Mark Yao

The user would be confused while facing a error commit without
any error report.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index fa0d9f7..999c2e0 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -674,8 +674,10 @@ static int vop_plane_atomic_check(struct drm_plane *plane,
 * Src.x1 can be odd when do clip, but yuv plane start point
 * need align with 2 pixel.
 */
-   if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
+   if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) {
+   DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
return -EINVAL;
+   }
 
return 0;
 }
-- 
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[PATCH 1/6] drm/rockchip: vop: no need wait vblank on crtc enable

2017-07-31 Thread Mark Yao

Since atomic framework, crtc enable and disable are in pairs,
no need to wait vblank.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 -
 1 file changed, 36 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 1d42049..0bfd563 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -893,42 +893,6 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
return;
}
 
-   /*
-* If dclk rate is zero, mean that scanout is stop,
-* we don't need wait any more.
-*/
-   if (clk_get_rate(vop->dclk)) {
-   /*
-* Rk3288 vop timing register is immediately, when configure
-* display timing on display time, may cause tearing.
-*
-* Vop standby will take effect at end of current frame,
-* if dsp hold valid irq happen, it means standby complete.
-*
-* mode set:
-*standby and wait complete --> |
-*  | display time
-*  |
-*  |---> dsp hold irq
-* configure display timing --> |
-* standby exit |
-*  | new frame start.
-*/
-
-   reinit_completion(>dsp_hold_completion);
-   vop_dsp_hold_valid_irq_enable(vop);
-
-   spin_lock(>reg_lock);
-
-   VOP_REG_SET(vop, common, standby, 1);
-
-   spin_unlock(>reg_lock);
-
-   wait_for_completion(>dsp_hold_completion);
-
-   vop_dsp_hold_valid_irq_disable(vop);
-   }
-
pin_pol = BIT(DCLK_INVERT);
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
   BIT(HSYNC_POSITIVE) : 0;
-- 
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Re: [PATCH v6 0/7] drm/rockchip: add all full framework vop support

2017-07-30 Thread Mark yao


Hi

Pushed to drm-misc-next.

Thanks Sean Paul, Jeffy Chen's review, Heiko's test and Rob's ack.

Best regards.

On 2017年07月26日 14:18, Mark Yao wrote:

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
   3.1   rk3288
   3.2   rk3368
   3.4   rk3366
   3.5   rk3399 big
   3.6   rk3399 lit
   3.7   rk3228
   3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.13-rc1.

And other chips tested on rockchip kernel 4.4:

https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v6:
- fix some patches complie error
- fix rk3036 display blank

Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- Explain more on patch commit message
- move write_relaxed flags to vop registers
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

Mark Yao (7):
   drm/rockchip: vop: initialize registers directly
   drm/rockchip: vop: move write_relaxed flags to vop register
   drm/rockchip: vop: move line_flag_num to interrupt registers
   drm/rockchip: vop: group vop registers
   drm/rockchip: vop: add a series of vop support
   dt-bindings: display: rockchip: fill Documents for vop series
   drm/rockchip: vop: rk3328: fix overlay abnormal

  .../bindings/display/rockchip/rockchip-vop.txt |   4 +
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 375 ++---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
  5 files changed, 1075 insertions(+), 399 deletions(-)




--
Ｍark Yao


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[PATCH v6.1 4/7] drm/rockchip: vop: group vop registers

2017-07-28 Thread Mark Yao

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Jeffy Chen <jeffy.c...@rock-chips.com>
---
Changes in v6.1
- fix Null pointer crash on vop_reg_set

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 101 -
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  60 ---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112 +++-
 3 files changed, 146 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index fd47da5..39912f2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,30 +42,19 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define REG_SET(x, base, reg, v) \
-   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
-  v, reg.write_mask, reg.relaxed)
-#define REG_SET_MASK(x, base, reg, mask, v) \
-   vop_mask_write(x, base + reg.offset, \
-  mask, reg.shift, v, reg.write_mask, reg.relaxed)
-
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v)
+   vop_reg_set(vop, >phy->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v)
+   vop_reg_set(vop, >phy->scl->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v)
-#define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v)
-
-#define VOP_INTR_GET(vop, name) \
-   vop_read_reg(vop, 0, >data->ctrl->name)
-
-#define VOP_INTR_SET(vop, name, v) \
-   REG_SET(vop, 0, vop->data->intr->name, v)
+   vop_reg_set(vop, >phy->scl->ext->name, \
+   win->base, ~0, v, #name)
 
 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
+   vop_reg_set(vop, >data->intr->name, 0, mask, v, #name)
+
+#define VOP_REG_SET(vop, group, name, v) \
+   vop_reg_set(vop, >data->group->name, 0, ~0, v, #name)
 
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
@@ -82,7 +71,7 @@
vop_get_intr_type(vop, >data->intr->name, type)
 
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
@@ -164,14 +153,22 @@ static inline uint32_t vop_read_reg(struct vop *vop, 
uint32_t base,
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 }
 
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
 {
-   if (!mask)
+   int offset, mask, shift;
+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }
+
+   offset = reg->offset + _offset;
+   mask = reg->mask & _mask;
+   shift = reg->shift;
 
-   if (write_mask) {
+   if (reg->write_mask) {
v = ((v << shift) & 0x) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
@@ -180,7 +177,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t 
offset,
vop->regsbak[offset >> 2] = v;
}
 
-   if (relaxed)
+   if (reg->relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
@@ -202,7 +199,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
 
 static inline void vop_cfg_done(struct vop *vop)
 {
-   VOP_CTRL_SET(vop, cfg_done, 1);
+   VOP_REG_SET(vop, common, cfg_done, 1);
 }
 
 static bool has_rb_swapped(uint32_t format)
@@ -540,7 +537,7 @@ static int vop_enable(struct drm_crtc *crtc)
 
spin_lock(>reg_lock);
 
-   VOP_CTRL_SET(vop, standby, 0);
+   VOP_REG_SET(vop, common, standby, 1);
 
spin_unlo

Re: [PATCH v6 4/7] drm/rockchip: vop: group vop registers

2017-07-27 Thread Mark yao


Hi Heiko

On 2017年07月28日 09:02, Mark yao wrote:

Hi Heiko

Thanks for the test.

On 2017年07月27日 18:10, Heiko Stübner wrote:

Am Donnerstag, 27. Juli 2017, 11:51:06 CEST schrieb Heiko Stübner:

Hi Mark,

Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---

  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99
  
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  60 ---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112

+++- 3 files changed, 144 insertions(+), 127
deletions(-)

This breaks display support on both rk3036 and rk3288 and I end up
with a null pointer dereference in

[   10.640297] Unable to handle kernel NULL pointer dereference at virtual
address  [   10.654430] pgd = c0204000
[   10.657452] [] *pgd=
[   10.661473] Internal error: Oops: 5 [#1] SMP ARM
[   10.35] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp
snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip
clk_rk808 spi_rockchip [   10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not
tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [   10.692430] Hardware name:
Rockchip (Device Tree)
[   10.697692] Workqueue: events deferred_probe_work_func
[   10.702152] Linux video capture interface: v2.00
[   10.708590] task: ee38c800 task.stack: ed2e6000
[   10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm]
[   10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm]

The obvious reason for that is


@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop,
uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) &
reg->mask; }

-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
-  uint32_t mask, uint32_t shift, uint32_t v,
-  bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+uint32_t _offset, uint32_t _mask, uint32_t v,
+const char *reg_name)
  {
-if (!mask)
+int offset = reg->offset + _offset;
+int mask = reg->mask & _mask;
+int shift = reg->shift;


Does the crash is that using reg->offset/mask/shift before !reg checking?


I reproduce this cause, from objdump, it crash on "int mask = reg->mask & _mask; 
"
Seems difference gcc has difference behavior, my aarch64 gcc maybe optimize it,
only access when the value be used. I think that is the reason why rk3399 works 
on my test.

I will fix it at next version.




+
+if (!reg || !reg->mask) {
+dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
  return;
+}

where the check for !reg happens after it got already dereferenced.
But even with that fixed I end up with

on rk3288:
[7.254823] rockchip-vop ff93.vop: Warning: not support global_regdone_en
[7.262847] rockchip-vop ff93.vop: Warning: not support gate
[7.269580] rockchip-vop ff93.vop: Warning: not support gate
[7.302765] rockchip-vop ff94.vop: Warning: not support global_regdone_en
[7.310758] rockchip-vop ff94.vop: Warning: not support gate
[7.317475] rockchip-vop ff94.vop: Warning: not support gate
[7.425724] rockchip-vop ff93.vop: Warning: not support edp_pin_pol
[7.526298] rockchip-vop ff94.vop: Warning: not support hdmi_pin_pol


Rk3288 does not support independent pin_pol settings, all output interfaces 
share the pin_pol register,
So not support hdmi_pin_pol here is correct.

hdmi pin pol would be set by following register:
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),



on rk3036:
[   12.389138] rockchip-vop 10118000.vop: Warning: not support global_regdone_en
[   12.397324] rockchip-vop 10118000.vop: Warning: not support gate
[   12.404165] rockchip-vop 10118000.vop: Warning: not support gate
[   13.747361] rockchip-vop 10118000.vop: Warning: not support hdmi_pin_pol
[   13.747371] rockchip-vop 10118000.vop: Warning: not support hdmi_en
[   13.747379] rockchip-vop 10118000.vop: Warning: not support hpost_st_end
[   13.747385] rockchip-vop 10118000.vop: Warning: not support vpost_st_end
[   13.747461] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
[   13.767098] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
[   13.786060] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl

While reqdone and friends are obviously features of newer vops, at least
the hdmi pin-pol is available on both these socs.

With this patch applied (and null-ptr fixed) I end up without hdmi output
on both socs.


Hmmm, I am confused, from code review, I didn't see what will cause hdmi not 
work on rk3036 and rk3288,

Give me some time, I try to bringup my popmetal rk328

Re: [PATCH v6 4/7] drm/rockchip: vop: group vop registers

2017-07-27 Thread Mark yao


Hi Heiko

Thanks for the test.

On 2017年07月27日 18:10, Heiko Stübner wrote:

Am Donnerstag, 27. Juli 2017, 11:51:06 CEST schrieb Heiko Stübner:

Hi Mark,

Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---

  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99
  
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  60 ---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112

+++- 3 files changed, 144 insertions(+), 127
deletions(-)

This breaks display support on both rk3036 and rk3288 and I end up
with a null pointer dereference in

[   10.640297] Unable to handle kernel NULL pointer dereference at virtual
address  [   10.654430] pgd = c0204000
[   10.657452] [] *pgd=
[   10.661473] Internal error: Oops: 5 [#1] SMP ARM
[   10.35] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp
snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip
clk_rk808 spi_rockchip [   10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not
tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [   10.692430] Hardware name:
Rockchip (Device Tree)
[   10.697692] Workqueue: events deferred_probe_work_func
[   10.702152] Linux video capture interface: v2.00
[   10.708590] task: ee38c800 task.stack: ed2e6000
[   10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm]
[   10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm]

The obvious reason for that is


@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop,
uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) &
reg->mask; }

-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
  {
-   if (!mask)
+   int offset = reg->offset + _offset;
+   int mask = reg->mask & _mask;
+   int shift = reg->shift;


Does the crash is that using reg->offset/mask/shift before !reg checking?


+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }

where the check for !reg happens after it got already dereferenced.
But even with that fixed I end up with

on rk3288:
[7.254823] rockchip-vop ff93.vop: Warning: not support global_regdone_en
[7.262847] rockchip-vop ff93.vop: Warning: not support gate
[7.269580] rockchip-vop ff93.vop: Warning: not support gate
[7.302765] rockchip-vop ff94.vop: Warning: not support global_regdone_en
[7.310758] rockchip-vop ff94.vop: Warning: not support gate
[7.317475] rockchip-vop ff94.vop: Warning: not support gate
[7.425724] rockchip-vop ff93.vop: Warning: not support edp_pin_pol
[7.526298] rockchip-vop ff94.vop: Warning: not support hdmi_pin_pol


Rk3288 does not support independent pin_pol settings, all output interfaces 
share the pin_pol register,
So not support hdmi_pin_pol here is correct.

hdmi pin pol would be set by following register:
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),



on rk3036:
[   12.389138] rockchip-vop 10118000.vop: Warning: not support global_regdone_en
[   12.397324] rockchip-vop 10118000.vop: Warning: not support gate
[   12.404165] rockchip-vop 10118000.vop: Warning: not support gate
[   13.747361] rockchip-vop 10118000.vop: Warning: not support hdmi_pin_pol
[   13.747371] rockchip-vop 10118000.vop: Warning: not support hdmi_en
[   13.747379] rockchip-vop 10118000.vop: Warning: not support hpost_st_end
[   13.747385] rockchip-vop 10118000.vop: Warning: not support vpost_st_end
[   13.747461] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
[   13.767098] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
[   13.786060] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl

While reqdone and friends are obviously features of newer vops, at least
the hdmi pin-pol is available on both these socs.

With this patch applied (and null-ptr fixed) I end up without hdmi output
on both socs.


Hmmm, I am confused, from code review, I didn't see what will cause hdmi not 
work on rk3036 and rk3288,

Give me some time, I try to bringup my popmetal rk3288 board to do the test.

Heiko, Thanks very much for your test.




Heiko

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--
Ｍark Yao

[PATCH v6 4/7] drm/rockchip: vop: group vop registers

2017-07-26 Thread Mark Yao

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99 
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  60 ---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112 +++-
 3 files changed, 144 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index fd47da5..92d098b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,30 +42,19 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define REG_SET(x, base, reg, v) \
-   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
-  v, reg.write_mask, reg.relaxed)
-#define REG_SET_MASK(x, base, reg, mask, v) \
-   vop_mask_write(x, base + reg.offset, \
-  mask, reg.shift, v, reg.write_mask, reg.relaxed)
-
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v)
+   vop_reg_set(vop, >phy->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v)
+   vop_reg_set(vop, >phy->scl->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v)
-#define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v)
-
-#define VOP_INTR_GET(vop, name) \
-   vop_read_reg(vop, 0, >data->ctrl->name)
-
-#define VOP_INTR_SET(vop, name, v) \
-   REG_SET(vop, 0, vop->data->intr->name, v)
+   vop_reg_set(vop, >phy->scl->ext->name, \
+   win->base, ~0, v, #name)
 
 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
+   vop_reg_set(vop, >data->intr->name, 0, mask, v, #name)
+
+#define VOP_REG_SET(vop, group, name, v) \
+   vop_reg_set(vop, >data->group->name, 0, ~0, v, #name)
 
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
@@ -82,7 +71,7 @@
vop_get_intr_type(vop, >data->intr->name, type)
 
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, 
uint32_t base,
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 }
 
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
 {
-   if (!mask)
+   int offset = reg->offset + _offset;
+   int mask = reg->mask & _mask;
+   int shift = reg->shift;
+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }
 
-   if (write_mask) {
+   if (reg->write_mask) {
v = ((v << shift) & 0x) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
@@ -180,7 +175,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t 
offset,
vop->regsbak[offset >> 2] = v;
}
 
-   if (relaxed)
+   if (reg->relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
@@ -202,7 +197,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
 
 static inline void vop_cfg_done(struct vop *vop)
 {
-   VOP_CTRL_SET(vop, cfg_done, 1);
+   VOP_REG_SET(vop, common, cfg_done, 1);
 }
 
 static bool has_rb_swapped(uint32_t format)
@@ -540,7 +535,7 @@ static int vop_enable(struct drm_crtc *crtc)
 
spin_lock(>reg_lock);
 
-   VOP_CTRL_SET(vop, standby, 0);
+   VOP_REG_SET(vop, common, standby, 1);
 
spin_unlock(>reg_lock);
 
@@ -600,7 +595,7 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
 
spin_lock(>

[PATCH v6 5/7] drm/rockchip: vop: add a series of vop support

2017-07-26 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v3:
- fixup some mistake
- use separate structures instead VOP_REG_VER mechanism

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   9 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 218 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 3 files changed, 908 insertions(+), 224 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 3ba962c..43d08c8 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -15,6 +15,14 @@
 #ifndef _ROCKCHIP_DRM_VOP_H
 #define _ROCKCHIP_DRM_VOP_H
 
+/*
+ * major: IP major version, used for IP structure
+ * minor: big feature change under same structure
+ */
+#define VOP_VERSION(major, minor)  ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
+
 enum vop_data_format {
VOP_FMT_ARGB = 0,
VOP_FMT_RGB888,
@@ -142,6 +150,7 @@ struct vop_win_data {
 };
 
 struct vop_data {
+   uint32_t version;
const struct vop_intr *intr;
const struct vop_common *common;
const struct vop_misc *misc;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 20607a8..bc7b2d0 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -277,6 +277,7 @@
 };
 
 static const struct vop_data rk3288_vop = {
+   .version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = _vop_intr,
.common = _common,
@@ -286,7 +287,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -296,22 +297,95 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
-   .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
-   .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
-   .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
+static const struct vop_intr rk3368_vop_intr = {
+   .intrs = rk3368_vop_intrs,
+   .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0x, 16),
+   .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
+   .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
+   .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
+};
+
+static const struct vop_win_phy rk3368_win23_data = {
+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
+   .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
+   .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
+   .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
+   .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
+   .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+};
+
+static const struct vop_win_data rk3368_vop_win_data[] = {
+   { .base = 0x00, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x40, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x00, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x50, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_output rk3368_output = {
+   .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16),
+   .hdmi_pin_pol = VOP_REG(RK3

[PATCH v6 7/7] drm/rockchip: vop: rk3328: fix overlay abnormal

2017-07-26 Thread Mark Yao

It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
   axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
   axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 92d098b..e4b3388 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1452,7 +1452,9 @@ static int vop_initial(struct vop *vop)
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
+   int channel = i * 2 + 1;
 
+   VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 1);
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 43d08c8..af1091f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -141,6 +141,7 @@ struct vop_win_phy {
 
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
+   struct vop_reg channel;
 };
 
 struct vop_win_data {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bc7b2d0..94de7b9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -197,6 +197,7 @@
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+   .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {
-- 
1.9.1


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[PATCH v6 2/7] drm/rockchip: vop: move write_relaxed flags to vop register

2017-07-26 Thread Mark Yao

Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
   cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v6:
- fix compile error

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 28 ---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 -
 3 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 81164d6..a792ea3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,33 +42,27 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
-
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
-
-#define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+#define REG_SET(x, base, reg, v) \
+   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
+  v, reg.write_mask, reg.relaxed)
+#define REG_SET_MASK(x, base, reg, mask, v) \
+   vop_mask_write(x, base + reg.offset, \
+  mask, reg.shift, v, reg.write_mask, reg.relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   REG_SET(x, win->base, win->phy->name, v)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   REG_SET(x, win->base, win->phy->scl->name, v)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
+   REG_SET(x, win->base, win->phy->scl->ext->name, v)
 #define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   REG_SET(x, 0, (x)->data->ctrl->name, v)
 
 #define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, >data->ctrl->name)
 
 #define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
+   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 084d3b2..056b974 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -29,6 +29,7 @@ struct vop_reg {
uint32_t shift;
uint32_t mask;
bool write_mask;
+   bool relaxed;
 };
 
 struct vop_ctrl {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 58da855..d7974da 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -20,17 +20,23 @@
 #include "rockchip_drm_vop.h"
 #include "rockchip_vop_reg.h"
 
-#define VOP_REG(off, _mask, s) \
-   {.offset = off, \
+#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
+   { \
+.offset = off, \
 .mask = _mask, \
-.shift = s, \
-.write_mask = false,}
+.shift = _shift, \
+.write_mask = _write_mask, \
+.relaxed = _relaxed, \
+   }
 
-#define VOP_REG_MASK(off, _mask, s) \
-   {.offset = off, \
-.mask = _mask, \
-.shift = s, \
-.write_mask = true,}
+#define VOP_REG(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, true)
+
+#define VOP_REG_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, false)
+
+#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, true, false)
 
 static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
@@ -116,7 +122,

[PATCH v6 6/7] dt-bindings: display: rockchip: fill Documents for vop series

2017-07-26 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk3228-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
1.9.1


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[PATCH v6 3/7] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-26 Thread Mark Yao

In the hardware design process, the design of line flags
register is associated with the interrupt register,
placing the line flags in the interrupt definition is
more reasonable, and it would make multi-vop define easilier.

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v6:
- fixes complie error

Changes in v3:
- Explain more in details, introduce why we need this patch

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 10 +++---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  8 
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index a792ea3..fd47da5 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -61,8 +61,12 @@
 #define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, >data->ctrl->name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
+#define VOP_INTR_SET(vop, name, v) \
+   REG_SET(vop, 0, vop->data->intr->name, v)
+
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
+
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -72,7 +76,7 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
@@ -982,7 +986,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
+   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
 
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 056b974..850f8e4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -60,8 +60,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -69,6 +67,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index d7974da..0a5f0d2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -116,6 +116,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -130,7 +131,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -226,7 +226,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -258,6 +257,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -294,8 +294,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1

[PATCH v6 0/7] drm/rockchip: add all full framework vop support

2017-07-26 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.13-rc1.

And other chips tested on rockchip kernel 4.4:
   
https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v6:
- fix some patches complie error
- fix rk3036 display blank

Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict 

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- Explain more on patch commit message
- move write_relaxed flags to vop registers
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

Mark Yao (7):
  drm/rockchip: vop: initialize registers directly
  drm/rockchip: vop: move write_relaxed flags to vop register
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: group vop registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: rockchip: fill Documents for vop series
  drm/rockchip: vop: rk3328: fix overlay abnormal

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 375 ++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 1075 insertions(+), 399 deletions(-)

-- 
1.9.1


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[PATCH v6 1/7] drm/rockchip: vop: initialize registers directly

2017-07-26 Thread Mark Yao

At present we are using init_table to initialize some
registers, but the Register init table use un-document define,
it is unreadable, and sometimes we only want to update tiny
bits, init table method is not friendly, it's diffcult to
reuse for difference chips.

To make it clean, initialize registers directly, and drops
init_table mechanism out.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v6:
- fix rk3036 blank display

Changes in v3:
- Explain more in details

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 44 -
 3 files changed, 11 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d45033..81164d6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1395,7 +1395,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1455,13 +1454,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..58da855 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -119,6 +119,7 @@
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
+   .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
@@ -127,13 +128,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +188,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +211,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_u

Re: [PATCH v5 2/7] drm/rockchip: vop: move write_relaxed flags to vop register

2017-07-26 Thread Mark yao


On 2017年07月26日 05:47, Heiko Stuebner wrote:

Hi Mark,

Am Donnerstag, 20. Juli 2017, 10:43:27 CEST schrieb Mark Yao:

Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 14 +++---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 -
  2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 81164d6..784a2b7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,18 +42,12 @@
  #include "rockchip_drm_psr.h"
  #include "rockchip_drm_vop.h"
  
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \

-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
-
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
-
  #define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
+  v, reg.write_mask, reg.relaxed)
  #define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, \
+  mask, reg.shift, v, reg.write_mask, reg.relaxed)

you only introduce the relaxed element of struct vop_reg in patch4.
So using it here produces a compile error

../drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function ‘vop_cfg_done’:
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:47:33: error: ‘const struct 
vop_reg’ has no member named ‘relaxed’
v, reg.write_mask, reg.relaxed)
  ^
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:59:3: note: in expansion of 
macro ‘REG_SET’
REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
^~~
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:201:2: note: in expansion of 
macro ‘VOP_CTRL_SET’
   VOP_CTRL_SET(vop, cfg_done, 1);
   ^~~~

when only patches 1+2 are applied. So the relaxed field addition should
definitly move into this patch to not break bisectability.


Heiko





Hi Heiko

Thanks for the test, will fix it at next version.

--
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Re: [PATCH v5 3/7] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-26 Thread Mark yao


On 2017年07月26日 05:54, Heiko Stuebner wrote:

Hi Mark,

Am Donnerstag, 20. Juli 2017, 10:43:32 CEST schrieb Mark Yao:

In the hardware design process, the design of line flags
register is associated with the interrupt register,
placing the line flags in the interrupt definition is
more reasonable, and it would make multi-vop define easilier.

Changes in v3:
- Explain more in details, introduce why we need this patch

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
  3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 784a2b7..4f6c7bc 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -982,7 +982,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
  
-	VOP_CTRL_SET(vop, line_flag_num[0], vact_end);

+   VOP_INTR_SET(vop, line_flag_num[0], vact_end);

With patches applied up to this one I end up with

   CC [M]  drivers/gpu/drm/rockchip/rockchip_drm_vop.o
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function ‘vop_crtc_enable’:
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:985:46: error: macro 
"VOP_INTR_SET" requires 4 arguments, but only 3 given
   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
   ^
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:985:2: error: ‘VOP_INTR_SET’ 
undeclared (first use in this function)
   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
   ^~~~
../drivers/gpu/drm/rockchip/rockchip_drm_vop.c:985:2: note: each undeclared 
identifier is reported only once for each function it appears in

In patch4 you replace this again, with
-   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
+   VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);

but this intermediate breakage should not happen, to keep bisectability.


Heiko




Hi Heiko

Thanks for the test, will fix it at next version.

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Re: [PATCH v5 1/7] drm/rockchip: vop: initialize registers directly

2017-07-25 Thread Mark yao


On 2017年07月26日 06:36, Heiko Stuebner wrote:

Hi Mark,

Am Donnerstag, 20. Juli 2017, 10:43:22 CEST schrieb Mark Yao:

At present we are using init_table to initialize some
registers, but the Register init table use un-document define,
it is unreadable, and sometimes we only want to update tiny
bits, init table method is not friendly, it's diffcult to
reuse for difference chips.

To make it clean, initialize registers directly, and drops
init_table mechanism out.

Changes in v3:
- Explain more in details

Signed-off-by: Mark Yao <mark@rock-chips.com>

[...]


diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
  };
  
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {

-   {RK3036_DSP_CTRL1, 0x},
-};
-
  static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,

This seems to break vop initialization on my rk3036 kylin board.

Before, kylin was able to bring output to the hdmi but with this
patch applied this stops working. As the init-value is to zero it seems
there is still something turned on, that should be turned off instead.

rk3288 seems to stay in working condition though.


Heiko

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Hi Heiko

Thanks for your testing on rk3036 board.

I research the init table on rk3036, the dsp_blank reset value is 1, we need 
set the register to zero.

So I think not working problem can be fixed by following change:

drivers/gpu/drm/rockchip/rockchip_vop_reg.c:
static const struct vop_ctrl rk3036_ctrl_data = {
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
+   .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),

--
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Re: [PATCH v5 6/7] dt-bindings: display: rockchip: fill Documents for vop series

2017-07-24 Thread Mark yao


On 2017年07月25日 03:53, Rob Herring wrote:

On Thu, Jul 20, 2017 at 10:43:53AM +0800, Mark Yao wrote:

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

  Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
  1 file changed, 4 insertions(+)

Acked-by: Rob Herring <r...@kernel.org>




Thanks for the Ack. :-)

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Re: [PATCH] [RESEND] drm/rockchip: fix Kconfig dependencies

2017-07-23 Thread Mark yao


On 2017年07月22日 05:12, Arnd Bergmann wrote:

A bug that I had fixed earlier just came back, with CONFIG_EXTCON=m,
the rockchip drm driver will fail to link:

drivers/gpu/drm/rockchip/cdn-dp-core.o: In function `cdn_dp_get_port_lanes':
cdn-dp-core.c:(.text.cdn_dp_get_port_lanes+0x30): undefined reference to 
`extcon_get_state'
cdn-dp-core.c:(.text.cdn_dp_get_port_lanes+0x6c): undefined reference to 
`extcon_get_property'
drivers/gpu/drm/rockchip/cdn-dp-core.o: In function 
`cdn_dp_check_sink_connection':
cdn-dp-core.c:(.text.cdn_dp_check_sink_connection+0x80): undefined reference to 
`extcon_get_state'
drivers/gpu/drm/rockchip/cdn-dp-core.o: In function `cdn_dp_enable':
cdn-dp-core.c:(.text.cdn_dp_enable+0x748): undefined reference to 
`extcon_get_property'

The problem is that that the sub-drivers are now all linked into the
main rockchip drm module, which breaks all the Kconfig dependencies
that are specified in the options for those sub-drivers.

This clarifies the dependency to ensure that we can only turn on the DP
driver when EXTCON is reachable. As the 'select' statements can now
cause additional options to become built-in when they should be
loadable modules, I'm moving those into the main driver config option.
The dependency on DRM_ROCKCHIP can be reduced into a single 'if'
statement here for brevity, but this has no functional effect.

Fixes: b6705157b2db ("drm/rockchip: add extcon dependency for DP")
Fixes: 8820b68bd378 ("drm/rockchip: Refactor the component match logic.")
Link:https://patchwork.kernel.org/patch/9648761/
Acked-by: Guenter Roeck
Tested-by: Jeffy Chen
Signed-off-by: Arnd Bergmann


Pushed to drm-misc-fixes.

Thanks.

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[PATCH v5 6/7] dt-bindings: display: rockchip: fill Documents for vop series

2017-07-19 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk3228-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
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[PATCH v5 7/7] drm/rockchip: vop: rk3328: fix overlay abnormal

2017-07-19 Thread Mark Yao

It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
   axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
   axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 92d098b..e4b3388 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1452,7 +1452,9 @@ static int vop_initial(struct vop *vop)
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
+   int channel = i * 2 + 1;
 
+   VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 1);
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 43d08c8..af1091f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -141,6 +141,7 @@ struct vop_win_phy {
 
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
+   struct vop_reg channel;
 };
 
 struct vop_win_data {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 99f8ba4..cc8d408 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -196,6 +196,7 @@
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+   .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {
-- 
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[PATCH v5 0/7] drm/rockchip: add all full framework vop support

2017-07-19 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.13-rc1.

And other chips tested on rockchip kernel 4.4:
   
https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg

Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict 

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- Explain more on patch commit message
- move write_relaxed flags to vop registers
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define

Mark Yao (7):
  drm/rockchip: vop: initialize registers directly
  drm/rockchip: vop: move write_relaxed flags to vop register
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: group vop registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: rockchip: fill Documents for vop series
  drm/rockchip: vop: rk3328: fix overlay abnormal

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 374 ++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 1074 insertions(+), 399 deletions(-)

-- 
1.9.1


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[PATCH v5 1/7] drm/rockchip: vop: initialize registers directly

2017-07-19 Thread Mark Yao

At present we are using init_table to initialize some
registers, but the Register init table use un-document define,
it is unreadable, and sometimes we only want to update tiny
bits, init table method is not friendly, it's diffcult to
reuse for difference chips.

To make it clean, initialize registers directly, and drops
init_table mechanism out.

Changes in v3:
- Explain more in details

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
 3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d45033..81164d6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1395,7 +1395,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1455,13 +1454,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -224,22 +220,10 @@
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),

[PATCH v5 3/7] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-19 Thread Mark Yao

In the hardware design process, the design of line flags
register is associated with the interrupt register,
placing the line flags in the interrupt definition is
more reasonable, and it would make multi-vop define easilier.

Changes in v3:
- Explain more in details, introduce why we need this patch

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 784a2b7..4f6c7bc 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -982,7 +982,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
+   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
 
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 084d3b2..9c5da32 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -59,8 +59,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -68,6 +66,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 691dd42..064a46d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -116,6 +116,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -129,7 +130,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -225,7 +225,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -257,6 +256,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -293,8 +293,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -311,6 +309,8 @@
 static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
-- 
1.9.1


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[PATCH v5 5/7] drm/rockchip: vop: add a series of vop support

2017-07-19 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Changes in v3:
- fixup some mistake
- use separate structures instead VOP_REG_VER mechanism

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   9 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 202 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 3 files changed, 902 insertions(+), 214 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 3ba962c..43d08c8 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -15,6 +15,14 @@
 #ifndef _ROCKCHIP_DRM_VOP_H
 #define _ROCKCHIP_DRM_VOP_H
 
+/*
+ * major: IP major version, used for IP structure
+ * minor: big feature change under same structure
+ */
+#define VOP_VERSION(major, minor)  ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
+
 enum vop_data_format {
VOP_FMT_ARGB = 0,
VOP_FMT_RGB888,
@@ -142,6 +150,7 @@ struct vop_win_data {
 };
 
 struct vop_data {
+   uint32_t version;
const struct vop_intr *intr;
const struct vop_common *common;
const struct vop_misc *misc;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 53bcdd5..99f8ba4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -276,6 +276,7 @@
 };
 
 static const struct vop_data rk3288_vop = {
+   .version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = _vop_intr,
.common = _common,
@@ -285,7 +286,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -295,14 +296,87 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
-   .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
-   .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
-   .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
+static const struct vop_intr rk3368_vop_intr = {
+   .intrs = rk3368_vop_intrs,
+   .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0x, 16),
+   .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
+   .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
+   .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
+};
+
+static const struct vop_win_phy rk3368_win23_data = {
+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
+   .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
+   .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
+   .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
+   .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
+   .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+};
+
+static const struct vop_win_data rk3368_vop_win_data[] = {
+   { .base = 0x00, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x40, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x00, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x50, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_output rk3368_output = {
+   .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16),
+   .hdmi_pin_pol = VOP_REG(RK3

[PATCH v5 4/7] drm/rockchip: vop: group vop registers

2017-07-19 Thread Mark Yao

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  61 +---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 106 +++-
 3 files changed, 142 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4f6c7bc..92d098b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,27 +42,20 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define REG_SET(x, base, reg, v, mode) \
-   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
-  v, reg.write_mask, reg.relaxed)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   vop_mask_write(x, base + reg.offset, \
-  mask, reg.shift, v, reg.write_mask, reg.relaxed)
-
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   vop_reg_set(vop, >phy->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   vop_reg_set(vop, >phy->scl->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
-#define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   vop_reg_set(vop, >phy->scl->ext->name, \
+   win->base, ~0, v, #name)
+
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   vop_reg_set(vop, >data->intr->name, 0, mask, v, #name)
 
-#define VOP_INTR_GET(vop, name) \
-   vop_read_reg(vop, 0, >data->ctrl->name)
+#define VOP_REG_SET(vop, group, name, v) \
+   vop_reg_set(vop, >data->group->name, 0, ~0, v, #name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -72,13 +65,13 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
 
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
@@ -160,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, 
uint32_t base,
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 }
 
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
 {
-   if (!mask)
+   int offset = reg->offset + _offset;
+   int mask = reg->mask & _mask;
+   int shift = reg->shift;
+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }
 
-   if (write_mask) {
+   if (reg->write_mask) {
v = ((v << shift) & 0x) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
@@ -176,7 +175,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t 
offset,
vop->regsbak[offset >> 2] = v;
}
 
-   if (relaxed)
+   if (reg->relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
@@ -198,7 +197,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
 
 static inline void vop_cfg_done(struct vop *vop)
 {
-   VOP_CTRL_SET(vop, cfg_done, 1);
+   VOP_REG_SET(vop, common, cfg_done, 1);
 }
 
 static bool has_rb_swapped(uint32_t format)
@@ -536,7 +

[PATCH v5 2/7] drm/rockchip: vop: move write_relaxed flags to vop register

2017-07-19 Thread Mark Yao

Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
   cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 14 +++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 -
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 81164d6..784a2b7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,18 +42,12 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
-
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
-
 #define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
+  v, reg.write_mask, reg.relaxed)
 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, \
+  mask, reg.shift, v, reg.write_mask, reg.relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, win->base, win->phy->name, v, RELAXED)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 00e9d79..691dd42 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -20,17 +20,23 @@
 #include "rockchip_drm_vop.h"
 #include "rockchip_vop_reg.h"
 
-#define VOP_REG(off, _mask, s) \
-   {.offset = off, \
+#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
+   { \
+.offset = off, \
 .mask = _mask, \
-.shift = s, \
-.write_mask = false,}
+.shift = _shift, \
+.write_mask = _write_mask, \
+.relaxed = _relaxed, \
+   }
 
-#define VOP_REG_MASK(off, _mask, s) \
-   {.offset = off, \
-.mask = _mask, \
-.shift = s, \
-.write_mask = true,}
+#define VOP_REG(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, true)
+
+#define VOP_REG_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, false)
+
+#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, true, false)
 
 static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
@@ -116,7 +122,7 @@
 };
 
 static const struct vop_ctrl rk3036_ctrl_data = {
-   .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
+   .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -124,7 +130,7 @@
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
-   .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
 static const struct vop_data rk3036_vop = {
@@ -200,7 +206,7 @@
 };
 
 static const struct vop_ctrl rk3288_ctrl_data = {
-   .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
@@ -221,7 +227,7 @@
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
-   .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
 
 /*
@@ -265,7 +271,7 @@
 };
 
 static const struct vop_ctrl rk3399_ctrl_data = {
-   .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3399_SYS_CTR

Re: [PATCH v2 5/5] dt-bindings: display: fill Documents for series of vop

2017-07-19 Thread Mark yao


On 2017年07月18日 01:24, Rob Herring wrote:

On Wed, Jul 12, 2017 at 10:04:02AM +0800, Mark Yao wrote:

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)

This goes below '---' and you need a commit msg here. Also, it is not
clear in the subject this is for Rockchip.



Got it, will fix it at next version.

Thanks.


Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
  1 file changed, 4 insertions(+)

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--
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Re: [PATCH v4 0/7] drm/rockchip: add all full framework vop support

2017-07-18 Thread Mark yao


Sorry for sending this mail without thread, my send-patches scripts has a 
bug:-( , Already fix the script bug.

On 2017年07月19日 10:57, Mark Yao wrote:

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
   3.1   rk3288
   3.2   rk3368
   3.4   rk3366
   3.5   rk3399 big
   3.6   rk3399 lit
   3.7   rk3228
   3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.13-rc1.

And other chips tested on rockchip kernel 4.4:

https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- move write_relaxed flags to vop registers
- Explain more on patch commit message
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Mark Yao (7):
   drm/rockchip: vop: initialize registers directly
   drm/rockchip: vop: move write_relaxed flags to vop register
   drm/rockchip: vop: move line_flag_num to interrupt registers
   drm/rockchip: vop: group vop registers
   drm/rockchip: vop: add a series of vop support
   dt-bindings: display: fill Documents for series of vop
   drm/rockchip: vop: rk3328: fix overlay abnormal

  .../bindings/display/rockchip/rockchip-vop.txt |   4 +
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 374 ++---
  drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
  5 files changed, 1074 insertions(+), 399 deletions(-)




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[PATCH v4 0/7] drm/rockchip: add all full framework vop support

2017-07-18 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.13-rc1.

And other chips tested on rockchip kernel 4.4:
   
https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict 

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- move write_relaxed flags to vop registers
- Explain more on patch commit message
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Mark Yao (7):
  drm/rockchip: vop: initialize registers directly
  drm/rockchip: vop: move write_relaxed flags to vop register
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: group vop registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: fill Documents for series of vop
  drm/rockchip: vop: rk3328: fix overlay abnormal

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 374 ++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 1074 insertions(+), 399 deletions(-)

-- 
1.9.1


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[PATCH v4 1/7] drm/rockchip: vop: initialize registers directly

2017-07-18 Thread Mark Yao

At present we are using init_table to initialize some
registers, but the Register init table use un-document define,
it is unreadable, and sometimes we only want to update tiny
bits, init table method is not friendly, it's diffcult to
reuse for difference chips.

To make it clean, initialize registers directly, and drops
init_table mechanism out.

Changes in v3:
- Explain more in details

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
 3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d45033..81164d6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1395,7 +1395,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1455,13 +1454,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -224,22 +220,10 @@
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),

[PATCH v4 4/7] drm/rockchip: vop: group vop registers

2017-07-18 Thread Mark Yao

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  61 +---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 106 +++-
 3 files changed, 142 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4f6c7bc..92d098b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,27 +42,20 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define REG_SET(x, base, reg, v, mode) \
-   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
-  v, reg.write_mask, reg.relaxed)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   vop_mask_write(x, base + reg.offset, \
-  mask, reg.shift, v, reg.write_mask, reg.relaxed)
-
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   vop_reg_set(vop, >phy->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   vop_reg_set(vop, >phy->scl->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
-#define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   vop_reg_set(vop, >phy->scl->ext->name, \
+   win->base, ~0, v, #name)
+
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   vop_reg_set(vop, >data->intr->name, 0, mask, v, #name)
 
-#define VOP_INTR_GET(vop, name) \
-   vop_read_reg(vop, 0, >data->ctrl->name)
+#define VOP_REG_SET(vop, group, name, v) \
+   vop_reg_set(vop, >data->group->name, 0, ~0, v, #name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -72,13 +65,13 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
 
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
@@ -160,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, 
uint32_t base,
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 }
 
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
 {
-   if (!mask)
+   int offset = reg->offset + _offset;
+   int mask = reg->mask & _mask;
+   int shift = reg->shift;
+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }
 
-   if (write_mask) {
+   if (reg->write_mask) {
v = ((v << shift) & 0x) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
@@ -176,7 +175,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t 
offset,
vop->regsbak[offset >> 2] = v;
}
 
-   if (relaxed)
+   if (reg->relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
@@ -198,7 +197,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
 
 static inline void vop_cfg_done(struct vop *vop)
 {
-   VOP_CTRL_SET(vop, cfg_done, 1);
+   VOP_REG_SET(vop, common, cfg_done, 1);
 }
 
 static bool has_rb_swapped(uint32_t format)
@@ -536,7 +

[PATCH v4 3/7] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-18 Thread Mark Yao

In the hardware design process, the design of line flags
register is associated with the interrupt register,
placing the line flags in the interrupt definition is
more reasonable, and it would make multi-vop define easilier.

Changes in v3:
- Explain more in details, introduce why we need this patch

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 784a2b7..4f6c7bc 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -982,7 +982,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
+   VOP_INTR_SET(vop, line_flag_num[0], vact_end);
 
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 084d3b2..9c5da32 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -59,8 +59,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -68,6 +66,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 691dd42..064a46d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -116,6 +116,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -129,7 +130,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -225,7 +225,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -257,6 +256,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -293,8 +293,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -311,6 +309,8 @@
 static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
-- 
1.9.1


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dri-devel@lists.freedesktop.org
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[PATCH v4 2/7] drm/rockchip: vop: move write_relaxed flags to vop register

2017-07-18 Thread Mark Yao

Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
   cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 14 +++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 -
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 81164d6..784a2b7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,18 +42,12 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
-
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
-
 #define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
+  v, reg.write_mask, reg.relaxed)
 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, \
+  mask, reg.shift, v, reg.write_mask, reg.relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, win->base, win->phy->name, v, RELAXED)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 00e9d79..691dd42 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -20,17 +20,23 @@
 #include "rockchip_drm_vop.h"
 #include "rockchip_vop_reg.h"
 
-#define VOP_REG(off, _mask, s) \
-   {.offset = off, \
+#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
+   { \
+.offset = off, \
 .mask = _mask, \
-.shift = s, \
-.write_mask = false,}
+.shift = _shift, \
+.write_mask = _write_mask, \
+.relaxed = _relaxed, \
+   }
 
-#define VOP_REG_MASK(off, _mask, s) \
-   {.offset = off, \
-.mask = _mask, \
-.shift = s, \
-.write_mask = true,}
+#define VOP_REG(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, true)
+
+#define VOP_REG_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, false)
+
+#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, true, false)
 
 static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
@@ -116,7 +122,7 @@
 };
 
 static const struct vop_ctrl rk3036_ctrl_data = {
-   .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
+   .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -124,7 +130,7 @@
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
-   .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
 static const struct vop_data rk3036_vop = {
@@ -200,7 +206,7 @@
 };
 
 static const struct vop_ctrl rk3288_ctrl_data = {
-   .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
@@ -221,7 +227,7 @@
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
-   .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
 
 /*
@@ -265,7 +271,7 @@
 };
 
 static const struct vop_ctrl rk3399_ctrl_data = {
-   .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3399_SYS_CTR

[PATCH v4 6/7] dt-bindings: display: fill Documents for series of vop

2017-07-18 Thread Mark Yao

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk3228-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
1.9.1


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[PATCH v4 5/7] drm/rockchip: vop: add a series of vop support

2017-07-18 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Changes in v3:
- fixup some mistake
- use separate structures instead VOP_REG_VER mechanism

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   9 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 202 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 3 files changed, 902 insertions(+), 214 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 3ba962c..43d08c8 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -15,6 +15,14 @@
 #ifndef _ROCKCHIP_DRM_VOP_H
 #define _ROCKCHIP_DRM_VOP_H
 
+/*
+ * major: IP major version, used for IP structure
+ * minor: big feature change under same structure
+ */
+#define VOP_VERSION(major, minor)  ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
+
 enum vop_data_format {
VOP_FMT_ARGB = 0,
VOP_FMT_RGB888,
@@ -142,6 +150,7 @@ struct vop_win_data {
 };
 
 struct vop_data {
+   uint32_t version;
const struct vop_intr *intr;
const struct vop_common *common;
const struct vop_misc *misc;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 53bcdd5..99f8ba4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -276,6 +276,7 @@
 };
 
 static const struct vop_data rk3288_vop = {
+   .version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = _vop_intr,
.common = _common,
@@ -285,7 +286,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -295,14 +296,87 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
-   .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
-   .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
-   .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
+static const struct vop_intr rk3368_vop_intr = {
+   .intrs = rk3368_vop_intrs,
+   .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0x, 16),
+   .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
+   .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
+   .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
+};
+
+static const struct vop_win_phy rk3368_win23_data = {
+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
+   .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
+   .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
+   .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
+   .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
+   .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+};
+
+static const struct vop_win_data rk3368_vop_win_data[] = {
+   { .base = 0x00, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x40, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x00, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x50, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_output rk3368_output = {
+   .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16),
+   .hdmi_pin_pol = VOP_REG(RK3

[PATCH v4 7/7] drm/rockchip: vop: rk3328: fix overlay abnormal

2017-07-18 Thread Mark Yao

It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
   axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
   axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 92d098b..e4b3388 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1452,7 +1452,9 @@ static int vop_initial(struct vop *vop)
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
+   int channel = i * 2 + 1;
 
+   VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 1);
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 43d08c8..af1091f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -141,6 +141,7 @@ struct vop_win_phy {
 
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
+   struct vop_reg channel;
 };
 
 struct vop_win_data {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 99f8ba4..cc8d408 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -196,6 +196,7 @@
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+   .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {
-- 
1.9.1


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[PATCH v3 6/7] dt-bindings: display: fill Documents for series of vop

2017-07-17 Thread Mark Yao

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk3228-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
1.9.1


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[PATCH v3 3/7] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-17 Thread Mark Yao

In the hardware design process, the design of line flags
register is associated with the interrupt register,
placing the line flags in the interrupt definition is
more reasonable, and it would make multi-vop define easilier.

Changes in v3:
- Explain more in details, introduce why we need this patch

Signed-off-by: Mark Yao <mark@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 101f3db..add097c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -471,7 +471,7 @@ static void vop_line_flag_irq_enable(struct vop *vop, int 
line_num)
 
spin_lock_irqsave(>irq_lock, flags);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], line_num);
+   VOP_INTR_SET(vop, line_flag_num[0], line_num);
VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 084d3b2..9c5da32 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -59,8 +59,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -68,6 +66,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 691dd42..064a46d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -116,6 +116,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -129,7 +130,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -225,7 +225,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -257,6 +256,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -293,8 +293,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -311,6 +309,8 @@
 static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
-- 
1.9.1


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[PATCH v3 5/7] drm/rockchip: vop: add a series of vop support

2017-07-17 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Changes in v3:
- fixup some mistake
- use separate structures instead VOP_REG_VER mechanism

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   9 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 202 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 3 files changed, 902 insertions(+), 214 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 3ba962c..43d08c8 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -15,6 +15,14 @@
 #ifndef _ROCKCHIP_DRM_VOP_H
 #define _ROCKCHIP_DRM_VOP_H
 
+/*
+ * major: IP major version, used for IP structure
+ * minor: big feature change under same structure
+ */
+#define VOP_VERSION(major, minor)  ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
+
 enum vop_data_format {
VOP_FMT_ARGB = 0,
VOP_FMT_RGB888,
@@ -142,6 +150,7 @@ struct vop_win_data {
 };
 
 struct vop_data {
+   uint32_t version;
const struct vop_intr *intr;
const struct vop_common *common;
const struct vop_misc *misc;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 53bcdd5..99f8ba4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -276,6 +276,7 @@
 };
 
 static const struct vop_data rk3288_vop = {
+   .version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = _vop_intr,
.common = _common,
@@ -285,7 +286,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -295,14 +296,87 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
-   .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0x, 0),
-   .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0x, 0),
-   .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0x, 0),
+static const struct vop_intr rk3368_vop_intr = {
+   .intrs = rk3368_vop_intrs,
+   .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0x, 16),
+   .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
+   .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
+   .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
+};
+
+static const struct vop_win_phy rk3368_win23_data = {
+   .data_formats = formats_win_lite,
+   .nformats = ARRAY_SIZE(formats_win_lite),
+   .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
+   .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
+   .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
+   .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
+   .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
+   .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0x, 0),
+   .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
+   .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
+   .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
+};
+
+static const struct vop_win_data rk3368_vop_win_data[] = {
+   { .base = 0x00, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_PRIMARY },
+   { .base = 0x40, .phy = _win01_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x00, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_OVERLAY },
+   { .base = 0x50, .phy = _win23_data,
+ .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const struct vop_output rk3368_output = {
+   .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16),
+   .hdmi_pin_pol = VOP_REG(RK3

[PATCH v3 7/7] drm/rockchip: vop: rk3328: fix overlay abnormal

2017-07-17 Thread Mark Yao

It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
   axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
   axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4e9d372..07efb42 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1450,7 +1450,9 @@ static int vop_initial(struct vop *vop)
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
+   int channel = i * 2 + 1;
 
+   VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 1);
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 43d08c8..af1091f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -141,6 +141,7 @@ struct vop_win_phy {
 
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
+   struct vop_reg channel;
 };
 
 struct vop_win_data {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 99f8ba4..cc8d408 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -196,6 +196,7 @@
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+   .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {
-- 
1.9.1


___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 2/7] drm/rockchip: vop: move write_relaxed flags to vop register

2017-07-17 Thread Mark Yao

Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
   cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 14 +++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 -
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 7a5f809..101f3db 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,18 +42,12 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
-
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
-
 #define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
+  v, reg.write_mask, reg.relaxed)
 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+   vop_mask_write(x, base + reg.offset, \
+  mask, reg.shift, v, reg.write_mask, reg.relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, win->base, win->phy->name, v, RELAXED)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 00e9d79..691dd42 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -20,17 +20,23 @@
 #include "rockchip_drm_vop.h"
 #include "rockchip_vop_reg.h"
 
-#define VOP_REG(off, _mask, s) \
-   {.offset = off, \
+#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
+   { \
+.offset = off, \
 .mask = _mask, \
-.shift = s, \
-.write_mask = false,}
+.shift = _shift, \
+.write_mask = _write_mask, \
+.relaxed = _relaxed, \
+   }
 
-#define VOP_REG_MASK(off, _mask, s) \
-   {.offset = off, \
-.mask = _mask, \
-.shift = s, \
-.write_mask = true,}
+#define VOP_REG(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, true)
+
+#define VOP_REG_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, false, false)
+
+#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
+   _VOP_REG(off, _mask, _shift, true, false)
 
 static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
@@ -116,7 +122,7 @@
 };
 
 static const struct vop_ctrl rk3036_ctrl_data = {
-   .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
+   .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -124,7 +130,7 @@
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
-   .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
 static const struct vop_data rk3036_vop = {
@@ -200,7 +206,7 @@
 };
 
 static const struct vop_ctrl rk3288_ctrl_data = {
-   .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
@@ -221,7 +227,7 @@
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
-   .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
+   .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
 };
 
 /*
@@ -265,7 +271,7 @@
 };
 
 static const struct vop_ctrl rk3399_ctrl_data = {
-   .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
+   .standby = VOP_REG_SYNC(RK3399_SYS_CTR

[PATCH v3 4/7] drm/rockchip: vop: group vop registers

2017-07-17 Thread Mark Yao

Grouping the vop registers facilitates make register
definition clearer, and also is useful for different vop
reuse the same group register.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  99 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  61 +---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 106 +++-
 3 files changed, 142 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index add097c..4e9d372 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,27 +42,20 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define REG_SET(x, base, reg, v, mode) \
-   vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
-  v, reg.write_mask, reg.relaxed)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   vop_mask_write(x, base + reg.offset, \
-  mask, reg.shift, v, reg.write_mask, reg.relaxed)
-
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   vop_reg_set(vop, >phy->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   vop_reg_set(vop, >phy->scl->name, win->base, ~0, v, #name)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
-#define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   vop_reg_set(vop, >phy->scl->ext->name, \
+   win->base, ~0, v, #name)
+
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   vop_reg_set(vop, >data->intr->name, 0, mask, v, #name)
 
-#define VOP_INTR_GET(vop, name) \
-   vop_read_reg(vop, 0, >data->ctrl->name)
+#define VOP_REG_SET(vop, group, name, v) \
+   vop_reg_set(vop, >data->group->name, 0, ~0, v, #name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -72,13 +65,13 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
 
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
@@ -160,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, 
uint32_t base,
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 }
 
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t shift, uint32_t v,
- bool write_mask, bool relaxed)
+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
+   uint32_t _offset, uint32_t _mask, uint32_t v,
+   const char *reg_name)
 {
-   if (!mask)
+   int offset = reg->offset + _offset;
+   int mask = reg->mask & _mask;
+   int shift = reg->shift;
+
+   if (!reg || !reg->mask) {
+   dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
return;
+   }
 
-   if (write_mask) {
+   if (reg->write_mask) {
v = ((v << shift) & 0x) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
@@ -176,7 +175,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t 
offset,
vop->regsbak[offset >> 2] = v;
}
 
-   if (relaxed)
+   if (reg->relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
@@ -198,7 +197,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
 
 static inline void vop_cfg_done(struct vop *vop)
 {
-   VOP_CTRL_SET(vop, cfg_done, 1);
+   VOP_REG_SET(vop, common, cfg_done, 1);
 }
 
 static bool has_rb_swapped(uint32_t format)
@@ -471,7

[PATCH v3 1/7] drm/rockchip: vop: initialize registers directly

2017-07-17 Thread Mark Yao

At present we are using init_table to initialize some
registers, but the Register init table use un-document define,
it is unreadable, and sometimes we only want to update tiny
bits, init table method is not friendly, it's diffcult to
reuse for difference chips.

To make it clean, initialize registers directly, and drops
init_table mechanism out.

Changes in v3:
- Explain more in details

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
 3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 45589d6..7a5f809 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1393,7 +1393,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1453,13 +1452,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -224,22 +220,10 @@
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),

[PATCH v3 0/7] drm/rockchip: add all full framework vop support

2017-07-17 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, fill missing vop on full framework.
Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

Group the vop register, it would make register  definition clearer and
more easily to reuse same group register define for difference vops.

Tested on rk3399 excavator board with kernel 4.12-rc1.

And other chips works find on rockchip kernel 4.4:
   
https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/rockchip

Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- move write_relaxed flags to vop registers
- Explain more on patch commit message
- fix rk3328 overlay abnormal

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Mark Yao (7):
  drm/rockchip: vop: initialize registers directly
  drm/rockchip: vop: move write_relaxed flags to vop register
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: group vop registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: fill Documents for series of vop
  drm/rockchip: vop: rk3328: fix overlay abnormal

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 109 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  81 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 374 ++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 1074 insertions(+), 399 deletions(-)

-- 
1.9.1


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Re: [PATCH v2 1/5] drm/rockchip: vop: get rid of register init table

2017-07-16 Thread Mark yao


On 2017年07月14日 04:29, Sean Paul wrote:

On Thu, Jul 13, 2017 at 09:33:45AM +0800, Mark yao wrote:

On 2017年07月13日 00:47, Sean Paul wrote:

On Wed, Jul 12, 2017 at 10:03:27AM +0800, Mark Yao wrote:

Register init table use un-document define, it is unreadable,
And sometimes we only want to update tiny bits, init table
method is not friendly, it's diffcult to reuse for difference
chips.

While I'm happy to see the init_table removed, it seems like the new code is not
equivalent to the old (ie: some register writes have been dropped). How did you
ensure that you're not breaking existing boards that depend on the deleted 
register
initialization?

Sean

All the existing boards works fine on my internal kernel board with the 
init_table removed,
We had tested all the existing boards, so it's no problem to removed init_table


That begs the question... why was it introduced if it's not necessary?

Hi Sean

Some registers need to be initialized when vop power on, global_config_done, 
blank, win gate, etc.
Previously init_table was introduced to handle the initialization of these 
registers.

So, when we remove the init_table mechanism, we need to re-join the 
initialization of these registers,
this job is already done in this patch.

I think the title "get rid of" caused some doubts, it's not just remove 
init_table mechanism,
to be exact, direct setting needed register instead of handling with init_table.

I will make it cleaner next version.

Thanks.



Sean


Signed-off-by: Mark Yao <mark@rock-chips.com>
---
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
   drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
   drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 
+++--
   3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 45589d6..7a5f809 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1393,7 +1393,6 @@ static void vop_destroy_crtc(struct vop *vop)
   static int vop_initial(struct vop *vop)
   {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
@@ -1453,13 +1452,14 @@ static int vop_initial(struct vop *vop)
memcpy(vop->regsbak, vop->regs, vop->len);
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
   };
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
   struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
struct vop_reg line_flag_num[2];
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
   };
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
   };
   struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
   };
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
   static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_da

Re: [PATCH v2 3/5] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-12 Thread Mark yao


On 2017年07月13日 01:54, Sean Paul wrote:

On Wed, Jul 12, 2017 at 10:03:46AM +0800, Mark Yao wrote:

Again, please add commit message describing the what and why of this change.

You can also add:

Reviewed-by: Sean Paul <seanp...@chromium.org>



Thanks for the review, will fix it at next version.


Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
  3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index a9180fd..be208ee 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -507,7 +507,7 @@ static void vop_line_flag_irq_enable(struct vop *vop, int 
line_num)
  
  	spin_lock_irqsave(>irq_lock, flags);
  
-	VOP_CTRL_SET(vop, line_flag_num[0], line_num);

+   VOP_INTR_SET(vop, line_flag_num[0], line_num);
VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
  
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h

index e4de890..f64685e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -70,8 +70,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
  
-	struct vop_reg line_flag_num[2];

-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
  };
@@ -79,6 +77,8 @@ struct vop_ctrl {
  struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7744603..159cedf 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -118,6 +118,7 @@
  static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -131,7 +132,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
  };
  
@@ -227,7 +227,6 @@

.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
  };
@@ -259,6 +258,7 @@
  static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -295,8 +295,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
  };
  
@@ -313,6 +311,8 @@

  static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0x, 0),
--
1.9.1





--
Ｍark Yao


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Re: [PATCH v2 2/5] drm/rockchip: vop: support verify registers with vop version

2017-07-12 Thread Mark yao


On 2017年07月13日 01:53, Sean Paul wrote:

On Wed, Jul 12, 2017 at 10:03:38AM +0800, Mark Yao wrote:

Please add a commit message describing *what* and *why* you are making the
change.


Got it, I will fix it at next version.

Thanks.



Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 66 +
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 18 ++--
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 20 ++---
  3 files changed, 77 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 7a5f809..a9180fd 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,33 +42,60 @@
  #include "rockchip_drm_psr.h"
  #include "rockchip_drm_vop.h"
  
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \

-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
+#define VOP_REG_SUPPORT(vop, reg) \
+   (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
+   reg.begin_minor <= VOP_MINOR(vop->data->version) && \
+   reg.end_minor >= VOP_MINOR(vop->data->version) && \
+   reg.mask))

This would be better suited as a static inline function. As would many of the
macros below.


Got it, will fix it at next version.


  
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \

-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
+#define VOP_WIN_SUPPORT(vop, win, name) \
+   VOP_REG_SUPPORT(vop, win->phy->name)
  
-#define REG_SET(x, base, reg, v, mode) \

-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+#define VOP_CTRL_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
+
+#define VOP_INTR_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->intr->name)
+
+#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
+   vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)

There's really no point to this, just call vop_mask_write directly.


Got it, will fix it at next version.



+
+#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
+   do { \
+   if (VOP_REG_SUPPORT(vop, reg)) \
+   __REG_SET(vop, off + reg.offset, mask, reg.shift, \

s/mask/reg.mask & mask/


Got it, will fix it at next version.



+ v, reg.write_mask, relaxed); \
+   else \
+   dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
+   } while (0)


Also better as static inline, IMO.


Good idea, I will try it.




+
+#define REG_SET(x, name, off, reg, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask, v, relaxed)

s/reg.mask/~0/


Got it, will fix it at next version.



+#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)

s/reg.mask &//

Also, these can become static inline functions as well.


Got it, will fix it at next version.


  
  #define VOP_WIN_SET(x, win, name, v) \

-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->name, v, true)
+#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
+   REG_SET(x, name, 0, win->ext->name, v, true)
  #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->name, v, true)
  #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->ext->name, v, true)
+
  #define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  
  #define VOP_INTR_GET(vop, name) \

vop_read_reg(vop, 0, >data->ctrl->name)
  
-#define VOP_INTR_SET(vop, name, mask, v) \

-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
+#define VOP_INTR_SET(vop, name, v) \
+   REG_SET(vop, name, 0, vop->data->intr->name, \
+   v, false)
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   REG_SET_MASK(vop, n

Re: [PATCH v2 1/5] drm/rockchip: vop: get rid of register init table

2017-07-12 Thread Mark yao


On 2017年07月13日 00:47, Sean Paul wrote:

On Wed, Jul 12, 2017 at 10:03:27AM +0800, Mark Yao wrote:

Register init table use un-document define, it is unreadable,
And sometimes we only want to update tiny bits, init table
method is not friendly, it's diffcult to reuse for difference
chips.

While I'm happy to see the init_table removed, it seems like the new code is not
equivalent to the old (ie: some register writes have been dropped). How did you
ensure that you're not breaking existing boards that depend on the deleted 
register
initialization?

Sean


All the existing boards works fine on my internal kernel board with the 
init_table removed,
We had tested all the existing boards, so it's no problem to removed init_table




Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
  3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 45589d6..7a5f809 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1393,7 +1393,6 @@ static void vop_destroy_crtc(struct vop *vop)
  static int vop_initial(struct vop *vop)
  {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
  
@@ -1453,13 +1452,14 @@ static int vop_initial(struct vop *vop)
  
  	memcpy(vop->regsbak, vop->regs, vop->len);
  
-	for (i = 0; i < vop_data->table_size; i++)

-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
  
  	for (i = 0; i < vop_data->win_size; i++) {

const struct vop_win_data *win = _data->win[i];
  
  		VOP_WIN_SET(vop, win, enable, 0);

+   VOP_WIN_SET(vop, win, gate, 1);
}
  
  	vop_cfg_done(vop);

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
  };
  
-struct vop_reg_data {

-   uint32_t offset;
-   uint32_t value;
-};
-
  struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
  
  	struct vop_reg line_flag_num[2];
  
+	struct vop_reg global_regdone_en;

struct vop_reg cfg_done;
  };
  
@@ -115,6 +112,7 @@ struct vop_win_phy {

uint32_t nformats;
  
  	struct vop_reg enable;

+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
  };
  
  struct vop_data {

-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
  };
  
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {

-   {RK3036_DSP_CTRL1, 0x},
-};
-
  static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
  static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mod

Re: [PATCH v2 4/5] drm/rockchip: vop: add a series of vop support

2017-07-12 Thread Mark yao


  
  
On 2017年07月13日 02:33, Sean Paul wrote:


  On Wed, Jul 12, 2017 at 10:03:54AM +0800, Mark Yao wrote:

  
Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit

  
  
Below you say little vop is major == 2, but you have major == 3 here.


"RK3399 lit" is a full design vop framework, just cut down some
feature from rk3399 big design, so it's IP major is 3.

the little vop is rk3066, rk3188, rk3036, etc.


  


  
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 202 +--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 2 files changed, 863 insertions(+), 244 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 159cedf..b33483c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -211,6 +211,7 @@
 	.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 	.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 	.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
+	.dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
 	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
@@ -220,14 +221,19 @@
 	.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
 	.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
-	.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
+	.pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
+	.dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0xf, 16, 3, 5, -1),
+	.rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
+	.hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
+	.edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
+	.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
 	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 	.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 	.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 	.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 	.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-	.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
+	.global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 	.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),

  
  
I'm not really convinced VOP_REG_VER is a good idea. In the case of dp_en and
pin_pol, the register is already used for different offsets, so presumably
you're writing into don't care offsets?


VOP_REG_VER control when the register works.
for pin_pol, it only works on version(3.0 - 3.1),  rk3288, it's
dummy operate on other chips.
for dp_en, it works on version (3.5 - bigger), rk3399 big, rk3399
lit, rk322x, etc.
it's dummy operate on rk3288, rk3368.

Using VOP_REG means the register works on all platform,  Using
VOP_REG_VER means only can use on some platform.

So don't worry about writing wrong offsets, the register would be
dummy on un-support platform.

  

In the other cases, it just looks like a few new registers added for 3368 and
3399. In this scenario, I don't think it's that bad to just have separate
structs for each version that has distinct features. There's going to be more
duplication, but then it's super easy to understand which platform has which
registers.


separate
structs is TODO on my plan, separate with control, modesetting, etc.
but many register has no a clean group define, and need rewrite
write/read ops,
need handle conflict for each platform.

And I think  VOP_REG_VER mechanism can both works with separate
structs.





  

The whole versioning system is a little strange. For example, is each version
guaranteed to have the registered defined for the previous version (ie: 3.6
contains all registers defined for 3.5)?


Mostly, new version will contains all register of previous, if some
register only support on old version,
example, pin_pol, only support on rk3288,

Re: [PATCH 09/16] drm/rockchip: Use for_each_oldnew_plane_in_state in vop_crtc_atomic_flush

2017-07-12 Thread Mark yao


On 2017年07月12日 16:13, Maarten Lankhorst wrote:

for_each_obj_in_state is about to be removed, so use the new atomic
iterator macros.

Signed-off-by: Maarten Lankhorst<maarten.lankho...@linux.intel.com>
Cc: Mark Yao<mark@rock-chips.com>
Cc: Heiko Stuebner<he...@sntech.de>
Cc:linux-arm-ker...@lists.infradead.org
Cc:linux-rockc...@lists.infradead.org


Looks good for me:

Acked-by: Mark Yao <mark@rock-chips.com>

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[PATCH v2 4/5] drm/rockchip: vop: add a series of vop support

2017-07-11 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk3228
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 202 +--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 2 files changed, 863 insertions(+), 244 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 159cedf..b33483c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -211,6 +211,7 @@
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
+   .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
@@ -220,14 +221,19 @@
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
-   .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
+   .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
+   .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0xf, 16, 3, 5, -1),
+   .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
+   .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
+   .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
+   .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
+   .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -265,6 +271,7 @@
 };
 
 static const struct vop_data rk3288_vop = {
+   .version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_RGB10,
.intr = _vop_intr,
.ctrl = _ctrl_data,
@@ -272,33 +279,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const struct vop_ctrl rk3399_ctrl_data = {
-   .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
-   .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
-   .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
-   .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
-   .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
-   .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
-   .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
-   .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
-   .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
-   .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
-   .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
-   .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
-   .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
-   .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
-   .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
-   .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
-   .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
-   .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
-   .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
-   .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
-   .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
-};
-
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -308,54 +289,173 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop

[PATCH v2 5/5] dt-bindings: display: fill Documents for series of vop

2017-07-11 Thread Mark Yao

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..5d835d9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk3228-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
1.9.1


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[PATCH v2 2/5] drm/rockchip: vop: support verify registers with vop version

2017-07-11 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 66 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 18 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 20 ++---
 3 files changed, 77 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 7a5f809..a9180fd 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,33 +42,60 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
+#define VOP_REG_SUPPORT(vop, reg) \
+   (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
+   reg.begin_minor <= VOP_MINOR(vop->data->version) && \
+   reg.end_minor >= VOP_MINOR(vop->data->version) && \
+   reg.mask))
 
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
+#define VOP_WIN_SUPPORT(vop, win, name) \
+   VOP_REG_SUPPORT(vop, win->phy->name)
 
-#define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+#define VOP_CTRL_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
+
+#define VOP_INTR_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->intr->name)
+
+#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
+   vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
+
+#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
+   do { \
+   if (VOP_REG_SUPPORT(vop, reg)) \
+   __REG_SET(vop, off + reg.offset, mask, reg.shift, \
+ v, reg.write_mask, relaxed); \
+   else \
+   dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
+   } while (0)
+
+#define REG_SET(x, name, off, reg, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
+#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->name, v, true)
+#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
+   REG_SET(x, name, 0, win->ext->name, v, true)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->name, v, true)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->ext->name, v, true)
+
 #define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
 
 #define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, >data->ctrl->name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
+#define VOP_INTR_SET(vop, name, v) \
+   REG_SET(vop, name, 0, vop->data->intr->name, \
+   v, false)
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
+mask, v, false)
+
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -78,13 +105,16 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
 
+#define VOP_CTRL_GET(x, name) \
+   vop_read_reg(x, 0, >data->ctrl->name)
+
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #

[PATCH v2 3/5] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-11 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index a9180fd..be208ee 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -507,7 +507,7 @@ static void vop_line_flag_irq_enable(struct vop *vop, int 
line_num)
 
spin_lock_irqsave(>irq_lock, flags);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], line_num);
+   VOP_INTR_SET(vop, line_flag_num[0], line_num);
VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index e4de890..f64685e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -70,8 +70,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -79,6 +77,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7744603..159cedf 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -118,6 +118,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -131,7 +132,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -227,7 +227,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -259,6 +258,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -295,8 +295,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -313,6 +311,8 @@
 static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0x, 0),
-- 
1.9.1


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[PATCH v2 1/5] drm/rockchip: vop: get rid of register init table

2017-07-11 Thread Mark Yao

Register init table use un-document define, it is unreadable,
And sometimes we only want to update tiny bits, init table
method is not friendly, it's diffcult to reuse for difference
chips.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
 3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 45589d6..7a5f809 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1393,7 +1393,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1453,13 +1452,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -224,22 +220,10 @@
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
+   .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };

[PATCH v2 0/5] drm/rockchip: add all full framework vop support

2017-07-11 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, The newer vop design always have some different to the old one,
So we add a register verify mechanism to distinguish those register, then
the registers table can be reused.

And people can easy to know the different for the vops from register table.

Tested on rk3399 evb board.

Changes in v2:
- rename rk322x to rk3228(Heiko Stübner)
- correct some vop registers define

Mark Yao (5):
  drm/rockchip: vop: get rid of register init table
  drm/rockchip: vop: support verify registers with vop version
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: fill Documents for series of vop

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|  74 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  32 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 263 +++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 956 insertions(+), 322 deletions(-)

-- 
1.9.1


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Re: [PATCH 5/5] dt-bindings: display: fill Documents for series of vop

2017-07-11 Thread Mark yao


On 2017年07月11日 20:45, Heiko Stübner wrote:

Hi Mark,

Am Dienstag, 11. Juli 2017, 20:42:38 CEST schrieb Mark Yao:

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
  Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4
 1 file changed, 4 insertions(+)

diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index
9eb3f0a..11fa3b0 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
  - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk322x-vop";

please don't use wildcards in devicetree compatibles. We've somehow
standardized on using rk3228 for both the rk3228 and rk3229 (which are
nearly the same soc with some speed adjustments)

So,
+   "rockchip,rk3228-vop";
please


Thanks
Heiko


Got it, I will fix it at next version

Thanks
Mark




+   "rockchip,rk3328-vop";

  - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier








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[PATCH 4/5] drm/rockchip: vop: add a series of vop support

2017-07-11 Thread Mark Yao

Vop Full framework now has following vops:
IP versionchipname
  3.1   rk3288
  3.2   rk3368
  3.4   rk3366
  3.5   rk3399 big
  3.6   rk3399 lit
  3.7   rk322x
  3.8   rk3328

The above IP version is from H/W define, some of vop support get
the IP version from VERSION_INFO register, some are not.
hardcode the IP version for each vop to identify them.

major version: used for IP structure, Vop full framework is 3,
   vop little framework is 2.
minor version: on same structure, newer design vop will bigger
   then old one.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 198 --
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++--
 2 files changed, 859 insertions(+), 244 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 159cedf..c5d7c70 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -211,6 +211,7 @@
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
+   .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
@@ -221,13 +222,18 @@
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
+   .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0xf, 16, 3, 5, -1),
+   .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
+   .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
+   .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
+   .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
+   .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -272,33 +278,7 @@
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
 };
 
-static const struct vop_ctrl rk3399_ctrl_data = {
-   .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
-   .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
-   .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
-   .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
-   .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
-   .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
-   .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
-   .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
-   .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
-   .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
-   .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
-   .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
-   .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
-   .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
-   .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
-   .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
-   .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
-   .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
-   .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
-   .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
-   .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
-};
-
-static const int rk3399_vop_intrs[] = {
+static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
LINE_FLAG_INTR,
@@ -308,54 +288,170 @@
DSP_HOLD_VALID_INTR,
 };
 
-static const struct vop_intr rk3399_vop_intr = {
-   .intrs = rk3399_vop_intrs,
-   .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
-   .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0x, 0),
-   .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0x, 0),
-   .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0x, 0),
+static const struct vop_intr rk3368_vop_intr = {
+   .intrs = rk3368_vop_intrs,
+   .nintrs = ARRA

[PATCH 3/5] drm/rockchip: vop: move line_flag_num to interrupt registers

2017-07-11 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index a9180fd..be208ee 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -507,7 +507,7 @@ static void vop_line_flag_irq_enable(struct vop *vop, int 
line_num)
 
spin_lock_irqsave(>irq_lock, flags);
 
-   VOP_CTRL_SET(vop, line_flag_num[0], line_num);
+   VOP_INTR_SET(vop, line_flag_num[0], line_num);
VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index e4de890..f64685e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -70,8 +70,6 @@ struct vop_ctrl {
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
 
-   struct vop_reg line_flag_num[2];
-
struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
@@ -79,6 +77,8 @@ struct vop_ctrl {
 struct vop_intr {
const int *intrs;
uint32_t nintrs;
+
+   struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 7744603..159cedf 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -118,6 +118,7 @@
 static const struct vop_intr rk3036_intr = {
.intrs = rk3036_vop_intrs,
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
@@ -131,7 +132,6 @@
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -227,7 +227,6 @@
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };
@@ -259,6 +258,7 @@
 static const struct vop_intr rk3288_vop_intr = {
.intrs = rk3288_vop_intrs,
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
@@ -295,8 +295,6 @@
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
-   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
 };
 
@@ -313,6 +311,8 @@
 static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
+   .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0x, 0),
+   .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0x, 16),
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0x, 0),
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0x, 0),
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0x, 0),
-- 
1.9.1


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[PATCH 5/5] dt-bindings: display: fill Documents for series of vop

2017-07-11 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt 
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a..11fa3b0 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
 - compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+   "rockchip,rk3368-vop";
+   "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+   "rockchip,rk322x-vop";
+   "rockchip,rk3328-vop";
 
 - interrupts: should contain a list of all VOP IP block interrupts in the
 order: VSYNC, LCD_SYSTEM. The interrupt specifier
-- 
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[PATCH 2/5] drm/rockchip: vop: support verify registers with vop version

2017-07-11 Thread Mark Yao

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 66 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 18 ++--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 20 ++---
 3 files changed, 77 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 7a5f809..a9180fd 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -42,33 +42,60 @@
 #include "rockchip_drm_psr.h"
 #include "rockchip_drm_vop.h"
 
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, true)
+#define VOP_REG_SUPPORT(vop, reg) \
+   (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
+   reg.begin_minor <= VOP_MINOR(vop->data->version) && \
+   reg.end_minor >= VOP_MINOR(vop->data->version) && \
+   reg.mask))
 
-#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
-   vop_mask_write(x, off, mask, shift, v, write_mask, false)
+#define VOP_WIN_SUPPORT(vop, win, name) \
+   VOP_REG_SUPPORT(vop, win->phy->name)
 
-#define REG_SET(x, base, reg, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-reg.mask, reg.shift, v, reg.write_mask)
-#define REG_SET_MASK(x, base, reg, mask, v, mode) \
-   __REG_SET_##mode(x, base + reg.offset, \
-mask, reg.shift, v, reg.write_mask)
+#define VOP_CTRL_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
+
+#define VOP_INTR_SUPPORT(vop, name) \
+   VOP_REG_SUPPORT(vop, vop->data->intr->name)
+
+#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
+   vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
+
+#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
+   do { \
+   if (VOP_REG_SUPPORT(vop, reg)) \
+   __REG_SET(vop, off + reg.offset, mask, reg.shift, \
+ v, reg.write_mask, relaxed); \
+   else \
+   dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
+   } while (0)
+
+#define REG_SET(x, name, off, reg, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
+#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
+   _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
 
 #define VOP_WIN_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->name, v, true)
+#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
+   REG_SET(x, name, 0, win->ext->name, v, true)
 #define VOP_SCL_SET(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->name, v, true)
 #define VOP_SCL_SET_EXT(x, win, name, v) \
-   REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
+   REG_SET(x, name, win->base, win->phy->scl->ext->name, v, true)
+
 #define VOP_CTRL_SET(x, name, v) \
-   REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+   REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
 
 #define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, >data->ctrl->name)
 
-#define VOP_INTR_SET(vop, name, mask, v) \
-   REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
+#define VOP_INTR_SET(vop, name, v) \
+   REG_SET(vop, name, 0, vop->data->intr->name, \
+   v, false)
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+   REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
+mask, v, false)
+
 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -78,13 +105,16 @@
mask |= 1 << i; \
} \
} \
-   VOP_INTR_SET(vop, name, mask, reg); \
+   VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
 #define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, >data->intr->name, type)
 
+#define VOP_CTRL_GET(x, name) \
+   vop_read_reg(x, 0, >data->ctrl->name)
+
 #define VOP_WIN_GET(x, win, name) \
-   vop_read_reg(x, win->base, >phy->name)
+   vop_read_reg(x, win->offset, win->phy->name)
 
 #

[PATCH 0/5] drm/rockchip: add all full framework vop support

2017-07-11 Thread Mark Yao

These patches try to make all current rockchip full framework vop works
on drm, The newer vop design always have some different to the old one,
So we add a register verify mechanism to distinguish those register, then
the registers table can be reused.

And people can easy to know the different for the vops from register table.

Mark Yao (5):
  drm/rockchip: vop: get rid of register init table
  drm/rockchip: vop: support verify registers with vop version
  drm/rockchip: vop: move line_flag_num to interrupt registers
  drm/rockchip: vop: add a series of vop support
  dt-bindings: display: fill Documents for series of vop

 .../bindings/display/rockchip/rockchip-vop.txt |   4 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|  74 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h|  32 +-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 259 +++---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h| 905 -
 5 files changed, 952 insertions(+), 322 deletions(-)

-- 
1.9.1


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[PATCH 1/5] drm/rockchip: vop: get rid of register init table

2017-07-11 Thread Mark Yao

Register init table use un-document define, it is unreadable,
And sometimes we only want to update tiny bits, init table
method is not friendly, it's diffcult to reuse for difference
chips.

Signed-off-by: Mark Yao <mark@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  6 ++--
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++-
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 43 +++--
 3 files changed, 10 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 45589d6..7a5f809 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1393,7 +1393,6 @@ static void vop_destroy_crtc(struct vop *vop)
 static int vop_initial(struct vop *vop)
 {
const struct vop_data *vop_data = vop->data;
-   const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
 
@@ -1453,13 +1452,14 @@ static int vop_initial(struct vop *vop)
 
memcpy(vop->regsbak, vop->regs, vop->len);
 
-   for (i = 0; i < vop_data->table_size; i++)
-   vop_writel(vop, init_table[i].offset, init_table[i].value);
+   VOP_CTRL_SET(vop, global_regdone_en, 1);
+   VOP_CTRL_SET(vop, dsp_blank, 0);
 
for (i = 0; i < vop_data->win_size; i++) {
const struct vop_win_data *win = _data->win[i];
 
VOP_WIN_SET(vop, win, enable, 0);
+   VOP_WIN_SET(vop, win, gate, 1);
}
 
vop_cfg_done(vop);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9979fd0..084d3b2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -24,11 +24,6 @@ enum vop_data_format {
VOP_FMT_YUV444SP,
 };
 
-struct vop_reg_data {
-   uint32_t offset;
-   uint32_t value;
-};
-
 struct vop_reg {
uint32_t offset;
uint32_t shift;
@@ -46,6 +41,7 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
+   struct vop_reg dsp_blank;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@@ -65,6 +61,7 @@ struct vop_ctrl {
 
struct vop_reg line_flag_num[2];
 
+   struct vop_reg global_regdone_en;
struct vop_reg cfg_done;
 };
 
@@ -115,6 +112,7 @@ struct vop_win_phy {
uint32_t nformats;
 
struct vop_reg enable;
+   struct vop_reg gate;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
@@ -136,8 +134,6 @@ struct vop_win_data {
 };
 
 struct vop_data {
-   const struct vop_reg_data *init_table;
-   unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bafd698..00e9d79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -127,13 +127,7 @@
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
-   {RK3036_DSP_CTRL1, 0x},
-};
-
 static const struct vop_data rk3036_vop = {
-   .init_table = rk3036_vop_init_reg_table,
-   .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.ctrl = _ctrl_data,
.intr = _intr,
.win = rk3036_vop_win_data,
@@ -193,7 +187,8 @@
 static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
-   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
+   .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
+   .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
@@ -215,6 +210,7 @@
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
+   .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
@@ -224,22 +220,10 @@
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
+   .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 };

Re: [PATCH] drm/rockchip: fix NULL check on devm_kzalloc() return value

2017-07-10 Thread Mark yao


On 2017年07月11日 03:04, Sean Paul wrote:

On Fri, Jul 07, 2017 at 08:56:28AM +0800, Mark yao wrote:

On 2017年07月07日 05:58, Gustavo A. R. Silva wrote:

The right variable to check here is port, not dp.

This issue was detected using Coccinelle and the following semantic patch:

@@
expression x;
identifier fld;
@@

* x = devm_kzalloc(...);
... when != x == NULL
x->fld

Signed-off-by: Gustavo A. R. Silva <garsi...@embeddedor.com>

Thanks for the fix,

Acked-by: Mark Yao <mark@rock-chips.com>

Hi Mark,
I've applied this patch, but in the future, please apply changes directly
instead of just acking.

If you're unable to apply it for some reason (vacation, etc), please reach out 
to
one of the -misc maintainers via email or irc so we don't inadvertently lose 
track
of it on the list.

Sean

Hi Sean

Got it,  I  will do it right next time.
Thanks to inform me this,




---
   drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c 
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index 14fa1f8..9b0b058 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -1195,7 +1195,7 @@ static int cdn_dp_probe(struct platform_device *pdev)
continue;
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-   if (!dp)
+   if (!port)
return -ENOMEM;
port->extcon = extcon;


--
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Re: [PATCH] drm/rockchip: fix NULL check on devm_kzalloc() return value

2017-07-06 Thread Mark yao


On 2017年07月07日 05:58, Gustavo A. R. Silva wrote:

The right variable to check here is port, not dp.

This issue was detected using Coccinelle and the following semantic patch:

@@
expression x;
identifier fld;
@@

* x = devm_kzalloc(...);
   ... when != x == NULL
   x->fld

Signed-off-by: Gustavo A. R. Silva <garsi...@embeddedor.com>


Thanks for the fix,

Acked-by: Mark Yao <mark@rock-chips.com>


---
  drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c 
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index 14fa1f8..9b0b058 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -1195,7 +1195,7 @@ static int cdn_dp_probe(struct platform_device *pdev)
continue;
  
  		port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);

-   if (!dp)
+   if (!port)
return -ENOMEM;
  
  		port->extcon = extcon;



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