[PATCH] drm/msm: rework vblank event handling in dpu_crtc
The vblank on/off calls were missing in dpu_crtc
leading to "driver forgot to call drm_crtc_vblank_off()"
warning while entering suspend state.
Also handle the state update completion event for
a crtc being disabled in current atomic commit.
This patch depends on https://www.spinics.net/lists/dri-devel/msg182402.html
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d171282..24715e4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1617,6 +1617,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_encoder *encoder;
struct msm_drm_private *priv;
int ret;
+ unsigned long flags;
if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
DPU_ERROR("invalid crtc\n");
@@ -1632,6 +1633,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
if (dpu_kms_is_suspend_state(crtc->dev))
_dpu_crtc_set_suspend(crtc, true);
+ /* Disable/save vblank irq handling */
+ drm_crtc_vblank_off(crtc);
+
mutex_lock(_crtc->crtc_lock);
/* wait for frame_event_done completion */
@@ -1669,7 +1673,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
dpu_power_handle_unregister_event(dpu_crtc->phandle,
dpu_crtc->power_event);
-
memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
dpu_crtc->num_mixers = 0;
dpu_crtc->mixers_swapped = false;
@@ -1679,6 +1682,13 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
cstate->bw_split_vote = false;
mutex_unlock(_crtc->crtc_lock);
+
+ if (crtc->state->event && !crtc->state->active) {
+ spin_lock_irqsave(>dev->event_lock, flags);
+ drm_crtc_send_vblank_event(crtc, crtc->state->event);
+ crtc->state->event = NULL;
+ spin_unlock_irqrestore(>dev->event_lock, flags);
+ }
}
static void dpu_crtc_enable(struct drm_crtc *crtc,
@@ -1718,6 +1728,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
mutex_unlock(_crtc->crtc_lock);
+ /* Enable/restore vblank irq handling */
+ drm_crtc_vblank_on(crtc);
+
dpu_crtc->power_event = dpu_power_handle_register_event(
dpu_crtc->phandle,
DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |
--
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[PATCH] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll
postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index dbf601f..6c3ed1b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -798,6 +798,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) return ERR_PTR(-ENOMEM); } + spin_lock_init(_10nm->postdiv_lock); + pll = _10nm->base; pll->min_rate = 10UL; pll->max_rate = 35UL; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v2] drm/msm/dpu: remove msm_prop entry from Makefile
msm_prop[.ch] files were removed in prop cleanup series but its reference were left in Makefile. Remove it. Changes in v2: - removed Change-id Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 9872928..2451d50 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -76,7 +76,6 @@ msm-y := \ disp/dpu1/dpu_power_handle.o \ dpu_dbg.o \ dpu_dbg_evtlog.o \ - msm_prop.o \ msm_atomic.o \ msm_debugfs.o \ msm_drv.o \ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH] drm/msm/dpu: remove msm_prop entry from Makefile
msm_prop[.ch] files were removed in prop cleanup series but its refrence were left in Makefile. Remove it. Change-Id: I185d82423c00a2df15a1b3daa7026c3a3e10c8e6 Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 9872928..2451d50 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -76,7 +76,6 @@ msm-y := \ disp/dpu1/dpu_power_handle.o \ dpu_dbg.o \ dpu_dbg_evtlog.o \ - msm_prop.o \ msm_atomic.o \ msm_debugfs.o \ msm_drv.o \ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH 07/11] drm/msm/dpu: remove dt parsing logic for bus_scale config
Bus scale config related dt-bindings are removed.
Add bus_scale config in driver instead.
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 254 +++
1 file changed, 167 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
index bdf18de..24c3274 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
@@ -20,15 +20,137 @@
#include
#include
#include
-#ifdef CONFIG_QCOM_BUS_SCALING
-#include
-#include
-#endif
#include
#include "dpu_power_handle.h"
#include "dpu_trace.h"
+#ifdef CONFIG_QCOM_BUS_SCALING
+#include
+#include
+
+#define DPU_BUS_VECTOR_ENTRY(src_val, dst_val, ab_val, ib_val) \
+ { \
+ .src = src_val,\
+ .dst = dst_val,\
+ .ab = (ab_val),\
+ .ib = (ib_val),\
+ }
+
+static struct msm_bus_vectors dpu_reg_bus_vectors[] = {
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST,
+MSM_BUS_SLAVE_DISPLAY_CFG, 0, 0),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST,
+MSM_BUS_SLAVE_DISPLAY_CFG, 0, 7680),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST,
+MSM_BUS_SLAVE_DISPLAY_CFG, 0, 15000),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_FIRST,
+MSM_BUS_SLAVE_DISPLAY_CFG, 0, 3),
+};
+
+static struct msm_bus_paths dpu_reg_bus_usecases[] = { {
+ .num_paths = 1,
+ .vectors = _reg_bus_vectors[0],
+}, {
+ .num_paths = 1,
+ .vectors = _reg_bus_vectors[1],
+}, {
+ .num_paths = 1,
+ .vectors = _reg_bus_vectors[2],
+}, {
+ .num_paths = 1,
+ .vectors = _reg_bus_vectors[3],
+} };
+
+static struct msm_bus_scale_pdata dpu_reg_bus_scale_table = {
+ .usecase = dpu_reg_bus_usecases,
+ .num_usecases = ARRAY_SIZE(dpu_reg_bus_usecases),
+ .name = "mdss_reg",
+};
+
+static struct msm_bus_vectors dpu_data_bus_vectors[] = {
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 0),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 0),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 64),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 64),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT0,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 64),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MDP_PORT1,
+MSM_BUS_SLAVE_MNOC_HF_MEM_NOC, 0, 64),
+};
+
+static struct msm_bus_paths dpu_data_bus_usecases[] = { {
+ .num_paths = 2,
+ .vectors = _data_bus_vectors[0],
+}, {
+ .num_paths = 2,
+ .vectors = _data_bus_vectors[2],
+}, {
+ .num_paths = 2,
+ .vectors = _data_bus_vectors[4],
+} };
+
+static struct msm_bus_scale_pdata dpu_data_bus_scale_table = {
+ .usecase = dpu_data_bus_usecases,
+ .num_usecases = ARRAY_SIZE(dpu_data_bus_usecases),
+ .name = "mdss_mnoc",
+};
+
+static struct msm_bus_vectors dpu_llcc_bus_vectors[] = {
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC,
+MSM_BUS_SLAVE_LLCC, 0, 0),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC,
+MSM_BUS_SLAVE_LLCC, 0, 64),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_MNOC_HF_MEM_NOC,
+MSM_BUS_SLAVE_LLCC, 0, 64),
+};
+
+static struct msm_bus_paths dpu_llcc_bus_usecases[] = { {
+ .num_paths = 1,
+ .vectors = _llcc_bus_vectors[0],
+}, {
+ .num_paths = 1,
+ .vectors = _llcc_bus_vectors[1],
+}, {
+ .num_paths = 1,
+ .vectors = _llcc_bus_vectors[2],
+} };
+static struct msm_bus_scale_pdata dpu_llcc_bus_scale_table = {
+ .usecase = dpu_llcc_bus_usecases,
+ .num_usecases = ARRAY_SIZE(dpu_llcc_bus_usecases),
+ .name = "mdss_llcc",
+};
+
+static struct msm_bus_vectors dpu_ebi_bus_vectors[] = {
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_LLCC,
+MSM_BUS_SLAVE_EBI_CH0, 0, 0),
+ DPU_BUS_VECTOR_ENTRY(MSM_BUS_MASTER_LLCC,
+MSM_BUS_SLAVE_EBI_CH0, 0, 64)
[DPU PATCH 04/11] dt-bindings: msm/disp: remove unused writeback bindings
DPU writeback support is not enabled yet so
removing the bindings. The corresponding driver
code is also removed. The bindings will be added
back when writeback support is reworked and enabled
based on new DRM writeback connector at a later stage.
Signed-off-by: Rajesh Yadav
---
.../devicetree/bindings/drm/msm/dpu-wb.txt | 23 --
1 file changed, 23 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/drm/msm/dpu-wb.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/dpu-wb.txt
b/Documentation/devicetree/bindings/drm/msm/dpu-wb.txt
deleted file mode 100644
index 02845536..000
--- a/Documentation/devicetree/bindings/drm/msm/dpu-wb.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-QTI Snapdragon Display Engine (DPU) writeback display
-
-Required properties:
-- compatible: "qcom,wb-display"
-
-Optional properties:
-- cell-index: Index of writeback device instance.
- Default to 0 if not specified.
-- label: String to describe this writeback display.
- Default to "unknown" if not specified.
-
-Example:
-
-/ {
- ...
-
- dpu_wb: qcom,wb-display {
- compatible = "qcom,wb-display";
- cell-index = <2>;
- label = "wb_display";
- };
-
-};
--
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[DPU PATCH 01/11] dt-bindings: msm/disp: remove unused dsi & panel bindings
DPU driver switched to existing upstream dsi driver so removing the dsi-staging specific dsi and panel bindings. Signed-off-by: Rajesh Yadav --- .../devicetree/bindings/drm/msm/dpu-dsi.txt| 102 --- .../devicetree/bindings/drm/msm/mdss-dsi-panel.txt | 772 - .../devicetree/bindings/fb/mdss-dsi-panel.txt | 742 Documentation/devicetree/bindings/fb/mdss-pll.txt | 103 --- 4 files changed, 1719 deletions(-) delete mode 100644 Documentation/devicetree/bindings/drm/msm/dpu-dsi.txt delete mode 100644 Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt delete mode 100644 Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt delete mode 100644 Documentation/devicetree/bindings/fb/mdss-pll.txt diff --git a/Documentation/devicetree/bindings/drm/msm/dpu-dsi.txt b/Documentation/devicetree/bindings/drm/msm/dpu-dsi.txt deleted file mode 100644 index 641cc26..000 --- a/Documentation/devicetree/bindings/drm/msm/dpu-dsi.txt +++ /dev/null @@ -1,102 +0,0 @@ -Qualcomm Technologies, Inc. - -mdss-dsi is the master DSI device which supports multiple DSI host controllers -that are compatible with MIPI display serial interface specification. - -DSI Controller: -Required properties: -- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported - versions include 1.4, 2.0 and 2.2. - eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, - qcom,dsi-ctrl-hw-v2.2 - And for dsi phy driver: - qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, - qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, - qcom,dsi-phy-v3.0 -- reg: Base address and length of DSI controller's memory - mapped regions. -- reg-names:A list of strings that name the list of regs. - "dsi_ctrl" - DSI controller memory region. - "mmss_misc" - MMSS misc memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for DSI controller operation. -- clock-names: Names of the clocks corresponding to handles. Following - clocks are required: - "mdp_core_clk" - "iface_clk" - "core_mmss_clk" - "bus_clk" - "byte_clk" - "pixel_clk" - "core_clk" - "byte_clk_rcg" - "pixel_clk_rcg" -- gdsc-supply: phandle to gdsc regulator node. -- vdda-supply: phandle to vdda regulator node. -- vcca-supply: phandle to vcca regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing MDSS client. -- qcom,msm-bus,num-cases: This is the number of bus scaling use cases - defined in the vectors property. This must be - set to <2> for MDSS DSI driver where use-case 0 - is used to remove BW votes from the system. Use - case 1 is used to generate bandwidth requestes - when sending command packets. -- qcom,msm-bus,num-paths: This represents number of paths in each bus - scaling usecase. This value depends on number of - AXI master ports dedicated to MDSS for - particular chipset. -- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt. - DSI driver should always set average bandwidth - (ab) to 0 and always use instantaneous - bandwidth(ib) values. - -Optional properties: -- label: String to describe controller. -- qcom,platform-te-gpio: Specifies the gpio used for TE. -- qcom,dsi-display-active: Current active display -- qcom,dsi-ctrl: handle to dsi controller device -- qcom,dsi-phy: handle to dsi phy device -- qcom,dsi-manager: Specifies dsi manager is present -- qcom,dsi-display: Specifies dsi display is present -- qcom,hdmi-display: Specifies hdmi is present -- qcom,dp-display:Specified dp is present -- qcom,-supply-entries: A node that lists the elements of the supply used by the - a particular "type&
[DPU PATCH 02/11] dt-bindings: msm/disp: remove unused display port bindings
DPU display port driver is not enabled yet so removing the bindings. The driver code is also reverted. The bindings will be added back when display port driver is reworked and enabled for sdm845. Signed-off-by: Rajesh Yadav --- .../devicetree/bindings/drm/msm/dpu-dp.txt | 217 - 1 file changed, 217 deletions(-) delete mode 100644 Documentation/devicetree/bindings/drm/msm/dpu-dp.txt diff --git a/Documentation/devicetree/bindings/drm/msm/dpu-dp.txt b/Documentation/devicetree/bindings/drm/msm/dpu-dp.txt deleted file mode 100644 index 1ed2715..000 --- a/Documentation/devicetree/bindings/drm/msm/dpu-dp.txt +++ /dev/null @@ -1,217 +0,0 @@ -Qualcomm Technologies, Inc. -dpu-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. -DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". -- reg: Base address and length of DP hardware's memory mapped regions. -- reg-names:A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_phy" - DP PHY memory region. - "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. - "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. - "dp_mmss_cc" - Display Clock Control memory region. - "qfprom_physical" - QFPROM Phys memory region. - "dp_pll" - USB3 DP combo PLL memory region. - "usb3_dp_com" - USB3 DP PHY combo memory region. - "hdcp_physical" - DP HDCP memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for Display Port operation. -- clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". -- gdsc-supply: phandle to gdsc regulator node. -- vdda-1p2-supply: phandle to vdda 1.2V regulator node. -- vdda-0p9-supply: phandle to vdda 0.9V regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,aux-en-gpio:Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio:Specifies the usbplug orientation gpio. -- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first - entry in this array corresponds to the register offset -
[DPU PATCH 00/11] Remove unused code and cleanup devicetree bindings for DPU driver
This patch series aims at removing unused code from DPU driver and also cleaning up its devicetree bindings. Following functionality is removed in this series: - Removed display port driver, it will be posted back later after verification on SDM845 - Removed HDCP 1.x support, it will be posted back with display port driver - Removed writeback support, it will be added at later stage based on DRM writeback connector series Additionally, following cleanups are done: - Remove bus_scale config from devicetree and use static config in driver - Cleanup devicetree binding to model actual (tree like) HW hierarchy - Cleanup unused utility functions This series is rebased on following: 1. https://lists.freedesktop.org/archives/freedreno/2018-May/002502.html 2. https://lists.freedesktop.org/archives/freedreno/2018-May/002565.html Jordan Crouse (1): drm/msm/dpu: Remove unused code and move the header Rajesh Yadav (10): dt-bindings: msm/disp: remove unused dsi & panel bindings dt-bindings: msm/disp: remove unused display port bindings Revert "drm/msm: Add DisplayPort support" dt-bindings: msm/disp: remove unused writeback bindings drm/msm/dpu: remove writeback support drm/msm/dpu: remove hdcp support drm/msm/dpu: remove dt parsing logic for bus_scale config dt-bindings: msm/disp: cleanup bindings for Snapdragon 845 DPU drm/msm/dpu: correct dpu_io_util.h include path drm/msm/dpu: move dpu_io_util to dpu folder .../devicetree/bindings/display/msm/dpu.txt| 318 ++-- .../devicetree/bindings/drm/msm/dpu-dp.txt | 217 --- .../devicetree/bindings/drm/msm/dpu-dsi.txt| 102 -- .../devicetree/bindings/drm/msm/dpu-wb.txt | 23 - .../devicetree/bindings/drm/msm/mdss-dsi-panel.txt | 772 -- .../devicetree/bindings/fb/mdss-dsi-panel.txt | 742 - Documentation/devicetree/bindings/fb/mdss-pll.txt | 103 -- drivers/gpu/drm/msm/Makefile | 21 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 94 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|2 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 63 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 1349 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 77 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c |3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 19 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 321 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 186 --- drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c| 186 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h| 61 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|5 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|1 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 253 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h |2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 42 +- drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c | 767 -- drivers/gpu/drm/msm/disp/dpu1/dpu_wb.h | 232 --- drivers/gpu/drm/msm/dp/dp_audio.c | 806 -- drivers/gpu/drm/msm/dp/dp_audio.h | 81 - drivers/gpu/drm/msm/dp/dp_aux.c| 570 --- drivers/gpu/drm/msm/dp/dp_aux.h| 44 - drivers/gpu/drm/msm/dp/dp_catalog.c| 1320 drivers/gpu/drm/msm/dp/dp_catalog.h| 163 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 1474 -- drivers/gpu/drm/msm/dp/dp_ctrl.h | 50 - drivers/gpu/drm/msm/dp/dp_debug.c | 503 --- drivers/gpu/drm/msm/dp/dp_debug.h | 60 - drivers/gpu/drm/msm/dp/dp_display.c| 1255 drivers/gpu/drm/msm/dp/dp_display.h| 52 - drivers/gpu/drm/msm/dp/dp_drm.c| 538 --- drivers/gpu/drm/msm/dp/dp_drm.h| 96 -- drivers/gpu/drm/msm/dp/dp_hdcp2p2.c| 927 drivers/gpu/drm/msm/dp/dp_link.c | 1548 --- drivers/gpu/drm/msm/dp/dp_link.h | 184 --- drivers/gpu/drm/msm/dp/dp_panel.c | 526 --- drivers/gpu/drm/msm/dp/dp_panel.h | 115 -- drivers/gpu/drm/msm/dp/dp_parser.c | 645 drivers/gpu/drm/msm/dp/dp_parser.h | 200 --- drivers/gpu/drm/msm/dp/dp_power.c | 593 drivers/gpu/drm/msm
[DPU PATCH 11/11] drm/msm/dpu: move dpu_io_util to dpu folder
dpu_io_util is used only by dpu driver so
move it to dpu folder.
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/Makefile| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 186
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 61 +
drivers/gpu/drm/msm/dpu_io_util.c | 186
drivers/gpu/drm/msm/dpu_io_util.h | 61 -
5 files changed, 248 insertions(+), 248 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h
delete mode 100644 drivers/gpu/drm/msm/dpu_io_util.c
delete mode 100644 drivers/gpu/drm/msm/dpu_io_util.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index f4c5951..956c6c4 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -68,6 +68,7 @@ msm-y := \
disp/dpu1/dpu_hw_top.o \
disp/dpu1/dpu_hw_util.o \
disp/dpu1/dpu_hw_vbif.o \
+ disp/dpu1/dpu_io_util.o \
disp/dpu1/dpu_irq.o \
disp/dpu1/dpu_kms.o \
disp/dpu1/dpu_kms_utils.o \
@@ -77,7 +78,6 @@ msm-y := \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
- dpu_io_util.o \
dpu_dbg_evtlog.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
new file mode 100644
index 000..f7caec3
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
@@ -0,0 +1,186 @@
+/* Copyright (c) 2012-2015, 2017-2018, The Linux Foundation.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+
+#include "dpu_io_util.h"
+
+void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk)
+{
+ int i;
+
+ for (i = num_clk - 1; i >= 0; i--) {
+ if (clk_arry[i].clk)
+ clk_put(clk_arry[i].clk);
+ clk_arry[i].clk = NULL;
+ }
+}
+
+int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name);
+ rc = PTR_RET(clk_arry[i].clk);
+ if (rc) {
+ DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name, rc);
+ goto error;
+ }
+ }
+
+ return rc;
+
+error:
+ for (i--; i >= 0; i--) {
+ if (clk_arry[i].clk)
+ clk_put(clk_arry[i].clk);
+ clk_arry[i].clk = NULL;
+ }
+
+ return rc;
+}
+
+int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ if (clk_arry[i].clk) {
+ if (clk_arry[i].type != DSS_CLK_AHB) {
+ DEV_DBG("%pS->%s: '%s' rate %ld\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name,
+ clk_arry[i].rate);
+ rc = clk_set_rate(clk_arry[i].clk,
+ clk_arry[i].rate);
+ if (rc) {
+ DEV_ERR("%pS->%s: %s failed. rc=%d\n",
+ __builtin_return_address(0),
+ __func__,
+ clk_arry[i].clk_name, rc);
+ break;
+ }
+ }
+ } else {
+ DEV_ERR("%pS->%s: '%s' is not available\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+ rc = -EPERM;
+ break;
+ }
+ }
+
+ return rc;
+}
+
+int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
+{
+ int i, rc = 0;
+
+ if (enable) {
+ for (i = 0; i < num_clk; i++) {
+ DEV_DBG("%pS->%s:
[DPU PATCH 10/11] drm/msm/dpu: correct dpu_io_util.h include path
dpu_io_util.h is moved from standard include path to driver folder, correct the include path in code. Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c index 24c3274..f997bd9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "dpu_power_handle.h" #include "dpu_trace.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h index 9a6d4b9..193f468 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h @@ -21,7 +21,7 @@ #define DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 16 #define DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0 -#include +#include "dpu_io_util.h" /* event will be triggered before power handler disable */ #define DPU_POWER_EVENT_PRE_DISABLE0x1 -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH 08/11] dt-bindings: msm/disp: cleanup bindings for Snapdragon 845 DPU
SDM845 SoC has a MDSS top level wrapper which includes sub-blocks as dpu, dsi, dp, hdmi etc. But current DPU bindings are defined as if there is flat device hierarchy. The MDSS and DPU HW blocks were represented by single device and DSI, HDMI, DP etc. blocks are represented as separate independent devices. This change updates the binding as tree like hierarchy where MDSS is parent device and DPU, DSI, DP and HDMI are child devices to correctly model the HW associations. Signed-off-by: Rajesh Yadav --- .../devicetree/bindings/display/msm/dpu.txt| 318 - 1 file changed, 118 insertions(+), 200 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index 90cd3e0..a4407b8 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -1,206 +1,124 @@ Qualcomm Technologies, Inc. DPU KMS -Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user -interface to different panel interfaces. DPU driver is the core of -display subsystem which manage all data paths to different panel interfaces. - -Required properties -- compatible: Must be "qcom,dpu-kms" -- compatible: "msm-hdmi-audio-codec-rx"; -- reg: Offset and length of the register set for the device. -- reg-names : Names to refer to register sets related to this device -- clocks: List of Phandles for clock device nodes -needed by the device. -- clock-names: List of clock names needed by the device. -- mmagic-supply: Phandle for mmagic mdss supply regulator device node. -- vdd-supply: Phandle for vdd regulator device node. -- interrupt-parent: Must be core interrupt controller. -- interrupts: Interrupt associated with MDSS. -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells: Should be one. The first cell is interrupt number. -- iommus: Specifies the SID's used by this context bank. +Description: + +Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates +sub-blocks like DPU display controller, DSI and DP interfaces etc. +The DPU display controller is found in SDM845 SoC. + +MDSS: +Required properties: +- compatible: "qcom,dpu-mdss" +- reg: physical base address and length of contoller's registers. +- reg-names: register region names. The following region is required: + * "mdss_phys" +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: list of phandles for clock device nodes needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required: + * "iface" + * "bus" + * "core" +- interrupts: interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- iommus: phandle of iommu device node. +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. Optional properties: -- clock-rate: List of clock rates in Hz. -- clock-max-rate: List of maximum clock rate in Hz that this device supports. -- qcom,platform-supply-entries:A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - -- reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,dpu-dram-channels: This represents the number of channels in the - Bus memory controller. -- qcom,dpu-num-nrt-paths: Integer property represents the number of
[DPU PATCH 09/11] drm/msm/dpu: Remove unused code and move the header
From: Jordan Crouse
Remove unused code from dpu_io_util.c. The functions are only
used inside of the msm driver so remove the EXPORT_SYMBOL
tags and move the header dpu_io_util.h from include/linux.
Signed-off-by: Jordan Crouse
[rya...@codeaurora.org: rebased and removed some extra unused code]
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/dpu_io_util.c | 380 +-
drivers/gpu/drm/msm/dpu_io_util.h | 61 ++
drivers/gpu/drm/msm/msm_drv.h | 1 -
include/linux/dpu_io_util.h | 115
4 files changed, 66 insertions(+), 491 deletions(-)
create mode 100644 drivers/gpu/drm/msm/dpu_io_util.h
delete mode 100644 include/linux/dpu_io_util.h
diff --git a/drivers/gpu/drm/msm/dpu_io_util.c
b/drivers/gpu/drm/msm/dpu_io_util.c
index ecc297c..f7caec3 100644
--- a/drivers/gpu/drm/msm/dpu_io_util.c
+++ b/drivers/gpu/drm/msm/dpu_io_util.c
@@ -13,318 +13,9 @@
#include
#include
-#include
-#include
#include
-#include
-#define MAX_I2C_CMDS 16
-void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug)
-{
- u32 in_val;
-
- if (!io || !io->base) {
- DEV_ERR("%pS->%s: invalid input\n",
- __builtin_return_address(0), __func__);
- return;
- }
-
- if (offset > io->len) {
- DEV_ERR("%pS->%s: offset out of range\n",
- __builtin_return_address(0), __func__);
- return;
- }
-
- writel_relaxed(value, io->base + offset);
- if (debug) {
- in_val = readl_relaxed(io->base + offset);
- DEV_DBG("[%08x] => %08x [%08x]\n",
- (u32)(unsigned long)(io->base + offset),
- value, in_val);
- }
-} /* dss_reg_w */
-EXPORT_SYMBOL(dss_reg_w);
-
-u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug)
-{
- u32 value;
-
- if (!io || !io->base) {
- DEV_ERR("%pS->%s: invalid input\n",
- __builtin_return_address(0), __func__);
- return -EINVAL;
- }
-
- if (offset > io->len) {
- DEV_ERR("%pS->%s: offset out of range\n",
- __builtin_return_address(0), __func__);
- return -EINVAL;
- }
-
- value = readl_relaxed(io->base + offset);
- if (debug)
- DEV_DBG("[%08x] <= %08x\n",
- (u32)(unsigned long)(io->base + offset), value);
-
- return value;
-} /* dss_reg_r */
-EXPORT_SYMBOL(dss_reg_r);
-
-void dss_reg_dump(void __iomem *base, u32 length, const char *prefix,
- u32 debug)
-{
- if (debug)
- print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
- (void *)base, length, false);
-} /* dss_reg_dump */
-EXPORT_SYMBOL(dss_reg_dump);
-
-static struct resource *msm_dss_get_res_byname(struct platform_device *pdev,
- unsigned int type, const char *name)
-{
- struct resource *res = NULL;
-
- res = platform_get_resource_byname(pdev, type, name);
- if (!res)
- DEV_ERR("%s: '%s' resource not found\n", __func__, name);
-
- return res;
-} /* msm_dss_get_res_byname */
-EXPORT_SYMBOL(msm_dss_get_res_byname);
-
-int msm_dss_ioremap_byname(struct platform_device *pdev,
- struct dss_io_data *io_data, const char *name)
-{
- struct resource *res = NULL;
-
- if (!pdev || !io_data) {
- DEV_ERR("%pS->%s: invalid input\n",
- __builtin_return_address(0), __func__);
- return -EINVAL;
- }
-
- res = msm_dss_get_res_byname(pdev, IORESOURCE_MEM, name);
- if (!res) {
- DEV_ERR("%pS->%s: '%s' msm_dss_get_res_byname failed\n",
- __builtin_return_address(0), __func__, name);
- return -ENODEV;
- }
-
- io_data->len = (u32)resource_size(res);
- io_data->base = ioremap(res->start, io_data->len);
- if (!io_data->base) {
- DEV_ERR("%pS->%s: '%s' ioremap failed\n",
- __builtin_return_address(0), __func__, name);
- return -EIO;
- }
-
- return 0;
-} /* msm_dss_ioremap_byname */
-EXPORT_SYMBOL(msm_dss_ioremap_byname);
-
-void msm_dss_iounmap(struct dss_io_data *io_data)
-{
- if (!io_data) {
- DEV_ERR("%pS->%s: invalid input\n",
- __builtin_return_address(0), __func__);
- return;
- }
-
- if (io_data->base) {
- iounmap(io_data->base);
- io_data->base = NULL;
- }
- io_data->len = 0;
-} /* msm_dss_iounmap */
-EXPORT_SYMBOL(msm_dss_iounmap);
-
-int msm_dss_config_vreg(struct device *dev, s
[DPU PATCH 06/11] drm/msm/dpu: remove hdcp support
Remove hdcp 1.x support from dpu driver.
The hdcp 1.x support will be posted back with
display port driver.
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/dpu_hdcp.h| 74 --
drivers/gpu/drm/msm/dpu_hdcp_1x.c | 1579 -
2 files changed, 1653 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dpu_hdcp.h
delete mode 100644 drivers/gpu/drm/msm/dpu_hdcp_1x.c
diff --git a/drivers/gpu/drm/msm/dpu_hdcp.h b/drivers/gpu/drm/msm/dpu_hdcp.h
deleted file mode 100644
index 63a98ca..000
--- a/drivers/gpu/drm/msm/dpu_hdcp.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright (c) 2012, 2014-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DPU_HDCP_H__
-#define __DPU_HDCP_H__
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "dpu_kms.h"
-
-enum dpu_hdcp_client_id {
- HDCP_CLIENT_HDMI,
- HDCP_CLIENT_DP,
-};
-
-enum dpu_hdcp_states {
- HDCP_STATE_INACTIVE,
- HDCP_STATE_AUTHENTICATING,
- HDCP_STATE_AUTHENTICATED,
- HDCP_STATE_AUTH_FAIL,
- HDCP_STATE_AUTH_ENC_NONE,
- HDCP_STATE_AUTH_ENC_1X,
- HDCP_STATE_AUTH_ENC_2P2
-};
-
-struct dpu_hdcp_init_data {
- struct dss_io_data *core_io;
- struct dss_io_data *qfprom_io;
- struct dss_io_data *hdcp_io;
- struct drm_dp_aux *drm_aux;
- struct mutex *mutex;
- struct workqueue_struct *workq;
- void *cb_data;
- void (*notify_status)(void *cb_data, enum dpu_hdcp_states status);
- u8 sink_rx_status;
- unsigned char *revision;
- u32 phy_addr;
- bool sec_access;
- enum dpu_hdcp_client_id client_id;
-};
-
-struct dpu_hdcp_ops {
- int (*isr)(void *ptr);
- int (*cp_irq)(void *ptr);
- int (*reauthenticate)(void *input);
- int (*authenticate)(void *hdcp_ctrl);
- bool (*feature_supported)(void *input);
- void (*off)(void *hdcp_ctrl);
-};
-
-void *dpu_hdcp_1x_init(struct dpu_hdcp_init_data *init_data);
-void dpu_hdcp_1x_deinit(void *input);
-struct dpu_hdcp_ops *dpu_hdcp_1x_start(void *input);
-void *dpu_dp_hdcp2p2_init(struct dpu_hdcp_init_data *init_data);
-void dpu_dp_hdcp2p2_deinit(void *input);
-const char *dpu_hdcp_state_name(enum dpu_hdcp_states hdcp_state);
-struct dpu_hdcp_ops *dpu_dp_hdcp2p2_start(void *input);
-#endif /* __DPU_HDCP_H__ */
diff --git a/drivers/gpu/drm/msm/dpu_hdcp_1x.c
b/drivers/gpu/drm/msm/dpu_hdcp_1x.c
deleted file mode 100644
index ebbd591..000
--- a/drivers/gpu/drm/msm/dpu_hdcp_1x.c
+++ /dev/null
@@ -1,1579 +0,0 @@
-/* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt)"[dpu-hdcp1x] %s: " fmt, __func__
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "dpu_hdcp.h"
-#include "hdmi.xml.h"
-#include "video/msm_hdmi_hdcp_mgr.h"
-#include "dp/dp_reg.h"
-
-#define DPU_HDCP_STATE_NAME (dpu_hdcp_state_name(hdcp->hdcp_state))
-
-/* QFPROM Registers for HDMI/HDCP */
-#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB (0x00F8)
-#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB (0x00FC)
-#define QFPROM_RAW_VERSION_4 (0x00A8)
-#define SEC_CTRL_HW_VERSION (0x6000)
-#define HDCP_KSV_LSB (0x60D8)
-#define HDCP_KSV_MSB (0x60DC)
-#define HDCP_KSV_VERSION_4_OFFSET(0x0014)
-
-/* SEC_CTRL version that supports HDCP SEL */
-#define HDCP_SEL_MIN_SEC_VERSION (0x5001)
-
-/* HDCP Keys state based on HDMI_HDCP_LINK0_STATUS:KEYS_STATE */
-#define HDCP_KEYS_STATE_NO_KEYS0
-#define HDCP_KEYS_STATE_NOT_CHECKED1
-#define HDCP_KEYS_STATE_CHECKING 2
-#define HDCP_KEYS_STATE_VALID 3
-#define HDCP_KEYS_STATE_AKSV_NOT_VALID 4
-#define HDCP_KEYS_STATE_CHKSUM_MISMATCH5
-#define HDCP_KEYS_STATE_PROD_AKSV 6
-#define HDCP_KEYS_STATE_RESERVED 7
-
-#define TZ_HDCP_CMD_ID 0x4401
-
-#
[DPU PATCH 05/11] drm/msm/dpu: remove writeback support
Remove writeback support from dpu driver
as it is not enabled.
Writeback support will be added back later
based on DRM writeback connector.
Signed-off-by: Rajesh Yadav
---
drivers/gpu/drm/msm/Makefile |5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 94 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 63 -
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 1349
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 41 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 77 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c |3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 19 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |6 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |4 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 321 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 186 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 42 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c | 767 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_wb.h | 232
21 files changed, 23 insertions(+), 3211 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7fc3974..f4c5951 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -68,7 +68,6 @@ msm-y := \
disp/dpu1/dpu_hw_top.o \
disp/dpu1/dpu_hw_util.o \
disp/dpu1/dpu_hw_vbif.o \
- disp/dpu1/dpu_hw_wb.o \
disp/dpu1/dpu_irq.o \
disp/dpu1/dpu_kms.o \
disp/dpu1/dpu_kms_utils.o \
@@ -99,9 +98,6 @@ msm-y := \
msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o
-msm_wb-$(CONFIG_DRM_MSM_WRITEBACK) += disp/dpu1/dpu_wb.o \
- disp/dpu1/dpu_encoder_phys_wb.o
-
msm-$(CONFIG_DRM_MSM_ROTATOR) += disp/dpu1/dpu_hw_rot.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
@@ -134,4 +130,3 @@ msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
endif
obj-$(CONFIG_DRM_MSM) += msm.o
-obj-$(CONFIG_DRM_MSM_WRITEBACK) += msm_wb.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 0f3aa60..39def93 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -440,8 +440,7 @@ static inline enum dpu_crtc_client_type
dpu_crtc_get_client_type(
if (!cstate)
return NRT_CLIENT;
- return dpu_crtc_get_intf_mode(crtc) == INTF_MODE_WB_LINE ? NRT_CLIENT :
- RT_CLIENT;
+ return RT_CLIENT;
}
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1d45c8f..7dd609c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1405,15 +1405,6 @@ static enum dpu_intf dpu_encoder_get_intf(struct
dpu_mdss_cfg *catalog,
return INTF_MAX;
}
-static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
- enum dpu_intf_type type, u32 controller_id)
-{
- if (controller_id < catalog->wb_count)
- return catalog->wb[controller_id].id;
-
- return WB_MAX;
-}
-
static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
struct dpu_encoder_phys *phy_enc)
{
@@ -2144,12 +2135,6 @@ static int _dpu_encoder_status_show(struct seq_file *s,
void *data)
case INTF_MODE_CMD:
seq_puts(s, "mode: command\n");
break;
- case INTF_MODE_WB_BLOCK:
- seq_puts(s, "mode: wb block\n");
- break;
- case INTF_MODE_WB_LINE:
- seq_puts(s, "mode: wb line\n");
- break;
default:
seq_puts(s, "mode: ???\n");
break;
@@ -2409,39 +2394,6 @@ static int dpu_encoder_virt_add_phys_encs(
return 0;
}
-static int dpu_encoder_virt_add_phys_enc_wb(struct dpu_encoder_virt *dpu_enc,
- struct dpu_enc_phys_init_params *params)
-{
-#ifdef CONFIG_DRM_MSM_WRITEBACK
- struct dpu_encoder_phys *enc = NULL;
-
[DPU PATCH v3 03/12] drm/msm/dpu: add MDSS top level driver for dpu
SoCs containing dpu have a MDSS top level wrapper which includes sub-blocks as dpu, dsi, phy, dp etc. MDSS top level wrapper manages common resources like common clocks, power and irq for its sub-blocks. Currently, in dpu driver, all the power resource management is part of power_handle which manages these resources via a custom implementation. And the resource relationships are not modelled properly in dt. Moreover the irq domain handling code is part of dpu device (which is a child device) due to lack of a dedicated driver for MDSS top level wrapper device. This change adds dpu_mdss top level driver to handle common clock like - core clock, ahb clock (for register access), main power supply (i.e. gdsc) and irq management. The top level mdss device/driver acts as an interrupt controller and manage hwirq mapping for its child devices. It implements runtime_pm support for resource management. Child nodes can control these resources via runtime_pm get/put calls on their corresponding devices due to parent child relationship defined in dt. Changes in v3: - use "clock-frequency" dt-binding instead of "clock-rate", is it an optional binding (Sean Paul) - remove handling of "clock-max-rate" proprietary dt-binding (Sean Paul) - remove intermediate storing of msm_ioremap() retcode on failure instead return retcode directly (Sean Paul) - msm_ioremap() prints error log in case of failure, so remove additional log from it's caller - updated max core clock rate - dropped (Reviewed-by: Jordan Crouse) due to above changes Changes in v2: - merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul) - merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul) - fix indentation for irq_find_mapping call (Sean Paul) - remove unnecessary goto statements from dpu_mdss_irq (Sean Paul) - remove redundant param checks from dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse) - remove redundant param checks from dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse) - return error code from dpu_mdss_enable/disable (Sean Paul/Jordan Crouse) - remove redundant param check from dpu_mdss_destroy (Sean Paul) - remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse) - remove compatibility check from dpu_mdss_init as it is conditionally called from msm_drv (Sean Paul) - reworked msm_dss_parse_clock() to add return checks for of_property_read_* calls, fix log message and fix alignment issues (Sean Paul/Jordan Crouse) - remove extra line before dpu_mdss_init (Sean Paul) - remove redundant param checks from __intr_offset and make it a void function to avoid unnecessary error handling from caller (Jordan Crouse) - remove redundant param check from dpu_mdss_irq (Jordan Crouse) - change mdss address space log message to debug and use %pK for kernel pointers (Jordan Crouse) - remove unnecessary log message from msm_dss_parse_clock (Jordan Crouse) - don't export msm_dss_parse_clock since it is used only by dpu driver (Jordan Crouse) Signed-off-by: Rajesh Yadav <rya...@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 97 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 -- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 9 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 28 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 251 ++ drivers/gpu/drm/msm/dpu_io_util.c | 49 + drivers/gpu/drm/msm/msm_drv.c | 26 ++- drivers/gpu/drm/msm/msm_drv.h | 2 +- drivers/gpu/drm/msm/msm_kms.h | 1 + include/linux/dpu_io_util.h | 2 + 17 files changed, 329 insertions(+), 227 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index d7558ed..d9826c1 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -81,6 +81,7 @@ msm-y := \ disp/dpu1/dpu_reg_dma.o \ disp/dpu1/dpu_rm.o \ disp/dpu1/dpu_vbif.o \ + disp/dpu1/dpu_mdss.o \ dpu_dbg.o \ dpu_io_util.o \ dpu_dbg_evtlog.o \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/dr
[DPU PATCH v3 07/12] drm/msm/dpu: remove clock management code from dpu_power_handle
MDSS and dpu drivers manage their respective clocks via
runtime_pm. Remove custom clock management code from
dpu_power_handle.
Also dpu core clock management code is restricted to
dpu_core_perf module.
Changes in v3:
- none
Changes in v2:
- remove local variable to hold and return error code
in _dpu_core_perf_set_core_clk_rate() instead return
retcode directly from msm_dss_clk_set_rate() call (Sean Paul)
- dpu_core_perf_init() is called from dpu_kms_hw_init() and
most of the params passed are already validated so remove
redundant checks from dpu_core_perf_init() (Sean Paul)
- return >clk_config[i] directly to avoid local variable
in _dpu_kms_get_clk() (Sean Paul)
- invert conditional check to eliminate local rate variable
from dpu_kms_get_clk_rate() (Sean Paul)
- remove end label from dpu_power_resource_init() and return
directly on dpu_power_parse_dt_supply() failure as no cleanup
is needed (Sean Paul)
- remove checks for vtotal and vrefresh from
dpu_encoder_phys_cmd_tearcheck_config() as they should be
valid in mode_set call (Sean Paul)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 41 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 28 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 9 +
drivers/gpu/drm/msm/dpu_power_handle.c | 196 +
drivers/gpu/drm/msm/dpu_power_handle.h | 40 -
7 files changed, 63 insertions(+), 268 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 981f77f..5b79077 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -365,6 +365,17 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
}
}
+static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
+{
+ struct dss_clk *core_clk = kms->perf.core_clk;
+
+ if (core_clk->max_rate && (rate > core_clk->max_rate))
+ rate = core_clk->max_rate;
+
+ core_clk->rate = rate;
+ return msm_dss_clk_set_rate(core_clk, 1);
+}
+
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
{
u64 clk_rate = kms->perf.perf_tune.min_core_clk;
@@ -376,7 +387,8 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms
*kms)
dpu_cstate = to_dpu_crtc_state(crtc->state);
clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
clk_rate);
- clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
+ clk_rate = clk_round_rate(kms->perf.core_clk->clk,
+ clk_rate);
}
}
@@ -484,15 +496,11 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- /* Temp change to avoid crash in clk_set_rate API. */
-#ifdef QCOM_DPU_SET_CLK
- if (dpu_power_clk_set_rate(>phandle,
- kms->perf.clk_name, clk_rate)) {
+ if (_dpu_core_perf_set_core_clk_rate(kms, clk_rate)) {
DPU_ERROR("failed to set %s clock rate %llu\n",
- kms->perf.clk_name, clk_rate);
+ kms->perf.core_clk->clk_name, clk_rate);
return;
}
-#endif
kms->perf.core_clk_rate = clk_rate;
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
@@ -656,7 +664,6 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
dpu_core_perf_debugfs_destroy(perf);
perf->max_core_clk_rate = 0;
perf->core_clk = NULL;
- perf->clk_name = NULL;
perf->phandle = NULL;
perf->catalog = NULL;
perf->dev = NULL;
@@ -667,9 +674,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
struct dpu_power_client *pclient,
- char *clk_name)
+ struct dss_clk *core_clk)
{
- if (!perf || !dev || !catalog || !phandle || !pclient || !clk_name) {
+ if (!pclient) {
DPU_ERROR("invalid parameters\n");
return -EINVAL;
}
@@ -678,23 +685,13 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
[DPU PATCH v3 04/12] drm/msm/dpu: create new platform driver for dpu device
Current MSM display controller HW matches a tree like
hierarchy where MDSS top level wrapper is parent device
and mdp5/dpu, dsi, dp are child devices.
Each child device like mdp5, dsi etc. have a separate driver,
but currently dpu handling is tied to a single driver which
was managing both mdss and dpu resources.
Inorder to have the cleaner one to one device and driver
association, this change adds a new platform_driver for dpu
child device node which implements the kms functionality.
The dpu driver implements runtime_pm support for managing clocks
and bus bandwidth etc.
Changes in v3:
- none
Changes in v2:
- remove redundant param check from _dpu_kms_hw_destroy (Sean Paul)
- remove explicit calls to devm_kfree (Sean Paul)
- merge dpu_init into dpu_bind (Sean Paul)
- merge dpu_destroy into dpu_unbind (Sean Paul)
- use %pK for kernel pointer printing (Jordan Crouse)
- remove explicit devm allocation failure message (Jordan Crouse)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Jordan Crouse <jcro...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 238 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 +
drivers/gpu/drm/msm/msm_drv.c | 2 +
drivers/gpu/drm/msm/msm_drv.h | 3 +
4 files changed, 196 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e4ab753..85f3dbc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1030,16 +1030,12 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms,
unsigned long rate,
return rate;
}
-static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
- struct platform_device *pdev)
+static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
{
struct drm_device *dev;
struct msm_drm_private *priv;
int i;
- if (!dpu_kms || !pdev)
- return;
-
dev = dpu_kms->dev;
if (!dev)
return;
@@ -1091,15 +1087,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
dpu_kms->core_client = NULL;
if (dpu_kms->vbif[VBIF_NRT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_NRT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
dpu_kms->vbif[VBIF_NRT] = NULL;
if (dpu_kms->vbif[VBIF_RT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_RT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
if (dpu_kms->mmio)
- msm_iounmap(pdev, dpu_kms->mmio);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
dpu_reg_dma_deinit();
@@ -1172,8 +1168,6 @@ int dpu_kms_mmu_attach(struct dpu_kms *dpu_kms, bool
secure_only)
static void dpu_kms_destroy(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms;
- struct drm_device *dev;
- struct platform_device *platformdev;
if (!kms) {
DPU_ERROR("invalid kms\n");
@@ -1181,20 +1175,7 @@ static void dpu_kms_destroy(struct msm_kms *kms)
}
dpu_kms = to_dpu_kms(kms);
- dev = dpu_kms->dev;
- if (!dev) {
- DPU_ERROR("invalid device\n");
- return;
- }
-
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- return;
- }
-
- _dpu_kms_hw_destroy(dpu_kms, platformdev);
- kfree(dpu_kms);
+ _dpu_kms_hw_destroy(dpu_kms);
}
static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
@@ -1550,7 +1531,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
struct dpu_kms *dpu_kms;
struct drm_device *dev;
struct msm_drm_private *priv;
- struct platform_device *platformdev;
int i, rc = -EINVAL;
if (!kms) {
@@ -1565,34 +1545,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto end;
}
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- goto end;
- }
-
priv = dev->dev_private;
if (!priv) {
DPU_ERROR("invalid private data\n");
goto end;
}
- dpu_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
+ dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys");
if (IS_ERR(dpu_kms->mmio)) {
rc = PTR_ERR(dpu_kms->mmio);
DPU_ERROR("mdp registe
[DPU PATCH v3 12/12] drm/msm/dpu: add error handling in dpu_core_perf_crtc_update
dpu_core_perf_crtc_update() is responsible for aggregating
the data bus bandwidth and dpu core clock rate requirements
and request the same for all active crtcs.
Currently, there is no error handling support in this function
so there is no way caller can know if the perf request fails.
This change adds error handling code in dpu_core_perf_crtc_update().
The caller side error handling is not added in this patch.
Changes in v3:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 37 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 3 ++-
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index d3a1ed9..85c0229 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -248,7 +248,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
return 0;
}
-static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
+static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
struct drm_crtc *crtc, u32 bus_id)
{
u64 bw_sum_of_intfs = 0, bus_ab_quota, bus_ib_quota;
@@ -257,6 +257,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
= dpu_crtc_get_client_type(crtc);
struct drm_crtc *tmp_crtc;
struct dpu_crtc_state *dpu_cstate;
+ int ret = 0;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
@@ -286,25 +287,28 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
switch (curr_client_type) {
case NRT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ ret = dpu_power_data_bus_set_quota(
+ >phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
- bus_id, bus_ab_quota, bus_ib_quota);
+ bus_id, bus_ab_quota, bus_ib_quota);
break;
case RT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ ret = dpu_power_data_bus_set_quota(
+ >phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
- bus_id, bus_ab_quota, bus_ib_quota);
+ bus_id, bus_ab_quota, bus_ib_quota);
break;
default:
DPU_ERROR("invalid client type:%d\n", curr_client_type);
break;
}
+ return ret;
}
/**
@@ -399,7 +403,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms
*kms)
return clk_rate;
}
-void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
+int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
int params_changed, bool stop_req)
{
struct dpu_core_perf_params *new, *old;
@@ -410,16 +414,17 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
int i;
struct msm_drm_private *priv;
struct dpu_kms *kms;
+ int ret;
if (!crtc) {
DPU_ERROR("invalid crtc\n");
- return;
+ return -EINVAL;
}
kms = _dpu_crtc_get_kms(crtc);
if (!kms || !kms->catalog) {
DPU_ERROR("invalid kms\n");
- return;
+ return -EINVAL;
}
priv = kms->dev->dev_private;
@@ -482,8 +487,14 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
update_bus, update_clk);
for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- if (update_bus & BIT(i))
- _dpu_core_perf_crtc_update_bus(kms, crtc, i);
+ if (update_bus & BIT(i)) {
+ ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i);
+ if (ret) {
+ DPU_ERROR("crtc-%d: failed to update bw vote
for bus-%d\n",
+ crtc->base.id, i);
+ return ret;
+ }
+ }
}
/*
@@ -495,15 +506,17 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req,
[DPU PATCH v3 10/12] drm/msm/dpu: use runtime_pm calls in dpu_dbg
Currently, msm_drv was creating dpu_power_handle client
which was used by dpu_dbg module to enable power resources
before register debug dumping.
Now since, the mdss core power resource handling is
implemented via runtime_pm and same has been removed
from dpu_power_handle. Remove dpu_power_handle dependency
from msm_drv and use pm_runtime_get/put_sync calls from
dpu_dbg module on dpu_mdss top level device for core,
ahb clock and power resource management (for register access).
Changes in v3:
- none
Changes in v2:
- resolved conflict in dpu_core_perf_init
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/dpu_dbg.c | 18 +++---
drivers/gpu/drm/msm/dpu_dbg.h | 13 ++---
drivers/gpu/drm/msm/msm_drv.c | 27 +--
drivers/gpu/drm/msm/msm_drv.h | 1 -
7 files changed, 11 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 5b79077..2cf3fca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -673,18 +673,11 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk)
{
- if (!pclient) {
- DPU_ERROR("invalid parameters\n");
- return -EINVAL;
- }
-
perf->dev = dev;
perf->catalog = catalog;
perf->phandle = phandle;
- perf->pclient = pclient;
perf->core_clk = core_clk;
perf->max_core_clk_rate = core_clk->max_rate;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 015b5f0..5198e3c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
@@ -53,7 +53,6 @@ struct dpu_core_perf_tune {
* @debugfs_root: top level debug folder
* @catalog: Pointer to catalog configuration
* @phandle: Pointer to power handler
- * @pclient: Pointer to power client
* @core_clk: Pointer to core clock structure
* @core_clk_rate: current core clock rate
* @max_core_clk_rate: maximum allowable core clock rate
@@ -68,7 +67,6 @@ struct dpu_core_perf {
struct dentry *debugfs_root;
struct dpu_mdss_cfg *catalog;
struct dpu_power_handle *phandle;
- struct dpu_power_client *pclient;
struct dss_clk *core_clk;
u64 core_clk_rate;
u64 max_core_clk_rate;
@@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
* @dev: Pointer to drm device
* @catalog: Pointer to catalog
* @phandle: Pointer to power handle
- * @pclient: Pointer to power client
* @core_clk: pointer to core clock
*/
int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk);
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 349bda5..9c3b220 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1721,8 +1721,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
#endif
rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
- >phandle, priv->pclient,
- _dpu_kms_get_clk(dpu_kms, "core_clk"));
+ >phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
if (rc) {
DPU_ERROR("failed to init perf %d\n", rc);
goto perf_err;
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 4a39b82..27538bc 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "dpu_dbg.h"
#include "disp/dpu1/dpu_hw_catalog.h"
@@ -167,7 +168,6 @@ struct dpu_dbg_vbif_debug_bus {
* @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @power_ctrl: callback structure for enabling power for reading hw registers
* @req_dump_blks: list of blocks requested for dumping
* @panic_on_err: whether to kernel panic after triggerin
[DPU PATCH v3 02/12] drm/msm/mdp5: subclass msm_mdss for mdp5
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Changes in v3:
- none
Changes in v2:
- fixed indentation for irq_domain_add_linear call (Sean Paul)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
drivers/gpu/drm/msm/msm_drv.c | 23 +++--
drivers/gpu/drm/msm/msm_kms.h | 20 ++--
3 files changed, 110 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7..1cc4e57 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
#include "msm_drv.h"
#include "mdp5_kms.h"
-/*
- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
- struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+ struct msm_mdss base;
void __iomem *mmio, *vbif;
@@ -41,22 +39,22 @@ struct msm_mdss {
} irqcontroller;
};
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
{
- msm_writel(data, mdss->mmio + reg);
+ msm_writel(data, mdp5_mdss->mmio + reg);
}
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
{
- return msm_readl(mdss->mmio + reg);
+ return msm_readl(mdp5_mdss->mmio + reg);
}
static irqreturn_t mdss_irq(int irq, void *arg)
{
- struct msm_mdss *mdss = arg;
+ struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
- intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
+ intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
VERB("intr=%08x", intr);
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
- mdss->irqcontroller.domain, hwirq));
+ mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
static void mdss_hw_mask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
static void mdss_hw_unmask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
@@ -109,13 +107,13 @@ static void mdss_hw_unmask_irq(struct irq_data *irqd)
static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- struct msm_mdss *mdss = d->host_data;
+ struct mdp5_mdss *mdp5_mdss = d->host_data;
if (!(VALID_IRQS & (1 << hwirq)))
return -EPERM;
irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, mdss);
+ irq_set_chip_data(irq, mdp5_mdss);
return 0;
}
@@ -126,90 +124,99 @@ static int mdss_hw_irqdomain_map(struct irq_domain *d,
unsigned int irq,
};
-static int mdss_irq_domain_init(struct msm_mdss *mdss)
+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
{
- struct device *dev = mdss->dev->dev;
+ struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,
- mdss);
+ mdp5_mdss);
if (!d) {
dev_err(dev, "mdss irq domain add failed\n");
return -ENXIO;
}
[DPU PATCH v3 11/12] drm/msm/dpu: move dpu_power_handle to dpu folder
Now, since dpu_power_handle manages only bus scaling
and power enable/disable notifications which are restricted
to dpu driver, move dpu_power_handle to dpu folder.
Changes in v3:
- none
Changes in v2:
- resolved conflict in dpu_unbind
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 39 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 688 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++
drivers/gpu/drm/msm/dpu_power_handle.c | 688 ---
drivers/gpu/drm/msm/dpu_power_handle.h | 288 --
drivers/gpu/drm/msm/msm_drv.c| 9 -
drivers/gpu/drm/msm/msm_drv.h| 4 -
14 files changed, 1008 insertions(+), 1015 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d9826c1..f578d5a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -82,10 +82,10 @@ msm-y := \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
+ disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
dpu_io_util.o \
dpu_dbg_evtlog.o \
- dpu_power_handle.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 5c5cc56..33ab2ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,7 +18,6 @@
#include
#include "dpu_core_irq.h"
-#include "dpu_power_handle.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 2cf3fca..d3a1ed9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -257,7 +257,6 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
= dpu_crtc_get_client_type(crtc);
struct drm_crtc *tmp_crtc;
struct dpu_crtc_state *dpu_cstate;
- struct msm_drm_private *priv = kms->dev->dev_private;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
@@ -287,7 +286,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
switch (curr_client_type) {
case NRT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
@@ -295,7 +294,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
break;
case RT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e2d2e32..99c5e75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -598,6 +598,7 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
_dpu_crtc_destroy_dest_scaler(dpu_crtc);
_dpu_crtc_deinit_events(dpu_crtc);
+ dpu_crtc->phandle = NULL;
drm_crtc_cleanup(crtc);
mutex_destroy(_crtc->crtc_lock);
@@ -2572,7 +2573,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
}
if (dpu_crtc->power_event)
- dpu_power_handle_unregister_event(>phandle,
+ dpu_po
[DPU PATCH v3 09/12] drm/msm/dp: remove dpu_power_handle calls from dp driver
DP driver was dependent on dpu_power_handle for MDSS
common clocks and gdsc (main power supply).
The common clocks and power is managed by MDSS top
wrapper device now which is parent of all sub-devices
like DP device.
For same reason, clock and power management code is
removed from dpu_power_handle. Hence, remove the
dpu_power_handle calls from dp driver.
Changes in v3:
- none
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/dp/dp_power.c | 32 +---
drivers/gpu/drm/msm/dp/dp_power.h | 4 +---
2 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index f6e341b..2a85b38 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -26,8 +26,6 @@ struct dp_power_private {
struct clk *pixel_parent;
struct dp_power dp_power;
- struct dpu_power_client *dp_core_client;
- struct dpu_power_handle *phandle;
bool core_clks_on;
bool link_clks_on;
@@ -410,8 +408,7 @@ static int dp_power_config_gpios(struct dp_power_private
*power, bool flip,
return 0;
}
-static int dp_power_client_init(struct dp_power *dp_power,
- struct dpu_power_handle *phandle)
+static int dp_power_client_init(struct dp_power *dp_power)
{
int rc = 0;
struct dp_power_private *power;
@@ -436,19 +433,8 @@ static int dp_power_client_init(struct dp_power *dp_power,
goto error_clk;
}
- power->phandle = phandle;
- snprintf(dp_client_name, DP_CLIENT_NAME_SIZE, "dp_core_client");
- power->dp_core_client = dpu_power_client_create(phandle,
- dp_client_name);
- if (IS_ERR_OR_NULL(power->dp_core_client)) {
- pr_err("[%s] client creation failed for DP", dp_client_name);
- rc = -EINVAL;
- goto error_client;
- }
return 0;
-error_client:
- dp_power_clk_init(power, false);
error_clk:
dp_power_regulator_deinit(power);
error_power:
@@ -466,7 +452,6 @@ static void dp_power_client_deinit(struct dp_power
*dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
- dpu_power_client_destroy(power->phandle, power->dp_core_client);
dp_power_clk_init(power, false);
dp_power_regulator_deinit(power);
}
@@ -521,13 +506,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
goto err_gpio;
}
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, true);
- if (rc) {
- pr_err("Power resource enable failed\n");
- goto err_dpu_power;
- }
-
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
if (rc) {
pr_err("failed to enable DP core clocks\n");
@@ -537,8 +515,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
return 0;
err_clk:
- dpu_power_resource_enable(power->phandle, power->dp_core_client, false);
-err_dpu_power:
dp_power_config_gpios(power, flip, false);
err_gpio:
dp_power_pinctrl_set(power, false);
@@ -562,12 +538,6 @@ static int dp_power_deinit(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, false);
- if (rc) {
- pr_err("Power resource enable failed, rc=%d\n", rc);
- goto exit;
- }
dp_power_config_gpios(power, false, false);
dp_power_pinctrl_set(power, false);
dp_power_regulator_ctrl(power, false);
diff --git a/drivers/gpu/drm/msm/dp/dp_power.h
b/drivers/gpu/drm/msm/dp/dp_power.h
index 84fe01d..d9dab72 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.h
+++ b/drivers/gpu/drm/msm/dp/dp_power.h
@@ -16,7 +16,6 @@
#define _DP_POWER_H_
#include "dp_parser.h"
-#include "dpu_power_handle.h"
/**
* sruct dp_power - DisplayPort's power related data
@@ -32,8 +31,7 @@ struct dp_power {
int (*clk_enable)(struct dp_power *power, enum dp_pm_type pm_type,
bool enable);
int (*set_pixel_clk_parent)(struct dp_power *power);
- int (*power_client_init)(struct dp_power *power,
- struct dpu_power_handle *phandle);
+ int (*power_client_init)(struct dp_power *power);
void (*power_client_deinit)(struct dp_power *power);
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
__
[DPU PATCH v3 08/12] drm/msm/dpu: remove power management code from dpu_power_handle
Mdss main power supply (mdss_gdsc) is implemented as a
generic power domain and mdss top level wrapper device
manage it via runtime_pm. Remove custom power management
code from dpu_power_handle.
Changes in v3:
- remove redundant param check from
dpu_power_resource_init() (Sean Paul)
Changes in v2:
- resolved merge conflict in dpu_power_resource_init
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/dpu_power_handle.c | 195 +
drivers/gpu/drm/msm/dpu_power_handle.h | 2 -
2 files changed, 1 insertion(+), 196 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c
b/drivers/gpu/drm/msm/dpu_power_handle.c
index 12602ae..bdf18de 100644
--- a/drivers/gpu/drm/msm/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/dpu_power_handle.c
@@ -101,150 +101,6 @@ void dpu_power_client_destroy(struct dpu_power_handle
*phandle,
}
}
-static int dpu_power_parse_dt_supply(struct platform_device *pdev,
- struct dss_module_power *mp)
-{
- int i = 0, rc = 0;
- u32 tmp = 0;
- struct device_node *of_node = NULL, *supply_root_node = NULL;
- struct device_node *supply_node = NULL;
-
- if (!pdev || !mp) {
- pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
- return -EINVAL;
- }
-
- of_node = pdev->dev.of_node;
-
- mp->num_vreg = 0;
- supply_root_node = of_get_child_by_name(of_node,
- "qcom,platform-supply-entries");
- if (!supply_root_node) {
- pr_debug("no supply entry present\n");
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node)
- mp->num_vreg++;
-
- if (mp->num_vreg == 0) {
- pr_debug("no vreg\n");
- return rc;
- }
-
- pr_debug("vreg found. count=%d\n", mp->num_vreg);
- mp->vreg_config = devm_kzalloc(>dev, sizeof(struct dss_vreg) *
- mp->num_vreg, GFP_KERNEL);
- if (!mp->vreg_config) {
- rc = -ENOMEM;
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node) {
-
- const char *st = NULL;
-
- rc = of_property_read_string(supply_node,
- "qcom,supply-name", );
- if (rc) {
- pr_err("error reading name. rc=%d\n", rc);
- goto error;
- }
-
- strlcpy(mp->vreg_config[i].vreg_name, st,
- sizeof(mp->vreg_config[i].vreg_name));
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-min-voltage", );
- if (rc) {
- pr_err("error reading min volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].min_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-max-voltage", );
- if (rc) {
- pr_err("error reading max volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].max_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-enable-load", );
- if (rc) {
- pr_err("error reading enable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].enable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-disable-load", );
- if (rc) {
- pr_err("error reading disable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].disable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-on-sleep", );
- if (rc)
- pr_debug("error reading supply pre sleep value.
rc=%d\n",
- rc);
-
- mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-off-sleep", );
- if (rc)
- pr_de
[DPU PATCH v3 06/12] drm/msm/dpu: use runtime_pm calls on dpu device
The dpu driver implements runtime_pm support for managing
dpu specific resources like - clocks, bus bandwidth etc.
Use pm_runtime_get/put_sync calls on dpu device.
The common clocks and power management for all child nodes
(mdp5/dpu, dsi, dp etc) is done by parent MDSS device/driver
via runtime_pm due to parent child relationship.
Changes in v3:
- none
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 8 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 45 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c| 6 ++--
5 files changed, 31 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 977adc4..5c5cc56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -452,10 +452,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
spin_lock_init(_kms->irq_obj.cb_lock);
@@ -496,7 +496,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
if (atomic_read(_kms->irq_obj.enable_counts[i]) ||
!list_empty(_kms->irq_obj.irq_cb_tbl[i]))
@@ -504,7 +504,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
kfree(dpu_kms->irq_obj.irq_cb_tbl);
kfree(dpu_kms->irq_obj.enable_counts);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 48920b05..e2d2e32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -86,8 +86,12 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc
*dpu_crtc, bool enable)
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
/**
@@ -2250,7 +2254,6 @@ static int _dpu_crtc_vblank_enable_no_lock(
/* drop lock since power crtc cb may try to re-acquire lock */
mutex_unlock(_crtc->crtc_lock);
- pm_runtime_get_sync(dev->dev);
ret = _dpu_crtc_power_enable(dpu_crtc, true);
mutex_lock(_crtc->crtc_lock);
if (ret)
@@ -2580,7 +2583,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
/* disable clk & bw control until clk & bw properties are set */
cstate->bw_control = false;
cstate->bw_split_vote = false;
- pm_runtime_put_sync(crtc->dev->dev);
mutex_unlock(_crtc->crtc_lock);
}
@@ -2611,8 +2613,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
return;
}
- pm_runtime_get_sync(crtc->dev->dev);
-
drm_for_each_encoder(encoder, crtc->dev) {
if (encoder->crtc != crtc)
continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4386360..298a6ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -268,8 +268,12 @@ static inline int _dpu_encoder_power_enable(struct
dpu_encoder_virt *dpu_enc,
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
void dpu_encoder_helper_repor
[DPU PATCH v3 05/12] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address
The dpu sub-block offsets were defined wrt mdss base address
instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog
offsets for all dpu sub blocks wrt dpu base address.
Changes in v3:
- none
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c5b370f..2fd3254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -80,7 +80,7 @@
static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
- .base = 0x1000, .len = 0x45C,
+ .base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
.has_dest_scaler = true,
@@ -111,27 +111,27 @@
static struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
- .base = 0x2000, .len = 0xE4,
+ .base = 0x1000, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_1", .id = CTL_1,
- .base = 0x2200, .len = 0xE4,
+ .base = 0x1200, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_2", .id = CTL_2,
- .base = 0x2400, .len = 0xE4,
+ .base = 0x1400, .len = 0xE4,
.features = 0
},
{
.name = "ctl_3", .id = CTL_3,
- .base = 0x2600, .len = 0xE4,
+ .base = 0x1600, .len = 0xE4,
.features = 0
},
{
.name = "ctl_4", .id = CTL_4,
- .base = 0x2800, .len = 0xE4,
+ .base = 0x1800, .len = 0xE4,
.features = 0
},
};
@@ -211,21 +211,21 @@
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+ SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+ SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+ SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+ SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+ SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+ SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+ SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+ SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
};
@@ -252,17 +252,17 @@
.lm_pair_mask = (1 << _lmpair) \
}
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+ LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+ LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+ LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
DS_MAX, PINGPONG_2, LM_5),
LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+ LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
DS_MAX, PINGPONG_3, LM_2),
};
@@ -270,7 +270,7 @@
* DSPP sub blocks config
*/
static struct dpu_dspp_top_cfg sdm845_dspp_top = {
- .name = "dspp_top", .base = 0x1300, .len = 0xc
+ .name = "dspp_top", .base = 0x300, .len = 0xc
};
static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
@@ -304,10 +304,10 @@
}
static struct dpu_dspp_cfg sdm845_dspp[] = {
[DPU PATCH v3 01/12] drm/msm: remove redundant pm_runtime_enable call from msm_drv
MDSS top level device includes the common power resources and it's corresponding driver (i.e. mdp5_mdss) handles call to enable/disable runtime_pm for enabling these resources. Remove redundant pm_runtime_enable call from msm_drv. Changes in v3: - none Changes in v2: - none Signed-off-by: Rajesh Yadav <rya...@codeaurora.org> Reviewed-by: Sean Paul <seanp...@chromium.org> --- drivers/gpu/drm/msm/msm_drv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ebc40a9..9bb436f 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -581,7 +581,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto fail; } priv->kms = kms; - pm_runtime_enable(dev); /** * Since kms->funcs->hw_init(kms) might call -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v3 00/12] Refactor DPU device/driver hierarchy and add runtime_pm support
ecks for vtotal and vrefresh from dpu_encoder_phys_cmd_tearcheck_config() as they should be valid in mode_set() call (Sean Paul) - add error handling in dpu_core_perf_crtc_update() (Sean Paul) Rajesh Yadav (12): drm/msm: remove redundant pm_runtime_enable call from msm_drv drm/msm/mdp5: subclass msm_mdss for mdp5 drm/msm/dpu: add MDSS top level driver for dpu drm/msm/dpu: create new platform driver for dpu device drm/msm/dpu: update dpu sub-block offsets wrt dpu base address drm/msm/dpu: use runtime_pm calls on dpu device drm/msm/dpu: remove clock management code from dpu_power_handle drm/msm/dpu: remove power management code from dpu_power_handle drm/msm/dp: remove dpu_power_handle calls from dp driver drm/msm/dpu: use runtime_pm calls in dpu_dbg drm/msm/dpu: move dpu_power_handle to dpu folder drm/msm/dpu: add error handling in dpu_core_perf_crtc_update drivers/gpu/drm/msm/Makefile |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 106 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 82 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |2 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 17 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 77 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 46 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c| 48 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 337 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 251 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 688 + drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 +-- drivers/gpu/drm/msm/dp/dp_power.c | 32 +- drivers/gpu/drm/msm/dp/dp_power.h |4 +- drivers/gpu/drm/msm/dpu_dbg.c | 18 +- drivers/gpu/drm/msm/dpu_dbg.h | 13 +- drivers/gpu/drm/msm/dpu_io_util.c | 49 + drivers/gpu/drm/msm/dpu_power_handle.c | 1075 drivers/gpu/drm/msm/dpu_power_handle.h | 330 -- drivers/gpu/drm/msm/msm_drv.c | 86 +- drivers/gpu/drm/msm/msm_drv.h | 10 +- drivers/gpu/drm/msm/msm_kms.h | 21 +- include/linux/dpu_io_util.h|2 + 32 files changed, 1803 insertions(+), 2035 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v2 11/12] drm/msm/dpu: move dpu_power_handle to dpu folder
Now, since dpu_power_handle manages only bus scaling
and power enable/disable notifications which are restricted
to dpu driver, move dpu_power_handle to dpu folder.
Changes in v2:
- resolved conflict in dpu_unbind
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 39 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 693 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++
drivers/gpu/drm/msm/dpu_power_handle.c | 693 ---
drivers/gpu/drm/msm/dpu_power_handle.h | 288 --
drivers/gpu/drm/msm/msm_drv.c| 9 -
drivers/gpu/drm/msm/msm_drv.h| 4 -
14 files changed, 1013 insertions(+), 1020 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d9826c1..f578d5a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -82,10 +82,10 @@ msm-y := \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
+ disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
dpu_io_util.o \
dpu_dbg_evtlog.o \
- dpu_power_handle.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 5c5cc56..33ab2ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,7 +18,6 @@
#include
#include "dpu_core_irq.h"
-#include "dpu_power_handle.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 2cf3fca..d3a1ed9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -257,7 +257,6 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
= dpu_crtc_get_client_type(crtc);
struct drm_crtc *tmp_crtc;
struct dpu_crtc_state *dpu_cstate;
- struct msm_drm_private *priv = kms->dev->dev_private;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
@@ -287,7 +286,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
switch (curr_client_type) {
case NRT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
@@ -295,7 +294,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
break;
case RT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e2d2e32..99c5e75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -598,6 +598,7 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
_dpu_crtc_destroy_dest_scaler(dpu_crtc);
_dpu_crtc_deinit_events(dpu_crtc);
+ dpu_crtc->phandle = NULL;
drm_crtc_cleanup(crtc);
mutex_destroy(_crtc->crtc_lock);
@@ -2572,7 +2573,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
}
if (dpu_crtc->power_event)
- dpu_power_handle_unregister_event(>phandle,
+ dpu_power_handle_unregister_event(dpu_crtc->phandle,
dpu_c
[DPU PATCH v2 12/12] drm/msm/dpu: add error handling in dpu_core_perf_crtc_update
dpu_core_perf_crtc_update() is responsible for aggregating
the data bus bandwidth and dpu core clock rate requirements
and request the same for all active crtcs.
Currently, there is no error handling support in this function
so there is no way caller can know if the perf request fails.
This change adds error handling code in dpu_core_perf_crtc_update().
The caller side error handling is not added in this patch.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 37 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 3 ++-
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index d3a1ed9..85c0229 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -248,7 +248,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
return 0;
}
-static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
+static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
struct drm_crtc *crtc, u32 bus_id)
{
u64 bw_sum_of_intfs = 0, bus_ab_quota, bus_ib_quota;
@@ -257,6 +257,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
= dpu_crtc_get_client_type(crtc);
struct drm_crtc *tmp_crtc;
struct dpu_crtc_state *dpu_cstate;
+ int ret = 0;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
@@ -286,25 +287,28 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
switch (curr_client_type) {
case NRT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ ret = dpu_power_data_bus_set_quota(
+ >phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
- bus_id, bus_ab_quota, bus_ib_quota);
+ bus_id, bus_ab_quota, bus_ib_quota);
break;
case RT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ ret = dpu_power_data_bus_set_quota(
+ >phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
- bus_id, bus_ab_quota, bus_ib_quota);
+ bus_id, bus_ab_quota, bus_ib_quota);
break;
default:
DPU_ERROR("invalid client type:%d\n", curr_client_type);
break;
}
+ return ret;
}
/**
@@ -399,7 +403,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms
*kms)
return clk_rate;
}
-void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
+int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
int params_changed, bool stop_req)
{
struct dpu_core_perf_params *new, *old;
@@ -410,16 +414,17 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
int i;
struct msm_drm_private *priv;
struct dpu_kms *kms;
+ int ret;
if (!crtc) {
DPU_ERROR("invalid crtc\n");
- return;
+ return -EINVAL;
}
kms = _dpu_crtc_get_kms(crtc);
if (!kms || !kms->catalog) {
DPU_ERROR("invalid kms\n");
- return;
+ return -EINVAL;
}
priv = kms->dev->dev_private;
@@ -482,8 +487,14 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
update_bus, update_clk);
for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- if (update_bus & BIT(i))
- _dpu_core_perf_crtc_update_bus(kms, crtc, i);
+ if (update_bus & BIT(i)) {
+ ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i);
+ if (ret) {
+ DPU_ERROR("crtc-%d: failed to update bw vote
for bus-%d\n",
+ crtc->base.id, i);
+ return ret;
+ }
+ }
}
/*
@@ -495,15 +506,17 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- if (_dpu_core_perf_set_core_clk_rate(kms, clk_rate)) {
+
[DPU PATCH v2 10/12] drm/msm/dpu: use runtime_pm calls in dpu_dbg
Currently, msm_drv was creating dpu_power_handle client
which was used by dpu_dbg module to enable power resources
before register debug dumping.
Now since, the mdss core power resource handling is
implemented via runtime_pm and same has been removed
from dpu_power_handle. Remove dpu_power_handle dependency
from msm_drv and use pm_runtime_get/put_sync calls from
dpu_dbg module on dpu_mdss top level device for core,
ahb clock and power resource management (for register access).
Changes in v2:
- resolved conflict in dpu_core_perf_init
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/dpu_dbg.c | 18 +++---
drivers/gpu/drm/msm/dpu_dbg.h | 13 ++---
drivers/gpu/drm/msm/msm_drv.c | 27 +--
drivers/gpu/drm/msm/msm_drv.h | 1 -
7 files changed, 11 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 5b79077..2cf3fca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -673,18 +673,11 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk)
{
- if (!pclient) {
- DPU_ERROR("invalid parameters\n");
- return -EINVAL;
- }
-
perf->dev = dev;
perf->catalog = catalog;
perf->phandle = phandle;
- perf->pclient = pclient;
perf->core_clk = core_clk;
perf->max_core_clk_rate = core_clk->max_rate;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 9c1a719..cde48df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
@@ -53,7 +53,6 @@ struct dpu_core_perf_tune {
* @debugfs_root: top level debug folder
* @catalog: Pointer to catalog configuration
* @phandle: Pointer to power handler
- * @pclient: Pointer to power client
* @core_clk: Pointer to core clock structure
* @core_clk_rate: current core clock rate
* @max_core_clk_rate: maximum allowable core clock rate
@@ -68,7 +67,6 @@ struct dpu_core_perf {
struct dentry *debugfs_root;
struct dpu_mdss_cfg *catalog;
struct dpu_power_handle *phandle;
- struct dpu_power_client *pclient;
struct dss_clk *core_clk;
u64 core_clk_rate;
u64 max_core_clk_rate;
@@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
* @dev: Pointer to drm device
* @catalog: Pointer to catalog
* @phandle: Pointer to power handle
- * @pclient: Pointer to power client
* @core_clk: pointer to core clock
*/
int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk);
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 349bda5..9c3b220 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1721,8 +1721,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
#endif
rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
- >phandle, priv->pclient,
- _dpu_kms_get_clk(dpu_kms, "core_clk"));
+ >phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
if (rc) {
DPU_ERROR("failed to init perf %d\n", rc);
goto perf_err;
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 4a39b82..27538bc 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "dpu_dbg.h"
#include "disp/dpu1/dpu_hw_catalog.h"
@@ -167,7 +168,6 @@ struct dpu_dbg_vbif_debug_bus {
* @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @power_ctrl: callback structure for enabling power for reading hw registers
* @req_dump_blks: list of blocks requested for dumping
* @panic_on_err: whether to kernel panic after triggering dump via debugfs
* @dump_work: work struct for deferring register dump work to sep
[DPU PATCH v2 09/12] drm/msm/dp: remove dpu_power_handle calls from dp driver
DP driver was dependent on dpu_power_handle for MDSS
common clocks and gdsc (main power supply).
The common clocks and power is managed by MDSS top
wrapper device now which is parent of all sub-devices
like DP device.
For same reason, clock and power management code is
removed from dpu_power_handle. Hence, remove the
dpu_power_handle calls from dp driver.
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/dp/dp_power.c | 32 +---
drivers/gpu/drm/msm/dp/dp_power.h | 4 +---
2 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index f6e341b..2a85b38 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -26,8 +26,6 @@ struct dp_power_private {
struct clk *pixel_parent;
struct dp_power dp_power;
- struct dpu_power_client *dp_core_client;
- struct dpu_power_handle *phandle;
bool core_clks_on;
bool link_clks_on;
@@ -410,8 +408,7 @@ static int dp_power_config_gpios(struct dp_power_private
*power, bool flip,
return 0;
}
-static int dp_power_client_init(struct dp_power *dp_power,
- struct dpu_power_handle *phandle)
+static int dp_power_client_init(struct dp_power *dp_power)
{
int rc = 0;
struct dp_power_private *power;
@@ -436,19 +433,8 @@ static int dp_power_client_init(struct dp_power *dp_power,
goto error_clk;
}
- power->phandle = phandle;
- snprintf(dp_client_name, DP_CLIENT_NAME_SIZE, "dp_core_client");
- power->dp_core_client = dpu_power_client_create(phandle,
- dp_client_name);
- if (IS_ERR_OR_NULL(power->dp_core_client)) {
- pr_err("[%s] client creation failed for DP", dp_client_name);
- rc = -EINVAL;
- goto error_client;
- }
return 0;
-error_client:
- dp_power_clk_init(power, false);
error_clk:
dp_power_regulator_deinit(power);
error_power:
@@ -466,7 +452,6 @@ static void dp_power_client_deinit(struct dp_power
*dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
- dpu_power_client_destroy(power->phandle, power->dp_core_client);
dp_power_clk_init(power, false);
dp_power_regulator_deinit(power);
}
@@ -521,13 +506,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
goto err_gpio;
}
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, true);
- if (rc) {
- pr_err("Power resource enable failed\n");
- goto err_dpu_power;
- }
-
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
if (rc) {
pr_err("failed to enable DP core clocks\n");
@@ -537,8 +515,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
return 0;
err_clk:
- dpu_power_resource_enable(power->phandle, power->dp_core_client, false);
-err_dpu_power:
dp_power_config_gpios(power, flip, false);
err_gpio:
dp_power_pinctrl_set(power, false);
@@ -562,12 +538,6 @@ static int dp_power_deinit(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, false);
- if (rc) {
- pr_err("Power resource enable failed, rc=%d\n", rc);
- goto exit;
- }
dp_power_config_gpios(power, false, false);
dp_power_pinctrl_set(power, false);
dp_power_regulator_ctrl(power, false);
diff --git a/drivers/gpu/drm/msm/dp/dp_power.h
b/drivers/gpu/drm/msm/dp/dp_power.h
index 84fe01d..d9dab72 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.h
+++ b/drivers/gpu/drm/msm/dp/dp_power.h
@@ -16,7 +16,6 @@
#define _DP_POWER_H_
#include "dp_parser.h"
-#include "dpu_power_handle.h"
/**
* sruct dp_power - DisplayPort's power related data
@@ -32,8 +31,7 @@ struct dp_power {
int (*clk_enable)(struct dp_power *power, enum dp_pm_type pm_type,
bool enable);
int (*set_pixel_clk_parent)(struct dp_power *power);
- int (*power_client_init)(struct dp_power *power,
- struct dpu_power_handle *phandle);
+ int (*power_client_init)(struct dp_power *power);
void (*power_client_deinit)(struct dp_power *power);
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v2 07/12] drm/msm/dpu: remove clock management code from dpu_power_handle
MDSS and dpu drivers manage their respective clocks via
runtime_pm. Remove custom clock management code from
dpu_power_handle.
Also dpu core clock management code is restricted to
dpu_core_perf module.
Changes in v2:
- remove local variable to hold and return error code
in _dpu_core_perf_set_core_clk_rate() instead return
retcode directly from msm_dss_clk_set_rate() call (Sean Paul)
- dpu_core_perf_init() is called from dpu_kms_hw_init() and
most of the params passed are already validated so remove
redundant checks from dpu_core_perf_init() (Sean Paul)
- return >clk_config[i] directly to avoid local variable
in _dpu_kms_get_clk() (Sean Paul)
- invert conditional check to eliminate local rate variable
from dpu_kms_get_clk_rate() (Sean Paul)
- remove end label from dpu_power_resource_init() and return
directly on dpu_power_parse_dt_supply() failure as no cleanup
is needed (Sean Paul)
- remove checks for vtotal and vrefresh from
dpu_encoder_phys_cmd_tearcheck_config() as they should be
valid in mode_set call (Sean Paul)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 41 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 28 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 9 +
drivers/gpu/drm/msm/dpu_power_handle.c | 196 +
drivers/gpu/drm/msm/dpu_power_handle.h | 40 -
7 files changed, 63 insertions(+), 268 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 981f77f..5b79077 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -365,6 +365,17 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
}
}
+static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
+{
+ struct dss_clk *core_clk = kms->perf.core_clk;
+
+ if (core_clk->max_rate && (rate > core_clk->max_rate))
+ rate = core_clk->max_rate;
+
+ core_clk->rate = rate;
+ return msm_dss_clk_set_rate(core_clk, 1);
+}
+
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
{
u64 clk_rate = kms->perf.perf_tune.min_core_clk;
@@ -376,7 +387,8 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms
*kms)
dpu_cstate = to_dpu_crtc_state(crtc->state);
clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
clk_rate);
- clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
+ clk_rate = clk_round_rate(kms->perf.core_clk->clk,
+ clk_rate);
}
}
@@ -484,15 +496,11 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- /* Temp change to avoid crash in clk_set_rate API. */
-#ifdef QCOM_DPU_SET_CLK
- if (dpu_power_clk_set_rate(>phandle,
- kms->perf.clk_name, clk_rate)) {
+ if (_dpu_core_perf_set_core_clk_rate(kms, clk_rate)) {
DPU_ERROR("failed to set %s clock rate %llu\n",
- kms->perf.clk_name, clk_rate);
+ kms->perf.core_clk->clk_name, clk_rate);
return;
}
-#endif
kms->perf.core_clk_rate = clk_rate;
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
@@ -656,7 +664,6 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
dpu_core_perf_debugfs_destroy(perf);
perf->max_core_clk_rate = 0;
perf->core_clk = NULL;
- perf->clk_name = NULL;
perf->phandle = NULL;
perf->catalog = NULL;
perf->dev = NULL;
@@ -667,9 +674,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
struct dpu_power_client *pclient,
- char *clk_name)
+ struct dss_clk *core_clk)
{
- if (!perf || !dev || !catalog || !phandle || !pclient || !clk_name) {
+ if (!pclient) {
DPU_ERROR("invalid parameters\n");
return -EINVAL;
}
@@ -678,23 +685,13 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
perf->catalog = catalog;
perf->phandle = phandle;
perf->pclient =
[DPU PATCH v2 08/12] drm/msm/dpu: remove power management code from dpu_power_handle
Mdss main power supply (mdss_gdsc) is implemented as a
generic power domain and mdss top level wrapper device
manage it via runtime_pm. Remove custom power management
code from dpu_power_handle.
Changes in v2:
- resolved merge conflict in dpu_power_resource_init
- dropped (Reviewed-by: Sean Paul) due to above change
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/dpu_power_handle.c | 194 +
drivers/gpu/drm/msm/dpu_power_handle.h | 2 -
2 files changed, 3 insertions(+), 193 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c
b/drivers/gpu/drm/msm/dpu_power_handle.c
index 12602ae..77be106 100644
--- a/drivers/gpu/drm/msm/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/dpu_power_handle.c
@@ -101,150 +101,6 @@ void dpu_power_client_destroy(struct dpu_power_handle
*phandle,
}
}
-static int dpu_power_parse_dt_supply(struct platform_device *pdev,
- struct dss_module_power *mp)
-{
- int i = 0, rc = 0;
- u32 tmp = 0;
- struct device_node *of_node = NULL, *supply_root_node = NULL;
- struct device_node *supply_node = NULL;
-
- if (!pdev || !mp) {
- pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
- return -EINVAL;
- }
-
- of_node = pdev->dev.of_node;
-
- mp->num_vreg = 0;
- supply_root_node = of_get_child_by_name(of_node,
- "qcom,platform-supply-entries");
- if (!supply_root_node) {
- pr_debug("no supply entry present\n");
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node)
- mp->num_vreg++;
-
- if (mp->num_vreg == 0) {
- pr_debug("no vreg\n");
- return rc;
- }
-
- pr_debug("vreg found. count=%d\n", mp->num_vreg);
- mp->vreg_config = devm_kzalloc(>dev, sizeof(struct dss_vreg) *
- mp->num_vreg, GFP_KERNEL);
- if (!mp->vreg_config) {
- rc = -ENOMEM;
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node) {
-
- const char *st = NULL;
-
- rc = of_property_read_string(supply_node,
- "qcom,supply-name", );
- if (rc) {
- pr_err("error reading name. rc=%d\n", rc);
- goto error;
- }
-
- strlcpy(mp->vreg_config[i].vreg_name, st,
- sizeof(mp->vreg_config[i].vreg_name));
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-min-voltage", );
- if (rc) {
- pr_err("error reading min volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].min_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-max-voltage", );
- if (rc) {
- pr_err("error reading max volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].max_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-enable-load", );
- if (rc) {
- pr_err("error reading enable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].enable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-disable-load", );
- if (rc) {
- pr_err("error reading disable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].disable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-on-sleep", );
- if (rc)
- pr_debug("error reading supply pre sleep value.
rc=%d\n",
- rc);
-
- mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-off-sleep", );
- if (rc)
- pr_debug("error reading supply pre sleep value.
rc=%d\n",
- rc);
-
- mp->vreg_config[i].pre_off_sleep =
[DPU PATCH v2 06/12] drm/msm/dpu: use runtime_pm calls on dpu device
The dpu driver implements runtime_pm support for managing
dpu specific resources like - clocks, bus bandwidth etc.
Use pm_runtime_get/put_sync calls on dpu device.
The common clocks and power management for all child nodes
(mdp5/dpu, dsi, dp etc) is done by parent MDSS device/driver
via runtime_pm due to parent child relationship.
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 8 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 45 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c| 6 ++--
5 files changed, 31 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 977adc4..5c5cc56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -452,10 +452,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
spin_lock_init(_kms->irq_obj.cb_lock);
@@ -496,7 +496,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
if (atomic_read(_kms->irq_obj.enable_counts[i]) ||
!list_empty(_kms->irq_obj.irq_cb_tbl[i]))
@@ -504,7 +504,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
kfree(dpu_kms->irq_obj.irq_cb_tbl);
kfree(dpu_kms->irq_obj.enable_counts);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 48920b05..e2d2e32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -86,8 +86,12 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc
*dpu_crtc, bool enable)
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
/**
@@ -2250,7 +2254,6 @@ static int _dpu_crtc_vblank_enable_no_lock(
/* drop lock since power crtc cb may try to re-acquire lock */
mutex_unlock(_crtc->crtc_lock);
- pm_runtime_get_sync(dev->dev);
ret = _dpu_crtc_power_enable(dpu_crtc, true);
mutex_lock(_crtc->crtc_lock);
if (ret)
@@ -2580,7 +2583,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
/* disable clk & bw control until clk & bw properties are set */
cstate->bw_control = false;
cstate->bw_split_vote = false;
- pm_runtime_put_sync(crtc->dev->dev);
mutex_unlock(_crtc->crtc_lock);
}
@@ -2611,8 +2613,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
return;
}
- pm_runtime_get_sync(crtc->dev->dev);
-
drm_for_each_encoder(encoder, crtc->dev) {
if (encoder->crtc != crtc)
continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4386360..298a6ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -268,8 +268,12 @@ static inline int _dpu_encoder_power_enable(struct
dpu_encoder_virt *dpu_enc,
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *
[DPU PATCH v2 05/12] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address
The dpu sub-block offsets were defined wrt mdss base address
instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog
offsets for all dpu sub blocks wrt dpu base address.
Changes in v2:
- none
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c5b370f..2fd3254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -80,7 +80,7 @@
static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
- .base = 0x1000, .len = 0x45C,
+ .base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
.has_dest_scaler = true,
@@ -111,27 +111,27 @@
static struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
- .base = 0x2000, .len = 0xE4,
+ .base = 0x1000, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_1", .id = CTL_1,
- .base = 0x2200, .len = 0xE4,
+ .base = 0x1200, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_2", .id = CTL_2,
- .base = 0x2400, .len = 0xE4,
+ .base = 0x1400, .len = 0xE4,
.features = 0
},
{
.name = "ctl_3", .id = CTL_3,
- .base = 0x2600, .len = 0xE4,
+ .base = 0x1600, .len = 0xE4,
.features = 0
},
{
.name = "ctl_4", .id = CTL_4,
- .base = 0x2800, .len = 0xE4,
+ .base = 0x1800, .len = 0xE4,
.features = 0
},
};
@@ -211,21 +211,21 @@
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+ SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+ SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+ SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+ SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+ SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+ SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+ SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+ SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
};
@@ -252,17 +252,17 @@
.lm_pair_mask = (1 << _lmpair) \
}
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+ LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+ LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+ LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
DS_MAX, PINGPONG_2, LM_5),
LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+ LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
DS_MAX, PINGPONG_3, LM_2),
};
@@ -270,7 +270,7 @@
* DSPP sub blocks config
*/
static struct dpu_dspp_top_cfg sdm845_dspp_top = {
- .name = "dspp_top", .base = 0x1300, .len = 0xc
+ .name = "dspp_top", .base = 0x300, .len = 0xc
};
static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
@@ -304,10 +304,10 @@
}
static struct dpu_dspp_cfg sdm845_dspp[] = {
[DPU PATCH v2 04/12] drm/msm/dpu: create new platform driver for dpu device
Current MSM display controller HW matches a tree like
hierarchy where MDSS top level wrapper is parent device
and mdp5/dpu, dsi, dp are child devices.
Each child device like mdp5, dsi etc. have a separate driver,
but currently dpu handling is tied to a single driver which
was managing both mdss and dpu resources.
Inorder to have the cleaner one to one device and driver
association, this change adds a new platform_driver for dpu
child device node which implements the kms functionality.
The dpu driver implements runtime_pm support for managing clocks
and bus bandwidth etc.
Changes in v2:
- remove redundant param check from _dpu_kms_hw_destroy (Sean Paul)
- remove explicit calls to devm_kfree (Sean Paul)
- merge dpu_init into dpu_bind (Sean Paul)
- merge dpu_destroy into dpu_unbind (Sean Paul)
- use %pK for kernel pointer printing (Jordan Crouse)
- remove explicit devm allocation failure message (Jordan Crouse)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 238 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 +
drivers/gpu/drm/msm/msm_drv.c | 2 +
drivers/gpu/drm/msm/msm_drv.h | 3 +
4 files changed, 196 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e4ab753..85f3dbc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1030,16 +1030,12 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms,
unsigned long rate,
return rate;
}
-static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
- struct platform_device *pdev)
+static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
{
struct drm_device *dev;
struct msm_drm_private *priv;
int i;
- if (!dpu_kms || !pdev)
- return;
-
dev = dpu_kms->dev;
if (!dev)
return;
@@ -1091,15 +1087,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
dpu_kms->core_client = NULL;
if (dpu_kms->vbif[VBIF_NRT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_NRT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
dpu_kms->vbif[VBIF_NRT] = NULL;
if (dpu_kms->vbif[VBIF_RT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_RT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
if (dpu_kms->mmio)
- msm_iounmap(pdev, dpu_kms->mmio);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
dpu_reg_dma_deinit();
@@ -1172,8 +1168,6 @@ int dpu_kms_mmu_attach(struct dpu_kms *dpu_kms, bool
secure_only)
static void dpu_kms_destroy(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms;
- struct drm_device *dev;
- struct platform_device *platformdev;
if (!kms) {
DPU_ERROR("invalid kms\n");
@@ -1181,20 +1175,7 @@ static void dpu_kms_destroy(struct msm_kms *kms)
}
dpu_kms = to_dpu_kms(kms);
- dev = dpu_kms->dev;
- if (!dev) {
- DPU_ERROR("invalid device\n");
- return;
- }
-
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- return;
- }
-
- _dpu_kms_hw_destroy(dpu_kms, platformdev);
- kfree(dpu_kms);
+ _dpu_kms_hw_destroy(dpu_kms);
}
static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
@@ -1550,7 +1531,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
struct dpu_kms *dpu_kms;
struct drm_device *dev;
struct msm_drm_private *priv;
- struct platform_device *platformdev;
int i, rc = -EINVAL;
if (!kms) {
@@ -1565,34 +1545,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto end;
}
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- goto end;
- }
-
priv = dev->dev_private;
if (!priv) {
DPU_ERROR("invalid private data\n");
goto end;
}
- dpu_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
+ dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys");
if (IS_ERR(dpu_kms->mmio)) {
rc = PTR_ERR(dpu_kms->mmio);
DPU_ERROR("mdp register memory map failed: %d\n", rc);
dpu_kms->mmio = NULL;
goto error;
}
- DRM_INF
[DPU PATCH v2 03/12] drm/msm/dpu: add MDSS top level driver for dpu
SoCs containing dpu have a MDSS top level wrapper
which includes sub-blocks as dpu, dsi, phy, dp etc.
MDSS top level wrapper manages common resources like
common clocks, power and irq for its sub-blocks.
Currently, in dpu driver, all the power resource
management is part of power_handle which manages
these resources via a custom implementation. And
the resource relationships are not modelled properly
in dt. Moreover the irq domain handling code is part
of dpu device (which is a child device) due to lack
of a dedicated driver for MDSS top level wrapper
device.
This change adds dpu_mdss top level driver to handle
common clock like - core clock, ahb clock
(for register access), main power supply (i.e. gdsc)
and irq management.
The top level mdss device/driver acts as an interrupt
controller and manage hwirq mapping for its child
devices.
It implements runtime_pm support for resource management.
Child nodes can control these resources via runtime_pm
get/put calls on their corresponding devices due to parent
child relationship defined in dt.
Changes in v2:
- merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul)
- merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul)
- fix indentation for irq_find_mapping call (Sean Paul)
- remove unnecessary goto statements from dpu_mdss_irq (Sean Paul)
- remove redundant param checks from
dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse)
- remove redundant param checks from
dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse)
- return error code from dpu_mdss_enable/disable (Sean Paul/Jordan
Crouse)
- remove redundant param check from dpu_mdss_destroy (Sean Paul)
- remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse)
- remove compatibility check from dpu_mdss_init as
it is conditionally called from msm_drv (Sean Paul)
- reworked msm_dss_parse_clock() to add return checks for
of_property_read_* calls, fix log message and
fix alignment issues (Sean Paul/Jordan Crouse)
- remove extra line before dpu_mdss_init (Sean Paul)
- remove redundant param checks from __intr_offset and
make it a void function to avoid unnecessary error
handling from caller (Jordan Crouse)
- remove redundant param check from dpu_mdss_irq (Jordan Crouse)
- change mdss address space log message to debug and use %pK for
kernel pointers (Jordan Crouse)
- remove unnecessary log message from msm_dss_parse_clock (Jordan
Crouse)
- don't export msm_dss_parse_clock since it is used
only by dpu driver (Jordan Crouse)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 97 -
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 9 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 7 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 28 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 -
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 254 ++
drivers/gpu/drm/msm/dpu_io_util.c | 57 +
drivers/gpu/drm/msm/msm_drv.c | 26 ++-
drivers/gpu/drm/msm/msm_drv.h | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 1 +
include/linux/dpu_io_util.h | 2 +
16 files changed, 339 insertions(+), 226 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d7558ed..d9826c1 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -81,6 +81,7 @@ msm-y := \
disp/dpu1/dpu_reg_dma.o \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
+ disp/dpu1/dpu_mdss.o \
dpu_dbg.o \
dpu_io_util.o \
dpu_dbg_evtlog.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index fe33013..977adc4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -515,103 +515,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
dpu_kms->irq_obj.total_irqs = 0;
}
-static void dpu_core_irq_mask(struct irq_data *irqd)
-{
- struct dpu_kms *dpu_kms;
-
- if (!irqd || !irq_data_get_irq_chip_data(irqd)) {
- DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
- return;
- }
- dpu_kms = irq_data_get_irq_chip_data(irqd);
-
- /* memory barrier */
- sm
[DPU PATCH v2 01/12] drm/msm: remove redundant pm_runtime_enable call from msm_drv
MDSS top level device includes the common power resources and it's corresponding driver (i.e. mdp5_mdss) handles call to enable/disable runtime_pm for enabling these resources. Remove redundant pm_runtime_enable call from msm_drv. Changes in v2: - none Signed-off-by: Rajesh Yadav <rya...@codeaurora.org> Reviewed-by: Sean Paul <seanp...@chromium.org> --- drivers/gpu/drm/msm/msm_drv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ebc40a9..9bb436f 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -581,7 +581,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto fail; } priv->kms = kms; - pm_runtime_enable(dev); /** * Since kms->funcs->hw_init(kms) might call -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v2 02/12] drm/msm/mdp5: subclass msm_mdss for mdp5
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Changes in v2:
- fixed indentation for irq_domain_add_linear call (Sean Paul)
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
drivers/gpu/drm/msm/msm_drv.c | 23 +++--
drivers/gpu/drm/msm/msm_kms.h | 20 ++--
3 files changed, 110 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7..1cc4e57 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
#include "msm_drv.h"
#include "mdp5_kms.h"
-/*
- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
- struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+ struct msm_mdss base;
void __iomem *mmio, *vbif;
@@ -41,22 +39,22 @@ struct msm_mdss {
} irqcontroller;
};
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
{
- msm_writel(data, mdss->mmio + reg);
+ msm_writel(data, mdp5_mdss->mmio + reg);
}
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
{
- return msm_readl(mdss->mmio + reg);
+ return msm_readl(mdp5_mdss->mmio + reg);
}
static irqreturn_t mdss_irq(int irq, void *arg)
{
- struct msm_mdss *mdss = arg;
+ struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
- intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
+ intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
VERB("intr=%08x", intr);
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
- mdss->irqcontroller.domain, hwirq));
+ mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
static void mdss_hw_mask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
static void mdss_hw_unmask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
@@ -109,13 +107,13 @@ static void mdss_hw_unmask_irq(struct irq_data *irqd)
static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- struct msm_mdss *mdss = d->host_data;
+ struct mdp5_mdss *mdp5_mdss = d->host_data;
if (!(VALID_IRQS & (1 << hwirq)))
return -EPERM;
irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, mdss);
+ irq_set_chip_data(irq, mdp5_mdss);
return 0;
}
@@ -126,90 +124,99 @@ static int mdss_hw_irqdomain_map(struct irq_domain *d,
unsigned int irq,
};
-static int mdss_irq_domain_init(struct msm_mdss *mdss)
+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
{
- struct device *dev = mdss->dev->dev;
+ struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,
- mdss);
+ mdp5_mdss);
if (!d) {
dev_err(dev, "mdss irq domain add failed\n");
return -ENXIO;
}
- mdss->irqcontroller.enabled_ma
[DPU PATCH v2 00/12] Refactor DPU device/driver hierarchy and add runtime_pm support
SoCs containing mdp5 or dpu have a MDSS top level wrapper which includes sub-blocks as mdp5/dpu, dsi, dp, hdmi etc. The MDSS top level wrapper manages common resources like common clocks, main power supply and interrupts for its sub-blocks. But current dpu driver implementation is based on a flat device hierarchy where MDSS/DPU HW blocks were represented by single device and DSI/DP etc. are represented as independent devices w/o any relationships b/t these nodes which doesn't model the HW associations precisely. A minimal MDSS and DPU controller device separation is done in following patch series [1] but currently both these devices match to a single driver which is getting probed two times and all the resources are still tied to DPU device. Moreover, all the power resource management in DPU driver is part of power_handle module which manages these resources via a custom implementation. Irq domain handling is part of DPU device, due to lack of a dedicated driver for MDSS top level wrapper device. This patch series aims at adding separate drivers for MDSS top level wrapper device and DPU child device. MDP5 device/driver is used as a reference for this refactoring effort. Both the drivers implement runtime_pm support for their power resource management. Child nodes can control common resources managed by parent device due to parent child relationship defined in dt. The top level MDSS device acts as an interrupt controller and manages hwirq mappings for its child devices. Inorder to add MDP5 and DPU specific MDSS driver implementation, this patch series also subclasses existing msm_mdss define. A helper interface (msm_mdss_funcs) is added to invoke the platform specific implementations. This change also corrects hw catalog offsets for all sub blocks present within DPU device. The offset are now defined wrt DPU base address (instead of using MDSS base address). Clock and Power handling code have been removed from dpu_power_handle since each device manages it's resources via runtime_pm. Now, since dpu_power_handle manages only bus scaling and power enable/disable notifications and it's usage is restricted to DPU driver only, moved dpu_power_handle code to DPU folder. The dt bindings update patch will be sent subsequently. This patch series depends on [1]. 1 - https://lists.freedesktop.org/archives/freedreno/2018-April/002354.html Changes in v2: - fix indentation issues in dpu_mdss (Sean Paul) - merge tiny static functions (like _dpu_mdss_hw_rev_init() and _dpu_mdss_get_intr_sources()) in caller functions (Sean Paul) - remove unnecessary goto statements from dpu_mdss_irq (Sean Paul) - remove redundant input param checks from dpu_mdss and dpu_kms (Sean Paul/Jordan Crouse) - return error code from dpu_mdss_enable/disable (Sean Paul/Jordan Crouse) - remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse) - remove compatibility check from dpu_mdss_init as it is conditionally called from msm_drv (Sean Paul) - reworked msm_dss_parse_clock() to add return checks for of_property_read_* calls, fix log message and fix alignment issues (Sean Paul/Jordan Crouse) - remove redundant param checks from __intr_offset and make it a void function to avoid unnecessary error handling from caller (Jordan Crouse) - use %pK for kernel pointers (Jordan Crouse) - don't export msm_dss_parse_clock since it is used only by dpu driver (Jordan Crouse) - merge dpu_init into dpu_bind and dpu_destroy into dpu_unbind (Sean Paul) - remove explicit devm allocation failure message (Jordan Crouse) - remove local variable to hold and return error code in _dpu_core_perf_set_core_clk_rate() instead return retcode directly from msm_dss_clk_set_rate() call (Sean Paul) - return >clk_config[i] directly to avoid local variable in _dpu_kms_get_clk() (Sean Paul) - invert conditional check to eliminate local rate variable from dpu_kms_get_clk_rate() (Sean Paul) - remove end label from dpu_power_resource_init() and return directly on dpu_power_parse_dt_supply() failure as no cleanup is needed (Sean Paul) - remove checks for vtotal and vrefresh from dpu_encoder_phys_cmd_tearcheck_config() as they should be valid in mode_set() call (Sean Paul) - add error handling in dpu_core_perf_crtc_update() (Sean Paul) Rajesh Yadav (12): drm/msm: remove pm_runtime_enable call from msm_drv drm/msm/mdp5: subclass msm_mdss for mdp5 drm/msm/dpu: add MDSS top level driver for dpu drm/msm/dpu: create new platform driver for dpu device drm/msm/dpu: update dpu sub-block offsets wrt dpu base address drm/msm/dpu: use runtime_pm calls on dpu device drm/msm/dpu: remove clock management code from dpu_power_handle drm/msm/dpu: remove po
[DPU PATCH 09/11] drm/msm/dp: remove dpu_power_handle calls from dp driver
DP driver was dependent on dpu_power_handle for MDSS
common clocks and gdsc (main power supply).
The common clocks and power is managed by MDSS top
wrapper device now which is parent of all sub-devices
like DP device.
For same reason, clock and power management code is
removed from dpu_power_handle. Hence, remove the
dpu_power_handle calls from dp driver.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/dp/dp_power.c | 32 +---
drivers/gpu/drm/msm/dp/dp_power.h | 4 +---
2 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index f6e341b..2a85b38 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -26,8 +26,6 @@ struct dp_power_private {
struct clk *pixel_parent;
struct dp_power dp_power;
- struct dpu_power_client *dp_core_client;
- struct dpu_power_handle *phandle;
bool core_clks_on;
bool link_clks_on;
@@ -410,8 +408,7 @@ static int dp_power_config_gpios(struct dp_power_private
*power, bool flip,
return 0;
}
-static int dp_power_client_init(struct dp_power *dp_power,
- struct dpu_power_handle *phandle)
+static int dp_power_client_init(struct dp_power *dp_power)
{
int rc = 0;
struct dp_power_private *power;
@@ -436,19 +433,8 @@ static int dp_power_client_init(struct dp_power *dp_power,
goto error_clk;
}
- power->phandle = phandle;
- snprintf(dp_client_name, DP_CLIENT_NAME_SIZE, "dp_core_client");
- power->dp_core_client = dpu_power_client_create(phandle,
- dp_client_name);
- if (IS_ERR_OR_NULL(power->dp_core_client)) {
- pr_err("[%s] client creation failed for DP", dp_client_name);
- rc = -EINVAL;
- goto error_client;
- }
return 0;
-error_client:
- dp_power_clk_init(power, false);
error_clk:
dp_power_regulator_deinit(power);
error_power:
@@ -466,7 +452,6 @@ static void dp_power_client_deinit(struct dp_power
*dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
- dpu_power_client_destroy(power->phandle, power->dp_core_client);
dp_power_clk_init(power, false);
dp_power_regulator_deinit(power);
}
@@ -521,13 +506,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
goto err_gpio;
}
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, true);
- if (rc) {
- pr_err("Power resource enable failed\n");
- goto err_dpu_power;
- }
-
rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
if (rc) {
pr_err("failed to enable DP core clocks\n");
@@ -537,8 +515,6 @@ static int dp_power_init(struct dp_power *dp_power, bool
flip)
return 0;
err_clk:
- dpu_power_resource_enable(power->phandle, power->dp_core_client, false);
-err_dpu_power:
dp_power_config_gpios(power, flip, false);
err_gpio:
dp_power_pinctrl_set(power, false);
@@ -562,12 +538,6 @@ static int dp_power_deinit(struct dp_power *dp_power)
power = container_of(dp_power, struct dp_power_private, dp_power);
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
- rc = dpu_power_resource_enable(power->phandle,
- power->dp_core_client, false);
- if (rc) {
- pr_err("Power resource enable failed, rc=%d\n", rc);
- goto exit;
- }
dp_power_config_gpios(power, false, false);
dp_power_pinctrl_set(power, false);
dp_power_regulator_ctrl(power, false);
diff --git a/drivers/gpu/drm/msm/dp/dp_power.h
b/drivers/gpu/drm/msm/dp/dp_power.h
index 84fe01d..d9dab72 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.h
+++ b/drivers/gpu/drm/msm/dp/dp_power.h
@@ -16,7 +16,6 @@
#define _DP_POWER_H_
#include "dp_parser.h"
-#include "dpu_power_handle.h"
/**
* sruct dp_power - DisplayPort's power related data
@@ -32,8 +31,7 @@ struct dp_power {
int (*clk_enable)(struct dp_power *power, enum dp_pm_type pm_type,
bool enable);
int (*set_pixel_clk_parent)(struct dp_power *power);
- int (*power_client_init)(struct dp_power *power,
- struct dpu_power_handle *phandle);
+ int (*power_client_init)(struct dp_power *power);
void (*power_client_deinit)(struct dp_power *power);
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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dri-devel@lists.freedesktop.org
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[DPU PATCH 11/11] drm/msm/dpu: move dpu_power_handle to dpu folder
Now, since dpu_power_handle manages only bus scaling
and power enable/disable notifications which are restricted
to dpu driver, move dpu_power_handle to dpu folder.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 39 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 694 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++
drivers/gpu/drm/msm/dpu_power_handle.c | 694 ---
drivers/gpu/drm/msm/dpu_power_handle.h | 288 --
drivers/gpu/drm/msm/msm_drv.c| 9 -
drivers/gpu/drm/msm/msm_drv.h| 4 -
14 files changed, 1014 insertions(+), 1021 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c
delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d9826c1..f578d5a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -82,10 +82,10 @@ msm-y := \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
+ disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
dpu_io_util.o \
dpu_dbg_evtlog.o \
- dpu_power_handle.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 5c5cc56..33ab2ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,7 +18,6 @@
#include
#include "dpu_core_irq.h"
-#include "dpu_power_handle.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index e2e7c06..18da169 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -257,7 +257,6 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
= dpu_crtc_get_client_type(crtc);
struct drm_crtc *tmp_crtc;
struct dpu_crtc_state *dpu_cstate;
- struct msm_drm_private *priv = kms->dev->dev_private;
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
@@ -287,7 +286,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
switch (curr_client_type) {
case NRT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
@@ -295,7 +294,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
break;
case RT_CLIENT:
- dpu_power_data_bus_set_quota(>phandle, kms->core_client,
+ dpu_power_data_bus_set_quota(>phandle, kms->core_client,
DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
bus_id, bus_ab_quota, bus_ib_quota);
DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e2d2e32..99c5e75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -598,6 +598,7 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
_dpu_crtc_destroy_dest_scaler(dpu_crtc);
_dpu_crtc_deinit_events(dpu_crtc);
+ dpu_crtc->phandle = NULL;
drm_crtc_cleanup(crtc);
mutex_destroy(_crtc->crtc_lock);
@@ -2572,7 +2573,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
}
if (dpu_crtc->power_event)
- dpu_power_handle_unregister_event(>phandle,
+ dpu_power_handle_unregister_event(dpu_crtc->phandle,
dpu_crtc->power_event);
@@ -2643,7 +2644,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
[DPU PATCH 08/11] drm/msm/dpu: remove power management code from dpu_power_handle
Mdss main power supply (mdss_gdsc) is implemented as a
generic power domain and mdss top level wrapper device
manage it via runtime_pm. Remove custom power management
code from dpu_power_handle.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/dpu_power_handle.c | 190 +
drivers/gpu/drm/msm/dpu_power_handle.h | 2 -
2 files changed, 1 insertion(+), 191 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c
b/drivers/gpu/drm/msm/dpu_power_handle.c
index 17bae4b..909fbb8 100644
--- a/drivers/gpu/drm/msm/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/dpu_power_handle.c
@@ -101,150 +101,6 @@ void dpu_power_client_destroy(struct dpu_power_handle
*phandle,
}
}
-static int dpu_power_parse_dt_supply(struct platform_device *pdev,
- struct dss_module_power *mp)
-{
- int i = 0, rc = 0;
- u32 tmp = 0;
- struct device_node *of_node = NULL, *supply_root_node = NULL;
- struct device_node *supply_node = NULL;
-
- if (!pdev || !mp) {
- pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
- return -EINVAL;
- }
-
- of_node = pdev->dev.of_node;
-
- mp->num_vreg = 0;
- supply_root_node = of_get_child_by_name(of_node,
- "qcom,platform-supply-entries");
- if (!supply_root_node) {
- pr_debug("no supply entry present\n");
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node)
- mp->num_vreg++;
-
- if (mp->num_vreg == 0) {
- pr_debug("no vreg\n");
- return rc;
- }
-
- pr_debug("vreg found. count=%d\n", mp->num_vreg);
- mp->vreg_config = devm_kzalloc(>dev, sizeof(struct dss_vreg) *
- mp->num_vreg, GFP_KERNEL);
- if (!mp->vreg_config) {
- rc = -ENOMEM;
- return rc;
- }
-
- for_each_child_of_node(supply_root_node, supply_node) {
-
- const char *st = NULL;
-
- rc = of_property_read_string(supply_node,
- "qcom,supply-name", );
- if (rc) {
- pr_err("error reading name. rc=%d\n", rc);
- goto error;
- }
-
- strlcpy(mp->vreg_config[i].vreg_name, st,
- sizeof(mp->vreg_config[i].vreg_name));
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-min-voltage", );
- if (rc) {
- pr_err("error reading min volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].min_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-max-voltage", );
- if (rc) {
- pr_err("error reading max volt. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].max_voltage = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-enable-load", );
- if (rc) {
- pr_err("error reading enable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].enable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-disable-load", );
- if (rc) {
- pr_err("error reading disable load. rc=%d\n", rc);
- goto error;
- }
- mp->vreg_config[i].disable_load = tmp;
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-on-sleep", );
- if (rc)
- pr_debug("error reading supply pre sleep value.
rc=%d\n",
- rc);
-
- mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pre-off-sleep", );
- if (rc)
- pr_debug("error reading supply pre sleep value.
rc=%d\n",
- rc);
-
- mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
-
- rc = of_property_read_u32(supply_node,
- "qcom,supply-pos
[DPU PATCH 02/11] drm/msm/mdp5: subclass msm_mdss for mdp5
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
drivers/gpu/drm/msm/msm_drv.c | 23 +++--
drivers/gpu/drm/msm/msm_kms.h | 20 ++--
3 files changed, 110 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7..88190e3 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
#include "msm_drv.h"
#include "mdp5_kms.h"
-/*
- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
- struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+ struct msm_mdss base;
void __iomem *mmio, *vbif;
@@ -41,22 +39,22 @@ struct msm_mdss {
} irqcontroller;
};
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
{
- msm_writel(data, mdss->mmio + reg);
+ msm_writel(data, mdp5_mdss->mmio + reg);
}
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
{
- return msm_readl(mdss->mmio + reg);
+ return msm_readl(mdp5_mdss->mmio + reg);
}
static irqreturn_t mdss_irq(int irq, void *arg)
{
- struct msm_mdss *mdss = arg;
+ struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
- intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
+ intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
VERB("intr=%08x", intr);
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
- mdss->irqcontroller.domain, hwirq));
+ mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
static void mdss_hw_mask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
static void mdss_hw_unmask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
@@ -109,13 +107,13 @@ static void mdss_hw_unmask_irq(struct irq_data *irqd)
static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- struct msm_mdss *mdss = d->host_data;
+ struct mdp5_mdss *mdp5_mdss = d->host_data;
if (!(VALID_IRQS & (1 << hwirq)))
return -EPERM;
irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, mdss);
+ irq_set_chip_data(irq, mdp5_mdss);
return 0;
}
@@ -126,90 +124,99 @@ static int mdss_hw_irqdomain_map(struct irq_domain *d,
unsigned int irq,
};
-static int mdss_irq_domain_init(struct msm_mdss *mdss)
+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
{
- struct device *dev = mdss->dev->dev;
+ struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,
- mdss);
+ mdp5_mdss);
if (!d) {
dev_err(dev, "mdss irq domain add failed\n");
return -ENXIO;
}
- mdss->irqcontroller.enabled_mask = 0;
- mdss->irqcontroller.domain = d;
+ mdp5_mdss->irqcontroller.enabled_mask = 0;
+ mdp5_mdss->irqcontroller.domain =
[DPU PATCH 10/11] drm/msm/dpu: use runtime_pm calls in dpu_dbg
Currently, msm_drv was creating dpu_power_handle client
which was used by dpu_dbg module to enable power resources
before register debug dumping.
Now since, the mdss core power resource handling is
implemented via runtime_pm and same has been removed
from dpu_power_handle. Remove dpu_power_handle dependency
from msm_drv and use pm_runtime_get/put_sync calls from
dpu_dbg module on dpu_mdss top level device for core,
ahb clock and power resource management (for register access).
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 4 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/dpu_dbg.c | 18 +++---
drivers/gpu/drm/msm/dpu_dbg.h | 13 ++---
drivers/gpu/drm/msm/msm_drv.c | 27 +--
drivers/gpu/drm/msm/msm_drv.h | 1 -
7 files changed, 12 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index d1364fa..e2e7c06 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -676,10 +676,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk)
{
- if (!perf || !dev || !catalog || !phandle || !pclient || !core_clk) {
+ if (!perf || !dev || !catalog || !phandle || !core_clk) {
DPU_ERROR("invalid parameters\n");
return -EINVAL;
}
@@ -687,7 +686,6 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
perf->dev = dev;
perf->catalog = catalog;
perf->phandle = phandle;
- perf->pclient = pclient;
perf->core_clk = core_clk;
perf->max_core_clk_rate = core_clk->max_rate;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 9c1a719..cde48df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
@@ -53,7 +53,6 @@ struct dpu_core_perf_tune {
* @debugfs_root: top level debug folder
* @catalog: Pointer to catalog configuration
* @phandle: Pointer to power handler
- * @pclient: Pointer to power client
* @core_clk: Pointer to core clock structure
* @core_clk_rate: current core clock rate
* @max_core_clk_rate: maximum allowable core clock rate
@@ -68,7 +67,6 @@ struct dpu_core_perf {
struct dentry *debugfs_root;
struct dpu_mdss_cfg *catalog;
struct dpu_power_handle *phandle;
- struct dpu_power_client *pclient;
struct dss_clk *core_clk;
u64 core_clk_rate;
u64 max_core_clk_rate;
@@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
* @dev: Pointer to drm device
* @catalog: Pointer to catalog
* @phandle: Pointer to power handle
- * @pclient: Pointer to power client
* @core_clk: pointer to core clock
*/
int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
- struct dpu_power_client *pclient,
struct dss_clk *core_clk);
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index f6511c9..67bef32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1728,8 +1728,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
#endif
rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
- >phandle, priv->pclient,
- _dpu_kms_get_clk(dpu_kms, "core_clk"));
+ >phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
if (rc) {
DPU_ERROR("failed to init perf %d\n", rc);
goto perf_err;
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 4a39b82..27538bc 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "dpu_dbg.h"
#include "disp/dpu1/dpu_hw_catalog.h"
@@ -167,7 +168,6 @@ struct dpu_dbg_vbif_debug_bus {
* @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @power_ctrl: callback structure for enabling power for reading hw registers
* @req_dump_blks: list of blocks requested for dumping
* @panic_on_err: whether to kernel panic after triggering dump via debugfs
*
[DPU PATCH 05/11] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address
The dpu sub-block offsets were defined wrt mdss base address
instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog
offsets for all dpu sub blocks wrt dpu base address.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c5b370f..2fd3254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -80,7 +80,7 @@
static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
- .base = 0x1000, .len = 0x45C,
+ .base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
.has_dest_scaler = true,
@@ -111,27 +111,27 @@
static struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
- .base = 0x2000, .len = 0xE4,
+ .base = 0x1000, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_1", .id = CTL_1,
- .base = 0x2200, .len = 0xE4,
+ .base = 0x1200, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_2", .id = CTL_2,
- .base = 0x2400, .len = 0xE4,
+ .base = 0x1400, .len = 0xE4,
.features = 0
},
{
.name = "ctl_3", .id = CTL_3,
- .base = 0x2600, .len = 0xE4,
+ .base = 0x1600, .len = 0xE4,
.features = 0
},
{
.name = "ctl_4", .id = CTL_4,
- .base = 0x2800, .len = 0xE4,
+ .base = 0x1800, .len = 0xE4,
.features = 0
},
};
@@ -211,21 +211,21 @@
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+ SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+ SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+ SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+ SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+ SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+ SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+ SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+ SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
};
@@ -252,17 +252,17 @@
.lm_pair_mask = (1 << _lmpair) \
}
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+ LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+ LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+ LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
DS_MAX, PINGPONG_2, LM_5),
LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+ LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
DS_MAX, PINGPONG_3, LM_2),
};
@@ -270,7 +270,7 @@
* DSPP sub blocks config
*/
static struct dpu_dspp_top_cfg sdm845_dspp_top = {
- .name = "dspp_top", .base = 0x1300, .len = 0xc
+ .name = "dspp_top", .base = 0x300, .len = 0xc
};
static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
@@ -304,10 +304,10 @@
}
static struct dpu_dspp_cfg sdm845_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x55000),
- DSPP_BLK("dspp_1", DS
[DPU PATCH 06/11] drm/msm/dpu: use runtime_pm calls on dpu device
The dpu driver implements runtime_pm support for managing
dpu specific resources like - clocks, bus bandwidth etc.
Use pm_runtime_get/put_sync calls on dpu device.
The common clocks and power management for all child nodes
(mdp5/dpu, dsi, dp etc) is done by parent MDSS device/driver
via runtime_pm due to parent child relationship.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 8 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 45 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c| 6 ++--
5 files changed, 31 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 977adc4..5c5cc56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -452,10 +452,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
spin_lock_init(_kms->irq_obj.cb_lock);
@@ -496,7 +496,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
}
priv = dpu_kms->dev->dev_private;
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
+ pm_runtime_get_sync(_kms->pdev->dev);
for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
if (atomic_read(_kms->irq_obj.enable_counts[i]) ||
!list_empty(_kms->irq_obj.irq_cb_tbl[i]))
@@ -504,7 +504,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
dpu_clear_all_irqs(dpu_kms);
dpu_disable_all_irqs(dpu_kms);
- dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
+ pm_runtime_put_sync(_kms->pdev->dev);
kfree(dpu_kms->irq_obj.irq_cb_tbl);
kfree(dpu_kms->irq_obj.enable_counts);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 48920b05..e2d2e32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -86,8 +86,12 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc
*dpu_crtc, bool enable)
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
/**
@@ -2250,7 +2254,6 @@ static int _dpu_crtc_vblank_enable_no_lock(
/* drop lock since power crtc cb may try to re-acquire lock */
mutex_unlock(_crtc->crtc_lock);
- pm_runtime_get_sync(dev->dev);
ret = _dpu_crtc_power_enable(dpu_crtc, true);
mutex_lock(_crtc->crtc_lock);
if (ret)
@@ -2580,7 +2583,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
/* disable clk & bw control until clk & bw properties are set */
cstate->bw_control = false;
cstate->bw_split_vote = false;
- pm_runtime_put_sync(crtc->dev->dev);
mutex_unlock(_crtc->crtc_lock);
}
@@ -2611,8 +2613,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
return;
}
- pm_runtime_get_sync(crtc->dev->dev);
-
drm_for_each_encoder(encoder, crtc->dev) {
if (encoder->crtc != crtc)
continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4386360..298a6ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -268,8 +268,12 @@ static inline int _dpu_encoder_power_enable(struct
dpu_encoder_virt *dpu_enc,
dpu_kms = to_dpu_kms(priv->kms);
- return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
- enable);
+ if (enable)
+ pm_runtime_get_sync(_kms->pdev->dev);
+ else
+ pm_runtime_put_sync(_kms->pdev->dev);
+
+ return 0;
}
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
@@ -796,10 +800,8 @@ static void _dpu_encoder_resource_c
[DPU PATCH 07/11] drm/msm/dpu: remove clock management code from dpu_power_handle
MDSS and dpu drivers manage their respective clocks via
runtime_pm. Remove custom clock management code from
dpu_power_handle.
Also dpu core clock management code is restricted to
dpu_core_perf module.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 44 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 32 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 9 +
drivers/gpu/drm/msm/dpu_power_handle.c | 195 +
drivers/gpu/drm/msm/dpu_power_handle.h | 40 -
7 files changed, 69 insertions(+), 264 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 981f77f..d1364fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -365,6 +365,20 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
}
}
+static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
+{
+ struct dss_clk *core_clk = kms->perf.core_clk;
+ int rc = -EINVAL;
+
+ if (core_clk->max_rate && (rate > core_clk->max_rate))
+ rate = core_clk->max_rate;
+
+ core_clk->rate = rate;
+ rc = msm_dss_clk_set_rate(core_clk, 1);
+
+ return rc;
+}
+
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
{
u64 clk_rate = kms->perf.perf_tune.min_core_clk;
@@ -376,7 +390,8 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms
*kms)
dpu_cstate = to_dpu_crtc_state(crtc->state);
clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
clk_rate);
- clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
+ clk_rate = clk_round_rate(kms->perf.core_clk->clk,
+ clk_rate);
}
}
@@ -484,15 +499,11 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- /* Temp change to avoid crash in clk_set_rate API. */
-#ifdef QCOM_DPU_SET_CLK
- if (dpu_power_clk_set_rate(>phandle,
- kms->perf.clk_name, clk_rate)) {
+ if (_dpu_core_perf_set_core_clk_rate(kms, clk_rate)) {
DPU_ERROR("failed to set %s clock rate %llu\n",
- kms->perf.clk_name, clk_rate);
+ kms->perf.core_clk->clk_name, clk_rate);
return;
}
-#endif
kms->perf.core_clk_rate = clk_rate;
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
@@ -656,7 +667,6 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
dpu_core_perf_debugfs_destroy(perf);
perf->max_core_clk_rate = 0;
perf->core_clk = NULL;
- perf->clk_name = NULL;
perf->phandle = NULL;
perf->catalog = NULL;
perf->dev = NULL;
@@ -667,9 +677,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
struct dpu_mdss_cfg *catalog,
struct dpu_power_handle *phandle,
struct dpu_power_client *pclient,
- char *clk_name)
+ struct dss_clk *core_clk)
{
- if (!perf || !dev || !catalog || !phandle || !pclient || !clk_name) {
+ if (!perf || !dev || !catalog || !phandle || !pclient || !core_clk) {
DPU_ERROR("invalid parameters\n");
return -EINVAL;
}
@@ -678,23 +688,13 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
perf->catalog = catalog;
perf->phandle = phandle;
perf->pclient = pclient;
- perf->clk_name = clk_name;
+ perf->core_clk = core_clk;
- perf->core_clk = dpu_power_clk_get_clk(phandle, clk_name);
- if (!perf->core_clk) {
- DPU_ERROR("invalid core clk\n");
- goto err;
- }
-
- perf->max_core_clk_rate = dpu_power_clk_get_max_rate(phandle, clk_name);
+ perf->max_core_clk_rate = core_clk->max_rate;
if (!perf->max_core_clk_rate) {
DPU_DEBUG("optional max core clk rate, use default\n");
perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
}
return 0;
-
-err:
- dpu_core_perf_destroy(perf);
- return -ENODEV;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 1965ff5..9c1a719 100644
--- a/d
[DPU PATCH 04/11] drm/msm/dpu: create new platform driver for dpu device
Current MSM display controller HW matches a tree like
hierarchy where MDSS top level wrapper is parent device
and mdp5/dpu, dsi, dp are child devices.
Each child device like mdp5, dsi etc. have a separate driver,
but currently dpu handling is tied to a single driver which
was managing both mdss and dpu resources.
Inorder to have the cleaner one to one device and driver
association, this change adds a new platform_driver for dpu
child device node which implements the kms functionality.
The dpu driver implements runtime_pm support for managing clocks
and bus bandwidth etc.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 251 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 +
drivers/gpu/drm/msm/msm_drv.c | 2 +
drivers/gpu/drm/msm/msm_drv.h | 3 +
4 files changed, 214 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e4ab753..2cd51fc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1030,14 +1030,13 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms,
unsigned long rate,
return rate;
}
-static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
- struct platform_device *pdev)
+static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
{
struct drm_device *dev;
struct msm_drm_private *priv;
int i;
- if (!dpu_kms || !pdev)
+ if (!dpu_kms)
return;
dev = dpu_kms->dev;
@@ -1091,15 +1090,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
dpu_kms->core_client = NULL;
if (dpu_kms->vbif[VBIF_NRT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_NRT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
dpu_kms->vbif[VBIF_NRT] = NULL;
if (dpu_kms->vbif[VBIF_RT])
- msm_iounmap(pdev, dpu_kms->vbif[VBIF_RT]);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
if (dpu_kms->mmio)
- msm_iounmap(pdev, dpu_kms->mmio);
+ msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
dpu_reg_dma_deinit();
@@ -1172,8 +1171,6 @@ int dpu_kms_mmu_attach(struct dpu_kms *dpu_kms, bool
secure_only)
static void dpu_kms_destroy(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms;
- struct drm_device *dev;
- struct platform_device *platformdev;
if (!kms) {
DPU_ERROR("invalid kms\n");
@@ -1181,20 +1178,7 @@ static void dpu_kms_destroy(struct msm_kms *kms)
}
dpu_kms = to_dpu_kms(kms);
- dev = dpu_kms->dev;
- if (!dev) {
- DPU_ERROR("invalid device\n");
- return;
- }
-
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- return;
- }
-
- _dpu_kms_hw_destroy(dpu_kms, platformdev);
- kfree(dpu_kms);
+ _dpu_kms_hw_destroy(dpu_kms);
}
static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
@@ -1550,7 +1534,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
struct dpu_kms *dpu_kms;
struct drm_device *dev;
struct msm_drm_private *priv;
- struct platform_device *platformdev;
int i, rc = -EINVAL;
if (!kms) {
@@ -1565,34 +1548,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto end;
}
- platformdev = to_platform_device(dev->dev);
- if (!platformdev) {
- DPU_ERROR("invalid platform device\n");
- goto end;
- }
-
priv = dev->dev_private;
if (!priv) {
DPU_ERROR("invalid private data\n");
goto end;
}
- dpu_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
+ dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys");
if (IS_ERR(dpu_kms->mmio)) {
rc = PTR_ERR(dpu_kms->mmio);
DPU_ERROR("mdp register memory map failed: %d\n", rc);
dpu_kms->mmio = NULL;
goto error;
}
- DRM_INFO("mapped mdp address space @%p\n", dpu_kms->mmio);
- dpu_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
+ DRM_INFO("mapped dpu address space @%p\n", dpu_kms->mmio);
+ dpu_kms->mmio_len = msm_iomap_size(dpu_kms->pdev, "mdp_phys");
rc = dpu_dbg_reg_register_base(DPU_DBG_NAME, dpu_kms->mmio,
dpu
[DPU PATCH 00/11] Refactor DPU device/driver hierarchy and add runtime_pm support
SoCs containing mdp5 or dpu have a MDSS top level wrapper which includes sub-blocks as mdp5/dpu, dsi, dp, hdmi etc. The MDSS top level wrapper manages common resources like common clocks, main power supply and interrupts for its sub-blocks. But current dpu driver implementation is based on a flat device hierarchy where MDSS/DPU HW blocks were represented by single device and DSI/DP etc. are represented as independent devices w/o any relationships b/t these nodes which doesn't model the HW associations precisely. A minimal MDSS and DPU controller device separation is done in following patch series [1] but currently both these devices match to a single driver which is getting probed two times and all the resources are still tied to DPU device. Moreover, all the power resource management in DPU driver is part of power_handle module which manages these resources via a custom implementation. Irq domain handling is part of DPU device, due to lack of a dedicated driver for MDSS top level wrapper device. This patch series aims at adding separate drivers for MDSS top level wrapper device and DPU child device. MDP5 device/driver is used as a reference for this refactoring effort. Both the drivers implement runtime_pm support for their power resource management. Child nodes can control common resources managed by parent device due to parent child relationship defined in dt. The top level MDSS device acts as an interrupt controller and manages hwirq mappings for its child devices. Inorder to add MDP5 and DPU specific MDSS driver implementation, this patch series also subclasses existing msm_mdss define. A helper interface (msm_mdss_funcs) is added to invoke the platform specific implementations. This change also corrects hw catalog offsets for all sub blocks present within DPU device. The offset are now defined wrt DPU base address (instead of using MDSS base address). Clock and Power handling code have been removed from dpu_power_handle since each device manages it's resources via runtime_pm. Now, since dpu_power_handle manages only bus scaling and power enable/disable notifications and it's usage is restricted to DPU driver only, moved dpu_power_handle code to DPU folder. This patch series depends on [1]. 1 - https://lists.freedesktop.org/archives/freedreno/2018-April/002354.html Rajesh Yadav (11): drm/msm: remove pm_runtime_enable call from msm_drv drm/msm/mdp5: subclass msm_mdss for mdp5 drm/msm/dpu: add MDSS top level driver for dpu drm/msm/dpu: create new platform driver for dpu device drm/msm/dpu: update dpu sub-block offsets wrt dpu base address drm/msm/dpu: use runtime_pm calls on dpu device drm/msm/dpu: remove clock management code from dpu_power_handle drm/msm/dpu: remove power management code from dpu_power_handle drm/msm/dp: remove dpu_power_handle calls from dp driver drm/msm/dpu: use runtime_pm calls in dpu_dbg drm/msm/dpu: move dpu_power_handle to dpu folder drivers/gpu/drm/msm/Makefile |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 106 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 51 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |2 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 17 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 77 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 47 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 - drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c| 48 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 354 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 301 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 694 + drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 +-- drivers/gpu/drm/msm/dp/dp_power.c | 32 +- drivers/gpu/drm/msm/dp/dp_power.h |4 +- drivers/gpu/drm/msm/dpu_dbg.c | 18 +- drivers/gpu/drm/msm/dpu_dbg.h | 13 +- drivers/gpu/drm/msm/dpu_io_util.c | 55 + drivers/gpu/drm/msm/dpu_power_handle.c | 1075 drivers/gpu/drm/msm/dpu_power_handle.h | 330 -- drivers/gpu/drm/msm/msm_drv.c | 86 +- drivers/gpu/drm/msm/msm_drv.h | 10 +- drivers/gpu/drm/msm/msm_kms.h | 22 +- include/linux/dpu_io_util.h|2 + 32 files changed
[DPU PATCH 03/11] drm/msm/dpu: add MDSS top level driver for dpu
SoCs containing dpu have a MDSS top level wrapper
which includes sub-blocks as dpu, dsi, phy, dp etc.
MDSS top level wrapper manages common resources like
common clocks, power and irq for its sub-blocks.
Currently, in dpu driver, all the power resource
management is part of power_handle which manages
these resources via a custom implementation. And
the resource relationships are not modelled properly
in dt. Moreover the irq domain handling code is part
of dpu device (which is a child device) due to lack
of a dedicated driver for MDSS top level wrapper
device.
This change adds dpu_mdss top level driver to handle
common clock like - core clock, ahb clock
(for register access), main power supply (i.e. gdsc)
and irq management.
The top level mdss device/driver acts as an interrupt
controller and manage hwirq mapping for its child
devices.
It implements runtime_pm support for resource management.
Child nodes can control these resources via runtime_pm
get/put calls on their corresponding devices due to parent
child relationship defined in dt.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 97 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 9 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 7 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 29 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 11 -
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 48 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 301 ++
drivers/gpu/drm/msm/dpu_io_util.c | 55
drivers/gpu/drm/msm/msm_drv.c | 26 +-
drivers/gpu/drm/msm/msm_drv.h | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 2 +
include/linux/dpu_io_util.h | 2 +
16 files changed, 390 insertions(+), 222 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d7558ed..d9826c1 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -81,6 +81,7 @@ msm-y := \
disp/dpu1/dpu_reg_dma.o \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
+ disp/dpu1/dpu_mdss.o \
dpu_dbg.o \
dpu_io_util.o \
dpu_dbg_evtlog.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index fe33013..977adc4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -515,103 +515,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
dpu_kms->irq_obj.total_irqs = 0;
}
-static void dpu_core_irq_mask(struct irq_data *irqd)
-{
- struct dpu_kms *dpu_kms;
-
- if (!irqd || !irq_data_get_irq_chip_data(irqd)) {
- DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
- return;
- }
- dpu_kms = irq_data_get_irq_chip_data(irqd);
-
- /* memory barrier */
- smp_mb__before_atomic();
- clear_bit(irqd->hwirq, _kms->irq_controller.enabled_mask);
- /* memory barrier */
- smp_mb__after_atomic();
-}
-
-static void dpu_core_irq_unmask(struct irq_data *irqd)
-{
- struct dpu_kms *dpu_kms;
-
- if (!irqd || !irq_data_get_irq_chip_data(irqd)) {
- DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
- return;
- }
- dpu_kms = irq_data_get_irq_chip_data(irqd);
-
- /* memory barrier */
- smp_mb__before_atomic();
- set_bit(irqd->hwirq, _kms->irq_controller.enabled_mask);
- /* memory barrier */
- smp_mb__after_atomic();
-}
-
-static struct irq_chip dpu_core_irq_chip = {
- .name = "dpu",
- .irq_mask = dpu_core_irq_mask,
- .irq_unmask = dpu_core_irq_unmask,
-};
-
-static int dpu_core_irqdomain_map(struct irq_domain *domain,
- unsigned int irq, irq_hw_number_t hwirq)
-{
- struct dpu_kms *dpu_kms;
- int rc;
-
- if (!domain || !domain->host_data) {
- DPU_ERROR("invalid parameters domain %d\n", domain != NULL);
- return -EINVAL;
- }
- dpu_kms = domain->host_data;
-
- irq_set_chip_and_handler(irq, _core_irq_chip, handle_level_irq);
- rc = irq_set_chip_data(irq, dpu_kms);
-
- return rc;
-}
-
-static const struct irq_domain_ops dpu_core_irqdomain_ops = {
- .map = dpu_core_irqdomain_map,
- .xlate = irq_domain_xlate_onecell,
-};
-
-int dpu_core_irq_domain_add(struct dpu_kms *dpu_kms)
-{
- struct device *dev;
- struct ir
[DPU PATCH 01/11] drm/msm: remove redundant pm_runtime_enable call from msm_drv
MDSS top level device includes the common power resources and it's corresponding driver (i.e. mdp5_mdss) handles call to enable/disable runtime_pm for enabling these resources. Remove redundant pm_runtime_enable call from msm_drv. Signed-off-by: Rajesh Yadav <rya...@codeaurora.org> --- drivers/gpu/drm/msm/msm_drv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ebc40a9..9bb436f 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -581,7 +581,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto fail; } priv->kms = kms; - pm_runtime_enable(dev); /** * Since kms->funcs->hw_init(kms) might call -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v3 1/2] dt-bindings: msm/disp: Remove DPU RSC device bindings
MSM Display controller includes RSC (Resource Coordinator)
HW block which can control DPU power resources without
DPU driver intervention.
Removing DPU RSC device/driver support till the RSC
dependencies make their way upstream.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
.../devicetree/bindings/display/msm/dpu-rsc.txt| 96 --
1 file changed, 96 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
b/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
deleted file mode 100644
index f5fbcda..000
--- a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Qualcomm Technologies, Inc. DPU RSC
-
-Snapdragon Display Engine implements display rsc to driver
-display core to different modes for power saving
-
-Required properties
-- compatible: Must be "qcom,dpu-rsc"
-- reg: Offset and length of the register set for
- the device.
-- reg-names: Names to refer to register sets related
- to this device
-
-Optional properties:
-- clocks: List of phandles for clock device nodes
- needed by the device.
-- clock-names: List of clock names needed by the device.
-- vdd-supply: phandle for vdd regulator device node.
-- qcom,dpu-rsc-version:U32 property represents the rsc
version. It helps to
- select correct sequence for dpu rsc based on
version.
-- qcom,dpu-dram-channels: U32 property represents the number of channels
in the
- Bus memory controller.
-- qcom,dpu-num-nrt-paths: U32 property represents the number of
non-realtime
- paths in each Bus Scaling Usecase. This value
depends on
- number of AXI ports that are dedicated to
non-realtime VBIF
- for particular chipset.
- These paths must be defined after rt-paths in
- "qcom,msm-bus,vectors-KBps" vector request.
-
-Bus Scaling Subnodes:
-- qcom,dpu-data-bus: Property to provide Bus scaling for data bus
access for
- dpu blocks.
-- qcom,dpu-llcc-bus: Property to provide Bus scaling for data bus
access for
- mnoc to llcc.
-- qcom,dpu-ebi-bus:Property to provide Bus scaling for data bus
access for
- llcc to ebi.
-
-Bus Scaling Data:
-- qcom,msm-bus,name: String property describing client name.
-- qcom,msm-bus,active-only:Boolean context flag for requests in active or
- dual (active & sleep) contex
-- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
- defined in the vectors property.
-- qcom,msm-bus,num-paths: This represents the number of paths in each
- Bus Scaling Usecase.
-- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
- of (src, dst, ab, ib) which is defined at
-
Documentation/devicetree/bindings/arm/msm/msm_bus.txt
- * Current values of src & dst are defined at
- include/linux/msm-bus-board.h
-Example:
- dpu_rscc {
- cell-index = <0>;
- compatible = "qcom,dpu-rsc";
- reg = <0xaf2 0x1c44>,
- <0xaf3 0x3fd4>;
- reg-names = "drv", "wrapper";
- clocks = <_mmss clk_mdss_ahb_clk>,
- <_mmss clk_mdss_axi_clk>;
- clock-names = "iface_clk", "bus_clk";
- vdd-supply = <_mdss>;
-
- qcom,dpu-rsc-version = <1>;
- qcom,dpu-dram-channels = <2>;
- qcom,dpu-num-nrt-paths = <1>;
-
- qcom,dpu-data-bus {
- qcom,msm-bus,name = "dpu_rsc";
- qcom,msm-bus,active-only;
- qcom,msm-bus,num-cases = <3>;
- qcom,msm-bus,num-paths = <2>;
- qcom,msm-bus,vectors-KBps =
- <22 512 0 0>, <23 512 0 0>,
- <22 512 0 640>, <23 512 0 640>,
- <22 512 0 640>, <23 512 0 640>;
- };
- qcom,dpu-llcc-bus {
- qcom,msm-bus,name = "dpu_rsc_llcc";
-
[DPU PATCH v3 0/2] Remove DPU RSC support
MSM display controller hardware (DPU) has an inbuilt RSC (Resource Coordinator) HW block which can control power resources and bus bandwidth voting based on frame timing parameters without DPU driver intervention. Downstream driver relies on RSC driver for controlling these resources (via RSC HW block) for better power benefits. Removing RSC device/driver support till the RSC dependencies make their way upstream. In absence of RSC HW, DPU driver controls these resources currently via a custom implementation for power management. Next, we will work on moving the power resource management using runtime_pm. Corresponding devicetree binding are also removed. Details for DPU driver upstreaming: https://lists.freedesktop.org/archives/freedreno/2018-February/001678.html Changes in v3: - Added more details to commit message and cover letter (Daniel Vetter) Changes in v2: - Remove last reference to dpu_power_rsc_update - Add DPU PATCH tag for better filtering - Rebase on tip of for-next-staging Rajesh Yadav (2): dt-bindings: msm/disp: Remove DPU RSC device bindings drm/msm: Remove RSC support from DPU driver .../devicetree/bindings/display/msm/dpu-rsc.txt| 96 -- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 130 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |6 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 242 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|7 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |3 - drivers/gpu/drm/msm/dpu_dbg.c | 27 - drivers/gpu/drm/msm/dpu_dbg.h | 10 - drivers/gpu/drm/msm/dpu_power_handle.c | 73 +- drivers/gpu/drm/msm/dpu_power_handle.h |4 - drivers/gpu/drm/msm/dpu_rsc.c | 1367 drivers/gpu/drm/msm/dpu_rsc_hw.c | 818 drivers/gpu/drm/msm/dpu_rsc_priv.h | 191 --- include/linux/dpu_rsc.h| 302 - 18 files changed, 42 insertions(+), 3278 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt delete mode 100644 drivers/gpu/drm/msm/dpu_rsc.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_hw.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_priv.h delete mode 100644 include/linux/dpu_rsc.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH v2 1/2] dt-bindings: msm/disp: Remove DPU RSC device bindings
Display controller's power resources and bus
bandwidth voting is controlled by DPU device.
Remove DPU RSC (hardware block for DPU power
resource control) device support.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
.../devicetree/bindings/display/msm/dpu-rsc.txt| 96 --
1 file changed, 96 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
b/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
deleted file mode 100644
index f5fbcda..000
--- a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Qualcomm Technologies, Inc. DPU RSC
-
-Snapdragon Display Engine implements display rsc to driver
-display core to different modes for power saving
-
-Required properties
-- compatible: Must be "qcom,dpu-rsc"
-- reg: Offset and length of the register set for
- the device.
-- reg-names: Names to refer to register sets related
- to this device
-
-Optional properties:
-- clocks: List of phandles for clock device nodes
- needed by the device.
-- clock-names: List of clock names needed by the device.
-- vdd-supply: phandle for vdd regulator device node.
-- qcom,dpu-rsc-version:U32 property represents the rsc
version. It helps to
- select correct sequence for dpu rsc based on
version.
-- qcom,dpu-dram-channels: U32 property represents the number of channels
in the
- Bus memory controller.
-- qcom,dpu-num-nrt-paths: U32 property represents the number of
non-realtime
- paths in each Bus Scaling Usecase. This value
depends on
- number of AXI ports that are dedicated to
non-realtime VBIF
- for particular chipset.
- These paths must be defined after rt-paths in
- "qcom,msm-bus,vectors-KBps" vector request.
-
-Bus Scaling Subnodes:
-- qcom,dpu-data-bus: Property to provide Bus scaling for data bus
access for
- dpu blocks.
-- qcom,dpu-llcc-bus: Property to provide Bus scaling for data bus
access for
- mnoc to llcc.
-- qcom,dpu-ebi-bus:Property to provide Bus scaling for data bus
access for
- llcc to ebi.
-
-Bus Scaling Data:
-- qcom,msm-bus,name: String property describing client name.
-- qcom,msm-bus,active-only:Boolean context flag for requests in active or
- dual (active & sleep) contex
-- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
- defined in the vectors property.
-- qcom,msm-bus,num-paths: This represents the number of paths in each
- Bus Scaling Usecase.
-- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
- of (src, dst, ab, ib) which is defined at
-
Documentation/devicetree/bindings/arm/msm/msm_bus.txt
- * Current values of src & dst are defined at
- include/linux/msm-bus-board.h
-Example:
- dpu_rscc {
- cell-index = <0>;
- compatible = "qcom,dpu-rsc";
- reg = <0xaf2 0x1c44>,
- <0xaf3 0x3fd4>;
- reg-names = "drv", "wrapper";
- clocks = <_mmss clk_mdss_ahb_clk>,
- <_mmss clk_mdss_axi_clk>;
- clock-names = "iface_clk", "bus_clk";
- vdd-supply = <_mdss>;
-
- qcom,dpu-rsc-version = <1>;
- qcom,dpu-dram-channels = <2>;
- qcom,dpu-num-nrt-paths = <1>;
-
- qcom,dpu-data-bus {
- qcom,msm-bus,name = "dpu_rsc";
- qcom,msm-bus,active-only;
- qcom,msm-bus,num-cases = <3>;
- qcom,msm-bus,num-paths = <2>;
- qcom,msm-bus,vectors-KBps =
- <22 512 0 0>, <23 512 0 0>,
- <22 512 0 640>, <23 512 0 640>,
- <22 512 0 640>, <23 512 0 640>;
- };
- qcom,dpu-llcc-bus {
- qcom,msm-bus,name = "dpu_rsc_llcc";
- qcom,msm-bus,active-only
[DPU PATCH v2 0/2] Remove DPU RSC support
MSM display controller hardware (DPU) has an inbuilt RSC block which can control power resources and bus bandwidth voting based on frame timing parameters w/o DPU driver intervention. In absence of RSC HW, DPU driver controls these resources. Downstream driver relies on RSC driver for controlling these resources (via RSC HW block) for better power benefits. Since, DPU driver can control these resources, removing RSC driver support. Corresponding devicetree binding are also removed. Details for DPU driver upstreaming: https://lists.freedesktop.org/archives/freedreno/2018-February/001678.html Changes in v2: - Remove last reference to dpu_power_rsc_update - Add DPU PATCH tag for better filtering - Rebase on tip of for-next-staging Rajesh Yadav (2): dt-bindings: msm/disp: Remove DPU RSC device bindings drm/msm: Remove RSC support from DPU driver .../devicetree/bindings/display/msm/dpu-rsc.txt| 96 -- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 130 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |6 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 242 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|7 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |3 - drivers/gpu/drm/msm/dpu_dbg.c | 27 - drivers/gpu/drm/msm/dpu_dbg.h | 10 - drivers/gpu/drm/msm/dpu_power_handle.c | 73 +- drivers/gpu/drm/msm/dpu_power_handle.h |4 - drivers/gpu/drm/msm/dpu_rsc.c | 1367 drivers/gpu/drm/msm/dpu_rsc_hw.c | 818 drivers/gpu/drm/msm/dpu_rsc_priv.h | 191 --- include/linux/dpu_rsc.h| 302 - 18 files changed, 42 insertions(+), 3278 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt delete mode 100644 drivers/gpu/drm/msm/dpu_rsc.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_hw.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_priv.h delete mode 100644 include/linux/dpu_rsc.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[DPU PATCH 3/3] drm/msm/dsi-staging: Gate bus scale code
DSI driver relies on downstream bus scaling
driver (msm_bus) for bus bandwidth voting.
Gate the bus bandwidth voting code under
CONFIG_QCOM_BUS_SCALING.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c | 8
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c| 7 ++-
drivers/gpu/drm/msm/dsi-staging/dsi_phy.c | 2 ++
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
index 919de1e..047f759 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
@@ -17,7 +17,9 @@
#include
#include "dsi_clk.h"
+#ifdef CONFIG_QCOM_BUS_SCALING
#include
+#endif
struct dsi_core_clks {
struct dsi_core_clk_info clks;
@@ -226,6 +228,7 @@ int dsi_core_clk_start(struct dsi_core_clks *c_clks)
}
}
+#ifdef CONFIG_QCOM_BUS_SCALING
if (c_clks->bus_handle) {
rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 1);
if (rc) {
@@ -233,11 +236,14 @@ int dsi_core_clk_start(struct dsi_core_clks *c_clks)
goto error_disable_mmss_clk;
}
}
+#endif
return rc;
+#ifdef CONFIG_QCOM_BUS_SCALING
error_disable_mmss_clk:
if (c_clks->clks.core_mmss_clk)
clk_disable_unprepare(c_clks->clks.core_mmss_clk);
+#endif
error_disable_bus_clk:
if (c_clks->clks.bus_clk)
@@ -259,6 +265,7 @@ int dsi_core_clk_stop(struct dsi_core_clks *c_clks)
{
int rc = 0;
+#ifdef CONFIG_QCOM_BUS_SCALING
if (c_clks->bus_handle) {
rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 0);
if (rc) {
@@ -266,6 +273,7 @@ int dsi_core_clk_stop(struct dsi_core_clks *c_clks)
return rc;
}
}
+#endif
if (c_clks->clks.core_mmss_clk)
clk_disable_unprepare(c_clks->clks.core_mmss_clk);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index fae1b565..0ab92bb 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -17,7 +17,9 @@
#include
#include
#include
+#ifdef CONFIG_QCOM_BUS_SCALING
#include
+#endif
#include
#include
@@ -716,6 +718,7 @@ static int dsi_ctrl_axi_bus_client_init(struct
platform_device *pdev,
struct dsi_ctrl *ctrl)
{
int rc = 0;
+#ifdef CONFIG_QCOM_BUS_SCALING
struct dsi_ctrl_bus_scale_info *bus = >axi_bus_info;
bus->bus_scale_table = msm_bus_cl_get_pdata(pdev);
@@ -731,12 +734,13 @@ static int dsi_ctrl_axi_bus_client_init(struct
platform_device *pdev,
rc = -EINVAL;
pr_err("failed to register axi bus client\n");
}
-
+#endif
return rc;
}
static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl *ctrl)
{
+#ifdef CONFIG_QCOM_BUS_SCALING
struct dsi_ctrl_bus_scale_info *bus = >axi_bus_info;
if (bus->bus_handle) {
@@ -744,6 +748,7 @@ static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl
*ctrl)
bus->bus_handle = 0;
}
+#endif
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index c13e5bb..e712c61 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -17,7 +17,9 @@
#include
#include
#include
+#ifdef CONFIG_QCOM_BUS_SCALING
#include
+#endif
#include
#include "msm_drv.h"
--
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[DPU PATCH 2/3] drm/msm: Fix return type mismatch for dpu_kms_init
dpu_kms_init returns pointer to struct msm_kms but
incase of platform_get_irq() failure, int was returned.
Fix the return type to avoid compilation error.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8ef75f5..531efa9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -2027,7 +2027,7 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
DPU_ERROR("failed to get irq: %d\n", irq);
- return irq;
+ return ERR_PTR(irq);
}
priv = dev->dev_private;
--
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[DPU PATCH 1/3] drm/msm: Remove unused variables
Fix compilation errors due to unused variables.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1 -
4 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index bf46cf1..51cffc4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2587,7 +2587,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
- int ret, i;
+ int ret;
if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
DPU_ERROR("invalid crtc\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 2bc5894..3b1212b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -264,7 +264,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct
dpu_encoder_phys *phys_enc,
const struct msm_format *format;
int ret;
struct msm_gem_address_space *aspace;
- u32 fb_mode;
if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog ||
!phys_enc->connector) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 7186c64..8ef75f5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -426,7 +426,6 @@ static void dpu_kms_commit(struct msm_kms *kms, struct
drm_atomic_state *state)
{
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
- struct dpu_crtc_state *cstate;
int i;
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c657e6b..b11a918 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -2742,7 +2742,6 @@ static void dpu_plane_destroy_state(struct drm_plane
*plane,
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
struct dpu_plane_state *old_state;
- struct drm_property *drm_prop;
if (!plane) {
DPU_ERROR("invalid plane\n");
--
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[DPU PATCH 0/3] Minor fixes in MSM DPU driver
This patch series includes few minor fixes in MSM DPU and dsi-staging stagging driver which are identified while pulling in the patches to downstream tree. DPU driver is currently hosted at https://gitlab.freedesktop.org/seanpaul/dpu-staging Rajesh Yadav (3): drm/msm: Remove unused variables drm/msm: Fix return type mismatch for dpu_kms_init drm/msm/dsi-staging: Gate bus scale code drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1 - drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c | 8 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 7 ++- drivers/gpu/drm/msm/dsi-staging/dsi_phy.c | 2 ++ 7 files changed, 18 insertions(+), 6 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/2] dt-bindings: msm/disp: Remove DPU RSC device bindings
Display controller's power resources and bus
bandwidth voting is controlled by DPU device.
Remove DPU RSC (hardware block for DPU power
resource control) device support.
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
.../devicetree/bindings/display/msm/dpu-rsc.txt| 96 --
1 file changed, 96 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
b/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
deleted file mode 100644
index f5fbcda..000
--- a/Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Qualcomm Technologies, Inc. DPU RSC
-
-Snapdragon Display Engine implements display rsc to driver
-display core to different modes for power saving
-
-Required properties
-- compatible: Must be "qcom,dpu-rsc"
-- reg: Offset and length of the register set for
- the device.
-- reg-names: Names to refer to register sets related
- to this device
-
-Optional properties:
-- clocks: List of phandles for clock device nodes
- needed by the device.
-- clock-names: List of clock names needed by the device.
-- vdd-supply: phandle for vdd regulator device node.
-- qcom,dpu-rsc-version:U32 property represents the rsc
version. It helps to
- select correct sequence for dpu rsc based on
version.
-- qcom,dpu-dram-channels: U32 property represents the number of channels
in the
- Bus memory controller.
-- qcom,dpu-num-nrt-paths: U32 property represents the number of
non-realtime
- paths in each Bus Scaling Usecase. This value
depends on
- number of AXI ports that are dedicated to
non-realtime VBIF
- for particular chipset.
- These paths must be defined after rt-paths in
- "qcom,msm-bus,vectors-KBps" vector request.
-
-Bus Scaling Subnodes:
-- qcom,dpu-data-bus: Property to provide Bus scaling for data bus
access for
- dpu blocks.
-- qcom,dpu-llcc-bus: Property to provide Bus scaling for data bus
access for
- mnoc to llcc.
-- qcom,dpu-ebi-bus:Property to provide Bus scaling for data bus
access for
- llcc to ebi.
-
-Bus Scaling Data:
-- qcom,msm-bus,name: String property describing client name.
-- qcom,msm-bus,active-only:Boolean context flag for requests in active or
- dual (active & sleep) contex
-- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
- defined in the vectors property.
-- qcom,msm-bus,num-paths: This represents the number of paths in each
- Bus Scaling Usecase.
-- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
- of (src, dst, ab, ib) which is defined at
-
Documentation/devicetree/bindings/arm/msm/msm_bus.txt
- * Current values of src & dst are defined at
- include/linux/msm-bus-board.h
-Example:
- dpu_rscc {
- cell-index = <0>;
- compatible = "qcom,dpu-rsc";
- reg = <0xaf2 0x1c44>,
- <0xaf3 0x3fd4>;
- reg-names = "drv", "wrapper";
- clocks = <_mmss clk_mdss_ahb_clk>,
- <_mmss clk_mdss_axi_clk>;
- clock-names = "iface_clk", "bus_clk";
- vdd-supply = <_mdss>;
-
- qcom,dpu-rsc-version = <1>;
- qcom,dpu-dram-channels = <2>;
- qcom,dpu-num-nrt-paths = <1>;
-
- qcom,dpu-data-bus {
- qcom,msm-bus,name = "dpu_rsc";
- qcom,msm-bus,active-only;
- qcom,msm-bus,num-cases = <3>;
- qcom,msm-bus,num-paths = <2>;
- qcom,msm-bus,vectors-KBps =
- <22 512 0 0>, <23 512 0 0>,
- <22 512 0 640>, <23 512 0 640>,
- <22 512 0 640>, <23 512 0 640>;
- };
- qcom,dpu-llcc-bus {
- qcom,msm-bus,name = "dpu_rsc_llcc";
- qcom,msm-bus,active-only
[DPU PATCH 0/2] Remove DPU RSC support
MSM display controller hardware (DPU) has an inbuilt RSC block which can control power resources and bus bandwidth voting w/o driver intervention. Downstream driver relies on RSC hardware block for controlling these resources for better power benefits. Since, DPU driver controls these resources, removing RSC support. Corresponding devicetree binding are also removed in this series. DPU driver is currently hosted at https://gitlab.freedesktop.org/seanpaul/dpu-staging Rajesh Yadav (2): dt-bindings: msm/disp: Remove DPU RSC device bindings drm/msm: Remove RSC support from DPU driver .../devicetree/bindings/display/msm/dpu-rsc.txt| 96 -- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 130 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |6 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 242 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|7 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 20 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |3 - drivers/gpu/drm/msm/dpu_dbg.c | 27 - drivers/gpu/drm/msm/dpu_dbg.h | 10 - drivers/gpu/drm/msm/dpu_power_handle.c | 71 +- drivers/gpu/drm/msm/dpu_power_handle.h |4 - drivers/gpu/drm/msm/dpu_rsc.c | 1367 drivers/gpu/drm/msm/dpu_rsc_hw.c | 818 drivers/gpu/drm/msm/dpu_rsc_priv.h | 191 --- include/linux/dpu_rsc.h| 302 - 18 files changed, 42 insertions(+), 3276 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt delete mode 100644 drivers/gpu/drm/msm/dpu_rsc.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_hw.c delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_priv.h delete mode 100644 include/linux/dpu_rsc.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
