[PATCH] drm/atomic: Add new reverse iterator over all plane state (V2)
Add reverse iterator for_each_oldnew_plane_in_state_reverse to compliment the for_each_oldnew_plane_in_state way or reading plane states. The plane states are required to be read in reverse order for amd drivers, cause the z order convention followed in linux is opposite to how the planes are supposed to be presented to DC engine, which is in common to both windows and linux. V2: fix compile time errors due to -Werror flag. Signed-off-by: Shirish S <shiris...@amd.com> Signed-off-by: Pratik Vishwakarma <pratik.vishwaka...@amd.com> Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- include/drm/drm_atomic.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index cf13842..3fe8dde 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (new_plane_state) = (__state)->planes[__i].new_state, 1)) /** + * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic + * update in reverse order + * @__state: drm_atomic_state pointer + * @plane: drm_plane iteration cursor + * @old_plane_state: drm_plane_state iteration cursor for the old state + * @new_plane_state: drm_plane_state iteration cursor for the new state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all planes in an atomic update in reverse order, + * tracking both old and new state. This is useful in places where the + * state delta needs to be considered, for example in atomic check functions. + */ +#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ + for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ +(__i) >= 0;\ +(__i)--) \ + for_each_if ((__state)->planes[__i].ptr && \ +((plane) = (__state)->planes[__i].ptr, \ + (old_plane_state) = (__state)->planes[__i].old_state,\ + (new_plane_state) = (__state)->planes[__i].new_state, 1)) + +/** * for_each_old_plane_in_state - iterate over all planes in an atomic update * @__state: drm_atomic_state pointer * @plane: drm_plane iteration cursor -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: add check for plane functions
On Mon, Mar 20, 2017 at 1:51 PM, Daniel Vetter <dan...@ffwll.ch> wrote:
> On Mon, Mar 20, 2017 at 09:58:01AM +0530, Shirish S wrote:
>> First of all, thanks for your comments/insights.
>>
>> On Sat, Mar 18, 2017 at 12:59 AM, Eric Anholt <e...@anholt.net> wrote:
>> > Ville Syrjälä <ville.syrj...@linux.intel.com> writes:
>> >
>> >> On Fri, Mar 17, 2017 at 05:57:52PM +0100, Daniel Vetter wrote:
>> >>> On Fri, Mar 17, 2017 at 01:08:43PM +0200, Ville Syrjälä wrote:
>> >>> > On Fri, Mar 17, 2017 at 03:46:34PM +0530, Shirish S wrote:
>> >>> > > On Fri, Mar 17, 2017 at 3:26 PM, Ville Syrjälä
>> >>> > > <ville.syrj...@linux.intel.com> wrote:
>> >>> > > > On Fri, Mar 17, 2017 at 01:25:08PM +0530, Shirish S wrote:
>> >>> > > >> update_plane() and disable_plane() functions
>> >>> > > >> assoiciated with setting plane are called
>> >>> > > >> without any check, causing kernel panic.
>> >>> > > >
>> >>> > > > Why are you registering a plane without the funcs?
>> >>> > > >
>> >>> > > Basically, enabling planes and making them fully functional is
>> >>> > > generally a 2 -step process,
>> >>> > > so i suggest for new drivers wanting to implement/re-design planes,
>> >>> > > would like to tap
>> >>> > > the flow at enabling(listing caps) and later at ensuring it works.
>> >>> >
>> >>> > I don't think there's much point in exposing something that
>> >>> > doesn't work. And even if you do, you could always just use
>> >>> > stub functions.
>> >>>
>> >>> Yes, just wire up stub functions if you want to enable planes with
>> >>> multi-step patch series.
>> >>>
>> >>> > > I noticed that there is a underlying assumption only for
>> >>> > > plane->(funcs) are implemented, whereas for
>> >>> > > other function for crtc/connector/encoder function calls there is a
>> >>> > > sanity check(or WARN_ON) through out the framework.
>> >>> > >
>> >>> > > I believe this check wont cause any performance/functional impact.
>> >>> > > Please let me know if am missing anything.
>> >>> > > And further more help developers to focus on enabling planes via
>> >>> > > various tests without causing reboots/system hangs.
>> >>> >
>> >>> > I don't particularly like adding more unconditional runtime checks
>> >>> > that just to protect developers from themselves. If you really
>> >>> > think there's value in these, then at least add the checks into
>> >>> > the plane init codepath so that it's a one time cost.
>> >>> >
>> All the plane->funcs are guarded before being called , be it:
>> late_register()
>> early_unregister()
>> atomic_destroy_state() etc.,
>> only update/disable_plane() are called without checking their
>> existence, am just extending the protocol.
>> >>> > The same approach could be used for all the other non-optional
>> >>> > hooks. Otherwise the same WARN_ON()s would have to be sprinkled
>> >>> > all over the place, and there's always the risk of missing a few
>> >>> > codepaths that call a specific hook.
>> >>>
>> >>> I think for these here there's negative value - it allows developers to
>> >>> create completely broken planes. Stub functions really seem like a much
>> >>> better idea.
>> >>
>> >> I was thinking
>> >>
>> >> drm_whatever_init()
>> >> {
>> >> if (WARN_ON(!funcs->mandatory_thing))
>> >> return -EINVAL;
>> >> }
>> >>
>> I think since the motive here is to
>> * convey user space that it does not have permissions to
>> update/disable available plane due to implementation issues.
>> * Keeping system alive/usable after non-permitted call.
>> Adding a WARN_ON() trace showing something is missing at boot/insmod
>> time, wont solve the purpose.
>>
>> This development phase here could be setting-up infra for adding a
>> plane available on hardware,populate its capabilities
>> and to kn
Re: [PATCH] drm: add check for plane functions
First of all, thanks for your comments/insights.
On Sat, Mar 18, 2017 at 12:59 AM, Eric Anholt <e...@anholt.net> wrote:
> Ville Syrjälä <ville.syrj...@linux.intel.com> writes:
>
>> On Fri, Mar 17, 2017 at 05:57:52PM +0100, Daniel Vetter wrote:
>>> On Fri, Mar 17, 2017 at 01:08:43PM +0200, Ville Syrjälä wrote:
>>> > On Fri, Mar 17, 2017 at 03:46:34PM +0530, Shirish S wrote:
>>> > > On Fri, Mar 17, 2017 at 3:26 PM, Ville Syrjälä
>>> > > <ville.syrj...@linux.intel.com> wrote:
>>> > > > On Fri, Mar 17, 2017 at 01:25:08PM +0530, Shirish S wrote:
>>> > > >> update_plane() and disable_plane() functions
>>> > > >> assoiciated with setting plane are called
>>> > > >> without any check, causing kernel panic.
>>> > > >
>>> > > > Why are you registering a plane without the funcs?
>>> > > >
>>> > > Basically, enabling planes and making them fully functional is
>>> > > generally a 2 -step process,
>>> > > so i suggest for new drivers wanting to implement/re-design planes,
>>> > > would like to tap
>>> > > the flow at enabling(listing caps) and later at ensuring it works.
>>> >
>>> > I don't think there's much point in exposing something that
>>> > doesn't work. And even if you do, you could always just use
>>> > stub functions.
>>>
>>> Yes, just wire up stub functions if you want to enable planes with
>>> multi-step patch series.
>>>
>>> > > I noticed that there is a underlying assumption only for
>>> > > plane->(funcs) are implemented, whereas for
>>> > > other function for crtc/connector/encoder function calls there is a
>>> > > sanity check(or WARN_ON) through out the framework.
>>> > >
>>> > > I believe this check wont cause any performance/functional impact.
>>> > > Please let me know if am missing anything.
>>> > > And further more help developers to focus on enabling planes via
>>> > > various tests without causing reboots/system hangs.
>>> >
>>> > I don't particularly like adding more unconditional runtime checks
>>> > that just to protect developers from themselves. If you really
>>> > think there's value in these, then at least add the checks into
>>> > the plane init codepath so that it's a one time cost.
>>> >
All the plane->funcs are guarded before being called , be it:
late_register()
early_unregister()
atomic_destroy_state() etc.,
only update/disable_plane() are called without checking their
existence, am just extending the protocol.
>>> > The same approach could be used for all the other non-optional
>>> > hooks. Otherwise the same WARN_ON()s would have to be sprinkled
>>> > all over the place, and there's always the risk of missing a few
>>> > codepaths that call a specific hook.
>>>
>>> I think for these here there's negative value - it allows developers to
>>> create completely broken planes. Stub functions really seem like a much
>>> better idea.
>>
>> I was thinking
>>
>> drm_whatever_init()
>> {
>> if (WARN_ON(!funcs->mandatory_thing))
>> return -EINVAL;
>> }
>>
I think since the motive here is to
* convey user space that it does not have permissions to
update/disable available plane due to implementation issues.
* Keeping system alive/usable after non-permitted call.
Adding a WARN_ON() trace showing something is missing at boot/insmod
time, wont solve the purpose.
This development phase here could be setting-up infra for adding a
plane available on hardware,populate its capabilities
and to know how user space reads it and tweak it before moving to
configuring registers.
To add to what @Eric Anholt mentioned, without this patch developer
comes to know about
the mandatory functions required in a real tough way of panic and
system freezes,
just because the core framework invokes a NULL function pointer
without checking.
(Am re-stressing here, that only update/disable planes are exceptions
rest all have required checks.)
>> rather than putting the WARN_ON()s around each call of
>> funcs->mandatory_thing().
>>
There are similar checks around every
"[crtc/encoder]->funcs->[hooked_up_function specific to vendor]",
including plane functions called in drm_plane.c & other places like:
drivers/gpu/drm/drm_crtc_helper.c:1074: if
(plane->funcs->atomic_duplicate_state)
Re: [PATCH] drm: add check for plane functions
On Fri, Mar 17, 2017 at 3:26 PM, Ville Syrjälä
<ville.syrj...@linux.intel.com> wrote:
> On Fri, Mar 17, 2017 at 01:25:08PM +0530, Shirish S wrote:
>> update_plane() and disable_plane() functions
>> assoiciated with setting plane are called
>> without any check, causing kernel panic.
>
> Why are you registering a plane without the funcs?
>
Basically, enabling planes and making them fully functional is
generally a 2 -step process,
so i suggest for new drivers wanting to implement/re-design planes,
would like to tap
the flow at enabling(listing caps) and later at ensuring it works.
I noticed that there is a underlying assumption only for
plane->(funcs) are implemented, whereas for
other function for crtc/connector/encoder function calls there is a
sanity check(or WARN_ON) through out the framework.
I believe this check wont cause any performance/functional impact.
Please let me know if am missing anything.
And further more help developers to focus on enabling planes via
various tests without causing reboots/system hangs.
>>
>> This patch adds the required check to avoid it.
>>
>> Change-Id: I0d6792608b33e674c217388aa57c4b7d680d9bc7
>> Signed-off-by: Shirish S <shiris...@amd.com>
>> ---
>> drivers/gpu/drm/drm_plane.c | 6 ++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
>> index 249c0ae..f675f8b 100644
>> --- a/drivers/gpu/drm/drm_plane.c
>> +++ b/drivers/gpu/drm/drm_plane.c
>> @@ -456,6 +456,12 @@ static int __setplane_internal(struct drm_plane *plane,
>> {
>> int ret = 0;
>>
>> + if (plane->funcs->disable_plane == NULL ||
>> + plane->funcs->update_plane == NULL) {
>> + DRM_ERROR("plane funcs not implemented\n");
>> + ret = -EPERM;
>> + goto out;
>> + }
>> /* No fb means shut it down */
>> if (!fb) {
>> plane->old_fb = plane->fb;
>> --
>> 2.7.4
>>
>> ___
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Ville Syrjälä
> Intel OTC
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: add check for plane functions
update_plane() and disable_plane() functions
assoiciated with setting plane are called
without any check, causing kernel panic.
This patch adds the required check to avoid it.
Change-Id: I0d6792608b33e674c217388aa57c4b7d680d9bc7
Signed-off-by: Shirish S <shiris...@amd.com>
---
drivers/gpu/drm/drm_plane.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 249c0ae..f675f8b 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -456,6 +456,12 @@ static int __setplane_internal(struct drm_plane *plane,
{
int ret = 0;
+ if (plane->funcs->disable_plane == NULL ||
+ plane->funcs->update_plane == NULL) {
+ DRM_ERROR("plane funcs not implemented\n");
+ ret = -EPERM;
+ goto out;
+ }
/* No fb means shut it down */
if (!fb) {
plane->old_fb = plane->fb;
--
2.7.4
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[PATCH] drm/exynos: add phy settings for exynos5420
This patch adds phy settings of the below
mentioned pixel clocks in Exynos5420:
85.5 MHz- 1366x768 at 60Hz
162 MHz - 1600x1200 at 60Hz
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index e05c86a..07ba387 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -523,6 +523,15 @@ static const struct hdmiphy_config hdmiphy_5420_configs[]
= {
},
},
{
+ .pixel_clock = 8550,
+ .conf = {
+ 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0xc8,
+ 0x84, 0xe8, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86,
+ 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 8875,
.conf = {
0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
@@ -576,6 +585,15 @@ static const struct hdmiphy_config hdmiphy_5420_configs[]
= {
0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
},
},
+ {
+ .pixel_clock = 16200,
+ .conf = {
+ 0x01, 0x54, 0x87, 0x05, 0x40, 0x01, 0x00, 0xc8,
+ 0x82, 0xc8, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86,
+ 0x54, 0x4c, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
};
static struct hdmi_driver_data exynos5420_hdmi_driver_data = {
--
1.7.9.5
[PATCH] drm/exynos: restore core HDMI settings
Hi, On Wed, Feb 19, 2014 at 4:02 PM, Inki Dae wrote: > 2014-02-14 16:34 GMT+09:00 Shirish S : >> In DVI mode the video preamble and Guard band should >> be disabled whereas it should be applied in HDMI mode, >> the re-applying of preamble and guard band was missing, >> which resulted in display failures when switched to HDMI >> mode from DVI mode. >> This patch ensures the setting is applied in HDMI mode. >> >> Signed-off-by: Shirish S >> --- >> drivers/gpu/drm/exynos/exynos_hdmi.c |2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c >> b/drivers/gpu/drm/exynos/exynos_hdmi.c >> index a0e10ae..a102076 100644 >> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c >> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c >> @@ -994,6 +994,8 @@ static void hdmi_conf_init(struct hdmi_context *hdata) >> /* choose HDMI mode */ >> hdmi_reg_writemask(hdata, HDMI_MODE_SEL, >> HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); >> + /* Apply Video preable and Guard band in HDMI mode only */ >> + hdmi_reg_writeb(hdata, HDMI_CON_2, 0); > > Isn't hdmi_conf_init function always called after hdmi core is reset? > And HDMI_CON_2 would have 0 as reset value. It seems that your code > isn't meaningful. > Now that rahul's patch of "drm/exynos: replace hdmi reset with hdmi disable" which removes hdmi core reset is merged in your tree, my patch is required since if the user connects HDMI monitor via DVI connector, unplugs and then connects to HDMI TV via HDMI cable, it wont work as the settings of DVI are still on and not reset-ted. Can you kindly apply this patch? > If you want to set HDMI_CON_2 to HDMI mode in there then it would > better to use meaningful macro, HDMI_VID_PREAMBLE_DIS and > HDMI_GUARD_BAND_DIS. > > Thanks, > Inki Dae > >> /* disable bluescreen */ >> hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); >> >> -- >> 1.7.9.5 >> >> ___ >> dri-devel mailing list >> dri-devel at lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/dri-devel > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel Thanks & Regards, Shirish S
[PATCH] drm/exynos: add phy settings for RB resolutions
Hi,
Have posted a patch that updates the phy settings provided by our hardware team.
For now support for 88.75 MHz is removed, will update it as and when i
recieve and settings
for that pixel clock.
Regards,
Shirish S
On Wed, Apr 2, 2014 at 9:39 AM, Shirish S wrote:
> Hi,
> Kindly hold the merging of this patch, i shall
> update it with proper values, once i receive it from our hardware team.
> Regards,
> ShirisH S
> On Thu, Mar 20, 2014 at 1:05 PM, St?phane Marchesin
> wrote:
>>
>>
>>
>> On Wed, Mar 12, 2014 at 10:28 PM, Shirish S wrote:
>>>
>>> This patch adds support for the below mentioned
>>> pixel clocks in Exynos5250.
>>> Without them, following display modes won't
>>> be supported:
>>>
>>> 71 MHz - 1280x800 at 60Hz RB
>>> 73.25 MHz - 800x600 at 120Hz RB
>>> 88.75 MHz - 1440x900 at 60Hz RB
>>> 115.5 MHz - 1024x768 at 120Hz RB
>>> 119 MHz - 1680x1050 at 60Hz RB
>>>
>>> Signed-off-by: Shirish S
>>> ---
>>> V2: Incorporated review comments
>>>
>>> drivers/gpu/drm/exynos/exynos_hdmi.c | 45
>>> ++
>>> 1 file changed, 45 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> index 12fdf55..406d89d 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>>> @@ -304,6 +304,24 @@ static const struct hdmiphy_config
>>> hdmiphy_v14_configs[] = {
>>> },
>>> },
>>> {
>>> + .pixel_clock = 7100,
>>> + .conf = {
>>> + 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
>>> + 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>>> + 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>>> + },
>>> + },
>>> + {
>>> + .pixel_clock = 7325,
>>> + .conf = {
>>> + 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
>>> + 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>>> + 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>>> + },
>>> + },
>>> + {
>>> .pixel_clock = 74176000,
>>> .conf = {
>>> 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
>>> @@ -331,6 +349,15 @@ static const struct hdmiphy_config
>>> hdmiphy_v14_configs[] = {
>>> },
>>> },
>>> {
>>> + .pixel_clock = 8875,
>>> + .conf = {
>>> + 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
>>> + 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>>> + 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>>> + },
>>> + },
>>> + {
>>> .pixel_clock = 10650,
>>> .conf = {
>>> 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
>>> @@ -349,6 +376,24 @@ static const struct hdmiphy_config
>>> hdmiphy_v14_configs[] = {
>>> },
>>> },
>>> {
>>> + .pixel_clock = 11550,
>>> + .conf = {
>>> + 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
>>> + 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
>>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>>> + 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
>>> + },
>>> + },
>>> + {
>>> + .pixel_clock = 11900,
>>
>>
>>
>> We have found that the 119MHz clock doesn't work in Chrome OS (the clock
>> doesn't stabilize), so we removed it. We should probably remove it here as
>> well.
>>
>> St?phane
>>
> I have informed this issue to the hardware team, and will update it
> once i receive
> any changes,
> Also i
>>> + .conf = {
>>> + 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
>>> + 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
>>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>>> + 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
>>> + },
>>> + },
>>> + {
>>> .pixel_clock = 14625,
>>> .conf = {
>>> 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
>>> --
>>> 1.7.10.4
>>>
>>> ___
>>> dri-devel mailing list
>>> dri-devel at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>>
[PATCH] drm/exynos: update phy settings for RB resolutions
This patch updates phy settings of the below
mentioned pixel clocks in Exynos5250 and removes
support for 88.75MHz, for it is not supported.
71 MHz - 1280x800 at 60Hz RB
73.25 MHz - 800x600 at 120Hz RB
115.5 MHz - 1024x768 at 120Hz RB
119 MHz - 1680x1050 at 60Hz RB
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 33 -
1 file changed, 12 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 9a6d652..7f14faf 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -319,18 +319,18 @@ static const struct hdmiphy_config hdmiphy_v14_configs[]
= {
{
.pixel_clock = 7100,
.conf = {
- 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
- 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
+ 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
},
},
{
.pixel_clock = 7325,
.conf = {
- 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
- 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
+ 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
},
},
@@ -362,15 +362,6 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
- .pixel_clock = 8875,
- .conf = {
- 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
- 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
.pixel_clock = 10650,
.conf = {
0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
@@ -391,18 +382,18 @@ static const struct hdmiphy_config hdmiphy_v14_configs[]
= {
{
.pixel_clock = 11550,
.conf = {
- 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
- 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
+ 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
},
},
{
.pixel_clock = 11900,
.conf = {
- 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
- 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
+ 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
},
},
--
1.7.9.5
[PATCH] drm/exynos: add phy settings for RB resolutions
Hi,
Kindly hold the merging of this patch, i shall
update it with proper values, once i receive it from our hardware team.
Regards,
ShirisH S
On Thu, Mar 20, 2014 at 1:05 PM, St?phane Marchesin
wrote:
>
>
>
> On Wed, Mar 12, 2014 at 10:28 PM, Shirish S wrote:
>>
>> This patch adds support for the below mentioned
>> pixel clocks in Exynos5250.
>> Without them, following display modes won't
>> be supported:
>>
>> 71 MHz - 1280x800 at 60Hz RB
>> 73.25 MHz - 800x600 at 120Hz RB
>> 88.75 MHz - 1440x900 at 60Hz RB
>> 115.5 MHz - 1024x768 at 120Hz RB
>> 119 MHz - 1680x1050 at 60Hz RB
>>
>> Signed-off-by: Shirish S
>> ---
>> V2: Incorporated review comments
>>
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 45
>> ++
>> 1 file changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 12fdf55..406d89d 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -304,6 +304,24 @@ static const struct hdmiphy_config
>> hdmiphy_v14_configs[] = {
>> },
>> },
>> {
>> + .pixel_clock = 7100,
>> + .conf = {
>> + 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
>> + 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>> + 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>> + },
>> + },
>> + {
>> + .pixel_clock = 7325,
>> + .conf = {
>> + 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
>> + 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>> + 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>> + },
>> + },
>> + {
>> .pixel_clock = 74176000,
>> .conf = {
>> 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
>> @@ -331,6 +349,15 @@ static const struct hdmiphy_config
>> hdmiphy_v14_configs[] = {
>> },
>> },
>> {
>> + .pixel_clock = 8875,
>> + .conf = {
>> + 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
>> + 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>> + 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
>> + },
>> + },
>> + {
>> .pixel_clock = 10650,
>> .conf = {
>> 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
>> @@ -349,6 +376,24 @@ static const struct hdmiphy_config
>> hdmiphy_v14_configs[] = {
>> },
>> },
>> {
>> + .pixel_clock = 11550,
>> + .conf = {
>> + 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
>> + 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>> + 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
>> + },
>> + },
>> + {
>> + .pixel_clock = 11900,
>
>
>
> We have found that the 119MHz clock doesn't work in Chrome OS (the clock
> doesn't stabilize), so we removed it. We should probably remove it here as
> well.
>
> St?phane
>
I have informed this issue to the hardware team, and will update it
once i receive
any changes,
Also i
>> + .conf = {
>> + 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
>> + 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
>> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
>> + 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
>> + },
>> + },
>> + {
>> .pixel_clock = 14625,
>> .conf = {
>> 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
>> --
>> 1.7.10.4
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
[PATCH] drm/exynos: set the active aspect ratio as per mode
Now that the drm_display_mode also provides aspect
ratio for all resolutions, this patch adds its usage
to set the active aspect ratio of AVI info frame
packets as per CEA-861-D standard's Table 9.
This is also needed to abide by the 7-27
compliance test of HDMI.
Signed-off-by: Shirish S
---
V2: rebased on new branch
V3: Incorporated review comments
drivers/gpu/drm/exynos/exynos_hdmi.c | 35 +++---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 12fdf55..9b0b617 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -53,12 +53,13 @@
/* AVI header and aspect ratio */
#define HDMI_AVI_VERSION 0x02
#define HDMI_AVI_LENGTH0x0D
-#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
-#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
/* AUI header info */
#define HDMI_AUI_VERSION 0x01
#define HDMI_AUI_LENGTH0x0A
+#defineAVI_SAME_AS_PIC_ASPECT_RATIO 0x8
+#defineAVI_4_3_CENTER_RATIO0x9
+#defineAVI_16_9_CENTER_RATIO 0xa
enum hdmi_type {
HDMI_TYPE13,
@@ -162,6 +163,7 @@ struct hdmi_v14_conf {
struct hdmi_conf_regs {
int pixel_clock;
int cea_video_id;
+ enum hdmi_picture_aspect aspect_ratio;
union {
struct hdmi_v13_conf v13_conf;
struct hdmi_v14_conf v14_conf;
@@ -669,7 +671,6 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
{
u32 hdr_sum;
u8 chksum;
- u32 aspect_ratio;
u32 mod;
u32 vic;
@@ -698,10 +699,28 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
AVI_ACTIVE_FORMAT_VALID |
AVI_UNDERSCANNED_DISPLAY_VALID);
- aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
-
- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
- AVI_SAME_AS_PIC_ASPECT_RATIO);
+ /*
+* Set the aspect ratio as per the mode, mentioned in
+* Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
+*/
+ switch (hdata->mode_conf.aspect_ratio) {
+ case HDMI_PICTURE_ASPECT_4_3:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+ hdata->mode_conf.aspect_ratio |
+ AVI_4_3_CENTER_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_16_9:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+ hdata->mode_conf.aspect_ratio |
+ AVI_16_9_CENTER_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_NONE:
+ default:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+ hdata->mode_conf.aspect_ratio |
+ AVI_SAME_AS_PIC_ASPECT_RATIO);
+ break;
+ }
vic = hdata->mode_conf.cea_video_id;
hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
@@ -1519,6 +1538,7 @@ static void hdmi_v13_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
@@ -1615,6 +1635,7 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->v_line, 2, m->vtotal);
--
1.7.10.4
[PATCH] drm/exynos: add phy settings for RB resolutions
This patch adds support for the below mentioned
pixel clocks in Exynos5250.
Without them, following display modes won?t
be supported:
71 MHz - 1280x800 at 60Hz RB
73.25 MHz - 800x600 at 120Hz RB
88.75 MHz - 1440x900 at 60Hz RB
115.5 MHz - 1024x768 at 120Hz RB
119 MHz - 1680x1050 at 60Hz RB
Signed-off-by: Shirish S
---
V2: Incorporated review comments
drivers/gpu/drm/exynos/exynos_hdmi.c | 45 ++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 12fdf55..406d89d 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -304,6 +304,24 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 7100,
+ .conf = {
+ 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
+ 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
+ .pixel_clock = 7325,
+ .conf = {
+ 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
+ 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 74176000,
.conf = {
0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
@@ -331,6 +349,15 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 8875,
+ .conf = {
+ 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
+ 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 10650,
.conf = {
0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
@@ -349,6 +376,24 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 11550,
+ .conf = {
+ 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
+ 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
+ .pixel_clock = 11900,
+ .conf = {
+ 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
+ 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 14625,
.conf = {
0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
--
1.7.10.4
[PATCH] drm/exynos: set the active aspect ratio as per mode
Hi Tomasz,
On Wed, Mar 12, 2014 at 8:19 AM, Tomasz Figa wrote:
> Hi Shirish,
>
>
> On 10.03.2014 04:44, Shirish S wrote:
>>
>> now that the drm_display_mode also provides aspect
>> ratio for all resolutions, this patch adds its usage
>> to set the active aspect ratio of AVI info frame
>> packets as per CEA-861-D standard's Table 9.
>>
>> This is also needed to abide by the 7-27
>> compliance test of HDMI.
>>
>> Signed-off-by: Shirish S
>> ---
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 33
>> +++--
>> 1 file changed, 27 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index c021ddc..8aca52a 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -53,8 +53,6 @@
>> /* AVI header and aspect ratio */
>> #define HDMI_AVI_VERSION 0x02
>> #define HDMI_AVI_LENGTH 0x0D
>> -#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
>> -#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
>>
>> /* AUI header info */
>> #define HDMI_AUI_VERSION 0x01
>> @@ -65,6 +63,12 @@ enum hdmi_type {
>> HDMI_TYPE14,
>> };
>>
>> +enum active_aspect_ratio {
>> + AVI_SAME_AS_PIC_ASPECT_RATIO = 8,
>> + AVI_4_3_Center_RATIO,
>> + AVI_16_9_Center_RATIO,
>> +};
>> +
>
>
> CodingStyle: Please define these using preprocessor macros, since they are
> bitfield values. Also coding style implies using uppercase for constants.
>
>
Agreed, updated in the next path set.
>> struct hdmi_resources {
>> struct clk *hdmi;
>> struct clk *sclk_hdmi;
>> @@ -162,6 +166,7 @@ struct hdmi_v14_conf {
>> struct hdmi_conf_regs {
>> int pixel_clock;
>> int cea_video_id;
>> + enum hdmi_picture_aspect aspect_ratio;
>> union {
>> struct hdmi_v13_conf v13_conf;
>> struct hdmi_v14_conf v14_conf;
>> @@ -668,7 +673,6 @@ static void hdmi_reg_infoframe(struct hdmi_context
>> *hdata,
>> {
>> u32 hdr_sum;
>> u8 chksum;
>> - u32 aspect_ratio;
>> u32 mod;
>> u32 vic;
>>
>> @@ -697,10 +701,25 @@ static void hdmi_reg_infoframe(struct hdmi_context
>> *hdata,
>> AVI_ACTIVE_FORMAT_VALID |
>> AVI_UNDERSCANNED_DISPLAY_VALID);
>>
>> - aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
>> -
>> - hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
>> + /*
>> +* Set the aspect ratio as per the mode, mentioned in
>> +* Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
>> +*/
>> + switch (hdata->mode_conf.aspect_ratio) {
>> + case HDMI_PICTURE_ASPECT_4_3:
>> + hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
>> aspect_ratio |
>> + AVI_4_3_Center_RATIO);
>
>
> CodingStyle: Please keep wrapped function calls aligned using tabs at least
> to the opening parenthesis.
>
>
>> + break;
>> + case HDMI_PICTURE_ASPECT_16_9:
>> + hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
>> aspect_ratio |
>> + AVI_16_9_Center_RATIO);
>
>
> Ditto.
>
Agreed, updated in next patch set.
>
>> + break;
>> + case HDMI_PICTURE_ASPECT_NONE:
>> + default:
>> + hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
>> aspect_ratio |
>> AVI_SAME_AS_PIC_ASPECT_RATIO);
>
>
> Ditto.
>
> Best regards,
> Tomasz
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
Thanks & Regards,
Shirish S
[PATCH] drm/exynos: add phy settings for RB resolutions
Hi Tomasz,
Thanks for the review comments,
On Wed, Mar 12, 2014 at 8:26 AM, Tomasz Figa wrote:
>
> Hi Shirish,
>
>
> On 10.03.2014 15:17, Shirish S wrote:
>>
>> below is list of pixel clocks and resoluitons
>> this patch adds:
>>
>> 7100 - 1280x800 at 60Hz RB
>> 7325 - 800x600 at 120Hz RB
>> 8875 - 1440x900 at 60Hz RB
>> 11550 - 1024x768 at 120Hz RB
>> 11900 - 1680x1050 at 60Hz RB
>>
>> without these pixel clocks' support the mentioned
>> resolutions fail to be detected in exynos5250.
>
>
> This commit message is poorly written. Please start sentences with capital
> letters and check spelling before sending.
>
> Here follows an example of commit message for this patch:
>
> 8<---
>
> This patch adds several new pixel clock settings for HDMI PHY v14
> (Exynos5250). Without them following display modes cannot be supported:
>
> 7100 Hz - 1280x800 at 60Hz RB
> 7325 Hz - 800x600 at 120Hz RB
> 8875 Hz - 1440x900 at 60Hz RB
> 11550 Hz - 1024x768 at 120Hz RB
> 11900 Hz - 1680x1050 at 60Hz RB
>
> --->8
>
>
agreed, have updated it in the next patchset
>>
>> Signed-off-by: Shirish S
>> ---
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 45
>> ++
>> 1 file changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index c021ddc..650ce48 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -303,6 +303,24 @@ static const struct hdmiphy_config
>> hdmiphy_v14_configs[] = {
>> },
>> },
>> {
>> + .pixel_clock = 7100,
>> + .conf = {
>> + 0x01, 0x91, 0x1E, 0x15, 0x40, 0x3C, 0xCE, 0x08,
>
>
> Lowercase is preferred by kernel coding style for hexadecimal values.
Done.
>
> Best regards,
> Tomasz
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
Thanks & Regards,
Shirish S
[PATCH] drm/exynos: add hdmi power on/off sequence
This patch implements the power on/off sequence
(and its dependant functions) of HDMI exynos5250
as provided by the hardware team.
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 137 +-
drivers/gpu/drm/exynos/regs-hdmi.h | 15
2 files changed, 133 insertions(+), 19 deletions(-)
mode change 100644 => 100755 drivers/gpu/drm/exynos/exynos_hdmi.c
mode change 100644 => 100755 drivers/gpu/drm/exynos/regs-hdmi.h
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
old mode 100644
new mode 100755
index 12fdf55..ee000f7
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -180,6 +180,7 @@ struct hdmi_context {
void __iomem*regs;
int irq;
+ void __iomem*phy_pow_ctrl_reg;
struct i2c_client *ddc_port;
struct i2c_client *hdmiphy_port;
@@ -387,6 +388,33 @@ static inline void hdmi_reg_writemask(struct hdmi_context
*hdata,
writel(value, hdata->regs + reg_id);
}
+
+static inline void hdmi_phy_pow_ctrl_reg_writemask(struct hdmi_context *hdata,
+u32 value, u32 mask)
+{
+ u32 old = readl(hdata->phy_pow_ctrl_reg);
+ value = (value & mask) | (old & ~mask);
+ writel(value, hdata->phy_pow_ctrl_reg);
+}
+
+static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
+ u32 reg_offset, u8 value)
+{
+ if (hdata->hdmiphy_port) {
+ u8 buffer[2];
+ int ret;
+
+ buffer[0] = reg_offset;
+ buffer[1] = value;
+
+ ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
+ if (ret == 2)
+ return 0;
+ return ret;
+ } else
+ return 0;
+}
+
static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
{
#define DUMPREG(reg_id) \
@@ -1386,19 +1414,14 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)
static void hdmiphy_conf_reset(struct hdmi_context *hdata)
{
- u8 buffer[2];
u32 reg;
clk_disable_unprepare(hdata->res.sclk_hdmi);
clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
clk_prepare_enable(hdata->res.sclk_hdmi);
- /* operation mode */
- buffer[0] = 0x1f;
- buffer[1] = 0x00;
-
- if (hdata->hdmiphy_port)
- i2c_master_send(hdata->hdmiphy_port, buffer, 2);
+ hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
+ HDMI_PHY_ENABLE_MODE_SET);
if (hdata->type == HDMI_TYPE13)
reg = HDMI_V13_PHY_RSTOUT;
@@ -1414,16 +1437,42 @@ static void hdmiphy_conf_reset(struct hdmi_context
*hdata)
static void hdmiphy_poweron(struct hdmi_context *hdata)
{
- if (hdata->type == HDMI_TYPE14)
- hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
- HDMI_PHY_POWER_OFF_EN);
+ if (hdata->type == HDMI_TYPE13)
+ return;
+
+ DRM_DEBUG_KMS("\n");
+
+ /* For PHY Mode Setting */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
+ HDMI_PHY_ENABLE_MODE_SET);
+ /* Phy Power On */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
+ HDMI_PHY_POWER_ON);
+ /* For PHY Mode Setting */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
+ HDMI_PHY_DISABLE_MODE_SET);
+ /* PHY SW Reset */
+ hdmiphy_conf_reset(hdata);
}
static void hdmiphy_poweroff(struct hdmi_context *hdata)
{
- if (hdata->type == HDMI_TYPE14)
- hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
- HDMI_PHY_POWER_OFF_EN);
+ if (hdata->type == HDMI_TYPE13)
+ return;
+
+ DRM_DEBUG_KMS("\n");
+
+ /* PHY SW Reset */
+ hdmiphy_conf_reset(hdata);
+ /* For PHY Mode Setting */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
+ HDMI_PHY_ENABLE_MODE_SET);
+ /* PHY Power Off */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
+ HDMI_PHY_POWER_OFF);
+ /* For PHY Mode Setting */
+ hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
+ HDMI_PHY_DISABLE_MODE_SET);
}
static void hdmiphy_conf_apply(struct hdmi_context *hdata)
@@ -1476,6 +1525,14 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
DRM_ERROR("failed to read hdmiphy config\n");
return;
}
+ usleep_range(1, 12000);
+
+ ret = hdmiphy_reg_writeb(hdata, HDMI
[PATCH] drm/exynos: set the active aspect ratio as per mode
now that the drm_display_mode also provides aspect
ratio for all resolutions, this patch adds its usage
to set the active aspect ratio of AVI info frame
packets as per CEA-861-D standard's Table 9.
This is also needed to abide by the 7-27
compliance test of HDMI.
V2: rebased it to TODO branch, and
made the orr'ing logic correct
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 38 +++---
1 file changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index c021ddc..bba54c9 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -53,8 +53,6 @@
/* AVI header and aspect ratio */
#define HDMI_AVI_VERSION 0x02
#define HDMI_AVI_LENGTH0x0D
-#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
-#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
/* AUI header info */
#define HDMI_AUI_VERSION 0x01
@@ -65,6 +63,12 @@ enum hdmi_type {
HDMI_TYPE14,
};
+enum active_aspect_ratio {
+ AVI_SAME_AS_PIC_ASPECT_RATIO = 8,
+ AVI_4_3_Center_RATIO,
+ AVI_16_9_Center_RATIO,
+};
+
struct hdmi_resources {
struct clk *hdmi;
struct clk *sclk_hdmi;
@@ -162,6 +166,7 @@ struct hdmi_v14_conf {
struct hdmi_conf_regs {
int pixel_clock;
int cea_video_id;
+ enum hdmi_picture_aspect aspect_ratio;
union {
struct hdmi_v13_conf v13_conf;
struct hdmi_v14_conf v14_conf;
@@ -668,7 +673,6 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
{
u32 hdr_sum;
u8 chksum;
- u32 aspect_ratio;
u32 mod;
u32 vic;
@@ -697,10 +701,28 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
AVI_ACTIVE_FORMAT_VALID |
AVI_UNDERSCANNED_DISPLAY_VALID);
- aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
-
- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
- AVI_SAME_AS_PIC_ASPECT_RATIO);
+ /*
+* Set the aspect ratio as per the mode, mentioned in
+* Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
+*/
+ switch (hdata->mode_conf.aspect_ratio) {
+ case HDMI_PICTURE_ASPECT_4_3:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+(hdata->mode_conf.aspect_ratio << 4) |
+AVI_4_3_Center_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_16_9:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+(hdata->mode_conf.aspect_ratio << 4) |
+AVI_16_9_Center_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_NONE:
+ default:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
+(hdata->mode_conf.aspect_ratio << 4) |
+AVI_SAME_AS_PIC_ASPECT_RATIO);
+ break;
+ }
vic = hdata->mode_conf.cea_video_id;
hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
@@ -1421,6 +1443,7 @@ static void hdmi_v13_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
@@ -1517,6 +1540,7 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->v_line, 2, m->vtotal);
--
1.7.10.4
[PATCH] drm/exynos: add phy settings for RB resolutions
below is list of pixel clocks and resoluitons
this patch adds:
7100 - 1280x800 at 60Hz RB
7325 - 800x600 at 120Hz RB
8875 - 1440x900 at 60Hz RB
11550 - 1024x768 at 120Hz RB
11900 - 1680x1050 at 60Hz RB
without these pixel clocks' support the mentioned
resolutions fail to be detected in exynos5250.
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 45 ++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index c021ddc..650ce48 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -303,6 +303,24 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 7100,
+ .conf = {
+ 0x01, 0x91, 0x1E, 0x15, 0x40, 0x3C, 0xCE, 0x08,
+ 0x04, 0x20, 0xB2, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xAD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
+ .pixel_clock = 7325,
+ .conf = {
+ 0x01, 0xD1, 0x1F, 0x15, 0x40, 0x18, 0xE9, 0x08,
+ 0x02, 0xA0, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 74176000,
.conf = {
0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
@@ -330,6 +348,15 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 8875,
+ .conf = {
+ 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xFE, 0x08,
+ 0x06, 0x20, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0x8A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 10650,
.conf = {
0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
@@ -348,6 +375,24 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
},
{
+ .pixel_clock = 11550,
+ .conf = {
+ 0x01, 0xD1, 0x30, 0x1A, 0x40, 0x40, 0x10, 0x04,
+ 0x04, 0xA0, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0xAA, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
+ .pixel_clock = 11900,
+ .conf = {
+ 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xD8, 0x08,
+ 0x06, 0x20, 0x2A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
+ 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
+ 0x54, 0x9D, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
+ },
+ },
+ {
.pixel_clock = 14625,
.conf = {
0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
--
1.7.10.4
[PATCH] drm/exynos: set the active aspect ratio as per mode
now that the drm_display_mode also provides aspect
ratio for all resolutions, this patch adds its usage
to set the active aspect ratio of AVI info frame
packets as per CEA-861-D standard's Table 9.
This is also needed to abide by the 7-27
compliance test of HDMI.
Signed-off-by: Shirish S
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index c021ddc..8aca52a 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -53,8 +53,6 @@
/* AVI header and aspect ratio */
#define HDMI_AVI_VERSION 0x02
#define HDMI_AVI_LENGTH0x0D
-#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
-#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
/* AUI header info */
#define HDMI_AUI_VERSION 0x01
@@ -65,6 +63,12 @@ enum hdmi_type {
HDMI_TYPE14,
};
+enum active_aspect_ratio {
+ AVI_SAME_AS_PIC_ASPECT_RATIO = 8,
+ AVI_4_3_Center_RATIO,
+ AVI_16_9_Center_RATIO,
+};
+
struct hdmi_resources {
struct clk *hdmi;
struct clk *sclk_hdmi;
@@ -162,6 +166,7 @@ struct hdmi_v14_conf {
struct hdmi_conf_regs {
int pixel_clock;
int cea_video_id;
+ enum hdmi_picture_aspect aspect_ratio;
union {
struct hdmi_v13_conf v13_conf;
struct hdmi_v14_conf v14_conf;
@@ -668,7 +673,6 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
{
u32 hdr_sum;
u8 chksum;
- u32 aspect_ratio;
u32 mod;
u32 vic;
@@ -697,10 +701,25 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
AVI_ACTIVE_FORMAT_VALID |
AVI_UNDERSCANNED_DISPLAY_VALID);
- aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
-
- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
+ /*
+* Set the aspect ratio as per the mode, mentioned in
+* Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
+*/
+ switch (hdata->mode_conf.aspect_ratio) {
+ case HDMI_PICTURE_ASPECT_4_3:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
+ AVI_4_3_Center_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_16_9:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
+ AVI_16_9_Center_RATIO);
+ break;
+ case HDMI_PICTURE_ASPECT_NONE:
+ default:
+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
AVI_SAME_AS_PIC_ASPECT_RATIO);
+ break;
+ }
vic = hdata->mode_conf.cea_video_id;
hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
@@ -1421,6 +1440,7 @@ static void hdmi_v13_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
@@ -1517,6 +1537,7 @@ static void hdmi_v14_mode_set(struct hdmi_context *hdata,
hdata->mode_conf.cea_video_id =
drm_match_cea_mode((struct drm_display_mode *)m);
hdata->mode_conf.pixel_clock = m->clock * 1000;
+ hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
hdmi_set_reg(core->v_line, 2, m->vtotal);
--
1.7.10.4
[PATCH] drm/exynos: restore core HDMI settings
In DVI mode the video preamble and Guard band should be disabled whereas it should be applied in HDMI mode, the re-applying of preamble and guard band was missing, which resulted in display failures when switched to HDMI mode from DVI mode. This patch ensures the setting is applied in HDMI mode. Signed-off-by: Shirish S --- drivers/gpu/drm/exynos/exynos_hdmi.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index a0e10ae..a102076 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -994,6 +994,8 @@ static void hdmi_conf_init(struct hdmi_context *hdata) /* choose HDMI mode */ hdmi_reg_writemask(hdata, HDMI_MODE_SEL, HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); + /* Apply Video preable and Guard band in HDMI mode only */ + hdmi_reg_writeb(hdata, HDMI_CON_2, 0); /* disable bluescreen */ hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi Tomasz,
Thanks for the review comments, please find my replies inline.
On Thu, Dec 19, 2013 at 6:49 PM, Tomasz Figa wrote:
> On Thursday 19 of December 2013 17:42:28 Shirish S wrote:
>> This patch adds dt support to hdmiphy config settings
>> as it is board specific and depends on the signal pattern
>> of board.
>>
>> Signed-off-by: Shirish S
>> ---
>> .../devicetree/bindings/video/exynos_hdmi.txt | 34
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 89
>>
>> 2 files changed, 105 insertions(+), 18 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> index 323983b..0766e6e 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> @@ -13,6 +13,31 @@ Required properties:
>> b) pin number within the gpio controller.
>> c) optional flags and pull up/down.
>>
>> +Optional-but-recommended properties:
>> +- hdmiphy-configs: following information about the hdmiphy config settings.
>> + a) "config: config" specifies the phy configuration settings,
>
> Why do you need this "config: " part? (This is called "label" in DT
> terminology by the way and can be used to reference the node from
> properties of other nodes, by so called "phandle".)
>
The config is required for every pixel clock that the IP supports,
since in the parsing i iterate through all pixel clocks, i have used 'N'.
However, if you proposed approach below is ok, then all of this shall
be removed.
>> + where 'N' denotes the number of configuration, since every
>> + pixel clock can have its unique configuration.
>> + "samsung,pixel-clock" specifies the pixel clock
>> + "samsung,de-emphasis-level" provides fine control of TMDS data
>> + pre emphasis, below shown is example for
>> + data de-emphasis register at address 0x145D0040.
>> + hdmiphy at 38[16] for bits[3:0] permitted values are in
>> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
>> + increments for every LSB
>> + hdmiphy at 38[16] for bits[7:4] permitted values are in
>> + the range of 0dB to -7.45dB at increments of -0.45dB
>> + for every LSB.
>> + "samsung,clock-level" provides fine control of TMDS data
>> + amplitude for each channel,
>> + for example if 0x145D005C is the address of clock level
>> + register then,
>> + hdmiphy at 38[23] for bits [1:0] permitted values are
>> in
>> + the range of 0 mVdiff & 60 mVdiff for each channel at
>> + increments 20 mVdiff of amplitude levels for every LSB,
>> + hdmiphy at 38[23] for bits [7:3] permitted values are
>> in
>> + the range of 790 and 1430 mV at 20mV increments for
>> + every LSB.
>> Example:
>>
>> hdmi {
>> @@ -20,4 +45,13 @@ Example:
>> reg = <0x1453 0x10>;
>> interrupts = <0 95 0>;
>> hpd-gpio = < 7 1>;
>> + hdmiphy-configs {
>> + config0: config0 {
>> + samsung,pixel-clock = <2520>;
>> + samsung,de-emphasis-level = /bits/ 8 <0x26>;
>
> nit: Two spaces before "/bits/".
have corrected in the next patchset.
>
>> + samsung,clock-level = /bits/ 8 < 0x66>;
>
> nit: Two spaces before "/bits/" and incorrect space after "<".
have corrected in the next patchset.
>
> Generally the list of configurations should look like below:
>
> phy-configs {
> #address-cells = <1>;
> #size-cells = <0>;
>
> config at 0 {
> reg = <0>;
> /* other properties... */
> };
>
> config at 1 {
> reg = <1>;
> /* other properties... */
> };
>
> /* ... */
> };
>
> This is how bus-like structures should be represented in device tree.
> Also, since t
[PATCH] drm: edid: enable probing and listing of non rb modes
The current solution checks for the existing RB mode,
if available in the edid block returns by adding it,
but does not populate the connector with the modes
of same resolution but which are non-rb modes.
As a result the probing and listing of non-rb modes can't
be made, in case the rb mode's pixel clock is not
supported but non-rb mode is supported.
This patch changes the drm_mode_std mode selection to
collect all the supported modes and not just one mode.
Signed-off-by: Shirish S
---
drivers/gpu/drm/drm_edid.c | 39 ++-
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 8835dcd..ba865f1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1592,12 +1592,13 @@ bad_std_timing(u8 a, u8 b)
* Take the standard timing params (in this case width, aspect, and refresh)
* and convert them into a real mode using CVT/GTF/DMT.
*/
-static struct drm_display_mode *
+static unsigned int
drm_mode_std(struct drm_connector *connector, struct edid *edid,
struct std_timing *t, int revision)
{
struct drm_device *dev = connector->dev;
struct drm_display_mode *m, *mode = NULL;
+ unsigned int modes = 0;
int hsize, vsize;
int vrefresh_rate;
unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
@@ -1607,7 +1608,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
int timing_level = standard_timing_level(edid);
if (bad_std_timing(t->hsize, t->vfreq_aspect))
- return NULL;
+ return modes;
/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
hsize = t->hsize * 8 + 248;
@@ -1643,7 +1644,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
list_for_each_entry(m, >probed_modes, head)
if (m->hdisplay == hsize && m->vdisplay == vsize &&
drm_mode_vrefresh(m) == vrefresh_rate)
- return NULL;
+ return modes;
/* HDTV hack, part 2 */
if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
@@ -1652,19 +1653,21 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
mode->hdisplay = 1366;
mode->hsync_start = mode->hsync_start - 1;
mode->hsync_end = mode->hsync_end - 1;
- return mode;
+ goto done;
}
/* check whether it can be found in default mode table */
if (drm_monitor_supports_rb(edid)) {
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
true);
- if (mode)
- return mode;
+ if (mode) {
+ drm_mode_probed_add(connector, mode);
+ modes++;
+ }
}
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
if (mode)
- return mode;
+ goto done;
/* okay, generate it */
switch (timing_level) {
@@ -1681,7 +1684,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
*/
mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
if (!mode)
- return NULL;
+ return modes;
if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
drm_mode_destroy(dev, mode);
mode = drm_gtf_mode_complex(dev, hsize, vsize,
@@ -1697,7 +1700,11 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
false);
break;
}
- return mode;
+
+done:
+ drm_mode_probed_add(connector, mode);
+ return modes++;
+
}
/*
@@ -2179,15 +2186,10 @@ do_standard_modes(struct detailed_timing *timing, void
*c)
int i;
for (i = 0; i < 6; i++) {
struct std_timing *std;
- struct drm_display_mode *newmode;
std = >data.timings[i];
- newmode = drm_mode_std(connector, edid, std,
+ closure->modes += drm_mode_std(connector, edid, std,
edid->revision);
- if (newmode) {
- drm_mode_probed_add(connector, newmode);
- closure->modes++;
- }
}
}
}
@@ -2208,15 +2210,10 @@ add_standard_modes(struct drm_connector *connector,
struct edid *edid)
};
for (i = 0; i < EDID_STD_TIMINGS; i++) {
- struct drm_display_mode *newmode;
-
[PATCH] Enable probing of non-rb modes
With the current implementation of collecting edid modes, in case rb mode exists for a non rb mode of same resolution and vrefresh, the non-rb mode is never fed to display controller to be probed, as a result we lose on using the non-rb mode, if the display controller does not support rb mode but supports non-rb. For instance in case of 1680x1050 at 60Hz: with monitor whose EDID supports RB, if connected to display controller does not support 1680x1050 at 60Hz RB but it supports 1680x1050 at 60Hz, with the current implementation the non-rb mode 1680x1050 at 60Hz is not listed in connectors probed modes and hence on running xrandr is not listed. V2: made drm_mode_std static Shirish S (1): drm: edid: enable probing and listing of non rb modes drivers/gpu/drm/drm_edid.c | 39 ++- 1 file changed, 18 insertions(+), 21 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 34
drivers/gpu/drm/exynos/exynos_hdmi.c | 89
2 files changed, 105 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..0766e6e 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+Optional-but-recommended properties:
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "samsung,pixel-clock" specifies the pixel clock
+ "samsung,de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "samsung,clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,13 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+
+ /* ... */
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..2fa0074 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -771,20 +774,10 @@ static struct edid *hdmi_get_edid(void *ctx, struct
drm_connector *connector)
static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
{
- const struct hdmiphy_config *confs;
- int count, i;
-
- if (hdata->type == HDMI_TYPE13) {
- confs = hdmiphy_v13_configs;
- count = ARRAY_SIZE(hdmiphy_v13_configs);
- } else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
- } else
- return -EINVAL;
+ int i;
- for (i = 0; i < count; i++)
- if (confs[i].pixel_clock == pixel_clock)
+ for (i = 0; i < hdata->nr_confs; i++)
+ if (hdata->confs[i].pixel_clock == pixel_clock)
return i;
DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
@@ -1363,10 +1356,7 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
return;
}
- if (hdata->type == HDMI_TYPE13)
- hdmiphy_data = hdmiphy_v13_configs
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..45c8583 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..6bc562c 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..10da02f 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. V8: Fixed build error V9: rebased and incorporated Tomasz comments. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 34 arch/arm/boot/dts/cros5250-common.dtsi | 74 arch/arm/boot/dts/exynos5250-arndale.dts | 74 arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 drivers/gpu/drm/exynos/exynos_hdmi.c | 89 5 files changed, 327 insertions(+), 18 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
+ linux-samsung-soc mailing list. On Wed, Dec 4, 2013 at 10:05 AM, Shirish S wrote: > Hi Tomasz, > Thanks for the reivew, please see my replies inline. > > On Fri, Nov 29, 2013 at 10:56 PM, Tomasz Figa wrote: >> Hi Shirish, >> >> Please see my comments inline. >> >> On Monday 25 of November 2013 14:24:39 Shirish S wrote: >>> This patch adds dt support to hdmiphy config settings >>> as it is board specific and depends on the signal pattern >>> of board. >>> >>> Signed-off-by: Shirish S >>> --- >>> .../devicetree/bindings/video/exynos_hdmi.txt | 31 >>> drivers/gpu/drm/exynos/exynos_hdmi.c | 77 >>> +++- >>> 2 files changed, 104 insertions(+), 4 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> index 323983b..6eeb333 100644 >>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> @@ -13,6 +13,30 @@ Required properties: >>> b) pin number within the gpio controller. >>> c) optional flags and pull up/down. >>> >>> +- hdmiphy-configs: following information about the hdmiphy config settings. >> >> Is this node required or optional? If it's required, then it breaks >> compatibility with already existing DTBs, which is not desirable. >> > Yes its an Optional-but-recommended node, and i have mentioned the same > in this document in next patch set(v9). >>> + a) "config: config" specifies the phy configuration settings, >>> + where 'N' denotes the number of configuration, since every >>> + pixel clock can have its unique configuration. >> >> Node names should not have any semantic meaning for parsing code. I know >> that there are already existing bindings which rely on presence of >> particularly named nodes, but that's not right and new bindings should >> not follow that. >> > I referred Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt > for the implementation, am not clear with what you want me to do here, however > the requirement seems similar as pinctrl, can u kindly suggest any > existing newer > implementations to refer. >> Also what do you need the label of each config node for? >> > Each label here is a different pixel clock and corresponding phy setting, and > it may vary from one pixel clock to other hence i need one for each config > node. >> Generally from parsing perspective you shouldn't really care about node >> names. All you seem to do in the driver is iterating over all specified >> nodes and matching them with internal driver data using pixel clock >> frequency. >> > True, that is what i intended to do.I think for the requirement > at hand, this should be fine. >>> + "pixel-clock" specifies the pixel clock >> >> Vendor-specific properties should have vendor prefix, so this one should >> be called "samsung,pixel-clock". >> > Agreed, updated in the next patch set(v9). >>> + "conifig-de-emphasis-level" provides fine control of TMDS data >> >> Typo: s/conifig/config >> >> Also it should be called "samsung,de-emphasis-level". >> > Agreed, updated in the next patch set(v9). >>> + pre emphasis, below shown is example for >>> + data de-emphasis register at address 0x145D0040. >>> + hdmiphy at 38[16] for bits[3:0] permitted values are >>> in >>> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff >>> + increments for every LSB >>> + hdmiphy at 38[16] for bits[7:4] permitted values are >>> in >>> + the range of 0dB to -7.45dB at increments of -0.45dB >>> + for every LSB. >>> + "config-clock-level" provides fine control of TMDS data >> >> "samsung,clock-level" >> > Agreed, updated in the next patch set(v9). >>> + amplitude for each channel, >>> + for example if 0x145D005C is the address of clock level >> [snip] >>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c >>> b/drivers/gpu/drm/exynos/exynos_hdmi.c >>> index 32ce9a6..5f599e3 100644 >>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c >>>
[PATCH] Enable probing of non-rb modes
Gentle Reminder! On Mon, Nov 25, 2013 at 2:21 PM, Shirish S wrote: > With the current implementation of collecting edid modes, > in case rb mode exists for a non rb mode of same resolution and > vrefresh, the non-rb mode is never fed to display controller to be > probed, as a result we lose on using the non-rb mode, if the display > controller does not support rb mode but supports non-rb. > > > For instance in case of 1680x1050 at 60Hz: > with monitor whose EDID supports RB, > if connected to display controller does not support 1680x1050 at 60Hz RB but > it > supports 1680x1050 at 60Hz, with the current implementation the non-rb mode > 1680x1050 at 60Hz is not listed in connectors probed modes and hence on > running > xrandr is not listed. > > V2: Incorporate review comments by Adam Jackson > remove suffix of 'rb' > > Shirish S (1): > drm: edid: enable probing and listing of non rb modes > > drivers/gpu/drm/drm_edid.c | 40 ++-- > 1 file changed, 18 insertions(+), 22 deletions(-) > > -- > 1.7.9.5 >
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 34
drivers/gpu/drm/exynos/exynos_hdmi.c | 89
2 files changed, 105 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..0766e6e 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+Optional-but-recommended properties:
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "samsung,pixel-clock" specifies the pixel clock
+ "samsung,de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "samsung,clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,13 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+
+ /* ... */
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..2fa0074 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -771,20 +774,10 @@ static struct edid *hdmi_get_edid(void *ctx, struct
drm_connector *connector)
static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
{
- const struct hdmiphy_config *confs;
- int count, i;
-
- if (hdata->type == HDMI_TYPE13) {
- confs = hdmiphy_v13_configs;
- count = ARRAY_SIZE(hdmiphy_v13_configs);
- } else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
- } else
- return -EINVAL;
+ int i;
- for (i = 0; i < count; i++)
- if (confs[i].pixel_clock == pixel_clock)
+ for (i = 0; i < hdata->nr_confs; i++)
+ if (hdata->confs[i].pixel_clock == pixel_clock)
return i;
DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
@@ -1363,10 +1356,7 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
return;
}
- if (hdata->type == HDMI_TYPE13)
- hdmiphy_data = hdmiphy_v13_configs
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..45c8583 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..6bc562c 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..10da02f 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = <2520>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ samsung,pixel-clock = <2700>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ samsung,pixel-clock = <27027000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ samsung,pixel-clock = <3600>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ samsung,pixel-clock = <4000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ samsung,pixel-clock = <6500>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ samsung,pixel-clock = <74176000>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ samsung,pixel-clock = <7425>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ samsung,pixel-clock = <8350>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ samsung,pixel-clock = <10650>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ samsung,pixel-clock = <10800>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ samsung,pixel-clock = <14625>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ samsung,pixel-clock = <14850>;
+ samsung,de-emphasis-level = /bits/ 8 <0x26>;
+ samsung,clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. V8: Fixed build error V9: rebased and incorporated Tomasz comments. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 34 arch/arm/boot/dts/cros5250-common.dtsi | 74 arch/arm/boot/dts/exynos5250-arndale.dts | 74 arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 drivers/gpu/drm/exynos/exynos_hdmi.c | 89 5 files changed, 327 insertions(+), 18 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi Tomasz,
Thanks for the reivew, please see my replies inline.
On Fri, Nov 29, 2013 at 10:56 PM, Tomasz Figa wrote:
> Hi Shirish,
>
> Please see my comments inline.
>
> On Monday 25 of November 2013 14:24:39 Shirish S wrote:
>> This patch adds dt support to hdmiphy config settings
>> as it is board specific and depends on the signal pattern
>> of board.
>>
>> Signed-off-by: Shirish S
>> ---
>> .../devicetree/bindings/video/exynos_hdmi.txt | 31
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 77
>> +++-
>> 2 files changed, 104 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> index 323983b..6eeb333 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> @@ -13,6 +13,30 @@ Required properties:
>> b) pin number within the gpio controller.
>> c) optional flags and pull up/down.
>>
>> +- hdmiphy-configs: following information about the hdmiphy config settings.
>
> Is this node required or optional? If it's required, then it breaks
> compatibility with already existing DTBs, which is not desirable.
>
Yes its an Optional-but-recommended node, and i have mentioned the same
in this document in next patch set(v9).
>> + a) "config: config" specifies the phy configuration settings,
>> + where 'N' denotes the number of configuration, since every
>> + pixel clock can have its unique configuration.
>
> Node names should not have any semantic meaning for parsing code. I know
> that there are already existing bindings which rely on presence of
> particularly named nodes, but that's not right and new bindings should
> not follow that.
>
I referred Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
for the implementation, am not clear with what you want me to do here, however
the requirement seems similar as pinctrl, can u kindly suggest any
existing newer
implementations to refer.
> Also what do you need the label of each config node for?
>
Each label here is a different pixel clock and corresponding phy setting, and
it may vary from one pixel clock to other hence i need one for each config node.
> Generally from parsing perspective you shouldn't really care about node
> names. All you seem to do in the driver is iterating over all specified
> nodes and matching them with internal driver data using pixel clock
> frequency.
>
True, that is what i intended to do.I think for the requirement
at hand, this should be fine.
>> + "pixel-clock" specifies the pixel clock
>
> Vendor-specific properties should have vendor prefix, so this one should
> be called "samsung,pixel-clock".
>
Agreed, updated in the next patch set(v9).
>> + "conifig-de-emphasis-level" provides fine control of TMDS data
>
> Typo: s/conifig/config
>
> Also it should be called "samsung,de-emphasis-level".
>
Agreed, updated in the next patch set(v9).
>> + pre emphasis, below shown is example for
>> + data de-emphasis register at address 0x145D0040.
>> + hdmiphy at 38[16] for bits[3:0] permitted values are in
>> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
>> + increments for every LSB
>> + hdmiphy at 38[16] for bits[7:4] permitted values are in
>> + the range of 0dB to -7.45dB at increments of -0.45dB
>> + for every LSB.
>> + "config-clock-level" provides fine control of TMDS data
>
> "samsung,clock-level"
>
Agreed, updated in the next patch set(v9).
>> + amplitude for each channel,
>> + for example if 0x145D005C is the address of clock level
> [snip]
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 32ce9a6..5f599e3 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
> [snip]
>> +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
>> + struct hdmi_context *hdata)
>> +{
>> + struct device *dev = >dev;
>> + struct device_node *dev_np = dev->of_node;
>> + struct device_node *phy_conf, *cfg_np;
>> + int i, pixel_clock = 0;
>> +
>> + /* Initialize with default config */
>> + hdata->c
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 31
drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++-
2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..6eeb333 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,30 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "config-clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +44,11 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..7934c6e 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1894,6 +1897,63 @@ fail:
return -ENODEV;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+ struct device *dev = >dev;
+ struct device_node *dev_np = dev->of_node;
+ struct device_node *phy_conf, *cfg
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..77408c6 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..48b00f7 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..96e2cad 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. V8: Fixed build error Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 31 arch/arm/boot/dts/cros5250-common.dtsi | 74 +++ arch/arm/boot/dts/exynos5250-arndale.dts | 74 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++- 5 files changed, 326 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi,
On Tue, Nov 26, 2013 at 6:30 AM, Inki Dae wrote:
> Hi Shirish,
>
> 2013/11/25 Shirish S :
>> This patch adds dt support to hdmiphy config settings
>> as it is board specific and depends on the signal pattern
>> of board.
>>
>> Signed-off-by: Shirish S
>> ---
>> .../devicetree/bindings/video/exynos_hdmi.txt | 31
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 77
>> +++-
>> 2 files changed, 104 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> index 323983b..6eeb333 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> @@ -13,6 +13,30 @@ Required properties:
>> b) pin number within the gpio controller.
>> c) optional flags and pull up/down.
>>
>> +- hdmiphy-configs: following information about the hdmiphy config settings.
>> + a) "config: config" specifies the phy configuration settings,
>> + where 'N' denotes the number of configuration, since every
>> + pixel clock can have its unique configuration.
>> + "pixel-clock" specifies the pixel clock
>> + "conifig-de-emphasis-level" provides fine control of TMDS
>> data
>> +pre emphasis, below shown is example for
>> + data de-emphasis register at address 0x145D0040.
>> + hdmiphy at 38[16] for bits[3:0] permitted values are
>> in
>> + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
>> + increments for every LSB
>> + hdmiphy at 38[16] for bits[7:4] permitted values are
>> in
>> + the range of 0dB to -7.45dB at increments of -0.45dB
>> + for every LSB.
>> + "config-clock-level" provides fine control of TMDS data
>> + amplitude for each channel,
>> + for example if 0x145D005C is the address of clock level
>> + register then,
>> + hdmiphy at 38[23] for bits [1:0] permitted values
>> are in
>> + the range of 0 mVdiff & 60 mVdiff for each channel at
>> + increments 20 mVdiff of amplitude levels for every
>> LSB,
>> + hdmiphy at 38[23] for bits [7:3] permitted values
>> are in
>> + the range of 790 and 1430 mV at 20mV increments for
>> + every LSB.
>> Example:
>>
>> hdmi {
>> @@ -20,4 +44,11 @@ Example:
>> reg = <0x1453 0x10>;
>> interrupts = <0 95 0>;
>> hpd-gpio = < 7 1>;
>> + hdmiphy-configs {
>> + config0: config0 {
>> + pixel-clock = <2520>;
>> + config-de-emphasis-level = /bits/ 8 <0x26>;
>> + config-clock-level = /bits/ 8 < 0x66>;
>> + };
>> + }
>> };
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 32ce9a6..5f599e3 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -197,6 +197,9 @@ struct hdmi_context {
>>
>> struct hdmi_resources res;
>>
>> + struct hdmiphy_config *confs;
>> + int nr_confs;
>> +
>> int hpd_gpio;
>>
>> enum hdmi_type type;
>> @@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
>> = {
>> },
>> };
>>
>> -static const struct hdmiphy_config hdmiphy_v14_configs[] = {
>> +static struct hdmiphy_config hdmiphy_v14_configs[] = {
>> {
>> .pixel_clock = 2520,
>> .conf = {
>> @@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context
>> *hdata, u32 pixel_clock)
>> confs = hdmiphy_v13_configs;
>> count = ARRAY_SIZE(hdmiphy_v13_configs);
>> } else if (hdata->type == HDMI_TYPE14) {
>> - confs = hdmiphy_v14
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 31
drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++-
2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..6eeb333 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,30 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "config-clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +44,11 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..5f599e3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1894,6 +1897,63 @@ fail:
return -ENODEV;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+ struct device *dev = >dev;
+ struct device_node *dev_np = dev->of_node;
+ struct device_node *phy_conf, *cfg
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..77408c6 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..48b00f7 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH] drm: edid: enable probing and listing of non rb modes
The current solution checks for the existing RB mode,
if available in the edid block returns by adding it,
but does not populate the connector with the modes
of same resolution but which are non-rb modes.
As a result the probing and listing of non-rb modes can't
be made, in case the rb mode's pixel clock is not
supported but non-rb mode is supported.
This patch changes the drm_mode_std mode selection to
collect all the supported modes and not just one mode.
Signed-off-by: Shirish S
---
drivers/gpu/drm/drm_edid.c | 40 ++--
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fb7cf0e..765aa96 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1587,12 +1587,12 @@ bad_std_timing(u8 a, u8 b)
* Take the standard timing params (in this case width, aspect, and refresh)
* and convert them into a real mode using CVT/GTF/DMT.
*/
-static struct drm_display_mode *
-drm_mode_std(struct drm_connector *connector, struct edid *edid,
+unsigned int drm_mode_std(struct drm_connector *connector, struct edid *edid,
struct std_timing *t, int revision)
{
struct drm_device *dev = connector->dev;
struct drm_display_mode *m, *mode = NULL;
+ unsigned int modes = 0;
int hsize, vsize;
int vrefresh_rate;
unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
@@ -1602,7 +1602,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
int timing_level = standard_timing_level(edid);
if (bad_std_timing(t->hsize, t->vfreq_aspect))
- return NULL;
+ return modes;
/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
hsize = t->hsize * 8 + 248;
@@ -1638,7 +1638,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
list_for_each_entry(m, >probed_modes, head)
if (m->hdisplay == hsize && m->vdisplay == vsize &&
drm_mode_vrefresh(m) == vrefresh_rate)
- return NULL;
+ return modes;
/* HDTV hack, part 2 */
if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
@@ -1647,19 +1647,21 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
mode->hdisplay = 1366;
mode->hsync_start = mode->hsync_start - 1;
mode->hsync_end = mode->hsync_end - 1;
- return mode;
+ goto done;
}
/* check whether it can be found in default mode table */
if (drm_monitor_supports_rb(edid)) {
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
true);
- if (mode)
- return mode;
+ if (mode) {
+ drm_mode_probed_add(connector, mode);
+ modes++;
+ }
}
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
if (mode)
- return mode;
+ goto done;
/* okay, generate it */
switch (timing_level) {
@@ -1676,7 +1678,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
*/
mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
if (!mode)
- return NULL;
+ return modes;
if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
drm_mode_destroy(dev, mode);
mode = drm_gtf_mode_complex(dev, hsize, vsize,
@@ -1692,7 +1694,11 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
false);
break;
}
- return mode;
+
+done:
+ drm_mode_probed_add(connector, mode);
+ return modes++;
+
}
/*
@@ -2174,15 +2180,10 @@ do_standard_modes(struct detailed_timing *timing, void
*c)
int i;
for (i = 0; i < 6; i++) {
struct std_timing *std;
- struct drm_display_mode *newmode;
std = >data.timings[i];
- newmode = drm_mode_std(connector, edid, std,
+ closure->modes += drm_mode_std(connector, edid, std,
edid->revision);
- if (newmode) {
- drm_mode_probed_add(connector, newmode);
- closure->modes++;
- }
}
}
}
@@ -2203,15 +2204,10 @@ add_standard_modes(struct drm_connector *connector,
struct edid *edid)
};
for (i = 0; i < EDID_STD_TIMINGS; i++) {
-
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..96e2cad 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 31 arch/arm/boot/dts/cros5250-common.dtsi | 74 +++ arch/arm/boot/dts/exynos5250-arndale.dts | 74 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++- 5 files changed, 326 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH] drm: edid: enable probing and listing of non rb modes
The current solution checks for the existing RB mode,
if available in the edid block returns by adding it,
but does not populate the connector with the modes
of same resolution but which are non-rb modes.
As a result the probing and listing of non-rb modes can't
be made, in case the rb mode's pixel clock is not
supported but non-rb mode is supported.
This patch changes the drm_mode_std mode selection to
collect all the supported modes and not just one mode.
Signed-off-by: Shirish S
---
drivers/gpu/drm/drm_edid.c | 40 ++--
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fb7cf0e..765aa96 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1587,12 +1587,12 @@ bad_std_timing(u8 a, u8 b)
* Take the standard timing params (in this case width, aspect, and refresh)
* and convert them into a real mode using CVT/GTF/DMT.
*/
-static struct drm_display_mode *
-drm_mode_std(struct drm_connector *connector, struct edid *edid,
+unsigned int drm_mode_std(struct drm_connector *connector, struct edid *edid,
struct std_timing *t, int revision)
{
struct drm_device *dev = connector->dev;
struct drm_display_mode *m, *mode = NULL;
+ unsigned int modes = 0;
int hsize, vsize;
int vrefresh_rate;
unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
@@ -1602,7 +1602,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
int timing_level = standard_timing_level(edid);
if (bad_std_timing(t->hsize, t->vfreq_aspect))
- return NULL;
+ return modes;
/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
hsize = t->hsize * 8 + 248;
@@ -1638,7 +1638,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
list_for_each_entry(m, >probed_modes, head)
if (m->hdisplay == hsize && m->vdisplay == vsize &&
drm_mode_vrefresh(m) == vrefresh_rate)
- return NULL;
+ return modes;
/* HDTV hack, part 2 */
if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
@@ -1647,19 +1647,21 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
mode->hdisplay = 1366;
mode->hsync_start = mode->hsync_start - 1;
mode->hsync_end = mode->hsync_end - 1;
- return mode;
+ goto done;
}
/* check whether it can be found in default mode table */
if (drm_monitor_supports_rb(edid)) {
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
true);
- if (mode)
- return mode;
+ if (mode) {
+ drm_mode_probed_add(connector, mode);
+ modes++;
+ }
}
mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
if (mode)
- return mode;
+ goto done;
/* okay, generate it */
switch (timing_level) {
@@ -1676,7 +1678,7 @@ drm_mode_std(struct drm_connector *connector, struct edid
*edid,
*/
mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
if (!mode)
- return NULL;
+ return modes;
if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
drm_mode_destroy(dev, mode);
mode = drm_gtf_mode_complex(dev, hsize, vsize,
@@ -1692,7 +1694,11 @@ drm_mode_std(struct drm_connector *connector, struct
edid *edid,
false);
break;
}
- return mode;
+
+done:
+ drm_mode_probed_add(connector, mode);
+ return modes++;
+
}
/*
@@ -2174,15 +2180,10 @@ do_standard_modes(struct detailed_timing *timing, void
*c)
int i;
for (i = 0; i < 6; i++) {
struct std_timing *std;
- struct drm_display_mode *newmode;
std = >data.timings[i];
- newmode = drm_mode_std(connector, edid, std,
+ closure->modes += drm_mode_std(connector, edid, std,
edid->revision);
- if (newmode) {
- drm_mode_probed_add(connector, newmode);
- closure->modes++;
- }
}
}
}
@@ -2203,15 +2204,10 @@ add_standard_modes(struct drm_connector *connector,
struct edid *edid)
};
for (i = 0; i < EDID_STD_TIMINGS; i++) {
-
[PATCH] Enable probing of non-rb modes
With the current implementation of collecting edid modes, in case rb mode exists for a non rb mode of same resolution and vrefresh, the non-rb mode is never fed to display controller to be probed, as a result we lose on using the non-rb mode, if the display controller does not support rb mode but supports non-rb. For instance in case of 1680x1050 at 60Hz: with monitor whose EDID supports RB, if connected to display controller does not support 1680x1050 at 60Hz RB but it supports 1680x1050 at 60Hz, with the current implementation the non-rb mode 1680x1050 at 60Hz is not listed in connectors probed modes and hence on running xrandr is not listed. V2: Incorporate review comments by Adam Jackson remove suffix of 'rb' Shirish S (1): drm: edid: enable probing and listing of non rb modes drivers/gpu/drm/drm_edid.c | 40 ++-- 1 file changed, 18 insertions(+), 22 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi Mark, I have uploaded patch set 5 and 6 back to back, but unfortunately still nr-configs is stuck in the example explanation in the exynos_hdmi.txt, just to inform you that am waiting for your review comments so that i can rectify it along with them in the next patch set. Regards, Shirish S On Mon, Nov 18, 2013 at 11:37 AM, Shirish S wrote: > Hi, > > On Fri, Nov 15, 2013 at 9:47 PM, Mark Rutland wrote: >> On Tue, Oct 29, 2013 at 08:12:32AM +, Shirish S wrote: >>> This patch adds dt support to hdmiphy config settings >>> as it is board specific and depends on the signal pattern >>> of board. >>> >>> Signed-off-by: Shirish S >>> --- >>> .../devicetree/bindings/video/exynos_hdmi.txt | 34 + >>> drivers/gpu/drm/exynos/exynos_hdmi.c | 79 >>> +++- >>> 2 files changed, 109 insertions(+), 4 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> index 323983b..c685c90 100644 >>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >>> @@ -13,6 +13,32 @@ Required properties: >>> b) pin number within the gpio controller. >>> c) optional flags and pull up/down. >>> >>> +- hdmiphy-configs: following information about the hdmiphy config settings. >>> +a) "nr-configs" specifies the number of pixel clocks supported. >> >> I really don't see why this is necessary. It's redundant, and it's easy >> for the driver to derive this from the number of config nodes, which >> it can count. >> > Agreed, i have removed this field and now use the pixel clock to update the > required values. >>> + b) "config: config" specifies the phy configuration settings, >>> + wher 'N' denotes the number of iteration. >> >> The number of iteration? > Corrected in next patch set. >> >>> + "pixel-clock" specifies the pixel clock >>> + "conifig-de-emphasis-level" specifies the 8 bit configuration >>> + of Data De-emphasis levels,below shown is example for >>> + data de-emphasis register at address 0x145D0040. >>> + hdmiphy at 38[16] for bits[3:0] permitted values: >>> + means 760 mVdiff && means 1400 >>> mVdiff >>> + 1LSB corresponds to 20mVdiff >>> + hdmiphy at 38[16] for bits[7:4] permitted values: >>> + 0dB >>> + 0001-0.25dB >>> + 0010-0.7dB >>> + 0011-1.15dB >>> + -7.45dB >>> + "config-clock-level" specifies the 8 bit configuration for >>> + the corresponding clock level, for example if 0x145D005C >>> + is the address of clock level register. >> >> I don't understand what this intended to mean. > Have updated in next patch set, hope its understandable. >> >>> + hdmiphy at 38[23] for bits [1:0] permitted values: >>> + 00 means 0 mVdiff && 11 means 60 mVdiff >>> + hdmiphy at 38[23] for bits [7:3] permitted values: >>> + 0 is 790 mVdiff >>> + 1 is 1430 mVdiff >>> + 1LSB corresponds to 20mVdiff >> >> That last line was confusing. Why not state that this is a value between >> 790 and 1430 mV in 20mV increments? >> > Agreed, have made the change in next patch set. >> Thanks, >> Mark. > Thanks, > Shirish S
[PATCH] drm: edid: enable probing and listing of non rb modes
Hi,
On Sat, Nov 16, 2013 at 12:29 AM, Adam Jackson wrote:
> On Fri, 2013-11-15 at 10:38 +0530, Shirish S wrote:
>> The current solution checks for the existing RB mode,
>> if available in the edid block returns by adding it,
>> but does not populate the connector with the modes
>> of same resolution but which are non-rb modes.
>>
>> As a result the probing and listing of non-rb modes can't
>> be made, in case the rb mode's pixel clock is not
>> supported but non-rb mode is supported.
>
> This is... almost okay.
>
> So the EDID 1.4 spec says that for modes in standard descriptors:
>
> a) if there's a match in DMT, use DMT
> b) if there's a range descriptor and it says GTF, use GTF
> c) if there's a range descriptor and it says CVT, use CVT
> d) if there's no range descriptor, use CVT
>
> But case d) is clearly insane if the sink is EDID 1.3, CVT wasn't a
> standard when 1.3 was defined, so the sink may not in fact support CVT
> timings. Hence the logic in standard_timing_level().
>
> The other thing the spec says is that if you're using CVT for standard
> descriptors that you should use normal blanking instead of reduced.
> This is... problematic. If we see 1920x1200 at 60 in a standard descriptor
> we almost certainly _don't_ mean normal blanking, because that won't fit
> on single-link DVI. And if both the source and the sink support reduced
> blanking we should probably prefer it, it's marginally less power
> consumption on digital links and marginally better picture quality on
> analog links.
>
> So probably what we should do instead is:
>
> - if drm_monitor_supports_rb(), add both normal and reduced blanking
> timings for either the DMT or CVT path
> - extend drm_connector to also have rb-allowed to match interlace and
> doublescan
> - fix up all the drivers to indicate rb-allowed (except whatever broken
> thing it is you're trying to work around here)
> - fix drm_mode_validate_flag and callers to filter out rb modes as
> appropriate
>
> Also: CVT dates to 2003. EDID 1.4 was 2006. Any hardware being made in
> 2013 that can't generate RB timings is going out of its way to be
> broken. You should really demand better from your hardware.
>
True, but we have to deal with such hardware also, so with this patch
can we add up to the mode collection logic, to accomodate such hardwares also?
>> 1. adds "rb" suffix to rb modes.
>
> No. The userspace convention is:
>
> dmt:~% cvt -r 1920 1080
> # 1920x1080 59.93 Hz (CVT 2.07M9-R) hsync: 66.59 kHz; pclk: 138.50 MHz
> Modeline "1920x1080R" 138.50 1920 1968 2000 2080 1080 1083 1088
> +hsync -vsync
>
> drm_mode_parse_command_line_for_connector() expects the same thing.
> Let's be consistent.
>
I found that there is a suffix for interlaced modes, which got added
recently, hence thought of adding this,
with the addition of 'rb" suffix my system shows up more modes that is
supports and there is no need to
actually set the particular mode to know if its RB or non-RB.
Without this change it never showed 1920x1080R kind of mode, am i
missing anything?
>> @@ -1621,19 +1621,20 @@ drm_mode_std(struct drm_connector *connector, struct
>> edid *edid,
>> mode->hdisplay = 1366;
>> mode->hsync_start = mode->hsync_start - 1;
>> mode->hsync_end = mode->hsync_end - 1;
>> - return mode;
>> + goto done;
>> }
>>
>> /* check whether it can be found in default mode table */
>> if (drm_monitor_supports_rb(edid)) {
>> mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
>>true);
>> - if (mode)
>> - return mode;
>> + if (mode) {
>> + drm_mode_probed_add(connector, mode);
>> + modes++;
>> + }
>> }
>> mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
>> - if (mode)
>> - return mode;
>> + goto done;
>>
>> /* okay, generate it */
>> switch (timing_level) {
>
> Unconditional "goto done" that skips all the logic for generating modes
> not in the dmt list? This breaks everything _but_ case a) above, so eg.
> 1600x900 at 60 would no longer be generated.
>
My bad ,missed it, will correct it in the next patch set, if you are
ok with this logic of mine.
Kindly confirm if you want me to send next patch set with updated
changes or what/way i am working on
is not required.
> - ajax
>
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 33 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++-
2 files changed, 106 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..1021c74 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+a) "nr-configs" specifies the number of pixel clocks supported.
+ b) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "config-clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,12 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ nr-configs = <1>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..5f599e3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1894,6 +1897,63 @@ fail:
return -ENODEV;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 74
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..77408c6 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..48b00f7 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..96e2cad 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: removed nr-configs form the dtsi files. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 33 + arch/arm/boot/dts/cros5250-common.dtsi | 74 +++ arch/arm/boot/dts/exynos5250-arndale.dts | 74 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++- 5 files changed, 328 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 33 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++-
2 files changed, 106 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..1021c74 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+a) "nr-configs" specifies the number of pixel clocks supported.
+ b) "config: config" specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy at 38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ "config-clock-level" provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy at 38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff & 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy at 38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,12 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ nr-configs = <1>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..5f599e3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1894,6 +1897,63 @@ fail:
return -ENODEV;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..3cd1779 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,81 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 75 ++
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..c771ba3 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,81 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 75 +
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..e1f4e08 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,81 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 33 + arch/arm/boot/dts/cros5250-common.dtsi | 75 +++ arch/arm/boot/dts/exynos5250-arndale.dts | 75 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 75 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++- 5 files changed, 331 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi, On Fri, Nov 15, 2013 at 9:47 PM, Mark Rutland wrote: > On Tue, Oct 29, 2013 at 08:12:32AM +0000, Shirish S wrote: >> This patch adds dt support to hdmiphy config settings >> as it is board specific and depends on the signal pattern >> of board. >> >> Signed-off-by: Shirish S >> --- >> .../devicetree/bindings/video/exynos_hdmi.txt | 34 + >> drivers/gpu/drm/exynos/exynos_hdmi.c | 79 >> +++- >> 2 files changed, 109 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> index 323983b..c685c90 100644 >> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> @@ -13,6 +13,32 @@ Required properties: >> b) pin number within the gpio controller. >> c) optional flags and pull up/down. >> >> +- hdmiphy-configs: following information about the hdmiphy config settings. >> +a) "nr-configs" specifies the number of pixel clocks supported. > > I really don't see why this is necessary. It's redundant, and it's easy > for the driver to derive this from the number of config nodes, which > it can count. > Agreed, i have removed this field and now use the pixel clock to update the required values. >> + b) "config: config" specifies the phy configuration settings, >> + wher 'N' denotes the number of iteration. > > The number of iteration? Corrected in next patch set. > >> + "pixel-clock" specifies the pixel clock >> + "conifig-de-emphasis-level" specifies the 8 bit configuration >> + of Data De-emphasis levels,below shown is example for >> + data de-emphasis register at address 0x145D0040. >> + hdmiphy at 38[16] for bits[3:0] permitted values: >> + means 760 mVdiff && means 1400 mVdiff >> + 1LSB corresponds to 20mVdiff >> + hdmiphy at 38[16] for bits[7:4] permitted values: >> + 0dB >> + 0001-0.25dB >> + 0010-0.7dB >> + 0011-1.15dB >> + -7.45dB >> + "config-clock-level" specifies the 8 bit configuration for >> + the corresponding clock level, for example if 0x145D005C >> + is the address of clock level register. > > I don't understand what this intended to mean. Have updated in next patch set, hope its understandable. > >> + hdmiphy at 38[23] for bits [1:0] permitted values: >> + 00 means 0 mVdiff && 11 means 60 mVdiff >> + hdmiphy at 38[23] for bits [7:3] permitted values: >> + 0 is 790 mVdiff >> + 1 is 1430 mVdiff >> + 1LSB corresponds to 20mVdiff > > That last line was confusing. Why not state that this is a value between > 790 and 1430 mV in 20mV increments? > Agreed, have made the change in next patch set. > Thanks, > Mark. Thanks, Shirish S
[PATCH] drm: edid: enable probing and listing of non rb modes
The current solution checks for the existing RB mode,
if available in the edid block returns by adding it,
but does not populate the connector with the modes
of same resolution but which are non-rb modes.
As a result the probing and listing of non-rb modes can't
be made, in case the rb mode's pixel clock is not
supported but non-rb mode is supported.
This patch does 2 things:
1. adds "rb" suffix to rb modes.
2. changes the drm_mode_std mode selection to collect
all the supported modes and not just one mode.
Signed-off-by: Shirish S
---
drivers/gpu/drm/drm_edid.c | 74 +---
1 file changed, 36 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 830f750..3276761 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -184,7 +184,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
896, 1048, 0, 600, 601, 604, 631, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 800x600 at 120Hz RB */
- { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
+ { DRM_MODE("800x600rb", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
880, 960, 0, 600, 603, 607, 636, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 848x480 at 60Hz */
@@ -213,7 +213,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1168, 1376, 0, 768, 769, 772, 808, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1024x768 at 120Hz RB */
- { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
+ { DRM_MODE("1024x768rb", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
1104, 1184, 0, 768, 771, 775, 813, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1152x864 at 75Hz */
@@ -221,7 +221,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1344, 1600, 0, 864, 865, 868, 900, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1280x768 at 60Hz RB */
- { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
+ { DRM_MODE("1280x768rb", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
1360, 1440, 0, 768, 771, 778, 790, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1280x768 at 60Hz */
@@ -237,11 +237,11 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1496, 1712, 0, 768, 771, 778, 809, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1280x768 at 120Hz RB */
- { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
+ { DRM_MODE("1280x768rb", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
1360, 1440, 0, 768, 771, 778, 813, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1280x800 at 60Hz RB */
- { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
+ { DRM_MODE("1280x800rb", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
1360, 1440, 0, 800, 803, 809, 823, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1280x800 at 60Hz */
@@ -257,7 +257,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1496, 1712, 0, 800, 803, 809, 843, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1280x800 at 120Hz RB */
- { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
+ { DRM_MODE("1280x800rb", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
1360, 1440, 0, 800, 803, 809, 847, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1280x960 at 60Hz */
@@ -269,7 +269,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1504, 1728, 0, 960, 961, 964, 1011, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1280x960 at 120Hz RB */
- { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
+ { DRM_MODE("1280x960rb", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
1360, 1440, 0, 960, 963, 967, 1017, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
/* 1280x1024 at 60Hz */
@@ -285,7 +285,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
/* 1280x1024 at 120Hz RB */
- { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
+ { DRM_MODE("1280x1024rb", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
[PATCH] Enable probing of non-rb modes
With the current implementation of collecting edid modes, in case rb mode exists for a non rb mode of same resolution and vrefresh, the non-rb mode is never fed to display controller to be probed, as a result we lose on using the non-rb mode, if the display controller does not support rb mode but supports non-rb. For instance in case of 1680x1050 at 60Hz: with monitor whose EDID supports RB, if connected to display controller does not support 1680x1050 at 60Hz RB but it supports 1680x1050 at 60Hz, with the current implementation the non-rb mode 1680x1050 at 60Hz is not listed in connectors probed modes and hence on running xrandr is not listed. Shirish S (1): drm: edid: enable probing and listing of non rb modes drivers/gpu/drm/drm_edid.c | 74 +--- 1 file changed, 36 insertions(+), 38 deletions(-) -- 1.7.9.5
[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 34 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 79 +++-
2 files changed, 109 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..c685c90 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,32 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+a) "nr-configs" specifies the number of pixel clocks supported.
+ b) "config: config" specifies the phy configuration settings,
+ wher 'N' denotes the number of iteration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" specifies the 8 bit configuration
+ of Data De-emphasis levels,below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy at 38[16] for bits[3:0] permitted values:
+ means 760 mVdiff && means 1400 mVdiff
+ 1LSB corresponds to 20mVdiff
+ hdmiphy at 38[16] for bits[7:4] permitted values:
+ 0dB
+ 0001-0.25dB
+ 0010-0.7dB
+ 0011-1.15dB
+ -7.45dB
+ "config-clock-level" specifies the 8 bit configuration for
+ the corresponding clock level, for example if 0x145D005C
+ is the address of clock level register.
+ hdmiphy at 38[23] for bits [1:0] permitted values:
+ 00 means 0 mVdiff && 11 means 60 mVdiff
+ hdmiphy at 38[23] for bits [7:3] permitted values:
+ 0 is 790 mVdiff
+ 1 is 1430 mVdiff
+ 1LSB corresponds to 20mVdiff
Example:
hdmi {
@@ -20,4 +46,12 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ nr-configs = <1>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..065ac1f 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -197,6 +197,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1894,6 +1897,65 @@ fail:
return -ENODEV;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
[PATCH 3/4] ARM: exynos: dts: cros5250: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/cros5250-common.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..3cd1779 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -301,6 +301,81 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
gpio-keys {
--
1.7.9.5
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 75 ++
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..c771ba3 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,81 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
regulators {
--
1.7.9.5
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 75 +
1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..e1f4e08 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,81 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB & Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 34 + arch/arm/boot/dts/cros5250-common.dtsi | 75 +++ arch/arm/boot/dts/exynos5250-arndale.dts | 75 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 75 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 79 +++- 5 files changed, 334 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
On Tue, Oct 29, 2013 at 4:08 AM, Mark Rutland wrote: > On Mon, Oct 28, 2013 at 10:15:00AM +0000, Shirish S wrote: >> Hi Mark, >> Firstly thanks for reviewing. > > Hi, > > Please could you refrain from replying in HTML and use plaintext, it's rather > difficult to respond sensibly. > Sorry for your troubles,hope with this reply its fine. >> >> >> On Mon, Oct 28, 2013 at 12:20 PM, Mark Rutland >> wrote: >> >> Hi, >> >> On Mon, Oct 28, 2013 at 06:24:22AM +, Shirish S wrote: >> > This patch adds dt support to hdmiphy config settings >> > as it is board specific and depends on the signal pattern >> > of board. >> > >> > Signed-off-by: Shirish S >> > --- >> > .../devicetree/bindings/video/exynos_hdmi.txt | 29 >> > arch/arm/boot/dts/exynos5250-arndale.dts |6 +- >> > drivers/gpu/drm/exynos/exynos_hdmi.c | 70 >> ++-- >> > 3 files changed, 98 insertions(+), 7 deletions(-) >> > >> > diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/ >> Documentation/devicetree/bindings/video/exynos_hdmi.txt >> > index 323983b..770f92d 100644 >> > --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> > +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt >> > @@ -13,6 +13,27 @@ Required properties: >> > b) pin number within the gpio controller. >> > c) optional flags and pull up/down. >> > >> > +- hdmiphy-confs: following information about the hdmiphy conf >> settings. >> >> Judging by the other patches, this is a node, not a property. >> >> >> Yes its a node. > > My point was that the documentation should reflect this. > Its property and not a node, i had misunderstood the concepts. >> >> > +a) "nr-confs" specifies the number of pixel clocks supported. >> >> Why is this needed? Someone will get it wrong eventually and it can be >> figured >> out currently by counting the child nodes, testing if they have the >> appropriate >> properties. >> >> >> Actually i need to get the array size also from dt, hence this is approach i >> have taken > > While this approach works now for perfect DTs, as I pointed out it is encoding > redundant information and could be broken by future changes. Please fix this. > Hope you have had a look at my next patch set (v4), this property is now more or less optional, i mean if the user enters wrong number of configs it shall not be considered and driver shall use the predefined table provided in the driver. >> >> > + b) "confX: confX" specifies the phy configuration settings, >> >> This is confusing. What is X? >> >> >> I am trying to generalize, here X means any numerical, and the programmer >> needs >> to >> make sure conf0:conf0, wherein X is 0.I shall provide the values permitted >> for >> X in my next patch set. > > Please be explicit with your definitions. Experience shows that people will > get > this wrong. > Is the way i have documented in patch set v4 still wrong, or its clear? >> >> The label is irrelevant -- none of this patch looks for phandles pointing >> at >> configurations, nor is the precise name of the label important. >> >> This is a node, not a property. >> >> >> Ideally every conf a combination of pixel clock and new >> values for data and clock level. > > This answers neither of my concerns. > The fact that its a property and not a node,and contains pairs of pixel clock and config values should answer your concerns. Please note: in this case(exynos5250) the config values seem to same for all the pixel clocks, however in the next chipset (exynos5420) the values vary across pixel clocks, that is the reason why i need to keep these config values attached to pixel clocks. >> >> > + "clock-frequency" specifies the pixel clock >> >> Is this a frequency to configure the pixel clock with, or the >> pre-determined >> frequency of a clock that we will select? >> >> >> No, as the explanation suggests its the pixel clock itself. > > That doesn't answer my question. Is this the frequency that the pixel clock is > fixed at in hardware, or is this a value to configure the pixel clock with? > This the frequency that the pixel clock is fi
[PATCH 0/3] Add dt support for exynos hdmiphy settings
Ok, i shall rebase. On Mon, Oct 28, 2013 at 7:32 PM, Inki Dae wrote: > Hi Shirish, > > I have merged the re-factoring patch set from Sean Paul to exynos-drm-next. > Can you re-base your patch set at top of exynos-drm-next? > > Thanks, > Inki Dae > > > -Original Message- > > From: Shirish S [mailto:s.shirish at samsung.com] > > Sent: Monday, October 28, 2013 7:39 PM > > To: dri-devel at lists.freedesktop.org; inki.dae at samsung.com; > > devicetree at vger.kernel.org > > Cc: seanpaul at chromium.org; sw0312.kim at samsung.com; mark.rutland at > > arm.com; > > shirish at chromium.org; Shirish S > > Subject: [PATCH 0/3] Add dt support for exynos hdmiphy settings > > > > For various revisions of a chipset if the signal pattern is changed for > > every > > revision, then the phy setting need to be updated correspondingly by > > measuring > > the signal. > > For getting correct signals the clock level and data de-emphasis > > levels needs to be adjusted. > > Since only these 2 values matter,we can move the same to dt, > > wherein we can have different dt files for every revision. > > > > This is an initial patchset towards achieving the same > > for exynos 5250 and can be later extended to future chipsets. > > > > V2: replaced moving of entire phy config structure with only > > required and justifiable conf registers. > > > > V3: Incorporated Mark Rutland's comments. > > > > Shirish S (3): > > ARM: dts: smdk5250: Add hdmi phy settings > > ARM: dts: arndale: Add hdmi phy settings > > drm: exynos: hdmi: Add dt support for hdmiphy settings > > > > .../devicetree/bindings/video/exynos_hdmi.txt | 32 + > > arch/arm/boot/dts/exynos5250-arndale.dts | 68 > ++ > > arch/arm/boot/dts/exynos5250-smdk5250.dts | 68 > ++ > > drivers/gpu/drm/exynos/exynos_hdmi.c | 76 > ++- > > - > > 4 files changed, 240 insertions(+), 4 deletions(-) > > > > -- > > 1.7.9.5 > > -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20131029/a8cea800/attachment-0001.html>
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 32 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 76 ++--
2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..c3b546a 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,30 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
+a) "nr-configs" specifies the number of pixel clocks supported.
+ b) "config: config" specifies the phy configuration settings,
+ wher 'N' denotes the number of iteration.
+ "pixel-clock" specifies the pixel clock
+ "conifig-de-emphasis-level" specifies the 8 bit configuration
+ of Data De-emphasis levels,below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ 0x145D0040 [3:0] permitted values:
+ means 760 mVdiff && means 1400 mVdiff
+ 0x145D0040 [7:4] permitted values:
+ 0dB
+ 0001-0.25dB
+ 0010-0.7dB
+ 0011-1.15dB
+ -7.45dB
+ "config-clock-level" specifies the 8 bit configuration for
+ the corresponding clock level, for example if 0x145D005C
+ is the address of clock level register.
+ 0x145D005C [1:0] permitted values:
+ 00 means 0 mVdiff && 11 means 60 mVdiff
+ 0x145D005C [7:3] permitted values:
+ 0 is 790 mVdiff
+ 1 is 1430 mVdiff
Example:
hdmi {
@@ -20,4 +44,12 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-configs {
+ nr-configs = <1>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..7b94a5d 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -778,8 +781,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1366,7 +1369,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
hdmiphy_data = hdmiphy_v13_configs[i].conf;
else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata->confs[i].conf;
memcpy(buffer, hdmiphy_data, 32);
ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
@@ -1858,6 +1861,62 @@ void hdmi_attach_hdmiphy_client(struct i2c_client
*hdmiphy)
hdmi_hdmiphy = hdmiphy;
}
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+ struct device *dev = >dev;
+ struct device_node *dev_np = dev->of_node;
+ struct device_n
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 68 ++
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..3b33704 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -427,6 +427,74 @@
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
+ hdmiphy-configs {
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
mmc_reg: voltage-regulator {
--
1.7.9.5
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 68 +
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..0795e23 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,74 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-configs {
+ nr-configs = <13>;
+ config0: config0 {
+ pixel-clock = <2520>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config1: config1 {
+ pixel-clock = <2700>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config2: config2 {
+ pixel-clock = <27027000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config3: config3 {
+ pixel-clock = <3600>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config4: config4 {
+ pixel-clock = <4000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config5: config5 {
+ pixel-clock = <6500>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config6: config6 {
+ pixel-clock = <74176000>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config7: config7 {
+ pixel-clock = <7425>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config8: config8 {
+ pixel-clock = <8350>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config9: config9 {
+ pixel-clock = <10650>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config10: config10 {
+ pixel-clock = <10800>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config11: config11 {
+ pixel-clock = <14625>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ config12: config12 {
+ pixel-clock = <14850>;
+ config-de-emphasis-level = /bits/ 8 <0x26>;
+ config-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 32 + arch/arm/boot/dts/exynos5250-arndale.dts | 68 ++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 68 ++ drivers/gpu/drm/exynos/exynos_hdmi.c | 76 ++-- 4 files changed, 240 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
Hi Mark, Firstly thanks for reviewing. On Mon, Oct 28, 2013 at 12:20 PM, Mark Rutland wrote: > Hi, > > On Mon, Oct 28, 2013 at 06:24:22AM +, Shirish S wrote: > > This patch adds dt support to hdmiphy config settings > > as it is board specific and depends on the signal pattern > > of board. > > > > Signed-off-by: Shirish S > > --- > > .../devicetree/bindings/video/exynos_hdmi.txt | 29 > > arch/arm/boot/dts/exynos5250-arndale.dts |6 +- > > drivers/gpu/drm/exynos/exynos_hdmi.c | 70 > ++-- > > 3 files changed, 98 insertions(+), 7 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt > b/Documentation/devicetree/bindings/video/exynos_hdmi.txt > > index 323983b..770f92d 100644 > > --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt > > +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt > > @@ -13,6 +13,27 @@ Required properties: > > b) pin number within the gpio controller. > > c) optional flags and pull up/down. > > > > +- hdmiphy-confs: following information about the hdmiphy conf settings. > > Judging by the other patches, this is a node, not a property. > > Yes its a node. > > +a) "nr-confs" specifies the number of pixel clocks supported. > > Why is this needed? Someone will get it wrong eventually and it can be > figured > out currently by counting the child nodes, testing if they have the > appropriate > properties. > > Actually i need to get the array size also from dt, hence this is approach i have taken > > + b) "confX: confX" specifies the phy configuration settings, > > This is confusing. What is X? > > I am trying to generalize, here X means any numerical, and the programmer needs to make sure conf0:conf0, wherein X is 0.I shall provide the values permitted for X in my next patch set. > The label is irrelevant -- none of this patch looks for phandles pointing > at > configurations, nor is the precise name of the label important. > > This is a node, not a property. > > Ideally every conf a combination of pixel clock and new values for data and clock level. > > + "clock-frequency" specifies the pixel clock > > Is this a frequency to configure the pixel clock with, or the > pre-determined > frequency of a clock that we will select? > > No, as the explanation suggests its the pixel clock itself. > > + "con-de-emphasis-level" specifies the configuration > > + of Data De-emphasis levels. > > Please explain _why_ we need this configuration. > > Our chipset to undergo HDMI compliance test and noticed that the HDMI Compliance Test id 7-10 was failing for eye diagram test. Hence on further analysis, it was found that altering the data de-emphasis levels and clock level are required to pass the test.And also these values may vary for variuos board revisons, this is the purpose of this whole patch set. > Also, "con" is not a good abbreviation of "configuration", "config" would > be > preferable. > > Agreed, will update the same in next patch set. > > + 0x145D0040h[3:0] permitted values: > > + means 760 mVdiff && means 1400 > mVdiff > > I assume the 'h' suffix is a redundant description that the constant is > hexadecimal. Please drop it. > > Agreed, will update the same in next patch set. > What is 0x145D0040? The address of the register, or its value? > > Its the address of the hdmiphy register for data level configuration. > The description is confusing, 0x145D0040h[3:0] is always 0[3:0]. > > This description is extracted from the one specified in manual, in my first patch set the reviewers had asked me to provide the explaination for every bit, which i have provided. > Why does this need to be the exact value programmed into the register > rather > than separate values the driver can compose? > > As mentioned above the value is must for clearing the test 7-10, and also its derived by a trial and error method with the HDMI analyser. > > + 0x145D0040h[7:4] permitted values: > > + 000 0dB > > + 0001-0.25dB > > + 0010-0.7dB > > + 0011-1.15dB > > + -7.45dB > > Again, this seems very odd. Why this format? > > This binary translation of what the bits actually mean.In the final result it was
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 29
arch/arm/boot/dts/exynos5250-arndale.dts |6 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 70 ++--
3 files changed, 98 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..770f92d 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,27 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-confs: following information about the hdmiphy conf settings.
+a) "nr-confs" specifies the number of pixel clocks supported.
+ b) "confX: confX" specifies the phy configuration settings,
+ "clock-frequency" specifies the pixel clock
+ "con-de-emphasis-level" specifies the configuration
+ of Data De-emphasis levels.
+ 0x145D0040h[3:0] permitted values:
+ means 760 mVdiff && means 1400 mVdiff
+ 0x145D0040h[7:4] permitted values:
+ 000 0dB
+ 0001-0.25dB
+ 0010-0.7dB
+ 0011-1.15dB
+ -7.45dB
+ "con-clock-level" specifies the configuration for
+ the corresponding clock level.
+ 0x145D005Ch [1:0] permitted values:
+ 00 means 0 mVdiff && 11 means 60 mVdiff
+ 0x145D005Ch [7:3] permitted values:
+ 0 is 790 mVdiff
+ 1 is 1430 mVdiff
Example:
hdmi {
@@ -20,4 +41,12 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-confs {
+ nr-confs = <1>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ }
};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index c23f16b..436b75a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,9 @@
hdmi {
hpd-gpio = < 7 2>;
+ vdd_osc-supply = <_reg>;
+ vdd_pll-supply = <_reg>;
+ vdd-supply = <_reg>;
hdmiphy-confs {
nr-confs = <13>;
conf0: conf0 {
@@ -492,9 +495,6 @@
conf-clock-level = /bits/ 8 < 0x66>;
};
};
- vdd_osc-supply = <_reg>;
- vdd_pll-supply = <_reg>;
- vdd-supply = <_reg>;
};
mmc_reg: voltage-regulator {
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..3125e67 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -778,8 +781,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata,
u32 pixel_clock)
confs = hdmiphy_v13_configs;
count = ARRAY_SIZE(hdmiphy_v13_configs);
} else if (hdata->type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
+ confs = hdata->confs;
+ count = hdata->nr_confs;
} else
return -EINVAL;
@@ -1366,7 +1369,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
if (hdata->type == HDMI_TYPE13)
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 68 ++
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..c23f16b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,74 @@
hdmi {
hpd-gpio = < 7 2>;
+ hdmiphy-confs {
+ nr-confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf8: conf8 {
+ clock-frequency = <8350>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf9: conf9 {
+ clock-frequency = <10650>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf10: conf10 {
+ clock-frequency = <10800>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf11: conf11 {
+ clock-frequency = <14625>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf12: conf12 {
+ clock-frequency = <14850>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
vdd_osc-supply = <_reg>;
vdd_pll-supply = <_reg>;
vdd-supply = <_reg>;
--
1.7.9.5
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 68 +
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..d6d0801 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,74 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-confs {
+ nr-confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf8: conf8 {
+ clock-frequency = <8350>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf9: conf9 {
+ clock-frequency = <10650>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf10: conf10 {
+ clock-frequency = <10800>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf11: conf11 {
+ clock-frequency = <14625>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ conf12: conf12 {
+ clock-frequency = <14850>;
+ conf-de-emphasis-level = /bits/ 8 <0x26>;
+ conf-clock-level = /bits/ 8 < 0x66>;
+ };
+ };
};
codec at 1100 {
--
1.7.9.5
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 29 arch/arm/boot/dts/exynos5250-arndale.dts | 68 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 68 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 70 ++-- 4 files changed, 231 insertions(+), 4 deletions(-) -- 1.7.9.5
[PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
Hi,
I have uploaded patch set 2, with only required registers being moved to dt
file.
Thanks,
Shirish S
On Thu, Oct 3, 2013 at 7:58 AM, Shirish S wrote:
> Hi,
> First of all sorry for the late response,
>
>
> On Tue, Oct 1, 2013 at 10:09 AM, Inki Dae wrote:
>
>>
>>
>> > -Original Message-
>> > From: Sylwester Nawrocki [mailto:sylvester.nawrocki at gmail.com]
>> > Sent: Monday, September 30, 2013 7:09 AM
>> > To: Inki Dae
>> > Cc: Rahul Sharma; devicetree at vger.kernel.org; linux-samsung-soc;
>> > sw0312.kim; sunil joshi; dri-devel; kgene.kim; Shirish S; Sylwester
>> > Nawrocki; Rahul Sharma; Stephen Warren; Mark Rutland; Kumar Gala; Pawel
>> > Moll; Rob Herring; Sean Paul
>> > Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
>> hdmiphy
>> > driver
>> >
>> > On 09/28/2013 06:10 PM, Inki Dae wrote:
>> > >> Any opinion from Device-Tree folks?
>> > >>
>> > >> IMO, we should have same consensus on Shirish patches before
>> proceeding.
>> > >
>> > > Rahul, it seems that DT people have no interest in this issue. So
>> let's
>> > > have a consensus about this issue internally.
>> > >
>> > > To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
>> > > How about keeping hdmiphy config data in each board dts file?
>> >
>> > Please don't use HTML and quote only relevant part of e-mails. Otherwise
>> > there are good chances your messages end up in people's spam box.
>> >
>>
>> Ah, I missed checking text mode. Sorry about this. :)
>>
>>
>>
>> > It often helps to Cc a DT binding maintainer directly.
>> >
>>
>> Good idea.
>>
>> > Then, you consider moving the HDMI phy configuration to the device tree.
>> > As Sean suggested in this thread:
>> >
>>
>> Right.
>>
>> > ">> +static struct hdmiphy_config hdmiphy_4210_configs[] = {
>> > >> + {
>> > >> + .pixel_clock = 2700,
>> > >> + .conf = {
>> > >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
>> 0x40,
>> > >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
>> 0x87,
>> > >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
>> 0xE0,
>> > >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
>> 0x00,
>> > >> + },
>> > >> + },
>> > [trimmed couple more entries]
>> > >> +};
>> > >>
>> > > Are you aware of the effort to move these to dt? Since these are
>> > > board-specific values, it seems incorrect to apply them universally.
>> > > Shirish has uploaded a patch to the chromium review site to push these
>> > > into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
>> > > you can work that into your patch set?"
>> >
>> > The configuration data is 64 bytes of the register values IIUC. Would it
>> > be
>> > possible to figure out exact meaning of each byte ? Do all of these
>> bytes
>>
>> Right, but the user manual doesn't describe that enough so we might need
>> to
>> inquire for what it means to design team.
>>
>> > need to be changed per board ? Perhaps we can have per SoC static tables
>> > in
>> > the PHY driver and be overwriting only some of the bytes with values
>> read
>> > from device tree ?
>> >
>> > AFAIR firmware-like binary blobs (register address/value pairs) are not
>> > supposed to be stored in DT.
>> >
>> > If there is no detailed documentation for theese PHY configuration
>> tables
>> > I guess there is no choice but to put these raw 64 bytes in DT.
>> Presumably
>> > this should be a an required property defined only by board dts, since
>> > those
>> > values are PCB design dependent.
>> >
>> > However, if not all boards need tweaking this configuration data, then
>> it
>> > could make sense to define recommended per-SoC tables in the driver and
>> > overwrite from DT only if it is specified there for a specific board.
>> > If we can come up with universal configuration for a SoC and selected
>> > pixel
>> > clock frequency then it could likely be better to store that in the
>> driver
>> > rather than in DT.
>&
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
Hi,
First of all sorry for the late response,
On Tue, Oct 1, 2013 at 10:09 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Sylwester Nawrocki [mailto:sylvester.nawro...@gmail.com]
Sent: Monday, September 30, 2013 7:09 AM
To: Inki Dae
Cc: Rahul Sharma; devicet...@vger.kernel.org; linux-samsung-soc;
sw0312.kim; sunil joshi; dri-devel; kgene.kim; Shirish S; Sylwester
Nawrocki; Rahul Sharma; Stephen Warren; Mark Rutland; Kumar Gala; Pawel
Moll; Rob Herring; Sean Paul
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 09/28/2013 06:10 PM, Inki Dae wrote:
Any opinion from Device-Tree folks?
IMO, we should have same consensus on Shirish patches before
proceeding.
Rahul, it seems that DT people have no interest in this issue. So let's
have a consensus about this issue internally.
To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
How about keeping hdmiphy config data in each board dts file?
Please don't use HTML and quote only relevant part of e-mails. Otherwise
there are good chances your messages end up in people's spam box.
Ah, I missed checking text mode. Sorry about this. :)
It often helps to Cc a DT binding maintainer directly.
Good idea.
Then, you consider moving the HDMI phy configuration to the device tree.
As Sean suggested in this thread:
Right.
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
[trimmed couple more entries]
+};
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them universally.
Shirish has uploaded a patch to the chromium review site to push these
into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
you can work that into your patch set?
The configuration data is 64 bytes of the register values IIUC. Would it
be
possible to figure out exact meaning of each byte ? Do all of these bytes
Right, but the user manual doesn't describe that enough so we might need to
inquire for what it means to design team.
need to be changed per board ? Perhaps we can have per SoC static tables
in
the PHY driver and be overwriting only some of the bytes with values read
from device tree ?
AFAIR firmware-like binary blobs (register address/value pairs) are not
supposed to be stored in DT.
If there is no detailed documentation for theese PHY configuration tables
I guess there is no choice but to put these raw 64 bytes in DT.
Presumably
this should be a an required property defined only by board dts, since
those
values are PCB design dependent.
However, if not all boards need tweaking this configuration data, then it
could make sense to define recommended per-SoC tables in the driver and
overwrite from DT only if it is specified there for a specific board.
If we can come up with universal configuration for a SoC and selected
pixel
clock frequency then it could likely be better to store that in the
driver
rather than in DT.
Thanks you your opinion. However, we need to make sure how we take care of
the PHY configuration values. So I will have two steps to merge this pages
set.
To Rahul,
Could you post only your patch set regardless of Shirish's patch? I will
merge your patch set first because as is, Exynos drm hdmi driver is broken.
And, we need more discussions about Shirish patch. So I will not merge this
patch until we have a consensus about it.
To Shirish,
For your patch, it seems that you need to make sure to figure out exact
meaning of each byte of the PHY configuration values first. Maybe you need
to inquire for that to hardware or design team. And please separate the
values into common and specific parts if needed.
Agreed, I shall request our hardware team to provide description about the
phy values, and will update the patch, once i receive the same.
Thanks,
Inki Dae
--
Thanks,
Sylwester
Thanks,
Shirish S
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 18 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++-
2 files changed, 80 insertions(+), 129 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy-confs: following information about the hdmiphy conf settings.
+a) "nr-confs" specifies the number of pixel clocks supported.
+ b) "confX: confX" specifies the phy configuration settings,
+ "clock-frequency" specifies the pixel clock
+ "conf" specifies the setting for the corresponding pixel clock
Example:
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy-confs {
+ nr-confs = <1>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
};
+struct hdmiphy_config {
+ int pixel_clock;
+ u8 conf[32];
+};
+
struct hdmi_context {
struct device *dev;
struct drm_device *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
= {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
- {
- .pixel_clock = 2520,
- .conf = {
- 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
- 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
- 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
- },
- },
- {
- .pixel_clock = 3600,
- .conf = {
- 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 4000,
- .conf = {
- 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80,
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
hdmi {
hpd-gpio = < 7 2>;
+ hdmiphy-confs {
+ nr-confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy-confs {
+ nr-confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = gpx3 7 0;
+ hdmiphy-confs {
+ nr-confs = 13;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf1: conf1 {
+ clock-frequency = 2700;
+ conf = /bits/ 8
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf2: conf2 {
+ clock-frequency = 27027000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf3: conf3 {
+ clock-frequency = 3600;
+ conf = /bits/ 8
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf4: conf4 {
+ clock-frequency = 4000;
+ conf = /bits/ 8
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf5: conf5 {
+ clock-frequency = 6500;
+ conf = /bits/ 8
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf6: conf6 {
+ clock-frequency = 74176000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf7: conf7 {
+ clock-frequency = 7425;
+ conf = /bits/ 8
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf8: conf8
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
hdmi {
hpd-gpio = gpx3 7 2;
+ hdmiphy-confs {
+ nr-confs = 13;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf1: conf1 {
+ clock-frequency = 2700;
+ conf = /bits/ 8
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf2: conf2 {
+ clock-frequency = 27027000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf3: conf3 {
+ clock-frequency = 3600;
+ conf = /bits/ 8
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf4: conf4 {
+ clock-frequency = 4000;
+ conf = /bits/ 8
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf5: conf5 {
+ clock-frequency = 6500;
+ conf = /bits/ 8
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf6: conf6 {
+ clock-frequency = 74176000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf7: conf7 {
+ clock-frequency = 7425;
+ conf = /bits/ 8
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf8: conf8
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S s.shir...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt | 18 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++-
2 files changed, 80 insertions(+), 129 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy-confs: following information about the hdmiphy conf settings.
+a) nr-confs specifies the number of pixel clocks supported.
+ b) confX: confX specifies the phy configuration settings,
+ clock-frequency specifies the pixel clock
+ conf specifies the setting for the corresponding pixel clock
Example:
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ hdmiphy-confs {
+ nr-confs = 1;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
};
+struct hdmiphy_config {
+ int pixel_clock;
+ u8 conf[32];
+};
+
struct hdmi_context {
struct device *dev;
struct drm_device *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
= {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
- {
- .pixel_clock = 2520,
- .conf = {
- 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
- 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
- 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
- },
- },
- {
- .pixel_clock = 3600,
- .conf = {
- 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 4000,
- .conf = {
- 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 18 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++-
2 files changed, 80 insertions(+), 129 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy_confs: following information about the hdmiphy conf settings.
+a) "nr_confs" specifies the number of pixel clocks supported.
+ b) "confX: confX" specifies the phy configuration settings,
+ "clock-frequency" specifies the pixel clock
+ "conf" specifies the setting for the corresponding pixel clock
Example:
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy_confs {
+ nr_confs = <1>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
};
+struct hdmiphy_config {
+ int pixel_clock;
+ u8 conf[32];
+};
+
struct hdmi_context {
struct device *dev;
struct drm_device *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
= {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
- {
- .pixel_clock = 2520,
- .conf = {
- 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
- 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
- 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
- },
- },
- {
- .pixel_clock = 3600,
- .conf = {
- 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 4000,
- .conf = {
- 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80,
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
hdmi {
hpd-gpio = < 7 2>;
+ hdmiphy_confs {
+ nr_confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy_confs {
+ nr_confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S
---
.../devicetree/bindings/video/exynos_hdmi.txt | 18 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++-
2 files changed, 80 insertions(+), 129 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy_confs: following information about the hdmiphy conf settings.
+a) "nr_confs" specifies the number of pixel clocks supported.
+ b) "confX: confX" specifies the phy configuration settings,
+ "clock-frequency" specifies the pixel clock
+ "conf" specifies the setting for the corresponding pixel clock
Example:
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = <0x1453 0x10>;
interrupts = <0 95 0>;
hpd-gpio = < 7 1>;
+ hdmiphy_confs {
+ nr_confs = <1>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
};
+struct hdmiphy_config {
+ int pixel_clock;
+ u8 conf[32];
+};
+
struct hdmi_context {
struct device *dev;
struct drm_device *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
= {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
- {
- .pixel_clock = 2520,
- .conf = {
- 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
- 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
- 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
- },
- },
- {
- .pixel_clock = 3600,
- .conf = {
- 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 4000,
- .conf = {
- 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80,
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
hdmi {
hpd-gpio = < 7 2>;
+ hdmiphy_confs {
+ nr_confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = < 7 0>;
+ hdmiphy_confs {
+ nr_confs = <13>;
+ conf0: conf0 {
+ clock-frequency = <2520>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf1: conf1 {
+ clock-frequency = <2700>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf2: conf2 {
+ clock-frequency = <27027000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ >;
+ };
+ conf3: conf3 {
+ clock-frequency = <3600>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf4: conf4 {
+ clock-frequency = <4000>;
+ conf = /bits/ 8 <
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf5: conf5 {
+ clock-frequency = <6500>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf6: conf6 {
+ clock-frequency = <74176000>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ >;
+ };
+ conf7: conf7 {
+ clock-frequency = <7425>;
+ conf = /bits/ 8 <
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x0
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4
[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = gpx3 7 0;
+ hdmiphy_confs {
+ nr_confs = 13;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf1: conf1 {
+ clock-frequency = 2700;
+ conf = /bits/ 8
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf2: conf2 {
+ clock-frequency = 27027000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf3: conf3 {
+ clock-frequency = 3600;
+ conf = /bits/ 8
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf4: conf4 {
+ clock-frequency = 4000;
+ conf = /bits/ 8
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf5: conf5 {
+ clock-frequency = 6500;
+ conf = /bits/ 8
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf6: conf6 {
+ clock-frequency = 74176000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf7: conf7 {
+ clock-frequency = 7425;
+ conf = /bits/ 8
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf8: conf8
