[PATCH] rnndb: Add Pixel Extension registers

[Stephane Viau]

Pixel Extension are extra pixels fed to the QSEED2 scalar; this
information is needed to produce an output image. These values
depend on various parameters, such as scalar type, initial phase,
phase step, etc.

Pixel extension values used to be handled and calculated by
hardware; however, software could also overwrite those values for
optimization.

In some hardware (eg: MDP5 v1.7), software *must* program those
values since they are not handled in hardware.

Change-Id: I4900165e770f8da702a4f938044616daf5aa81af
Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml   | 24 
 rnndb/mdp/mdp_common.xml |  7 +++
 2 files changed, 31 insertions(+)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index df02377..c829737 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -390,6 +390,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



+   



@@ -406,6 +407,29 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



+   
+   
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   



diff --git a/rnndb/mdp/mdp_common.xml b/rnndb/mdp/mdp_common.xml
index 5e8e421..226596a 100644
--- a/rnndb/mdp/mdp_common.xml
+++ b/rnndb/mdp/mdp_common.xml
@@ -39,6 +39,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

+
+   
+ 
+   
+
+
+
 
bits per component (non-alpha channel)
 
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 10/10] drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996)

[Stephane Viau]

This change adds the basic MDP5 support for MSM8996.

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/mdp.txt |  2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c   | 95 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h   |  9 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   | 18 +++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |  2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 18 +++--
 drivers/gpu/drm/msm/mdp/mdp_kms.h |  5 ++
 7 files changed, 135 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/msm/mdp.txt 
b/Documentation/devicetree/bindings/drm/msm/mdp.txt
index 99ba764..0114a87 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdp.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdp.txt
@@ -22,6 +22,7 @@ Optional properties:
   * "iommu_clk"
   * "mmagic_clk"
 - mmagic-supply: phandle for mmagic GDSC regulator used during IOMMU 
translation
+- iommus: phandle for IOMMU v2 device

 Example:

@@ -48,5 +49,6 @@ Example:
< TV_SRC>,
< HDMI_TV_CLK>,
< MDP_TV_CLK>;
+   iommus = <_smmu 0>;
};
 };
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index a1e26f2..bb1225a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -27,6 +27,8 @@ const struct mdp5_cfg_hw msm8x74v1_config = {
.mdp = {
.count = 1,
.base = { 0x00100 },
+   .caps = MDP_CAP_SMP |
+   0,
},
.smp = {
.mmb_count = 22,
@@ -96,6 +98,8 @@ const struct mdp5_cfg_hw msm8x74v2_config = {
.mdp = {
.count = 1,
.base = { 0x00100 },
+   .caps = MDP_CAP_SMP |
+   0,
},
.smp = {
.mmb_count = 22,
@@ -165,6 +169,8 @@ const struct mdp5_cfg_hw apq8084_config = {
.mdp = {
.count = 1,
.base = { 0x00100 },
+   .caps = MDP_CAP_SMP |
+   0,
},
.smp = {
.mmb_count = 44,
@@ -242,6 +248,8 @@ const struct mdp5_cfg_hw msm8x16_config = {
.mdp = {
.count = 1,
.base = { 0x01000 },
+   .caps = MDP_CAP_SMP |
+   0,
},
.smp = {
.mmb_count = 8,
@@ -301,6 +309,8 @@ const struct mdp5_cfg_hw msm8x94_config = {
.mdp = {
.count = 1,
.base = { 0x01000 },
+   .caps = MDP_CAP_SMP |
+   0,
},
.smp = {
.mmb_count = 44,
@@ -370,7 +380,89 @@ const struct mdp5_cfg_hw msm8x94_config = {
[3] = INTF_HDMI,
},
},
-   .max_clk = 32000,
+   .max_clk = 4,
+};
+
+const struct mdp5_cfg_hw msm8x96_config = {
+   .name = "msm8x96",
+   .mdp = {
+   .count = 1,
+   .base = { 0x01000 },
+   .caps = MDP_CAP_DSC |
+   MDP_CAP_CDM |
+   0,
+   },
+   .ctl = {
+   .count = 5,
+   .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
+   .flush_hw_mask = 0xf4ff,
+   },
+   .pipe_vig = {
+   .count = 4,
+   .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
+   .caps = MDP_PIPE_CAP_HFLIP  |
+   MDP_PIPE_CAP_VFLIP  |
+   MDP_PIPE_CAP_SCALE  |
+   MDP_PIPE_CAP_CSC|
+   MDP_PIPE_CAP_DECIMATION |
+   MDP_PIPE_CAP_SW_PIX_EXT |
+   0,
+   },
+   .pipe_rgb = {
+   .count = 4,
+   .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
+   .caps = MDP_PIPE_CAP_HFLIP  |
+   MDP_PIPE_CAP_VFLIP  |
+   MDP_PIPE_CAP_SCALE  |
+   MDP_PIPE_CAP_DECIMATION |
+   MDP_PIPE_CAP_SW_PIX_EXT |
+   0,
+   },
+   .pipe_dma = {
+   .count = 2,
+   .base = { 0x25000, 0x27000 },
+   .caps = MDP_PIPE_CAP_HFLIP  |
+   MDP_PIPE_CAP_VFLIP  |
+   MDP_PIPE_CAP_SW_PIX_EXT |
+   0,
+   },
+   .lm = {
+   .count = 6,
+   .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 
},
+   .nb_stages = 8,
+   .max_width = 2560,
+   .max_height = 0x,
+   },
+   .dspp = {
+   .count = 2,
+   .base = { 0x55000, 0x57000 },
+   },
+   .ad

[PATCH 09/10] drm/msm/mdp: Add Software Pixel Extension support

[Stephane Viau]

In order to produce an image, the scalar needs to be fed extra
pixels. These top/bottom/left/right values depend on a various of
factors, including resolution, scaling type, phase step and
initial phase.

Pixel Extension are programmed by hardware in most targets - and
can be overwritten by software. For some targets (e.g.: msm8996),
software *must* program those registers.

In order to ease this computation, let's always use bilinear
filters, which are easier to program from kernel. Eventually,
all of these values will come down from user space for better
quality.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 158 --
 drivers/gpu/drm/msm/mdp/mdp_kms.h |   1 +
 2 files changed, 128 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index c294033..c86f49f 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -542,40 +542,120 @@ static int calc_scaley_steps(struct drm_plane *plane,
return 0;
 }

-static uint32_t get_scale_config(enum mdp_chroma_samp_type chroma_sample,
-   uint32_t src, uint32_t dest, bool hor)
+static uint32_t get_scale_config(const struct mdp_format *format,
+   uint32_t src, uint32_t dst, bool horz)
 {
-   uint32_t y_filter =   (src <= dest) ? SCALE_FILTER_CA  : 
SCALE_FILTER_PCMN;
-   uint32_t y_a_filter = (src <= dest) ? SCALE_FILTER_BIL : 
SCALE_FILTER_PCMN;
-   uint32_t uv_filter = ((src / 2) <= dest) ? /* 2x upsample */
-   SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
-   uint32_t value = 0;
-
-   if (chroma_sample == CHROMA_420 || chroma_sample == CHROMA_H2V1) {
-   if (hor)
-   value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter);
-   else
-   value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter);
-   } else if (src != dest) {
-   if (hor)
-   value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_a_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter);
-   else
-   value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_a_filter) |
-   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter);
+   bool scaling = format->is_yuv ? true : (src != dst);
+   uint32_t sub, pix_fmt = format->base.pixel_format;
+   uint32_t ya_filter, uv_filter;
+   bool yuv = format->is_yuv;
+
+   if (!scaling)
+   return 0;
+
+   if (yuv) {
+   sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
+drm_format_vert_chroma_subsampling(pix_fmt);
+   uv_filter = ((src / sub) <= dst) ?
+  SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
}
+   ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
+
+   if (horz)
+   return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
+   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
+   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
+   COND(yuv, 
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
+   else
+   return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
+   MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
+   MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
+   COND(yuv, 
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
+}
+
+static void calc_pixel_ext(const struct mdp_format *format,
+   uint32_t src, uint32_t dst, uint32_t phase_step[2],
+   int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
+   bool horz)
+{
+   bool scaling = format->is_yuv ? true : (src != dst);
+   int i;
+
+   /*
+* Note:
+* We assume here that:
+* 1. PCMN filter is used for downscale
+* 2. bilinear filter is used for upscale
+* 3. we are in a single pipe configuration
+*/

-   return value;
+   

[PATCH 08/10] drm/msm/mdp5: Use the newly introduced enum mdp_component_type

[Stephane Viau]

When calculating phase steps, let's use the same enum
mdp_component_type in order to ease the readability; 0/1 indexes
are a bit confusing and we now have explicit values to index
this type of arrays.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 07fb62f..c294033 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -494,7 +494,7 @@ static int calc_phase_step(uint32_t src, uint32_t dst, 
uint32_t *out_phase)

 static int calc_scalex_steps(struct drm_plane *plane,
uint32_t pixel_format, uint32_t src, uint32_t dest,
-   uint32_t phasex_steps[2])
+   uint32_t phasex_steps[COMP_MAX])
 {
struct mdp5_kms *mdp5_kms = get_kms(plane);
struct device *dev = mdp5_kms->dev->dev;
@@ -510,15 +510,16 @@ static int calc_scalex_steps(struct drm_plane *plane,

hsub = drm_format_horz_chroma_subsampling(pixel_format);

-   phasex_steps[0] = phasex_step;
-   phasex_steps[1] = phasex_step / hsub;
+   phasex_steps[COMP_0]   = phasex_step;
+   phasex_steps[COMP_3]   = phasex_step;
+   phasex_steps[COMP_1_2] = phasex_step / hsub;

return 0;
 }

 static int calc_scaley_steps(struct drm_plane *plane,
uint32_t pixel_format, uint32_t src, uint32_t dest,
-   uint32_t phasey_steps[2])
+   uint32_t phasey_steps[COMP_MAX])
 {
struct mdp5_kms *mdp5_kms = get_kms(plane);
struct device *dev = mdp5_kms->dev->dev;
@@ -534,8 +535,9 @@ static int calc_scaley_steps(struct drm_plane *plane,

vsub = drm_format_vert_chroma_subsampling(pixel_format);

-   phasey_steps[0] = phasey_step;
-   phasey_steps[1] = phasey_step / vsub;
+   phasey_steps[COMP_0]   = phasey_step;
+   phasey_steps[COMP_3]   = phasey_step;
+   phasey_steps[COMP_1_2] = phasey_step / vsub;

return 0;
 }
@@ -587,8 +589,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
enum mdp5_pipe pipe = mdp5_plane->pipe;
const struct mdp_format *format;
uint32_t nplanes, config = 0;
-   /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */
-   uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,};
+   uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
uint32_t hdecm = 0, vdecm = 0;
uint32_t pix_format;
bool vflip, hflip;
@@ -696,13 +697,13 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,

if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) {
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
-   phasex_step[0]);
+   phasex_step[COMP_0]);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
-   phasey_step[0]);
+   phasey_step[COMP_0]);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
-   phasex_step[1]);
+   phasex_step[COMP_1_2]);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
-   phasey_step[1]);
+   phasey_step[COMP_1_2]);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
MDP5_PIPE_DECIMATION_VERT(vdecm) |
MDP5_PIPE_DECIMATION_HORZ(hdecm));
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 07/10] drm/msm/mdp: Update generated headers (Pixel Extension)

[Stephane Viau]

This change is the output of Envytools change:

"rnndb: Add Pixel Extension registers"

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h  | 82 +++-
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 11 -
 2 files changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index af9b932..bb4eae3 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,9 +8,9 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
36021 bytes, from 2015-07-31 21:25:50)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
37194 bytes, from 2015-07-31 21:28:36)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2015-04-30 16:26:30)
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2576 bytes, from 2015-07-31 21:25:50)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2849 bytes, from 2015-07-31 21:28:36)

 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -887,6 +887,7 @@ static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum 
mdp5_pipe_bwc val)
 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1
0x0004
 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE  0x0040
 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD  0x0080
+#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE  0x8000

 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { 
return 0x003c + __offset_PIPE(i0); }

@@ -924,6 +925,83 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t 
val)
return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & 
MDP5_PIPE_DECIMATION_HORZ__MASK;
 }

+static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
+{
+   switch (idx) {
+   case COMP_0: return 0x0100;
+   case COMP_1_2: return 0x0110;
+   case COMP_3: return 0x0120;
+   default: return INVALID_IDX(idx);
+   }
+}
+static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum 
mdp_component_type i1) { return 0x + __offset_PIPE(i0) + 
__offset_SW_PIX_EXT(i1); }
+
+static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum 
mdp_component_type i1) { return 0x + __offset_PIPE(i0) + 
__offset_SW_PIX_EXT(i1); }
+#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x00ff
+#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT0
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
+}
+#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0xff00
+#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT8
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
+}
+#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK
0x00ff
+#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT   16
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
+}
+#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK
0xff00
+#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT   24
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum 
mdp_component_type i1) { return 0x0004 + __offset_PIPE(i0) + 
__offset_SW_PIX_EXT(i1); }
+#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK  0x00ff
+#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
+}
+#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK  0xff00
+#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
+static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
+{
+   return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & 
MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
+}
+#d

[PATCH 06/10] drm/msm/hdmi: Add basic HDMI support for msm8996

[Stephane Viau]

The HDMI controller is new in MDP5 v1.7. As of now, this change
doesn't reflect the novelty and only adds the basics so the probe
gets triggered.

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/hdmi.txt |  3 +++
 drivers/gpu/drm/msm/hdmi/hdmi.c| 17 ++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt 
b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
index e926239..379ee2e 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -2,6 +2,7 @@ Qualcomm adreno/snapdragon hdmi output

 Required properties:
 - compatible: one of the following
+   * "qcom,hdmi-tx-8996"
* "qcom,hdmi-tx-8994"
* "qcom,hdmi-tx-8084"
* "qcom,hdmi-tx-8974"
@@ -21,6 +22,7 @@ Required properties:
 Optional properties:
 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
+- power-domains: reference to the power domain(s), if available.
 - pinctrl-names: the pin control state names; should contain "default"
 - pinctrl-0: the default pinctrl state (active)
 - pinctrl-1: the "sleep" pinctrl state
@@ -35,6 +37,7 @@ Example:
reg-names = "core_physical";
reg = <0x04a0 0x1000>;
interrupts = ;
+   power-domains = < MDSS_GDSC>;
clock-names =
"core_clk",
"master_iface_clk",
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 101b324..1f4a95e 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -328,6 +328,9 @@ fail:
.item ## _names = item ##_names_ ## entry, \
.item ## _cnt   = ARRAY_SIZE(item ## _names_ ## entry)

+static const char *pwr_reg_names_none[] = {};
+static const char *hpd_reg_names_none[] = {};
+
 static struct hdmi_platform_config hdmi_tx_8660_config = {
.phy_init = hdmi_phy_8x60_init,
 };
@@ -367,18 +370,26 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
.hpd_freq  = hpd_clk_freq_8x74,
 };

-static const char *hpd_reg_names_8x94[] = {};
-
 static struct hdmi_platform_config hdmi_tx_8994_config = {
.phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */
HDMI_CFG(pwr_reg, 8x74),
-   HDMI_CFG(hpd_reg, 8x94),
+   HDMI_CFG(hpd_reg, none),
+   HDMI_CFG(pwr_clk, 8x74),
+   HDMI_CFG(hpd_clk, 8x74),
+   .hpd_freq  = hpd_clk_freq_8x74,
+};
+
+static struct hdmi_platform_config hdmi_tx_8996_config = {
+   .phy_init = NULL,
+   HDMI_CFG(pwr_reg, none),
+   HDMI_CFG(hpd_reg, none),
HDMI_CFG(pwr_clk, 8x74),
HDMI_CFG(hpd_clk, 8x74),
.hpd_freq  = hpd_clk_freq_8x74,
 };

 static const struct of_device_id dt_match[] = {
+   { .compatible = "qcom,hdmi-tx-8996", .data = _tx_8996_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8994_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8084_config },
{ .compatible = "qcom,hdmi-tx-8974", .data = _tx_8974_config },
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 05/10] drm/msm/mdp5: Vote for SMMU power when performing translations

[Stephane Viau]

On most recent chipsets, clients need to vote for SMMU power
(regulator and clock) themselves for as long as they want the
SMMU to be on, performing translations.

This change enables (disables) the SMMU power just before
attaching (after detaching) MDP5 device to the SMMU.

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/mdp.txt |  3 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   | 65 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |  3 ++
 3 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/drm/msm/mdp.txt 
b/Documentation/devicetree/bindings/drm/msm/mdp.txt
index 0833eda..99ba764 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdp.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdp.txt
@@ -19,6 +19,9 @@ Optional properties:
 - gpus: phandle for gpu device
 - clock-names: the following clocks are optional:
   * "lut_clk"
+  * "iommu_clk"
+  * "mmagic_clk"
+- mmagic-supply: phandle for mmagic GDSC regulator used during IOMMU 
translation

 Example:

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 61fcb41..983bd53 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -129,6 +129,54 @@ static void mdp5_preclose(struct msm_kms *kms, struct 
drm_file *file)
mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
 }

+static int mdp5_translation_ctrl_pwr(struct mdp5_kms *mdp5_kms, bool on)
+{
+   struct device *dev = mdp5_kms->dev->dev;
+   int ret;
+
+   if (on) {
+   if (mdp5_kms->mmagic) {
+   ret = regulator_enable(mdp5_kms->mmagic);
+   if (ret) {
+   dev_err(dev, "failed to enable mmagic GDSC: 
%d\n", ret);
+   return ret;
+   }
+   }
+   if (mdp5_kms->mmagic_clk) {
+   clk_prepare_enable(mdp5_kms->mmagic_clk);
+   if (ret) {
+   dev_err(dev, "failed to enable mmagic_clk\n");
+   goto undo_gdsc;
+   }
+   }
+   if (mdp5_kms->iommu_clk) {
+   ret = clk_prepare_enable(mdp5_kms->iommu_clk);
+   if (ret) {
+   dev_err(dev, "failed to enable iommu_clk\n");
+   goto undo_mmagic_clk;
+   }
+   }
+   } else {
+   if (mdp5_kms->iommu_clk)
+   clk_disable_unprepare(mdp5_kms->iommu_clk);
+   if (mdp5_kms->mmagic_clk)
+   clk_disable_unprepare(mdp5_kms->mmagic_clk);
+   if (mdp5_kms->mmagic)
+   regulator_disable(mdp5_kms->mmagic);
+   }
+
+   return 0;
+
+undo_mmagic_clk:
+   if (mdp5_kms->mmagic_clk)
+   clk_disable_unprepare(mdp5_kms->mmagic_clk);
+undo_gdsc:
+   if (mdp5_kms->mmagic)
+   regulator_disable(mdp5_kms->mmagic);
+
+   return ret;
+}
+
 static void mdp5_destroy(struct msm_kms *kms)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
@@ -138,6 +186,7 @@ static void mdp5_destroy(struct msm_kms *kms)

if (mmu) {
mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
+   mdp5_translation_ctrl_pwr(mdp5_kms, false);
mmu->funcs->destroy(mmu);
}

@@ -520,6 +569,13 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
goto fail;
}

+   mdp5_kms->mmagic = devm_regulator_get_optional(>dev, "mmagic");
+   if (IS_ERR(mdp5_kms->mmagic)) {
+   ret = PTR_ERR(mdp5_kms->mmagic);
+   DBG("failed to get mmagic GDSC regulator: %d\n", ret);
+   mdp5_kms->mmagic = NULL;
+   }
+
/* mandatory clocks: */
ret = get_clk(pdev, _kms->axi_clk, "bus_clk", true);
if (ret)
@@ -539,6 +595,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)

/* optional clocks: */
get_clk(pdev, _kms->lut_clk, "lut_clk", false);
+   get_clk(pdev, _kms->mmagic_clk, "mmagic_clk", false);
+   get_clk(pdev, _kms->iommu_clk, "iommu_clk", false);

/* we need to set a default rate before enabling.  Set a safe
 * rate first, then figure out hw revision, and then set a
@@ -612,6 +670,13 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
DBG("coherent hardware translation table walks is off");
}

+   ret = mdp5_translation_ctrl_pwr(mdp5_kms, true);
+   if (ret) {
+ 

[PATCH 04/10] drm/msm/mdp5: Avoid printing error messages for optional clocks

[Stephane Viau]

The current behavior is to try to get optional clocks and print a
dev_err message in case of failure. This looks rather confusing
and may increase with the amount of optional clocks.

We may need a cleaner way to handle per-device clocks but in the
meantime, let's reduce the amount of dev_err messages during the
probe.

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/mdp.txt |  3 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   | 27 ++-
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/msm/mdp.txt 
b/Documentation/devicetree/bindings/drm/msm/mdp.txt
index 1a0598e..0833eda 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdp.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdp.txt
@@ -11,13 +11,14 @@ Required properties:
 - clock-names: the following clocks are required:
   * "core_clk"
   * "iface_clk"
-  * "lut_clk"
   * "src_clk"
   * "hdmi_clk"
   * "mpd_clk"

 Optional properties:
 - gpus: phandle for gpu device
+- clock-names: the following clocks are optional:
+  * "lut_clk"

 Example:

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index e11028c6..61fcb41 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -454,15 +454,19 @@ static void read_hw_revision(struct mdp5_kms *mdp5_kms,
 }

 static int get_clk(struct platform_device *pdev, struct clk **clkp,
-   const char *name)
+   const char *name, bool mandatory)
 {
struct device *dev = >dev;
struct clk *clk = devm_clk_get(dev, name);
-   if (IS_ERR(clk)) {
+   if (IS_ERR(clk) && mandatory) {
dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
return PTR_ERR(clk);
}
-   *clkp = clk;
+   if (IS_ERR(clk))
+   DBG("skipping %s", name);
+   else
+   *clkp = clk;
+
return 0;
 }

@@ -516,25 +520,26 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
goto fail;
}

-   ret = get_clk(pdev, _kms->axi_clk, "bus_clk");
+   /* mandatory clocks: */
+   ret = get_clk(pdev, _kms->axi_clk, "bus_clk", true);
if (ret)
goto fail;
-   ret = get_clk(pdev, _kms->ahb_clk, "iface_clk");
+   ret = get_clk(pdev, _kms->ahb_clk, "iface_clk", true);
if (ret)
goto fail;
-   ret = get_clk(pdev, _kms->src_clk, "core_clk_src");
+   ret = get_clk(pdev, _kms->src_clk, "core_clk_src", true);
if (ret)
goto fail;
-   ret = get_clk(pdev, _kms->core_clk, "core_clk");
+   ret = get_clk(pdev, _kms->core_clk, "core_clk", true);
if (ret)
goto fail;
-   ret = get_clk(pdev, _kms->lut_clk, "lut_clk");
-   if (ret)
-   DBG("failed to get (optional) lut_clk clock");
-   ret = get_clk(pdev, _kms->vsync_clk, "vsync_clk");
+   ret = get_clk(pdev, _kms->vsync_clk, "vsync_clk", true);
if (ret)
goto fail;

+   /* optional clocks: */
+   get_clk(pdev, _kms->lut_clk, "lut_clk", false);
+
/* we need to set a default rate before enabling.  Set a safe
 * rate first, then figure out hw revision, and then set a
 * more optimal rate:
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 03/10] drm/msm: Fix IOMMU clean up path in case msm_iommu_new() fails

[Stephane Viau]

msm_iommu_new() can fail and this change makes sure that we
detect the failure and free the allocated domain before going
any further.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 1 +
 drivers/gpu/drm/msm/msm_gpu.c   | 8 
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 14ac20a..e11028c6 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -590,6 +590,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
if (IS_ERR(mmu)) {
ret = PTR_ERR(mmu);
dev_err(dev->dev, "failed to init iommu: %d\n", ret);
+   iommu_domain_free(config->platform.iommu);
goto fail;
}

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 5d31b5a..aed9f37 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -651,6 +651,14 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
if (iommu) {
dev_info(drm->dev, "%s: using IOMMU\n", name);
gpu->mmu = msm_iommu_new(>dev, iommu);
+   if (IS_ERR(gpu->mmu)) {
+   ret = PTR_ERR(gpu->mmu);
+   dev_err(drm->dev, "failed to init iommu: %d\n", ret);
+   gpu->mmu = NULL;
+   iommu_domain_free(iommu);
+   goto fail;
+   }
+
} else {
dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM 
carveout!\n", name);
}
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 02/10] drm/msm/mdp5: Disable hardware translation table walks (MSM8996)

[Stephane Viau]

On certain targets (eg, MSM8996) we need to set the following
domain attribute for correct operation of the SMMU:
DOMAIN_ATTR_COHERENT_HTW_DISABLE.

Setting that attribute is very important on 8996. Without it, we would
see crazy translation faults.

Note:
There could be support for coherent hardware table walks in
the future

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index bbab6e6..14ac20a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -584,6 +584,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
mdelay(16);

if (config->platform.iommu) {
+   int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
+
mmu = msm_iommu_new(>dev, config->platform.iommu);
if (IS_ERR(mmu)) {
ret = PTR_ERR(mmu);
@@ -591,6 +593,19 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
goto fail;
}

+   /*
+* On certain targets (8996, for example) we need to set the
+* following domain attribute for correct operation of the SMMU;
+* Without it, we would see crazy translation faults..
+*/
+   if (rev == 7) {
+   int disable_htw = 1;
+
+   iommu_domain_set_attr(config->platform.iommu,
+   DOMAIN_ATTR_COHERENT_HTW_DISABLE, _htw);
+   DBG("coherent hardware translation table walks is off");
+   }
+
ret = mmu->funcs->attach(mmu, iommu_ports,
ARRAY_SIZE(iommu_ports));
if (ret) {
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 01/10] drm/msm/mdp5: remove the cfg pointer from SMP struct

[Stephane Viau]

We want to make sure we control all the information being passed
down to SMP block. Having access to the cfg pointer here may create
bad things in the future.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index efb918d..a6facaf 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -61,7 +61,7 @@ struct mdp5_smp_block {
int mmb_size;   /* MMB: size in bytes */
uint32_t clients[MAX_CLIENTS];  /* SMP port allocation /pipe */
mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
-   int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
+   uint8_t reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };

 #define MDP5_INTF_NUM_MAX  5
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 563cca9..6f425c2 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -90,7 +90,7 @@
 struct mdp5_smp {
struct drm_device *dev;

-   const struct mdp5_smp_block *cfg;
+   uint8_t reserved[MAX_CLIENTS]; /* fixed MMBs allocation per client */

int blk_cnt;
int blk_size;
@@ -141,10 +141,10 @@ static int smp_request_block(struct mdp5_smp *smp,
struct mdp5_kms *mdp5_kms = get_kms(smp);
struct mdp5_client_smp_state *ps = >client_state[cid];
int i, ret, avail, cur_nblks, cnt = smp->blk_cnt;
-   int reserved;
+   uint8_t reserved;
unsigned long flags;

-   reserved = smp->cfg->reserved[cid];
+   reserved = smp->reserved[cid];

spin_lock_irqsave(>state_lock, flags);

@@ -405,12 +405,12 @@ struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, 
const struct mdp5_smp_blo
}

smp->dev = dev;
-   smp->cfg = cfg;
smp->blk_cnt = cfg->mmb_count;
smp->blk_size = cfg->mmb_size;

/* statically tied MMBs cannot be re-allocated: */
bitmap_copy(smp->state, cfg->reserved_state, smp->blk_cnt);
+   memcpy(smp->reserved, cfg->reserved, sizeof(smp->reserved));
spin_lock_init(>state_lock);

return smp;
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 00/10] drm/msm: Add support for MSM8996

[Stephane Viau]

This series of patches adds support for MSM8996, including MDP5 v1.7.
Note that only the HDMI interface is supported for now. 

Stephane Viau (10):
  drm/msm/mdp5: remove the cfg pointer from SMP struct
  drm/msm/mdp5: Disable hardware translation table walks (MSM8996)
  drm/msm: Fix IOMMU clean up path in case msm_iommu_new() fails
  drm/msm/mdp5: Avoid printing error messages for optional clocks
  drm/msm/mdp5: Vote for SMMU power when performing translations
  drm/msm/hdmi: Add basic HDMI support for msm8996
  drm/msm/mdp: Update generated headers (Pixel Extension)
  drm/msm/mdp5: Use the newly introduced enum mdp_component_type
  drm/msm/mdp: Add Software Pixel Extension support
  drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996)

 Documentation/devicetree/bindings/drm/msm/hdmi.txt |   3 +
 Documentation/devicetree/bindings/drm/msm/mdp.txt  |   8 +-
 drivers/gpu/drm/msm/hdmi/hdmi.c|  17 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h|  82 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c|  95 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h|  11 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c| 126 +++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h|   5 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c  | 201 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c|   8 +-
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h   |  11 +-
 drivers/gpu/drm/msm/mdp/mdp_kms.h  |   6 +
 drivers/gpu/drm/msm/msm_gpu.c  |   8 +
 13 files changed, 501 insertions(+), 80 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: Rename scalers' filter fields

[Stephane Viau]

The current names were guessed based on downstream driver.
This change replaces the filter fields' names to avoid any
confusion.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 6e92e54..d9a2381 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -355,7 +355,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
+   



@@ -388,13 +388,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
-   
-   
-   
+   
+   
+   
+   
+   
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: Rename 1st Source Chroma Sampling option

[Stephane Viau]

enum mdp_chroma_samp_type's first value (0) is actually shared by
all non-subsampled formats; that is RGB but also some YUV formats
(eg: YUV444). This change makes the name a little less confusing.

Signed-off-by: Stephane Viau 
Signed-off-by: Wentao Xu 
---
 rnndb/mdp/mdp_common.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rnndb/mdp/mdp_common.xml b/rnndb/mdp/mdp_common.xml
index b4d1949..694b635 100644
--- a/rnndb/mdp/mdp_common.xml
+++ b/rnndb/mdp/mdp_common.xml
@@ -7,7 +7,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">
 

 
-
+
 
 
 
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 6/6] drm/msm/mdp5: add more YUV formats for MDP5

[Stephane Viau]

Add packed YUV422 and planar YUV420 formats to MDP supported
formats.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 105 +-
 drivers/gpu/drm/msm/mdp/mdp_format.c  |  19 ++
 2 files changed, 77 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 7fb526d..3d63e21 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
@@ -40,6 +40,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
+
 static void set_scanout_locked(struct drm_plane *plane,
struct drm_framebuffer *fb);

@@ -346,16 +347,21 @@ static int calc_phase_step(uint32_t src, uint32_t dst, 
uint32_t *out_phase)
return 0;
 }

-static int calc_scalex_steps(uint32_t pixel_format, uint32_t src, uint32_t 
dest,
+static int calc_scalex_steps(struct drm_plane *plane,
+   uint32_t pixel_format, uint32_t src, uint32_t dest,
uint32_t phasex_steps[2])
 {
+   struct mdp5_kms *mdp5_kms = get_kms(plane);
+   struct device *dev = mdp5_kms->dev->dev;
uint32_t phasex_step;
unsigned int hsub;
int ret;

ret = calc_phase_step(src, dest, _step);
-   if (ret)
+   if (ret) {
+   dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
return ret;
+   }

hsub = drm_format_horz_chroma_subsampling(pixel_format);

@@ -365,16 +371,21 @@ static int calc_scalex_steps(uint32_t pixel_format, 
uint32_t src, uint32_t dest,
return 0;
 }

-static int calc_scaley_steps(uint32_t pixel_format, uint32_t src, uint32_t 
dest,
+static int calc_scaley_steps(struct drm_plane *plane,
+   uint32_t pixel_format, uint32_t src, uint32_t dest,
uint32_t phasey_steps[2])
 {
+   struct mdp5_kms *mdp5_kms = get_kms(plane);
+   struct device *dev = mdp5_kms->dev->dev;
uint32_t phasey_step;
unsigned int vsub;
int ret;

ret = calc_phase_step(src, dest, _step);
-   if (ret)
+   if (ret) {
+   dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
return ret;
+   }

vsub = drm_format_vert_chroma_subsampling(pixel_format);

@@ -384,28 +395,38 @@ static int calc_scaley_steps(uint32_t pixel_format, 
uint32_t src, uint32_t dest,
return 0;
 }

-static uint32_t get_scalex_config(uint32_t src, uint32_t dest)
-{
-   uint32_t filter;
-
-   filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
-
-   return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(filter) |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(filter)  |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(filter);
-}
-
-static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
+static uint32_t get_scale_config(enum mdp_chroma_samp_type chroma_sample,
+   uint32_t src, uint32_t dest, bool hor)
 {
-   uint32_t filter;
-
-   filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
+   uint32_t y_filter =   (src <= dest) ? SCALE_FILTER_CA  : 
SCALE_FILTER_PCMN;
+   uint32_t y_a_filter = (src <= dest) ? SCALE_FILTER_BIL : 
SCALE_FILTER_PCMN;
+   uint32_t uv_filter = ((src / 2) <= dest) ? /* 2x upsample */
+ SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
+   uint32_t value = 0;
+
+   if (chroma_sample == CHROMA_420 || chroma_sample == CHROMA_H2V1) {
+   if (hor)
+   value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_filter) |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter) |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter);
+   else
+   value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_filter) |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter) |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter);
+   } else if (src != dest) {
+   if (hor)
+   value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
+   
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_a_filter) |
+  

[PATCH 5/6] drm/msm/mdp5: use 2 memory clients for YUV formats on newer mdp5

[Stephane Viau]

From: Wentao Xu <went...@codeaurora.org>

Newer MDP5 uses 2 shared memory pool clients for certain YUV formats.
For example, if VIG0 is used to fetch data in YUYV format, it will use
VIG0_Y for Y component, and VIG0_Cr for UV packed.

Signed-off-by: Wentao Xu 
[rebase]
Signed-off-by: Stephane Viau 

Change-Id: I24df222372b6cea5e67d2331e2c842c4faba383e
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c   | 26 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h   |  3 ++-
 3 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 622f7de..7fb526d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -449,7 +449,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,

/* Request some memory from the SMP: */
ret = mdp5_smp_request(mdp5_kms->smp,
-   mdp5_plane->pipe, fb->pixel_format, src_w);
+   mdp5_plane->pipe, format, src_w, false);
if (ret)
return ret;

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 64a27d8..563cca9 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -90,6 +90,8 @@
 struct mdp5_smp {
struct drm_device *dev;

+   const struct mdp5_smp_block *cfg;
+
int blk_cnt;
int blk_size;

@@ -137,14 +139,12 @@ static int smp_request_block(struct mdp5_smp *smp,
u32 cid, int nblks)
 {
struct mdp5_kms *mdp5_kms = get_kms(smp);
-   const struct mdp5_cfg_hw *hw_cfg;
struct mdp5_client_smp_state *ps = >client_state[cid];
int i, ret, avail, cur_nblks, cnt = smp->blk_cnt;
int reserved;
unsigned long flags;

-   hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
-   reserved = hw_cfg->smp.reserved[cid];
+   reserved = smp->cfg->reserved[cid];

spin_lock_irqsave(>state_lock, flags);

@@ -209,12 +209,14 @@ static void set_fifo_thresholds(struct mdp5_smp *smp,
  * decimated width.  Ie. SMP buffering sits downstream of decimation (which
  * presumably happens during the dma from scanout buffer).
  */
-int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, u32 fmt, u32 
width)
+int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe,
+   const struct mdp_format *format, u32 width, bool hdecim)
 {
struct mdp5_kms *mdp5_kms = get_kms(smp);
struct drm_device *dev = mdp5_kms->dev;
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
int i, hsub, nplanes, nlines, nblks, ret;
+   u32 fmt = format->base.pixel_format;

nplanes = drm_format_num_planes(fmt);
hsub = drm_format_horz_chroma_subsampling(fmt);
@@ -222,6 +224,21 @@ int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe 
pipe, u32 fmt, u32 wid
/* different if BWC (compressed framebuffer?) enabled: */
nlines = 2;

+   /* Newer MDPs have split/packing logic, which fetches sub-sampled
+* U and V components (splits them from Y if necessary) and packs
+* them together, writes to SMP using a single client.
+*/
+   if ((rev > 0) && (format->chroma_sample > CHROMA_FULL)) {
+   fmt = DRM_FORMAT_NV24;
+   nplanes = 2;
+
+   /* if decimation is enabled, HW decimates less on the
+* sub sampled chroma components
+*/
+   if (hdecim && (hsub > 1))
+   hsub = 1;
+   }
+
for (i = 0, nblks = 0; i < nplanes; i++) {
int n, fetch_stride, cpp;

@@ -388,6 +405,7 @@ struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, 
const struct mdp5_smp_blo
}

smp->dev = dev;
+   smp->cfg = cfg;
smp->blk_cnt = cfg->mmb_count;
smp->blk_size = cfg->mmb_size;

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h
index 5b6c236..20b87e8 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h
@@ -39,7 +39,8 @@ struct mdp5_smp;
 struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct 
mdp5_smp_block *cfg);
 void  mdp5_smp_destroy(struct mdp5_smp *smp);

-int  mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, u32 fmt, u32 
width);
+int  mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe,
+   const struct mdp_format *format, u32 width, bool hdecim);
 void mdp5_smp_configure(struct mdp5_smp *smp, enum mdp5_pipe pipe);
 void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe);
 void mdp5_smp_release(struct mdp5_smp *smp, enum mdp5_pipe pipe);
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 4/6] drm/msm/mdp: mark if a MDP format is YUV at definition

[Stephane Viau]

From: Wentao Xu <went...@codeaurora.org>

This makes it easy to determine if a format is YUV. The old
method of using chroma sample type incorrectly marks YUV444 as
RGB format.

Signed-off-by: Wentao Xu 
[rebase]
Signed-off-by: Stephane Viau 

Change-Id: I3e1fa4473be8421fac8d79100f30bff5823be5f4
---
 drivers/gpu/drm/msm/mdp/mdp_format.c | 27 ++-
 drivers/gpu/drm/msm/mdp/mdp_kms.h|  3 ++-
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c 
b/drivers/gpu/drm/msm/mdp/mdp_format.c
index 7b0524d..fd803c5 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -71,7 +71,7 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
 };

-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs) { \
+#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, 
yuv) { \
.base = { .pixel_format = DRM_FORMAT_ ## name }, \
.bpc_a = BPC ## a ## A,  \
.bpc_r = BPC ## r,   \
@@ -83,7 +83,8 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.cpp = c,\
.unpack_count = cnt, \
.fetch_type = fp,\
-   .chroma_sample = cs  \
+   .chroma_sample = cs, \
+   .is_yuv = yuv,   \
 }

 #define BPC0A 0
@@ -95,30 +96,30 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
 static const struct mdp_format formats[] = {
/*  name  a  r  g  b   e0 e1 e2 e3  alpha   tight  cpp cnt ... */
FMT(ARGB, 8, 8, 8, 8,  1, 0, 2, 3,  true,   true,  4,  4,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(ABGR, 8, 8, 8, 8,  2, 0, 1, 3,  true,   true,  4,  4,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGBA, 8, 8, 8, 8,  3, 1, 0, 2,  true,   true,  4,  4,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGRA, 8, 8, 8, 8,  3, 2, 0, 1,  true,   true,  4,  4,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(XRGB, 8, 8, 8, 8,  1, 0, 2, 3,  false,  true,  4,  4,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGB888,   0, 8, 8, 8,  1, 0, 2, 0,  false,  true,  3,  3,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGR888,   0, 8, 8, 8,  2, 0, 1, 0,  false,  true,  3,  3,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGB565,   0, 5, 6, 5,  1, 0, 2, 0,  false,  true,  2,  3,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGR565,   0, 5, 6, 5,  2, 0, 1, 0,  false,  true,  2,  3,
-   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),

/* --- RGB formats above / YUV formats below this line --- */

FMT(NV12, 0, 8, 8, 8,  1, 2, 0, 0,  false,  true,  2, 2,
-   MDP_PLANE_PSEUDO_PLANAR, CHROMA_420),
+   MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
FMT(NV21, 0, 8, 8, 8,  2, 1, 0, 0,  false,  true,  2, 2,
-   MDP_PLANE_PSEUDO_PLANAR, CHROMA_420),
+   MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
 };

 /*
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h 
b/drivers/gpu/drm/msm/mdp/mdp_kms.h
index 2d3428c..02c6b7f 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h
@@ -90,9 +90,10 @@ struct mdp_format {
uint8_t cpp, unpack_count;
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
+   bool is_yuv;
 };
 #define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->chroma_sample > 
CHROMA_RGB)
+#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)

 uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool 
rgb_only);
 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 3/6] drm/msm/mdp: Update generated headers (chroma_samp)

[Stephane Viau]

See Envytools patch:

rnndb: Rename 1st Source Chroma Sampling option

Signed-off-by: Wentao Xu 
Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 37 +++-
 1 file changed, 3 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
index 641d036..973dec2 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -8,45 +8,14 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml (
676 bytes, from 2014-12-05 15:34:49)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml(  
20915 bytes, from 2015-03-24 22:05:22)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml  (   
2352 bytes, from 2015-04-12 15:02:42)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml(  
35083 bytes, from 2015-04-12 15:04:03)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (  
22094 bytes, from 2015-05-12 12:45:23)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml(
344 bytes, from 2013-08-11 19:26:32)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml (   
1686 bytes, from 2014-10-31 16:48:57)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml (
600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml   (  
29012 bytes, from 2015-05-12 12:45:23)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (  
10416 bytes, from 2015-05-12 12:45:23)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml (   2353 
bytes, from 2015-07-06 18:15:42)

-Copyright (C) 2013-2015 by the following authors:
-- Rob Clark  (robclark)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+Copyright (C) 2015
 */


 enum mdp_chroma_samp_type {
-   CHROMA_RGB = 0,
+   CHROMA_FULL = 0,
CHROMA_H2V1 = 1,
CHROMA_H1V2 = 2,
CHROMA_420 = 3,
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/6] drm/msm/mdp5: Rename scalers' filter fields

[Stephane Viau]

The current names were guessed based on downstream driver.
This change replaces the filter fields' names to avoid any
confusion.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 2227556..622f7de 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -391,9 +391,9 @@ static uint32_t get_scalex_config(uint32_t src, uint32_t 
dest)
filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;

return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(filter) |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(filter)  |
-   MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(filter);
+   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(filter) |
+   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(filter)  |
+   MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(filter);
 }

 static uint32_t get_scaley_config(uint32_t src, uint32_t dest)
@@ -403,9 +403,9 @@ static uint32_t get_scaley_config(uint32_t src, uint32_t 
dest)
filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;

return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
-   MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(filter) |
-   MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(filter)  |
-   MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(filter);
+   MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(filter) |
+   MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(filter)  |
+   MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(filter);
 }

 static int mdp5_plane_mode_set(struct drm_plane *plane,
@@ -516,7 +516,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count 
- 1) |
COND(format->unpack_tight, 
MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
-   MDP5_PIPE_SRC_FORMAT_NUM_PLANES(format->fetch_type) |
+   MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |

MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 1/6] drm/msm/mdp5: Update generated headers (filter fieds)

[Stephane Viau]

See envytools commit: "rnndb: Rename scalers' filter fields"

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 58 -
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 3977737..4e568e9 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
35083 bytes, from 2015-06-26 15:38:43)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
35043 bytes, from 2015-06-26 15:41:34)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2015-04-30 16:26:30)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2352 bytes, from 2015-06-26 13:24:47)

@@ -795,11 +795,11 @@ static inline uint32_t 
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 }
 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT  0x0002
 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB  0x0004
-#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK  0x0018
-#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val)
+#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK  0x0018
+#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
 {
-   return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & 
MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
+   return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & 
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
 }
 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0180
 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT23
@@ -889,41 +889,41 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t 
val)
 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 
0x0204 + __offset_PIPE(i0); }
 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN   0x0001
 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN   0x0002
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x0300
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT8
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum 
mdp5_scale_filter val)
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK  0x0300
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum 
mdp5_scale_filter val)
 {
-   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & 
MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
+   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & 
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
 }
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x0c00
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT10
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum 
mdp5_scale_filter val)
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK  0x0c00
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum 
mdp5_scale_filter val)
 {
-   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & 
MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
+   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & 
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
 }
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK  0x3000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum 
mdp5_scale_filter val)
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK0x3000
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT   12
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum 
mdp5_scale_filter val)
 {
-   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & 
MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
+   return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) 
& MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
 }
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK  0xc000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
-static inl

[PATCH 0/6] drm/msm/mdp: Add the rest of YUV formats

[Stephane Viau]

Well, I think this patch set sums up the YUV formats support for MDP5.
Some tricks need to be done around the SMP client allocation to reflect
the newer MDP5 hardware, where all U and V pixels are fetched together.
Envytools patches will be sent separately for the two generated headers.

Rgds,
Stephane.

Stephane Viau (4):
  drm/msm/mdp5: Update generated headers (filter fieds)
  drm/msm/mdp5: Rename scalers' filter fields
  drm/msm/mdp: Update generated headers (chroma_samp)
  drm/msm/mdp5: add more YUV formats for MDP5

Wentao Xu (2):
  drm/msm/mdp: mark if a MDP format is YUV at definition
  drm/msm/mdp5: use 2 memory clients for YUV formats on newer mdp5

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h   |  58 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 109 --
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c   |  26 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h   |   3 +-
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h  |  37 +-
 drivers/gpu/drm/msm/mdp/mdp_format.c  |  46 +
 drivers/gpu/drm/msm/mdp/mdp_kms.h |   3 +-
 7 files changed, 151 insertions(+), 131 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/2] drm/msm: Add support for msm8x94

[Stephane Viau]

This change adds the MDP and HDMI support for msm8x94.
Note that HDMI PHY registers are not being accessed anymore from
the driver.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c   | 30 -
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  8 +++-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 43 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c   | 73 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  8 ++--
 5 files changed, 129 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 8145362..4d73a69 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -89,16 +89,15 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->config = config;

/* not sure about which phy maps to which msm.. probably I miss some */
-   if (config->phy_init)
+   if (config->phy_init) {
hdmi->phy = config->phy_init(hdmi);
-   else
-   hdmi->phy = ERR_PTR(-ENXIO);

-   if (IS_ERR(hdmi->phy)) {
-   ret = PTR_ERR(hdmi->phy);
-   dev_err(>dev, "failed to load phy: %d\n", ret);
-   hdmi->phy = NULL;
-   goto fail;
+   if (IS_ERR(hdmi->phy)) {
+   ret = PTR_ERR(hdmi->phy);
+   dev_err(>dev, "failed to load phy: %d\n", ret);
+   hdmi->phy = NULL;
+   goto fail;
+   }
}

hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI");
@@ -330,7 +329,19 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
.hpd_freq  = hpd_clk_freq_8x74,
 };

+static const char *hpd_reg_names_8x94[] = {};
+
+static struct hdmi_platform_config hdmi_tx_8x94_config = {
+   .phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */
+   HDMI_CFG(pwr_reg, 8x74),
+   HDMI_CFG(hpd_reg, 8x94),
+   HDMI_CFG(pwr_clk, 8x74),
+   HDMI_CFG(hpd_clk, 8x74),
+   .hpd_freq  = hpd_clk_freq_8x74,
+};
+
 static const struct of_device_id dt_match[] = {
+   { .compatible = "qcom,hdmi-tx-8x94", .data = _tx_8x94_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8084_config },
{ .compatible = "qcom,hdmi-tx-8074", .data = _tx_8074_config },
{ .compatible = "qcom,hdmi-tx-8960", .data = _tx_8960_config },
@@ -347,8 +358,7 @@ static int get_gpio(struct device *dev, struct device_node 
*of_node, const char
snprintf(name2, sizeof(name2), "%s-gpio", name);
gpio = of_get_named_gpio(of_node, name2, 0);
if (gpio < 0) {
-   dev_err(dev, "failed to get gpio: %s (%d)\n",
-   name, gpio);
+   DBG("failed to get gpio: %s (%d)", name, gpio);
gpio = -1;
}
}
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index a7a1d82..00cec41 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -100,7 +100,9 @@ static void hdmi_bridge_pre_enable(struct drm_bridge 
*bridge)
hdmi_audio_update(hdmi);
}

-   phy->funcs->powerup(phy, hdmi->pixclock);
+   if (phy)
+   phy->funcs->powerup(phy, hdmi->pixclock);
+
hdmi_set_mode(hdmi, true);
 }

@@ -120,7 +122,9 @@ static void hdmi_bridge_post_disable(struct drm_bridge 
*bridge)

DBG("power down");
hdmi_set_mode(hdmi, false);
-   phy->funcs->powerdown(phy);
+
+   if (phy)
+   phy->funcs->powerdown(phy);

if (hdmi->power_on) {
power_off(bridge);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index ece572d..cdc818c 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -84,21 +84,25 @@ static int gpio_config(struct hdmi *hdmi, bool on)
int ret;

if (on) {
-   ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK");
-   if (ret) {
-   dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
-   "HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
-   goto error1;
+   if (config->ddc_clk_gpio != -1) {
+   ret = gpio_request(config->ddc_clk_gpio, 
"HDMI_DDC_CLK");
+   if (ret) {
+   dev_err(dev, "'%s'(%d) gpio_

[PATCH 1/2] drm/msm/hdmi: remove ->reset() from HDMI PHY

[Stephane Viau]

->reset() currently only accesses HDMI core registers, and yet it
is located in hdmi_phy*. Since no PHY registers are being
accessed during ->reset(), it would be better to bring that
function in hdmi core module where HDMI core registers are
usually being accessed.

This will also help for msm8x94 for which no PHY registers
accesses are done (->phy_init == NULL) but the HDMI PHY reset
from HDMI core still needs to be done.

Note:
SW_RESET_PLL bit is not written in hdmi_phy_8x60_reset(); this
write should not affect anything if the corresponding field is
not writable.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  1 -
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 51 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c  | 52 
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c  | 32 -
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c  | 57 ---
 5 files changed, 50 insertions(+), 143 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 68fdfb3..a155c4a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -117,7 +117,6 @@ static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)

 struct hdmi_phy_funcs {
void (*destroy)(struct hdmi_phy *phy);
-   void (*reset)(struct hdmi_phy *phy);
void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
void (*powerdown)(struct hdmi_phy *phy);
 };
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index a1650f4..ece572d 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -28,6 +28,55 @@ struct hdmi_connector {
 };
 #define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base)

+static void hdmi_phy_reset(struct hdmi *hdmi)
+{
+   unsigned int val;
+
+   val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
+
+   if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
+   /* pull low */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val & ~HDMI_PHY_CTRL_SW_RESET);
+   } else {
+   /* pull high */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val | HDMI_PHY_CTRL_SW_RESET);
+   }
+
+   if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
+   /* pull low */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
+   } else {
+   /* pull high */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val | HDMI_PHY_CTRL_SW_RESET_PLL);
+   }
+
+   msleep(100);
+
+   if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
+   /* pull high */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val | HDMI_PHY_CTRL_SW_RESET);
+   } else {
+   /* pull low */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val & ~HDMI_PHY_CTRL_SW_RESET);
+   }
+
+   if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
+   /* pull high */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val | HDMI_PHY_CTRL_SW_RESET_PLL);
+   } else {
+   /* pull low */
+   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+   val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
+   }
+}
+
 static int gpio_config(struct hdmi *hdmi, bool on)
 {
struct device *dev = >pdev->dev;
@@ -181,7 +230,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
}

hdmi_set_mode(hdmi, false);
-   phy->funcs->reset(phy);
+   hdmi_phy_reset(hdmi);
hdmi_set_mode(hdmi, true);

hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
index 6997ec6..3a01cb5 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
@@ -426,57 +426,6 @@ static void hdmi_phy_8960_destroy(struct hdmi_phy *phy)
kfree(phy_8960);
 }

-static void hdmi_phy_8960_reset(struct hdmi_phy *phy)
-{
-   struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
-   struct hdmi *hdmi = phy_8960->hdmi;
-   unsigned int val;
-
-   val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
-
-   if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
-   /* pull low */
-   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
-   val & ~HDMI_PHY_CTRL_SW_RESET);
-   } else {
-   /* pull high */
-   hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
-   val | HDMI_PHY_CTRL_SW_RESET);
-   }
-
-   if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
-

[PATCH 0/2] drm/msm: HDMI PHY rework for MSM8x94 support

[Stephane Viau]

This it to follow up with my RFC sent a few days ago[1].

Since the RFC got discussed and approved through IRC, here are the actual
patches.

Rgds,
Stephane.

[1] http://lists.freedesktop.org/archives/dri-devel/2015-June/084788.html

Stephane Viau (2):
  drm/msm/hdmi: remove ->reset() from HDMI PHY
  drm/msm: Add support for msm8x94

 drivers/gpu/drm/msm/hdmi/hdmi.c   | 30 ++
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  1 -
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  8 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 94 +--
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c  | 52 -
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c  | 32 ---
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c  | 57 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c   | 73 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  8 ++-
 9 files changed, 179 insertions(+), 176 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[RFC 2/2] drm/msm: Add support for msm8x94

[Stephane Viau]

This change adds the MDP and HDMI support for msm8x94.
Note that HDMI PHY registers are not being accessed anymore from
the driver.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c   | 30 -
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  8 +++-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 43 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c   | 73 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  8 ++--
 5 files changed, 129 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 8145362..4d73a69 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -89,16 +89,15 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->config = config;

/* not sure about which phy maps to which msm.. probably I miss some */
-   if (config->phy_init)
+   if (config->phy_init) {
hdmi->phy = config->phy_init(hdmi);
-   else
-   hdmi->phy = ERR_PTR(-ENXIO);

-   if (IS_ERR(hdmi->phy)) {
-   ret = PTR_ERR(hdmi->phy);
-   dev_err(>dev, "failed to load phy: %d\n", ret);
-   hdmi->phy = NULL;
-   goto fail;
+   if (IS_ERR(hdmi->phy)) {
+   ret = PTR_ERR(hdmi->phy);
+   dev_err(>dev, "failed to load phy: %d\n", ret);
+   hdmi->phy = NULL;
+   goto fail;
+   }
}

hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI");
@@ -330,7 +329,19 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
.hpd_freq  = hpd_clk_freq_8x74,
 };

+static const char *hpd_reg_names_8x94[] = {};
+
+static struct hdmi_platform_config hdmi_tx_8x94_config = {
+   .phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */
+   HDMI_CFG(pwr_reg, 8x74),
+   HDMI_CFG(hpd_reg, 8x94),
+   HDMI_CFG(pwr_clk, 8x74),
+   HDMI_CFG(hpd_clk, 8x74),
+   .hpd_freq  = hpd_clk_freq_8x74,
+};
+
 static const struct of_device_id dt_match[] = {
+   { .compatible = "qcom,hdmi-tx-8x94", .data = _tx_8x94_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8084_config },
{ .compatible = "qcom,hdmi-tx-8074", .data = _tx_8074_config },
{ .compatible = "qcom,hdmi-tx-8960", .data = _tx_8960_config },
@@ -347,8 +358,7 @@ static int get_gpio(struct device *dev, struct device_node 
*of_node, const char
snprintf(name2, sizeof(name2), "%s-gpio", name);
gpio = of_get_named_gpio(of_node, name2, 0);
if (gpio < 0) {
-   dev_err(dev, "failed to get gpio: %s (%d)\n",
-   name, gpio);
+   DBG("failed to get gpio: %s (%d)", name, gpio);
gpio = -1;
}
}
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index a7a1d82..00cec41 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -100,7 +100,9 @@ static void hdmi_bridge_pre_enable(struct drm_bridge 
*bridge)
hdmi_audio_update(hdmi);
}

-   phy->funcs->powerup(phy, hdmi->pixclock);
+   if (phy)
+   phy->funcs->powerup(phy, hdmi->pixclock);
+
hdmi_set_mode(hdmi, true);
 }

@@ -120,7 +122,9 @@ static void hdmi_bridge_post_disable(struct drm_bridge 
*bridge)

DBG("power down");
hdmi_set_mode(hdmi, false);
-   phy->funcs->powerdown(phy);
+
+   if (phy)
+   phy->funcs->powerdown(phy);

if (hdmi->power_on) {
power_off(bridge);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index ece572d..cdc818c 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -84,21 +84,25 @@ static int gpio_config(struct hdmi *hdmi, bool on)
int ret;

if (on) {
-   ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK");
-   if (ret) {
-   dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
-   "HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
-   goto error1;
+   if (config->ddc_clk_gpio != -1) {
+   ret = gpio_request(config->ddc_clk_gpio, 
"HDMI_DDC_CLK");
+   if (ret) {
+   dev_err(dev, "'%s'(%d) gpio_

[RFC 1/2] [RFC] drm/msm/hdmi: remove ->reset() from HDMI PHY

[Stephane Viau]

->reset() currently only accesses HDMI core registers, and yet it
is located in hdmi_phy*. Since no PHY registers are being
accessed during ->reset(), it would be better to bring that
function in hdmi core module where HDMI core registers are
usually being accessed.

This will also help for msm8x94 for which no PHY registers
accesses are done (->phy_init == NULL) but the HDMI PHY reset
from HDMI core still needs to be done.

Note:
SW_RESET_PLL bit is not written in hdmi_phy_8x60_reset(); this
write should not affect anything if the corresponding field is
not writable.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  1 -
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 51 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c  | 52 
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c  | 32 -
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c  | 57 ---
 5 files changed, 50 insertions(+), 143 deletions(-)



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[RFC 0/2] drm/msm: HDMI PHY rework for MSM8x94 support

[Stephane Viau]

The RFC concerns a code restructuring of the HDMI module, which mainly has two
purposes:

1. architectural 
HDMI registers are divided in two parts: HDMI core and HDMI PHY. The HDMI Core
registers are common to all chipsets sharing the MDP version (MDP5 here). On
the other hand, HDMI PHY registers depend on the interface and process (28nm,
20nm, ...) being used for the same chipsets. Some chipsets (eg: msm8x94) don't
require us to access HDMI PHY registers.
>From a software architecture point of view, it would make sense that all HDMI
PHY registers should only be accessed by (PHY) hdmi_phy_*.c files, while all 
HDMI Core registers are read/written by the (core) hdmi.c and hdmi_connector.c
files.

2. readability 
Once we add msm8x94, which does not program HDMI PHY registers, it will be
easier to handle the HDMI core register programming because a hdmi_phy_*.c
file won't be created for this chipset. Instead of creating such a stub file
or some kind of workaround, it only makes sense to bring the HDMI core register 
programming where it is supposed to be.

To summarize, this re-structuring is to improve the code architecture,
facilitate the introduction of msm8x94 support and won't change the current
functionality.

Stephane Viau (2):
  [RFC] drm/msm/hdmi: remove ->reset() from HDMI PHY
  drm/msm: Add support for msm8x94

 drivers/gpu/drm/msm/hdmi/hdmi.c   | 30 ++
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  1 -
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  8 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 94 +--
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c  | 52 -
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c  | 32 ---
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c  | 57 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c   | 73 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  8 ++-
 9 files changed, 179 insertions(+), 176 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v3 2/2] drm/msm/hdmi: Use pinctrl in HDMI driver

[Stephane Viau]

Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.

Signed-off-by: Stephane Viau 
---
v3:
- Use pins binding handled in driver really_probe()  [Ivan]

v2:
- Add devicetree binding documentation for pinctrl property  [Ivan]
- Use pinctrl framework's PINCTRL_STATE_DEFAULT/SLEEP states [Ivan]

 Documentation/devicetree/bindings/drm/msm/hdmi.txt |  6 ++
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c  | 11 +++
 2 files changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt 
b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
index a29a55f..c43aa53 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -20,6 +20,9 @@ Required properties:
 Optional properties:
 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
+- pinctrl-names: the pin control state names; should contain "default"
+- pinctrl-0: the default pinctrl state (active)
+- pinctrl-1: the "sleep" pinctrl state

 Example:

@@ -44,5 +47,8 @@ Example:
qcom,hdmi-tx-hpd = < 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <_hdmi_mvs>;
hdmi-mux-supply = <_3p3v>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_active  _active  _active>;
+   pinctrl-1 = <_suspend _suspend _suspend>;
};
 };
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index e29b62a..ece572d 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -16,6 +16,7 @@
  */

 #include 
+#include 

 #include "msm_kms.h"
 #include "hdmi.h"
@@ -199,6 +200,12 @@ static int hpd_enable(struct hdmi_connector 
*hdmi_connector)
}
}

+   ret = pinctrl_pm_select_default_state(dev);
+   if (ret) {
+   dev_err(dev, "pinctrl state chg failed: %d\n", ret);
+   goto fail;
+   }
+
ret = gpio_config(hdmi, true);
if (ret) {
dev_err(dev, "failed to configure GPIOs: %d\n", ret);
@@ -268,6 +275,10 @@ static void hdp_disable(struct hdmi_connector 
*hdmi_connector)
if (ret)
dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret);

+   ret = pinctrl_pm_select_sleep_state(dev);
+   if (ret)
+   dev_warn(dev, "pinctrl state chg failed: %d\n", ret);
+
for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_disable(hdmi->hpd_regs[i]);
if (ret)
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v3 1/2] drm/msm/hdmi: Point to the right struct device

[Stephane Viau]

DRM device's dev (hdmi->dev->dev) points to the mdss_mdp device
handle. Instead, we should get a reference to the mdss_hdmi
handle.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 32 +++
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 914bf95..e29b62a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -78,14 +78,14 @@ static void hdmi_phy_reset(struct hdmi *hdmi)

 static int gpio_config(struct hdmi *hdmi, bool on)
 {
-   struct drm_device *dev = hdmi->dev;
+   struct device *dev = >pdev->dev;
const struct hdmi_platform_config *config = hdmi->config;
int ret;

if (on) {
ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK");
if (ret) {
-   dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
+   dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
goto error1;
}
@@ -93,7 +93,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)

ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA");
if (ret) {
-   dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
+   dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_DATA", config->ddc_data_gpio, ret);
goto error2;
}
@@ -101,7 +101,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)

ret = gpio_request(config->hpd_gpio, "HDMI_HPD");
if (ret) {
-   dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
+   dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_HPD", config->hpd_gpio, ret);
goto error3;
}
@@ -111,7 +111,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
if (config->mux_en_gpio != -1) {
ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN");
if (ret) {
-   dev_err(dev->dev, "'%s'(%d) gpio_request 
failed: %d\n",
+   dev_err(dev, "'%s'(%d) gpio_request failed: 
%d\n",
"HDMI_MUX_EN", config->mux_en_gpio, 
ret);
goto error4;
}
@@ -121,7 +121,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
if (config->mux_sel_gpio != -1) {
ret = gpio_request(config->mux_sel_gpio, 
"HDMI_MUX_SEL");
if (ret) {
-   dev_err(dev->dev, "'%s'(%d) gpio_request 
failed: %d\n",
+   dev_err(dev, "'%s'(%d) gpio_request failed: 
%d\n",
"HDMI_MUX_SEL", config->mux_sel_gpio, 
ret);
goto error5;
}
@@ -132,7 +132,7 @@ static int gpio_config(struct hdmi *hdmi, bool on)
ret = gpio_request(config->mux_lpm_gpio,
"HDMI_MUX_LPM");
if (ret) {
-   dev_err(dev->dev,
+   dev_err(dev,
"'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_LPM",
config->mux_lpm_gpio, ret);
@@ -185,7 +185,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
 {
struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
-   struct drm_device *dev = hdmi_connector->base.dev;
+   struct device *dev = >pdev->dev;
struct hdmi_phy *phy = hdmi->phy;
uint32_t hpd_ctrl;
int i, ret;
@@ -193,7 +193,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_enable(hdmi->hpd_regs[i]);
if (ret) {
-   dev_err(dev->dev, "failed to enable hpd regulator: %s 
(%d)\n",
+   dev_err(dev, "failed to enable hpd regulator: %s 
(%d)\n",
config->hpd_reg_names[i], ret);
  

[PATCH v3 0/2] drm/msm/hdmi: Use pinctrl in HDMI driver

[Stephane Viau]

Pinctrl support for HDMI needs a small fix before the actual implementation...

Stephane Viau (2):
  drm/msm/hdmi: Point to the right struct device
  drm/msm/hdmi: Use pinctrl in HDMI driver

 Documentation/devicetree/bindings/drm/msm/hdmi.txt |  6 +++
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c  | 43 ++
 2 files changed, 33 insertions(+), 16 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm/mdp: Add support for more 32-bit RGB formats

[Stephane Viau]

That will complete the lists of Alpha + RGB formats.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp_format.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c 
b/drivers/gpu/drm/msm/mdp/mdp_format.c
index f683433..7b0524d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -96,6 +96,12 @@ static const struct mdp_format formats[] = {
/*  name  a  r  g  b   e0 e1 e2 e3  alpha   tight  cpp cnt ... */
FMT(ARGB, 8, 8, 8, 8,  1, 0, 2, 3,  true,   true,  4,  4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   FMT(ABGR, 8, 8, 8, 8,  2, 0, 1, 3,  true,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   FMT(RGBA, 8, 8, 8, 8,  3, 1, 0, 2,  true,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
+   FMT(BGRA, 8, 8, 8, 8,  3, 2, 0, 1,  true,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(XRGB, 8, 8, 8, 8,  1, 0, 2, 3,  false,  true,  4,  4,
MDP_PLANE_INTERLEAVED, CHROMA_RGB),
FMT(RGB888,   0, 8, 8, 8,  1, 0, 2, 0,  false,  true,  3,  3,
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2] drm/msm/hdmi: Use pinctrl in HDMI driver

[Stephane Viau]

Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.

Signed-off-by: Stephane Viau 
---
v2:
- Add devicetree binding documentation for pinctrl property  [Ivan]
- Use pinctrl framework's PINCTRL_STATE_DEFAULT/SLEEP states [Ivan]
- Fix a couple of checkpatch warnings

 Documentation/devicetree/bindings/drm/msm/hdmi.txt |  6 +
 drivers/gpu/drm/msm/hdmi/hdmi.c| 27 +++
 drivers/gpu/drm/msm/hdmi/hdmi.h|  5 
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c  | 31 ++
 4 files changed, 69 insertions(+)

diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt 
b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
index a29a55f..01ff7c6 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -20,6 +20,9 @@ Required properties:
 Optional properties:
 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
+- pinctrl-names: the pin control state names; should contain "default"
+- pinctrl-0: the default pinctrl state (active)
+- pinctrl-n: the "sleep" pinctrl state (n == 1) and others

 Example:

@@ -44,5 +47,8 @@ Example:
qcom,hdmi-tx-hpd = < 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <_hdmi_mvs>;
hdmi-mux-supply = <_3p3v>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_active  _active  _active>;
+   pinctrl-1 = <_suspend _suspend _suspend>;
};
 };
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 8145362..1197086 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -354,6 +354,20 @@ static int get_gpio(struct device *dev, struct device_node 
*of_node, const char
}
return gpio;
 }
+
+static struct pinctrl_state *get_pinctrl_state(struct device *dev,
+   struct pinctrl *pinctrl, const char *name)
+{
+   struct pinctrl_state *state = pinctrl_lookup_state(pinctrl, name);
+
+   if (IS_ERR_OR_NULL(state)) {
+   dev_err(dev, "failed to get pinctrl state \"%s\" (%ld)",
+   name, PTR_ERR(state));
+   return NULL;
+   }
+
+   return state;
+}
 #endif

 static int hdmi_bind(struct device *dev, struct device *master, void *data)
@@ -365,6 +379,7 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
 #ifdef CONFIG_OF
struct device_node *of_node = dev->of_node;
const struct of_device_id *match;
+   struct pinctrl *pinctrl;

match = of_match_node(dt_match, of_node);
if (match && match->data) {
@@ -383,6 +398,18 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
hdmi_cfg->mux_sel_gpio  = get_gpio(dev, of_node, 
"qcom,hdmi-tx-mux-sel");
hdmi_cfg->mux_lpm_gpio  = get_gpio(dev, of_node, 
"qcom,hdmi-tx-mux-lpm");

+   /* not all targets have pinctrl, do not fail in case of error: */
+   pinctrl = devm_pinctrl_get(dev);
+   if (IS_ERR_OR_NULL(pinctrl)) {
+   dev_warn(dev, "cannot get pinctrl: %s\n", of_node->name);
+   } else {
+   hdmi_cfg->active  = get_pinctrl_state(dev, pinctrl,
+ PINCTRL_STATE_DEFAULT);
+   hdmi_cfg->sleep   = get_pinctrl_state(dev, pinctrl,
+ PINCTRL_STATE_SLEEP);
+   hdmi_cfg->pinctrl = pinctrl;
+   DBG("pinctrl initialized.");
+   }
 #else
static struct hdmi_platform_config config = {};
static const char *hpd_clk_names[] = {
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index a155c4a..4742df2 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "msm_drv.h"
@@ -95,6 +96,10 @@ struct hdmi_platform_config {
/* gpio's: */
int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio;
int mux_lpm_gpio;
+
+   /* pinctrl: */
+   struct pinctrl *pinctrl;
+   struct pinctrl_state *active, *sleep;
 };

 void hdmi_set_mode(struct hdmi *hdmi, bool power_on);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 914bf95..cbffb8a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -181,6 +181,23 @@ error1:
return ret;
 }

+static int pinctrl_config(stru

[PATCH] drm/msm/hdmi: Use pinctrl in HDMI driver

[Stephane Viau]

Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c   | 25 +
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  5 +
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 31 +++
 3 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 8145362..6120666 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -354,6 +354,20 @@ static int get_gpio(struct device *dev, struct device_node 
*of_node, const char
}
return gpio;
 }
+
+static struct pinctrl_state *get_pinctrl_state(struct device *dev,
+   struct pinctrl *pinctrl, const char *name)
+{
+   struct pinctrl_state *state = pinctrl_lookup_state(pinctrl, name);
+
+   if (IS_ERR_OR_NULL(state)) {
+   dev_err(dev, "failed to get pinctrl state \"%s\" (%ld)",
+   name, PTR_ERR(state));
+   return NULL;
+   }
+
+   return state;
+}
 #endif

 static int hdmi_bind(struct device *dev, struct device *master, void *data)
@@ -365,6 +379,7 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
 #ifdef CONFIG_OF
struct device_node *of_node = dev->of_node;
const struct of_device_id *match;
+   struct pinctrl *pinctrl;

match = of_match_node(dt_match, of_node);
if (match && match->data) {
@@ -383,6 +398,16 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
hdmi_cfg->mux_sel_gpio  = get_gpio(dev, of_node, 
"qcom,hdmi-tx-mux-sel");
hdmi_cfg->mux_lpm_gpio  = get_gpio(dev, of_node, 
"qcom,hdmi-tx-mux-lpm");

+   /* not all targets have pinctrl, do not fail in case of error: */
+   pinctrl = devm_pinctrl_get(dev);
+   if (IS_ERR_OR_NULL(pinctrl)) {
+   dev_warn(dev, "cannot get pinctrl: %s\n", of_node->name);
+   } else {
+   hdmi_cfg->active  = get_pinctrl_state(dev, pinctrl, 
"hdmi_active");
+   hdmi_cfg->sleep   = get_pinctrl_state(dev, pinctrl, 
"hdmi_sleep");
+   hdmi_cfg->pinctrl = pinctrl;
+   DBG("pinctrl initialized.");
+   }
 #else
static struct hdmi_platform_config config = {};
static const char *hpd_clk_names[] = {
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index a155c4a..4742df2 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "msm_drv.h"
@@ -95,6 +96,10 @@ struct hdmi_platform_config {
/* gpio's: */
int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio;
int mux_lpm_gpio;
+
+   /* pinctrl: */
+   struct pinctrl *pinctrl;
+   struct pinctrl_state *active, *sleep;
 };

 void hdmi_set_mode(struct hdmi *hdmi, bool power_on);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 914bf95..6bbda54 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -181,6 +181,23 @@ error1:
return ret;
 }

+static int pinctrl_config(struct hdmi *hdmi, bool on)
+{
+   struct drm_device *dev = hdmi->dev;
+   const struct hdmi_platform_config *config = hdmi->config;
+   struct pinctrl_state *state = on ? config->active : config->sleep;
+   int ret;
+
+   ret = pinctrl_select_state(config->pinctrl, state);
+   if (ret)
+   dev_err(dev->dev, "failed to set pinctrl state to %s: %d\n",
+   on ? "active" : "sleep", ret);
+
+   DBG("pinctrl %s", on ? "on" : "off");
+
+   return ret;
+}
+
 static int hpd_enable(struct hdmi_connector *hdmi_connector)
 {
struct hdmi *hdmi = hdmi_connector->hdmi;
@@ -199,6 +216,14 @@ static int hpd_enable(struct hdmi_connector 
*hdmi_connector)
}
}

+   if (config->pinctrl) {
+   ret = pinctrl_config(hdmi, true);
+   if (ret) {
+   dev_err(dev->dev, "can't configure pinctrl: %d\n", ret);
+   goto fail;
+   }
+   }
+
ret = gpio_config(hdmi, true);
if (ret) {
dev_err(dev->dev, "failed to configure GPIOs: %d\n", ret);
@@ -268,6 +293,12 @@ static void hdp_disable(struct hdmi_connector 
*hdmi_connector)
if (ret)
dev_warn(dev->d

[PATCH] drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()

[Stephane Viau]

The index of ->planes[] array (3rd parameter) cannot be equal to MAX_PLANE.
This looks like a typo that is now fixed.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 18a3d20..57b8f56 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -273,7 +273,7 @@ static void set_scanout_locked(struct drm_plane *plane,
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
msm_framebuffer_iova(fb, mdp5_kms->id, 2));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
-   msm_framebuffer_iova(fb, mdp5_kms->id, 4));
+   msm_framebuffer_iova(fb, mdp5_kms->id, 3));

plane->fb = fb;
 }
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm: Fix compil issue when DRM_MSM_FBDEV is disabled

[Stephane Viau]

When CONFIG_DRM_MSM_FBDEV is not defined,
CONFIG_DRM_KMS_FB_HELPER does not get selected and
drm_fb_helper_*() helper functions are thus not available.

This change fixes these link issues.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/msm_drv.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2b1218c..35380ec 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -21,9 +21,11 @@

 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
+#ifdef DRM_MSM_FBDEV
struct msm_drm_private *priv = dev->dev_private;
if (priv->fbdev)
drm_fb_helper_hotplug_event(priv->fbdev);
+#endif
 }

 static const struct drm_mode_config_funcs mode_config_funcs = {
@@ -419,9 +421,11 @@ static void msm_preclose(struct drm_device *dev, struct 
drm_file *file)

 static void msm_lastclose(struct drm_device *dev)
 {
+#ifdef DRM_MSM_FBDEV
struct msm_drm_private *priv = dev->dev_private;
if (priv->fbdev)
drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
+#endif
 }

 static irqreturn_t msm_irq(int irq, void *arg)
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm: fix unbalanced DRM framebuffer init/destroy

[Stephane Viau]

When msm_framebuffer_init() fails before calling drm_framebuffer_init(),
drm_framebuffer_cleanup() [called in msm_framebuffer_destroy()]
is still being called even though drm_framebuffer_init() was not
called for that buffer. Thus a NULL pointer derefencing:

[  247.529691] Unable to handle kernel NULL pointer dereference at virtual 
address 027c
...
[  247.563996] PC is at __mutex_lock_slowpath+0x94/0x3a8
...
[  247.823025] [] (__mutex_lock_slowpath) from [] 
(mutex_lock+0x20/0x3c)
[  247.831186] [] (mutex_lock) from [] 
(drm_framebuffer_cleanup+0x18/0x38)
[  247.839520] [] (drm_framebuffer_cleanup) from [] 
(msm_framebuffer_destroy+0x48/0x100)
[  247.849066] [] (msm_framebuffer_destroy) from [] 
(msm_framebuffer_init+0x1e8/0x228)
[  247.858439] [] (msm_framebuffer_init) from [] 
(msm_framebuffer_create+0x70/0x134)
[  247.867642] [] (msm_framebuffer_create) from [] 
(internal_framebuffer_create+0x67c/0x7b4)
[  247.877537] [] (internal_framebuffer_create) from [] 
(drm_mode_addfb2+0x20/0x98)
[  247.886650] [] (drm_mode_addfb2) from [] 
(drm_ioctl+0x240/0x420)
[  247.894378] [] (drm_ioctl) from [] 
(do_vfs_ioctl+0x4e4/0x5a4)
...

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/msm_fb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index 6b573e6..c0f09d3 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -239,8 +239,7 @@ struct drm_framebuffer *msm_framebuffer_init(struct 
drm_device *dev,
return fb;

 fail:
-   if (fb)
-   msm_framebuffer_destroy(fb);
+   kfree(msm_fb);

return ERR_PTR(ret);
 }
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: Add 28nm PLL register description

[Stephane Viau]

Each interface (DSI/eDP/HDMI) has to control its own PLL.
This change only add the register description for each one of them.

Let's not make the register description common as some registers
may not be implemented the same way for each interface PHY.

Signed-off-by: Stephane Viau 
---
 rnndb/dsi/dsi.xml   | 66 +
 rnndb/edp/edp.xml   | 51 +
 rnndb/hdmi/hdmi.xml | 51 +
 3 files changed, 168 insertions(+)

diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 480ec46..ce6085a 100644
--- a/rnndb/dsi/dsi.xml
+++ b/rnndb/dsi/dsi.xml
@@ -442,4 +442,70 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
 
diff --git a/rnndb/edp/edp.xml b/rnndb/edp/edp.xml
index ea2a74b..00fc611 100644
--- a/rnndb/edp/edp.xml
+++ b/rnndb/edp/edp.xml
@@ -185,4 +185,55 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
 
diff --git a/rnndb/hdmi/hdmi.xml b/rnndb/hdmi/hdmi.xml
index 9ac5e00..d3336a9 100644
--- a/rnndb/hdmi/hdmi.xml
+++ b/rnndb/hdmi/hdmi.xml
@@ -640,4 +640,55 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+
+
 
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm: Update generated headers (PLL registers)

[Stephane Viau]

This change includes the generated file of the following:

rnndb: Add 28nm PLL register description

Each interface (DSI/eDP/HDMI) has to control its own PLL.
This change only add the register description for each one of them.

Let's not make the register description common as some registers
may not be implemented the same way for each interface PHY.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/dsi/dsi.xml.h   | 118 +++-
 drivers/gpu/drm/msm/edp/edp.xml.h   | 104 +++
 drivers/gpu/drm/msm/hdmi/hdmi.xml.h |  99 ++
 3 files changed, 295 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h 
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 1dcfae2..aa63952 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -8,8 +8,8 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml (  18681 
bytes, from 2015-03-04 23:08:31)
-- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml (   1453 
bytes, from 2015-01-28 21:43:22)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/dsi/dsi.xml (  
21462 bytes, from 2015-04-30 16:36:31)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2015-04-30 16:26:30)

 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -835,5 +835,119 @@ static inline uint32_t 
DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)

 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x0018

+#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG
0x
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG  0x0004
+
+#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG   0x0008
+
+#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG
0x000c
+
+#define REG_DSI_28nm_PHY_PLL_VREG_CFG  0x0010
+
+#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG
0x0014
+
+#define REG_DSI_28nm_PHY_PLL_DMUX_CFG  0x0018
+
+#define REG_DSI_28nm_PHY_PLL_AMUX_CFG  0x001c
+
+#define REG_DSI_28nm_PHY_PLL_GLB_CFG   0x0020
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B   0x0001
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B   0x0002
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B0x0004
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE0x0008
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG  0x0024
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG  0x0028
+
+#define REG_DSI_28nm_PHY_PLL_LPFR_CFG  0x002c
+
+#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x0030
+
+#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x0034
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG0  0x0038
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG1  0x003c
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG2  0x0040
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG3  0x0044
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG4  0x0048
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG0  0x004c
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG1  0x0050
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG2  0x0054
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG3  0x0058
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0
0x005c
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1
0x0060
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2
0x0064
+
+#define REG_DSI_28nm_PHY_PLL_TEST_CFG  0x0068
+#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x0001
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG0  0x006c
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG1  0x0070
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG2  0x0074
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG3  0x0078
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG4  0x007c
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG5  0x0080
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG6  0x0084
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG7  0x0088
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG8  0x008c
+
+#define

[PATCH] drm/msm/mdp5: Fix iteration on INTF config array

[Stephane Viau]

The current iteration in get_dsi_id_from_intf() is wrong:
instead of iterating until hw_cfg->intf.count, we need to iterate 
until MDP5_INTF_NUM_MAX here.

Let's take the example of msm8x16:

 hw_cfg->intf.count = 1
 intfs[0] = INTF_Disabled
 intfs[1] = INTF_DSI

If we stop iterating once i reaches hw_cfg->intf.count (== 1),
we will miss the test for intfs[1].

Actually, this hw_cfg->intf.count entry is quite confusing and is not
(or *should not be*) used anywhere else; let's remove it.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 34 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  9 ++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 12 ++--
 3 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 8bcd177..9ff25a3 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -72,14 +72,13 @@ const struct mdp5_cfg_hw msm8x74_config = {
.base = { 0x12d00, 0x12e00, 0x12f00 },
},
.intf = {
-   .count = 4,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
-   },
-   .intfs = {
-   [0] = INTF_eDP,
-   [1] = INTF_DSI,
-   [2] = INTF_DSI,
-   [3] = INTF_HDMI,
+   .connect = {
+   [0] = INTF_eDP,
+   [1] = INTF_DSI,
+   [2] = INTF_DSI,
+   [3] = INTF_HDMI,
+   },
},
.max_clk = 2,
 };
@@ -142,14 +141,13 @@ const struct mdp5_cfg_hw apq8084_config = {
.base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
},
.intf = {
-   .count = 5,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
-   },
-   .intfs = {
-   [0] = INTF_eDP,
-   [1] = INTF_DSI,
-   [2] = INTF_DSI,
-   [3] = INTF_HDMI,
+   .connect = {
+   [0] = INTF_eDP,
+   [1] = INTF_DSI,
+   [2] = INTF_DSI,
+   [3] = INTF_HDMI,
+   },
},
.max_clk = 32000,
 };
@@ -196,10 +194,12 @@ const struct mdp5_cfg_hw msm8x16_config = {

},
.intf = {
-   .count = 1, /* INTF_1 */
-   .base = { 0x6B800 },
+   .base = { 0x0, 0x6b800 },
+   .connect = {
+   [0] = INTF_DISABLED,
+   [1] = INTF_DSI,
+   },
},
-   /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
.max_clk = 32000,
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 3a551b0..69349ab 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -59,6 +59,11 @@ struct mdp5_smp_block {

 #define MDP5_INTF_NUM_MAX  5

+struct mdp5_intf_block {
+   uint32_t base[MAX_BASES];
+   u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
+};
+
 struct mdp5_cfg_hw {
char  *name;

@@ -72,9 +77,7 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block dspp;
struct mdp5_sub_block ad;
struct mdp5_sub_block pp;
-   struct mdp5_sub_block intf;
-
-   u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
+   struct mdp5_intf_block intf;

uint32_t max_clk;
 };
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 02ef86b..f6c5896 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -208,8 +208,8 @@ static struct drm_encoder *construct_encoder(struct 
mdp5_kms *mdp5_kms,

 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
 {
-   const int intf_cnt = hw_cfg->intf.count;
-   const u32 *intfs = hw_cfg->intfs;
+   const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
+   const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
int id = 0, i;

for (i = 0; i < intf_cnt; i++) {
@@ -230,7 +230,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int 
intf_num)
struct msm_drm_private *priv = dev->dev_private;
const struct mdp5_cfg_hw *hw_cfg =
mdp5_cfg_get_hw_config(mdp5_kms->cfg);
-   enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num];
+   enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
struct drm_encoder *encoder;
int ret = 0;

@@ -367,7 +367,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
/* Construct encoders and modeset initialize connector devices
 * for each external display interface.
 */
-   f

[PATCH] drm/msm/dsi: Fix a couple more 64-bit build warnings

[Stephane Viau]

Avoid such errors at compilation time:
format '%d' expects argument of type 'int', but argument 3 has type 
'size_t'

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index fdc54e3..1e3cd30 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1023,7 +1023,7 @@ static int dsi_short_read1_resp(u8 *buf, const struct 
mipi_dsi_msg *msg)
*data = buf[1]; /* strip out dcs type */
return 1;
} else {
-   pr_err("%s: read data does not match with rx_buf len %d\n",
+   pr_err("%s: read data does not match with rx_buf len %zu\n",
__func__, msg->rx_len);
return -EINVAL;
}
@@ -1040,7 +1040,7 @@ static int dsi_short_read2_resp(u8 *buf, const struct 
mipi_dsi_msg *msg)
data[1] = buf[2];
return 2;
} else {
-   pr_err("%s: read data does not match with rx_buf len %d\n",
+   pr_err("%s: read data does not match with rx_buf len %zu\n",
__func__, msg->rx_len);
return -EINVAL;
}
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16

[Stephane Viau]

This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.

Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI connectors.

v2: add CTL flush register's hardware mask [pointed by Archit]

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 52 -
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 96ea6dd..3d963cc 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -150,10 +150,60 @@ const struct mdp5_cfg_hw apq8084_config = {
.max_clk = 32000,
 };

+const struct mdp5_cfg_hw msm8x16_config = {
+   .name = "msm8x16",
+   .mdp = {
+   .count = 1,
+   .base = { 0x01000 },
+   },
+   .smp = {
+   .mmb_count = 8,
+   .mmb_size = 8192,
+   .clients = {
+   [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
+   [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
+   },
+   },
+   .ctl = {
+   .count = 5,
+   .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
+   .flush_hw_mask = 0x4003,
+   },
+   .pipe_vig = {
+   .count = 1,
+   .base = { 0x05000 },
+   },
+   .pipe_rgb = {
+   .count = 2,
+   .base = { 0x15000, 0x17000 },
+   },
+   .pipe_dma = {
+   .count = 1,
+   .base = { 0x25000 },
+   },
+   .lm = {
+   .count = 2, /* LM0 and LM3 */
+   .base = { 0x45000, 0x48000 },
+   .nb_stages = 5,
+   },
+   .dspp = {
+   .count = 1,
+   .base = { 0x55000 },
+
+   },
+   .intf = {
+   .count = 1, /* INTF_1 */
+   .base = { 0x6B800 },
+   },
+   /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
+   .max_clk = 32000,
+};
+
 static const struct mdp5_cfg_handler cfg_handlers[] = {
{ .revision = 0, .config = { .hw = _config } },
{ .revision = 2, .config = { .hw = _config } },
{ .revision = 3, .config = { .hw = _config } },
+   { .revision = 6, .config = { .hw = _config } },
 };


-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 4/5] drm/msm/mdp5: Get SMP client list from mdp5_cfg

[Stephane Viau]

SMP blocks are configured for specific client IDs (ports).
These client IDs can be different from one chip to another for a
given pipe.

e.g.: DMA0 pipe fetch Y component is connected to:
 - port #10 for MDP5 v1.3
 - port #4 for MDP5 v1.6

In order to be compatible for upcoming versions of MDP5, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 20 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 44 ++---
 3 files changed, 41 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index f786c70..96ea6dd 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -31,6 +31,11 @@ const struct mdp5_cfg_hw msm8x74_config = {
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
+   .clients = {
+   [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
+   [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
+   [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
+   },
},
.ctl = {
.count = 5,
@@ -86,11 +91,18 @@ const struct mdp5_cfg_hw apq8084_config = {
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
+   .clients = {
+   [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
+   [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
+   [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
+   [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
+   [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
+   },
.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
-   .reserved[CID_RGB0] = 2,
-   .reserved[CID_RGB1] = 2,
-   .reserved[CID_RGB2] = 2,
-   .reserved[CID_RGB3] = 2,
+   .reserved = {
+   /* Two SMP blocks are statically tied to RGB pipes: */
+   [16] = 2, [17] = 2, [18] = 2, [22] = 2,
+   },
},
.ctl = {
.count = 5,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 11f3e86..3a551b0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -52,6 +52,7 @@ struct mdp5_ctl_block {
 struct mdp5_smp_block {
int mmb_count;  /* number of SMP MMBs */
int mmb_size;   /* MMB: size in bytes */
+   uint32_t clients[MAX_CLIENTS];  /* SMP port allocation /pipe */
mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 361c064..16702ae 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -74,7 +74,7 @@ struct mdp5_smp {
spinlock_t state_lock;
mdp5_smp_state_t state; /* to track smp allocation amongst pipes: */

-   struct mdp5_client_smp_state client_state[CID_MAX];
+   struct mdp5_client_smp_state client_state[MAX_CLIENTS];
 };

 static inline
@@ -85,27 +85,31 @@ struct mdp5_kms *get_kms(struct mdp5_smp *smp)
return to_mdp5_kms(to_mdp_kms(priv->kms));
 }

-static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane)
+static inline u32 pipe2client(enum mdp5_pipe pipe, int plane)
 {
-   WARN_ON(plane >= pipe2nclients(pipe));
-   switch (pipe) {
-   case SSPP_VIG0: return CID_VIG0_Y + plane;
-   case SSPP_VIG1: return CID_VIG1_Y + plane;
-   case SSPP_VIG2: return CID_VIG2_Y + plane;
-   case SSPP_RGB0: return CID_RGB0;
-   case SSPP_RGB1: return CID_RGB1;
-   case SSPP_RGB2: return CID_RGB2;
-   case SSPP_DMA0: return CID_DMA0_Y + plane;
-   case SSPP_DMA1: return CID_DMA1_Y + plane;
-   case SSPP_VIG3: return CID_VIG3_Y + plane;
-   case SSPP_RGB3: return CID_RGB3;
-   default:return CID_UNUSED;
-   }
+#define CID_UNUSED 0
+
+   if (WARN_ON(plane >= pipe2nclients(pipe)))
+   return CID_UNUSED;
+
+   /*
+* Note on SMP clients:
+* For ViG pipes, fetch Y/Cr/Cb-components clients are always
+* consecutive, and in that order.
+*
+* e.g.:
+* if mdp5_cfg->smp.clients[SSPP_VIG0] = N,
+*  Y  plane's client ID is N
+*  Cr plane's client ID is N + 1
+*  Cb plane's client ID is N + 2
+*/
+
+   return mdp5_cfg->smp.clients[pipe] + plane;
 }

 /* step #1: update # of blocks pending for the client:

[PATCH v2 3/5] drm/msm/mdp5: Update headers (remove enum mdp5_client_id)

[Stephane Viau]

This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 41 ++---
 1 file changed, 7 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index cb931ca..b4e2624 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
29843 bytes, from 2015-03-09 12:32:38)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
28872 bytes, from 2015-03-09 12:40:51)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -97,33 +97,6 @@ enum mdp5_pipe_bwc {
BWC_Q_MED = 2,
 };

-enum mdp5_client_id {
-   CID_UNUSED = 0,
-   CID_VIG0_Y = 1,
-   CID_VIG0_CR = 2,
-   CID_VIG0_CB = 3,
-   CID_VIG1_Y = 4,
-   CID_VIG1_CR = 5,
-   CID_VIG1_CB = 6,
-   CID_VIG2_Y = 7,
-   CID_VIG2_CR = 8,
-   CID_VIG2_CB = 9,
-   CID_DMA0_Y = 10,
-   CID_DMA0_CR = 11,
-   CID_DMA0_CB = 12,
-   CID_DMA1_Y = 13,
-   CID_DMA1_CR = 14,
-   CID_DMA1_CB = 15,
-   CID_RGB0 = 16,
-   CID_RGB1 = 17,
-   CID_RGB2 = 18,
-   CID_VIG3_Y = 19,
-   CID_VIG3_CR = 20,
-   CID_VIG3_CB = 21,
-   CID_RGB3 = 22,
-   CID_MAX = 23,
-};
-
 enum mdp5_cursor_format {
CURSOR_FMT_ARGB = 0,
CURSOR_FMT_ARGB1555 = 2,
@@ -276,19 +249,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t 
i0, uint32_t i1) { retu
 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) 
{ return 0x0080 + __offset_MDP(i0) + 0x4*i1; }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0xff00
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
 }
@@ -298,19 +271,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t 
i0, uint32_t i1) { retu
 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) 
{ return 0x0130 + __offset_MDP(i0) + 0x4*i1; }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0xff00
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
 }
-- 
Qualcomm Inn

[PATCH v2 2/5] drm/msm/mdp5: Separate MDP5 domain from MDSS domain

[Stephane Viau]

MDP block is actually contained inside the MDSS block. For some
chipsets, the base address of the MDP registers is different from the
current (assumed) 0x100 offset.

Like CTL and LM blocks, this changes introduce a dynamic offset
for the MDP instance, which can be found out at runtime, once the
MDSS HW version is read.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  8 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 20 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 26 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  9 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 20 ++--
 7 files changed, 48 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 6c467fb..f786c70 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -24,6 +24,10 @@ const struct mdp5_cfg_hw *mdp5_cfg = NULL;

 const struct mdp5_cfg_hw msm8x74_config = {
.name = "msm8x74",
+   .mdp = {
+   .count = 1,
+   .base = { 0x00100 },
+   },
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
@@ -75,6 +79,10 @@ const struct mdp5_cfg_hw msm8x74_config = {

 const struct mdp5_cfg_hw apq8084_config = {
.name = "apq8084",
+   .mdp = {
+   .count = 1,
+   .base = { 0x00100 },
+   },
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 93bee92..11f3e86 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -61,6 +61,7 @@ struct mdp5_smp_block {
 struct mdp5_cfg_hw {
char  *name;

+   struct mdp5_sub_block mdp;
struct mdp5_smp_block smp;
struct mdp5_ctl_block ctl;
struct mdp5_sub_block pipe_vig;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 7c0adf5..0fa7fce 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -112,31 +112,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms,
u32 intf_sel;

spin_lock_irqsave(_kms->resource_lock, flags);
-   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
+   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0));

switch (intf->num) {
case 0:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type);
break;
case 1:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type);
break;
case 2:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type);
break;
case 3:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type);
break;
default:
BUG();
break;
}

-   mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
+   mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel);
spin_unlock_irqrestore(_kms->resource_lock, flags);
 }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index a940710..33bd4c6 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -23,7 +23,7 @@

 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
 {
-   mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
+   mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
 }

 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
@@ -35,8 +35,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
mdp5_enable(mdp5_kms);
-   mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0x);
- 

[PATCH v2 1/5] drm/msm/mdp5: Update headers (introduce MDP5 domain)

[Stephane Viau]

This change contains the generated header file for the following
change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain".

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 203 +++-
 1 file changed, 118 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index b4d8716..cb931ca 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27094 bytes, from 2015-01-23 16:27:31)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
29843 bytes, from 2015-03-09 12:32:38)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -174,139 +174,172 @@ enum mdp5_data_format {
 #define MDP5_IRQ_INTF2_VSYNC   0x2000
 #define MDP5_IRQ_INTF3_UNDER_RUN   0x4000
 #define MDP5_IRQ_INTF3_VSYNC   0x8000
-#define REG_MDP5_HW_VERSION0x
+#define REG_MDSS_HW_VERSION0x
+#define MDSS_HW_VERSION_STEP__MASK 0x
+#define MDSS_HW_VERSION_STEP__SHIFT0
+static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & 
MDSS_HW_VERSION_STEP__MASK;
+}
+#define MDSS_HW_VERSION_MINOR__MASK0x0fff
+#define MDSS_HW_VERSION_MINOR__SHIFT   16
+static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & 
MDSS_HW_VERSION_MINOR__MASK;
+}
+#define MDSS_HW_VERSION_MAJOR__MASK0xf000
+#define MDSS_HW_VERSION_MAJOR__SHIFT   28
+static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & 
MDSS_HW_VERSION_MAJOR__MASK;
+}
+
+#define REG_MDSS_HW_INTR_STATUS
0x0010
+#define MDSS_HW_INTR_STATUS_INTR_MDP   0x0001
+#define MDSS_HW_INTR_STATUS_INTR_DSI0  0x0010
+#define MDSS_HW_INTR_STATUS_INTR_DSI1  0x0020
+#define MDSS_HW_INTR_STATUS_INTR_HDMI  0x0100
+#define MDSS_HW_INTR_STATUS_INTR_EDP   0x1000

-#define REG_MDP5_HW_INTR_STATUS
0x0010
-#define MDP5_HW_INTR_STATUS_INTR_MDP   0x0001
-#define MDP5_HW_INTR_STATUS_INTR_DSI0  0x0010
-#define MDP5_HW_INTR_STATUS_INTR_DSI1  0x0020
-#define MDP5_HW_INTR_STATUS_INTR_HDMI  0x0100
-#define MDP5_HW_INTR_STATUS_INTR_EDP   0x1000
+static inline uint32_t __offset_MDP(uint32_t idx)
+{
+   switch (idx) {
+   case 0: return (mdp5_cfg->mdp.base[0]);
+   default: return INVALID_IDX(idx);
+   }
+}
+static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x + 
__offset_MDP(i0); }

-#define REG_MDP5_MDP_VERSION   0x0100
-#define MDP5_MDP_VERSION_MINOR__MASK   0x00ff
-#define MDP5_MDP_VERSION_MINOR__SHIFT  16
-static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
+static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 
0x + __offset_MDP(i0); }
+#define MDP5_MDP_HW_VERSION_STEP__MASK 0x
+#define MDP5_MDP_HW_VERSION_STEP__SHIFT0
+static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
+{
+   return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & 
MDP5_MDP_HW_VERSION_STEP__MASK;
+}
+#define MDP5_MDP_HW_VERSION_MINOR__MASK
0x0fff
+#define MDP5_MDP_HW_VERSION_MINOR__SHIFT   16
+static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)
 {
-   return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & 
MDP5_MDP_VERSION_MINOR__MASK;
+   return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & 
MDP5_MDP_HW_VERSION_MINOR__MASK;
 }
-#define MDP5_MDP_VERSION_MAJOR__MASK   0xf000
-#define MDP5_MDP_VERSION_MAJOR__SHIFT 

[PATCH v2 0/5] drm/msm: Add display configuration for msm8x16

[Stephane Viau]

This patch set contains a couple modifications of the MDP5 register
description, followed by the MDP hw configuration of the msm8016 and
msm8916 chipsets.

v2: add CTL flush register's hardware mask [pointed by Archit]

Stephane Viau (5):
  drm/msm/mdp5: Update headers (introduce MDP5 domain)
  drm/msm/mdp5: Separate MDP5 domain from MDSS domain
  drm/msm/mdp5: Update headers (remove enum mdp5_client_id)
  drm/msm/mdp5: Get SMP client list from mdp5_cfg
  drm/msm/mdp5: Add hardware configuration for msm8x16

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 230 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  80 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c |  20 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c |  26 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |   9 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |   2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c |  64 -
 8 files changed, 258 insertions(+), 175 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb/mdp5: Add some CTL flush bits

[Stephane Viau]

Some upcoming targets have more bits to set in CTL_FLUSH registers.

Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 8 
 1 file changed, 8 insertions(+)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 423249a..03dcc3a 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -250,11 +250,19 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



+   





+   
+   
+   
+   
+   
+   
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/2] drm/msm/mdp5: Remove CTL flush dummy bits

[Stephane Viau]

This TODO can now be removed and replaced by the previous patch
"drm/msm/mdp5: Update headers (add CTL flush bits)"

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 0fa7fce..5488b687 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -316,13 +316,6 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 
blend_cfg)

 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)
 {
-   /* these are dummy bits for now, but will appear in next chipsets: */
-#define MDP5_CTL_FLUSH_TIMING_00x8000
-#define MDP5_CTL_FLUSH_TIMING_10x4000
-#define MDP5_CTL_FLUSH_TIMING_20x2000
-#define MDP5_CTL_FLUSH_TIMING_30x1000
-#define MDP5_CTL_FLUSH_WB  0x0001
-
if (intf->type == INTF_WB)
return MDP5_CTL_FLUSH_WB;

@@ -337,10 +330,6 @@ u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)

 u32 mdp_ctl_flush_mask_cursor(int cursor_id)
 {
-   /* these are dummy bits for now, but will appear in next chipsets: */
-#define MDP5_CTL_FLUSH_CURSOR_00x0040
-#define MDP5_CTL_FLUSH_CURSOR_10x0080
-
switch (cursor_id) {
case 0: return MDP5_CTL_FLUSH_CURSOR_0;
case 1: return MDP5_CTL_FLUSH_CURSOR_1;
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 1/2] drm/msm/mdp5: Update headers (add CTL flush bits)

[Stephane Viau]

Some upcoming targets have more bits to set in CTL_FLUSH
registers.

Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index b4e2624..b9a4ded 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,9 +8,9 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
28872 bytes, from 2015-03-09 12:40:51)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
29312 bytes, from 2015-03-23 21:18:48)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-03-23 20:38:49)

 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -458,11 +458,19 @@ static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { 
return 0x0018 + __o
 #define MDP5_CTL_FLUSH_DSPP0   0x2000
 #define MDP5_CTL_FLUSH_DSPP1   0x4000
 #define MDP5_CTL_FLUSH_DSPP2   0x8000
+#define MDP5_CTL_FLUSH_WB  0x0001
 #define MDP5_CTL_FLUSH_CTL 0x0002
 #define MDP5_CTL_FLUSH_VIG30x0004
 #define MDP5_CTL_FLUSH_RGB30x0008
 #define MDP5_CTL_FLUSH_LM5 0x0010
 #define MDP5_CTL_FLUSH_DSPP3   0x0020
+#define MDP5_CTL_FLUSH_CURSOR_0
0x0040
+#define MDP5_CTL_FLUSH_CURSOR_1
0x0080
+#define MDP5_CTL_FLUSH_CHROMADOWN_00x0400
+#define MDP5_CTL_FLUSH_TIMING_3
0x1000
+#define MDP5_CTL_FLUSH_TIMING_2
0x2000
+#define MDP5_CTL_FLUSH_TIMING_1
0x4000
+#define MDP5_CTL_FLUSH_TIMING_0
0x8000

 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x001c + 
__offset_CTL(i0); }

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 0/2] Implement CTL flush dummy bits

[Stephane Viau]

This patchset proposes in a couple of changes (separate generated header)
to remove the temporary defined symbols in the code and place them into
the generated header file.

Stephane Viau (2):
  drm/msm/mdp5: Update headers (add CTL flush bits)
  drm/msm/mdp5: Remove CTL flush dummy bits

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 12 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 ---
 2 files changed, 10 insertions(+), 13 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v3 4/4] drm/msm/mdp5: Make the intf connection in config module

[Stephane Viau]

Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   8 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   4 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 112 ++--
 3 files changed, 75 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 72c075a..8bee023 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -62,6 +62,10 @@ const struct mdp5_cfg_hw msm8x74_config = {
.count = 4,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 2,
 };

@@ -111,6 +115,10 @@ const struct mdp5_cfg_hw apq8084_config = {
.count = 5,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 32000,
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 69e35ac..12224d7 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -56,6 +56,8 @@ struct mdp5_smp_block {
int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };

+#define MDP5_INTF_NUM_MAX  5
+
 struct mdp5_cfg_hw {
char  *name;

@@ -69,6 +71,8 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block ad;
struct mdp5_sub_block intf;

+   u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
+
uint32_t max_clk;
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 390d9d2..7e03af5 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -161,6 +161,44 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
return 0;
 }

+static int construct_encoder(struct mdp5_kms *mdp5_kms,
+   enum mdp5_intf_type intf_type, int intf_num)
+{
+   struct drm_device *dev = mdp5_kms->dev;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct drm_encoder *encoder;
+   struct mdp5_interface intf = {
+   .num= intf_num,
+   .type   = intf_type,
+   .mode   = MDP5_INTF_MODE_NONE,
+   };
+   int ret = 0;
+
+   encoder = mdp5_encoder_init(dev, );
+   if (IS_ERR(encoder)) {
+   ret = PTR_ERR(encoder);
+   dev_err(dev->dev, "failed to construct encoder: %d\n", ret);
+   return ret;
+   }
+
+   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
+   priv->encoders[priv->num_encoders++] = encoder;
+
+   if (intf_type == INTF_HDMI) {
+   ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init HDMI: %d\n", ret);
+
+   } else if (intf_type == INTF_eDP) {
+   /* Construct bridge/connector for eDP: */
+   ret = msm_edp_modeset_init(priv->edp, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init eDP: %d\n", ret);
+   }
+
+   return ret;
+}
+
 static int modeset_init(struct mdp5_kms *mdp5_kms)
 {
static const enum mdp5_pipe crtcs[] = {
@@ -171,7 +209,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
};
struct drm_device *dev = mdp5_kms->dev;
struct msm_drm_private *priv = dev->dev_private;
-   struct drm_encoder *encoder;
const struct mdp5_cfg_hw *hw_cfg;
int i, ret;

@@ -222,56 +259,29 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
}
}

-   if (priv->hdmi) {
-   struct mdp5_interface intf = {
-   .num= 3,
-   .type   = INTF_HDMI,
-   .mode   = MDP5_INTF_MODE_NONE,
-   };
-
-   /* Construct encoder for HDMI: */
-   encoder = mdp5_encoder_init(dev, );
-   if (IS_ERR(encoder)) {
-   dev_err(dev->dev, "failed to construct encoder\n");
-   ret = PTR_ERR(encoder);
-   goto fail;
-   }
-
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
-   priv->encoders[priv->num_encode

[PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines

[Stephane Viau]

Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of the pipeline
status (eg: whether pipeline registers are flushed AND output WB
buffers are ready, in case of WB interface).

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  31 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  72 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |   1 +
 7 files changed, 276 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index c078f30..72c075a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x0003,
},
.pipe_vig = {
.count = 3,
@@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x003f,
},
.pipe_vig = {
.count = 4,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 4e90740..69e35ac 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -44,6 +44,11 @@ struct mdp5_lm_block {
uint32_t nb_stages; /* number of stages per blender */
 };

+struct mdp5_ctl_block {
+   MDP5_SUB_BLOCK_DEFINITION;
+   uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
+};
+
 struct mdp5_smp_block {
int mmb_count;  /* number of SMP MMBs */
int mmb_size;   /* MMB: size in bytes */
@@ -55,7 +60,7 @@ struct mdp5_cfg_hw {
char  *name;

struct mdp5_smp_block smp;
-   struct mdp5_sub_block ctl;
+   struct mdp5_ctl_block ctl;
struct mdp5_sub_block pipe_vig;
struct mdp5_sub_block pipe_rgb;
struct mdp5_sub_block pipe_dma;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 15136f1..9527ad1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -82,8 +82,6 @@ static void request_pending(struct drm_crtc *crtc, uint32_t 
pending)
mdp_irq_register(_kms(crtc)->base, _crtc->vblank);
 }

-#define mdp5_lm_get_flush(lm)  mdp_ctl_flush_mask_lm(lm)
-
 static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
@@ -110,8 +108,8 @@ static void crtc_flush_all(struct drm_crtc *crtc)
drm_atomic_crtc_for_each_plane(plane, crtc) {
flush_mask |= mdp5_plane_get_flush(plane);
}
-   flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
-   flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
+
+   flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);

crtc_flush(crtc, flush_mask);
 }
@@ -442,13 +440,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   struct drm_gem_object *cursor_bo, *old_bo;
+   struct drm_gem_object *cursor_bo, *old_bo = NULL;
uint32_t blendcfg, cursor_addr, stride;
int ret, bpp, lm;
unsigned int depth;
enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w, roi_h;
+   bool cursor_enable = true;
unsigned long flags;

if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
@@ -461,7 +460,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

if (!handle) {
DBG("Cursor off");
-   return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false);
+   cursor_enable = false;
+   goto set_cursor;
}

cursor_bo = drm_gem_object_lookup(dev, file, handle);
@@ -502,11 +502,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

spin_unlock_irqrestore(_crtc->cursor.lock, flags);

-   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true);
-   if (ret)
+set_cursor:
+   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
+   if (ret) {
+   dev_err(dev->dev, "failed to %sable cursor: %d\n",

[PATCH v3 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration

[Stephane Viau]

DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().

For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for DSI.

This change takes care of configuring the whole pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  4 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39 ++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 91 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  3 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 29 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 16 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 48 ---
 7 files changed, 159 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index dba4d52..4e90740 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -84,6 +84,10 @@ const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct 
mdp5_cfg_handler *cfg_hn
 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);

+#define mdp5_cfg_intf_is_virtual(intf_type) ({ \
+   typeof(intf_type) __val = (intf_type);  \
+   (__val) >= INTF_VIRTUAL ? true : false; })
+
 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
uint32_t major, uint32_t minor);
 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index bfba236..15136f1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -611,48 +611,17 @@ void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, 
struct drm_file *file)
 }

 /* set interface for routing crtc->encoder: */
-void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
-   enum mdp5_intf intf_id)
+void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   uint32_t intf_sel;
-   unsigned long flags;
+   int lm = mdp5_crtc_get_lm(crtc);

/* now that we know what irq's we want: */
-   mdp5_crtc->err.irqmask = intf2err(intf);
-   mdp5_crtc->vblank.irqmask = intf2vblank(intf);
+   mdp5_crtc->err.irqmask = intf2err(intf->num);
+   mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
mdp_irq_update(_kms->base);

-   spin_lock_irqsave(_kms->resource_lock, flags);
-   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
-
-   switch (intf) {
-   case 0:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id);
-   break;
-   case 1:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id);
-   break;
-   case 2:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id);
-   break;
-   case 3:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id);
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
-   spin_unlock_irqrestore(_kms->resource_lock, flags);
-
-   DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
 }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 1511290..a548113 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -33,6 +33,16 @@
  * requested by the client (in mdp5_crtc_mode_set()).
  */

+struct op_mode {
+   struct mdp5_interface intf;
+   /*
+* TODO: add a state variable to control the pipeline
+*
+* eg: WB interface needs both buffer addresses to be committed +
+* output buffers ready to be written into, before we can START.
+*/
+};
+
 struct mdp5_ctl {
struct mdp5_ctl_manager *ctlm;

@@ -41,8 +51,8 @@ struct mdp5_ctl {
/* whether this CTL has been allocated or not: */
bool busy;

-   /* memory output connection (@see mdp5_ctl_mode): */
-   u32 mode;
+   /* Operation Mode Configuration for the Pipeline */
+   struct op_mode pipeline;

/* REG_MDP5_CTL_*() registers access info + lock: */

[PATCH v3 1/4] drm/msm/mdp5: Update generated header files

[Stephane Viau]

Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
 1 file changed, 33 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index c276624..095a54c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27229 bytes, from 2015-02-10 17:00:41)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27094 bytes, from 2015-01-23 16:27:31)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -37,11 +37,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 */


-enum mdp5_intf {
+enum mdp5_intf_type {
+   INTF_DISABLED = 0,
INTF_DSI = 1,
INTF_HDMI = 3,
INTF_LCDC = 5,
INTF_eDP = 9,
+   INTF_VIRTUAL = 100,
+   INTF_WB = 101,
 };

 enum mdp5_intfnum {
@@ -67,11 +70,11 @@ enum mdp5_pipe {

 enum mdp5_ctl_mode {
MODE_NONE = 0,
-   MODE_ROT0 = 1,
-   MODE_ROT1 = 2,
-   MODE_WB0 = 3,
-   MODE_WB1 = 4,
-   MODE_WFD = 5,
+   MODE_WB_0_BLOCK = 1,
+   MODE_WB_1_BLOCK = 2,
+   MODE_WB_0_LINE = 3,
+   MODE_WB_1_LINE = 4,
+   MODE_WB_2_LINE = 5,
 };

 enum mdp5_pack_3d {
@@ -144,30 +147,25 @@ enum mdp5_data_format {
DATA_FORMAT_YUV = 1,
 };

-#define MDP5_IRQ_INTF0_WB_ROT_COMP 0x0001
-#define MDP5_IRQ_INTF1_WB_ROT_COMP 0x0002
-#define MDP5_IRQ_INTF2_WB_ROT_COMP 0x0004
-#define MDP5_IRQ_INTF3_WB_ROT_COMP 0x0008
-#define MDP5_IRQ_INTF0_WB_WFD  0x0010
-#define MDP5_IRQ_INTF1_WB_WFD  0x0020
-#define MDP5_IRQ_INTF2_WB_WFD  0x0040
-#define MDP5_IRQ_INTF3_WB_WFD  0x0080
-#define MDP5_IRQ_INTF0_PING_PONG_COMP  0x0100
-#define MDP5_IRQ_INTF1_PING_PONG_COMP  0x0200
-#define MDP5_IRQ_INTF2_PING_PONG_COMP  0x0400
-#define MDP5_IRQ_INTF3_PING_PONG_COMP  0x0800
-#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR
0x1000
-#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR
0x2000
-#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR
0x4000
-#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR
0x8000
-#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR
0x0001
-#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR
0x0002
-#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR
0x0004
-#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR
0x0008
-#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF  0x0010
-#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF  0x0020
-#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF  0x0040
-#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF  0x0080
+#define MDP5_IRQ_WB_0_DONE 0x0001
+#define MDP5_IRQ_WB_1_DONE 0x0002
+#define MDP5_IRQ_WB_2_DONE 0x0010
+#define MDP5_IRQ_PING_PONG_0_DONE  0x0100
+#define MDP5_IRQ_PING_PONG_1_DONE  0x0200
+#define MDP5_IRQ_PING_PONG_2_DONE  0x0400
+#define MDP5_IRQ_PING_PONG_3_DONE  0x0800
+#define MDP5_IRQ_PING_PONG_0_RD_PTR0x1000
+#define MDP5_IRQ_PING_PONG_1_RD_PTR0x2000
+#define MDP5_IRQ_PING_PONG_2_RD_PTR0x4000
+#define MDP5_IRQ_PING_PONG_3_RD_PTR0x8000
+#define MDP5_IRQ_PING_PONG_0_WR_PTR0x0001
+#define MDP5_IRQ_PING_PONG_1_WR_PTR0x0002
+#define MDP5_IRQ_PING_PONG_2_WR_PTR0x0004
+#define MDP5_IRQ_PING_PONG_3_WR_PTR0x0008
+#define MDP5_IRQ_PING_PONG_0_AUTO_REF  0x0010
+#define MDP5_IRQ_PING_PONG_1_AUTO_REF

[PATCH v3 0/4] drm/msm: preparation for WB/DSI connectors

[Stephane Viau]

WB and DSI support are in the pipe and will come out soon. Before that,
we need to prepare the MDP5 driver so we can support these connectors.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers

Note:
"drm/msm: Add display configuration for msm8x16" patch set depends on
"drm/msm: preparation for WB/DSI connectors" patch set.

Stephane Viau (4):
  drm/msm/mdp5: Update generated header files
  drm/msm/mdp5: Enhance operation mode for pipeline configuration
  drm/msm/mdp5: Add START signal to kick off certain pipelines
  drm/msm/mdp5: Make the intf connection in config module

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h |  68 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  10 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  15 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  70 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 326 +---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  75 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  40 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 100 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  49 -
 9 files changed, 522 insertions(+), 231 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: update generated headers

[Stephane Viau]

From: Beeresh Gopal 

To avoid ambiguity rename register
FRAME_SIZE to SSTILE_FRAME_SIZE.

Signed-off-by: Beeresh Gopal 
---
 rnndb/mdp/mdp4.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rnndb/mdp/mdp4.xml b/rnndb/mdp/mdp4.xml
index 26d1deb..a84f530 100644
--- a/rnndb/mdp/mdp4.xml
+++ b/rnndb/mdp/mdp4.xml
@@ -290,7 +290,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 2/2] drm/msm/mdp4: Support NV12MT format in mdp4

[Stephane Viau]

From: Beeresh Gopal <gbeer...@codeaurora.org>

Using fb modifier flag, support NV12MT format in MDP4.

v2:
- rework the modifier's description [Daniel Vetter's comment]
- drop .set_mode_config() callback [Rob Clark's comment]

Signed-off-by: Beeresh Gopal 
Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  2 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 22 ++
 include/uapi/drm/drm_fourcc.h |  5 +
 3 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
index d81e19d..6387881 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
@@ -119,6 +119,8 @@ static int mdp4_hw_init(struct msm_kms *kms)
if (mdp4_kms->rev > 1)
mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);

+   dev->mode_config.allow_fb_modifiers = true;
+
 out:
pm_runtime_put_sync(dev->dev);

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
index cde2500..2c2d6a5 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
@@ -33,6 +33,21 @@ struct mdp4_plane {
 };
 #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)

+/* MDP format helper functions */
+static inline
+enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb)
+{
+   bool is_tile = false;
+
+   if (fb->modifier[1] == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
+   is_tile = true;
+
+   if (fb->pixel_format == DRM_FORMAT_NV12 && is_tile)
+   return FRAME_TILE_YCBCR_420;
+
+   return FRAME_LINEAR;
+}
+
 static void mdp4_plane_set_scanout(struct drm_plane *plane,
struct drm_framebuffer *fb);
 static int mdp4_plane_mode_set(struct drm_plane *plane,
@@ -203,6 +218,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
+   enum mdp4_frame_format frame_type = mdp4_get_frame_format(fb);

if (!(crtc && fb)) {
DBG("%s: disabled!", mdp4_plane->name);
@@ -302,6 +318,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count 
- 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) 
|
+   MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
COND(format->unpack_tight, 
MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
@@ -322,6 +339,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);

+   if (frame_type != FRAME_LINEAR)
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
+   MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
+   MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
+
return 0;
 }

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 188e61f..2ff79cb 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -161,4 +161,9 @@
  * authoritative source for all of these.
  */

+/* Samsung framebuffer modifiers */
+
+/* Tiled: 64x32 pixel macroblocks */
+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+
 #endif /* DRM_FOURCC_H */
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 1/2] drm/msm: update generated headers

[Stephane Viau]

From: Beeresh Gopal 

To avoid ambiguity rename FRAME_SIZE to
SSTILE_FRAME_SIZE

Signed-off-by: Beeresh Gopal 
---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 36 +
 1 file changed, 14 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 1d39174..2d0029d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -8,19 +8,11 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml (
676 bytes, from 2014-12-05 15:34:49)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml(  
20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml(  
27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (  
11712 bytes, from 2013-08-17 17:13:43)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml(
344 bytes, from 2013-08-11 19:26:32)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml (   
1686 bytes, from 2014-10-31 16:48:57)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml (
600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml   (  
26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (   
8253 bytes, from 2014-12-08 16:13:00)
-
-Copyright (C) 2013-2014 by the following authors:
+- /local/mnt/workspace/sandbox/envytools/rnndb/mdp/mdp4.xml(  
20915 bytes, from 2015-02-06 15:25:51)
+- /local/mnt/workspace/sandbox/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2015-02-06 15:25:09)
+- /local/mnt/workspace/sandbox/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-02-06 15:25:09)
+
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)

 Permission is hereby granted, free of charge, to any person obtaining
@@ -680,18 +672,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t 
val)
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & 
MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
 }

-static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 
0x00020048 + 0x1*i0; }
-#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK  0x
-#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)
+static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { 
return 0x00020048 + 0x1*i0; }
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK   0x
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT  16
+static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
 {
-   return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & 
MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK;
+   return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & 
MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
 }
-#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK   0x
-#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT  0
-static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK
0x
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT   0
+static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
 {
-   return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & 
MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;
+   return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & 
MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
 }

 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 
0x00020050 + 0x1*i0; }
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 0/2] drm/msm: Add support for NV12MT format in mdp4

[Stephane Viau]

Resending a v2 on behalf of Beeresh with comments from Daniel and Rob
addressed.

Beeresh Gopal (2):
  drm/msm: update generated headers
  drm/msm/mdp4: Support NV12MT format in mdp4

 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h   | 36 ---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  2 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 22 +++
 include/uapi/drm/drm_fourcc.h |  5 +
 4 files changed, 43 insertions(+), 22 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/2] rnndb: Do not use enum mdp5_client_id to configure SMP

[Stephane Viau]

SMP blocks are configured for specific client IDs (ports).
These client IDs can be different from one chip to another for a
given pipe.

e.g.: DMA0 pipe fetch Y component is connected to:
 - port #10 for MDP5 v1.3
 - port #4 for MDP5 v1.6

In order to be compatible for upcoming versions of MDP5, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 34 --
 1 file changed, 4 insertions(+), 30 deletions(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index aedaa7c..423249a 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -91,33 +91,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-



@@ -160,9 +133,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
+
+   
+   
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 1/2] rnndb: Separate MDP5 domain from MDSS domain

[Stephane Viau]

MDP block is actually contained inside the MDSS block. For some
chipsets, the base address of the MDP registers is different from the
current (assumed) 0x100 offset.

Like CTL and  LM blocks, this changes introduce a dynamic offset
for the MDP instance, which can be found out at runtime, once the
MDSS HW version is read.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 123 +
 1 file changed, 67 insertions(+), 56 deletions(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index db2e15c..aedaa7c 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -9,6 +9,22 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">
 
 

+
+   
+   
+   
+   
+   
+
+   
+   
+   
+   
+   
+   
+   
+
+
 


@@ -149,64 +165,59 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
-   
-   
-   
-   
-
-   
-   
-   
-   
+   
+   
+   
+   
+   
+   
+   

-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   

-   
-   
-   
-   
-   
-   
+   
+   
+   
+   
+   
+   

-   
-  
-  
-  
- 
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
+   
+  
+  
+  
+ 
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   



@@ -224,7 +235,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">


 
-
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16

[Stephane Viau]

This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.

Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI connectors.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 51 -
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 96ea6dd..9ff7ac1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -150,10 +150,59 @@ const struct mdp5_cfg_hw apq8084_config = {
.max_clk = 32000,
 };

+const struct mdp5_cfg_hw msm8x16_config = {
+   .name = "msm8x16",
+   .mdp = {
+   .count = 1,
+   .base = { 0x01000 },
+   },
+   .smp = {
+   .mmb_count = 8,
+   .mmb_size = 8192,
+   .clients = {
+   [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
+   [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
+   },
+   },
+   .ctl = {
+   .count = 5,
+   .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
+   },
+   .pipe_vig = {
+   .count = 1,
+   .base = { 0x05000 },
+   },
+   .pipe_rgb = {
+   .count = 2,
+   .base = { 0x15000, 0x17000 },
+   },
+   .pipe_dma = {
+   .count = 1,
+   .base = { 0x25000 },
+   },
+   .lm = {
+   .count = 2, /* LM0 and LM3 */
+   .base = { 0x45000, 0x48000 },
+   .nb_stages = 5,
+   },
+   .dspp = {
+   .count = 1,
+   .base = { 0x55000 },
+
+   },
+   .intf = {
+   .count = 1, /* INTF_1 */
+   .base = { 0x6B800 },
+   },
+   /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
+   .max_clk = 32000,
+};
+
 static const struct mdp5_cfg_handler cfg_handlers[] = {
{ .revision = 0, .config = { .hw = _config } },
{ .revision = 2, .config = { .hw = _config } },
{ .revision = 3, .config = { .hw = _config } },
+   { .revision = 6, .config = { .hw = _config } },
 };


-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 4/5] drm/msm/mdp5: Get SMP client list from mdp5_cfg

[Stephane Viau]

SMP blocks are configured for specific client IDs (ports).
These client IDs can be different from one chip to another for a
given pipe.

e.g.: DMA0 pipe fetch Y component is connected to:
 - port #10 for MDP5 v1.3
 - port #4 for MDP5 v1.6

In order to be compatible for upcoming versions of MDP5, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 20 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 44 ++---
 3 files changed, 41 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index f786c70..96ea6dd 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -31,6 +31,11 @@ const struct mdp5_cfg_hw msm8x74_config = {
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
+   .clients = {
+   [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
+   [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
+   [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
+   },
},
.ctl = {
.count = 5,
@@ -86,11 +91,18 @@ const struct mdp5_cfg_hw apq8084_config = {
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
+   .clients = {
+   [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
+   [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
+   [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
+   [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
+   [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
+   },
.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
-   .reserved[CID_RGB0] = 2,
-   .reserved[CID_RGB1] = 2,
-   .reserved[CID_RGB2] = 2,
-   .reserved[CID_RGB3] = 2,
+   .reserved = {
+   /* Two SMP blocks are statically tied to RGB pipes: */
+   [16] = 2, [17] = 2, [18] = 2, [22] = 2,
+   },
},
.ctl = {
.count = 5,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 11f3e86..3a551b0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -52,6 +52,7 @@ struct mdp5_ctl_block {
 struct mdp5_smp_block {
int mmb_count;  /* number of SMP MMBs */
int mmb_size;   /* MMB: size in bytes */
+   uint32_t clients[MAX_CLIENTS];  /* SMP port allocation /pipe */
mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 361c064..16702ae 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -74,7 +74,7 @@ struct mdp5_smp {
spinlock_t state_lock;
mdp5_smp_state_t state; /* to track smp allocation amongst pipes: */

-   struct mdp5_client_smp_state client_state[CID_MAX];
+   struct mdp5_client_smp_state client_state[MAX_CLIENTS];
 };

 static inline
@@ -85,27 +85,31 @@ struct mdp5_kms *get_kms(struct mdp5_smp *smp)
return to_mdp5_kms(to_mdp_kms(priv->kms));
 }

-static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane)
+static inline u32 pipe2client(enum mdp5_pipe pipe, int plane)
 {
-   WARN_ON(plane >= pipe2nclients(pipe));
-   switch (pipe) {
-   case SSPP_VIG0: return CID_VIG0_Y + plane;
-   case SSPP_VIG1: return CID_VIG1_Y + plane;
-   case SSPP_VIG2: return CID_VIG2_Y + plane;
-   case SSPP_RGB0: return CID_RGB0;
-   case SSPP_RGB1: return CID_RGB1;
-   case SSPP_RGB2: return CID_RGB2;
-   case SSPP_DMA0: return CID_DMA0_Y + plane;
-   case SSPP_DMA1: return CID_DMA1_Y + plane;
-   case SSPP_VIG3: return CID_VIG3_Y + plane;
-   case SSPP_RGB3: return CID_RGB3;
-   default:return CID_UNUSED;
-   }
+#define CID_UNUSED 0
+
+   if (WARN_ON(plane >= pipe2nclients(pipe)))
+   return CID_UNUSED;
+
+   /*
+* Note on SMP clients:
+* For ViG pipes, fetch Y/Cr/Cb-components clients are always
+* consecutive, and in that order.
+*
+* e.g.:
+* if mdp5_cfg->smp.clients[SSPP_VIG0] = N,
+*  Y  plane's client ID is N
+*  Cr plane's client ID is N + 1
+*  Cb plane's client ID is N + 2
+*/
+
+   return mdp5_cfg->smp.clients[pipe] + plane;
 }

 /* step #1: update # of blocks pending for the client:

[PATCH 3/5] drm/msm/mdp5: Update headers (remove enum mdp5_client_id)

[Stephane Viau]

This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 41 ++---
 1 file changed, 7 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index cb931ca..b4e2624 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
29843 bytes, from 2015-03-09 12:32:38)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
28872 bytes, from 2015-03-09 12:40:51)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -97,33 +97,6 @@ enum mdp5_pipe_bwc {
BWC_Q_MED = 2,
 };

-enum mdp5_client_id {
-   CID_UNUSED = 0,
-   CID_VIG0_Y = 1,
-   CID_VIG0_CR = 2,
-   CID_VIG0_CB = 3,
-   CID_VIG1_Y = 4,
-   CID_VIG1_CR = 5,
-   CID_VIG1_CB = 6,
-   CID_VIG2_Y = 7,
-   CID_VIG2_CR = 8,
-   CID_VIG2_CB = 9,
-   CID_DMA0_Y = 10,
-   CID_DMA0_CR = 11,
-   CID_DMA0_CB = 12,
-   CID_DMA1_Y = 13,
-   CID_DMA1_CR = 14,
-   CID_DMA1_CB = 15,
-   CID_RGB0 = 16,
-   CID_RGB1 = 17,
-   CID_RGB2 = 18,
-   CID_VIG3_Y = 19,
-   CID_VIG3_CR = 20,
-   CID_VIG3_CB = 21,
-   CID_RGB3 = 22,
-   CID_MAX = 23,
-};
-
 enum mdp5_cursor_format {
CURSOR_FMT_ARGB = 0,
CURSOR_FMT_ARGB1555 = 2,
@@ -276,19 +249,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t 
i0, uint32_t i1) { retu
 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) 
{ return 0x0080 + __offset_MDP(i0) + 0x4*i1; }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0xff00
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & 
MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
 }
@@ -298,19 +271,19 @@ static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t 
i0, uint32_t i1) { retu
 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) 
{ return 0x0130 + __offset_MDP(i0) + 0x4*i1; }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT0
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0xff00
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT8
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
 }
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff
 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT16
-static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id 
val)
+static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
 {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & 
MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
 }
-- 
Qualcomm Inn

[PATCH 2/5] drm/msm/mdp5: Separate MDP5 domain from MDSS domain

[Stephane Viau]

MDP block is actually contained inside the MDSS block. For some
chipsets, the base address of the MDP registers is different from the
current (assumed) 0x100 offset.

Like CTL and LM blocks, this changes introduce a dynamic offset
for the MDP instance, which can be found out at runtime, once the
MDSS HW version is read.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  8 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 20 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 26 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  9 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 20 ++--
 7 files changed, 48 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 6c467fb..f786c70 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -24,6 +24,10 @@ const struct mdp5_cfg_hw *mdp5_cfg = NULL;

 const struct mdp5_cfg_hw msm8x74_config = {
.name = "msm8x74",
+   .mdp = {
+   .count = 1,
+   .base = { 0x00100 },
+   },
.smp = {
.mmb_count = 22,
.mmb_size = 4096,
@@ -75,6 +79,10 @@ const struct mdp5_cfg_hw msm8x74_config = {

 const struct mdp5_cfg_hw apq8084_config = {
.name = "apq8084",
+   .mdp = {
+   .count = 1,
+   .base = { 0x00100 },
+   },
.smp = {
.mmb_count = 44,
.mmb_size = 8192,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 93bee92..11f3e86 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -61,6 +61,7 @@ struct mdp5_smp_block {
 struct mdp5_cfg_hw {
char  *name;

+   struct mdp5_sub_block mdp;
struct mdp5_smp_block smp;
struct mdp5_ctl_block ctl;
struct mdp5_sub_block pipe_vig;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 7c0adf5..0fa7fce 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -112,31 +112,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms,
u32 intf_sel;

spin_lock_irqsave(_kms->resource_lock, flags);
-   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
+   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0));

switch (intf->num) {
case 0:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type);
break;
case 1:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type);
break;
case 2:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type);
break;
case 3:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type);
+   intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
+   intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type);
break;
default:
BUG();
break;
}

-   mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
+   mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel);
spin_unlock_irqrestore(_kms->resource_lock, flags);
 }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index a940710..33bd4c6 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -23,7 +23,7 @@

 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
 {
-   mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
+   mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
 }

 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
@@ -35,8 +35,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
mdp5_enable(mdp5_kms);
-   mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0x);
- 

[PATCH 1/5] drm/msm/mdp5: Update headers (introduce MDP5 domain)

[Stephane Viau]

This change contains the generated header file for the following
change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain".

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 203 +++-
 1 file changed, 118 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index b4d8716..cb931ca 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27094 bytes, from 2015-01-23 16:27:31)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
29843 bytes, from 2015-03-09 12:32:38)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -174,139 +174,172 @@ enum mdp5_data_format {
 #define MDP5_IRQ_INTF2_VSYNC   0x2000
 #define MDP5_IRQ_INTF3_UNDER_RUN   0x4000
 #define MDP5_IRQ_INTF3_VSYNC   0x8000
-#define REG_MDP5_HW_VERSION0x
+#define REG_MDSS_HW_VERSION0x
+#define MDSS_HW_VERSION_STEP__MASK 0x
+#define MDSS_HW_VERSION_STEP__SHIFT0
+static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & 
MDSS_HW_VERSION_STEP__MASK;
+}
+#define MDSS_HW_VERSION_MINOR__MASK0x0fff
+#define MDSS_HW_VERSION_MINOR__SHIFT   16
+static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & 
MDSS_HW_VERSION_MINOR__MASK;
+}
+#define MDSS_HW_VERSION_MAJOR__MASK0xf000
+#define MDSS_HW_VERSION_MAJOR__SHIFT   28
+static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
+{
+   return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & 
MDSS_HW_VERSION_MAJOR__MASK;
+}
+
+#define REG_MDSS_HW_INTR_STATUS
0x0010
+#define MDSS_HW_INTR_STATUS_INTR_MDP   0x0001
+#define MDSS_HW_INTR_STATUS_INTR_DSI0  0x0010
+#define MDSS_HW_INTR_STATUS_INTR_DSI1  0x0020
+#define MDSS_HW_INTR_STATUS_INTR_HDMI  0x0100
+#define MDSS_HW_INTR_STATUS_INTR_EDP   0x1000

-#define REG_MDP5_HW_INTR_STATUS
0x0010
-#define MDP5_HW_INTR_STATUS_INTR_MDP   0x0001
-#define MDP5_HW_INTR_STATUS_INTR_DSI0  0x0010
-#define MDP5_HW_INTR_STATUS_INTR_DSI1  0x0020
-#define MDP5_HW_INTR_STATUS_INTR_HDMI  0x0100
-#define MDP5_HW_INTR_STATUS_INTR_EDP   0x1000
+static inline uint32_t __offset_MDP(uint32_t idx)
+{
+   switch (idx) {
+   case 0: return (mdp5_cfg->mdp.base[0]);
+   default: return INVALID_IDX(idx);
+   }
+}
+static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x + 
__offset_MDP(i0); }

-#define REG_MDP5_MDP_VERSION   0x0100
-#define MDP5_MDP_VERSION_MINOR__MASK   0x00ff
-#define MDP5_MDP_VERSION_MINOR__SHIFT  16
-static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
+static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 
0x + __offset_MDP(i0); }
+#define MDP5_MDP_HW_VERSION_STEP__MASK 0x
+#define MDP5_MDP_HW_VERSION_STEP__SHIFT0
+static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
+{
+   return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & 
MDP5_MDP_HW_VERSION_STEP__MASK;
+}
+#define MDP5_MDP_HW_VERSION_MINOR__MASK
0x0fff
+#define MDP5_MDP_HW_VERSION_MINOR__SHIFT   16
+static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)
 {
-   return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & 
MDP5_MDP_VERSION_MINOR__MASK;
+   return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & 
MDP5_MDP_HW_VERSION_MINOR__MASK;
 }
-#define MDP5_MDP_VERSION_MAJOR__MASK   0xf000
-#define MDP5_MDP_VERSION_MAJOR__SHIFT 

[PATCH 0/5] drm/msm: Add display configuration for msm8x16

[Stephane Viau]

This patch set contains a couple modifications of the MDP5 register
description, followed by the MDP hw configuration of the msm8016 and
msm8916 chipsets.

Stephane Viau (5):
  drm/msm/mdp5: Update headers (introduce MDP5 domain)
  drm/msm/mdp5: Separate MDP5 domain from MDSS domain
  drm/msm/mdp5: Update headers (remove enum mdp5_client_id)
  drm/msm/mdp5: Get SMP client list from mdp5_cfg
  drm/msm/mdp5: Add hardware configuration for msm8x16

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 230 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  79 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c |  20 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c |  26 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |   9 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |   2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c |  64 -
 8 files changed, 257 insertions(+), 175 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH v2 4/4] drm/msm/mdp5: Make the intf connection in config module

[Stephane Viau]

Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   8 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   4 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 111 ++--
 3 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 72c075a..8bee023 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -62,6 +62,10 @@ const struct mdp5_cfg_hw msm8x74_config = {
.count = 4,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 2,
 };

@@ -111,6 +115,10 @@ const struct mdp5_cfg_hw apq8084_config = {
.count = 5,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 32000,
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 69e35ac..12224d7 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -56,6 +56,8 @@ struct mdp5_smp_block {
int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };

+#define MDP5_INTF_NUM_MAX  5
+
 struct mdp5_cfg_hw {
char  *name;

@@ -69,6 +71,8 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block ad;
struct mdp5_sub_block intf;

+   u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
+
uint32_t max_clk;
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 390d9d2..73729e9 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -161,6 +161,44 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
return 0;
 }

+static int construct_encoder(struct mdp5_kms *mdp5_kms,
+   enum mdp5_intf_type intf_type, int intf_num)
+{
+   struct drm_device *dev = mdp5_kms->dev;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct drm_encoder *encoder;
+   struct mdp5_interface intf = {
+   .num= intf_num,
+   .type   = intf_type,
+   .mode   = MDP5_INTF_MODE_NONE,
+   };
+   int ret = 0;
+
+   encoder = mdp5_encoder_init(dev, );
+   if (IS_ERR(encoder)) {
+   ret = PTR_ERR(encoder);
+   dev_err(dev->dev, "failed to construct encoder: %d\n", ret);
+   return ret;
+   }
+
+   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
+   priv->encoders[priv->num_encoders++] = encoder;
+
+   if (intf_type == INTF_HDMI) {
+   ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init HDMI: %d\n", ret);
+
+   } else if (intf_type == INTF_eDP) {
+   /* Construct bridge/connector for eDP: */
+   ret = msm_edp_modeset_init(priv->edp, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init eDP: %d\n", ret);
+   }
+
+   return ret;
+}
+
 static int modeset_init(struct mdp5_kms *mdp5_kms)
 {
static const enum mdp5_pipe crtcs[] = {
@@ -171,7 +209,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
};
struct drm_device *dev = mdp5_kms->dev;
struct msm_drm_private *priv = dev->dev_private;
-   struct drm_encoder *encoder;
const struct mdp5_cfg_hw *hw_cfg;
int i, ret;

@@ -222,56 +259,29 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
}
}

-   if (priv->hdmi) {
-   struct mdp5_interface intf = {
-   .num= 3,
-   .type   = INTF_HDMI,
-   .mode   = MDP5_INTF_MODE_NONE,
-   };
-
-   /* Construct encoder for HDMI: */
-   encoder = mdp5_encoder_init(dev, );
-   if (IS_ERR(encoder)) {
-   dev_err(dev->dev, "failed to construct encoder\n");
-   ret = PTR_ERR(encoder);
-   goto fail;
-   }
-
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
-   priv->encoders[priv->num_encoders++] = encoder;
-
-   ret = hdmi_modeset_init(priv->hdmi

[PATCH v2 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines

[Stephane Viau]

Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of the pipeline
status (eg: whether pipeline registers are flushed AND output WB
buffers are ready, in case of WB interface).

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  31 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  72 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |   1 +
 7 files changed, 276 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index c078f30..72c075a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x0003,
},
.pipe_vig = {
.count = 3,
@@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x003f,
},
.pipe_vig = {
.count = 4,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 4e90740..69e35ac 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -44,6 +44,11 @@ struct mdp5_lm_block {
uint32_t nb_stages; /* number of stages per blender */
 };

+struct mdp5_ctl_block {
+   MDP5_SUB_BLOCK_DEFINITION;
+   uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
+};
+
 struct mdp5_smp_block {
int mmb_count;  /* number of SMP MMBs */
int mmb_size;   /* MMB: size in bytes */
@@ -55,7 +60,7 @@ struct mdp5_cfg_hw {
char  *name;

struct mdp5_smp_block smp;
-   struct mdp5_sub_block ctl;
+   struct mdp5_ctl_block ctl;
struct mdp5_sub_block pipe_vig;
struct mdp5_sub_block pipe_rgb;
struct mdp5_sub_block pipe_dma;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 15136f1..9527ad1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -82,8 +82,6 @@ static void request_pending(struct drm_crtc *crtc, uint32_t 
pending)
mdp_irq_register(_kms(crtc)->base, _crtc->vblank);
 }

-#define mdp5_lm_get_flush(lm)  mdp_ctl_flush_mask_lm(lm)
-
 static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
@@ -110,8 +108,8 @@ static void crtc_flush_all(struct drm_crtc *crtc)
drm_atomic_crtc_for_each_plane(plane, crtc) {
flush_mask |= mdp5_plane_get_flush(plane);
}
-   flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
-   flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
+
+   flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);

crtc_flush(crtc, flush_mask);
 }
@@ -442,13 +440,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   struct drm_gem_object *cursor_bo, *old_bo;
+   struct drm_gem_object *cursor_bo, *old_bo = NULL;
uint32_t blendcfg, cursor_addr, stride;
int ret, bpp, lm;
unsigned int depth;
enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w, roi_h;
+   bool cursor_enable = true;
unsigned long flags;

if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
@@ -461,7 +460,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

if (!handle) {
DBG("Cursor off");
-   return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false);
+   cursor_enable = false;
+   goto set_cursor;
}

cursor_bo = drm_gem_object_lookup(dev, file, handle);
@@ -502,11 +502,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

spin_unlock_irqrestore(_crtc->cursor.lock, flags);

-   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true);
-   if (ret)
+set_cursor:
+   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
+   if (ret) {
+   dev_err(dev->dev, "failed to %sable cursor: %d\n",

[PATCH v2 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration

[Stephane Viau]

DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().

For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for DSI.

This change takes care of configuring the whole pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  4 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39 ++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 91 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  3 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 29 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 16 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 48 ---
 7 files changed, 159 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index dba4d52..4e90740 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -84,6 +84,10 @@ const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct 
mdp5_cfg_handler *cfg_hn
 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);

+#define mdp5_cfg_intf_is_virtual(intf_type) ({ \
+   typeof(intf_type) __val = (intf_type);  \
+   (__val) >= INTF_VIRTUAL ? true : false; })
+
 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
uint32_t major, uint32_t minor);
 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index bfba236..15136f1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -611,48 +611,17 @@ void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, 
struct drm_file *file)
 }

 /* set interface for routing crtc->encoder: */
-void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
-   enum mdp5_intf intf_id)
+void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   uint32_t intf_sel;
-   unsigned long flags;
+   int lm = mdp5_crtc_get_lm(crtc);

/* now that we know what irq's we want: */
-   mdp5_crtc->err.irqmask = intf2err(intf);
-   mdp5_crtc->vblank.irqmask = intf2vblank(intf);
+   mdp5_crtc->err.irqmask = intf2err(intf->num);
+   mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
mdp_irq_update(_kms->base);

-   spin_lock_irqsave(_kms->resource_lock, flags);
-   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
-
-   switch (intf) {
-   case 0:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id);
-   break;
-   case 1:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id);
-   break;
-   case 2:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id);
-   break;
-   case 3:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id);
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
-   spin_unlock_irqrestore(_kms->resource_lock, flags);
-
-   DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
 }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 1511290..a548113 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -33,6 +33,16 @@
  * requested by the client (in mdp5_crtc_mode_set()).
  */

+struct op_mode {
+   struct mdp5_interface intf;
+   /*
+* TODO: add a state variable to control the pipeline
+*
+* eg: WB interface needs both buffer addresses to be committed +
+* output buffers ready to be written into, before we can START.
+*/
+};
+
 struct mdp5_ctl {
struct mdp5_ctl_manager *ctlm;

@@ -41,8 +51,8 @@ struct mdp5_ctl {
/* whether this CTL has been allocated or not: */
bool busy;

-   /* memory output connection (@see mdp5_ctl_mode): */
-   u32 mode;
+   /* Operation Mode Configuration for the Pipeline */
+   struct op_mode pipeline;

/* REG_MDP5_CTL_*() registers access info + lock: */

[PATCH v2 1/4] drm/msm/mdp5: Update generated header files

[Stephane Viau]

Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
 1 file changed, 33 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index c276624..095a54c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27229 bytes, from 2015-02-10 17:00:41)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27094 bytes, from 2015-01-23 16:27:31)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -37,11 +37,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 */


-enum mdp5_intf {
+enum mdp5_intf_type {
+   INTF_DISABLED = 0,
INTF_DSI = 1,
INTF_HDMI = 3,
INTF_LCDC = 5,
INTF_eDP = 9,
+   INTF_VIRTUAL = 100,
+   INTF_WB = 101,
 };

 enum mdp5_intfnum {
@@ -67,11 +70,11 @@ enum mdp5_pipe {

 enum mdp5_ctl_mode {
MODE_NONE = 0,
-   MODE_ROT0 = 1,
-   MODE_ROT1 = 2,
-   MODE_WB0 = 3,
-   MODE_WB1 = 4,
-   MODE_WFD = 5,
+   MODE_WB_0_BLOCK = 1,
+   MODE_WB_1_BLOCK = 2,
+   MODE_WB_0_LINE = 3,
+   MODE_WB_1_LINE = 4,
+   MODE_WB_2_LINE = 5,
 };

 enum mdp5_pack_3d {
@@ -144,30 +147,25 @@ enum mdp5_data_format {
DATA_FORMAT_YUV = 1,
 };

-#define MDP5_IRQ_INTF0_WB_ROT_COMP 0x0001
-#define MDP5_IRQ_INTF1_WB_ROT_COMP 0x0002
-#define MDP5_IRQ_INTF2_WB_ROT_COMP 0x0004
-#define MDP5_IRQ_INTF3_WB_ROT_COMP 0x0008
-#define MDP5_IRQ_INTF0_WB_WFD  0x0010
-#define MDP5_IRQ_INTF1_WB_WFD  0x0020
-#define MDP5_IRQ_INTF2_WB_WFD  0x0040
-#define MDP5_IRQ_INTF3_WB_WFD  0x0080
-#define MDP5_IRQ_INTF0_PING_PONG_COMP  0x0100
-#define MDP5_IRQ_INTF1_PING_PONG_COMP  0x0200
-#define MDP5_IRQ_INTF2_PING_PONG_COMP  0x0400
-#define MDP5_IRQ_INTF3_PING_PONG_COMP  0x0800
-#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR
0x1000
-#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR
0x2000
-#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR
0x4000
-#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR
0x8000
-#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR
0x0001
-#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR
0x0002
-#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR
0x0004
-#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR
0x0008
-#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF  0x0010
-#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF  0x0020
-#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF  0x0040
-#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF  0x0080
+#define MDP5_IRQ_WB_0_DONE 0x0001
+#define MDP5_IRQ_WB_1_DONE 0x0002
+#define MDP5_IRQ_WB_2_DONE 0x0010
+#define MDP5_IRQ_PING_PONG_0_DONE  0x0100
+#define MDP5_IRQ_PING_PONG_1_DONE  0x0200
+#define MDP5_IRQ_PING_PONG_2_DONE  0x0400
+#define MDP5_IRQ_PING_PONG_3_DONE  0x0800
+#define MDP5_IRQ_PING_PONG_0_RD_PTR0x1000
+#define MDP5_IRQ_PING_PONG_1_RD_PTR0x2000
+#define MDP5_IRQ_PING_PONG_2_RD_PTR0x4000
+#define MDP5_IRQ_PING_PONG_3_RD_PTR0x8000
+#define MDP5_IRQ_PING_PONG_0_WR_PTR0x0001
+#define MDP5_IRQ_PING_PONG_1_WR_PTR0x0002
+#define MDP5_IRQ_PING_PONG_2_WR_PTR0x0004
+#define MDP5_IRQ_PING_PONG_3_WR_PTR0x0008
+#define MDP5_IRQ_PING_PONG_0_AUTO_REF  0x0010
+#define MDP5_IRQ_PING_PONG_1_AUTO_REF

[PATCH v2 0/4] drm/msm: preparation for WB/DSI connectors

[Stephane Viau]

WB and DSI support are in the pipe and will come out soon. Before that,
we need to prepare the MDP5 driver so we can support these connectors.

v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]

Stephane Viau (4):
  drm/msm/mdp5: Update generated header files
  drm/msm/mdp5: Enhance operation mode for pipeline configuration
  drm/msm/mdp5: Add START signal to kick off certain pipelines
  drm/msm/mdp5: Make the intf connection in config module

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h |  68 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  10 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  15 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  70 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 326 +---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  75 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  40 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  99 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  49 -
 9 files changed, 521 insertions(+), 231 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: Prepare for more interfaces support (WB, DSI)

[Stephane Viau]

More interfaces are soon coming into picture; rework the
interface type a bit in order to make the code more clear.
Ping Pong interrupts are not directly linked to an interface number.
This change removes the INTFn prefix for Ping Pong interrupts.
Also rename some fields linked to WB paths.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 67 +++---
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 3c199a1..4d9781c 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -11,11 +11,15 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

-   
+   
+   




+   
+   
+   



@@ -44,11 +48,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
-   
+   
+   
+   
+   
+   



@@ -110,30 +114,25 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
-   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   



@@ -165,10 +164,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
-   
-   
-   
+   
+   
+   
+   



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 4/4] drm/msm/mdp5: Make the intf connection in config module

[Stephane Viau]

Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   8 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   4 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 111 ++--
 3 files changed, 74 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 72c075a..8bee023 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -62,6 +62,10 @@ const struct mdp5_cfg_hw msm8x74_config = {
.count = 4,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 2,
 };

@@ -111,6 +115,10 @@ const struct mdp5_cfg_hw apq8084_config = {
.count = 5,
.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
},
+   .intfs = {
+   [0] = INTF_eDP,
+   [3] = INTF_HDMI,
+   },
.max_clk = 32000,
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index be149b3..4e91f14 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -58,6 +58,8 @@ struct mdp5_smp_block {
int reserved[MAX_CLIENTS];  /* # of MMBs allocated per client */
 };

+#define MDP5_INTF_NUM_MAX  5
+
 struct mdp5_cfg_hw {
char  *name;

@@ -71,6 +73,8 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block ad;
struct mdp5_sub_block intf;

+   u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
+
uint32_t max_clk;
 };

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 390d9d2..8cec00e 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -161,6 +161,44 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
return 0;
 }

+static int construct_encoder(struct mdp5_kms *mdp5_kms,
+   enum mdp5_intf_type intf_type, int intf_num)
+{
+   struct drm_device *dev = mdp5_kms->dev;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct drm_encoder *encoder;
+   struct mdp5_interface intf = {
+   .num= intf_num,
+   .type   = intf_type,
+   .mode   = MDP5_INTF_MODE_NONE,
+   };
+   int ret = 0;
+
+   encoder = mdp5_encoder_init(dev, );
+   if (IS_ERR(encoder)) {
+   ret = PTR_ERR(encoder);
+   dev_err(dev->dev, "failed to construct encoder: %d\n", ret);
+   return ret;
+   }
+
+   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
+   priv->encoders[priv->num_encoders++] = encoder;
+
+   if (intf_type == INTF_HDMI) {
+   ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init HDMI: %d\n", ret);
+
+   } else if (intf_type == INTF_eDP) {
+   /* Construct bridge/connector for eDP: */
+   ret = msm_edp_modeset_init(priv->edp, dev, encoder);
+   if (ret)
+   dev_err(dev->dev, "failed to init eDP: %d\n", ret);
+   }
+
+   return ret;
+}
+
 static int modeset_init(struct mdp5_kms *mdp5_kms)
 {
static const enum mdp5_pipe crtcs[] = {
@@ -171,7 +209,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
};
struct drm_device *dev = mdp5_kms->dev;
struct msm_drm_private *priv = dev->dev_private;
-   struct drm_encoder *encoder;
const struct mdp5_cfg_hw *hw_cfg;
int i, ret;

@@ -222,56 +259,29 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
}
}

-   if (priv->hdmi) {
-   struct mdp5_interface intf = {
-   .num= 3,
-   .type   = INTF_HDMI,
-   .mode   = MDP5_INTF_MODE_NONE,
-   };
-
-   /* Construct encoder for HDMI: */
-   encoder = mdp5_encoder_init(dev, );
-   if (IS_ERR(encoder)) {
-   dev_err(dev->dev, "failed to construct encoder\n");
-   ret = PTR_ERR(encoder);
-   goto fail;
-   }
-
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
-   priv->encoders[priv->num_encoders++] = encoder;
-
-   ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
-   if (ret) {
-

[PATCH 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines

[Stephane Viau]

Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of the pipeline
status (eg: whether pipeline registers are flushed AND output WB
buffers are ready, in case of WB interface).

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |   2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  31 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  72 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |   1 +
 7 files changed, 276 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index c078f30..72c075a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x0003,
},
.pipe_vig = {
.count = 3,
@@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
.ctl = {
.count = 5,
.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
+   .flush_hw_mask = 0x003f,
},
.pipe_vig = {
.count = 4,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index be587b8..be149b3 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -46,6 +46,11 @@ struct mdp5_lm_block {
uint32_t nb_stages; /* number of stages per blender */
 };

+struct mdp5_ctl_block {
+   MDP5_SUB_BLOCK_DEFINITION;
+   uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
+};
+
 struct mdp5_smp_block {
int mmb_count;  /* number of SMP MMBs */
int mmb_size;   /* MMB: size in bytes */
@@ -57,7 +62,7 @@ struct mdp5_cfg_hw {
char  *name;

struct mdp5_smp_block smp;
-   struct mdp5_sub_block ctl;
+   struct mdp5_ctl_block ctl;
struct mdp5_sub_block pipe_vig;
struct mdp5_sub_block pipe_rgb;
struct mdp5_sub_block pipe_dma;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 15136f1..9527ad1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -82,8 +82,6 @@ static void request_pending(struct drm_crtc *crtc, uint32_t 
pending)
mdp_irq_register(_kms(crtc)->base, _crtc->vblank);
 }

-#define mdp5_lm_get_flush(lm)  mdp_ctl_flush_mask_lm(lm)
-
 static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
@@ -110,8 +108,8 @@ static void crtc_flush_all(struct drm_crtc *crtc)
drm_atomic_crtc_for_each_plane(plane, crtc) {
flush_mask |= mdp5_plane_get_flush(plane);
}
-   flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
-   flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
+
+   flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);

crtc_flush(crtc, flush_mask);
 }
@@ -442,13 +440,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   struct drm_gem_object *cursor_bo, *old_bo;
+   struct drm_gem_object *cursor_bo, *old_bo = NULL;
uint32_t blendcfg, cursor_addr, stride;
int ret, bpp, lm;
unsigned int depth;
enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w, roi_h;
+   bool cursor_enable = true;
unsigned long flags;

if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
@@ -461,7 +460,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

if (!handle) {
DBG("Cursor off");
-   return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false);
+   cursor_enable = false;
+   goto set_cursor;
}

cursor_bo = drm_gem_object_lookup(dev, file, handle);
@@ -502,11 +502,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,

spin_unlock_irqrestore(_crtc->cursor.lock, flags);

-   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true);
-   if (ret)
+set_cursor:
+   ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
+   if (ret) {
+   dev_err(dev->dev, "failed to %sable cursor: %d\n",

[PATCH 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration

[Stephane Viau]

DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().

For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for DSI.

This change takes care of configuring the whole pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  2 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39 ++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 91 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  3 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 29 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 16 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 48 ---
 7 files changed, 157 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index dba4d52..be587b8 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -31,6 +31,8 @@ extern const struct mdp5_cfg_hw *mdp5_cfg;

 typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);

+#define MDP5_INTF_IS_VIRTUAL_DISPLAY(intf_type)   ((intf_type) >= INTF_VIRTUAL)
+
 #define MDP5_SUB_BLOCK_DEFINITION \
int count; \
uint32_t base[MAX_BASES]
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index bfba236..15136f1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -611,48 +611,17 @@ void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, 
struct drm_file *file)
 }

 /* set interface for routing crtc->encoder: */
-void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
-   enum mdp5_intf intf_id)
+void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   uint32_t intf_sel;
-   unsigned long flags;
+   int lm = mdp5_crtc_get_lm(crtc);

/* now that we know what irq's we want: */
-   mdp5_crtc->err.irqmask = intf2err(intf);
-   mdp5_crtc->vblank.irqmask = intf2vblank(intf);
+   mdp5_crtc->err.irqmask = intf2err(intf->num);
+   mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
mdp_irq_update(_kms->base);

-   spin_lock_irqsave(_kms->resource_lock, flags);
-   intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
-
-   switch (intf) {
-   case 0:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id);
-   break;
-   case 1:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id);
-   break;
-   case 2:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id);
-   break;
-   case 3:
-   intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
-   intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id);
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
-   spin_unlock_irqrestore(_kms->resource_lock, flags);
-
-   DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
 }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 1511290..3e88bb7 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -33,6 +33,16 @@
  * requested by the client (in mdp5_crtc_mode_set()).
  */

+struct op_mode {
+   struct mdp5_interface intf;
+   /*
+* TODO: add a state variable to control the pipeline
+*
+* eg: WB interface needs both buffer addresses to be committed +
+* output buffers ready to be written into, before we can START.
+*/
+};
+
 struct mdp5_ctl {
struct mdp5_ctl_manager *ctlm;

@@ -41,8 +51,8 @@ struct mdp5_ctl {
/* whether this CTL has been allocated or not: */
bool busy;

-   /* memory output connection (@see mdp5_ctl_mode): */
-   u32 mode;
+   /* Operation Mode Configuration for the Pipeline */
+   struct op_mode pipeline;

/* REG_MDP5_CTL_*() registers access info + lock: */
spinlock_t hw_lock;
@@ -94,19 +104,81 @@ u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
return mdp5_read(mdp5_kms, reg);
 }

+static void set_display_intf(struct mdp5_kms *mdp5_kms,
+   struct mdp5_interface *intf)
+{
+   unsigned long flags;
+   u32 intf_sel;
+
+   spin_lock_irqsave(_kms

[PATCH 1/4] drm/msm/mdp5: Update generated header files

[Stephane Viau]

Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
 1 file changed, 33 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index c276624..095a54c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27229 bytes, from 2015-02-10 17:00:41)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27094 bytes, from 2015-01-23 16:27:31)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

@@ -37,11 +37,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 */


-enum mdp5_intf {
+enum mdp5_intf_type {
+   INTF_DISABLED = 0,
INTF_DSI = 1,
INTF_HDMI = 3,
INTF_LCDC = 5,
INTF_eDP = 9,
+   INTF_VIRTUAL = 100,
+   INTF_WB = 101,
 };

 enum mdp5_intfnum {
@@ -67,11 +70,11 @@ enum mdp5_pipe {

 enum mdp5_ctl_mode {
MODE_NONE = 0,
-   MODE_ROT0 = 1,
-   MODE_ROT1 = 2,
-   MODE_WB0 = 3,
-   MODE_WB1 = 4,
-   MODE_WFD = 5,
+   MODE_WB_0_BLOCK = 1,
+   MODE_WB_1_BLOCK = 2,
+   MODE_WB_0_LINE = 3,
+   MODE_WB_1_LINE = 4,
+   MODE_WB_2_LINE = 5,
 };

 enum mdp5_pack_3d {
@@ -144,30 +147,25 @@ enum mdp5_data_format {
DATA_FORMAT_YUV = 1,
 };

-#define MDP5_IRQ_INTF0_WB_ROT_COMP 0x0001
-#define MDP5_IRQ_INTF1_WB_ROT_COMP 0x0002
-#define MDP5_IRQ_INTF2_WB_ROT_COMP 0x0004
-#define MDP5_IRQ_INTF3_WB_ROT_COMP 0x0008
-#define MDP5_IRQ_INTF0_WB_WFD  0x0010
-#define MDP5_IRQ_INTF1_WB_WFD  0x0020
-#define MDP5_IRQ_INTF2_WB_WFD  0x0040
-#define MDP5_IRQ_INTF3_WB_WFD  0x0080
-#define MDP5_IRQ_INTF0_PING_PONG_COMP  0x0100
-#define MDP5_IRQ_INTF1_PING_PONG_COMP  0x0200
-#define MDP5_IRQ_INTF2_PING_PONG_COMP  0x0400
-#define MDP5_IRQ_INTF3_PING_PONG_COMP  0x0800
-#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR
0x1000
-#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR
0x2000
-#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR
0x4000
-#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR
0x8000
-#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR
0x0001
-#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR
0x0002
-#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR
0x0004
-#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR
0x0008
-#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF  0x0010
-#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF  0x0020
-#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF  0x0040
-#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF  0x0080
+#define MDP5_IRQ_WB_0_DONE 0x0001
+#define MDP5_IRQ_WB_1_DONE 0x0002
+#define MDP5_IRQ_WB_2_DONE 0x0010
+#define MDP5_IRQ_PING_PONG_0_DONE  0x0100
+#define MDP5_IRQ_PING_PONG_1_DONE  0x0200
+#define MDP5_IRQ_PING_PONG_2_DONE  0x0400
+#define MDP5_IRQ_PING_PONG_3_DONE  0x0800
+#define MDP5_IRQ_PING_PONG_0_RD_PTR0x1000
+#define MDP5_IRQ_PING_PONG_1_RD_PTR0x2000
+#define MDP5_IRQ_PING_PONG_2_RD_PTR0x4000
+#define MDP5_IRQ_PING_PONG_3_RD_PTR0x8000
+#define MDP5_IRQ_PING_PONG_0_WR_PTR0x0001
+#define MDP5_IRQ_PING_PONG_1_WR_PTR0x0002
+#define MDP5_IRQ_PING_PONG_2_WR_PTR0x0004
+#define MDP5_IRQ_PING_PONG_3_WR_PTR0x0008
+#define MDP5_IRQ_PING_PONG_0_AUTO_REF  0x0010
+#define MDP5_IRQ_PING_PONG_1_AUTO_REF

[PATCH 0/4] drm/msm: preparation for WB/DSI connectors

[Stephane Viau]

WB and DSI support are in the pipe and will come out soon. Before that, we
need to prepare the MDP5 driver so we can support these connectors.

Stephane Viau (4):
  drm/msm/mdp5: Update generated header files
  drm/msm/mdp5: Enhance operation mode for pipeline configuration
  drm/msm/mdp5: Add START signal to kick off certain pipelines
  drm/msm/mdp5: Make the intf connection in config module

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h |  68 +++---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c |  10 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |  13 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  70 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 326 +---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h |  75 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  40 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  99 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  49 -
 9 files changed, 519 insertions(+), 231 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] rnndb: Add a 6th lm.base entry

[Stephane Viau]

Some target have up to 6 layer mixers (LM). Let the xml file
access the last LM's base address.

Signed-off-by: Stephane Viau 
---
 rnndb/mdp/mdp5.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index cd3bf37..eaaec47 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -380,7 +380,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



-   
+



-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/2] drm/msm/mdp5: Avoid flushing registers when CRTC is disabled

[Stephane Viau]

When a CRTC is disabled, no CTL is allocated to it (CRTC->ctl == NULL);
in that case we should not try to FLUSH registers and do nothing instead.

This can happen when we try to move a cursor but the CRTC's CTL
(CONTROL) has not been allocated yet (inactive CRTC).
It can also happens when we .atomic_check()/.atomic_flush() on a
disabled CRTC.

A CTL needs to be kept as long as the CRTC is alive. Releasing it
after the last VBlank is safer than in .atomic_flush().

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 26 +++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 946b71b..2aeae73 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -103,8 +103,8 @@ static void crtc_flush_all(struct drm_crtc *crtc)
struct drm_plane *plane;
uint32_t flush_mask = 0;

-   /* we could have already released CTL in the disable path: */
-   if (!mdp5_crtc->ctl)
+   /* this should not happen: */
+   if (WARN_ON(!mdp5_crtc->ctl))
return;

drm_atomic_crtc_for_each_plane(plane, crtc) {
@@ -143,6 +143,11 @@ static void complete_flip(struct drm_crtc *crtc, struct 
drm_file *file)
drm_atomic_crtc_for_each_plane(plane, crtc) {
mdp5_plane_complete_flip(plane);
}
+
+   if (mdp5_crtc->ctl && !crtc->state->enable) {
+   mdp5_ctl_release(mdp5_crtc->ctl);
+   mdp5_crtc->ctl = NULL;
+   }
 }

 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
@@ -386,14 +391,17 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc)
mdp5_crtc->event = crtc->state->event;
spin_unlock_irqrestore(>event_lock, flags);

+   /*
+* If no CTL has been allocated in mdp5_crtc_atomic_check(),
+* it means we are trying to flush a CRTC whose state is disabled:
+* nothing else needs to be done.
+*/
+   if (unlikely(!mdp5_crtc->ctl))
+   return;
+
blend_setup(crtc);
crtc_flush_all(crtc);
request_pending(crtc, PENDING_FLIP);
-
-   if (mdp5_crtc->ctl && !crtc->state->enable) {
-   mdp5_ctl_release(mdp5_crtc->ctl);
-   mdp5_crtc->ctl = NULL;
-   }
 }

 static int mdp5_crtc_set_property(struct drm_crtc *crtc,
@@ -495,6 +503,10 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, 
int x, int y)
uint32_t roi_h;
unsigned long flags;

+   /* In case the CRTC is disabled, just drop the cursor update */
+   if (unlikely(!crtc->state->enable))
+   return 0;
+
x = (x > 0) ? x : 0;
y = (y > 0) ? y : 0;

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 1/2] drm/msm: update generated headers (add 6th lm.base entry)

[Stephane Viau]

Some target have up to 6 layer mixers (LM).
Let the header file access the last LM's base address.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 15 ---
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 09b4a25..c276624 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -8,17 +8,9 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml (
676 bytes, from 2014-12-05 15:34:49)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml(  
20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml(  
27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (  
11712 bytes, from 2013-08-17 17:13:43)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml(
344 bytes, from 2013-08-11 19:26:32)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml (   
1686 bytes, from 2014-10-31 16:48:57)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml (
600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml   (  
26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (   
8253 bytes, from 2014-12-08 16:13:00)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml(  
27229 bytes, from 2015-02-10 17:00:41)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2014-06-02 18:31:15)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml  (   
2357 bytes, from 2015-01-23 16:20:19)

 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -910,6 +902,7 @@ static inline uint32_t __offset_LM(uint32_t idx)
case 2: return (mdp5_cfg->lm.base[2]);
case 3: return (mdp5_cfg->lm.base[3]);
case 4: return (mdp5_cfg->lm.base[4]);
+   case 5: return (mdp5_cfg->lm.base[5]);
default: return INVALID_IDX(idx);
}
 }
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 0/2] drm/msm/mdp5: A couple of fixes

[Stephane Viau]

The 4th CRTC could not be accessed because of a missing case entry.

Also, only flush registers when a CRTC is enabled (and thus a CTL is allocated).
This shall fix the cursor move issue that Rob mentioned.

Stephane Viau (2):
  drm/msm: update generated headers (add 6th lm.base entry)
  drm/msm/mdp5: Avoid flushing registers when CRTC is disabled

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h  | 15 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 26 +++---
 2 files changed, 23 insertions(+), 18 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm/mdp5: fixup "drm/msm: fix fallout of atomic dpms changes"

[Stephane Viau]

Commit 0b776d457b94 ("drm/msm: fix fallout of atomic dpms
changes") has a typo in both mdp5_encoder_helper_funcs and
mdp5_crtc_helper_funcs definitions:

.dpms entry should be replaced by .disable and .enable

Also fixed a typo in mdp5_encoder_enable().

Note that these typos are only present for MDP5. MDP4 is fine.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 4 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 46fac54..946b71b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -544,8 +544,8 @@ static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
.mode_fixup = mdp5_crtc_mode_fixup,
.mode_set_nofb = mdp5_crtc_mode_set_nofb,
-   .prepare = mdp5_crtc_disable,
-   .commit = mdp5_crtc_enable,
+   .disable = mdp5_crtc_disable,
+   .enable = mdp5_crtc_enable,
.atomic_check = mdp5_crtc_atomic_check,
.atomic_begin = mdp5_crtc_atomic_begin,
.atomic_flush = mdp5_crtc_atomic_flush,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 549d9a8..a09fa58 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -267,14 +267,14 @@ static void mdp5_encoder_enable(struct drm_encoder 
*encoder)
mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1);
spin_unlock_irqrestore(_encoder->intf_lock, flags);

-   mdp5_encoder->enabled = false;
+   mdp5_encoder->enabled = true;
 }

 static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
.mode_fixup = mdp5_encoder_mode_fixup,
.mode_set = mdp5_encoder_mode_set,
-   .prepare = mdp5_encoder_disable,
-   .commit = mdp5_encoder_enable,
+   .disable = mdp5_encoder_disable,
+   .enable = mdp5_encoder_enable,
 };

 /* initialize encoder */
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm/mdp5: only flush on a CRTC ->atomic_flush()

[Stephane Viau]

MDP5 hardware has some limitation and requires to avoid flushing
registers more than once between two Vblanks.

This change removes all FLUSH operations (except for HW cursor)
beside the one coming from a CRTC's ->atomic_flush().

This avoid this type of behavior (eg: CRTC + 1 plane overlay):

[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048)   CTL + LM0 + RGB0
[drm:mdp5_ctl_commit] flush (20040)   CTL + LM0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049)   CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank

and replaces it by:

[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048)   CTL + LM0 + RGB0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049)   CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank

Only *one* FLUSH is called between Vblanks interrupts.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 10f93cf..f455f38 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -297,7 +297,7 @@ static void mdp5_crtc_commit(struct drm_crtc *crtc)
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
DBG("%s", mdp5_crtc->name);
mdp5_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
-   crtc_flush_all(crtc);
+
/* drop the ref to mdp clk's that we got in prepare: */
mdp5_disable(get_kms(crtc));
 }
@@ -600,7 +600,6 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   uint32_t flush_mask = 0;
uint32_t intf_sel;
unsigned long flags;

@@ -639,10 +638,6 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,

DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
-   flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
-   flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
-
-   crtc_flush(crtc, flush_mask);
 }

 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm/mdp5: Fix negative SMP block allocation

[Stephane Viau]

In case we request a number of SMP blocks which is lower than
the already reserved blocks, we should not try to allocate a
negative number, but 0 blocks instead.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index bf55188..1f795af89 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -119,9 +119,10 @@ static int smp_request_block(struct mdp5_smp *smp,

spin_lock_irqsave(>state_lock, flags);

-   nblks -= reserved;
-   if (reserved)
+   if (reserved) {
+   nblks = max(0, nblks - reserved);
DBG("%d MMBs allocated (%d reserved)", nblks, reserved);
+   }

avail = cnt - bitmap_weight(smp->state, cnt);
if (nblks > avail) {
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 2/2] drm/msm/mdp5: Add hardware cursor support

[Stephane Viau]

From: Beeresh Gopal <gbeer...@codeaurora.org>

This patch implements the hardware accelarated cursor
support for MDP5 platforms.

Signed-off-by: Beeresh Gopal 
Signed-off-by: Wentao Xu 
Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 164 +++
 1 file changed, 164 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index f021f96..2021f09 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -24,6 +24,9 @@
 #include "drm_crtc_helper.h"
 #include "drm_flip_work.h"

+#define CURSOR_WIDTH   64
+#define CURSOR_HEIGHT  64
+
 #define SSPP_MAX   (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */

 struct mdp5_crtc {
@@ -47,8 +50,21 @@ struct mdp5_crtc {
 #define PENDING_FLIP   0x2
atomic_t pending;

+   /* for unref'ing cursor bo's after scanout completes: */
+   struct drm_flip_work unref_cursor_work;
+
struct mdp_irq vblank;
struct mdp_irq err;
+
+   struct {
+   /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
+   spinlock_t lock;
+
+   /* current cursor being scanned out: */
+   struct drm_gem_object *scanout_bo;
+   uint32_t width;
+   uint32_t height;
+   } cursor;
 };
 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)

@@ -129,11 +145,22 @@ static void complete_flip(struct drm_crtc *crtc, struct 
drm_file *file)
}
 }

+static void unref_cursor_worker(struct drm_flip_work *work, void *val)
+{
+   struct mdp5_crtc *mdp5_crtc =
+   container_of(work, struct mdp5_crtc, unref_cursor_work);
+   struct mdp5_kms *mdp5_kms = get_kms(_crtc->base);
+
+   msm_gem_put_iova(val, mdp5_kms->id);
+   drm_gem_object_unreference_unlocked(val);
+}
+
 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);

drm_crtc_cleanup(crtc);
+   drm_flip_work_cleanup(_crtc->unref_cursor_work);

kfree(mdp5_crtc);
 }
@@ -384,6 +411,132 @@ static int mdp5_crtc_set_property(struct drm_crtc *crtc,
return -EINVAL;
 }

+static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
+   struct drm_file *file, uint32_t handle,
+   uint32_t width, uint32_t height)
+{
+   struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+   struct drm_device *dev = crtc->dev;
+   struct mdp5_kms *mdp5_kms = get_kms(crtc);
+   struct drm_gem_object *cursor_bo, *old_bo;
+   uint32_t blendcfg, cursor_addr, stride;
+   int ret, bpp, lm;
+   unsigned int depth;
+   enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
+   uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
+   unsigned long flags;
+
+   if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
+   dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
+   return -EINVAL;
+   }
+
+   if (NULL == mdp5_crtc->ctl)
+   return -EINVAL;
+
+   if (!handle) {
+   DBG("Cursor off");
+   return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false);
+   }
+
+   cursor_bo = drm_gem_object_lookup(dev, file, handle);
+   if (!cursor_bo)
+   return -ENOENT;
+
+   ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, _addr);
+   if (ret)
+   return -EINVAL;
+
+   lm = mdp5_crtc->lm;
+   drm_fb_get_bpp_depth(DRM_FORMAT_ARGB, , );
+   stride = width * (bpp >> 3);
+
+   spin_lock_irqsave(_crtc->cursor.lock, flags);
+   old_bo = mdp5_crtc->cursor.scanout_bo;
+
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
+   MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
+   MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
+   MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
+   MDP5_LM_CURSOR_SIZE_ROI_H(height) |
+   MDP5_LM_CURSOR_SIZE_ROI_W(width));
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
+
+
+   blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
+   blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN;
+   blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
+   mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
+
+   mdp5_crtc->cursor.scanout_bo = cursor_bo;
+   mdp5_crtc->cursor.width = width;
+   mdp5_crtc->cursor.height = height;
+   spin_unlock_irqrestore(_crtc->cursor.lock, flags);
+
+   ret = mdp

[PATCH 1/2] drm/msm/mdp5: add register description for HW Cursor support

[Stephane Viau]

Update generated headers, in particular pick up the definitions
for Hardware Cursor support (MDP5).

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 79 +
 1 file changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 7833c22..09701a4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -129,6 +129,17 @@ enum mdp5_client_id {
CID_MAX = 23,
 };

+enum mdp5_cursor_format {
+   CURSOR_FMT_ARGB = 0,
+   CURSOR_FMT_ARGB1555 = 2,
+   CURSOR_FMT_ARGB = 4,
+};
+
+enum mdp5_cursor_alpha {
+   CURSOR_ALPHA_CONST = 0,
+   CURSOR_ALPHA_PER_PIXEL = 2,
+};
+
 enum mdp5_igc_type {
IGC_VIG = 0,
IGC_RGB = 1,
@@ -973,20 +984,88 @@ static inline uint32_t 
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i
 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t 
i1) { return 0x0048 + __offset_LM(i0) + 0x30*i1; }

 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 
0x00e0 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK0x
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT   0
+static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & 
MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
+}
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK0x
+#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT   16
+static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & 
MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
+}

 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 
0x00e4 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK
0x
+#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT   0
+static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & 
MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
+}
+#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK
0x
+#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT   16
+static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & 
MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
+}

 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x00e8 
+ __offset_LM(i0); }
+#define MDP5_LM_CURSOR_XY_SRC_X__MASK  0x
+#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
+static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & 
MDP5_LM_CURSOR_XY_SRC_X__MASK;
+}
+#define MDP5_LM_CURSOR_XY_SRC_Y__MASK  0x
+#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
+static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & 
MDP5_LM_CURSOR_XY_SRC_Y__MASK;
+}

 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 
0x00dc + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x
+#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT0
+static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & 
MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
+}

 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 
0x00ec + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x0007
+#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT0
+static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format 
val)
+{
+   return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & 
MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
+}

 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 
0x00f0 + __offset_LM(i0); }

 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 
0x00f4 + __offset_LM(i0); }
+#define MDP5_LM_CURSOR_START_XY_X_START__MASK  0x
+#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
+static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
+{
+   return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & 
MDP5_LM_CURSOR_START_XY_X_START__MASK;
+}
+#define MDP5_LM_CURSOR_START_XY_Y_START__MASK  0x
+#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
+static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
+{
+   return ((val) << MDP5

[PATCH 0/2] drm/msm/mdp5: hardware cursor support

[Stephane Viau]

This patch set contains the hardware cursor changes. Split into two, as usual,
in order to separate header file generation from the rest of the code.

Beeresh Gopal (1):
  drm/msm/mdp5: Add hardware cursor support

Stephane Viau (1):
  drm/msm/mdp5: add register description for HW Cursor support

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h  |  79 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 164 +++
 2 files changed, 243 insertions(+)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH RESEND] drm/msm/hdmi: use dynamic allocation for hdmi resources

[Stephane Viau]

Instead of reporting BUG_ON when resources arrays are not
dimensioned correctly, this patch does a dynamic allocation of
these arrays. This is needed for the following patches that add a
regulator for a new target.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 28 
 drivers/gpu/drm/msm/hdmi/hdmi.h |  8 
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 062c687..180041d 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -106,7 +106,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
goto fail;
}

-   BUG_ON(config->hpd_reg_cnt > ARRAY_SIZE(hdmi->hpd_regs));
+   hdmi->hpd_regs = devm_kzalloc(>dev, sizeof(hdmi->hpd_regs[0]) *
+   config->hpd_reg_cnt, GFP_KERNEL);
+   if (!hdmi->hpd_regs) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->hpd_reg_cnt; i++) {
struct regulator *reg;

@@ -122,7 +127,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->hpd_regs[i] = reg;
}

-   BUG_ON(config->pwr_reg_cnt > ARRAY_SIZE(hdmi->pwr_regs));
+   hdmi->pwr_regs = devm_kzalloc(>dev, sizeof(hdmi->pwr_regs[0]) *
+   config->pwr_reg_cnt, GFP_KERNEL);
+   if (!hdmi->pwr_regs) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->pwr_reg_cnt; i++) {
struct regulator *reg;

@@ -138,7 +148,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->pwr_regs[i] = reg;
}

-   BUG_ON(config->hpd_clk_cnt > ARRAY_SIZE(hdmi->hpd_clks));
+   hdmi->hpd_clks = devm_kzalloc(>dev, sizeof(hdmi->hpd_clks[0]) *
+   config->hpd_clk_cnt, GFP_KERNEL);
+   if (!hdmi->hpd_clks) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->hpd_clk_cnt; i++) {
struct clk *clk;

@@ -153,7 +168,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->hpd_clks[i] = clk;
}

-   BUG_ON(config->pwr_clk_cnt > ARRAY_SIZE(hdmi->pwr_clks));
+   hdmi->pwr_clks = devm_kzalloc(>dev, sizeof(hdmi->pwr_clks[0]) *
+   config->pwr_clk_cnt, GFP_KERNEL);
+   if (!hdmi->pwr_clks) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->pwr_clk_cnt; i++) {
struct clk *clk;

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 43e654f..9973e03 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -52,10 +52,10 @@ struct hdmi {

void __iomem *mmio;

-   struct regulator *hpd_regs[2];
-   struct regulator *pwr_regs[2];
-   struct clk *hpd_clks[3];
-   struct clk *pwr_clks[2];
+   struct regulator **hpd_regs;
+   struct regulator **pwr_regs;
+   struct clk **hpd_clks;
+   struct clk **pwr_clks;

struct hdmi_phy *phy;
struct i2c_adapter *i2c;
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH] drm/msm/mdp5: fix parameter type for mdp5_ctl_set_intf()

[Stephane Viau]

mdp5_ctl_set_intf()'s second argument should be "int", not "enum mdp5_intf".
The passed in value is "intf", not "intf_id".

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index dea4505..1511290 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -95,7 +95,7 @@ u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
 }


-int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, enum mdp5_intf intf)
+int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, int intf)
 {
unsigned long flags;
static const enum mdp5_intfnum intfnum[] = {
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
index 1018519..ad48788 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
@@ -34,7 +34,7 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
  */
 struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct 
drm_crtc *crtc);

-int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, enum mdp5_intf intf);
+int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, int intf);

 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, bool enable);

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 3/3] drm/msm/hdmi: rework hdmi configurations, using dt_match[]

[Stephane Viau]

In the same idea mdp5_cfg was added, this change allows us to quickly
add new instances, such as apq8084's HDMI in this case.

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/hdmi.txt |   1 +
 drivers/gpu/drm/msm/hdmi/hdmi.c| 128 +++--
 2 files changed, 71 insertions(+), 58 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt 
b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
index c25d5aa..a29a55f 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -3,6 +3,7 @@ Qualcomm adreno/snapdragon hdmi output
 Required properties:
 - compatible: one of the following
* "qcom,hdmi-tx-8084"
+   * "qcom,hdmi-tx-8074"
* "qcom,hdmi-tx-8660"
* "qcom,hdmi-tx-8960"
 - reg: Physical base address and length of the controller's registers
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c2fe4fa..36a12ee 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
@@ -291,6 +292,57 @@ fail:

 #include 

+#define HDMI_CFG(item, entry) \
+   .item ## _names = item ##_names_ ## entry, \
+   .item ## _cnt   = ARRAY_SIZE(item ## _names_ ## entry)
+
+static struct hdmi_platform_config hdmi_tx_8660_config = {
+   .phy_init = hdmi_phy_8x60_init,
+};
+
+static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"};
+static const char *hpd_clk_names_8960[] = {"core_clk", "master_iface_clk", 
"slave_iface_clk"};
+
+static struct hdmi_platform_config hdmi_tx_8960_config = {
+   .phy_init = hdmi_phy_8960_init,
+   HDMI_CFG(hpd_reg, 8960),
+   HDMI_CFG(hpd_clk, 8960),
+};
+
+static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"};
+static const char *hpd_reg_names_8x74[] = {"hpd-gdsc", "hpd-5v"};
+static const char *pwr_clk_names_8x74[] = {"extp_clk", "alt_iface_clk"};
+static const char *hpd_clk_names_8x74[] = {"iface_clk", "core_clk", 
"mdp_core_clk"};
+static unsigned long hpd_clk_freq_8x74[] = {0, 1920, 0};
+
+static struct hdmi_platform_config hdmi_tx_8074_config = {
+   .phy_init = hdmi_phy_8x74_init,
+   HDMI_CFG(pwr_reg, 8x74),
+   HDMI_CFG(hpd_reg, 8x74),
+   HDMI_CFG(pwr_clk, 8x74),
+   HDMI_CFG(hpd_clk, 8x74),
+   .hpd_freq  = hpd_clk_freq_8x74,
+};
+
+static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"};
+
+static struct hdmi_platform_config hdmi_tx_8084_config = {
+   .phy_init = hdmi_phy_8x74_init,
+   HDMI_CFG(pwr_reg, 8x74),
+   HDMI_CFG(hpd_reg, 8084),
+   HDMI_CFG(pwr_clk, 8x74),
+   HDMI_CFG(hpd_clk, 8x74),
+   .hpd_freq  = hpd_clk_freq_8x74,
+};
+
+static const struct of_device_id dt_match[] = {
+   { .compatible = "qcom,hdmi-tx-8084", .data = _tx_8084_config },
+   { .compatible = "qcom,hdmi-tx-8074", .data = _tx_8074_config },
+   { .compatible = "qcom,hdmi-tx-8960", .data = _tx_8960_config },
+   { .compatible = "qcom,hdmi-tx-8660", .data = _tx_8660_config },
+   {}
+};
+
 #ifdef CONFIG_OF
 static int get_gpio(struct device *dev, struct device_node *of_node, const 
char *name)
 {
@@ -314,63 +366,28 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
struct drm_device *drm = dev_get_drvdata(master);
struct msm_drm_private *priv = drm->dev_private;
static struct hdmi_platform_config config = {};
+   static struct hdmi_platform_config *hdmi_cfg;
struct hdmi *hdmi;
 #ifdef CONFIG_OF
struct device_node *of_node = dev->of_node;
+   const struct of_device_id *match;

-   if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8074")) {
-   static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"};
-   static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};
-   static const char *hpd_clk_names[] = {"iface_clk", "core_clk", 
"mdp_core_clk"};
-   static unsigned long hpd_clk_freq[] = {0, 1920, 0};
-   static const char *pwr_clk_names[] = {"extp_clk", 
"alt_iface_clk"};
-   config.phy_init  = hdmi_phy_8x74_init;
-   config.hpd_reg_names = hpd_reg_names;
-   config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
-   config.pwr_reg_names = p

[PATCH 2/3] drm/msm/hdmi: Add HDMI platform config for apq8084

[Stephane Viau]

This change add the regulator/clock configuration for MDP5 v1.3.
This config is close to the one already existing for 8x74, except
that one more regulator is needed (hpd-5v-en).

Signed-off-by: Stephane Viau 
---
 Documentation/devicetree/bindings/drm/msm/hdmi.txt |  1 +
 drivers/gpu/drm/msm/hdmi/hdmi.c| 17 +
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt 
b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
index aca917f..c25d5aa 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt
@@ -2,6 +2,7 @@ Qualcomm adreno/snapdragon hdmi output

 Required properties:
 - compatible: one of the following
+   * "qcom,hdmi-tx-8084"
* "qcom,hdmi-tx-8660"
* "qcom,hdmi-tx-8960"
 - reg: Physical base address and length of the controller's registers
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index a9092d6..c2fe4fa 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -334,6 +334,22 @@ static int hdmi_bind(struct device *dev, struct device 
*master, void *data)
config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
config.pwr_clk_names = pwr_clk_names;
config.pwr_clk_cnt   = ARRAY_SIZE(pwr_clk_names);
+   } else if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8084")) {
+   static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v", 
"hpd-5v-en"};
+   static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};
+   static const char *hpd_clk_names[] = {"iface_clk", "core_clk", 
"mdp_core_clk"};
+   static unsigned long hpd_clk_freq[] = {0, 1920, 0};
+   static const char *pwr_clk_names[] = {"extp_clk", 
"alt_iface_clk"};
+   config.phy_init  = hdmi_phy_8x74_init;
+   config.hpd_reg_names = hpd_reg_names;
+   config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
+   config.pwr_reg_names = pwr_reg_names;
+   config.pwr_reg_cnt   = ARRAY_SIZE(pwr_reg_names);
+   config.hpd_clk_names = hpd_clk_names;
+   config.hpd_freq  = hpd_clk_freq;
+   config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
+   config.pwr_clk_names = pwr_clk_names;
+   config.pwr_clk_cnt   = ARRAY_SIZE(pwr_clk_names);
} else if (of_device_is_compatible(of_node, "qcom,hdmi-tx-8960")) {
static const char *hpd_clk_names[] = {"core_clk", 
"master_iface_clk", "slave_iface_clk"};
static const char *hpd_reg_names[] = {"core-vdda", "hdmi-mux"};
@@ -439,6 +455,7 @@ static int hdmi_dev_remove(struct platform_device *pdev)
 }

 static const struct of_device_id dt_match[] = {
+   { .compatible = "qcom,hdmi-tx-8084" },
{ .compatible = "qcom,hdmi-tx-8074" },
{ .compatible = "qcom,hdmi-tx-8960" },
{ .compatible = "qcom,hdmi-tx-8660" },
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 1/3] drm/msm/hdmi: use dynamic allocation for hdmi resources

[Stephane Viau]

Instead of reporting BUG_ON when resources arrays are not
dimensioned correctly, this patch does a dynamic allocation of
these arrays. This is needed for the following patches that add a
regulator for a new target.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/hdmi/hdmi.c | 33 +
 drivers/gpu/drm/msm/hdmi/hdmi.h |  8 
 2 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 062c687..a9092d6 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -65,6 +65,11 @@ static void hdmi_destroy(struct hdmi *hdmi)
if (hdmi->i2c)
hdmi_i2c_destroy(hdmi->i2c);

+   devm_kfree(>pdev->dev, hdmi->pwr_clks);
+   devm_kfree(>pdev->dev, hdmi->hpd_clks);
+   devm_kfree(>pdev->dev, hdmi->pwr_regs);
+   devm_kfree(>pdev->dev, hdmi->hpd_regs);
+
platform_set_drvdata(hdmi->pdev, NULL);
 }

@@ -106,7 +111,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
goto fail;
}

-   BUG_ON(config->hpd_reg_cnt > ARRAY_SIZE(hdmi->hpd_regs));
+   hdmi->hpd_regs = devm_kzalloc(>dev, sizeof(hdmi->hpd_regs[0]) *
+   config->hpd_reg_cnt, GFP_KERNEL);
+   if (!hdmi->hpd_regs) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->hpd_reg_cnt; i++) {
struct regulator *reg;

@@ -122,7 +132,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->hpd_regs[i] = reg;
}

-   BUG_ON(config->pwr_reg_cnt > ARRAY_SIZE(hdmi->pwr_regs));
+   hdmi->pwr_regs = devm_kzalloc(>dev, sizeof(hdmi->pwr_regs[0]) *
+   config->pwr_reg_cnt, GFP_KERNEL);
+   if (!hdmi->pwr_regs) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->pwr_reg_cnt; i++) {
struct regulator *reg;

@@ -138,7 +153,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->pwr_regs[i] = reg;
}

-   BUG_ON(config->hpd_clk_cnt > ARRAY_SIZE(hdmi->hpd_clks));
+   hdmi->hpd_clks = devm_kzalloc(>dev, sizeof(hdmi->hpd_clks[0]) *
+   config->hpd_clk_cnt, GFP_KERNEL);
+   if (!hdmi->hpd_clks) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->hpd_clk_cnt; i++) {
struct clk *clk;

@@ -153,7 +173,12 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->hpd_clks[i] = clk;
}

-   BUG_ON(config->pwr_clk_cnt > ARRAY_SIZE(hdmi->pwr_clks));
+   hdmi->pwr_clks = devm_kzalloc(>dev, sizeof(hdmi->pwr_clks[0]) *
+   config->pwr_clk_cnt, GFP_KERNEL);
+   if (!hdmi->pwr_clks) {
+   ret = -ENOMEM;
+   goto fail;
+   }
for (i = 0; i < config->pwr_clk_cnt; i++) {
struct clk *clk;

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 43e654f..9973e03 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -52,10 +52,10 @@ struct hdmi {

void __iomem *mmio;

-   struct regulator *hpd_regs[2];
-   struct regulator *pwr_regs[2];
-   struct clk *hpd_clks[3];
-   struct clk *pwr_clks[2];
+   struct regulator **hpd_regs;
+   struct regulator **pwr_regs;
+   struct clk **hpd_clks;
+   struct clk **pwr_clks;

struct hdmi_phy *phy;
struct i2c_adapter *i2c;
-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 0/3] drm/msm: Add power supplies config for apq8084

[Stephane Viau]

The first patch makes it easier to have a different number of regulators
depending on the target. It is followed by the addition of the apq8084's
regulator config. Finally, the last patch makes things easier when a new
device needs to be added, especially when they share the same information.

Stephane Viau (3):
  drm/msm/hdmi: use dynamic allocation for hdmi resources
  drm/msm/hdmi: Add HDMI platform config for apq8084
  drm/msm/hdmi: rework hdmi configurations, using dt_match[]

 Documentation/devicetree/bindings/drm/msm/hdmi.txt |   2 +
 drivers/gpu/drm/msm/hdmi/hdmi.c| 144 ++---
 drivers/gpu/drm/msm/hdmi/hdmi.h|   8 +-
 3 files changed, 105 insertions(+), 49 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 4/4] drm/msm/mdp4: add YUV format support

[Stephane Viau]

From: Beeresh Gopal <gbeer...@codeaurora.org>

The patch add support for YUV frame format
for MDP4 platform.

Signed-off-by: Beeresh Gopal 
Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 104 +++---
 1 file changed, 95 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
index 76d0a40..6e3c1ef 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
@@ -17,6 +17,8 @@

 #include "mdp4_kms.h"

+#define DOWN_SCALE_MAX 8
+#define UP_SCALE_MAX   8

 struct mdp4_plane {
struct drm_plane base;
@@ -135,10 +137,6 @@ static void mdp4_plane_set_scanout(struct drm_plane *plane,
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
-   uint32_t iova = msm_framebuffer_iova(fb, mdp4_kms->id, 0);
-
-   DBG("%s: set_scanout: %08x (%u)", mdp4_plane->name,
-   iova, fb->pitches[0]);

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
MDP4_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
@@ -148,11 +146,45 @@ static void mdp4_plane_set_scanout(struct drm_plane 
*plane,
MDP4_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));

-   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), iova);
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
+   msm_framebuffer_iova(fb, mdp4_kms->id, 0));
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
+   msm_framebuffer_iova(fb, mdp4_kms->id, 1));
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
+   msm_framebuffer_iova(fb, mdp4_kms->id, 2));
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
+   msm_framebuffer_iova(fb, mdp4_kms->id, 3));

plane->fb = fb;
 }

+static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
+   enum mdp4_pipe pipe, struct csc_cfg *csc)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) {
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),
+   csc->matrix[i]);
+   }
+
+   for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) {
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),
+   csc->pre_bias[i]);
+
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),
+   csc->post_bias[i]);
+   }
+
+   for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) {
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i),
+   csc->pre_clamp[i]);
+
+   mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i),
+   csc->post_clamp[i]);
+   }
+}
+
 #define MDP4_VG_PHASE_STEP_DEFAULT 0x2000

 static int mdp4_plane_mode_set(struct drm_plane *plane,
@@ -162,6 +194,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
 {
+   struct drm_device *dev = plane->dev;
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
@@ -185,14 +218,59 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);

+   format = to_mdp_format(msm_framebuffer_format(fb));
+
+   if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
+   dev_err(dev->dev, "Width down scaling exceeds limits!\n");
+   return -ERANGE;
+   }
+
+   if (src_h > (crtc_h * DOWN_SCALE_MAX)) {
+   dev_err(dev->dev, "Height down scaling exceeds limits!\n");
+   return -ERANGE;
+   }
+
+   if (crtc_w > (src_w * UP_SCALE_MAX)) {
+   dev_err(dev->dev, "Width up scaling exceeds limits!\n");
+   return -ERANGE;
+   }
+
+   if (crtc_h > (src_h * UP_SCALE_MAX)) {
+   dev_err(dev->dev, "Height up scaling exceeds limits!\n");
+   return -ERANGE;
+   }
+
if (src_w != crtc_w) {
+   uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
-   /* TODO calc phasex_step */
+
+   if (MDP_FORMAT_IS_YUV(format)) {
+   if (crtc_w > src_w)
+   sel_unit = SCALE_PIXEL_RPT;
+  

[PATCH 3/4] drm/msm/mdp5: add NV12 support for MDP5

[Stephane Viau]

This change adds the NV12 format support for public planes.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 213 +++---
 drivers/gpu/drm/msm/msm_fb.c  |   2 +-
 2 files changed, 194 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 9a57e87..263a16b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -274,6 +274,155 @@ static void set_scanout_locked(struct drm_plane *plane,
plane->fb = fb;
 }

+/* Note: mdp5_plane->pipe_lock must be locked */
+static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
+{
+   uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
+~MDP5_PIPE_OP_MODE_CSC_1_EN;
+
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
+}
+
+/* Note: mdp5_plane->pipe_lock must be locked */
+static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
+   struct csc_cfg *csc)
+{
+   uint32_t  i, mode = 0; /* RGB, no CSC */
+   uint32_t *matrix;
+
+   if (unlikely(!csc))
+   return;
+
+   if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
+   mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
+   if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
+   mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
+   mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
+
+   matrix = csc->matrix;
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
+   MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
+
+   for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
+   uint32_t *pre_clamp = csc->pre_clamp;
+   uint32_t *post_clamp = csc->post_clamp;
+
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
+   MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
+   MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
+
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
+   MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
+   MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
+
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
+   MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
+
+   mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
+   MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
+   }
+}
+
+#define PHASE_STEP_SHIFT   21
+#define DOWN_SCALE_RATIO_MAX   32  /* 2^(26-21) */
+
+static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
+{
+   uint32_t unit;
+
+   if (src == 0 || dst == 0)
+   return -EINVAL;
+
+   /*
+* PHASE_STEP_X/Y is coded on 26 bits (25:0),
+* where 2^21 represents the unity "1" in fixed-point hardware design.
+* This leaves 5 bits for the integer part (downscale case):
+*  -> maximum downscale ratio = 0b1_ = 31
+*/
+   if (src > (dst * DOWN_SCALE_RATIO_MAX))
+   return -EOVERFLOW;
+
+   unit = 1 << PHASE_STEP_SHIFT;
+   *out_phase = mult_frac(unit, src, dst);
+
+   return 0;
+}
+
+static int calc_scalex_steps(uint32_t pixel_format, uint32_t src, uint32_t 
dest,
+   uint32_t phasex_steps[2])
+{
+   uint32_t phasex_step;
+   unsigned int hsub;
+   int ret;
+
+   ret = calc_phase_step(src, dest, _step);
+   if (ret)
+   return ret;
+
+   hsub = drm_format_horz_chroma_subsampling(pixel_format);
+
+   phasex_steps[0] = phasex_step;
+   phasex_steps[1] = phasex_step / hsub;
+
+   return 0;
+}
+
+static

[PATCH 2/4] drm/msm/mdp: add common YUV information for MDP4/MDP5

[Stephane Viau]

Both MDP4 and MDP5 share some code as far as YUV support is
concerned. This change adds this information and will be followed
by the actual MDP4 and MDP5 YUV support patches.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |  19 --
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |  19 --
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |   2 -
 drivers/gpu/drm/msm/mdp/mdp_format.c  | 108 +++---
 drivers/gpu/drm/msm/mdp/mdp_kms.h |  24 ++-
 drivers/gpu/drm/msm/msm_fb.c  |   2 +-
 drivers/gpu/drm/msm/msm_kms.h |   2 +
 7 files changed, 154 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
index cbd77bc..0a5c58b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
@@ -175,14 +175,25 @@ irqreturn_t mdp4_irq(struct msm_kms *kms);
 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);

+static inline bool pipe_supports_yuv(enum mdp4_pipe pipe)
+{
+   switch (pipe) {
+   case VG1:
+   case VG2:
+   case VG3:
+   case VG4:
+   return true;
+   default:
+   return false;
+   }
+}
+
 static inline
 uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
uint32_t max_formats)
 {
-   /* TODO when we have YUV, we need to filter supported formats
-* based on pipe_id..
-*/
-   return mdp_get_formats(pixel_formats, max_formats);
+   return mdp_get_formats(pixel_formats, max_formats,
+   !pipe_supports_yuv(pipe_id));
 }

 void mdp4_plane_install_properties(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index dd69c77..49d011e 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -165,14 +165,25 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct 
drm_crtc *crtc);
 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);

+static inline bool pipe_supports_yuv(enum mdp5_pipe pipe)
+{
+   switch (pipe) {
+   case SSPP_VIG0:
+   case SSPP_VIG1:
+   case SSPP_VIG2:
+   case SSPP_VIG3:
+   return true;
+   default:
+   return false;
+   }
+}
+
 static inline
 uint32_t mdp5_get_formats(enum mdp5_pipe pipe, uint32_t *pixel_formats,
uint32_t max_formats)
 {
-   /* TODO when we have YUV, we need to filter supported formats
-* based on pipe id..
-*/
-   return mdp_get_formats(pixel_formats, max_formats);
+   return mdp_get_formats(pixel_formats, max_formats,
+   !pipe_supports_yuv(pipe));
 }

 void mdp5_plane_install_properties(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 533df7c..9a57e87 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -18,8 +18,6 @@

 #include "mdp5_kms.h"

-#define MAX_PLANE  4
-
 struct mdp5_plane {
struct drm_plane base;
const char *name;
diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c 
b/drivers/gpu/drm/msm/mdp/mdp_format.c
index e0a6ffb..f683433 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
@@ -19,7 +20,58 @@
 #include "msm_drv.h"
 #include "mdp_kms.h"

-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt) { \
+static struct csc_cfg csc_convert[CSC_MAX] = {
+   [CSC_RGB2RGB] = {
+   .type = CSC_RGB2RGB,
+   .matrix = {
+   0x0200, 0x, 0x,
+   0x, 0x0200, 0x,
+   0x, 0x, 0x0200
+   },
+   .pre_bias = { 0x0, 0x0, 0x0 },
+   .post_bias ={ 0x0, 0x0, 0x0 },
+   .pre_clamp ={ 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
+   .post_clamp =   { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
+   },
+   [CSC_YUV2RGB] = {
+   .type = CSC_YUV2RGB,
+   .matrix = {
+   0x0254, 0x, 0x0331,
+   0x0254, 0xff37, 0xfe60,
+   0x0254, 0x0409, 0x
+   },
+   .pre_bias = { 0xfff0, 0xff80, 0xff80 },
+   .post_bias ={ 0x00, 0x00, 0x00 },
+   .pre_clamp ={ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
+   .post_clamp =   { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
+   },
+   [CSC_RGB2

[PATCH 1/4] drm/msm/mdp: add register description for YUV support

[Stephane Viau]

YUV support addition implies that sub-modules of the ViG pipes
need to be configured: Color Space Converter (CSC) and Scaler are
the main components used to convert YUV to RGB data. Note that
the output of a pipe has to be in RGB888 format since only this
format is understood by the (layer) mixers.

Generated headers are kept in a separate change to ease the
actual driver's code review.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h  |  44 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h  | 153 +--
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h |  30 +++---
 3 files changed, 205 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index a4a7f8c..b815c9c 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -72,6 +72,18 @@ enum mdp4_cursor_format {
CURSOR_XRGB = 2,
 };

+enum mdp4_frame_format {
+   FRAME_LINEAR = 0,
+   FRAME_TILE_ARGB_4X4 = 1,
+   FRAME_TILE_YCBCR_420 = 2,
+};
+
+enum mdp4_scale_unit {
+   SCALE_FIR = 0,
+   SCALE_MN_PHASE = 1,
+   SCALE_PIXEL_RPT = 2,
+};
+
 enum mdp4_dma {
DMA_P = 0,
DMA_S = 1,
@@ -637,6 +649,8 @@ static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum 
mdp4_pipe i0) { return 0x00

 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 
0x00020018 + 0x1*i0; }

+static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 
0x0002001c + 0x1*i0; }
+
 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 
0x00020040 + 0x1*i0; }
 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK
0x
 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT   0
@@ -720,7 +734,25 @@ static inline uint32_t 
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 }
 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT  0x0002
 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB  0x0004
+#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK
0x0018
+#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT   19
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
+{
+   return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & 
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
+}
 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL
0x0040
+#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c00
+#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT26
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum 
mdp_chroma_samp_type val)
+{
+   return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & 
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK
0x6000
+#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT   29
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum 
mdp4_frame_format val)
+{
+   return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & 
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
+}

 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 
0x00020054 + 0x1*i0; }
 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK   0x00ff
@@ -751,6 +783,18 @@ static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t 
val)
 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 
0x00020058 + 0x1*i0; }
 #define MDP4_PIPE_OP_MODE_SCALEX_EN0x0001
 #define MDP4_PIPE_OP_MODE_SCALEY_EN0x0002
+#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK
0x000c
+#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT   2
+static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit 
val)
+{
+   return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & 
MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
+}
+#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK
0x0030
+#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT   4
+static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit 
val)
+{
+   return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & 
MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
+}
 #define MDP4_PIPE_OP_MODE_SRC_YCBCR0x0200
 #define MDP4_PIPE_OP_MODE_DST_YCBCR0x0400
 #define MDP4_PIPE_OP_MODE_CSC_EN   0x0800
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index e87ef55..26cdfd5 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -88,13 +88,6 @@ enum mdp5_pack_3d {
PACK_3D_COL_INT = 3,
 };

-e

[PATCH 0/4] drm/msm: YUV suppport addition for MDP4 & MDP5

[Stephane Viau]

Hi,

So this set of patches adds YUV support for MDP4 and MDP5. This only concerns
the public planes (using ViG pipes).

The fun part was to rebase things on top of atomic but things worked out fine.
I was able to test this for MDP5 on a 8084 target. I cannot say the same for
MDP4 for which I don't have a build based on atomic yet. The change is pretty
similar to MDP5 though.

Rgds,
Stephane.


Beeresh Gopal (1):
  drm/msm/mdp4: add YUV format support

Stephane Viau (3):
  drm/msm/mdp: add register description for YUV support
  drm/msm/mdp: add common YUV information for MDP4/MDP5
  drm/msm/mdp5: add NV12 support for MDP5

 drivers/gpu/drm/msm/hdmi/hdmi.c   | 149 ++---
 drivers/gpu/drm/msm/hdmi/hdmi.h   |   8 +-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c |   1 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h   |  44 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |  19 ++-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 104 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h   | 153 +++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |  19 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 215 +++---
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h  |  30 +++--
 drivers/gpu/drm/msm/mdp/mdp_format.c  | 108 +--
 drivers/gpu/drm/msm/mdp/mdp_kms.h |  24 +++-
 drivers/gpu/drm/msm/msm_fb.c  |   4 +-
 drivers/gpu/drm/msm/msm_kms.h |   2 +
 14 files changed, 754 insertions(+), 126 deletions(-)

-- 
Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project

[PATCH 3/3] drm/msm: add multiple CRTC and overlay support

[Stephane Viau]

MDP5 currently support one single CRTC with its private pipe.
This change allows the configuration of multiple CRTCs with
the possibility to attach several public planes to these CRTCs.

Signed-off-by: Stephane Viau 
---
 drivers/gpu/drm/msm/Makefile|   1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h |   1 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 265 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 325 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 121 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  48 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  48 ++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 107 +++--
 9 files changed, 804 insertions(+), 125 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 51045b0..135c0e5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -25,6 +25,7 @@ msm-y := \
mdp/mdp4/mdp4_kms.o \
mdp/mdp4/mdp4_plane.o \
mdp/mdp5/mdp5_cfg.o \
+   mdp/mdp5/mdp5_ctl.o \
mdp/mdp5/mdp5_crtc.o \
mdp/mdp5/mdp5_encoder.o \
mdp/mdp5/mdp5_irq.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 00c8271..d0c98f9 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -24,6 +24,7 @@
  */
 extern const struct mdp5_cfg_hw *mdp5_cfg;

+#define MAX_CTL8
 #define MAX_BASES  8
 #define MAX_SMP_BLOCKS 44
 #define MAX_CLIENTS32
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index ebe2e60..fff012a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
@@ -22,16 +23,24 @@
 #include "drm_crtc_helper.h"
 #include "drm_flip_work.h"

+#define SSPP_MAX   (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
+
 struct mdp5_crtc {
struct drm_crtc base;
char name[8];
struct drm_plane *plane;
-   struct drm_plane *planes[8];
+   struct drm_plane *planes[SSPP_MAX];
+   int plane_count;
int id;
bool enabled;

-   /* which mixer/encoder we route output to: */
-   int mixer;
+   /* layer mixer used for this CRTC (+ its lock): */
+#define GET_LM_ID(crtc_id) ((crtc_id == 3) ? 5 : crtc_id)
+   int lm;
+   spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */
+
+   /* CTL used for this CRTC: */
+   void *ctl;

/* if there is a pending flip, these will be non-null: */
struct drm_pending_vblank_event *event;
@@ -58,6 +67,7 @@ struct mdp5_crtc {
struct mdp_irq err;
 };
 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
+#define is_private_plane(mdp5_crtc, drm_plane) (drm_plane == 
(mdp5_crtc)->plane)

 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
 {
@@ -73,26 +83,35 @@ static void request_pending(struct drm_crtc *crtc, uint32_t 
pending)
mdp_irq_register(_kms(crtc)->base, _crtc->vblank);
 }

-static void crtc_flush(struct drm_crtc *crtc)
+#define mdp5_lm_get_flush(lm)  mdp_ctl_flush_mask_lm(lm)
+
+static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 {
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
-   struct mdp5_kms *mdp5_kms = get_kms(crtc);
-   int id = mdp5_crtc->id;
-   uint32_t i, flush = 0;
+
+   DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
+   mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
+}
+
+/*
+ * flush updates, to make sure hw is updated to new scanout fb,
+ * so that we can safely queue unref to current fb (ie. next
+ * vblank we know hw is done w/ previous scanout_fb).
+ */
+static void crtc_flush_all(struct drm_crtc *crtc)
+{
+   struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+   uint32_t i, flush_mask = 0;

for (i = 0; i < ARRAY_SIZE(mdp5_crtc->planes); i++) {
struct drm_plane *plane = mdp5_crtc->planes[i];
-   if (plane) {
-   enum mdp5_pipe pipe = mdp5_plane_pipe(plane);
-   flush |= pipe2flush(pipe);
-   }
+   if (plane)
+   flush_mask |= mdp5_plane_get_flush(plane);
}
-   flush |= mixer2flush(mdp5_crtc->id);
-   flush |= MDP5_CTL_FLUSH_CTL;
+   flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
+   flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);

-   DBG("%s: flush=%08x", mdp5_crtc->name, flush);
-