[PATCH] linux-firmware: Update firmware for Cadence MHDP8546 DP bridge
Update firmware for Cadence MHDP8546 DP bridge to version 2.0.0.
The firmware source code now complies with MISRA2012 and HIS
rules and directives. Also, there are some improvements in AUX
channel communication handling.
Signed-off-by: Swapnil Jakhade
---
WHENCE | 4 ++--
cadence/mhdp8546.bin | Bin 131072 -> 131072 bytes
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/WHENCE b/WHENCE
index 7511677..d4bd8cf 100644
--- a/WHENCE
+++ b/WHENCE
@@ -5003,10 +5003,10 @@ Licence:
--
-Driver: cdns-mhdp - Cadence MHDP DP bridge
+Driver: cdns-mhdp - Cadence MHDP8546 DP bridge
File: cadence/mhdp8546.bin
-Version: 1.2.15
+Version: 2.0.0
Licence: Redistributable. See LICENCE.cadence for details
diff --git a/cadence/mhdp8546.bin b/cadence/mhdp8546.bin
index
40097e0ec908ab5c4b54803f4b99519ced7a5e3d..2f85f57c506e3347c1f4670b9a0b96e415d2eaaa
100755
GIT binary patch
literal 131072
zcmeFZd03NI_Bj47Nyu_lf=ZEqCV?m-b^_XJtrh|l*|b2Fy0rtrAmUQBbabqcHg*nGZ>=#f6y=tt-wzrmahLicB+gVF{5Eq?gSMTS-)H9Y&+qv@
z-{<-Gc)8oT+qvhSd+s^sjX;253Z+tsVOaYL3{yk={Xc|Z-%bvCS)DUko{cF6*z`d*
zdyqwBA(58rdyemgi^)mD=_J;X(J8uq-v#F
z{&$Xz4;I{lF239K3j9rg?*H}Q#U!jvMU=Kyl(k8;?Jbevps4IU5~K;naUW
z7rArt9tumx1T6cnbNio^Xt0DaXzJ#%(fom
z=$nvkox?`wLH-Mf*F$U%!!SGa-3npIpN+1W!bX1ta1oF`3h^~44}FS_Rzo=EkEuha
zveBCZFtsn_-H<;9aCQjSAbbm<1;Q=}JgDD14d5Uh0ezkh!PKXr?F9%NS@_B@bz(54
zZh^WoD04EChZ!K=CWo;Q8=d9LM#~i#hC(om2Xp;G!bbb1Vb~N10T6;9$RUJ6
zsDXY~iP`7|So{1S2yz$?)~$v$q=o_>03W_k-U4Ooq2Hr(V0cNT^TVGTfoSOw(UAv8)b
z?B-7}b;)F)L1^>ZeE0hA>{m=Abg
z1$CRB#nik7KyR>@0T5?FP(%GBSkDN=VbDehp$6z(4d-Yx&}9J3$qjwlp}Y~wK7zBd
z82UR6VHe~LkmtdiK7#r(f{mVnv(fD-Y;+>@(F`zHDx5!VJxgG&8cbaQWBw7!7sq1i
zT@Wys`!S%CEZD;s=p#N2Vwg)0&{0JqroO<@2GBw&#
[PATCH v11 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../display/bridge/cdns,mhdp8546.yaml | 169 ++
1 file changed, 169 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
new file mode 100644
index ..74d675fc6e7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP8546 bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+maxItems: 1
+description:
+ phandle to the DisplayPort PHY.
+
+ phy-names:
+items:
+ - const: dpphy
+
+ power-domains:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ First input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Second input port representing the DP bridge input.
+
+ port@2:
+type: object
+description:
+ Third input port representing the DP bridge input.
+
+ port@3:
+type: object
+description:
+ Fourth input port representing the DP bridge input.
+
+ port@4:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@4
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+else:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - phy-names
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+phy-names = "dpphy";
+interrupts = ;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+};
+};
+
+port@4 {
+reg = <4>;
+dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+};
+};
+};
+};
+};
+...
--
2.26.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v11 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge
Add a new DRM bridge driver for Cadence MHDP8546 DPTX IP used in TI J721E
SoC. MHDP DPTX IP is the component that complies with VESA DisplayPort (DP)
and embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and outputs it encoded in DP
format. Currently, it supports only SST mode.
Co-developed-by: Tomi Valkeinen
Signed-off-by: Tomi Valkeinen
Co-developed-by: Jyri Sarha
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig|2 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +
drivers/gpu/drm/bridge/cadence/Makefile |3 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 2522 +
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 399 +++
6 files changed, 2938 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig
create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3e11af4e9f63..ef91646441b1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -241,6 +241,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
+source "drivers/gpu/drm/bridge/cadence/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c589a6a7cbe1..2b3aff104e46 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -25,4 +25,5 @@ obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
+obj-y += cadence/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
new file mode 100644
index ..f49d77eb7814
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_CDNS_MHDP8546
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and outputs it encoded
+ in DP format.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
new file mode 100644
index ..676739cdf5e6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
+cdns-mhdp8546-y := cdns-mhdp8546-core.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
new file mode 100644
index ..7b1bd5d10923
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -0,0 +1,2522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP8546 DP bridge driver.
+ *
+ * Copyright (C) 2020 Cadence Design Systems, Inc.
+ *
+ * Authors: Quentin Schulz
+ * Swapnil Jakhade
+ * Yuti Amonkar
+ * Tomi Valkeinen
+ * Jyri Sarha
+ *
+ * TODO:
+ * - Implement optimized mailbox communication using mailbox interrupts
+ * - Add support for power management
+ * - Add support for features like audio, MST and fast link training
+ * - Implement request_fw_cancel to handle HW_STATE
+ * - Fix asynchronous loading of firmware implementation
+ * - Add DRM helper function for cdns_mhdp_lower_link_rate
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp8546-core.h"
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ in
[PATCH v11 0/3] drm: Add support for Cadence MHDP8546 DPI/DP bridge and J721E wrapper.
3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. Swapnil Jakhade (2): drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge drm: bridge: cdns-mhdp8546: Add TI J721E wrapper Yuti Amonkar (1): dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings .../display/bridge/cdns,mhdp8546.yaml | 169 ++ drivers/gpu/drm/bridge/Kconfig|2 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/cadence/Kconfig| 24 + drivers/gpu/drm/bridge/cadence/Makefile |4 + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 2532 + .../drm/bridge/cadence/cdns-mhdp8546-core.h | 400 +++ .../drm/bridge/cadence/cdns-mhdp8546-j721e.c | 78 + .../drm/bridge/cadence/cdns-mhdp8546-j721e.h | 19 + 9 files changed, 3229 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h -- 2.26.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v11 3/3] drm: bridge: cdns-mhdp8546: Add TI J721E wrapper
Add J721E wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/cadence/Kconfig| 13
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 10 +++
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-j721e.c | 78 +++
.../drm/bridge/cadence/cdns-mhdp8546-j721e.h | 19 +
6 files changed, 122 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index f49d77eb7814..511d67b16d14 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -9,3 +9,16 @@ config DRM_CDNS_MHDP8546
bridge and is meant to be directly embedded in a SoC.
It takes a DPI stream as input and outputs it encoded
in DP format.
+
+if DRM_CDNS_MHDP8546
+
+config DRM_CDNS_MHDP8546_J721E
+ depends on ARCH_K3_J721E_SOC || COMPILE_TEST
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721E Display Port and sets up the
+ clock and data muxes.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 676739cdf5e6..8f647991b374 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o
+cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 7b1bd5d10923..621ebdbff8a3 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -50,6 +50,8 @@
#include "cdns-mhdp8546-core.h"
+#include "cdns-mhdp8546-j721e.h"
+
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
{
int ret, empty;
@@ -2496,6 +2498,14 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP8546_J721E
+ { .compatible = "ti,j721e-mhdp8546",
+ .data = &(const struct cdns_mhdp_platform_info) {
+ .timings = _ti_j721e_bridge_timings,
+ .ops = _ti_j721e_ops,
+ },
+ },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
index c0fff78d15be..5897a85e3159 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
@@ -341,6 +341,7 @@ struct cdns_mhdp_platform_info {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
new file mode 100644
index ..dfe1b59514f7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP8546 DP wrapper
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+ */
+
+#include
+#include
+
+#include "cdns-mhdp8546-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1
[PATCH v10 0/3] drm: Add support for Cadence MHDP8546 DPI/DP bridge and J721E wrapper.
pdated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. Swapnil Jakhade (2): drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge drm: bridge: cdns-mhdp8546: Add TI J721E wrapper Yuti Amonkar (1): dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings .../display/bridge/cdns,mhdp8546.yaml | 154 + drivers/gpu/drm/bridge/Kconfig|2 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/cadence/Kconfig| 24 + drivers/gpu/drm/bridge/cadence/Makefile |4 + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 2532 + .../drm/bridge/cadence/cdns-mhdp8546-core.h | 400 +++ .../drm/bridge/cadence/cdns-mhdp8546-j721e.c | 78 + .../drm/bridge/cadence/cdns-mhdp8546-j721e.h | 19 + 9 files changed, 3214 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h -- 2.26.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v10 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../display/bridge/cdns,mhdp8546.yaml | 154 ++
1 file changed, 154 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
new file mode 100644
index ..a21a4bfe15cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP8546 bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+maxItems: 1
+description:
+ phandle to the DisplayPort PHY.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ First input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Second input port representing the DP bridge input.
+
+ port@2:
+type: object
+description:
+ Third input port representing the DP bridge input.
+
+ port@3:
+type: object
+description:
+ Fourth input port representing the DP bridge input.
+
+ port@4:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@4
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+else:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+};
+};
+
+port@4 {
+reg = <4>;
+dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+};
+};
+};
+};
+};
+...
--
2.26.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v10 3/3] drm: bridge: cdns-mhdp8546: Add TI J721E wrapper
Add J721E wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/cadence/Kconfig| 13
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 10 +++
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-j721e.c | 78 +++
.../drm/bridge/cadence/cdns-mhdp8546-j721e.h | 19 +
6 files changed, 122 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index f49d77eb7814..511d67b16d14 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -9,3 +9,16 @@ config DRM_CDNS_MHDP8546
bridge and is meant to be directly embedded in a SoC.
It takes a DPI stream as input and outputs it encoded
in DP format.
+
+if DRM_CDNS_MHDP8546
+
+config DRM_CDNS_MHDP8546_J721E
+ depends on ARCH_K3_J721E_SOC || COMPILE_TEST
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721E Display Port and sets up the
+ clock and data muxes.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 676739cdf5e6..8f647991b374 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o
+cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 7b1bd5d10923..621ebdbff8a3 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -50,6 +50,8 @@
#include "cdns-mhdp8546-core.h"
+#include "cdns-mhdp8546-j721e.h"
+
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
{
int ret, empty;
@@ -2496,6 +2498,14 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP8546_J721E
+ { .compatible = "ti,j721e-mhdp8546",
+ .data = &(const struct cdns_mhdp_platform_info) {
+ .timings = _ti_j721e_bridge_timings,
+ .ops = _ti_j721e_ops,
+ },
+ },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
index c0fff78d15be..5897a85e3159 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
@@ -341,6 +341,7 @@ struct cdns_mhdp_platform_info {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
new file mode 100644
index ..dfe1b59514f7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP8546 DP wrapper
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+ */
+
+#include
+#include
+
+#include "cdns-mhdp8546-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1
[PATCH v10 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge
Add a new DRM bridge driver for Cadence MHDP8546 DPTX IP used in TI J721E
SoC. MHDP DPTX IP is the component that complies with VESA DisplayPort (DP)
and embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and outputs it encoded in DP
format. Currently, it supports only SST mode.
Co-developed-by: Tomi Valkeinen
Signed-off-by: Tomi Valkeinen
Co-developed-by: Jyri Sarha
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig|2 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +
drivers/gpu/drm/bridge/cadence/Makefile |3 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 2522 +
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 399 +++
6 files changed, 2938 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig
create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3e11af4e9f63..ef91646441b1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -241,6 +241,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
+source "drivers/gpu/drm/bridge/cadence/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c589a6a7cbe1..2b3aff104e46 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -25,4 +25,5 @@ obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
+obj-y += cadence/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
new file mode 100644
index ..f49d77eb7814
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_CDNS_MHDP8546
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and outputs it encoded
+ in DP format.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
new file mode 100644
index ..676739cdf5e6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
+cdns-mhdp8546-y := cdns-mhdp8546-core.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
new file mode 100644
index ..7b1bd5d10923
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -0,0 +1,2522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP8546 DP bridge driver.
+ *
+ * Copyright (C) 2020 Cadence Design Systems, Inc.
+ *
+ * Authors: Quentin Schulz
+ * Swapnil Jakhade
+ * Yuti Amonkar
+ * Tomi Valkeinen
+ * Jyri Sarha
+ *
+ * TODO:
+ * - Implement optimized mailbox communication using mailbox interrupts
+ * - Add support for power management
+ * - Add support for features like audio, MST and fast link training
+ * - Implement request_fw_cancel to handle HW_STATE
+ * - Fix asynchronous loading of firmware implementation
+ * - Add DRM helper function for cdns_mhdp_lower_link_rate
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp8546-core.h"
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ in
[PATCH v9 3/3] drm: bridge: cdns-mhdp8546: Add TI J721E wrapper
Add J721E wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/cadence/Kconfig| 13
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 10 +++
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 1 +
.../drm/bridge/cadence/cdns-mhdp8546-j721e.c | 78 +++
.../drm/bridge/cadence/cdns-mhdp8546-j721e.h | 19 +
6 files changed, 122 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index f49d77eb7814..511d67b16d14 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -9,3 +9,16 @@ config DRM_CDNS_MHDP8546
bridge and is meant to be directly embedded in a SoC.
It takes a DPI stream as input and outputs it encoded
in DP format.
+
+if DRM_CDNS_MHDP8546
+
+config DRM_CDNS_MHDP8546_J721E
+ depends on ARCH_K3_J721E_SOC || COMPILE_TEST
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721E Display Port and sets up the
+ clock and data muxes.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 676739cdf5e6..8f647991b374 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o
+cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 14be6f370d6e..5dc83b2e3603 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -50,6 +50,8 @@
#include "cdns-mhdp8546-core.h"
+#include "cdns-mhdp8546-j721e.h"
+
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
{
int ret, empty;
@@ -2522,6 +2524,14 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP8546_J721E
+ { .compatible = "ti,j721e-mhdp8546",
+ .data = &(const struct cdns_mhdp_platform_info) {
+ .timings = _ti_j721e_bridge_timings,
+ .ops = _ti_j721e_ops,
+ },
+ },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
index 14ba7431fab8..d2183f3f3263 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
@@ -344,6 +344,7 @@ struct cdns_mhdp_platform_info {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
new file mode 100644
index ..dfe1b59514f7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP8546 DP wrapper
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+ */
+
+#include
+#include
+
+#include "cdns-mhdp8546-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1
[PATCH v9 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../display/bridge/cdns,mhdp8546.yaml | 154 ++
1 file changed, 154 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
new file mode 100644
index ..a21a4bfe15cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP8546 bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+maxItems: 1
+description:
+ phandle to the DisplayPort PHY.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ First input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Second input port representing the DP bridge input.
+
+ port@2:
+type: object
+description:
+ Third input port representing the DP bridge input.
+
+ port@3:
+type: object
+description:
+ Fourth input port representing the DP bridge input.
+
+ port@4:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@4
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+else:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+};
+};
+
+port@4 {
+reg = <4>;
+dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+};
+};
+};
+};
+};
+...
--
2.26.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge
Add a new DRM bridge driver for Cadence MHDP8546 DPTX IP used in TI J721E
SoC. MHDP DPTX IP is the component that complies with VESA DisplayPort (DP)
and embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and outputs it encoded in DP
format. Currently, it supports only SST mode.
Co-developed-by: Tomi Valkeinen
Signed-off-by: Tomi Valkeinen
Co-developed-by: Jyri Sarha
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
---
drivers/gpu/drm/bridge/Kconfig|2 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +
drivers/gpu/drm/bridge/cadence/Makefile |3 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 2548 +
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 402 +++
6 files changed, 2967 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/Kconfig
create mode 100644 drivers/gpu/drm/bridge/cadence/Makefile
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3e11af4e9f63..ef91646441b1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -241,6 +241,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
+source "drivers/gpu/drm/bridge/cadence/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c589a6a7cbe1..2b3aff104e46 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -25,4 +25,5 @@ obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
+obj-y += cadence/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
new file mode 100644
index ..f49d77eb7814
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_CDNS_MHDP8546
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and outputs it encoded
+ in DP format.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
new file mode 100644
index ..676739cdf5e6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
+cdns-mhdp8546-y := cdns-mhdp8546-core.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
new file mode 100644
index ..14be6f370d6e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -0,0 +1,2548 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP8546 DP bridge driver.
+ *
+ * Copyright (C) 2020 Cadence Design Systems, Inc.
+ *
+ * Authors: Quentin Schulz
+ * Swapnil Jakhade
+ * Yuti Amonkar
+ * Tomi Valkeinen
+ * Jyri Sarha
+ *
+ * TODO:
+ * - Implement optimized mailbox communication using mailbox interrupts
+ * - Add support for power management
+ * - Add support for features like audio, MST and fast link training
+ * - Implement request_fw_cancel to handle HW_STATE
+ * - Fix asynchronous loading of firmware implementation
+ * - Add DRM helper function for cdns_mhdp_lower_link_rate
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp8546-core.h"
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_i
[PATCH v9 0/3] drm: Add support for Cadence MHDP8546 DPI/DP bridge and J721E wrapper.
This patch series adds new DRM bridge driver for Cadence MHDP8546 DPI/DP bridge. The Cadence Display Port IP is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface, Display Port). Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. The MHDP bridge driver currently implements Single Stream Transport (SST) mode. It also adds Texas Instruments j721e SoC specific wrapper and adds the device tree bindings in YAML format. Some of the features that will be added later on include (but are not limited to): - Power Management (PM) support: We will implement the PM functions in next stage once there will be a stable driver in upstream - Audio and MST support The patch series has three patches in the below sequence: 1. 0001-dt-bindings-drm-bridge-Document-Cadence-MHDP8546-.patch Documents the bindings in yaml format. 2. 0002-drm-bridge-Add-support-for-Cadence-MHDP8546-DPI-D.patch This patch adds new DRM bridge driver for Cadence MHDP Display Port. The patch implements support for single stream transport mode. 3. 0003-drm-bridge-cdns-mhdp8546-Add-TI-J721E-wrapper.patch Adds Texas Instruments (TI) j721e wrapper for MHDP. The wrapper configures MHDP clocks and muxes as required by SoC. This patch series is dependent on PHY patch series [1] to add new PHY APIs to get/set PHY attributes which is under review and not merged yet. [1] https://lkml.org/lkml/2020/8/24/1586 Version History: v9: In 1/3 - Rename bindings file to cdns,mhdp8546.yaml. - Minor changes replacing mhdp with mhdp8546 to include IP part number. - Add 4 input ports and one output port supporting MST for DP bridge. In 2/3 - Add driver files in cadence folder under drm/bridge. - Rename driver files to include part number mhdp8546. - Remove link training calls from atomic_check. - Support DRM_BRIDGE_OP_HPD with hpd_enable, hpd_disable callbacks. - Remove unnecessary fw states. - Fix other review comments for v8 patches. In 3/3 - Add input_bus_flags specific for J721E in drm_bridge_timings. - Fix other review comments for v8 patches. v8: In 1/3 - Fix error reported by dt_binding_check - Fix indent in the example - Fix other comments given for v7 patches. In 2/3: - Implement bridge connector operations .get_edid() and .detect(). - Make connector creation optional based on DRM_BRIDGE_ATTACH_NO_CONNECTOR flag. - Fix other comments given for v7 patches. In 3/3 - Fix comments given for v7 patches. v7: In 1/3 - No change In 2/3 - Switch to atomic versions of bridge operations - Implement atomic_check() handler to perform all validation checks - Add struct cdns_mhdp_bridge_state with subclassed bridge state - Use PHY API[1] to get PHY attributes instead of reading from PHY DT node - Updated HPD handling and link configuration in IRQ handler - Add "link_mutex" protecting the access to all the link parameters - Add support to check and print FW version information - Add separate function to initialize host parameters to simplify probe - Use waitqueue instead of manual loop in cdns_mhdp_remove - Add forward declarations and header files in cdns-mhdp-core.h file - Use bool instead of single bit values in struct cdns_mhdp_device - Fix for other minor comments given for v6 patches In 3/3 - Use of_device_is_compatible() to set compatible string specific values - Move mhdp_ti_j721e_ops structure to cdns-mhdp-j721e.c - Remove duplicate Copyright message - Remove CONFIG_DRM_CDNS_MHDP_J721E check - Add Reviewed-by: Laurent Pinchart v6: - Added minor fixes in YAML file. - Added Reviewed-by: Laurent Pinchart to the YAML patch. - Removed all the FIXME comments which are invalid in drm driver. - Reduced the mailbox timeout from 5s to 2s. - Added Reviewed-by: Tomi Valkeinen to the 003-drm-mhdp-add-j721e-wrapper patch. - Added Signed-off all the module authors. - Fixed the compiler error Reported-by: kbuild test robot . v5: - Added Signed-off-by: Jyri Sarha tag to the code patches. v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Add Reviewed-by: Rob Herring tag to the Document Cadence MHDP bridge bindings patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. Swapnil Jakhade (2): drm: bridge: Add support for Cadence MHDP8
[PATCH v8 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
Add a new DRM bridge driver for Cadence MHDP DPTX IP used in TI J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and outputs it encoded in DP
format. Currently, it supports only SST mode.
Co-developed-by: Tomi Valkeinen
Signed-off-by: Tomi Valkeinen
Co-developed-by: Jyri Sarha
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |2 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2547 +++
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 396
4 files changed, 2956 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 43271c21d3fc..6a4c324302a8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and outputs it encoded
+ in DP format.
+
config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index d63d4b7e4347..7046bf077603 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
+cdns-mhdp-y := cdns-mhdp-core.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
new file mode 100644
index ..d47187ab358b
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -0,0 +1,2547 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright (C) 2020 Cadence Design Systems, Inc.
+ *
+ * Authors: Quentin Schulz
+ * Swapnil Jakhade
+ * Yuti Amonkar
+ * Tomi Valkeinen
+ * Jyri Sarha
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp-core.h"
+
+static DECLARE_WAIT_QUEUE_HEAD(fw_load_wq);
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in mailbox is not what we want
[PATCH v8 3/3] drm: bridge: cdns-mhdp: Add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig | 13 +
drivers/gpu/drm/bridge/Makefile | 2 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 15 +
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 1 +
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 72
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 19 +++
6 files changed, 122 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 6a4c324302a8..8c1738653b7e 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -38,6 +38,19 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and outputs it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ depends on ARCH_K3_J721E_SOC
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 7046bf077603..be92ebf620b6 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,8 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
cdns-mhdp-y := cdns-mhdp-core.o
+cdns-mhdp-$(CONFIG_DRM_CDNS_MHDP_J721E) += cdns-mhdp-j721e.o
+
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
index d47187ab358b..53c25f6ecddf 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -42,6 +42,8 @@
#include "cdns-mhdp-core.h"
+#include "cdns-mhdp-j721e.h"
+
static DECLARE_WAIT_QUEUE_HEAD(fw_load_wq);
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
@@ -1702,6 +1704,16 @@ static int cdns_mhdp_connector_init(struct
cdns_mhdp_device *mhdp)
conn->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH;
+ if (of_device_is_compatible(mhdp->dev->of_node, "ti,j721e-mhdp8546"))
+ /*
+* DP is internal to J7 SoC and we need to use DRIVE_POSEDGE
+* in the display controller. This is achieved for the time being
+* by defining SAMPLE_NEGEDGE here.
+*/
+ conn->display_info.bus_flags |=
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
+
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
DRM_ERROR("Failed to attach connector to encoder\n");
@@ -2521,6 +2533,9 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+ { .compatible = "ti,j721e-mhdp8546", .data = _ti_j721e_ops },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
index bd97a7aeb28b..d40a0f8615a4 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
@@ -343,6 +343,7 @@ struct cdns_mhdp_bridge_state {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index ..cc33c9afb5bb
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#define
[PATCH v8 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM bridge driver for Cadence MHDP DPI/DP bridge. The Cadence Display Port IP is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface, Display Port). Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. The MHDP bridge driver currently implements Single Stream Transport (SST) mode. It also adds Texas Instruments j721e SoC specific wrapper and adds the device tree bindings in YAML format. Some of the features that will be added later on include (but are not limited to): - Power Management (PM) support: We will implement the PM functions in next stage once there will be a stable driver in upstream - Audio and MST support The patch series has three patches in the below sequence: 1. 0001-dt-bindings-drm-bridge-Document-Cadence-MHDP-brid.patch Documents the bindings in yaml format. 2. 0002-drm-bridge-Add-support-for-Cadence-MHDP-DPI-DP-br.patch This patch adds new DRM bridge driver for Cadence MHDP Display Port. The patch implements support for single stream transport mode. 3. 0003-drm-bridge-cdns-mhdp-Add-j721e-wrapper.patch Adds Texas Instruments (TI) j721e wrapper for MHDP. The wrapper configures MHDP clocks and muxes as required by SoC. This patch series is dependent on PHY patch series [1] to add new PHY APIs to get/set PHY attributes which is under review and not merged yet. [1] https://lkml.org/lkml/2020/7/17/158 Version History: v8: In 1/3 - Fix error reported by dt_binding_check - Fix indent in the example - Fix other comments given for v7 patches. In 2/3: - Implement bridge connector operations .get_edid() and .detect(). - Make connector creation optional based on DRM_BRIDGE_ATTACH_NO_CONNECTOR flag. - Fix other comments given for v7 patches. In 3/3 - Fix comments given for v7 patches. v7: In 1/3 - No change In 2/3 - Switch to atomic versions of bridge operations - Implement atomic_check() handler to perform all validation checks - Add struct cdns_mhdp_bridge_state with subclassed bridge state - Use PHY API[1] to get PHY attributes instead of reading from PHY DT node - Updated HPD handling and link configuration in IRQ handler - Add "link_mutex" protecting the access to all the link parameters - Add support to check and print FW version information - Add separate function to initialize host parameters to simplify probe - Use waitqueue instead of manual loop in cdns_mhdp_remove - Add forward declarations and header files in cdns-mhdp-core.h file - Use bool instead of single bit values in struct cdns_mhdp_device - Fix for other minor comments given for v6 patches In 3/3 - Use of_device_is_compatible() to set compatible string specific values - Move mhdp_ti_j721e_ops structure to cdns-mhdp-j721e.c - Remove duplicate Copyright message - Remove CONFIG_DRM_CDNS_MHDP_J721E check - Add Reviewed-by: Laurent Pinchart v6: - Added minor fixes in YAML file. - Added Reviewed-by: Laurent Pinchart to the YAML patch. - Removed all the FIXME comments which are invalid in drm driver. - Reduced the mailbox timeout from 5s to 2s. - Added Reviewed-by: Tomi Valkeinen to the 003-drm-mhdp-add-j721e-wrapper patch. - Added Signed-off all the module authors. - Fixed the compiler error Reported-by: kbuild test robot . v5: - Added Signed-off-by: Jyri Sarha tag to the code patches. v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Add Reviewed-by: Rob Herring tag to the Document Cadence MHDP bridge bindings patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. Swapnil Jakhade (2): drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm: bridge: cdns-mhdp: Add j721e wrapper Yuti Amonkar (1): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings .../bindings/display/bridge/cdns,mhdp.yaml| 139 + drivers/gpu/drm/bridge/Kconfig| 24 + drivers/gpu/drm/bridge/Makefile |4 + drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2562 + drivers/gpu/drm/bridge/cdns-mhdp-core.h | 397 +++ drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 72 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 19 + 7 files changed, 3217 insertions(+) create mode 100644 Documentation/devicetree/bindin
[PATCH v8 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/cdns,mhdp.yaml| 139 ++
1 file changed, 139 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index ..dabccefe0983
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+maxItems: 1
+description:
+ phandle to the DisplayPort PHY.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ Input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+else:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+};
+};
+
+port@1 {
+reg = <1>;
+dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+};
+};
+};
+};
+};
+...
--
2.26.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
Add a new DRM bridge driver for Cadence MHDP DPTX IP used in TI J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and outputs it encoded in DP
format. Currently, it supports only SST mode.
Co-developed-by: Tomi Valkeinen
Signed-off-by: Tomi Valkeinen
Co-developed-by: Jyri Sarha
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |2 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2493 +++
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 396
4 files changed, 2902 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 43271c21d3fc..6a4c324302a8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and outputs it encoded
+ in DP format.
+
config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index d63d4b7e4347..0080a9f80f29 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
+cdns-mhdp-objs := cdns-mhdp-core.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
new file mode 100644
index ..b16c5503cef1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -0,0 +1,2493 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp-core.h"
+
+static DECLARE_WAIT_QUEUE_HEAD(fw_load_wq);
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int ret, empty;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+empty, !empty, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in mailbox is not what we want, we need to
+* clear the mailbox by reading its contents.
[PATCH v7 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM bridge driver for Cadence MHDP DPI/DP bridge. The Cadence Display Port IP is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface, Display Port). Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. The MHDP bridge driver currently implements Single Stream Transport (SST) mode. It also adds Texas Instruments j721e SoC specific wrapper and adds the device tree bindings in YAML format. Some of the features that will be added later on include (but are not limited to): - Power Management (PM) support: We will implement the PM functions in next stage once there will be a stable driver in upstream - Converting to connector bridge operations: This is not supported currently because of dependency on TIDSS driver which has some limitations in supporting new model - Audio and MST support The patch series has three patches in the below sequence: 1. 0001-dt-bindings-drm-bridge-Document-Cadence-MHDP-brid.patch Documents the bindings in yaml format. 2. 0002-drm-bridge-Add-support-for-Cadence-MHDP-DPI-DP-br.patch This patch adds new DRM bridge driver for Cadence MHDP Display Port. The patch implements support for single stream transport mode. 3. 0003-drm-bridge-cdns-mhdp-Add-j721e-wrapper.patch Adds Texas Instruments (TI) j721e wrapper for MHDP. The wrapper configures MHDP clocks and muxes as required by SoC. This patch series is dependent on PHY patch series [1] to add new PHY APIs to get/set PHY attributes which is under review and not merged yet. [1] https://lkml.org/lkml/2020/7/17/158 Version History: v7: In 1/3 - No change In 2/3 - Switch to atomic versions of bridge operations - Implement atomic_check() handler to perform all validation checks - Add struct cdns_mhdp_bridge_state with subclassed bridge state - Use PHY API[1] to get PHY attributes instead of reading from PHY DT node - Updated HPD handling and link configuration in IRQ handler - Add "link_mutex" protecting the access to all the link parameters - Add support to check and print FW version information - Add separate function to initialize host parameters to simplify probe - Use waitqueue instead of manual loop in cdns_mhdp_remove - Add forward declarations and header files in cdns-mhdp-core.h file - Use bool instead of single bit values in struct cdns_mhdp_device - Fix for other minor comments given for v6 patches In 3/3 - Use of_device_is_compatible() to set compatible string specific values - Move mhdp_ti_j721e_ops structure to cdns-mhdp-j721e.c - Remove duplicate Copyright message - Remove CONFIG_DRM_CDNS_MHDP_J721E check - Add Reviewed-by: Laurent Pinchart v6: - Added minor fixes in YAML file. - Added Reviewed-by: Laurent Pinchart to the YAML patch. - Removed all the FIXME comments which are invalid in drm driver. - Reduced the mailbox timeout from 5s to 2s. - Added Reviewed-by: Tomi Valkeinen to the 003-drm-mhdp-add-j721e-wrapper patch. - Added Signed-off all the module authors. - Fixed the compiler error Reported-by: kbuild test robot . v5: - Added Signed-off-by: Jyri Sarha tag to the code patches. v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Add Reviewed-by: Rob Herring tag to the Document Cadence MHDP bridge bindings patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. Swapnil Jakhade (2): drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm: bridge: cdns-mhdp: Add j721e wrapper Yuti Amonkar (1): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings .../bindings/display/bridge/cdns,mhdp.yaml| 127 + drivers/gpu/drm/bridge/Kconfig| 24 + drivers/gpu/drm/bridge/Makefile |7 + drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2508 + drivers/gpu/drm/bridge/cdns-mhdp-core.h | 397 +++ drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 75 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 19 + 7 files changed, 3157 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h create mode 100644 drivers/gpu/drm/bridge/cdns-mh
[PATCH v7 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/cdns,mhdp.yaml| 127 ++
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index ..cdf5760d4ec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+description:
+ phandle to the DisplayPort PHY.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ Input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+ };
+ };
+};
+};
+...
--
2.26.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 3/3] drm: bridge: cdns-mhdp: Add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig | 13
drivers/gpu/drm/bridge/Makefile | 5 ++
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 15 +
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 1 +
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 75
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 19 ++
6 files changed, 128 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 6a4c324302a8..8c1738653b7e 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -38,6 +38,19 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and outputs it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ depends on ARCH_K3_J721E_SOC
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_CHRONTEL_CH7033
tristate "Chrontel CH7033 Video Encoder"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 0080a9f80f29..f81d606e9598 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -2,6 +2,11 @@
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
cdns-mhdp-objs := cdns-mhdp-core.o
+
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ cdns-mhdp-objs += cdns-mhdp-j721e.o
+endif
+
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
index b16c5503cef1..eeb33c54334f 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -38,6 +38,8 @@
#include "cdns-mhdp-core.h"
+#include "cdns-mhdp-j721e.h"
+
static DECLARE_WAIT_QUEUE_HEAD(fw_load_wq);
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
@@ -1691,6 +1693,16 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
conn->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH;
+ if (of_device_is_compatible(mhdp->dev->of_node, "ti,j721e-mhdp8546"))
+ /*
+* DP is internal to J7 SoC and we need to use DRIVE_POSEDGE
+* in the display controller. This is achieved for the time being
+* by defining SAMPLE_NEGEDGE here.
+*/
+ conn->display_info.bus_flags |=
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
+
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
dev_err(mhdp->dev, "failed to attach connector to encoder\n");
@@ -2470,6 +2482,9 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+ { .compatible = "ti,j721e-mhdp8546", .data = _ti_j721e_ops },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
index d1bfcdef4249..4e176698caca 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
@@ -343,6 +343,7 @@ struct cdns_mhdp_bridge_state {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index ..7555c217c9a0
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SEC
