RE: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
Hi Joel,
We have released related datasheet and update these registers
description.
SCU300: Clock Selection Register
...
10:8 Soc display clock selection
000b: D-PLL
001b: Reserved
010b: 40MHz from USB 2.0 port1 PHY
011b: GPIOC6
100b: Reserved
101b: E-PLL divided by SCU308[17:12]
110b: M-PLL divided by SCU308[17:12]
111b: H-PLL divided by SCU308[17:12]
SCU308: Clock Selection Register Set 3
17:12 Soc display clock divider selection
00b: div 1
011011b: div 16
Thanks,
By Tommy
> -Original Message-
> From: Tommy Huang
> Sent: Tuesday, April 26, 2022 4:28 PM
> To: Joel Stanley
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: RE: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
>
>
>
> > -Original Message-
> > From: Joel Stanley
> > Sent: Tuesday, April 26, 2022 3:48 PM
> > To: Tommy Huang
> > Cc: David Airlie ; Daniel Vetter ;
> > Rob Herring ; Andrew Jeffery ;
> > linux-aspeed ; open list:DRM DRIVERS
> > ; devicetree
> > ; Linux ARM
> > ; Linux Kernel Mailing List
> > ; BMC-SW
> > Subject: Re: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
> >
> > On Fri, 4 Mar 2022 at 06:32, Tommy Haung
>
> > wrote:
> > >
> > > Update the aspeed_gfx_set_clk with display width.
> > > At AST2600, the display clock could be coming from HPLL clock / 16 =
> > > 75MHz. It would fit 1024x768@70Hz.
> > > Another chip will still keep 800x600.
> > >
> > > Signed-off-by: Tommy Haung
> > > ---
> > > drivers/gpu/drm/aspeed/aspeed_gfx.h | 12 ++
> > > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 29
> > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> |
> > > 16 +++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14
> > > +++-
> > > 4 files changed, 60 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > index eb4c267cde5e..c7aefee0657a 100644
> > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > @@ -109,11 +109,15 @@ int aspeed_gfx_create_output(struct drm_device
> > *drm);
> > > #define CRT_THROD_HIGH(x) ((x) << 8)
> > >
> > > /* SCU control */
> > > -#define SCU_G6_CLK_COURCE 0x300
> > > +#define G6_CLK_SOURCE 0x300
> > > +#define G6_CLK_SOURCE_MASK (BIT(8) | BIT(9) | BIT(10))
> > > +#define G6_CLK_SOURCE_HPLL (BIT(8) | BIT(9) | BIT(10))
> > > +#define G6_CLK_SOURCE_USB BIT(9)
> > > +#define G6_CLK_SEL30x308
> > > +#define G6_CLK_DIV_MASK0x3F000
> >
> > This register is defined in the data sheet as:
> >
> > 17:12 SOC Display clock selection when source is from DisplayPort PHY
> >
> > That doesn't match with what the code is doing. Can you clarify the
> > register definition?
>
> OK. I will clarify it and response it to you.
>
> >
> > > +#define G6_CLK_DIV_16
> > (BIT(16)|BIT(15)|BIT(13)|BIT(12))
> > > +#define G6_USB_40_CLK BIT(9)
> > >
> > > /* GFX FLAGS */
> > > #define CLK_MASK BIT(0)
> > > #define CLK_G6 BIT(0)
> > > -
> > > -#define G6_CLK_MASK(BIT(8) | BIT(9) | BIT(10))
> > > -#define G6_USB_40_CLK BIT(9)
> > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > index a24fab22eac4..5829be9c7c67 100644
> > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > @@ -23,6 +23,28 @@ drm_pipe_to_aspeed_gfx(struct
> > drm_simple_display_pipe *pipe)
> > > return container_of(pipe, struct aspeed_gfx, pipe); }
> > >
> > > +static void aspeed_gfx_set_clock_source(struct aspeed_gfx *priv,
> > > +int
> > > +mode_width) {
> > > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> > G6_CLK_SOURCE_MASK, 0x0);
> > > + regmap_update_bits(priv->scu, G6_CLK_SEL3,
> G6_CLK_D
RE: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
> -Original Message-
> From: Joel Stanley
> Sent: Tuesday, April 26, 2022 3:48 PM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: Re: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
>
> On Fri, 4 Mar 2022 at 06:32, Tommy Haung
> wrote:
> >
> > Update the aspeed_gfx_set_clk with display width.
> > At AST2600, the display clock could be coming from HPLL clock / 16 =
> > 75MHz. It would fit 1024x768@70Hz.
> > Another chip will still keep 800x600.
> >
> > Signed-off-by: Tommy Haung
> > ---
> > drivers/gpu/drm/aspeed/aspeed_gfx.h | 12 ++
> > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 29
> > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c |
> > 16 +++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14
> > +++-
> > 4 files changed, 60 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > index eb4c267cde5e..c7aefee0657a 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > @@ -109,11 +109,15 @@ int aspeed_gfx_create_output(struct drm_device
> *drm);
> > #define CRT_THROD_HIGH(x) ((x) << 8)
> >
> > /* SCU control */
> > -#define SCU_G6_CLK_COURCE 0x300
> > +#define G6_CLK_SOURCE 0x300
> > +#define G6_CLK_SOURCE_MASK (BIT(8) | BIT(9) | BIT(10))
> > +#define G6_CLK_SOURCE_HPLL (BIT(8) | BIT(9) | BIT(10))
> > +#define G6_CLK_SOURCE_USB BIT(9)
> > +#define G6_CLK_SEL30x308
> > +#define G6_CLK_DIV_MASK0x3F000
>
> This register is defined in the data sheet as:
>
> 17:12 SOC Display clock selection when source is from DisplayPort PHY
>
> That doesn't match with what the code is doing. Can you clarify the register
> definition?
OK. I will clarify it and response it to you.
>
> > +#define G6_CLK_DIV_16
> (BIT(16)|BIT(15)|BIT(13)|BIT(12))
> > +#define G6_USB_40_CLK BIT(9)
> >
> > /* GFX FLAGS */
> > #define CLK_MASK BIT(0)
> > #define CLK_G6 BIT(0)
> > -
> > -#define G6_CLK_MASK(BIT(8) | BIT(9) | BIT(10))
> > -#define G6_USB_40_CLK BIT(9)
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > index a24fab22eac4..5829be9c7c67 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > @@ -23,6 +23,28 @@ drm_pipe_to_aspeed_gfx(struct
> drm_simple_display_pipe *pipe)
> > return container_of(pipe, struct aspeed_gfx, pipe); }
> >
> > +static void aspeed_gfx_set_clock_source(struct aspeed_gfx *priv, int
> > +mode_width) {
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> G6_CLK_SOURCE_MASK, 0x0);
> > + regmap_update_bits(priv->scu, G6_CLK_SEL3, G6_CLK_DIV_MASK,
> > +0x0);
> > +
> > + switch (mode_width) {
> > + case 1024:
> > + /* hpll div 16 = 75Mhz */
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> > + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_HPLL);
> > + regmap_update_bits(priv->scu, G6_CLK_SEL3,
> > + G6_CLK_DIV_MASK, G6_CLK_DIV_16);
> > + break;
> > + case 800:
> > + default:
> > + /* usb 40Mhz */
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> > + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_USB);
> > + break;
> > + }
> > +}
> > +
> > static int aspeed_gfx_set_pixel_fmt(struct aspeed_gfx *priv, u32
> > *bpp) {
> > struct drm_crtc *crtc = >pipe.crtc; @@ -77,12 +99,11 @@
> > static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv)
> > regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); }
> >
> > -static void aspeed_gfx_set_clk(struct aspeed_gfx *priv)
> > +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv, int
> > +mode_width)
> > {
> > switch (priv->flags & CLK_MASK) {
> > case CLK_G6:
> > - regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> G6_CLK_MASK, 0x0);
>
RE: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
Hi Joel,
> -Original Message-
> From: Joel Stanley
> Sent: Tuesday, April 26, 2022 11:27 AM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: Re: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600
>
> On Fri, 4 Mar 2022 at 06:32, Tommy Haung
> wrote:
> >
> > Update the aspeed_gfx_set_clk with display width.
> > At AST2600, the display clock could be coming from HPLL clock / 16 =
> > 75MHz. It would fit 1024x768@70Hz.
> > Another chip will still keep 800x600.
> >
> > Signed-off-by: Tommy Haung
> > ---
> > drivers/gpu/drm/aspeed/aspeed_gfx.h | 12 ++
> > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 29
> > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c |
> > 16 +++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14
> > +++-
> > 4 files changed, 60 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > index eb4c267cde5e..c7aefee0657a 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > @@ -109,11 +109,15 @@ int aspeed_gfx_create_output(struct drm_device
> *drm);
> > #define CRT_THROD_HIGH(x) ((x) << 8)
> >
> > /* SCU control */
> > -#define SCU_G6_CLK_COURCE 0x300
> > +#define G6_CLK_SOURCE 0x300
> > +#define G6_CLK_SOURCE_MASK (BIT(8) | BIT(9) | BIT(10))
> > +#define G6_CLK_SOURCE_HPLL (BIT(8) | BIT(9) | BIT(10))
> > +#define G6_CLK_SOURCE_USB BIT(9)
> > +#define G6_CLK_SEL30x308
> > +#define G6_CLK_DIV_MASK0x3F000
> > +#define G6_CLK_DIV_16
> (BIT(16)|BIT(15)|BIT(13)|BIT(12))
> > +#define G6_USB_40_CLK BIT(9)
> >
> > /* GFX FLAGS */
> > #define CLK_MASK BIT(0)
> > #define CLK_G6 BIT(0)
> > -
> > -#define G6_CLK_MASK(BIT(8) | BIT(9) | BIT(10))
> > -#define G6_USB_40_CLK BIT(9)
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > index a24fab22eac4..5829be9c7c67 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > @@ -23,6 +23,28 @@ drm_pipe_to_aspeed_gfx(struct
> drm_simple_display_pipe *pipe)
> > return container_of(pipe, struct aspeed_gfx, pipe); }
> >
> > +static void aspeed_gfx_set_clock_source(struct aspeed_gfx *priv, int
> > +mode_width) {
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> G6_CLK_SOURCE_MASK, 0x0);
> > + regmap_update_bits(priv->scu, G6_CLK_SEL3, G6_CLK_DIV_MASK,
> > +0x0);
> > +
> > + switch (mode_width) {
> > + case 1024:
> > + /* hpll div 16 = 75Mhz */
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> > + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_HPLL);
> > + regmap_update_bits(priv->scu, G6_CLK_SEL3,
> > + G6_CLK_DIV_MASK, G6_CLK_DIV_16);
> > + break;
> > + case 800:
> > + default:
> > + /* usb 40Mhz */
> > + regmap_update_bits(priv->scu, G6_CLK_SOURCE,
> > + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_USB);
> > + break;
> > + }
>
> I'm not familiar with this area, but I think this belongs in the clock driver.
>
> We want to be able to call clk_set_rate() from the drm driver and have the
> clock driver update the correct bits in the SCU.
>
> Instead of specialising the 2600 vs others, could clk_set_rate() fail on the
> others, and cause the driver to stay at 800x600. If the set succeeds it can
> then
> run at the higher resolution. If this is not how the APIs work, we could
> instead
> have a clock_rate in struct aspeed_gfx and each platform can define its
> expected clock rate. It would then need a corresponding resolution.
>
> Please take a look at other drivers and see what they do.
Thanks for your common. The pixel clock selection is very limit on soc display.
Until now, there are just two resolutions (800x600@60 and 1024x768@70)could be
selected at ast2600.
And there is just 800x600@60 could be selected at ast2500 and ast2400.
Although I also want to have clk_set_rate() function t
RE: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
Hi Joel,
> -Original Message-
> From: Joel Stanley
> Sent: Tuesday, March 1, 2022 7:05 PM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
>
> On Tue, 1 Mar 2022 at 07:00, Tommy Huang
> wrote:
> >
> > Hi Joel,
> >
> > It seems that the reset control could keep original code behavior.
> > Just change the reset define in the .dtsi file from
> ASPEED_RESET_CRT1 into ASPEED_RESET_GRAPHICS.
>
> Right, because the ASPEED_RESET_CRT reset is released by the
> ASPEED_CLK_GATE_D1CLK line?
>
> include/dt-bindings/clock/ast2600-clock.h:#define ASPEED_RESET_CRT
> 13
>
> drivers/clk/clk-ast2600.c: /*
> clk rst name parent flags */
> drivers/clk/clk-ast2600.c: [ASPEED_CLK_GATE_D1CLK] = {
> 10, 13, "d1clk-gate", "d1clk", 0 >
>
>
>
> >
> > By the way, the HW controller states and FW programming register
> will be reset by CRT reset line.
> > And another part HW controller states will be reset by engine
> reset line.
>
> Thanks. Can we include that in the commit message for the device tree
> change?
>
Got it. I will add this and re-send the patches.
Thanks for your suggestion.
> >
> > Thanks,
> >
> > By Tommy
> >
> > > -Original Message-
> > > From: Joel Stanley
> > > Sent: Monday, February 28, 2022 5:51 PM
> > > To: Tommy Huang
> > > Cc: David Airlie ; Daniel Vetter
> > > ; Rob Herring ; Andrew Jeffery
> > > ; linux-aspeed ;
> > > open list:DRM DRIVERS ; devicetree
> > > ; Linux ARM
> > > ; Linux Kernel Mailing List
> > > ; BMC-SW
> > > Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for
> > > AST2600
> > >
> > > On Wed, 8 Dec 2021 at 01:34, Tommy Haung
> > > wrote:
> > > >
> > > > From: tommy-huang
> > > >
> > > > Add more reset and clock select code for AST2600.
> > > > The gfx_flags parameter was added for chip caps idenified.
> > >
> > > Can you tell me a bit more about the two reset lines:
> > >
> > > What is the CRT reset line controlling?
> > >
> > > What does the engine reset line control?
> > >
> > > Can we use devm_reset_control_array_get() to get whichever are
> > > specified in the device tree, so we don't need to have different
> > > logic for the 2600 and earlier chips?
> > >
> > >
> > >
> > > >
> > > > Signed-off-by: tommy-huang
> > > > ---
> > > > drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++-
> > > > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16
> > > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50
> > > ++--
> > > > 3 files changed, 77 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > index 4e6a442c3886..2c733225d3c7 100644
> > > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > @@ -8,7 +8,8 @@ struct aspeed_gfx {
> > > > struct drm_device drm;
> > > > void __iomem*base;
> > > > struct clk *clk;
> > > > - struct reset_control*rst;
> > > > + struct reset_control*rst_crt;
> > > > + struct reset_control*rst_engine;
> > > > struct regmap *scu;
> > > >
> > > > u32 dac_reg;
> > > > @@ -16,6 +17,7 @@ struct aspeed_gfx {
> > > > u32 vga_scratch_reg;
> > > > u32 throd_val;
> > > > u32 scan_line_max;
> > > > + u32 flags;
> > > >
> > > > struct drm_simple_display_pipe pipe;
> > > > struct drm_connectorconnector;
> > > > @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct
RE: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
Hi Joel,
It seems that the reset control could keep original code behavior.
Just change the reset define in the .dtsi file from ASPEED_RESET_CRT1
into ASPEED_RESET_GRAPHICS.
By the way, the HW controller states and FW programming register will
be reset by CRT reset line.
And another part HW controller states will be reset by engine reset
line.
Thanks,
By Tommy
> -Original Message-
> From: Joel Stanley
> Sent: Monday, February 28, 2022 5:51 PM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
>
> On Wed, 8 Dec 2021 at 01:34, Tommy Haung
> wrote:
> >
> > From: tommy-huang
> >
> > Add more reset and clock select code for AST2600.
> > The gfx_flags parameter was added for chip caps idenified.
>
> Can you tell me a bit more about the two reset lines:
>
> What is the CRT reset line controlling?
>
> What does the engine reset line control?
>
> Can we use devm_reset_control_array_get() to get whichever are specified in
> the device tree, so we don't need to have different logic for the 2600 and
> earlier chips?
>
>
>
> >
> > Signed-off-by: tommy-huang
> > ---
> > drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++-
> > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16
> > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50
> ++--
> > 3 files changed, 77 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > index 4e6a442c3886..2c733225d3c7 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > @@ -8,7 +8,8 @@ struct aspeed_gfx {
> > struct drm_device drm;
> > void __iomem*base;
> > struct clk *clk;
> > - struct reset_control*rst;
> > + struct reset_control*rst_crt;
> > + struct reset_control*rst_engine;
> > struct regmap *scu;
> >
> > u32 dac_reg;
> > @@ -16,6 +17,7 @@ struct aspeed_gfx {
> > u32 vga_scratch_reg;
> > u32 throd_val;
> > u32 scan_line_max;
> > + u32 flags;
> >
> > struct drm_simple_display_pipe pipe;
> > struct drm_connectorconnector;
> > @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct drm_device
> > *drm);
> > /* CRT_THROD */
> > #define CRT_THROD_LOW(x) (x)
> > #define CRT_THROD_HIGH(x) ((x) << 8)
> > +
> > +/* SCU control */
> > +#define SCU_G6_CLK_COURCE 0x300
> > +
> > +/* GFX FLAGS */
> > +#define RESET_MASK BIT(0)
> > +#define RESET_G6 BIT(0)
> > +#define CLK_MASK BIT(4)
> > +#define CLK_G6 BIT(4)
> > +
> > +#define G6_CLK_MASK(BIT(8) | BIT(9) | BIT(10))
> > +#define G6_USB_40_CLK BIT(9)
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > index 827e62c1daba..e0975ecda92d 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > @@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct
> aspeed_gfx *priv)
> > regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); }
> >
> > +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) {
> > + switch (priv->flags & CLK_MASK) {
> > + case CLK_G6:
> > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> G6_CLK_MASK, 0x0);
> > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> G6_CLK_MASK, G6_USB_40_CLK);
> > + break;
> > + default:
> > + break;
> > + }
> > +}
> > +
> > static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) {
> > struct drm_display_mode *m =
> > >pipe.crtc.state->adjusted_mode;
> > @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct
&g
RE: [PATCH v3 0/4] Add Aspeed AST2600 soc display support
Hi Joel, Got it. I will change user name for next patch send. The ast2600 is tested on my platform. And I will try this on the ast2500. Below is testing steps: 1. Apply the patch into project. 2. Add below config for VT and LOGO on. CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_CLUT224=y 3. The Linux logo will be shown on the screen, when the BMC boot in Linux. Thanks, By Tommy > -Original Message- > From: Joel Stanley > Sent: Wednesday, November 17, 2021 2:06 PM > To: Tommy Huang > Cc: David Airlie ; Daniel Vetter ; Rob > Herring ; Andrew Jeffery ; > linux-aspeed ; open list:DRM DRIVERS > ; devicetree ; > Linux ARM ; Linux Kernel Mailing List > ; BMC-SW > Subject: Re: [PATCH v3 0/4] Add Aspeed AST2600 soc display support > > On Wed, 17 Nov 2021 at 05:45, tommy-huang > wrote: > > > > v3: > > Refine the patch for clear separate purpose. > > Skip to send devicetree patch > > Thanks Tommy. A few things: > > - Set up your authorship in git: > > git config --global user.name "Tommy Haung" > > - The "Add AST2600 chip support" patch is the same as the one I sent, you can > put mine back in your series now > > - We should add a device tree bindings document > > Can you confirm you tested these changes on both the ast2500 and the > ast2600? How did you test? > > Cheers, > > Joel > > > > > > v2: > > Remove some unnecessary patch. > > Refine for reviwer request. > > > > v1: > > First add patch. > > > > Joel Stanley (2): > > ARM: dts: aspeed: Add GFX node to AST2600 > > ARM: dts: aspeed: ast2600-evb: Enable GFX device > > > > tommy-huang (2): > > drm/aspeed: Update INTR_STS handling > > drm/aspeed: Add AST2600 chip support > > > > arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++ > > arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++ > > drivers/gpu/drm/aspeed/aspeed_gfx.h | 1 + > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 15 ++- > > 4 files changed, 44 insertions(+), 1 deletion(-) > > > > -- > > 2.17.1 > >
[PATCH v3 1/4] ARM: dts: aspeed: Add GFX node to AST2600
From: Joel Stanley
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..e38c3742761b 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -351,6 +351,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx",
"aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = < ASPEED_CLK_GATE_D1CLK>;
+ resets = < ASPEED_RESET_GRAPHICS>;
+ syscon = <>;
+ status = "disabled";
+ interrupts = ;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
--
2.17.1
[PATCH v3 4/4] drm/aspeed: Add AST2600 chip support
Add AST2600 chip support and setting.
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index d4b56b3c7597..d10246b1d1c2 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -82,9 +82,18 @@ static const struct aspeed_gfx_config ast2500_config = {
.scan_line_max = 128,
};
+static const struct aspeed_gfx_config ast2600_config = {
+ .dac_reg = 0xc0,
+ .int_clear_reg = 0x68,
+ .vga_scratch_reg = 0x50,
+ .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
+ .scan_line_max = 128,
+};
+
static const struct of_device_id aspeed_gfx_match[] = {
{ .compatible = "aspeed,ast2400-gfx", .data = _config },
{ .compatible = "aspeed,ast2500-gfx", .data = _config },
+ { .compatible = "aspeed,ast2600-gfx", .data = _config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
--
2.17.1
[PATCH v3 3/4] drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx.h | 1 +
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
b/drivers/gpu/drm/aspeed/aspeed_gfx.h
index 96501152bafa..4e6a442c3886 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
@@ -12,6 +12,7 @@ struct aspeed_gfx {
struct regmap *scu;
u32 dac_reg;
+ u32 int_clr_reg;
u32 vga_scratch_reg;
u32 throd_val;
u32 scan_line_max;
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index b53fee6f1c17..d4b56b3c7597 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -60,6 +60,7 @@
struct aspeed_gfx_config {
u32 dac_reg;/* DAC register in SCU */
+ u32 int_clear_reg; /* Interrupt clear register */
u32 vga_scratch_reg;/* VGA scratch register in SCU */
u32 throd_val; /* Default Threshold Seting */
u32 scan_line_max; /* Max memory size of one scan line */
@@ -67,6 +68,7 @@ struct aspeed_gfx_config {
static const struct aspeed_gfx_config ast2400_config = {
.dac_reg = 0x2c,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
.scan_line_max = 64,
@@ -74,6 +76,7 @@ static const struct aspeed_gfx_config ast2400_config = {
static const struct aspeed_gfx_config ast2500_config = {
.dac_reg = 0x2c,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
.scan_line_max = 128,
@@ -119,7 +122,7 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void
*data)
if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
drm_crtc_handle_vblank(>pipe.crtc);
- writel(reg, priv->base + CRT_CTRL1);
+ writel(reg, priv->base + priv->int_clr_reg);
return IRQ_HANDLED;
}
@@ -147,6 +150,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
config = match->data;
priv->dac_reg = config->dac_reg;
+ priv->int_clr_reg = config->int_clear_reg;
priv->vga_scratch_reg = config->vga_scratch_reg;
priv->throd_val = config->throd_val;
priv->scan_line_max = config->scan_line_max;
--
2.17.1
[PATCH v3 0/4] Add Aspeed AST2600 soc display support
v3: Refine the patch for clear separate purpose. Skip to send devicetree patch v2: Remove some unnecessary patch. Refine for reviwer request. v1: First add patch. Joel Stanley (2): ARM: dts: aspeed: Add GFX node to AST2600 ARM: dts: aspeed: ast2600-evb: Enable GFX device tommy-huang (2): drm/aspeed: Update INTR_STS handling drm/aspeed: Add AST2600 chip support arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++ arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++ drivers/gpu/drm/aspeed/aspeed_gfx.h | 1 + drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 15 ++- 4 files changed, 44 insertions(+), 1 deletion(-) -- 2.17.1
[PATCH v3 2/4] ARM: dts: aspeed: ast2600-evb: Enable GFX device
From: Joel Stanley
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..e223dad2abd0 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,19 @@
reg = <0x8000 0x8000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x0100>;
+ alignment = <0x0100>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
@@ -300,3 +313,8 @@
vqmmc-supply = <_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
};
+
+ {
+ status = "okay";
+ memory-region = <_memory>;
+};
--
2.17.1
RE: [PATCH 3/4] drm/aspeed: Update INTR_STS handling
Hi Joel,
Thanks for your comment.
I will modify the patch and send it again.
> -Original Message-
> From: Joel Stanley
> Sent: Tuesday, November 16, 2021 2:19 PM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
> Subject: Re: [PATCH 3/4] drm/aspeed: Update INTR_STS handling
>
> On Mon, 1 Nov 2021 at 11:01, tommy-huang
> wrote:
> >
> > The V-sync INTR_STS is differnet on AST2600.
> > Change into general rule to handle it.
> >
> > Signed-off-by: tommy-huang
> > ---
> > drivers/gpu/drm/aspeed/aspeed_gfx.h | 2 ++
> > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 26
> > ++---
> > 2 files changed, 25 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > index 96501152bafa..5eed9275bce7 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > @@ -12,6 +12,8 @@ struct aspeed_gfx {
> > struct regmap *scu;
> >
> > u32 dac_reg;
> > + u32 int_reg;
> > + u32 int_clr_reg;
> > u32 vga_scratch_reg;
> > u32 throd_val;
> > u32 scan_line_max;
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > index b53fee6f1c17..1092060cb59c 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > @@ -60,6 +60,8 @@
> >
> > struct aspeed_gfx_config {
> > u32 dac_reg;/* DAC register in SCU */
> > + u32 int_status_reg; /* Interrupt status register */
>
> This is the same for all supported chips; do you need to introduce the
> variable
> for it?
>
> > + u32 int_clear_reg; /* Interrupt clear register */
> > u32 vga_scratch_reg;/* VGA scratch register in SCU */
> > u32 throd_val; /* Default Threshold Seting */
> > u32 scan_line_max; /* Max memory size of one scan line */
> > @@ -67,6 +69,8 @@ struct aspeed_gfx_config {
> >
> > static const struct aspeed_gfx_config ast2400_config = {
> > .dac_reg = 0x2c,
> > + .int_status_reg = 0x60,
> > + .int_clear_reg = 0x60,
> > .vga_scratch_reg = 0x50,
> > .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
> > .scan_line_max = 64,
> > @@ -74,14 +78,26 @@ static const struct aspeed_gfx_config
> > ast2400_config = {
> >
> > static const struct aspeed_gfx_config ast2500_config = {
> > .dac_reg = 0x2c,
> > + .int_status_reg = 0x60,
> > + .int_clear_reg = 0x60,
> > .vga_scratch_reg = 0x50,
> > .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
> > .scan_line_max = 128,
> > };
> >
> > +static const struct aspeed_gfx_config ast2600_config = {
> > + .dac_reg = 0xc0,
> > + .int_status_reg = 0x60,
> > + .int_clear_reg = 0x68,
> > + .vga_scratch_reg = 0x50,
> > + .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
> > + .scan_line_max = 128,
> > +};
>
> This patch combines adding the clear_reg functionality with support for the
> 2600. Can you split them out; add int_clear_reg first, and then add support
> for
> the 2600 in the following patch?
>
>
> > +
> > static const struct of_device_id aspeed_gfx_match[] = {
> > { .compatible = "aspeed,ast2400-gfx", .data = _config },
> > { .compatible = "aspeed,ast2500-gfx", .data = _config
> > },
> > + { .compatible = "aspeed,ast2600-gfx", .data = _config
> > + },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, aspeed_gfx_match); @@ -113,13 +129,15 @@
> > static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data) {
> > struct drm_device *drm = data;
> > struct aspeed_gfx *priv = to_aspeed_gfx(drm);
> > - u32 reg;
> > + u32 reg, clr_reg;
> >
> > - reg = readl(priv->base + CRT_CTRL1);
> > + reg = readl(priv->base + priv->int_reg);
> >
> > if (reg & CRT
RE: [PATCH 4/4] dt-bindings: gpu: Add ASPEED GFX bindings document
Hi Rob, Thanks for your comments. I got it. By Tommy > -Original Message- > From: Rob Herring > Sent: Tuesday, November 2, 2021 4:02 AM > To: Tommy Huang > Cc: dri-devel@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org; > linux-asp...@lists.ozlabs.org; dan...@ffwll.ch; BMC-SW > ; devicet...@vger.kernel.org; > linux-ker...@vger.kernel.org; robh...@kernel.org; j...@jms.id.au; > and...@aj.id.au; airl...@linux.ie > Subject: Re: [PATCH 4/4] dt-bindings: gpu: Add ASPEED GFX bindings document > > On Mon, 01 Nov 2021 19:01:07 +0800, tommy-huang wrote: > > Add ast2600-gfx description for gfx driver. > > > > Signed-off-by: tommy-huang > > --- > > Documentation/devicetree/bindings/gpu/aspeed-gfx.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > > Please add Acked-by/Reviewed-by tags when posting new versions. However, > there's no need to repost patches *only* to add the tags. The upstream > maintainer will do that for acks received on the version they apply. > > If a tag was not added on purpose, please state why and what changed.
[PATCH 4/4] dt-bindings: gpu: Add ASPEED GFX bindings document
Add ast2600-gfx description for gfx driver. Signed-off-by: tommy-huang --- Documentation/devicetree/bindings/gpu/aspeed-gfx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt index 958bdf962339..29ecf119cef2 100644 --- a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -3,6 +3,7 @@ Device tree configuration for the GFX display device on the ASPEED SoCs Required properties: - compatible * Must be one of the following: + + aspeed,ast2600-gfx + aspeed,ast2500-gfx + aspeed,ast2400-gfx * In addition, the ASPEED pinctrl bindings require the 'syscon' property to -- 2.17.1
[PATCH 3/4] drm/aspeed: Update INTR_STS handling
The V-sync INTR_STS is differnet on AST2600.
Change into general rule to handle it.
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx.h | 2 ++
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 26 ++---
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
b/drivers/gpu/drm/aspeed/aspeed_gfx.h
index 96501152bafa..5eed9275bce7 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
@@ -12,6 +12,8 @@ struct aspeed_gfx {
struct regmap *scu;
u32 dac_reg;
+ u32 int_reg;
+ u32 int_clr_reg;
u32 vga_scratch_reg;
u32 throd_val;
u32 scan_line_max;
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index b53fee6f1c17..1092060cb59c 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -60,6 +60,8 @@
struct aspeed_gfx_config {
u32 dac_reg;/* DAC register in SCU */
+ u32 int_status_reg; /* Interrupt status register */
+ u32 int_clear_reg; /* Interrupt clear register */
u32 vga_scratch_reg;/* VGA scratch register in SCU */
u32 throd_val; /* Default Threshold Seting */
u32 scan_line_max; /* Max memory size of one scan line */
@@ -67,6 +69,8 @@ struct aspeed_gfx_config {
static const struct aspeed_gfx_config ast2400_config = {
.dac_reg = 0x2c,
+ .int_status_reg = 0x60,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
.scan_line_max = 64,
@@ -74,14 +78,26 @@ static const struct aspeed_gfx_config ast2400_config = {
static const struct aspeed_gfx_config ast2500_config = {
.dac_reg = 0x2c,
+ .int_status_reg = 0x60,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
.scan_line_max = 128,
};
+static const struct aspeed_gfx_config ast2600_config = {
+ .dac_reg = 0xc0,
+ .int_status_reg = 0x60,
+ .int_clear_reg = 0x68,
+ .vga_scratch_reg = 0x50,
+ .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
+ .scan_line_max = 128,
+};
+
static const struct of_device_id aspeed_gfx_match[] = {
{ .compatible = "aspeed,ast2400-gfx", .data = _config },
{ .compatible = "aspeed,ast2500-gfx", .data = _config },
+ { .compatible = "aspeed,ast2600-gfx", .data = _config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
@@ -113,13 +129,15 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void
*data)
{
struct drm_device *drm = data;
struct aspeed_gfx *priv = to_aspeed_gfx(drm);
- u32 reg;
+ u32 reg, clr_reg;
- reg = readl(priv->base + CRT_CTRL1);
+ reg = readl(priv->base + priv->int_reg);
if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
drm_crtc_handle_vblank(>pipe.crtc);
- writel(reg, priv->base + CRT_CTRL1);
+ clr_reg = (readl(priv->base + priv->int_clr_reg) |
+ CRT_CTRL_VERTICAL_INTR_STS);
+ writel(clr_reg, priv->base + priv->int_clr_reg);
return IRQ_HANDLED;
}
@@ -147,6 +165,8 @@ static int aspeed_gfx_load(struct drm_device *drm)
config = match->data;
priv->dac_reg = config->dac_reg;
+ priv->int_reg = config->int_status_reg;
+ priv->int_clr_reg = config->int_clear_reg;
priv->vga_scratch_reg = config->vga_scratch_reg;
priv->throd_val = config->throd_val;
priv->scan_line_max = config->scan_line_max;
--
2.17.1
[PATCH 2/4] ARM: dts: aspeed: ast2600-evb: Enable GFX device
From: Joel Stanley
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..e223dad2abd0 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,19 @@
reg = <0x8000 0x8000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x0100>;
+ alignment = <0x0100>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
@@ -300,3 +313,8 @@
vqmmc-supply = <_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
};
+
+ {
+ status = "okay";
+ memory-region = <_memory>;
+};
--
2.17.1
[PATCH 1/4] ARM: dts: aspeed: Add GFX node to AST2600
From: Joel Stanley
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..e38c3742761b 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -351,6 +351,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx",
"aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = < ASPEED_CLK_GATE_D1CLK>;
+ resets = < ASPEED_RESET_GRAPHICS>;
+ syscon = <>;
+ status = "disabled";
+ interrupts = ;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
--
2.17.1
[PATCH 0/4] Add Aspeed AST2600 soc display support
The Aspeed AST2600 soc diaplay support is added in this patch. Because some hw designed is changed in this version, add them in this patch. v2: Remove some unnecessary patch. Refine for reviwer request. v1: First add patch. Joel Stanley (2): ARM: dts: aspeed: Add GFX node to AST2600 ARM: dts: aspeed: ast2600-evb: Enable GFX device tommy-huang (2): drm/aspeed: Update INTR_STS handling dt-bindings: gpu: Add ASPEED GFX bindings document .../devicetree/bindings/gpu/aspeed-gfx.txt| 1 + arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 + arch/arm/boot/dts/aspeed-g6.dtsi | 11 drivers/gpu/drm/aspeed/aspeed_gfx.h | 2 ++ drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 26 --- 5 files changed, 55 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH 2/6] ARM: dts: aspeed: ast2600-evb: Enable GFX device
From: Joel Stanley
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..195ccd1952da 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,19 @@
reg = <0x8000 0x8000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x0100>;
+ alignment = <0x0100>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
--
2.17.1
[PATCH 0/6] *** Add AST2600 GFX node ***
Add AST2600 GFX support first. Joel Stanley (5): ARM: dts: aspeed: Add GFX node to AST2600 ARM: dts: aspeed: ast2600-evb: Enable GFX device drm/aspeed: Add AST2600 support HACK: drm/aspeed: INTR_STS hadndling HACK: drm/aspeed: Paramterise modes tommy-huang (1): dt-bindings: gpu: Add ASPEED GFX bindings document .../devicetree/bindings/gpu/aspeed-gfx.txt | 1 + arch/arm/boot/dts/aspeed-ast2600-evb.dts | 13 + arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++ drivers/gpu/drm/aspeed/aspeed_gfx_drv.c| 18 +- 4 files changed, 38 insertions(+), 5 deletions(-) -- 2.17.1
[PATCH 6/6] dt-bindings: gpu: Add ASPEED GFX bindings document
Add ast2600-gfx description for gfx driver. Signed-off-by: tommy-huang --- Documentation/devicetree/bindings/gpu/aspeed-gfx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt index 958bdf962339..29ecf119cef2 100644 --- a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -3,6 +3,7 @@ Device tree configuration for the GFX display device on the ASPEED SoCs Required properties: - compatible * Must be one of the following: + + aspeed,ast2600-gfx + aspeed,ast2500-gfx + aspeed,ast2400-gfx * In addition, the ASPEED pinctrl bindings require the 'syscon' property to -- 2.17.1
[PATCH 5/6] HACK: drm/aspeed: Paramterise modes
From: Joel Stanley
The AST2600 will run at 1024x868.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index 33095477cc03..11a44b08bd3f 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -99,7 +99,7 @@ static const struct drm_mode_config_funcs
aspeed_gfx_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
};
-static int aspeed_gfx_setup_mode_config(struct drm_device *drm)
+static int aspeed_gfx_setup_mode_config(struct drm_device *drm, int width, int
height)
{
int ret;
@@ -109,8 +109,8 @@ static int aspeed_gfx_setup_mode_config(struct drm_device
*drm)
drm->mode_config.min_width = 0;
drm->mode_config.min_height = 0;
- drm->mode_config.max_width = 800;
- drm->mode_config.max_height = 600;
+ drm->mode_config.max_width = width;
+ drm->mode_config.max_height = height;
drm->mode_config.funcs = _gfx_mode_config_funcs;
return ret;
@@ -201,7 +201,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
writel(0, priv->base + CRT_CTRL1);
writel(0, priv->base + CRT_CTRL2);
- ret = aspeed_gfx_setup_mode_config(drm);
+ ret = aspeed_gfx_setup_mode_config(drm, 800, 600);
if (ret < 0)
return ret;
--
2.17.1
[PATCH 1/6] ARM: dts: aspeed: Add GFX node to AST2600
From: Joel Stanley
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..e38c3742761b 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -351,6 +351,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx",
"aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = < ASPEED_CLK_GATE_D1CLK>;
+ resets = < ASPEED_RESET_GRAPHICS>;
+ syscon = <>;
+ status = "disabled";
+ interrupts = ;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
--
2.17.1
[PATCH 4/6] HACK: drm/aspeed: INTR_STS hadndling
From: Joel Stanley
The 2600 uses this register differently. THis is a TODO to come up with
a method of handling that.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index ea9cb0a4f16c..33095477cc03 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -126,7 +126,8 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void
*data)
if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
drm_crtc_handle_vblank(>pipe.crtc);
- writel(reg, priv->base + CRT_CTRL1);
+ /* TODO */
+ writel(CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_STATUS);
return IRQ_HANDLED;
}
--
2.17.1
[PATCH 3/6] drm/aspeed: Add AST2600 support
From: Joel Stanley
The values for the threshold and scan line size come from the ASPEED
SDK.
The DAC register is SCUC0 in the AST2600 datasheet. It has the same
layout as the previous generations.
Signed-off-by: Joel Stanley
Signed-off-by: tommy-huang
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index b53fee6f1c17..ea9cb0a4f16c 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -79,9 +79,16 @@ static const struct aspeed_gfx_config ast2500_config = {
.scan_line_max = 128,
};
+static const struct aspeed_gfx_config ast2600_config = {
+ .dac_reg = 0xc0,
+ .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
+ .scan_line_max = 128,
+};
+
static const struct of_device_id aspeed_gfx_match[] = {
{ .compatible = "aspeed,ast2400-gfx", .data = _config },
{ .compatible = "aspeed,ast2500-gfx", .data = _config },
+ { .compatible = "aspeed,ast2600-gfx", .data = _config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
--
2.17.1
