[PATCH V2 2/2] drm: xlnx: dsi: Add Xilinx MIPI DSI-Tx subsystem driver
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, optional register interface for the DPHY and multiple RGB color formats. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework. Signed-off-by: Venkateshwar Rao Gannavarapu --- drivers/gpu/drm/xlnx/Kconfig| 12 ++ drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 429 3 files changed, 442 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index f9cf93c..a75bd76 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -1,3 +1,15 @@ +config DRM_XLNX_DSI + tristate "Xilinx DRM DSI Subsystem Driver" + depends on ARCH_ZYNQMP || COMPILE_TEST + depends on DRM && OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + help + DRM bridge driver for Xilinx programmable DSI subsystem controller. + choose this option if you hava a Xilinx MIPI-DSI Tx subsytem in + video pipeline. + config DRM_ZYNQMP_DPSUB tristate "ZynqMP DisplayPort Controller Driver" depends on ARCH_ZYNQMP || COMPILE_TEST diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 51c24b7..f90849b 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o zynqmp-dpsub-y := zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 000..39d8947 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA MIPI DSI Tx Controller driver. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Author: Venkateshwar Rao Gannavarapu + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* DSI Tx IP registers */ +#define XDSI_CCR 0x00 +#define XDSI_CCR_COREENB BIT(0) +#define XDSI_CCR_SOFTRST BIT(1) +#define XDSI_CCR_CRREADY BIT(2) +#define XDSI_CCR_CMDMODE BIT(3) +#define XDSI_CCR_DFIFORST BIT(4) +#define XDSI_CCR_CMDFIFORSTBIT(5) +#define XDSI_PCR 0x04 +#define XDSI_PCR_LANES_MASK3 +#define XDSI_PCR_VIDEOMODE(x) (((x) & 0x3) << 3) +#define XDSI_PCR_VIDEOMODE_MASKGENMASK(4, 3) +#define XDSI_PCR_VIDEOMODE_SHIFT 3 +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) +#define XDSI_PCR_PIXELFORMAT_MASK GENMASK(12, 11) +#define XDSI_PCR_PIXELFORMAT_SHIFT 11 +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) +#define XDSI_GIER 0x20 +#define XDSI_ISR 0x24 +#define XDSI_IER 0x28 +#define XDSI_STR 0x2C +#define XDSI_STR_RDY_SHPKT BIT(6) +#define XDSI_STR_RDY_LNGPKTBIT(7) +#define XDSI_STR_DFIFO_FULLBIT(8) +#define XDSI_STR_DFIFO_EMPTY BIT(9) +#define XDSI_STR_WAITFR_DATA BIT(10) +#define XDSI_STR_CMD_EXE_PGS BIT(11) +#define XDSI_STR_CCMD_PROC BIT(12) +#define XDSI_CMD 0x30 +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) +#define XDSI_DFR 0x34 +#define XDSI_TIME1 0x50 +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME1_HSA(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME2 0x54 +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) +#define XDSI_TIME3 0x58 +#define XDSI_TIME3_HFP(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME3_HBP(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME4 0x5c +#define XDSI_TIME4_VFP(x) ((x) & GENMASK(7, 0)) +#define XDSI_TIME4_VBP(x) (((x) & GENMASK(7, 0)) << 8) +#define XDSI_TIME4_VSA(x) (((x) & GENMASK(7, 0)) << 16) +#define XDSI_NUM_DATA_T4 + +/** + * struct xlnx_dsi - Xilinx DSI-TX core + * @bridge: DRM bridge structure + * @dsi_host: DSI host device + * @next_bridge: bridge structure + * @dev: device structure + * @clks: clock source structure + * @iomem: Base address of DSI s
[PATCH V2 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation
This patch adds dt binding for Xilinx DSI-TX subsystem.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with the programmable logic (FPGA).
Signed-off-by: Venkateshwar Rao Gannavarapu
---
.../bindings/display/xlnx/xlnx,dsi-tx.yaml | 101 +
1 file changed, 101 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
new file mode 100644
index 000..644934d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx DSI Transmitter subsystem Device Tree Bindings
+
+maintainers:
+ - Venkateshwar Rao Gannavarapu
+
+description: |
+ The Xilinx DSI Transmitter Subsystem implements the Mobile Industry
+ Processor Interface based display interface. It supports the interface
+ with the programmable logic (FPGA).
+
+ For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem.
+
+properties:
+ compatible:
+const: xlnx,dsi-tx-v2.0
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: AXI Lite CPU clock
+ - description: D-PHY clock
+
+ clock-names:
+items:
+ - const: s_axis_aclk
+ - const: dphy_clk_200M
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ This port should be the input endpoint.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ This port should be the output endpoint.
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+dsi0: dsi_tx@8002 {
+compatible = "xlnx,dsi-tx-v2.0";
+reg = <0x8002 0x2>;
+clocks = <_clk_0>, <_clk_1>;
+clock-names = "s_axis_aclk", "dphy_clk_200M";
+#address-cells = <1>;
+#size-cells = <0>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+reg = <0>;
+mipi_dsi_in: endpoint {
+remote-endpoint = <_disp>;
+};
+ };
+
+ port@1 {
+reg = <1>;
+mipi_dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+ };
+};
+
+panel@0 {
+ compatible = "auo,b101uan01";
+ reg = <0>;
+ port {
+panel_in: endpoint {
+remote-endpoint = <_dsi_out>;
+};
+ };
+};
+};
+
+...
--
1.8.3.1
[PATCH V2 0/2] Add Xilinx DSI-Tx subsystem DRM driver
MIPI DSI TX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between the video processing subsystems and MIPI-based displays. An internal high-speed physical layer design, D-PHY, is provided to allow direct connection to display peripherals. The subsystem consists of the following sub-blocks: - MIPI D-PHY - MIPI DSI TX Controller - AXI Crossbar Please refer pg238 [1]. The DSI TX Controller receives stream of image data through an input stream interface. At design time, this subsystem can be configured to number of lanes and pixel format. This patch series adds the dt-binding and DRM driver for Xilinx DSI-Tx soft IP. Changes in V2: - Rebased on 5.19 kernel - Moved mode_set functionality to atomic_enable as its deprecrated - Mask fixes - Replaced panel calls with bridge API's - Added mandatory atomic operations - Removed unnecessary logging - Added ARCH_ZYNQMP dependency in Kconfig - Fixed YAML warnings - Cleanup Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation drm: xlnx: dsi: Add Xilinx MIPI DSI-Tx subsystem driver .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 101 + drivers/gpu/drm/xlnx/Kconfig | 12 + drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c| 429 + 4 files changed, 543 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 1.8.3.1
[LINUX PATCH 2/2] drm: xlnx: dsi: driver for Xilinx DSI Tx subsystem
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, optional register interface for the DPHY and multiple RGB color formats. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework. Signed-off-by: Venkateshwar Rao Gannavarapu --- drivers/gpu/drm/xlnx/Kconfig| 14 ++ drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 456 3 files changed, 471 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index c3d0826..caa632b 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -14,3 +14,17 @@ config DRM_ZYNQMP_DPSUB This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose this option if you have a Xilinx ZynqMP SoC with DisplayPort subsystem. + +config DRM_XLNX_DSI + tristate "Xilinx DRM DSI Subsystem Driver" + depends on DRM && OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + select BACKLIGHT_LCD_SUPPORT + select BACKLIGHT_CLASS_DEVICE + select DRM_PANEL_SIMPLE + help + DRM bridge driver for Xilinx programmable DSI subsystem controller. + choose this option if you hava a Xilinx MIPI-DSI Tx subsytem in + video pipeline. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 51c24b7..1e97fbe 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,3 @@ zynqmp-dpsub-y := zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 000..a5291f3 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Xilinx FPGA MIPI DSI Tx Controller driver. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Author: Venkateshwar Rao G + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* DSI Tx IP registers */ +#define XDSI_CCR 0x00 +#define XDSI_CCR_COREENB BIT(0) +#define XDSI_CCR_SOFTRST BIT(1) +#define XDSI_CCR_CRREADY BIT(2) +#define XDSI_CCR_CMDMODE BIT(3) +#define XDSI_CCR_DFIFORST BIT(4) +#define XDSI_CCR_CMDFIFORSTBIT(5) +#define XDSI_PCR 0x04 +#define XDSI_PCR_LANES_MASK3 +#define XDSI_PCR_VIDEOMODE(x) (((x) & 0x3) << 3) +#define XDSI_PCR_VIDEOMODE_MASK(0x3 << 3) +#define XDSI_PCR_VIDEOMODE_SHIFT 3 +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) +#define XDSI_PCR_PIXELFORMAT_MASK (0x3 << 11) +#define XDSI_PCR_PIXELFORMAT_SHIFT 11 +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) +#define XDSI_GIER 0x20 +#define XDSI_ISR 0x24 +#define XDSI_IER 0x28 +#define XDSI_STR 0x2C +#define XDSI_STR_RDY_SHPKT BIT(6) +#define XDSI_STR_RDY_LNGPKTBIT(7) +#define XDSI_STR_DFIFO_FULLBIT(8) +#define XDSI_STR_DFIFO_EMPTY BIT(9) +#define XDSI_STR_WAITFR_DATA BIT(10) +#define XDSI_STR_CMD_EXE_PGS BIT(11) +#define XDSI_STR_CCMD_PROC BIT(12) +#define XDSI_STR_LPKT_MASK (0x5 << 7) +#define XDSI_CMD 0x30 +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) +#define XDSI_DFR 0x34 +#define XDSI_TIME1 0x50 +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME1_HSA(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME2 0x54 +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) +#define XDSI_TIME3 0x58 +#define XDSI_TIME3_HFP(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME3_HBP(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME4 0x5c +#define XDSI_TIME4_VFP(x) ((x) & GENMASK(7, 0)) +#define XDSI_TIME4_VBP(x) (((x) & GENMASK(7, 0)) << 8) +#define XDSI_TIME4_VSA(x) (((x) & GENMASK(7, 0)) << 16) +#define XDSI_NUM_DATA_T4 + +/** + * struct xlnx_dsi - Xilinx DSI-TX core + * @bridge: D
[LINUX PATCH 0/2] Add Xilinx DSI-Tx DRM driver
MIPI DSI TX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between the video processing subsystems and MIPI-based displays. An internal high-speed physical layer design, D-PHY, is provided to allow direct connection to display peripherals. The subsystem consists of the following sub-blocks: - MIPI D-PHY - MIPI DSI TX Controller - AXI Crossbar Please refer pg238 [1]. The DSI TX Controller receives stream of image data through an input stream interface. At design time, this subsystem can be configured to number of lanes and pixel format. This patch series adds the dt-binding and DRM driver for Xilinx DSI-Tx soft IP. References: [1]: https://www.xilinx.com/support/documentation/ip_documentation/mipi_dsi_tx_subsystem/v2_0/pg238-mipi-dsi-tx.pdf Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation drm: xlnx: dsi: driver for Xilinx DSI Tx subsystem .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 + drivers/gpu/drm/xlnx/Kconfig | 14 + drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c| 456 + 4 files changed, 576 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 1.8.3.1
[LINUX PATCH 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation
This patch adds dt binding for Xilinx DSI TX subsystem.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with the programmable logic (FPGA).
Signed-off-by: Venkateshwar Rao Gannavarapu
---
.../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 +
1 file changed, 105 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
new file mode 100644
index 000..8e23cf5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx DSI Transmitter subsystem
+
+maintainers:
+ - Venkateshwar Rao Gannavarapu
+
+description: |
+ The Xilinx DSI Transmitter Subsystem implements the Mobile Industry
+ Processor Interface based display interface. It supports the interface
+ with the programmable logic (FPGA).
+
+ For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem.
+
+properties:
+ compatible:
+const: xlnx,dsi-tx-v2.0
+
+ reg:
+maxItems: 1
+
+ clocks:
+description: List of clock specifiers
+items:
+ - description: AXI Lite CPU clock
+ - description: D-phy clock
+
+ clock-names:
+items:
+ - const: s_axis_aclk
+ - const: dphy_clk_200M
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/$defs/port-base
+description:
+ Input port node to receive pixel data from the
+ display controller. Exactly one endpoint must be
+ specified.
+properties:
+ endpoint:
+$ref: /schemas/graph.yaml#/properties/endpoint
+description: sub-node describing the input from CRTC
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ DSI output port node to the panel or the next bridge
+ in the chain
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+dsi_tx@8002 {
+compatible = "xlnx,dsi-tx-v2.0";
+reg = <0x8002 0x2>;
+clock-names = "s_axi_aclk", "dphy_clk_200M";
+clocks = <_clk_0>, <_clk_1>;
+
+panel@0 {
+compatible = "auo,b101uan01";
+reg = <0>;
+port {
+panel_in: endpoint {
+remote-endpoint = <_dsi_out>;
+};
+};
+};
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+#size-cells = <0>;
+#address-cells = <1>;
+reg = <0>;
+mipi_dsi_in: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_disp_crtc>;
+};
+};
+port@1 {
+reg = <1>;
+mipi_dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
--
1.8.3.1
[RFC PATCH V2 0/2] Add Xilinx DSI TX driver
Xilinx DSI-TX subsytem consists of DSI controller core, AXI crossbar and D-PHY as sub blocks. DSI TX subsystem driver supports multiple lanes upto 4, RGB color formats, video mode and command modes. DSI-TX driver is implemented as an encoder driver, as it going to be the final node in display pipeline. Xilinx doesn't support any converter logic to make this as bridge driver. Xilinx doesn't have such use cases where end node can't be an encoder like DSI-TX. And Xilinx encoder drivers represents a subsystem where individual blocks can't be used with external components / encoders. changes in v2: - converted bindings to .yaml format - updated compatible string with version number - addressed Laurent and Hyun's review comments - removed wrappers for enable/disable API's - few API's are inlined - fixes indent, extra spaces and alignments. - added generic long write command mode support Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: dsi: This add a DT binding for Xilinx DSI TX subsystem. drm: xlnx: dsi: driver for Xilinx DSI TX subsystem .../devicetree/bindings/display/xlnx/xlnx,dsi.yaml | 147 + drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c| 701 + 4 files changed, 861 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 1.8.3.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC PATCH V2 2/2] drm: xlnx: dsi: driver for Xilinx DSI TX subsystem
The Xilinx MIPI DSI TX subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, multiple RGB color formats, video mode and command mode. The driver provides the kernel mode setting and MIPI DSI host functionalities. Signed-off-by: Venkateshwar Rao Gannavarapu --- drivers/gpu/drm/xlnx/Kconfig| 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 701 3 files changed, 714 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index aa6cd88..991bb37 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose this option if you have a Xilinx ZynqMP SoC with DisplayPort subsystem. + +config DRM_XLNX_DSI + tristate "Xilinx DRM DSI Subsystem Driver" + select DRM_MIPI_DSI + select DRM_PANEL + select DRM_PANEL_SIMPLE + help + DRM KMS driver for Xilinx programmable DSI subsystem controller. + Choose this option if you have a Xilinx MIPI DSI-TX in video + pipeline. The driver provides the kernel mode settings and MIPI + DSI host functionalities. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 2b844c6..b7ee6ef 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,4 @@ zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o + +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 000..3231043 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA MIPI DSI Tx Controller driver + * + * Copyright (C) 2017 - 2019 Xilinx, Inc. + * + * Authors: + * - Saurabh Sengar + * - Venkateshwar Rao Gannavarapu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* DSI Tx IP registers */ +#define XDSI_CCR 0x00 +#define XDSI_CCR_COREENB BIT(0) +#define XDSI_CCR_SOFTRST BIT(1) +#define XDSI_CCR_CRREADY BIT(2) +#define XDSI_CCR_CMDMODE BIT(3) +#define XDSI_CCR_DFIFORST BIT(4) +#define XDSI_CCR_CMDFIFORSTBIT(5) +#define XDSI_PCR 0x04 +#define XDSI_PCR_VIDEOMODE(x) (((x) & 0x3) << 3) +#define XDSI_PCR_VIDEOMODE_MASK(0x3 << 3) +#define XDSI_PCR_VIDEOMODE_SHIFT 3 +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) +#define XDSI_GIER 0x20 +#define XDSI_ISR 0x24 +#define XDSI_IER 0x28 +#define XDSI_STR 0x2C +#define XDSI_STR_RDY_SHPKT BIT(6) +#define XDSI_STR_RDY_LNGPKTBIT(7) +#define XDSI_STR_DFIFO_FULLBIT(8) +#define XDSI_STR_DFIFO_EMPTY BIT(9) +#define XDSI_STR_WAITFR_DATA BIT(10) +#define XDSI_STR_CMD_EXE_PGS BIT(11) +#define XDSI_STR_CCMD_PROC BIT(12) +#define XDSI_STR_LPKT_MASK (0x5 << 7) +#define XDSI_CMD 0x30 +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) +#define XDSI_DFR 0x34 +#define XDSI_TIME1 0x50 +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME1_HSA(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME2 0x54 +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) +#define XDSI_TIME3 0x58 +#define XDSI_TIME3_HFP(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME3_HBP(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME4 0x5c +#define XDSI_TIME4_VFP(x) ((x) & GENMASK(7, 0)) +#define XDSI_TIME4_VBP(x) (((x) & GENMASK(7, 0)) << 8) +#define XDSI_TIME4_VSA(x) (((x) & GENMASK(7, 0)) << 16) +#define XDSI_LTIME 0x60 +#define XDSI_BLLP_TIME 0x64 +/* + * XDSI_NUM_DATA_T represents number of data types in the + * enum mipi_dsi_pixel_format in the MIPI DSI part of DRM framework. + */ +#def
[RFC PATCH V2 0/2] Add Xilinx DSI TX driver
Xilinx DSI-TX subsytem consists of DSI controller core, AXI crossbar and D-PHY as sub blocks. DSI TX subsystem driver supports multiple lanes upto 4, RGB color formats, video mode and command modes. DSI-TX driver is implemented as an encoder driver, as it going to be the final node in display pipeline. Xilinx doesn't support any converter logic to make this as bridge driver. Xilinx doesn't have such use cases where end node can't be an encoder like DSI-TX. And Xilinx encoder drivers represents a subsystem where individual blocks can't be used with external components / encoders. Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: dsi: This add a DT binding for Xilinx DSI TX subsystem. drm: xlnx: dsi: driver for Xilinx DSI TX subsystem .../devicetree/bindings/display/xlnx/xlnx,dsi.yaml | 147 + drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c| 701 + 4 files changed, 861 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 1.8.3.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC PATCH V2 1/2] dt-bindings: display: xlnx: dsi: This add a DT binding for Xilinx DSI TX subsystem.
The Xilinx MIPI DSI (Display Serial Interface) Transmitter subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with programmable logic (FPGA).
Signed-off-by: Venkateshwar Rao Gannavarapu
---
.../devicetree/bindings/display/xlnx/xlnx,dsi.yaml | 147 +
1 file changed, 147 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
new file mode 100644
index 000..73da0d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Programmable DSI-TX Subsystem
+
+description: |
+ The programmable MIPI DSI controller of Xilinx implements display pipeline
+ based on DSI v1.3 specification. The subsystem includes multiple functional
+ blocks as below
+
+ +---+
+---+
+ | || +--+
|
+ | || v--->+AXI CROSBAR
|XXX |
+ |FRAME BUFFER | AXI STREAM | || X
X |
+ |(DMA) | +--->++++--+
XX |
+ | +<--+||MIPI|
X |
+ | |||DSI-TX |
X |
+ | |||Controller |
++ |
+ | |||+->D-PHY
| |
+ +---+||| |
| |
+ S_AXIS_ACLK |+-<+
| |
+ +>+ |
| |
+ | |
| |
+ DPHY_CLK_200M| |
| |
+ +>+ |
| |
+ + |
++ |
+ |
|
+ | MIPI DSI TX SUBSYSTEM
|
+
+---+
+
+ The DSI TX controller consists of multiple layers such as lane management
layer,
+ low-level protocol and pixel-to-byte conversion. The DSI TX controller core
+ receives stream of image data through an input stream interface. The
subsystem
+ driver supports upto 4 lane support and generates PPI trasfers towards DPHY
+ with continuous clock. It supports Burst, non-burst modes and command modes.
+
+maintainers:
+ - Venkateshwar Rao Gannavarapu
+
+properties:
+ compatible:
+const: xlnx,dsi-1.0
+
+ reg:
+maxItems: 1
+
+ clocks:
+description: List of clock specifiers
+items:
+ - description: AXI Lite clock
+ - description: Video DPHY clock
+
+ clock-names:
+items:
+ - const: s_axis_aclk
+ - const: dphy_clk_200M
+
+ xlnx,dsi-num-lanes:
+description: Maximum number of lanes that IP configured with.
+ possible values are 1, 2, 4.
+
+allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 4]
+
+ xlnx,dsi-data-type:
+description: MIPI DSI pixel format.
+ possible values are 0, 1, 2, 3.
+
+allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3]
+
+ xlnx,dsi-cmd-mode:
+description: denotes command mode support
+
+allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1]
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ output / source port node, endpoint describing modules
+ connected the DSI TX subsystem
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - xlnx,dsi-num-lanes
+ - xlnx,dsi-data-type
+ - xlnx,dsi-cmd-mode
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mipi_dsi_tx_subsystem@8000 {
+ compatible = "
RE: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi Laurent, Thanks for the comment. >-Original Message- >From: Laurent Pinchart >Sent: Wednesday, June 17, 2020 3:18 AM >To: Venkateshwar Rao Gannavarapu >Cc: Hyun Kwon ; dri-devel@lists.freedesktop.org; >airl...@linux.ie; dan...@ffwll.ch; linux-ker...@vger.kernel.org; Sandip Kothari >; Vishal Sagar >Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem > >Hi GVRao, > >Sorry for the delayed reply. > >On Tue, Jun 09, 2020 at 02:48:25AM +, Venkateshwar Rao Gannavarapu >wrote: >> Hi Laurent, >> >> Thanks for the review. >> Please see my comments about D-PHY and bridge driver implementation. >> >> On Sunday, June 7, 2020 7:55 AM, Laurent Pinchart wrote: >> > On Sun, May 31, 2020 at 05:41:50PM +, Venkateshwar Rao >Gannavarapu wrote: >> >> On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote: >> >>> On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: >> >>>> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu >wrote: >> >>>>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display >> >>>>> video data from AXI-4 stream interface. >> >>>>> >> >>>>> It supports upto 4 lanes, optional register interface for the >> >>>>> DPHY, >> >>>> >> >>>> I don't see the register interface for dphy support. >> >>> >> >>> I think the D-PHY should be supported through a PHY driver, as it >> >>> seems to be shared between different subsystems. >> >> >> >> IP has the provision to read DPHY register for debug purpose only. >> >> No programming of DPHY is required in subsystem. >> > >> > Do you know if this is the same D-PHY as used in the CSI2-RX subsystem ? >> >> Same D-PHY core has been used in MIPI CSI2 RXSS, but with different >configuration. >> >> >>>>> multiple RGB color formats, command mode and video mode. >> >>>>> This is a MIPI-DSI host driver and provides DSI bus for panels. >> >>>>> This driver also helps to communicate with its panel using panel >> >>>>> framework. >> >>>>> >> >>>>> Signed-off-by: Venkateshwar Rao Gannavarapu >> >>>>> >> >>>>> --- >> >>>>> drivers/gpu/drm/xlnx/Kconfig| 11 + >> >>>>> drivers/gpu/drm/xlnx/Makefile | 2 + >> >>>>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 >> >>>>> >> >>> >> >>> Daniel Vetter has recently expressed his opiion that bridge >> >>> drivers should go to drivers/gpu/drm/bridge/. It would then be >> >>> drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. >> >> The DSI-TX subsystem IP block is not a bridge driver. >> The DSI-TX subsystem IP block itself contains all the drm >> encoder/connector functionality and it’s the last node in display pipe line. > >The DSI-TX subsystem IP block is indeed an encoder from a hardware point of >view, but it's not necessarily the last block in the display pipeline. While >the >output of the IP core goes of the the SoC, tt would be entirely feasible to >connect it to a DP to HDMI bridge on the board, such as the ANX7737 ([1]) for >instance. This is why we're pushing for all encoder (from a hardware point of >view) drivers to be implemented as DRM bridge, in order to make them usable >in different display pipelines, without hardcoding the assumption they will be >the last encoder in the pipeline. Thanks for the details. I can understand it as SoC requirement where crtc is fixed, but as a FPGA product encoder driver should work with any of crtc driver. And I still not see bridge implementation as hard requirement. Could you please explain what problem we face, if implemented as encoder driver. > >> I didn't see any hard >> requirement to implement it into bridge driver and I see many DSI >> drivers are implemented as encoder drivers. >> Xilinx PL DRM encoder drivers are implemented in modular approach so >> that they can work with any CRTC driver which handles the DMA calls. >> So, at this stage we want to upstream as encoder driver only. >> >> >>>>> 3 files changed, 768 insertions(+) create mode 100644 >> >>>>> drivers/gpu/drm/xlnx/xlnx_dsi.c > >[1] https://www.analogix.com/en/products/convertersbridges/anx7737 > >-- >Regards, > >Laurent Pinchart Regards, GVRao ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi Laurent, Thanks for the review. Please see my comments about D-PHY and bridge driver implementation. >-Original Message- >From: Laurent Pinchart >Sent: Sunday, June 7, 2020 7:55 AM >To: Venkateshwar Rao Gannavarapu >Cc: Hyun Kwon ; dri-devel@lists.freedesktop.org; >airl...@linux.ie; dan...@ffwll.ch; linux-ker...@vger.kernel.org; Sandip Kothari > >Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem > >Hi GVRao, > >On Sun, May 31, 2020 at 05:41:50PM +, Venkateshwar Rao Gannavarapu >wrote: >> On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote: >> > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: >> >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu >wrote: >> >>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video >> >>> data from AXI-4 stream interface. >> >>> >> >>> It supports upto 4 lanes, optional register interface for the >> >>> DPHY, >> >> >> >> I don't see the register interface for dphy support. >> > >> > I think the D-PHY should be supported through a PHY driver, as it >> > seems to be shared between different subsystems. >> >> IP has the provision to read DPHY register for debug purpose only. >> No programming of DPHY is required in subsystem. > >Do you know if this is the same D-PHY as used in the CSI2-RX subsystem ? Same D-PHY core has been used in MIPI CSI2 RXSS, but with different configuration. > >> >>> multiple RGB color formats, command mode and video mode. >> >>> This is a MIPI-DSI host driver and provides DSI bus for panels. >> >>> This driver also helps to communicate with its panel using panel >> >>> framework. >> >>> >> >>> Signed-off-by: Venkateshwar Rao Gannavarapu >> >>> >> >>> --- >> >>> drivers/gpu/drm/xlnx/Kconfig| 11 + >> >>> drivers/gpu/drm/xlnx/Makefile | 2 + >> >>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 >> >>> >> > >> > Daniel Vetter has recently expressed his opiion that bridge drivers >> > should go to drivers/gpu/drm/bridge/. It would then be >> > drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. The DSI-TX subsystem IP block is not a bridge driver. The DSI-TX subsystem IP block itself contains all the drm encoder/connector functionality and it’s the last node in display pipe line. I didn't see any hard requirement to implement it into bridge driver and I see many DSI drivers are implemented as encoder drivers. Xilinx PL DRM encoder drivers are implemented in modular approach so that they can work with any CRTC driver which handles the DMA calls. So, at this stage we want to upstream as encoder driver only. >> > >> >>> 3 files changed, 768 insertions(+) create mode 100644 >> >>> drivers/gpu/drm/xlnx/xlnx_dsi.c > >[snip] > >-- >Regards, > >Laurent Pinchart Regards, GVRao ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi Laurent & Hyun, Thanks for the review. >-Original Message- >From: Laurent Pinchart >Sent: Sunday, May 24, 2020 8:38 AM >To: Venkateshwar Rao Gannavarapu >Cc: Hyun Kwon ; Hyun Kwon ; dri- >de...@lists.freedesktop.org; airl...@linux.ie; dan...@ffwll.ch; linux- >ker...@vger.kernel.org; Sandip Kothari ; Venkateshwar >Rao Gannavarapu >Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem > >Hi GVRao, > >Thank you for the patch. > >On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu >wrote: >> > The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video >> > data from AXI-4 stream interface. >> > >> > It supports upto 4 lanes, optional register interface for the DPHY, >> >> I don't see the register interface for dphy support. > >I think the D-PHY should be supported through a PHY driver, as it seems to be >shared between different subsystems. > IP has the provision to read DPHY register for debug purpose only. No programming of DPHY is required in subsystem. >> > multiple RGB color formats, command mode and video mode. >> > This is a MIPI-DSI host driver and provides DSI bus for panels. >> > This driver also helps to communicate with its panel using panel >> > framework. >> > >> > Signed-off-by: Venkateshwar Rao Gannavarapu >> > >> > --- >> > drivers/gpu/drm/xlnx/Kconfig| 11 + >> > drivers/gpu/drm/xlnx/Makefile | 2 + >> > drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 >> > > >Daniel Vetter has recently expressed his opiion that bridge drivers should go >to >drivers/gpu/drm/bridge/. It would then be drivers/gpu/drm/bridge/xlnx/. I don't >have a strong opinion myself. > >> > 3 files changed, 768 insertions(+) >> > create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c >> > >> > diff --git a/drivers/gpu/drm/xlnx/Kconfig >> > b/drivers/gpu/drm/xlnx/Kconfig index aa6cd88..73873cf 100644 >> > --- a/drivers/gpu/drm/xlnx/Kconfig >> > +++ b/drivers/gpu/drm/xlnx/Kconfig >> > @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB >> > This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose >> > this option if you have a Xilinx ZynqMP SoC with DisplayPort >> > subsystem. >> > + >> > +config DRM_XLNX_DSI >> > +tristate "Xilinx DRM DSI Subsystem Driver" >> > +select DRM_MIPI_DSI >> > +select DRM_PANEL >> > +select DRM_PANEL_SIMPLE >> > +help >> > +This enables support for Xilinx MIPI-DSI. >> >> This sentence is not needed with below. Could you please rephrase the whole? OK. >> >> > +This is a DRM/KMS driver for Xilinx programmable DSI controller. >> > +Choose this option if you have a Xilinx MIPI DSI-TX controller >> > +subsytem. >> >> These seem incorrectly indented. Will check the indentation. >> >> > diff --git a/drivers/gpu/drm/xlnx/Makefile >> > b/drivers/gpu/drm/xlnx/Makefile index 2b844c6..b7ee6ef 100644 >> > --- a/drivers/gpu/drm/xlnx/Makefile >> > +++ b/drivers/gpu/drm/xlnx/Makefile >> > @@ -1,2 +1,4 @@ >> > zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o >> > obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o >> > + >> > +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o >> > diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c >> > b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index >> > 000..b8cae59 >> > --- /dev/null >> > +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c >> > @@ -0,0 +1,755 @@ >> > +// SPDX-License-Identifier: GPL-2.0 >> > +/* >> > + * Xilinx FPGA MIPI DSI Tx Controller driver >> > + * >> > + * Copyright (C) 2017 - 2019 Xilinx, Inc. >> > + * >> > + * Authors: >> > + * - Saurabh Sengar >> > + * - Venkateshwar Rao Gannavarapu >> > + >> > + */ >> > + >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include #include >> > +#include #include >> > + >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > +#include >> > + >> > +#include >> > +#include &g
RE: [RFC PATCH 1/2] dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings
Hi Sam, thanks for your comments. >-Original Message- >From: Sam Ravnborg >Sent: Sunday, April 26, 2020 1:59 AM >To: Venkateshwar Rao Gannavarapu >Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; dri- >de...@lists.freedesktop.org; Sandip Kothari ; >airl...@linux.ie; linux-ker...@vger.kernel.org; Venkateshwar Rao Gannavarapu > >Subject: Re: [RFC PATCH 1/2] dt-bindings: display: xlnx: Add Xilinx DSI TX >subsystem bindings > >Hi Venkateshwar > >On Tue, Apr 21, 2020 at 02:50:55AM +0530, Venkateshwar Rao Gannavarapu >wrote: >> This add a dt binding for Xilinx DSI TX subsystem. >> >> The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem >> implements the Mobile Industry Processor Interface (MIPI) based >> display interface. It supports the interface with the programmable logic >(FPGA). >> >> Signed-off-by: Venkateshwar Rao Gannavarapu >> >> --- >> .../devicetree/bindings/display/xlnx/xlnx,dsi.txt | 68 >> ++ > >Sorry, but new bindings in DT Schema format (.yaml) please. >We are working on migrating all bindings to DT Schema and do not want to add >new bindings in the old format. > I will address bindings in YAML format in V2 patch. > >> 1 file changed, 68 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt >> >> diff --git >> a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt >> b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt >> new file mode 100644 >> index 000..ef69729 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt >> @@ -0,0 +1,68 @@ >> +Device-Tree bindings for Xilinx MIPI DSI Tx IP core >> + >> +The IP core supports transmission of video data in MIPI DSI protocol. >> + >> +Required properties: >> + - compatible: Should be "xlnx-dsi". >> + - reg: physical base address and length of the registers set for the >> device. >> + - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller. >> + The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and >> + line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by >> + Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the >> packet >> + thus framed is convered to serial data by MIPI D-PHY core. Please refer >> + Xilinx pg238 for more details. This value should be equal to the number >> + of lanes supported by the connected DSI panel. Panel has to support this >> + value or has to be programmed to the same value that DSI Tx controller is >> + configured to. >> + - xlnx,dsi-datatype: Color format. The value should be one of >> +"MIPI_DSI_FMT_RGB888", >> + "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or >"MIPI_DSI_FMT_RGB565". >> + - #address-cells, #size-cells: should be set respectively to <1> and <0> >> + according to DSI host bindings (see MIPI DSI bindings [1]) >> + - clock-names: Must contain "s_axis_aclk" and "dphy_clk_200M" in same >order as >> + clocks listed in clocks property. >> + - clocks: List of phandles to Video and 200Mhz DPHY clocks. >> + - port: Logical block can be used / connected independently with >> + external device. In the display controller port nodes, topology >> + for entire pipeline should be described using the DT bindings defined in >> + Documentation/devicetree/bindings/graph.txt. > >> + - simple_panel: The subnode for connected panel. This represents the >> + DSI peripheral connected to the DSI host node. Please refer to >> + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The >> + simple-panel driver has auo,b101uan01 panel timing parameters added >along >> + with other existing panels. DSI driver derive the required Tx IP >> controller >> + timing values from the panel timing parameters.A >Please always use either a port or a ports node. > OK. > Sam > >> + >> +Required simple_panel properties: >> + - compatible: Value should be one of the panel names in >> + Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01". >> + For available panel compatible strings, please refer to bindings in >> + Documentation/devicetree/bindings/display/panel/ >> + >> +Optional properties: >> + - xlnx,dsi-cmd-mode: denotes command mode enable. >> + >> +[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt >> +[2]: Documentation/devicetree
[RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, optional register interface for the DPHY, multiple RGB color formats, command mode and video mode. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework. Signed-off-by: Venkateshwar Rao Gannavarapu --- drivers/gpu/drm/xlnx/Kconfig| 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 3 files changed, 768 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index aa6cd88..73873cf 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose this option if you have a Xilinx ZynqMP SoC with DisplayPort subsystem. + +config DRM_XLNX_DSI +tristate "Xilinx DRM DSI Subsystem Driver" +select DRM_MIPI_DSI +select DRM_PANEL +select DRM_PANEL_SIMPLE +help + This enables support for Xilinx MIPI-DSI. + This is a DRM/KMS driver for Xilinx programmable DSI controller. + Choose this option if you have a Xilinx MIPI DSI-TX controller + subsytem. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 2b844c6..b7ee6ef 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,4 @@ zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o + +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 000..b8cae59 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA MIPI DSI Tx Controller driver + * + * Copyright (C) 2017 - 2019 Xilinx, Inc. + * + * Authors: + * - Saurabh Sengar + * - Venkateshwar Rao Gannavarapu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* DSI Tx IP registers */ +#define XDSI_CCR 0x00 +#define XDSI_CCR_COREENB BIT(0) +#define XDSI_CCR_SOFTRST BIT(1) +#define XDSI_CCR_CRREADY BIT(2) +#define XDSI_CCR_CMDMODE BIT(3) +#define XDSI_CCR_DFIFORST BIT(4) +#define XDSI_CCR_CMDFIFORSTBIT(5) +#define XDSI_PCR 0x04 +#define XDSI_PCR_VIDEOMODE(x) (((x) & 0x3) << 3) +#define XDSI_PCR_VIDEOMODE_MASK(0x3 << 3) +#define XDSI_PCR_VIDEOMODE_SHIFT 3 +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) +#define XDSI_GIER 0x20 +#define XDSI_ISR 0x24 +#define XDSI_IER 0x28 +#define XDSI_STR 0x2C +#define XDSI_STR_RDY_SHPKT BIT(6) +#define XDSI_STR_RDY_LNGPKTBIT(7) +#define XDSI_STR_DFIFO_FULLBIT(8) +#define XDSI_STR_DFIFO_EMPTY BIT(9) +#define XDSI_STR_WAITFR_DATA BIT(10) +#define XDSI_STR_CMD_EXE_PGS BIT(11) +#define XDSI_STR_CCMD_PROC BIT(12) +#define XDSI_STR_LPKT_MASK (0x5 << 7) +#define XDSI_CMD 0x30 +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) +#define XDSI_DFR 0x34 +#define XDSI_TIME1 0x50 +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME1_HSA(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME2 0x54 +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) +#define XDSI_TIME3 0x58 +#define XDSI_TIME3_HFP(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME3_HBP(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME4 0x5c +#define XDSI_TIME4_VFP(x) ((x) & GENMASK(7, 0)) +#define XDSI_TIME4_VBP(x) (((x) & GENMASK(7, 0)) << 8) +#define XDSI_TIME4_VSA(x) (((x) & GENMASK(7, 0)) << 16) +#define XDSI_LTIME 0x60 +#define XDSI_BLLP_TIME 0x64 +/* + * XDSI_NUM_DATA_T represents number of data types in the + * enum mipi
[RFC PATCH 0/2] Add Xilinx DSI-TX DRM driver
MIPI DSI TX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between the video processing subsystems and MIPI-based displays. An internal high-speed physical layer design, D-PHY, is provided to allow direct connection to display peripherals. The subsystem consists of the following sub-blocks: - MIPI D-PHY - MIPI DSI TX Controller - AXI Crossbar Please refer pg238 [1]. The DSI TX Controller receives stream of image data through an input stream interface. At design time, this subsystem can be configured to number of lanes and command mode support. This patch series adds the dt-binding and DRM driver for Xilinx DSI-TX soft IP. patch is created on git://linuxtv.org/pinchartl/media.git drm/dpsub/next References: [1]: https://www.xilinx.com/support/documentation/ip_documentation/mipi_dsi_tx_subsystem/v2_0/pg238-mipi-dsi-tx.pdf Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings drm: xlnx: driver for Xilinx DSI TX Subsystem .../devicetree/bindings/display/xlnx/xlnx,dsi.txt | 68 ++ drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c| 755 + 4 files changed, 836 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC PATCH 1/2] dt-bindings: display: xlnx: Add Xilinx DSI TX subsystem bindings
This add a dt binding for Xilinx DSI TX subsystem.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with the programmable logic (FPGA).
Signed-off-by: Venkateshwar Rao Gannavarapu
---
.../devicetree/bindings/display/xlnx/xlnx,dsi.txt | 68 ++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt
new file mode 100644
index 000..ef69729
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt
@@ -0,0 +1,68 @@
+Device-Tree bindings for Xilinx MIPI DSI Tx IP core
+
+The IP core supports transmission of video data in MIPI DSI protocol.
+
+Required properties:
+ - compatible: Should be "xlnx-dsi".
+ - reg: physical base address and length of the registers set for the device.
+ - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller.
+ The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and
+ line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by
+ Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet
+ thus framed is convered to serial data by MIPI D-PHY core. Please refer
+ Xilinx pg238 for more details. This value should be equal to the number
+ of lanes supported by the connected DSI panel. Panel has to support this
+ value or has to be programmed to the same value that DSI Tx controller is
+ configured to.
+ - xlnx,dsi-datatype: Color format. The value should be one of
"MIPI_DSI_FMT_RGB888",
+ "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565".
+ - #address-cells, #size-cells: should be set respectively to <1> and <0>
+ according to DSI host bindings (see MIPI DSI bindings [1])
+ - clock-names: Must contain "s_axis_aclk" and "dphy_clk_200M" in same order as
+ clocks listed in clocks property.
+ - clocks: List of phandles to Video and 200Mhz DPHY clocks.
+ - port: Logical block can be used / connected independently with
+ external device. In the display controller port nodes, topology
+ for entire pipeline should be described using the DT bindings defined in
+ Documentation/devicetree/bindings/graph.txt.
+ - simple_panel: The subnode for connected panel. This represents the
+ DSI peripheral connected to the DSI host node. Please refer to
+ Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The
+ simple-panel driver has auo,b101uan01 panel timing parameters added along
+ with other existing panels. DSI driver derive the required Tx IP controller
+ timing values from the panel timing parameters.
+
+Required simple_panel properties:
+ - compatible: Value should be one of the panel names in
+ Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01".
+ For available panel compatible strings, please refer to bindings in
+ Documentation/devicetree/bindings/display/panel/
+
+Optional properties:
+ - xlnx,dsi-cmd-mode: denotes command mode enable.
+
+[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ mipi_dsi_tx_subsystem@8000 {
+ compatible = "xlnx,dsi";
+ reg = <0x0 0x8000 0x0 0x1>;
+ xlnx,dsi-num-lanes = <4>;
+ xlnx,dsi-data-type = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "dphy_clk_200M", "s_axis_aclk";
+ clocks = <_clk_0>, <_clk_1>;
+ encoder_dsi_port: port@0 {
+ reg = <0>;
+ dsi_encoder: endpoint {
+ remote-endpoint = <_ep>;
+ };
+ };
+ simple_panel: simple-panel@0 {
+ compatible = "auo,b101uan01";
+ reg = <0>;
+ };
+ };
--
2.7.4
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Delete this email message and any attachments immediately.
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