[PATCH i-g-t] tests/drm_read: drm_read fails for subtest invalid-buffer on chrome
Chrome platforms is unable to handle reading from -1. It terminates the test after reporting buffer overflow. Hence, changed the address for invalid buffer to NULL instead of -1. With this change, errno becomes EINTR when reading from NULL location. To accomodate, also changing the check of errno to EINTR instead of EFAULT Change-Id: I5f844af087c9826fcbcfbe301f0df5f727cb013b Signed-off-by: Vidya Srinivas --- tests/drm_read.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/drm_read.c b/tests/drm_read.c index ccf9d822fd8d..a8816bc1e587 100644 --- a/tests/drm_read.c +++ b/tests/drm_read.c @@ -106,8 +106,8 @@ static void test_invalid_buffer(int in) alarm(1); - igt_assert_eq(read(fd, (void *)-1, 4096), -1); - igt_assert_eq(errno, EFAULT); + igt_assert_eq(read(fd, (void *)NULL, 4096), -1); + igt_assert_eq(errno, EINTR); teardown(fd); } -- 2.7.4
[PATCH i-g-t] tests/kms_big_fb: Wait for vblank before collecting CRC
Without wait for vblank, CRC mismatch is seen
between big and small CRC on few systems
Change-Id: I3bec931aa901130997e693ac1cacf389e2a8100f
Signed-off-by: Vidya Srinivas
---
tests/kms_big_fb.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c
index b2027b6b9d1b..7d78ff829d41 100644
--- a/tests/kms_big_fb.c
+++ b/tests/kms_big_fb.c
@@ -254,6 +254,7 @@ static void unset_lut(data_t *data)
static bool test_plane(data_t *data)
{
igt_plane_t *plane = data->plane;
+ igt_display_t *display = >display;
struct igt_fb *small_fb = >small_fb;
struct igt_fb *big_fb = >big_fb;
int w = data->big_fb_width - small_fb->width;
@@ -337,16 +338,17 @@ static bool test_plane(data_t *data)
igt_display_commit2(>display, data->display.is_atomic ?
COMMIT_ATOMIC : COMMIT_UNIVERSAL);
-
+ igt_wait_for_vblank(data->drm_fd,
display->pipes[data->pipe].crtc_offset);
igt_pipe_crc_collect_crc(data->pipe_crc, _crc);
igt_plane_set_fb(plane, big_fb);
igt_fb_set_position(big_fb, plane, x, y);
igt_fb_set_size(big_fb, plane, small_fb->width,
small_fb->height);
+
igt_plane_set_size(plane, data->width, data->height);
igt_display_commit2(>display, data->display.is_atomic ?
COMMIT_ATOMIC : COMMIT_UNIVERSAL);
-
+ igt_wait_for_vblank(data->drm_fd,
display->pipes[data->pipe].crtc_offset);
igt_pipe_crc_collect_crc(data->pipe_crc, _crc);
igt_plane_set_fb(plane, NULL);
--
2.7.4
[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 106 +++-
drivers/gpu/drm/i915/i915_reg.h | 18 +-
2 files changed, 92 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..0a535932ed18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5404,26 +5404,37 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_tp_reg, dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_tp_reg = DP_TP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_tp_reg = TGL_DP_TP_CTL(pipe);
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5443,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
[PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
[PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support
From: Khaled Almahallawy
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
v2: uniform bit names TP4a/b/c (Manasi)
Signed-off-by: Khaled Almahallawy
Reviewed-by: Manasi Navare
Tested-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 04231ca5643b..a8a3ffcef5dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 pattern_val;
+ u32 pattern_val, dp_tp_ctl;
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
@@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
+ case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+ DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ dp_tp_ctl = intel_de_read(dev_priv,
TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+ dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
+ dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
dp_tp_ctl);
+ break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..4850890918dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9974,6 +9974,10 @@ enum skl_power_gate {
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
From: Khaled Almahallawy Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare (v1) Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, >hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250 -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support
From: Khaled Almahallawy
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
v2: uniform bit names TP4a/b/c (Manasi)
Signed-off-by: Khaled Almahallawy
Reviewed-by: Manasi Navare
Tested-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 04231ca5643b..a8a3ffcef5dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 pattern_val;
+ u32 pattern_val, dp_tp_ctl;
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
@@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
+ case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+ DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ dp_tp_ctl = intel_de_read(dev_priv,
TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+ dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
+ dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
dp_tp_ctl);
+ break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..4850890918dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9974,6 +9974,10 @@ enum skl_power_gate {
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
2.7.4
___
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[PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
[PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
From: Khaled Almahallawy Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare (v1) Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, >hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250 -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
[PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support
From: Khaled Almahallawy
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
v2: uniform bit names TP4a/b/c (Manasi)
Signed-off-by: Khaled Almahallawy
Reviewed-by: Manasi Navare
Tested-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 04231ca5643b..a8a3ffcef5dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 pattern_val;
+ u32 pattern_val, dp_tp_ctl;
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
@@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
+ case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+ DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ dp_tp_ctl = intel_de_read(dev_priv,
TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+ dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
+ dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
dp_tp_ctl);
+ break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..4850890918dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9974,6 +9974,10 @@ enum skl_power_gate {
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
From: Khaled Almahallawy Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare (v1) Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, >hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250 -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/i915/dp: DP PHY compliance for EHL/JSL
v2: Rebased patch on top of:
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
pattern_val = 0xFB;
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
@@ -5478,22
[PATCH 1/3] drm/dp: Add PHY_TEST_PATTERN CP2520 Pattern 2 and 3
From: Khaled Almahallawy Add the missing CP2520 pattern 2 and 3 phy compliance patterns v2: cosemtic changes Reviewed-by: Manasi Navare (v1) Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/drm_dp_helper.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d0fb78c6aca6 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1583,7 +1583,7 @@ int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, return err; break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, >hbr2_reset, sizeof(data->hbr2_reset)); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e2d2df5e869e..73285b4c25a0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -708,7 +708,9 @@ # define DP_PHY_TEST_PATTERN_ERROR_COUNT0x2 # define DP_PHY_TEST_PATTERN_PRBS7 0x3 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT10x5 +# define DP_PHY_TEST_PATTERN_CP2520_PAT20x6 +# define DP_PHY_TEST_PATTERN_CP2520_PAT30x7 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250 -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL
Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.
v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 81 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++--
2 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+ i915_reg_t dp_comp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+ else if (IS_TIGERLAKE(dev_priv))
+ dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
* current firmware of DPR-100 could not set it, so hardcoding
* now for complaince test.
*/
- DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0
0x0f83e0f8 0xf83e\n");
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0),
pattern_val);
pattern_val = 0x0f83e0f8;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1),
pattern_val);
pattern_val = 0xf83e;
- intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
- intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_de_write(dev_priv,
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+ pattern_val);
+ else
+ intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2),
pattern_val);
+ intel_de_write(dev_priv, dp_comp_reg,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
*/
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
[PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support
From: Khaled Almahallawy
Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
v2: uniform bit names TP4a/b/c (Manasi)
Signed-off-by: Khaled Almahallawy
Reviewed-by: Manasi Navare
Tested-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 --
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 04231ca5643b..a8a3ffcef5dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 pattern_val;
+ u32 pattern_val, dp_tp_ctl;
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
- case DP_PHY_TEST_PATTERN_CP2520:
+ case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
@@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp
*intel_dp)
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
+ case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+ DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+ intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+ dp_tp_ctl = intel_de_read(dev_priv,
TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+ dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
+ dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+ intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
dp_tp_ctl);
+ break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab4b1abd4364..4850890918dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9974,6 +9974,10 @@ enum skl_power_gate {
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/i915/dp: DP PHY compliance for JSL
Signed-off-by: Khaled Almahallawy
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/display/intel_dp.c | 40 ++---
1 file changed, 32 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7223367171d1..44663e8ac9a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp
*intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+ u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value,
trans_ddi_port_mask;
+ enum port port = intel_dig_port->base.port;
+ i915_reg_t dp_tp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ dp_tp_reg = DP_TP_CTL(port);
+ trans_ddi_port_mask = TRANS_DDI_PORT_MASK;
+ } else if (IS_TIGERLAKE(dev_priv)) {
+ dp_tp_reg = TGL_DP_TP_CTL(pipe);
+ trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK;
+ }
trans_ddi_func_ctl_value = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(pipe));
trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
- dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
+ dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg);
trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
- TGL_TRANS_DDI_PORT_MASK);
+ trans_ddi_port_mask);
trans_conf_value &= ~PIPECONF_ENABLE;
dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
trans_ddi_func_ctl_value);
- intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+ intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value);
}
static void
@@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp
*intel_dp, uint8_t lane_cnt)
enum port port = intel_dig_port->base.port;
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
- u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+ u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value,
trans_ddi_sel_port;
+ i915_reg_t dp_tp_reg;
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ dp_tp_reg = DP_TP_CTL(port);
+ trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port);
+ } else if (IS_TIGERLAKE(dev_priv)) {
+ dp_tp_reg = TGL_DP_TP_CTL(pipe);
+ trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port);
+ }
trans_ddi_func_ctl_value = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(pipe));
trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
- TGL_TRANS_DDI_SELECT_PORT(port);
+ trans_ddi_sel_port;
trans_conf_value |= PIPECONF_ENABLE;
dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
- intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+ intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value);
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
trans_ddi_func_ctl_value);
}
@@ -5557,6 +5575,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp)
static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct drm_i915_private *dev_priv = i915;
u8 response = DP_TEST_NAK;
u8 request = 0;
int status;
@@ -5582,6 +5601,11 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
response = intel_dp_autotest_edid(intel_dp);
break;
case DP_TEST_LINK_PHY_TEST_PATTERN:
+ if (!IS_ELKHARTLAKE(dev_priv) || !IS_TIGERLAKE(dev_priv)) {
+ drm_dbg_kms(>drm,
+ "PHY compliance for platform not supported\n");
+ return;
+ }
drm_dbg_kms(>drm, "PHY_PATTERN test requested\n");
response = intel_dp_autotest_phy_pattern(intel_dp);
break;
--
2.7.4
___
dri-devel mailing list
dri-d
[PATCH] drm: Fix for invalid pruning of modes in dual display cases
Currently in dual display connected boot scenarios, minimum of the resolutions
is taken for fb width and height as reference. Based on this resolution, other
modes are pruned.
Example Scenario: If DSI mode is 2560x1440 and HDMI is 1920x1080, during the
probing
the fb width and height is set to max 1920x1080 and the DSI mode gets pruned as
it is
more than the reference. As a result, there is no DSI display.
Patch fixes this issue by taking the max of the resolutions and creating the fb
based on the same.
Signed-off-by: Vidya Srinivas
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_fb_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index e934b54..6afc06f 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1482,8 +1482,8 @@ static int drm_fb_helper_single_fb_probe(struct
drm_fb_helper *fb_helper,
memset(, 0, sizeof(struct drm_fb_helper_surface_size));
sizes.surface_depth = 24;
sizes.surface_bpp = 32;
- sizes.fb_width = (unsigned)-1;
- sizes.fb_height = (unsigned)-1;
+ sizes.fb_width = 0;
+ sizes.fb_height = 0;
/* if driver picks 8 or 16 by default use that
for both depth/bpp */
@@ -1560,9 +1560,9 @@ static int drm_fb_helper_single_fb_probe(struct
drm_fb_helper *fb_helper,
}
if (lasth)
- sizes.fb_width = min_t(u32, desired_mode->hdisplay +
x, sizes.fb_width);
+ sizes.fb_width = max_t(u32, desired_mode->hdisplay +
x, sizes.fb_width);
if (lastv)
- sizes.fb_height = min_t(u32, desired_mode->vdisplay +
y, sizes.fb_height);
+ sizes.fb_height = max_t(u32, desired_mode->vdisplay +
y, sizes.fb_height);
}
if (crtc_count == 0 || sizes.fb_width == -1 || sizes.fb_height == -1) {
--
1.9.1
