[PATCH] drm/dp: Add DP phy test pattern DPCD bit definitions

2019-03-21 Thread clinton . a . taylor 
From: Clinton Taylor 

Added PHY_TEST_PATTERN_SEL bit definitions for DPCD 00248h and
HBR2_COMPLIANCE_SCRAMBLER_RESET DPCD definition.

Signed-off-by: Clinton Taylor 
---
 include/drm/drm_dp_helper.h | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 97ce790a5b5a..d22e293e457c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -564,8 +564,10 @@
 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO  (1 << 6) /* DPCD >= 1.2 */
 
 #define DP_TEST_LINK_RATE  0x219
-# define DP_LINK_RATE_162  (0x6)
-# define DP_LINK_RATE_27   (0xa)
+# define DP_TEST_LINK_RATE_162   0x6
+# define DP_TEST_LINK_RATE_270xa
+# define DP_TEST_LINK_RATE_54   0x14
+# define DP_TEST_LINK_RATE_81   0x1e
 
 #define DP_TEST_LANE_COUNT 0x220
 
@@ -640,6 +642,17 @@
 # define DP_TEST_COUNT_MASK0xf
 
 #define DP_TEST_PHY_PATTERN 0x248
+# define DP_TEST_PHY_PATTERN_NONE  0
+# define DP_TEST_PHY_PATTERN_D10_2 1
+# define DP_TEST_PHY_PATTERN_ERROR_COUNT   2
+# define DP_TEST_PHY_PATTERN_PRBS7 3
+# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM  4
+# define DP_TEST_PHY_PATTERN_CP2520_1  5 /* was HBR2 Compliance */
+# define DP_TEST_PHY_PATTERN_CP2520_2  6 /* DP 1.4 */
+# define DP_TEST_PHY_PATTERN_CP2520_3  7 /* DP 1.4 TPS4 */
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET   0x24A
+
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250
 #defineDP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 #defineDP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
-- 
2.19.1

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH] drm/edid: VSDB yCBCr420 Deep Color mode bit definitions

2018-10-05 Thread clinton . a . taylor 
From: Clint Taylor 

HDMI Forum VSDB YCBCR420 deep color capability bits are 2:0. Correct
definitions in the header for the mask to work correctly.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107893
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_edid.c | 2 +-
 include/drm/drm_edid.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1e2b940..ff0bfc6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4282,7 +4282,7 @@ static void drm_parse_ycbcr420_deep_color_info(struct 
drm_connector *connector,
struct drm_hdmi_info *hdmi = >display_info.hdmi;
 
dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
-   hdmi->y420_dc_modes |= dc_mask;
+   hdmi->y420_dc_modes = dc_mask;
 }
 
 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b25d12e..e3c4048 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -214,9 +214,9 @@ struct detailed_timing {
 #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
 
 /* YCBCR 420 deep color modes */
-#define DRM_EDID_YCBCR420_DC_48  (1 << 6)
-#define DRM_EDID_YCBCR420_DC_36  (1 << 5)
-#define DRM_EDID_YCBCR420_DC_30  (1 << 4)
+#define DRM_EDID_YCBCR420_DC_48  (1 << 2)
+#define DRM_EDID_YCBCR420_DC_36  (1 << 1)
+#define DRM_EDID_YCBCR420_DC_30  (1 << 0)
 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
DRM_EDID_YCBCR420_DC_36 | \
DRM_EDID_YCBCR420_DC_30)
-- 
1.9.1

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH V2] drm/cec: Add Source Physical address decode to drm_display_info

2017-05-16 Thread clinton . a . taylor 
From: Clint Taylor 

During VSDB decode bytes 4 and 5 contain the source physical address for
use the HDMI CEC. Make this data available as part of drm_display_info.

V2: Fix HTMLDOCS warnings for struct drm_hdmi_cec_spa

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_edid.c  | 10 ++
 include/drm/drm_connector.h | 20 
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2e55599..e64605b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3938,6 +3938,16 @@ static void drm_parse_hdmi_deep_color_info(struct 
drm_connector *connector,
struct drm_display_info *info = >display_info;
u8 len = cea_db_payload_len(db);
 
+   if (len >= 4) {
+   info->src_phy_addr.a = (db[4] & 0xF0) >> 4;
+   info->src_phy_addr.b = db[4] & 0x0F;
+   info->src_phy_addr.c = (db[5] & 0xF0) >> 4;
+   info->src_phy_addr.d = db[5] & 0x0F;
+
+   DRM_DEBUG_KMS("HDMI SPA = %01x.%01x.%01x.%01x\n",
+   info->src_phy_addr.a, info->src_phy_addr.b,
+   info->src_phy_addr.c, info->src_phy_addr.d);
+   }
if (len >= 6)
info->dvi_dual = db[6] & 1;
if (len >= 7)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9c15993..0df3511 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -127,6 +127,21 @@ struct drm_scdc {
struct drm_scrambling scrambling;
 };
 
+/**
+ * struct drm_hdmi_cec_spa
+ *
+ * Provides the Source Physical address from an HDMI VSDB EDID
+ */
+struct drm_hdmi_cec_spa {
+   /** @a: sink's Source Physical Address A field */
+   u8 a;
+   /** @b: sink's Source Physical Address B field */
+   u8 b;
+   /** @c: sink's Source Physical Address C field */
+   u8 c;
+   /** @d: sink's Source Physical Address D field */
+   u8 d;
+};
 
 /**
  * struct drm_hdmi_info - runtime information about the connected HDMI sink
@@ -263,6 +278,11 @@ struct drm_display_info {
 * @hdmi: advance features of a HDMI sink.
 */
struct drm_hdmi_info hdmi;
+
+   /**
+* @src_phy_addr: HDMI CEC Source Physical Address
+*/
+   struct drm_hdmi_cec_spa src_phy_addr;
 };
 
 int drm_display_info_set_bus_formats(struct drm_display_info *info,
-- 
1.9.1

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH] drm/cec: Add Source Physical address decode to drm_display_info

2017-05-15 Thread clinton . a . taylor 
From: Clint Taylor 

During VSDB decode bytes 4 and 5 contain the source physical address for
use the HDMI CEC. Make this data available as part of drm_display_info.

Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_edid.c  | 10 ++
 include/drm/drm_connector.h | 16 
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2e55599..e64605b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3938,6 +3938,16 @@ static void drm_parse_hdmi_deep_color_info(struct 
drm_connector *connector,
struct drm_display_info *info = >display_info;
u8 len = cea_db_payload_len(db);
 
+   if (len >= 4) {
+   info->src_phy_addr.a = (db[4] & 0xF0) >> 4;
+   info->src_phy_addr.b = db[4] & 0x0F;
+   info->src_phy_addr.c = (db[5] & 0xF0) >> 4;
+   info->src_phy_addr.d = db[5] & 0x0F;
+
+   DRM_DEBUG_KMS("HDMI SPA = %01x.%01x.%01x.%01x\n",
+   info->src_phy_addr.a, info->src_phy_addr.b,
+   info->src_phy_addr.c, info->src_phy_addr.d);
+   }
if (len >= 6)
info->dvi_dual = db[6] & 1;
if (len >= 7)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9c15993..4e2ee21 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -127,6 +127,17 @@ struct drm_scdc {
struct drm_scrambling scrambling;
 };
 
+/**
+ * struct drm_hdmi_cec_spa
+ *
+ * Provides the Source Physical address from an HDMI VSDB EDID
+ */
+struct drm_hdmi_cec_spa {
+   u8 a;
+   u8 b;
+   u8 c;
+   u8 d;
+};
 
 /**
  * struct drm_hdmi_info - runtime information about the connected HDMI sink
@@ -263,6 +274,11 @@ struct drm_display_info {
 * @hdmi: advance features of a HDMI sink.
 */
struct drm_hdmi_info hdmi;
+
+   /**
+* @src_phy_addr: HDMI CEC Source Physical Address
+*/
+   struct drm_hdmi_cec_spa src_phy_addr;
 };
 
 int drm_display_info_set_bus_formats(struct drm_display_info *info,
-- 
1.9.1

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3] drm/cec: Add CEC over Aux register definitions

2017-04-20 Thread clinton . a . taylor 
From: Clint Taylor 

Adding DPCD register definitions from the DP 1.3 specification for CEC
over AUX support.

V2: Add DP_ prefix to all defines.
V3: missed prefixes from the ESI1 defines

Cc: Jani Nikula 

Reviewed-by: Jani Nikula 
Signed-off-by: Clint Taylor 
---
 include/drm/drm_dp_helper.h |   59 +++
 1 file changed, 59 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c0bd0d7..3f4ad70 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -603,6 +603,9 @@
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
 
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
+# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE(1 << 0)
+# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
+# define DP_CEC_IRQ  (1 << 2)
 
 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005   /* 1.2 */
 
@@ -636,6 +639,62 @@
 # define DP_VSC_EXT_CEA_SDP_SUPPORTED  (1 << 6)  /* DP 1.4 */
 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)  /* DP 1.4 */
 
+/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
+#define DP_CEC_TUNNELING_CAPABILITY0x3000
+# define DP_CEC_TUNNELING_CAPABLE   (1 << 0)
+# define DP_CEC_SNOOPING_CAPABLE(1 << 1)
+# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
+
+#define DP_CEC_TUNNELING_CONTROL   0x3001
+# define DP_CEC_TUNNELING_ENABLE(1 << 0)
+# define DP_CEC_SNOOPING_ENABLE (1 << 1)
+
+#define DP_CEC_RX_MESSAGE_INFO 0x3002
+# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
+# define DP_CEC_RX_MESSAGE_LEN_SHIFT0
+# define DP_CEC_RX_MESSAGE_HPD_STATE(1 << 4)
+# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
+# define DP_CEC_RX_MESSAGE_ACKED(1 << 6)
+# define DP_CEC_RX_MESSAGE_ENDED(1 << 7)
+
+#define DP_CEC_TX_MESSAGE_INFO 0x3003
+# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
+# define DP_CEC_TX_MESSAGE_LEN_SHIFT0
+# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
+# define DP_CEC_TX_RETRY_COUNT_SHIFT4
+# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
+
+#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
+# define DP_CEC_RX_MESSAGE_INFO_VALID   (1 << 0)
+# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
+# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
+# define DP_CEC_TX_LINE_ERROR   (1 << 5)
+# define DP_CEC_TX_ADDRESS_NACK_ERROR   (1 << 6)
+# define DP_CEC_TX_DATA_NACK_ERROR  (1 << 7)
+
+#define DP_CEC_LOGICAL_ADDRESS_MASK0x300E /* 0x300F word */
+# define DP_CEC_LOGICAL_ADDRESS_0   (1 << 0)
+# define DP_CEC_LOGICAL_ADDRESS_1   (1 << 1)
+# define DP_CEC_LOGICAL_ADDRESS_2   (1 << 2)
+# define DP_CEC_LOGICAL_ADDRESS_3   (1 << 3)
+# define DP_CEC_LOGICAL_ADDRESS_4   (1 << 4)
+# define DP_CEC_LOGICAL_ADDRESS_5   (1 << 5)
+# define DP_CEC_LOGICAL_ADDRESS_6   (1 << 6)
+# define DP_CEC_LOGICAL_ADDRESS_7   (1 << 7)
+#define DP_CEC_LOGICAL_ADDRESS_MASK_2  0x300F /* 0x300E word */
+# define DP_CEC_LOGICAL_ADDRESS_8   (1 << 0)
+# define DP_CEC_LOGICAL_ADDRESS_9   (1 << 1)
+# define DP_CEC_LOGICAL_ADDRESS_10  (1 << 2)
+# define DP_CEC_LOGICAL_ADDRESS_11  (1 << 3)
+# define DP_CEC_LOGICAL_ADDRESS_12  (1 << 4)
+# define DP_CEC_LOGICAL_ADDRESS_13  (1 << 5)
+# define DP_CEC_LOGICAL_ADDRESS_14  (1 << 6)
+# define DP_CEC_LOGICAL_ADDRESS_15  (1 << 7)
+
+#define DP_CEC_RX_MESSAGE_BUFFER   0x3010
+#define DP_CEC_TX_MESSAGE_BUFFER   0x3020
+#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE0x0
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2] drm/cec: Add CEC over Aux register definitions

2017-04-20 Thread clinton . a . taylor 
From: Clint Taylor 

Adding DPCD register definitions from the DP 1.3 specification for CEC
over AUX support.

V2: Add DP_ prefix to all defines.

Reviewed-by: Jani Nikula 
Signed-off-by: Clint Taylor 
---
 include/drm/drm_dp_helper.h |   59 +++
 1 file changed, 59 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c0bd0d7..769b2a6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -603,6 +603,9 @@
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
 
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
+# define RX_GTC_MSTR_REQ_STATUS_CHANGE  (1 << 0)
+# define LOCK_ACQUISITION_REQUEST   (1 << 1)
+# define CEC_IRQ(1 << 2)
 
 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005   /* 1.2 */
 
@@ -636,6 +639,62 @@
 # define DP_VSC_EXT_CEA_SDP_SUPPORTED  (1 << 6)  /* DP 1.4 */
 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)  /* DP 1.4 */
 
+/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
+#define DP_CEC_TUNNELING_CAPABILITY0x3000
+# define DP_CEC_TUNNELING_CAPABLE   (1 << 0)
+# define DP_CEC_SNOOPING_CAPABLE(1 << 1)
+# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
+
+#define DP_CEC_TUNNELING_CONTROL   0x3001
+# define DP_CEC_TUNNELING_ENABLE(1 << 0)
+# define DP_CEC_SNOOPING_ENABLE (1 << 1)
+
+#define DP_CEC_RX_MESSAGE_INFO 0x3002
+# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
+# define DP_CEC_RX_MESSAGE_LEN_SHIFT0
+# define DP_CEC_RX_MESSAGE_HPD_STATE(1 << 4)
+# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
+# define DP_CEC_RX_MESSAGE_ACKED(1 << 6)
+# define DP_CEC_RX_MESSAGE_ENDED(1 << 7)
+
+#define DP_CEC_TX_MESSAGE_INFO 0x3003
+# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
+# define DP_CEC_TX_MESSAGE_LEN_SHIFT0
+# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
+# define DP_CEC_TX_RETRY_COUNT_SHIFT4
+# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
+
+#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
+# define DP_CEC_RX_MESSAGE_INFO_VALID   (1 << 0)
+# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
+# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
+# define DP_CEC_TX_LINE_ERROR   (1 << 5)
+# define DP_CEC_TX_ADDRESS_NACK_ERROR   (1 << 6)
+# define DP_CEC_TX_DATA_NACK_ERROR  (1 << 7)
+
+#define DP_CEC_LOGICAL_ADDRESS_MASK0x300E /* 0x300F word */
+# define DP_CEC_LOGICAL_ADDRESS_0   (1 << 0)
+# define DP_CEC_LOGICAL_ADDRESS_1   (1 << 1)
+# define DP_CEC_LOGICAL_ADDRESS_2   (1 << 2)
+# define DP_CEC_LOGICAL_ADDRESS_3   (1 << 3)
+# define DP_CEC_LOGICAL_ADDRESS_4   (1 << 4)
+# define DP_CEC_LOGICAL_ADDRESS_5   (1 << 5)
+# define DP_CEC_LOGICAL_ADDRESS_6   (1 << 6)
+# define DP_CEC_LOGICAL_ADDRESS_7   (1 << 7)
+#define DP_CEC_LOGICAL_ADDRESS_MASK_2  0x300F /* 0x300E word */
+# define DP_CEC_LOGICAL_ADDRESS_8   (1 << 0)
+# define DP_CEC_LOGICAL_ADDRESS_9   (1 << 1)
+# define DP_CEC_LOGICAL_ADDRESS_10  (1 << 2)
+# define DP_CEC_LOGICAL_ADDRESS_11  (1 << 3)
+# define DP_CEC_LOGICAL_ADDRESS_12  (1 << 4)
+# define DP_CEC_LOGICAL_ADDRESS_13  (1 << 5)
+# define DP_CEC_LOGICAL_ADDRESS_14  (1 << 6)
+# define DP_CEC_LOGICAL_ADDRESS_15  (1 << 7)
+
+#define DP_CEC_RX_MESSAGE_BUFFER   0x3010
+#define DP_CEC_TX_MESSAGE_BUFFER   0x3020
+#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE0x0
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH] drm/cec: Add CEC over Aux register definitions

2017-04-19 Thread clinton . a . taylor 
From: Clint Taylor 

Adding DPCD register definitions from the DP 1.3 specification for CEC
over AUX support.

Signed-off-by: Clint Taylor 
---
 include/drm/drm_dp_helper.h |   59 +++
 1 file changed, 59 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c0bd0d7..d188aff 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -603,6 +603,9 @@
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
 
 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
+# define RX_GTC_MSTR_REQ_STATUS_CHANGE  (1 << 0)
+# define LOCK_ACQUISITION_REQUEST   (1 << 1)
+# define CEC_IRQ(1 << 2)
 
 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005   /* 1.2 */
 
@@ -636,6 +639,62 @@
 # define DP_VSC_EXT_CEA_SDP_SUPPORTED  (1 << 6)  /* DP 1.4 */
 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)  /* DP 1.4 */
 
+/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
+#define CEC_TUNNELING_CAPABILITY0x3000
+# define CEC_TUNNELING_CAPABLE   (1 << 0)
+# define CEC_SNOOPING_CAPABLE(1 << 1)
+# define CEC_MULTIPLE_LA_CAPABLE (1 << 2)
+
+#define CEC_TUNNELING_CONTROL   0x3001
+# define CEC_TUNNELING_ENABLE(1 << 0)
+# define CEC_SNOOPING_ENABLE (1 << 1)
+
+#define CEC_RX_MESSAGE_INFO 0x3002
+# define CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
+# define CEC_RX_MESSAGE_LEN_SHIFT0
+# define CEC_RX_MESSAGE_HPD_STATE(1 << 4)
+# define CEC_RX_MESSAGE_HPD_LOST (1 << 5)
+# define CEC_RX_MESSAGE_ACKED(1 << 6)
+# define CEC_RX_MESSAGE_ENDED(1 << 7)
+
+#define CEC_TX_MESSAGE_INFO 0x3003
+# define CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
+# define CEC_TX_MESSAGE_LEN_SHIFT0
+# define CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
+# define CEC_TX_RETRY_COUNT_SHIFT4
+# define CEC_TX_MESSAGE_SEND (1 << 7)
+
+#define CEC_TUNNELING_IRQ_FLAGS 0x3004
+# define CEC_RX_MESSAGE_INFO_VALID   (1 << 0)
+# define CEC_RX_MESSAGE_OVERFLOW (1 << 1)
+# define CEC_TX_MESSAGE_SENT (1 << 4)
+# define CEC_TX_LINE_ERROR   (1 << 5)
+# define CEC_TX_ADDRESS_NACK_ERROR   (1 << 6)
+# define CEC_TX_DATA_NACK_ERROR  (1 << 7)
+
+#define CEC_LOGICAL_ADDRESS_MASK0x300E /* 0x300F word */
+# define CEC_LOGICAL_ADDRESS_0   (1 << 0)
+# define CEC_LOGICAL_ADDRESS_1   (1 << 1)
+# define CEC_LOGICAL_ADDRESS_2   (1 << 2)
+# define CEC_LOGICAL_ADDRESS_3   (1 << 3)
+# define CEC_LOGICAL_ADDRESS_4   (1 << 4)
+# define CEC_LOGICAL_ADDRESS_5   (1 << 5)
+# define CEC_LOGICAL_ADDRESS_6   (1 << 6)
+# define CEC_LOGICAL_ADDRESS_7   (1 << 7)
+#define CEC_LOGICAL_ADDRESS_MASK_2  0x300F /* 0x300E word */
+# define CEC_LOGICAL_ADDRESS_8   (1 << 0)
+# define CEC_LOGICAL_ADDRESS_9   (1 << 1)
+# define CEC_LOGICAL_ADDRESS_10  (1 << 2)
+# define CEC_LOGICAL_ADDRESS_11  (1 << 3)
+# define CEC_LOGICAL_ADDRESS_12  (1 << 4)
+# define CEC_LOGICAL_ADDRESS_13  (1 << 5)
+# define CEC_LOGICAL_ADDRESS_14  (1 << 6)
+# define CEC_LOGICAL_ADDRESS_15  (1 << 7)
+
+#define CEC_RX_MESSAGE_BUFFER   0x3010
+#define CEC_TX_MESSAGE_BUFFER   0x3020
+#define CEC_MESSAGE_BUFFER_LENGTH 0x10
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE0x0
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v6 1/2] drm_fourcc: Add new P010, P016 video format

2017-02-28 Thread clinton . a . taylor 
From: Clint Taylor 

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.

P016 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
V6: reversed Cb/Cr order in comments

Cc: Daniel Stone 
Cc: Ville Syrjälä 

Signed-off-by: Randy Li 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_fourcc.c  |3 +++
 include/uapi/drm/drm_fourcc.h |   21 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..3e0fd58 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,  
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+   { .format = DRM_FORMAT_P010,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P012,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P016,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
 
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..762646d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,27 @@
 #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /* 
non-subsampled Cb:Cr plane */
 
 /*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2 
subsampled Cr:Cb plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2 
subsampled Cr:Cb plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
+ */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2 
subsampled Cr:Cb plane 16 bits per channel */
+
+/*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
  * index 1: Cb plane, [7:0] Cb
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v5 1/2] drm_fourcc: Add new P010, P016 video format

2017-02-27 Thread clinton . a . taylor 
From: Clint Taylor 

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.

P016 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format

Cc: Daniel Stone 
Cc: Ville Syrjälä 

Signed-off-by: Randy Li 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_fourcc.c  |4 
 include/uapi/drm/drm_fourcc.h |   21 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,  
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+   /* FIXME a pixel in Y for P010 is 10 bits */
+   { .format = DRM_FORMAT_P010,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P012,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P016,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
 
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..306f979 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,27 @@
 #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /* 
non-subsampled Cb:Cr plane */
 
 /*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2 
subsampled Cb:Cr plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2 
subsampled Cb:Cr plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
+ */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2 
subsampled Cb:Cr plane 16 bits per channel */
+
+/*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
  * index 1: Cb plane, [7:0] Cb
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v4 1/2] drm_fourcc: Add new P010, P016 video format

2017-02-27 Thread clinton . a . taylor 
From: Clint Taylor 

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.

P016 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010
V4: format definition refined per review

Cc: Daniel Stone 
Cc: Ville Syrjälä 

Signed-off-by: Randy Li 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_fourcc.c  |4 
 include/uapi/drm/drm_fourcc.h |   18 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,  
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+   /* FIXME a pixel in Y for P010 is 10 bits */
+   { .format = DRM_FORMAT_P010,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P012,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P016,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
 
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..ad94464 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,24 @@
 #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /* 
non-subsampled Cb:Cr plane */
 
 /*
+ * 2 plane YCbCr MSB aligned P0?? formats
+ * index 0 = Y plane, word array [15:6] P010
+ * or
+ * index 0 = Y plane, word array [15:4] P012
+ * or 
+ * index 0 = Y plane, word array [15:0] P016
+ *
+ * index 1 = Cb:Cr plane, [31:22] Cb [15:6] Cr little endian P010
+ * or
+ * index 1 = Cb:Cr plane, [31:20] Cb [15:4] Cr little endian P012
+ * or
+ * index 1 = Cb:Cr plane, [31:16] Cb [15:0] Cr little endian P016
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2 
subsampled Cb:Cr plane 10 bits per channel */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2 
subsampled Cb:Cr plane 12 bits per channel */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2 
subsampled Cb:Cr plane 16 bits per channel */
+
+/*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
  * index 1: Cb plane, [7:0] Cb
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v3 1/2] drm_fourcc: Add new P010, P016 video format

2017-02-23 Thread clinton . a . taylor 
From: Clint Taylor 

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format. Rockchip's vop support this video format(little
endian only) as the input video format.

P012 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010

Cc: Daniel Stone 
Cc: Ville Syrjälä 

Signed-off-by: Randy Li 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/drm_fourcc.c  |4 
 include/uapi/drm/drm_fourcc.h |   14 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..5494764 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -165,6 +165,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,  
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,  
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+   /* FIXME a pixel in Y for P010 is 10 bits */
+   { .format = DRM_FORMAT_P010,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P012,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+   { .format = DRM_FORMAT_P016,.depth = 0,  
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
 
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..788dc36 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -128,6 +128,20 @@
 #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /* 
non-subsampled Cb:Cr plane */
 
 /*
+ * 2 plane YCbCr MSB aligned P0?? formats 
+ * index 0 = Y plane, word array [15:6] P010 
+ * index 0 = Y plane, word array [15:4] P012 
+ * index 0 = Y plane, word array [15:0] P016 
+ *  
+ * index 1 = U [31:22], V [15:6] P010
+ * index 1 = U [31:20], V [15:4] P012 
+ * index 1 = U [31:16], V [15:0] P016  
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2 
subsampled Cr:Cb plane 10 bits per channel */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2 
subsampled Cr:Cb plane 12 bits per channel */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2 
subsampled Cr:Cb plane 16 bits per channel */
+
+/*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
  * index 1: Cb plane, [7:0] Cb
-- 
1.7.9.5

___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel