[PATCH] drm/radeon: ERROR: "foo* bar" should be "foo *bar"
Fix five occurrences of the checkpatch.pl error:
ERROR: "foo* bar" should be "foo *bar"
ERROR: that open brace { should be on the previous line
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/radeon_audio.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_audio.c
b/drivers/gpu/drm/radeon/radeon_audio.c
index d6ccaf24ee0c..a010bc2c155c 100644
--- a/drivers/gpu/drm/radeon/radeon_audio.c
+++ b/drivers/gpu/drm/radeon/radeon_audio.c
@@ -35,15 +35,14 @@
void dce6_audio_enable(struct radeon_device *rdev, struct
r600_audio_pin *pin,
u8 enable_mask);
-struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev);
-struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev);
+struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
+struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode);
static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode);
-static const u32 pin_offsets[7] =
-{
+static const u32 pin_offsets[7] = {
(0x5e00 - 0x5e00),
(0x5e18 - 0x5e00),
(0x5e30 - 0x5e00),
@@ -359,7 +358,7 @@ static void radeon_audio_write_latency_fields(struct
drm_encoder *encoder,
radeon_encoder->audio->write_latency_fields(encoder, connector,
mode);
}
-struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder
*encoder)
+struct r600_audio_pin *radeon_audio_get_pin(struct drm_encoder
*encoder)
{
struct radeon_device *rdev = encoder->dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -526,7 +525,7 @@ static void radeon_audio_calc_cts(unsigned int
clock, int *CTS, int *N, int freq
*N, *CTS, freq);
}
-static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int
clock)
+static const struct radeon_hdmi_acr *radeon_audio_acr(unsigned int
clock)
{
static struct radeon_hdmi_acr res;
u8 i;
[PATCH] drm/radeon: ERROR: open brace '{' following function definitions go on the next line
Fix four occurrences of the checkpatch.pl error:
ERROR: open brace '{' following function definitions go on the next line
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 6f93f54bf651..2a3c3f8b02e2 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -61,19 +61,23 @@ struct atpx_mux {
u16 mux;
} __packed;
-bool radeon_has_atpx(void) {
+bool radeon_has_atpx(void)
+{
return radeon_atpx_priv.atpx_detected;
}
-bool radeon_has_atpx_dgpu_power_cntl(void) {
+bool radeon_has_atpx_dgpu_power_cntl(void)
+{
return radeon_atpx_priv.atpx.functions.power_cntl;
}
-bool radeon_is_atpx_hybrid(void) {
+bool radeon_is_atpx_hybrid(void)
+{
return radeon_atpx_priv.atpx.is_hybrid;
}
-bool radeon_atpx_dgpu_req_power_for_displays(void) {
+bool radeon_atpx_dgpu_req_power_for_displays(void)
+{
return radeon_atpx_priv.atpx.dgpu_req_power_for_displays;
}
[PATCH] drm/radeon: ERROR: open brace '{' following struct go on the same line
Fix seventeen occurrences of the checkpatch.pl error:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/smu7_discrete.h | 51 +-
1 file changed, 17 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/radeon/smu7_discrete.h
b/drivers/gpu/drm/radeon/smu7_discrete.h
index 0b0b404ff091..1f63cbbd6515 100644
--- a/drivers/gpu/drm/radeon/smu7_discrete.h
+++ b/drivers/gpu/drm/radeon/smu7_discrete.h
@@ -35,8 +35,7 @@
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
-struct SMU7_SoftRegisters
-{
+struct SMU7_SoftRegisters {
uint32_tRefClockFrequency;
uint32_tPmTimerP;
uint32_tFeatureEnables;
@@ -89,8 +88,7 @@ struct SMU7_SoftRegisters
typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
-struct SMU7_Discrete_VoltageLevel
-{
+struct SMU7_Discrete_VoltageLevel {
uint16_tVoltage;
uint16_tStdVoltageHiSidd;
uint16_tStdVoltageLoSidd;
@@ -100,8 +98,7 @@ struct SMU7_Discrete_VoltageLevel
typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
-struct SMU7_Discrete_GraphicsLevel
-{
+struct SMU7_Discrete_GraphicsLevel {
uint32_tFlags;
uint32_tMinVddc;
uint32_tMinVddcPhases;
@@ -131,8 +128,7 @@ struct SMU7_Discrete_GraphicsLevel
typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
-struct SMU7_Discrete_ACPILevel
-{
+struct SMU7_Discrete_ACPILevel {
uint32_tFlags;
uint32_tMinVddc;
uint32_tMinVddcPhases;
@@ -153,8 +149,7 @@ struct SMU7_Discrete_ACPILevel
typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
-struct SMU7_Discrete_Ulv
-{
+struct SMU7_Discrete_Ulv {
uint32_tCcPwrDynRm;
uint32_tCcPwrDynRm1;
uint16_tVddcOffset;
@@ -165,8 +160,7 @@ struct SMU7_Discrete_Ulv
typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
-struct SMU7_Discrete_MemoryLevel
-{
+struct SMU7_Discrete_MemoryLevel {
uint32_tMinVddc;
uint32_tMinVddcPhases;
uint32_tMinVddci;
@@ -206,8 +200,7 @@ struct SMU7_Discrete_MemoryLevel
typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
-struct SMU7_Discrete_LinkLevel
-{
+struct SMU7_Discrete_LinkLevel {
uint8_t PcieGenSpeed;
uint8_t PcieLaneCount;
uint8_t EnabledForActivity;
@@ -220,8 +213,7 @@ struct SMU7_Discrete_LinkLevel
typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
-struct SMU7_Discrete_MCArbDramTimingTableEntry
-{
+struct SMU7_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
@@ -230,15 +222,13 @@ struct SMU7_Discrete_MCArbDramTimingTableEntry
typedef struct SMU7_Discrete_MCArbDramTimingTableEntry
SMU7_Discrete_MCArbDramTimingTableEntry;
-struct SMU7_Discrete_MCArbDramTimingTable
-{
+struct SMU7_Discrete_MCArbDramTimingTable {
SMU7_Discrete_MCArbDramTimingTableEntry
entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU7_Discrete_MCArbDramTimingTable
SMU7_Discrete_MCArbDramTimingTable;
-struct SMU7_Discrete_UvdLevel
-{
+struct SMU7_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint16_t MinVddc;
@@ -250,8 +240,7 @@ struct SMU7_Discrete_UvdLevel
typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
-struct SMU7_Discrete_ExtClkLevel
-{
+struct SMU7_Discrete_ExtClkLevel {
uint32_t Frequency;
uint16_t MinVoltage;
uint8_t MinPhases;
@@ -260,8 +249,7 @@ struct SMU7_Discrete_ExtClkLevel
typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
-struct SMU7_Discrete_StateInfo
-{
+struct SMU7_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
@@ -285,8 +273,7 @@ struct SMU7_Discrete_StateInfo
typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
-struct SMU7_Discrete_DpmTable
-{
+struct SMU7_Discrete_DpmTable {
SMU7_PIDController GraphicsPIDController;
SMU7_PIDController MemoryPIDController;
SMU7_PIDController LinkPIDController;
@@ -406,23 +393,20 @@ typedef struct SMU7_Discrete_DpmTable
SMU7_Discrete_DpmTable;
#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT
SMU7_MAX_LEVELS_MEMORY
-struct SMU7_Discrete_MCRegisterAddress
-{
+struct SMU7_Discrete_MCRegisterAddress {
uint16_t s0;
uint16_t s1;
};
typedef struct SMU7_Discrete_MCRegisterAddress
SMU7_Discrete_MCRegisterAddress;
-struct SMU7_Discrete_MCRegisterSet
-{
+struct SMU7_Discrete_MCRegisterSet {
uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
-struct SMU7_Discrete_MCRegisters
-{
+struct SMU7_Discrete_MCRegisters {
uint8_t last;
uint8_t
[PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
Fix eight occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that close parenthesis ')'
ERROR: spaces required around that '?' (ctx:VxW)
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/sumo_dpm.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index f74f381af05f..8af793c89fd1 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -33,8 +33,7 @@
#define SUMO_MINIMUM_ENGINE_CLOCK 800
#define BOOST_DPM_LEVEL 7
-static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {
SUMO_UTC_DFLT_00,
SUMO_UTC_DFLT_01,
SUMO_UTC_DFLT_02,
@@ -52,8 +51,7 @@ static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
SUMO_UTC_DFLT_14,
};
-static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {
SUMO_DTC_DFLT_00,
SUMO_DTC_DFLT_01,
SUMO_DTC_DFLT_02,
@@ -109,11 +107,11 @@ static void sumo_mg_clockgating_enable(struct
radeon_device *rdev, bool enable)
local1 = RREG32(CG_CGTT_LOCAL_1);
if (enable) {
-WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 &
~CGCG_CGTT_LOCAL0_MASK) );
-WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 &
~CGCG_CGTT_LOCAL1_MASK) );
+WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 &
~CGCG_CGTT_LOCAL0_MASK));
+WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 &
~CGCG_CGTT_LOCAL1_MASK));
} else {
-WREG32(CG_CGTT_LOCAL_0, (0x & CGCG_CGTT_LOCAL0_MASK) |
(local0 & ~CGCG_CGTT_LOCAL0_MASK) );
-WREG32(CG_CGTT_LOCAL_1, (0xCFFF & CGCG_CGTT_LOCAL1_MASK) |
(local1 & ~CGCG_CGTT_LOCAL1_MASK) );
+WREG32(CG_CGTT_LOCAL_0, (0x & CGCG_CGTT_LOCAL0_MASK) |
(local0 & ~CGCG_CGTT_LOCAL0_MASK));
+WREG32(CG_CGTT_LOCAL_1, (0xCFFF & CGCG_CGTT_LOCAL1_MASK) |
(local1 & ~CGCG_CGTT_LOCAL1_MASK));
}
}
@@ -702,9 +700,9 @@ static void sumo_post_notify_alt_vddnb_change(struct
radeon_device *rdev,
u32 nbps1_new = 0;
if (old_ps != NULL)
-nbps1_old = (old_ps->flags &
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+nbps1_old = (old_ps->flags &
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
-nbps1_new = (new_ps->flags &
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+nbps1_new = (new_ps->flags &
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
if (nbps1_old == 0 && nbps1_new == 1)
sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
[PATCH] drm/radeon: ERROR: "(foo*)" should be "(foo *)"
Fix one occurrence of the checkpatch.pl error: ERROR: "(foo*)" should be "(foo *)" Signed-off-by: Jie Shi --- drivers/gpu/drm/radeon/uvd_v1_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c index 58557c2263a7..5684639d20a6 100644 --- a/drivers/gpu/drm/radeon/uvd_v1_0.c +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c @@ -142,7 +142,7 @@ int uvd_v1_0_resume(struct radeon_device *rdev) addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); -WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); +WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr)); return 0; }
[PATCH] drm/radeon: ERROR: spaces required around that '+=' (ctx:VxV)
Fix two occurrences of the checkpatch.pl error:
ERROR: spaces required around that '+=' (ctx:VxV)
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/r100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r100.c
b/drivers/gpu/drm/radeon/r100.c
index affa9e0309b2..2f0470f927f1 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1327,7 +1327,7 @@ int r100_packet3_load_vbpntr(struct
radeon_cs_parser *p,
return -EINVAL;
}
track->num_arrays = c;
-for (i = 0; i < (c - 1); i+=2, idx+=3) {
+for (i = 0; i < (c - 1); i += 2, idx += 3) {
r = radeon_cs_packet_next_reloc(p, , 0);
if (r) {
DRM_ERROR("No reloc for packet3 %d\n",
[PATCH] drm/radeon: ERROR: space prohibited before that ', ' (ctx:WxV)
Fix two occurrences of the checkpatch.pl error:
ERROR: space prohibited before that ',' (ctx:WxV)
ERROR: space required after that ',' (ctx:WxV)
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/atom-bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/atom-bits.h
b/drivers/gpu/drm/radeon/atom-bits.h
index e8fae5c77514..2bfd6d0ff050 100644
--- a/drivers/gpu/drm/radeon/atom-bits.h
+++ b/drivers/gpu/drm/radeon/atom-bits.h
@@ -33,7 +33,7 @@ static inline uint8_t get_u8(void *bios, int ptr)
#define CU8(ptr) get_u8(ctx->bios, (ptr))
static inline uint16_t get_u16(void *bios, int ptr)
{
-return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
+return get_u8(bios, ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
}
#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
#define CU16(ptr) get_u16(ctx->bios, (ptr))
[PATCH] drm/radeon/dpm: ERROR: open brace '{' following enum go on the same line
Fix four occurrences of the checkpatch.pl error:
ERROR: open brace '{' following enum go on the same line
Signed-off-by: Jie Shi
---
drivers/gpu/drm/radeon/ni_dpm.h | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ni_dpm.h
b/drivers/gpu/drm/radeon/ni_dpm.h
index 74e301936906..4e3e7303e035 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.h
+++ b/drivers/gpu/drm/radeon/ni_dpm.h
@@ -59,8 +59,7 @@ struct ni_mc_reg_table {
#define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 2
-enum ni_dc_cac_level
-{
+enum ni_dc_cac_level {
NISLANDS_DCCAC_LEVEL_0 = 0,
NISLANDS_DCCAC_LEVEL_1,
NISLANDS_DCCAC_LEVEL_2,
@@ -72,8 +71,7 @@ enum ni_dc_cac_level
NISLANDS_DCCAC_MAX_LEVELS
};
-struct ni_leakage_coeffients
-{
+struct ni_leakage_coeffients {
u32 at;
u32 bt;
u32 av;
@@ -83,8 +81,7 @@ struct ni_leakage_coeffients
u32 t_ref;
};
-struct ni_cac_data
-{
+struct ni_cac_data {
struct ni_leakage_coeffients leakage_coefficients;
u32 i_leakage;
s32 leakage_minimum_temperature;
@@ -100,8 +97,7 @@ struct ni_cac_data
u8 lts_truncate_n;
};
-struct ni_cac_weights
-{
+struct ni_cac_weights {
u32 weight_tcp_sig0;
u32 weight_tcp_sig1;
u32 weight_ta_sig;
