Re: [DPU PATCH v3 05/12] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address

2018-06-19 Thread ryadav 

Hi Sean,
Looks like this patch is missing on for-next branch.
Can you please help pull it in?

Thanks,
Rajesh

On 2018-05-14 20:56, Rajesh Yadav wrote:

The dpu sub-block offsets were defined wrt mdss base address
instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog
offsets for all dpu sub blocks wrt dpu base address.

Changes in v3:
- none

Changes in v2:
- none

Signed-off-by: Rajesh Yadav 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 
+++

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c5b370f..2fd3254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -80,7 +80,7 @@
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
-   .base = 0x1000, .len = 0x45C,
+   .base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
.has_dest_scaler = true,
@@ -111,27 +111,27 @@
 static struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
-   .base = 0x2000, .len = 0xE4,
+   .base = 0x1000, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_1", .id = CTL_1,
-   .base = 0x2200, .len = 0xE4,
+   .base = 0x1200, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_2", .id = CTL_2,
-   .base = 0x2400, .len = 0xE4,
+   .base = 0x1400, .len = 0xE4,
.features = 0
},
{
.name = "ctl_3", .id = CTL_3,
-   .base = 0x2600, .len = 0xE4,
+   .base = 0x1600, .len = 0xE4,
.features = 0
},
{
.name = "ctl_4", .id = CTL_4,
-   .base = 0x2800, .len = 0xE4,
+   .base = 0x1800, .len = 0xE4,
.features = 0
},
 };
@@ -211,21 +211,21 @@
}

 static struct dpu_sspp_cfg sdm845_sspp[] = {
-   SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+   SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
-   SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+   SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
-   SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+   SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
-   SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+   SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
-   SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+   SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
-   SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+   SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
-   SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+   SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
-   SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+   SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
 };

@@ -252,17 +252,17 @@
.lm_pair_mask = (1 << _lmpair) \
}
 static struct dpu_lm_cfg sdm845_lm[] = {
-   LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+   LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
DS_0, PINGPONG_0, LM_1),
-   LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+   LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
DS_1, PINGPONG_1, LM_0),
-   LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+   LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
DS_MAX, PINGPONG_2, LM_5),
LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
-   LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+   LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
DS_MAX, PINGPONG_3, LM_2),
 };

@@ -270,7 +270,7 @@
  * DSPP sub blocks config
  */
 static struct dpu_dspp_top_cfg sdm845_dspp_top = {
-   .name = "dspp_top", .base = 0x1300, .len = 0xc
+   .name = "dspp_top", .base = 0x300, .len = 0xc
 };

 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
@@ -304,10 +304,10 @@
}

 static struct dpu_dspp_cfg sdm845_dspp[] = {
-   DSPP_BLK("dspp_0", DSPP_0, 0x55000),
-   DSPP_BLK("dspp_1", DSPP_1, 0x57000),
-   DSPP_BLK("dspp_2", DSPP_2, 0x59000),
-   DSPP_BLK("dspp_3", DSPP_3, 0x5b000),
+   DSPP_BLK("dspp_0", DSPP_0, 0x54000),
+   DSPP_BLK("dspp_1", DSPP_1, 0x56000),
+

[DPU PATCH v3 05/12] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address

2018-05-14 Thread Rajesh Yadav 
The dpu sub-block offsets were defined wrt mdss base address
instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog
offsets for all dpu sub blocks wrt dpu base address.

Changes in v3:
- none

Changes in v2:
- none

Signed-off-by: Rajesh Yadav 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c5b370f..2fd3254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -80,7 +80,7 @@
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
-   .base = 0x1000, .len = 0x45C,
+   .base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
.has_dest_scaler = true,
@@ -111,27 +111,27 @@
 static struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
-   .base = 0x2000, .len = 0xE4,
+   .base = 0x1000, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_1", .id = CTL_1,
-   .base = 0x2200, .len = 0xE4,
+   .base = 0x1200, .len = 0xE4,
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
},
{
.name = "ctl_2", .id = CTL_2,
-   .base = 0x2400, .len = 0xE4,
+   .base = 0x1400, .len = 0xE4,
.features = 0
},
{
.name = "ctl_3", .id = CTL_3,
-   .base = 0x2600, .len = 0xE4,
+   .base = 0x1600, .len = 0xE4,
.features = 0
},
{
.name = "ctl_4", .id = CTL_4,
-   .base = 0x2800, .len = 0xE4,
+   .base = 0x1800, .len = 0xE4,
.features = 0
},
 };
@@ -211,21 +211,21 @@
}
 
 static struct dpu_sspp_cfg sdm845_sspp[] = {
-   SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+   SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
-   SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+   SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
-   SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+   SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
-   SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+   SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
-   SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+   SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
-   SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+   SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
-   SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+   SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
-   SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+   SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
 };
 
@@ -252,17 +252,17 @@
.lm_pair_mask = (1 << _lmpair) \
}
 static struct dpu_lm_cfg sdm845_lm[] = {
-   LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+   LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
DS_0, PINGPONG_0, LM_1),
-   LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+   LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
DS_1, PINGPONG_1, LM_0),
-   LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+   LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
DS_MAX, PINGPONG_2, LM_5),
LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
DS_MAX, PINGPONG_MAX, 0),
-   LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+   LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
DS_MAX, PINGPONG_3, LM_2),
 };
 
@@ -270,7 +270,7 @@
  * DSPP sub blocks config
  */
 static struct dpu_dspp_top_cfg sdm845_dspp_top = {
-   .name = "dspp_top", .base = 0x1300, .len = 0xc
+   .name = "dspp_top", .base = 0x300, .len = 0xc
 };
 
 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
@@ -304,10 +304,10 @@
}
 
 static struct dpu_dspp_cfg sdm845_dspp[] = {
-   DSPP_BLK("dspp_0", DSPP_0, 0x55000),
-   DSPP_BLK("dspp_1", DSPP_1, 0x57000),
-   DSPP_BLK("dspp_2", DSPP_2, 0x59000),
-   DSPP_BLK("dspp_3", DSPP_3, 0x5b000),
+   DSPP_BLK("dspp_0", DSPP_0, 0x54000),
+   DSPP_BLK("dspp_1", DSPP_1, 0x56000),
+   DSPP_BLK("dspp_2", DSPP_2, 0x58000),
+   DSPP_BLK("dspp_3", DSPP_3, 0x5a000),
 };