Re: [PATCH] drm/hisilicon: Added three new resolutions and changed the alignment to 128 Bytes

2019-12-31 Thread tiantao (H) 


Hi Daniel:

Thanks you very much ,I will follow your suggestion to split this to 
three patches.


Best
在 2019/12/30 18:23, Daniel Stone 写道:

Hi Tian,

On Sat, 28 Dec 2019 at 01:14, Tian Tao  wrote:

@@ -118,11 +119,9 @@ static void hibmc_plane_atomic_update(struct drm_plane 
*plane,
 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);

 reg = state->fb->width * (state->fb->format->cpp[0]);
-   /* now line_pad is 16 */
-   reg = PADDING(16, reg);

 line_l = state->fb->width * state->fb->format->cpp[0];
-   line_l = PADDING(16, line_l);
+   line_l = PADDING(128, line_l);


The 'line length' here is the 'stride' field of the FB. Stride is set
by userspace when allocating the buffer, and the kernel must not
attempt to guess what userspace set.

You should use state->fb->strides[0] directly here, and in your
atomic_check() function, make sure that the framebuffer stride is
correctly aligned.

Please split this into a separate change. Your commit has three
changes in it, which should all be separate commits:
   * enforce 128-byte stride alignment (is this a hardware limit?)
   * get the BO from drm_fb rather than hibmc_fb (can hibmc_fb->obj
just be removed now?)
   * add new clock/resolution configurations

Cheers,
Daniel

.



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Re: [PATCH] drm/hisilicon: Added three new resolutions and changed the alignment to 128 Bytes

2019-12-30 Thread Daniel Stone 
Hi Tian,

On Sat, 28 Dec 2019 at 01:14, Tian Tao  wrote:
> @@ -118,11 +119,9 @@ static void hibmc_plane_atomic_update(struct drm_plane 
> *plane,
> writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
>
> reg = state->fb->width * (state->fb->format->cpp[0]);
> -   /* now line_pad is 16 */
> -   reg = PADDING(16, reg);
>
> line_l = state->fb->width * state->fb->format->cpp[0];
> -   line_l = PADDING(16, line_l);
> +   line_l = PADDING(128, line_l);

The 'line length' here is the 'stride' field of the FB. Stride is set
by userspace when allocating the buffer, and the kernel must not
attempt to guess what userspace set.

You should use state->fb->strides[0] directly here, and in your
atomic_check() function, make sure that the framebuffer stride is
correctly aligned.

Please split this into a separate change. Your commit has three
changes in it, which should all be separate commits:
  * enforce 128-byte stride alignment (is this a hardware limit?)
  * get the BO from drm_fb rather than hibmc_fb (can hibmc_fb->obj
just be removed now?)
  * add new clock/resolution configurations

Cheers,
Daniel
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[PATCH] drm/hisilicon: Added three new resolutions and changed the alignment to 128 Bytes

2019-12-28 Thread Tian Tao 
Add the three new resolution 1440x900 and 1600x900, 640x480 for hibmc
and Set the FB Offset of the display hardware to 128 Byte alignment

Signed-off-by: Tian Tao 
Signed-off-by: Gong junjie 
---
 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c   | 11 +--
 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h |  2 ++
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
index f1ce6cb..69389b0 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
@@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config {
 };
 
 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
+   {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},
{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
@@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] 
= {
{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
+   {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},
+   {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
@@ -102,14 +105,12 @@ static void hibmc_plane_atomic_update(struct drm_plane 
*plane,
s64 gpu_addr = 0;
unsigned int line_l;
struct hibmc_drm_private *priv = plane->dev->dev_private;
-   struct hibmc_framebuffer *hibmc_fb;
struct drm_gem_vram_object *gbo;
 
if (!state->fb)
return;
 
-   hibmc_fb = to_hibmc_framebuffer(state->fb);
-   gbo = drm_gem_vram_of_gem(hibmc_fb->obj);
+   gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
 
gpu_addr = drm_gem_vram_offset(gbo);
if (WARN_ON_ONCE(gpu_addr < 0))
@@ -118,11 +119,9 @@ static void hibmc_plane_atomic_update(struct drm_plane 
*plane,
writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
 
reg = state->fb->width * (state->fb->format->cpp[0]);
-   /* now line_pad is 16 */
-   reg = PADDING(16, reg);
 
line_l = state->fb->width * state->fb->format->cpp[0];
-   line_l = PADDING(16, line_l);
+   line_l = PADDING(128, line_l);
writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
   HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
   priv->mmio + HIBMC_CRT_FB_WIDTH);
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h 
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
index 9b7e859..17b30c3 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
@@ -179,6 +179,7 @@
 #define CRT_PLL1_HS_74MHZ  0x23941dc2
 #define CRT_PLL1_HS_80MHZ  0x23941001
 #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2
+#define CRT_PLL1_HS_106MHZ 0x237C1641
 #define CRT_PLL1_HS_108MHZ 0x23b41b01
 #define CRT_PLL1_HS_162MHZ 0x23480681
 #define CRT_PLL1_HS_148MHZ 0x23541dc2
@@ -191,6 +192,7 @@
 #define CRT_PLL2_HS_78MHZ  0x50E147AE
 #define CRT_PLL2_HS_74MHZ  0x602B6AE7
 #define CRT_PLL2_HS_80MHZ  0x7000
+#define CRT_PLL2_HS_106MHZ 0x0075c28f
 #define CRT_PLL2_HS_108MHZ 0x8000
 #define CRT_PLL2_HS_162MHZ 0xA000
 #define CRT_PLL2_HS_148MHZ 0xB0CD
-- 
2.7.4

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