subject:"\[PATCH\] drm\/i915\/guc\: Update w\/a 14019159160"

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

2024-03-14 Thread Matt Roper

On Tue, Mar 12, 2024 at 04:43:06PM -0700, John Harrison wrote:
> On 3/12/2024 09:24, Matt Roper wrote:
> > On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
> > > From: John Harrison 
> > > 
> > > An existing workaround has been extended in both platforms affected
> > > and implementation complexity.
> > > 
> > > Signed-off-by: John Harrison 
> > > ---
> > >   drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
> > >   3 files changed, 15 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
> > > b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> > > index bebf28e3c4794..3e7060e859794 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> > > @@ -105,7 +105,8 @@ enum {
> > >* Workaround keys:
> > >*/
> > >   enum {
> > > - GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> > > 0x9001,
> > > + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> > > 0x9001,   /* Wa_14019159160 */
> > > + GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
> > > 0x9006,   /* Wa_14019159160 */
> > >   };
> > >   #endif /* _ABI_GUC_KLVS_ABI_H */
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > index 0c67d674c94de..4c3dae98656af 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > @@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > >   /* Wa_16019325821 */
> > >   /* Wa_14019159160 */
> > > - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> > > + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> >  From what I can see, this workaround is also needed on Xe_LPG+ (12.74)
> Isn't that an Xe platform? Or is 12.74 just ARL?

12.74 / Xe_LPG+ is used in some ARL, which is being officially supported
by i915.


Matt

> 
> John.
> 
> > now.
> > 
> > 
> > Matt
> > 
> > > + IS_DG2(gt->i915))
> > >   flags |= GUC_WA_RCS_CCS_SWITCHOUT;
> > >   /*
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > index 5c9908b56616e..00fe3c21a9b1c 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > @@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
> > >   return PAGE_ALIGN(total_size);
> > >   }
> > > -/* Wa_14019159160 */
> > > -static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 
> > > remain)
> > > +static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, 
> > > u32 *remain, u32 klv_id)
> > >   {
> > >   u32 size;
> > >   u32 klv_entry[] = {
> > >   /* 16:16 key/length */
> > > - FIELD_PREP(GUC_KLV_0_KEY, 
> > > GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
> > > + FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
> > >   FIELD_PREP(GUC_KLV_0_LEN, 0),
> > >   /* 0 dwords data */
> > >   };
> > >   size = sizeof(klv_entry);
> > > - GEM_BUG_ON(remain < size);
> > > + GEM_BUG_ON(*remain < size);
> > > - iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);
> > > + iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
> > > - return size;
> > > + *offset += size;
> > > + *remain -= size;
> > >   }
> > >   static void guc_waklv_init(struct intel_guc *guc)
> > > @@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
> > >   remain = guc_ads_waklv_size(guc);
> > >   /* Wa_14019159160 */
> > > - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> > > - size = guc_waklv_ra_mode(guc, offset, remain);
> > > - offset += size;
> > > - remain -= size;
> > > + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
> > > IS_DG2(gt->i915)) {
> > > + guc_waklv_enable_simple(guc, &offset, &remain,
> > > + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
> > > + guc_waklv_enable_simple(guc, &offset, &remain,
> > > + 
> > > GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
> > >   }
> > >   size = guc_ads_waklv_size(guc) - remain;
> > > -- 
> > > 2.43.0
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

2024-03-12 Thread Lucas De Marchi


On Tue, Mar 12, 2024 at 04:43:06PM -0700, John Harrison wrote:

On 3/12/2024 09:24, Matt Roper wrote:

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 0c67d674c94de..4c3dae98656af 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
/* Wa_16019325821 */
/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

From what I can see, this workaround is also needed on Xe_LPG+ (12.74)

Isn't that an Xe platform? Or is 12.74 just ARL?


official xe platforms start with Xe2, with graphics version being 20

Lucas De Marchi

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

2024-03-12 Thread John Harrison


On 3/12/2024 09:24, Matt Roper wrote:

On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

An existing workaround has been extended in both platforms affected
and implementation complexity.

Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
  3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index bebf28e3c4794..3e7060e859794 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
@@ -105,7 +105,8 @@ enum {
   * Workaround keys:
   */
  enum {
-   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,   /* Wa_14019159160 */
+   GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
0x9006,   /* Wa_14019159160 */
  };
  
  #endif /* _ABI_GUC_KLVS_ABI_H */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 0c67d674c94de..4c3dae98656af 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
  
  	/* Wa_16019325821 */

/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

 From what I can see, this workaround is also needed on Xe_LPG+ (12.74)

Isn't that an Xe platform? Or is 12.74 just ARL?

John.


now.


Matt


+   IS_DG2(gt->i915))
flags |= GUC_WA_RCS_CCS_SWITCHOUT;
  
  	/*

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 5c9908b56616e..00fe3c21a9b1c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
return PAGE_ALIGN(total_size);
  }
  
-/* Wa_14019159160 */

-static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 remain)
+static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 
*remain, u32 klv_id)
  {
u32 size;
u32 klv_entry[] = {
/* 16:16 key/length */
-   FIELD_PREP(GUC_KLV_0_KEY, 
GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
+   FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
FIELD_PREP(GUC_KLV_0_LEN, 0),
/* 0 dwords data */
};
  
  	size = sizeof(klv_entry);

-   GEM_BUG_ON(remain < size);
+   GEM_BUG_ON(*remain < size);
  
-	iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);

+   iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
  
-	return size;

+   *offset += size;
+   *remain -= size;
  }
  
  static void guc_waklv_init(struct intel_guc *guc)

@@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
remain = guc_ads_waklv_size(guc);
  
  	/* Wa_14019159160 */

-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
-   size = guc_waklv_ra_mode(guc, offset, remain);
-   offset += size;
-   remain -= size;
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(gt->i915)) {
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   
GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
}
  
  	size = guc_ads_waklv_size(guc) - remain;

--
2.43.0

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

2024-03-12 Thread Matt Roper

On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison 
> 
> An existing workaround has been extended in both platforms affected
> and implementation complexity.
> 
> Signed-off-by: John Harrison 
> ---
>  drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
>  3 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> index bebf28e3c4794..3e7060e859794 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> @@ -105,7 +105,8 @@ enum {
>   * Workaround keys:
>   */
>  enum {
> - GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> 0x9001,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> 0x9001,   /* Wa_14019159160 */
> + GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
> 0x9006,   /* Wa_14019159160 */
>  };
>  
>  #endif /* _ABI_GUC_KLVS_ABI_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 0c67d674c94de..4c3dae98656af 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  
>   /* Wa_16019325821 */
>   /* Wa_14019159160 */
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

>From what I can see, this workaround is also needed on Xe_LPG+ (12.74)
now.


Matt

> + IS_DG2(gt->i915))
>   flags |= GUC_WA_RCS_CCS_SWITCHOUT;
>  
>   /*
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 5c9908b56616e..00fe3c21a9b1c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
>   return PAGE_ALIGN(total_size);
>  }
>  
> -/* Wa_14019159160 */
> -static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 remain)
> +static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 
> *remain, u32 klv_id)
>  {
>   u32 size;
>   u32 klv_entry[] = {
>   /* 16:16 key/length */
> - FIELD_PREP(GUC_KLV_0_KEY, 
> GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
> + FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
>   FIELD_PREP(GUC_KLV_0_LEN, 0),
>   /* 0 dwords data */
>   };
>  
>   size = sizeof(klv_entry);
> - GEM_BUG_ON(remain < size);
> + GEM_BUG_ON(*remain < size);
>  
> - iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);
> + iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
>  
> - return size;
> + *offset += size;
> + *remain -= size;
>  }
>  
>  static void guc_waklv_init(struct intel_guc *guc)
> @@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
>   remain = guc_ads_waklv_size(guc);
>  
>   /* Wa_14019159160 */
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> - size = guc_waklv_ra_mode(guc, offset, remain);
> - offset += size;
> - remain -= size;
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
> IS_DG2(gt->i915)) {
> + guc_waklv_enable_simple(guc, &offset, &remain,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
> + guc_waklv_enable_simple(guc, &offset, &remain,
> + 
> GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
>   }
>  
>   size = guc_ads_waklv_size(guc) - remain;
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH] drm/i915/guc: Update w/a 14019159160

2024-03-07 Thread John . C . Harrison

From: John Harrison 

An existing workaround has been extended in both platforms affected
and implementation complexity.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index bebf28e3c4794..3e7060e859794 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
@@ -105,7 +105,8 @@ enum {
  * Workaround keys:
  */
 enum {
-   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,   /* Wa_14019159160 */
+   GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
0x9006,   /* Wa_14019159160 */
 };
 
 #endif /* _ABI_GUC_KLVS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 0c67d674c94de..4c3dae98656af 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 
/* Wa_16019325821 */
/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
+   IS_DG2(gt->i915))
flags |= GUC_WA_RCS_CCS_SWITCHOUT;
 
/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 5c9908b56616e..00fe3c21a9b1c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
return PAGE_ALIGN(total_size);
 }
 
-/* Wa_14019159160 */
-static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 remain)
+static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 
*remain, u32 klv_id)
 {
u32 size;
u32 klv_entry[] = {
/* 16:16 key/length */
-   FIELD_PREP(GUC_KLV_0_KEY, 
GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
+   FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
FIELD_PREP(GUC_KLV_0_LEN, 0),
/* 0 dwords data */
};
 
size = sizeof(klv_entry);
-   GEM_BUG_ON(remain < size);
+   GEM_BUG_ON(*remain < size);
 
-   iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);
+   iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
 
-   return size;
+   *offset += size;
+   *remain -= size;
 }
 
 static void guc_waklv_init(struct intel_guc *guc)
@@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
remain = guc_ads_waklv_size(guc);
 
/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
-   size = guc_waklv_ra_mode(guc, offset, remain);
-   offset += size;
-   remain -= size;
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(gt->i915)) {
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   
GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
}
 
size = guc_ads_waklv_size(guc) - remain;
-- 
2.43.0

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

[PATCH] drm/i915/guc: Update w/a 14019159160

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