[PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread Boszormenyi Zoltan 
2012-06-09 16:57 keltez?ssel, j.glisse at gmail.com ?rta:
> From: Jerome Glisse
>
> Fix regresson since the introduction of command stream checking on
> evergreen (thread referenced below). Issue is cause by ddx allocating
> bo with formula width*height*bpp while programming the GPU command
> stream with ALIGN(height, 8). In some case (where page alignment does
> not hide the extra size bo should be according to height alignment)
> the kernel will reject the command stream.
>
> This patch reprogram the command stream to slice - 1 (slice is
> a derivative value from height) which avoid rejecting the command
> stream while keeping the value of command stream checking from a
> security point of view.
>
> This patch also fix wrong computation of layer size for 2D tiled
> surface. Which should fix issue when 2D color tiling is enabled.
> This dump the radeon KMS_DRIVER_MINOR so userspace can know if
> they are on a fixed kernel or not.
>
> https://lkml.org/lkml/2012/6/3/80
> https://bugs.freedesktop.org/show_bug.cgi?id=50892
> https://bugs.freedesktop.org/show_bug.cgi?id=50857
>
> !!! STABLE need a custom version of this patch for 3.4 !!!
>
> v2: actually bump the minor version and add comment about stable
> v3: do compute the height the ddx was trying to use
>
> Signed-off-by: Jerome Glisse
> ---
>   drivers/gpu/drm/radeon/evergreen_cs.c |   50 
> ++---
>   drivers/gpu/drm/radeon/radeon_drv.c   |3 +-
>   2 files changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
> b/drivers/gpu/drm/radeon/evergreen_cs.c
> index 4e7dd2b..29c43c6 100644
> --- a/drivers/gpu/drm/radeon/evergreen_cs.c
> +++ b/drivers/gpu/drm/radeon/evergreen_cs.c
> @@ -52,6 +52,7 @@ struct evergreen_cs_track {
>   u32 cb_color_view[12];
>   u32 cb_color_pitch[12];
>   u32 cb_color_slice[12];
> + u32 cb_color_slice_idx[12];
>   u32 cb_color_attrib[12];
>   u32 cb_color_cmask_slice[8];/* unused */
>   u32 cb_color_fmask_slice[8];/* unused */
> @@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct 
> evergreen_cs_track *track)
>   track->cb_color_info[i] = 0;
>   track->cb_color_view[i] = 0x;
>   track->cb_color_pitch[i] = 0;
> - track->cb_color_slice[i] = 0;
> + track->cb_color_slice[i] = 0xfff;
> + track->cb_color_slice_idx[i] = 0;
>   }
>   track->cb_target_mask = 0x;
>   track->cb_shader_mask = 0x;
>   track->cb_dirty = true;
>
> + track->db_depth_slice = 0x;
>   track->db_depth_view = 0xC000;
>   track->db_depth_size = 0x;
>   track->db_depth_control = 0x;
> @@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct 
> radeon_cs_parser *p,
>   {
>   struct evergreen_cs_track *track = p->track;
>   unsigned palign, halign, tileb, slice_pt;
> + unsigned mtile_pr, mtile_ps, mtileb;
>
>   tileb = 64 * surf->bpe * surf->nsamples;
> - palign = track->group_size / (8 * surf->bpe * surf->nsamples);
> - palign = MAX(8, palign);
>   slice_pt = 1;
>   if (tileb>  surf->tsplit) {
>   slice_pt = tileb / surf->tsplit;
> @@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct 
> radeon_cs_parser *p,
>   /* macro tile width&  height */
>   palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
>   halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
> - surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
> + mtileb = (palign / 8) * (halign / 8) * tileb;;
> + mtile_pr = surf->nbx / palign;
> + mtile_ps = (mtile_pr * surf->nby) / halign;
> + surf->layer_size = mtile_ps * mtileb * slice_pt;
>   surf->base_align = (palign / 8) * (halign / 8) * tileb;
>   surf->palign = palign;
>   surf->halign = halign;
> @@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct 
> radeon_cs_parser *p, unsigned i
>
>   offset += surf.layer_size * mslice;
>   if (offset>  radeon_bo_size(track->cb_color_bo[id])) {
> + /* old ddx are broken they allocate bo with w*h*bpp but
> +  * program slice with ALIGN(h, 8), catch this and patch
> +  * command stream.
> +  */
> + if (!surf.mode) {
> + volatile u32 *ib = p->ib.ptr;
> + unsigned long tmp, nby, bsize, size, min = 0;
> +
> + /* find the height the ddx wants */
> + if (surf.nby>  8) {
> + min = surf.nby - 8;
> + }
> + bsize = radeon_bo_size(track->cb_color_bo[id]);
> + tmp = track->cb_color_bo_offset[id]<<  8;
> + for (nby = surf.nby;

[PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread Jerome Glisse 
On Sat, Jun 9, 2012 at 12:15 PM, Boszormenyi Zoltan  wrote:
> 2012-06-09 16:57 keltez?ssel, j.glisse at gmail.com ?rta:
>>
>> From: Jerome Glisse
>>
>> Fix regresson since the introduction of command stream checking on
>> evergreen (thread referenced below). Issue is cause by ddx allocating
>> bo with formula width*height*bpp while programming the GPU command
>> stream with ALIGN(height, 8). In some case (where page alignment does
>> not hide the extra size bo should be according to height alignment)
>> the kernel will reject the command stream.
>>
>> This patch reprogram the command stream to slice - 1 (slice is
>> a derivative value from height) which avoid rejecting the command
>> stream while keeping the value of command stream checking from a
>> security point of view.
>>
>> This patch also fix wrong computation of layer size for 2D tiled
>> surface. Which should fix issue when 2D color tiling is enabled.
>> This dump the radeon KMS_DRIVER_MINOR so userspace can know if
>> they are on a fixed kernel or not.
>>
>> https://lkml.org/lkml/2012/6/3/80
>> https://bugs.freedesktop.org/show_bug.cgi?id=50892
>> https://bugs.freedesktop.org/show_bug.cgi?id=50857
>>
>> !!! STABLE need a custom version of this patch for 3.4 !!!
>>
>> v2: actually bump the minor version and add comment about stable
>> v3: do compute the height the ddx was trying to use
>>
>> Signed-off-by: Jerome Glisse
>> ---
>> ?drivers/gpu/drm/radeon/evergreen_cs.c | ? 50
>> ++---
>> ?drivers/gpu/drm/radeon/radeon_drv.c ? | ? ?3 +-
>> ?2 files changed, 48 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c
>> b/drivers/gpu/drm/radeon/evergreen_cs.c
>> index 4e7dd2b..29c43c6 100644
>> --- a/drivers/gpu/drm/radeon/evergreen_cs.c
>> +++ b/drivers/gpu/drm/radeon/evergreen_cs.c
>> @@ -52,6 +52,7 @@ struct evergreen_cs_track {
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_view[12];
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_pitch[12];
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_slice[12];
>> + ? ? ? u32 ? ? ? ? ? ? ? ? ? ? cb_color_slice_idx[12];
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_attrib[12];
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_cmask_slice[8];/* unused */
>> ? ? ? ?u32 ? ? ? ? ? ? ? ? ? ? cb_color_fmask_slice[8];/* unused */
>> @@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct
>> evergreen_cs_track *track)
>> ? ? ? ? ? ? ? ?track->cb_color_info[i] = 0;
>> ? ? ? ? ? ? ? ?track->cb_color_view[i] = 0x;
>> ? ? ? ? ? ? ? ?track->cb_color_pitch[i] = 0;
>> - ? ? ? ? ? ? ? track->cb_color_slice[i] = 0;
>> + ? ? ? ? ? ? ? track->cb_color_slice[i] = 0xfff;
>> + ? ? ? ? ? ? ? track->cb_color_slice_idx[i] = 0;
>> ? ? ? ?}
>> ? ? ? ?track->cb_target_mask = 0x;
>> ? ? ? ?track->cb_shader_mask = 0x;
>> ? ? ? ?track->cb_dirty = true;
>>
>> + ? ? ? track->db_depth_slice = 0x;
>> ? ? ? ?track->db_depth_view = 0xC000;
>> ? ? ? ?track->db_depth_size = 0x;
>> ? ? ? ?track->db_depth_control = 0x;
>> @@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct
>> radeon_cs_parser *p,
>> ?{
>> ? ? ? ?struct evergreen_cs_track *track = p->track;
>> ? ? ? ?unsigned palign, halign, tileb, slice_pt;
>> + ? ? ? unsigned mtile_pr, mtile_ps, mtileb;
>>
>> ? ? ? ?tileb = 64 * surf->bpe * surf->nsamples;
>> - ? ? ? palign = track->group_size / (8 * surf->bpe * surf->nsamples);
>> - ? ? ? palign = MAX(8, palign);
>> ? ? ? ?slice_pt = 1;
>> ? ? ? ?if (tileb> ?surf->tsplit) {
>> ? ? ? ? ? ? ? ?slice_pt = tileb / surf->tsplit;
>> @@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct
>> radeon_cs_parser *p,
>> ? ? ? ?/* macro tile width& ?height */
>>
>> ? ? ? ?palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
>> ? ? ? ?halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
>> - ? ? ? surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
>> + ? ? ? mtileb = (palign / 8) * (halign / 8) * tileb;;
>> + ? ? ? mtile_pr = surf->nbx / palign;
>> + ? ? ? mtile_ps = (mtile_pr * surf->nby) / halign;
>> + ? ? ? surf->layer_size = mtile_ps * mtileb * slice_pt;
>> ? ? ? ?surf->base_align = (palign / 8) * (halign / 8) * tileb;
>> ? ? ? ?surf->palign = palign;
>> ? ? ? ?surf->halign = halign;
>> @@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct
>> radeon_cs_parser *p, unsigned i
>>
>> ? ? ? ?offset += surf.layer_size * mslice;
>> ? ? ? ?if (offset> ?radeon_bo_size(track->cb_color_bo[id])) {
>> + ? ? ? ? ? ? ? /* old ddx are broken they allocate bo with w*h*bpp but
>> + ? ? ? ? ? ? ? ?* program slice with ALIGN(h, 8), catch this and patch
>> + ? ? ? ? ? ? ? ?* command stream.
>> + ? ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? ? if (!surf.mode) {
>> + ? ? ? ? ? ? ? ? ? ? ? volatile u32 *ib = p->ib.ptr;
>> + ? ? ? ? ? ? ? ? ? ? ? unsigned long tmp, nby, bsize, size, min = 0;
>> +
>> + ? ? ? ? ? ? ? ? ? ? ? /* find the height the ddx wants */
>> + ? ? ? ? ? ? ? ? ? ? ? if (surf.nby> ?8) {
>> + ? ? ? ? ? ? ? ? ? ? ?

[PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread j.gli...@gmail.com 
From: Jerome Glisse 

Fix regresson since the introduction of command stream checking on
evergreen (thread referenced below). Issue is cause by ddx allocating
bo with formula width*height*bpp while programming the GPU command
stream with ALIGN(height, 8). In some case (where page alignment does
not hide the extra size bo should be according to height alignment)
the kernel will reject the command stream.

This patch reprogram the command stream to slice - 1 (slice is
a derivative value from height) which avoid rejecting the command
stream while keeping the value of command stream checking from a
security point of view.

This patch also fix wrong computation of layer size for 2D tiled
surface. Which should fix issue when 2D color tiling is enabled.
This dump the radeon KMS_DRIVER_MINOR so userspace can know if
they are on a fixed kernel or not.

https://lkml.org/lkml/2012/6/3/80
https://bugs.freedesktop.org/show_bug.cgi?id=50892
https://bugs.freedesktop.org/show_bug.cgi?id=50857

!!! STABLE need a custom version of this patch for 3.4 !!!

v2: actually bump the minor version and add comment about stable
v3: do compute the height the ddx was trying to use

Signed-off-by: Jerome Glisse 
---
 drivers/gpu/drm/radeon/evergreen_cs.c |   50 ++---
 drivers/gpu/drm/radeon/radeon_drv.c   |3 +-
 2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b..29c43c6 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
u32 cb_color_view[12];
u32 cb_color_pitch[12];
u32 cb_color_slice[12];
+   u32 cb_color_slice_idx[12];
u32 cb_color_attrib[12];
u32 cb_color_cmask_slice[8];/* unused */
u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct 
evergreen_cs_track *track)
track->cb_color_info[i] = 0;
track->cb_color_view[i] = 0x;
track->cb_color_pitch[i] = 0;
-   track->cb_color_slice[i] = 0;
+   track->cb_color_slice[i] = 0xfff;
+   track->cb_color_slice_idx[i] = 0;
}
track->cb_target_mask = 0x;
track->cb_shader_mask = 0x;
track->cb_dirty = true;

+   track->db_depth_slice = 0x;
track->db_depth_view = 0xC000;
track->db_depth_size = 0x;
track->db_depth_control = 0x;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
 {
struct evergreen_cs_track *track = p->track;
unsigned palign, halign, tileb, slice_pt;
+   unsigned mtile_pr, mtile_ps, mtileb;

tileb = 64 * surf->bpe * surf->nsamples;
-   palign = track->group_size / (8 * surf->bpe * surf->nsamples);
-   palign = MAX(8, palign);
slice_pt = 1;
if (tileb > surf->tsplit) {
slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
/* macro tile width & height */
palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
-   surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
+   mtileb = (palign / 8) * (halign / 8) * tileb;;
+   mtile_pr = surf->nbx / palign;
+   mtile_ps = (mtile_pr * surf->nby) / halign;
+   surf->layer_size = mtile_ps * mtileb * slice_pt;
surf->base_align = (palign / 8) * (halign / 8) * tileb;
surf->palign = palign;
surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct 
radeon_cs_parser *p, unsigned i

offset += surf.layer_size * mslice;
if (offset > radeon_bo_size(track->cb_color_bo[id])) {
+   /* old ddx are broken they allocate bo with w*h*bpp but
+* program slice with ALIGN(h, 8), catch this and patch
+* command stream.
+*/
+   if (!surf.mode) {
+   volatile u32 *ib = p->ib.ptr;
+   unsigned long tmp, nby, bsize, size, min = 0;
+
+   /* find the height the ddx wants */
+   if (surf.nby > 8) {
+   min = surf.nby - 8;
+   }
+   bsize = radeon_bo_size(track->cb_color_bo[id]);
+   tmp = track->cb_color_bo_offset[id] << 8;
+   for (nby = surf.nby; nby > min; nby--) {
+   size = nby * surf.nbx * surf.bpe * 
surf.nsamples;
+   if

[PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread j . glisse 
From: Jerome Glisse jgli...@redhat.com

Fix regresson since the introduction of command stream checking on
evergreen (thread referenced below). Issue is cause by ddx allocating
bo with formula width*height*bpp while programming the GPU command
stream with ALIGN(height, 8). In some case (where page alignment does
not hide the extra size bo should be according to height alignment)
the kernel will reject the command stream.

This patch reprogram the command stream to slice - 1 (slice is
a derivative value from height) which avoid rejecting the command
stream while keeping the value of command stream checking from a
security point of view.

This patch also fix wrong computation of layer size for 2D tiled
surface. Which should fix issue when 2D color tiling is enabled.
This dump the radeon KMS_DRIVER_MINOR so userspace can know if
they are on a fixed kernel or not.

https://lkml.org/lkml/2012/6/3/80
https://bugs.freedesktop.org/show_bug.cgi?id=50892
https://bugs.freedesktop.org/show_bug.cgi?id=50857

!!! STABLE need a custom version of this patch for 3.4 !!!

v2: actually bump the minor version and add comment about stable
v3: do compute the height the ddx was trying to use

Signed-off-by: Jerome Glisse jgli...@redhat.com
---
 drivers/gpu/drm/radeon/evergreen_cs.c |   50 ++---
 drivers/gpu/drm/radeon/radeon_drv.c   |3 +-
 2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b..29c43c6 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
u32 cb_color_view[12];
u32 cb_color_pitch[12];
u32 cb_color_slice[12];
+   u32 cb_color_slice_idx[12];
u32 cb_color_attrib[12];
u32 cb_color_cmask_slice[8];/* unused */
u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct 
evergreen_cs_track *track)
track-cb_color_info[i] = 0;
track-cb_color_view[i] = 0x;
track-cb_color_pitch[i] = 0;
-   track-cb_color_slice[i] = 0;
+   track-cb_color_slice[i] = 0xfff;
+   track-cb_color_slice_idx[i] = 0;
}
track-cb_target_mask = 0x;
track-cb_shader_mask = 0x;
track-cb_dirty = true;
 
+   track-db_depth_slice = 0x;
track-db_depth_view = 0xC000;
track-db_depth_size = 0x;
track-db_depth_control = 0x;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
 {
struct evergreen_cs_track *track = p-track;
unsigned palign, halign, tileb, slice_pt;
+   unsigned mtile_pr, mtile_ps, mtileb;
 
tileb = 64 * surf-bpe * surf-nsamples;
-   palign = track-group_size / (8 * surf-bpe * surf-nsamples);
-   palign = MAX(8, palign);
slice_pt = 1;
if (tileb  surf-tsplit) {
slice_pt = tileb / surf-tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
/* macro tile width  height */
palign = (8 * surf-bankw * track-npipes) * surf-mtilea;
halign = (8 * surf-bankh * surf-nbanks) / surf-mtilea;
-   surf-layer_size = surf-nbx * surf-nby * surf-bpe * slice_pt;
+   mtileb = (palign / 8) * (halign / 8) * tileb;;
+   mtile_pr = surf-nbx / palign;
+   mtile_ps = (mtile_pr * surf-nby) / halign;
+   surf-layer_size = mtile_ps * mtileb * slice_pt;
surf-base_align = (palign / 8) * (halign / 8) * tileb;
surf-palign = palign;
surf-halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct 
radeon_cs_parser *p, unsigned i
 
offset += surf.layer_size * mslice;
if (offset  radeon_bo_size(track-cb_color_bo[id])) {
+   /* old ddx are broken they allocate bo with w*h*bpp but
+* program slice with ALIGN(h, 8), catch this and patch
+* command stream.
+*/
+   if (!surf.mode) {
+   volatile u32 *ib = p-ib.ptr;
+   unsigned long tmp, nby, bsize, size, min = 0;
+
+   /* find the height the ddx wants */
+   if (surf.nby  8) {
+   min = surf.nby - 8;
+   }
+   bsize = radeon_bo_size(track-cb_color_bo[id]);
+   tmp = track-cb_color_bo_offset[id]  8;
+   for (nby = surf.nby; nby  min; nby--) {
+   size = nby * surf.nbx * surf.bpe * 
surf.nsamples;
+   if ((tmp + size * mslice) = bsize)

Re: [PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread Boszormenyi Zoltan 

2012-06-09 16:57 keltezéssel, j.gli...@gmail.com írta:

From: Jerome Glissejgli...@redhat.com

Fix regresson since the introduction of command stream checking on
evergreen (thread referenced below). Issue is cause by ddx allocating
bo with formula width*height*bpp while programming the GPU command
stream with ALIGN(height, 8). In some case (where page alignment does
not hide the extra size bo should be according to height alignment)
the kernel will reject the command stream.

This patch reprogram the command stream to slice - 1 (slice is
a derivative value from height) which avoid rejecting the command
stream while keeping the value of command stream checking from a
security point of view.

This patch also fix wrong computation of layer size for 2D tiled
surface. Which should fix issue when 2D color tiling is enabled.
This dump the radeon KMS_DRIVER_MINOR so userspace can know if
they are on a fixed kernel or not.

https://lkml.org/lkml/2012/6/3/80
https://bugs.freedesktop.org/show_bug.cgi?id=50892
https://bugs.freedesktop.org/show_bug.cgi?id=50857

!!! STABLE need a custom version of this patch for 3.4 !!!

v2: actually bump the minor version and add comment about stable
v3: do compute the height the ddx was trying to use

Signed-off-by: Jerome Glissejgli...@redhat.com
---
  drivers/gpu/drm/radeon/evergreen_cs.c |   50 ++---
  drivers/gpu/drm/radeon/radeon_drv.c   |3 +-
  2 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b..29c43c6 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
u32 cb_color_view[12];
u32 cb_color_pitch[12];
u32 cb_color_slice[12];
+   u32 cb_color_slice_idx[12];
u32 cb_color_attrib[12];
u32 cb_color_cmask_slice[8];/* unused */
u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct 
evergreen_cs_track *track)
track-cb_color_info[i] = 0;
track-cb_color_view[i] = 0x;
track-cb_color_pitch[i] = 0;
-   track-cb_color_slice[i] = 0;
+   track-cb_color_slice[i] = 0xfff;
+   track-cb_color_slice_idx[i] = 0;
}
track-cb_target_mask = 0x;
track-cb_shader_mask = 0x;
track-cb_dirty = true;

+   track-db_depth_slice = 0x;
track-db_depth_view = 0xC000;
track-db_depth_size = 0x;
track-db_depth_control = 0x;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
  {
struct evergreen_cs_track *track = p-track;
unsigned palign, halign, tileb, slice_pt;
+   unsigned mtile_pr, mtile_ps, mtileb;

tileb = 64 * surf-bpe * surf-nsamples;
-   palign = track-group_size / (8 * surf-bpe * surf-nsamples);
-   palign = MAX(8, palign);
slice_pt = 1;
if (tileb  surf-tsplit) {
slice_pt = tileb / surf-tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct 
radeon_cs_parser *p,
/* macro tile width  height */
palign = (8 * surf-bankw * track-npipes) * surf-mtilea;
halign = (8 * surf-bankh * surf-nbanks) / surf-mtilea;
-   surf-layer_size = surf-nbx * surf-nby * surf-bpe * slice_pt;
+   mtileb = (palign / 8) * (halign / 8) * tileb;;
+   mtile_pr = surf-nbx / palign;
+   mtile_ps = (mtile_pr * surf-nby) / halign;
+   surf-layer_size = mtile_ps * mtileb * slice_pt;
surf-base_align = (palign / 8) * (halign / 8) * tileb;
surf-palign = palign;
surf-halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct 
radeon_cs_parser *p, unsigned i

offset += surf.layer_size * mslice;
if (offset  radeon_bo_size(track-cb_color_bo[id])) {
+   /* old ddx are broken they allocate bo with w*h*bpp but
+* program slice with ALIGN(h, 8), catch this and patch
+* command stream.
+*/
+   if (!surf.mode) {
+   volatile u32 *ib = p-ib.ptr;
+   unsigned long tmp, nby, bsize, size, min = 0;
+
+   /* find the height the ddx wants */
+   if (surf.nby  8) {
+   min = surf.nby - 8;
+   }
+   bsize = radeon_bo_size(track-cb_color_bo[id]);
+   tmp = track-cb_color_bo_offset[id]  8;
+   for (nby = surf.nby; nby  min; nby--) {
+   size = nby * surf.nbx * surf.bpe * 
surf.nsamples;
+

Re: [PATCH] drm/radeon: fix tiling and command stream checking on evergreen v3

2012-06-09 Thread Jerome Glisse 
On Sat, Jun 9, 2012 at 12:15 PM, Boszormenyi Zoltan zbos...@pr.hu wrote:
 2012-06-09 16:57 keltezéssel, j.gli...@gmail.com írta:

 From: Jerome Glissejgli...@redhat.com

 Fix regresson since the introduction of command stream checking on
 evergreen (thread referenced below). Issue is cause by ddx allocating
 bo with formula width*height*bpp while programming the GPU command
 stream with ALIGN(height, 8). In some case (where page alignment does
 not hide the extra size bo should be according to height alignment)
 the kernel will reject the command stream.

 This patch reprogram the command stream to slice - 1 (slice is
 a derivative value from height) which avoid rejecting the command
 stream while keeping the value of command stream checking from a
 security point of view.

 This patch also fix wrong computation of layer size for 2D tiled
 surface. Which should fix issue when 2D color tiling is enabled.
 This dump the radeon KMS_DRIVER_MINOR so userspace can know if
 they are on a fixed kernel or not.

 https://lkml.org/lkml/2012/6/3/80
 https://bugs.freedesktop.org/show_bug.cgi?id=50892
 https://bugs.freedesktop.org/show_bug.cgi?id=50857

 !!! STABLE need a custom version of this patch for 3.4 !!!

 v2: actually bump the minor version and add comment about stable
 v3: do compute the height the ddx was trying to use

 Signed-off-by: Jerome Glissejgli...@redhat.com
 ---
  drivers/gpu/drm/radeon/evergreen_cs.c |   50
 ++---
  drivers/gpu/drm/radeon/radeon_drv.c   |    3 +-
  2 files changed, 48 insertions(+), 5 deletions(-)

 diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c
 b/drivers/gpu/drm/radeon/evergreen_cs.c
 index 4e7dd2b..29c43c6 100644
 --- a/drivers/gpu/drm/radeon/evergreen_cs.c
 +++ b/drivers/gpu/drm/radeon/evergreen_cs.c
 @@ -52,6 +52,7 @@ struct evergreen_cs_track {
        u32                     cb_color_view[12];
        u32                     cb_color_pitch[12];
        u32                     cb_color_slice[12];
 +       u32                     cb_color_slice_idx[12];
        u32                     cb_color_attrib[12];
        u32                     cb_color_cmask_slice[8];/* unused */
        u32                     cb_color_fmask_slice[8];/* unused */
 @@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct
 evergreen_cs_track *track)
                track-cb_color_info[i] = 0;
                track-cb_color_view[i] = 0x;
                track-cb_color_pitch[i] = 0;
 -               track-cb_color_slice[i] = 0;
 +               track-cb_color_slice[i] = 0xfff;
 +               track-cb_color_slice_idx[i] = 0;
        }
        track-cb_target_mask = 0x;
        track-cb_shader_mask = 0x;
        track-cb_dirty = true;

 +       track-db_depth_slice = 0x;
        track-db_depth_view = 0xC000;
        track-db_depth_size = 0x;
        track-db_depth_control = 0x;
 @@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct
 radeon_cs_parser *p,
  {
        struct evergreen_cs_track *track = p-track;
        unsigned palign, halign, tileb, slice_pt;
 +       unsigned mtile_pr, mtile_ps, mtileb;

        tileb = 64 * surf-bpe * surf-nsamples;
 -       palign = track-group_size / (8 * surf-bpe * surf-nsamples);
 -       palign = MAX(8, palign);
        slice_pt = 1;
        if (tileb  surf-tsplit) {
                slice_pt = tileb / surf-tsplit;
 @@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct
 radeon_cs_parser *p,
        /* macro tile width  height */

        palign = (8 * surf-bankw * track-npipes) * surf-mtilea;
        halign = (8 * surf-bankh * surf-nbanks) / surf-mtilea;
 -       surf-layer_size = surf-nbx * surf-nby * surf-bpe * slice_pt;
 +       mtileb = (palign / 8) * (halign / 8) * tileb;;
 +       mtile_pr = surf-nbx / palign;
 +       mtile_ps = (mtile_pr * surf-nby) / halign;
 +       surf-layer_size = mtile_ps * mtileb * slice_pt;
        surf-base_align = (palign / 8) * (halign / 8) * tileb;
        surf-palign = palign;
        surf-halign = halign;
 @@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct
 radeon_cs_parser *p, unsigned i

        offset += surf.layer_size * mslice;
        if (offset  radeon_bo_size(track-cb_color_bo[id])) {
 +               /* old ddx are broken they allocate bo with w*h*bpp but
 +                * program slice with ALIGN(h, 8), catch this and patch
 +                * command stream.
 +                */
 +               if (!surf.mode) {
 +                       volatile u32 *ib = p-ib.ptr;
 +                       unsigned long tmp, nby, bsize, size, min = 0;
 +
 +                       /* find the height the ddx wants */
 +                       if (surf.nby  8) {
 +                               min = surf.nby - 8;
 +                       }
 +                       bsize = radeon_bo_size(track-cb_color_bo[id]);
 +                       tmp = track-cb_color_bo_offset[id]  8;
 +