RE: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
Hi Quanyang & Laurent, I tested this patch(which moves pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable), i don't see any behavior change with patch, means with patch also DP display is not getting up and it is required to resolution change to make it up. Also valid bit is not getting set for VPLL_FRAC_CFG on bootup, same behavior as without patch. Thanks, Rohit > -Original Message- > From: Michal Simek > Sent: Wednesday, March 17, 2021 1:56 PM > To: quanyang.wang ; Laurent Pinchart > ; Rohit Visavalia > > Cc: Hyun Kwon ; David Airlie ; > Daniel Vetter ; Michal Simek ; dri- > de...@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel > clock > > +Rohit > > On 3/17/21 4:00 AM, quanyang.wang wrote: > > Hi Laurent, > > > > On 3/17/21 4:32 AM, Laurent Pinchart wrote: > >> Hi Quanyang, > >> > >> Thank you for the patch. > >> > >> On Wed, Mar 10, 2021 at 12:59:45PM +0800, > quanyang.w...@windriver.com > >> wrote: > >>> From: Quanyang Wang > >>> > >>> The Runtime PM subsystem will force the device "fd4a.zynqmp- > display" > >>> to enter suspend state while booting if the following conditions are > >>> met: > >>> - the usage counter is zero (pm_runtime_get_sync hasn't been called > >>> yet) > >>> - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) > >>> - no other device in the same power domain (dpdma node has no > >>> "power-domains = <_firmware PD_DP>" property) > >>> > >>> So there is a scenario as below: > >>> 1) DP device enters suspend state <- call zynqmp_gpd_power_off > >>> 2) zynqmp_disp_crtc_setup_clock <- configurate register > >>> VPLL_FRAC_CFG > >>> 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and > >>> clear previous > >>> VPLL_FRAC_CFG configuration > >>> 4) clk_prepare_enable(disp->pclk) <- enable failed since > >>> VPLL_FRAC_CFG > >>> configuration is corrupted > >>> > >>> From above, we can see that pm_runtime_get_sync may clear register > >>> VPLL_FRAC_CFG configuration and result the failure of clk enabling. > >>> Putting pm_runtime_get_sync at the very beginning of the function > >>> zynqmp_disp_crtc_atomic_enable can resolve this issue. > >> Isn't this an issue in the firmware though, which shouldn't clear the > >> previous VPLLF_FRAC_CFG ? > > > > Thank you for your review. I used to look into the atf and PWU code > > and it seems (I didn't add debug code > > > > to PMU to make sure if PMU really does this, I only in kernel call > > zynqmp_pm_get_pll_frac_data to make sure that > > > > the value in data field of VPLL_FRAC_CFG register is changed from > > 0x4000 to 0x0 after run pm_runtime_get_sync) > > > > that PMU intends to reset VPLL when there is an Off and On in DP > > Powerdomain. > > > > > > Linux ATF PWU > > > > zynqmp_gpd_power_on > > ->zynqmp_pm_set_requirement > > -->send PM_SET_REQUIREMENT to ATF ==> ATF send ipi to PWU > > ==> PmSetRequirement > > ->PmRequirementUpdate > > -->PmUpdateSlave(masterReq->slave) > > --->PmSlaveChangeState > > >PmSlaveChangeState > > ->PmSlaveClearAfterState > > -->PmClockRelease > > > > --->PmClockReleaseInt(>clock->base) > > >clk->class->release(clk) > > ->PmPllBypassAndReset > > //Here reset the VPLL then VPLL_FRAC_CFG is cleared. > > > >> > >>> Signed-off-by: Quanyang Wang > >> Nonetheless, this change looks good to me, I actually had the same > >> patch in my tree while investigation issues related to the clock > >> rate, so > >> > >> Reviewed-by: Laurent Pinchart > >> Tested-by: Laurent Pinchart > >> > >> I was hoping it would solve the issue I'm experiencing with th
Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
Hi Rohit, On 3/17/21 7:17 PM, Rohit Visavalia wrote: Hi Quanyang & Laurent, I tested this patch(which moves pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable), i don't see any behavior change with patch, means with patch also DP display is not getting up and it is required to resolution change to make it up. Also valid bit is not getting set for VPLL_FRAC_CFG on bootup, same behavior as without patch. Thank you for your test. This patch works under the condition of applying the below patch (drm: xlnx: set PLL_MODE_FRAC mode to VPLL_FRAC_CFG by re-enabling disp->pclk) (Patch 1) first. Without Patch 1, the VPLL mode isn't set correctly and clk_prepare_enable don't take effect. DP monitor can't receive any signal since the clk is wrong. After applying Patch 1, there will be error log in the boot message: [ 1.325602] zynqmp_pll_enable() clock enable failed for vpll_int, ret = -22 [ 1.325614] zynqmp-dpsub fd4a.display: failed to enable a pixel clock [ 1.456106] [ cut here ] [ 1.456109] [CRTC:33:crtc-0] vblank wait timed out [ 1.456152] WARNING: CPU: 2 PID: 75 at drivers/gpu/drm/drm_atomic_helper.c:1512 drm_atomic_helper_wait_for_vblanks.part.0+0x27c/0x298 [ 1.456172] Modules linked in: [ 1.456181] CPU: 2 PID: 75 Comm: kworker/2:1 Not tainted 5.12.0-rc2-00338-gf78d76e72a46-dirty #4 [ 1.456188] Hardware name: ZynqMP ZCU102 Rev1.0 (DT) [ 1.456194] Workqueue: events deferred_probe_work_func Then applying this patch ( drm: xlnx: call pm_runtime_get_sync before setting pixel clock), this issue will be fixed, DP monitor will receive signal, but screen is still black. Then applying the below patch (drm: xlnx: configure alpha value to make graphic layer opaque) (Patch 2), the DP will work well. Thanks, Quanyang Thanks, Rohit -Original Message- From: Michal Simek Sent: Wednesday, March 17, 2021 1:56 PM To: quanyang.wang ; Laurent Pinchart ; Rohit Visavalia Cc: Hyun Kwon ; David Airlie ; Daniel Vetter ; Michal Simek ; dri- de...@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org; linux- ker...@vger.kernel.org Subject: Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock +Rohit On 3/17/21 4:00 AM, quanyang.wang wrote: Hi Laurent, On 3/17/21 4:32 AM, Laurent Pinchart wrote: Hi Quanyang, Thank you for the patch. On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com wrote: From: Quanyang Wang The Runtime PM subsystem will force the device "fd4a.zynqmp- display" to enter suspend state while booting if the following conditions are met: - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) - no other device in the same power domain (dpdma node has no "power-domains = <_firmware PD_DP>" property) So there is a scenario as below: 1) DP device enters suspend state <- call zynqmp_gpd_power_off 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous VPLL_FRAC_CFG configuration 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG configuration is corrupted From above, we can see that pm_runtime_get_sync may clear register VPLL_FRAC_CFG configuration and result the failure of clk enabling. Putting pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable can resolve this issue. Isn't this an issue in the firmware though, which shouldn't clear the previous VPLLF_FRAC_CFG ? Thank you for your review. I used to look into the atf and PWU code and it seems (I didn't add debug code to PMU to make sure if PMU really does this, I only in kernel call zynqmp_pm_get_pll_frac_data to make sure that the value in data field of VPLL_FRAC_CFG register is changed from 0x4000 to 0x0 after run pm_runtime_get_sync) that PMU intends to reset VPLL when there is an Off and On in DP Powerdomain. Linux ATF PWU zynqmp_gpd_power_on ->zynqmp_pm_set_requirement -->send PM_SET_REQUIREMENT to ATF ==> ATF send ipi to PWU ==> PmSetRequirement ->PmRequirementUpdate -->PmUpdateSlave(masterReq->slave) --->PmSlaveChangeState >PmSlaveChangeState ->PmSlaveClearAfterState -->PmClockRelease --->PmClockReleaseInt(>clock->base) >clk->class->release(clk) ->PmPllBypassAndReset //Here reset the VP
Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
+Rohit On 3/17/21 4:00 AM, quanyang.wang wrote: > Hi Laurent, > > On 3/17/21 4:32 AM, Laurent Pinchart wrote: >> Hi Quanyang, >> >> Thank you for the patch. >> >> On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com >> wrote: >>> From: Quanyang Wang >>> >>> The Runtime PM subsystem will force the device "fd4a.zynqmp-display" >>> to enter suspend state while booting if the following conditions are >>> met: >>> - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) >>> - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) >>> - no other device in the same power domain (dpdma node has no >>> "power-domains = <_firmware PD_DP>" property) >>> >>> So there is a scenario as below: >>> 1) DP device enters suspend state <- call zynqmp_gpd_power_off >>> 2) zynqmp_disp_crtc_setup_clock <- configurate register >>> VPLL_FRAC_CFG >>> 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and >>> clear previous >>> VPLL_FRAC_CFG configuration >>> 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG >>> configuration is corrupted >>> >>> From above, we can see that pm_runtime_get_sync may clear register >>> VPLL_FRAC_CFG configuration and result the failure of clk enabling. >>> Putting pm_runtime_get_sync at the very beginning of the function >>> zynqmp_disp_crtc_atomic_enable can resolve this issue. >> Isn't this an issue in the firmware though, which shouldn't clear the >> previous VPLLF_FRAC_CFG ? > > Thank you for your review. I used to look into the atf and PWU code and > it seems (I didn't add debug code > > to PMU to make sure if PMU really does this, I only in kernel call > zynqmp_pm_get_pll_frac_data to make sure that > > the value in data field of VPLL_FRAC_CFG register is changed from 0x4000 > to 0x0 after run pm_runtime_get_sync) > > that PMU intends to reset VPLL when there is an Off and On in DP > Powerdomain. > > > Linux ATF PWU > > zynqmp_gpd_power_on > ->zynqmp_pm_set_requirement > -->send PM_SET_REQUIREMENT to ATF ==> ATF send ipi to PWU > ==> PmSetRequirement > ->PmRequirementUpdate > -->PmUpdateSlave(masterReq->slave) > --->PmSlaveChangeState > >PmSlaveChangeState > ->PmSlaveClearAfterState > -->PmClockRelease > > --->PmClockReleaseInt(>clock->base) > >clk->class->release(clk) > ->PmPllBypassAndReset > //Here reset the VPLL then VPLL_FRAC_CFG is cleared. > >> >>> Signed-off-by: Quanyang Wang >> Nonetheless, this change looks good to me, I actually had the same patch >> in my tree while investigation issues related to the clock rate, so >> >> Reviewed-by: Laurent Pinchart >> Tested-by: Laurent Pinchart >> >> I was hoping it would solve the issue I'm experiencing with the DP >> clock, but that's not the case :-( In a nutshell, when the DP is first >> started, the clock frequency is incorrect. The following quick & dirty >> patch fixes the problem: >> >> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c >> b/drivers/gpu/drm/xlnx/zynqmp_disp.c >> index 74ac0a064eb5..fdbe1b0640aa 100644 >> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c >> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c >> @@ -1439,6 +1439,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc >> *crtc, >> >> pm_runtime_get_sync(disp->dev); >> >> + ret = clk_prepare_enable(disp->pclk); >> + if (!ret) >> + clk_disable_unprepare(disp->pclk); >> + >> zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); >> >> ret = clk_prepare_enable(disp->pclk); >> >> The problem doesn't seem to be in the kernel, but on the TF-A or PMU >> firmware side. Have you experienced this by any chance ? > > Yes, I bumped into the same issue and I used to make a patch (Patch 1) > as below. > > I didn't send it to mainline because it seems not to be a driver issue. > The mode of VPLL > > is not set correctly because: > > 1) VPLL is enabled before linux > > 2) linux calling pm_clock_set_pll_mode can't really set register because > in ATF > > it only store the mode value to a structure and wait a clk-enable > request to do > > the register-set operation. > > 3) linux call clk_enable will not send a clk-enable request since it > checks that > > the VPLL is already hardware-enabled because of 1). > > So the firmware should disable VPLL when it exits and also in linux > zynqmp clk driver > > there should be a check list to reset some clks to a predefined state. > > > By the way, there is a tiny patch (Patch 2) to fix the black screen > issue in DP. I think you may > > be preparing a big
Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
Hi Laurent, On 3/17/21 4:32 AM, Laurent Pinchart wrote: Hi Quanyang, Thank you for the patch. On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com wrote: From: Quanyang Wang The Runtime PM subsystem will force the device "fd4a.zynqmp-display" to enter suspend state while booting if the following conditions are met: - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) - no other device in the same power domain (dpdma node has no "power-domains = <_firmware PD_DP>" property) So there is a scenario as below: 1) DP device enters suspend state <- call zynqmp_gpd_power_off 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous VPLL_FRAC_CFG configuration 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG configuration is corrupted From above, we can see that pm_runtime_get_sync may clear register VPLL_FRAC_CFG configuration and result the failure of clk enabling. Putting pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable can resolve this issue. Isn't this an issue in the firmware though, which shouldn't clear the previous VPLLF_FRAC_CFG ? Thank you for your review. I used to look into the atf and PWU code and it seems (I didn't add debug code to PMU to make sure if PMU really does this, I only in kernel call zynqmp_pm_get_pll_frac_data to make sure that the value in data field of VPLL_FRAC_CFG register is changed from 0x4000 to 0x0 after run pm_runtime_get_sync) that PMU intends to reset VPLL when there is an Off and On in DP Powerdomain. Linux ATF PWU zynqmp_gpd_power_on ->zynqmp_pm_set_requirement -->send PM_SET_REQUIREMENT to ATF ==>ATF send ipi to PWU ==> PmSetRequirement ->PmRequirementUpdate -->PmUpdateSlave(masterReq->slave) --->PmSlaveChangeState >PmSlaveChangeState ->PmSlaveClearAfterState -->PmClockRelease --->PmClockReleaseInt(>clock->base) >clk->class->release(clk) ->PmPllBypassAndReset //Here reset the VPLL then VPLL_FRAC_CFG is cleared. Signed-off-by: Quanyang Wang Nonetheless, this change looks good to me, I actually had the same patch in my tree while investigation issues related to the clock rate, so Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart I was hoping it would solve the issue I'm experiencing with the DP clock, but that's not the case :-( In a nutshell, when the DP is first started, the clock frequency is incorrect. The following quick & dirty patch fixes the problem: diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 74ac0a064eb5..fdbe1b0640aa 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -1439,6 +1439,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, pm_runtime_get_sync(disp->dev); + ret = clk_prepare_enable(disp->pclk); + if (!ret) + clk_disable_unprepare(disp->pclk); + zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); ret = clk_prepare_enable(disp->pclk); The problem doesn't seem to be in the kernel, but on the TF-A or PMU firmware side. Have you experienced this by any chance ? Yes, I bumped into the same issue and I used to make a patch (Patch 1) as below. I didn't send it to mainline because it seems not to be a driver issue. The mode of VPLL is not set correctly because: 1) VPLL is enabled before linux 2) linux calling pm_clock_set_pll_mode can't really set register because in ATF it only store the mode value to a structure and wait a clk-enable request to do the register-set operation. 3) linux call clk_enable will not send a clk-enable request since it checks that the VPLL is already hardware-enabled because of 1). So the firmware should disable VPLL when it exits and also in linux zynqmp clk driver there should be a check list to reset some clks to a predefined state. By the way, there is a tiny patch (Patch 2) to fix the black screen issue in DP. I think you
Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
Hi Quanyang,
Thank you for the patch.
On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com wrote:
> From: Quanyang Wang
>
> The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
> to enter suspend state while booting if the following conditions are met:
> - the usage counter is zero (pm_runtime_get_sync hasn't been called yet)
> - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node)
> - no other device in the same power domain (dpdma node has no
> "power-domains = <_firmware PD_DP>" property)
>
> So there is a scenario as below:
> 1) DP device enters suspend state <- call zynqmp_gpd_power_off
> 2) zynqmp_disp_crtc_setup_clock <- configurate register
> VPLL_FRAC_CFG
> 3) pm_runtime_get_sync<- call zynqmp_gpd_power_on and
> clear previous
> VPLL_FRAC_CFG configuration
> 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG
> configuration is corrupted
>
> From above, we can see that pm_runtime_get_sync may clear register
> VPLL_FRAC_CFG configuration and result the failure of clk enabling.
> Putting pm_runtime_get_sync at the very beginning of the function
> zynqmp_disp_crtc_atomic_enable can resolve this issue.
Isn't this an issue in the firmware though, which shouldn't clear the
previous VPLLF_FRAC_CFG ?
> Signed-off-by: Quanyang Wang
Nonetheless, this change looks good to me, I actually had the same patch
in my tree while investigation issues related to the clock rate, so
Reviewed-by: Laurent Pinchart
Tested-by: Laurent Pinchart
I was hoping it would solve the issue I'm experiencing with the DP
clock, but that's not the case :-( In a nutshell, when the DP is first
started, the clock frequency is incorrect. The following quick & dirty
patch fixes the problem:
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 74ac0a064eb5..fdbe1b0640aa 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -1439,6 +1439,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
pm_runtime_get_sync(disp->dev);
+ ret = clk_prepare_enable(disp->pclk);
+ if (!ret)
+ clk_disable_unprepare(disp->pclk);
+
zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
ret = clk_prepare_enable(disp->pclk);
The problem doesn't seem to be in the kernel, but on the TF-A or PMU
firmware side. Have you experienced this by any chance ?
> ---
> drivers/gpu/drm/xlnx/zynqmp_disp.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> index 148add0ca1d6..909e6c265406 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -1445,9 +1445,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
> struct drm_display_mode *adjusted_mode = >state->adjusted_mode;
> int ret, vrefresh;
>
> + pm_runtime_get_sync(disp->dev);
> +
> zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
>
> - pm_runtime_get_sync(disp->dev);
> ret = clk_prepare_enable(disp->pclk);
> if (ret) {
> dev_err(disp->dev, "failed to enable a pixel clock\n");
--
Regards,
Laurent Pinchart
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Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
Ping.
Any comment on this patch?
Thanks,
Quanyang
On 3/10/21 12:59 PM, quanyang.w...@windriver.com wrote:
From: Quanyang Wang
The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
to enter suspend state while booting if the following conditions are met:
- the usage counter is zero (pm_runtime_get_sync hasn't been called yet)
- no 'active' children (no zynqmp-dp-snd-xx node under dpsub node)
- no other device in the same power domain (dpdma node has no
"power-domains = <_firmware PD_DP>" property)
So there is a scenario as below:
1) DP device enters suspend state <- call zynqmp_gpd_power_off
2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG
3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear
previous
VPLL_FRAC_CFG configuration
4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG
configuration is corrupted
From above, we can see that pm_runtime_get_sync may clear register
VPLL_FRAC_CFG configuration and result the failure of clk enabling.
Putting pm_runtime_get_sync at the very beginning of the function
zynqmp_disp_crtc_atomic_enable can resolve this issue.
Signed-off-by: Quanyang Wang
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 148add0ca1d6..909e6c265406 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -1445,9 +1445,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_display_mode *adjusted_mode = >state->adjusted_mode;
int ret, vrefresh;
+ pm_runtime_get_sync(disp->dev);
+
zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
- pm_runtime_get_sync(disp->dev);
ret = clk_prepare_enable(disp->pclk);
if (ret) {
dev_err(disp->dev, "failed to enable a pixel clock\n");
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[PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock
From: Quanyang Wang
The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
to enter suspend state while booting if the following conditions are met:
- the usage counter is zero (pm_runtime_get_sync hasn't been called yet)
- no 'active' children (no zynqmp-dp-snd-xx node under dpsub node)
- no other device in the same power domain (dpdma node has no
"power-domains = <_firmware PD_DP>" property)
So there is a scenario as below:
1) DP device enters suspend state <- call zynqmp_gpd_power_off
2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG
3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear
previous
VPLL_FRAC_CFG configuration
4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG
configuration is corrupted
>From above, we can see that pm_runtime_get_sync may clear register
VPLL_FRAC_CFG configuration and result the failure of clk enabling.
Putting pm_runtime_get_sync at the very beginning of the function
zynqmp_disp_crtc_atomic_enable can resolve this issue.
Signed-off-by: Quanyang Wang
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 148add0ca1d6..909e6c265406 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -1445,9 +1445,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_display_mode *adjusted_mode = >state->adjusted_mode;
int ret, vrefresh;
+ pm_runtime_get_sync(disp->dev);
+
zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
- pm_runtime_get_sync(disp->dev);
ret = clk_prepare_enable(disp->pclk);
if (ret) {
dev_err(disp->dev, "failed to enable a pixel clock\n");
--
2.25.1
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