[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
In this specific case, the eg_surface_sanity function (or something
like that, I don't remember its name) returns an error. Then the
cascade of perfectly working fail codepaths propagate the error to the
OpenGL user as an unsupported framebuffer object setup.
Marek
On Tue, Oct 16, 2012 at 8:50 AM, Paul Menzel
wrote:
> Dear Marek,
>
>
> Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Ol??k:
>> The calculation led to the number 8192, which is too high.
>
> what is the reason it is limited to 4096? Hardware limitation?
>
> What are the ramifications? GPU hangs, rendering errors?
>
>> ---
>> radeon/radeon_surface.c |2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
>> index 66c2444..eb587d2 100644
>> --- a/radeon/radeon_surface.c
>> +++ b/radeon/radeon_surface.c
>> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
>> *surf_man,
>> } else {
>> /* tile split must be >= 256 for colorbuffer surfaces */
>> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
>> +if (surf->tile_split > 4096)
>> +surf->tile_split = 4096;
>> }
>> } else {
>> /* set tile split to row size */
>
>
> Thanks,
>
> Paul
[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
Dear Marek,
Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Ol??k:
> The calculation led to the number 8192, which is too high.
what is the reason it is limited to 4096? Hardware limitation?
What are the ramifications? GPU hangs, rendering errors?
> ---
> radeon/radeon_surface.c |2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
> index 66c2444..eb587d2 100644
> --- a/radeon/radeon_surface.c
> +++ b/radeon/radeon_surface.c
> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
> *surf_man,
> } else {
> /* tile split must be >= 256 for colorbuffer surfaces */
> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
> +if (surf->tile_split > 4096)
> +surf->tile_split = 4096;
> }
> } else {
> /* set tile split to row size */
Thanks,
Paul
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[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
On Mon, Oct 15, 2012 at 8:21 PM, Marek Ol??k wrote:
> The calculation led to the number 8192, which is too high.
Looks good.
Reviewed-by: Alex Deucher
> ---
> radeon/radeon_surface.c |2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
> index 66c2444..eb587d2 100644
> --- a/radeon/radeon_surface.c
> +++ b/radeon/radeon_surface.c
> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
> *surf_man,
> } else {
> /* tile split must be >= 256 for colorbuffer surfaces */
> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
> +if (surf->tile_split > 4096)
> +surf->tile_split = 4096;
> }
> } else {
> /* set tile split to row size */
> --
> 1.7.9.5
>
> ___
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> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
On Tue, Oct 16, 2012 at 2:50 AM, Paul Menzel
wrote:
> Dear Marek,
>
>
> Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Ol??k:
>> The calculation led to the number 8192, which is too high.
>
> what is the reason it is limited to 4096? Hardware limitation?
hw limit.
>
> What are the ramifications? GPU hangs, rendering errors?
Rendering errors.
Alex
>
>> ---
>> radeon/radeon_surface.c |2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
>> index 66c2444..eb587d2 100644
>> --- a/radeon/radeon_surface.c
>> +++ b/radeon/radeon_surface.c
>> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
>> *surf_man,
>> } else {
>> /* tile split must be >= 256 for colorbuffer surfaces */
>> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
>> +if (surf->tile_split > 4096)
>> +surf->tile_split = 4096;
>> }
>> } else {
>> /* set tile split to row size */
>
>
> Thanks,
>
> Paul
>
> ___
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> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be >= 256 for colorbuffer surfaces */
surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+if (surf->tile_split > 4096)
+surf->tile_split = 4096;
}
} else {
/* set tile split to row size */
--
1.7.9.5
Re: [PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
Dear Marek,
Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák:
The calculation led to the number 8192, which is too high.
what is the reason it is limited to 4096? Hardware limitation?
What are the ramifications? GPU hangs, rendering errors?
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be = 256 for colorbuffer surfaces */
surf-tile_split = MAX2(surf-nsamples * surf-bpe * 64, 256);
+if (surf-tile_split 4096)
+surf-tile_split = 4096;
}
} else {
/* set tile split to row size */
Thanks,
Paul
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Re: [PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
On Tue, Oct 16, 2012 at 2:50 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear Marek,
Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák:
The calculation led to the number 8192, which is too high.
what is the reason it is limited to 4096? Hardware limitation?
hw limit.
What are the ramifications? GPU hangs, rendering errors?
Rendering errors.
Alex
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be = 256 for colorbuffer surfaces */
surf-tile_split = MAX2(surf-nsamples * surf-bpe * 64, 256);
+if (surf-tile_split 4096)
+surf-tile_split = 4096;
}
} else {
/* set tile split to row size */
Thanks,
Paul
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Re: [PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
On Mon, Oct 15, 2012 at 8:21 PM, Marek Olšák mar...@gmail.com wrote:
The calculation led to the number 8192, which is too high.
Looks good.
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be = 256 for colorbuffer surfaces */
surf-tile_split = MAX2(surf-nsamples * surf-bpe * 64, 256);
+if (surf-tile_split 4096)
+surf-tile_split = 4096;
}
} else {
/* set tile split to row size */
--
1.7.9.5
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Re: [PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
In this specific case, the eg_surface_sanity function (or something
like that, I don't remember its name) returns an error. Then the
cascade of perfectly working fail codepaths propagate the error to the
OpenGL user as an unsupported framebuffer object setup.
Marek
On Tue, Oct 16, 2012 at 8:50 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear Marek,
Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák:
The calculation led to the number 8192, which is too high.
what is the reason it is limited to 4096? Hardware limitation?
What are the ramifications? GPU hangs, rendering errors?
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be = 256 for colorbuffer surfaces */
surf-tile_split = MAX2(surf-nsamples * surf-bpe * 64, 256);
+if (surf-tile_split 4096)
+surf-tile_split = 4096;
}
} else {
/* set tile split to row size */
Thanks,
Paul
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[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
---
radeon/radeon_surface.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be = 256 for colorbuffer surfaces */
surf-tile_split = MAX2(surf-nsamples * surf-bpe * 64, 256);
+if (surf-tile_split 4096)
+surf-tile_split = 4096;
}
} else {
/* set tile split to row size */
--
1.7.9.5
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