RE: [PATCH 07/10] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display

2018-01-10 Thread Hyun Kwon 
Hi Daniel,

> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Tuesday, January 09, 2018 1:47 AM
> To: Hyun Kwon <hy...@xilinx.com>
> Cc: dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; Michal
> Simek <michal.si...@xilinx.com>
> Subject: Re: [PATCH 07/10] drm: xlnx: DRM KMS driver for Xilinx ZynqMP
> DP subsystem display
> 
> On Thu, Jan 04, 2018 at 06:05:56PM -0800, Hyun Kwon wrote:
> > Xilinx ZynqMP has a hardened display pipeline. The pipeline can
> > be logically partitioned into 2 parts: display and DisplayPort.
> > This driver handles the display part of the pipeline that handles
> > buffer management and blending.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > ---
> >  drivers/gpu/drm/xlnx/zynqmp_disp.c | 2935
> 
> >  drivers/gpu/drm/xlnx/zynqmp_disp.h |   28 +
> >  2 files changed, 2963 insertions(+)
> >  create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c
> >  create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > new file mode 100644
> > index 000..68f829c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > @@ -0,0 +1,2935 @@
> > +/*
> > + * ZynqMP Display Controller Driver
> > + *
> > + *  Copyright (C) 2017 - 2018 Xilinx, Inc.
> > + *
> > + *  Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "xlnx_crtc.h"
> > +#include "xlnx_fb.h"
> > +#include "zynqmp_disp.h"
> > +#include "zynqmp_dp.h"
> > +#include "zynqmp_dpsub.h"
> > +
> > +/*
> > + * Overview
> > + * 
> > + *
> > + * The display part of ZynqMP DP subsystem. Internally, the device
> > + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio.
> > + * The driver creates the DRM crtc and plane objectes and maps the DRM
> > + * interface into those 3 blocks. In high level, the driver is layered
> > + * in the following way:
> > + *
> > + * zynqmp_disp_crtc & zynqmp_disp_plane
> > + * |->zynqmp_disp
> > + * |->zynqmp_disp_aud
> > + * |->zynqmp_disp_blend
> > + * |->zynqmp_disp_av_buf
> > + *
> > + * The driver APIs are used externally by
> > + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver
> > + * - zynqmp_dp: ZynqMP DP driver
> > + * - xlnx_crtc: Xilinx DRM specific crtc functions
> > + */
> > +
> > +/* Blender registers */
> > +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0   0x0
> > +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1   0x4
> > +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2   0x8
> > +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
> > +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA   0xc
> > +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK  0x1fe
> > +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX   0xff
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB
>   0x0
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY   0x3
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC   0x4
> > +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE   BIT(4)
> > +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL  0x18
> > +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US
>   BIT(0)
> > +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB  BIT(1)
> > +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS   BIT(8)
> > +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF  9
> > +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0   0x20
> > +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1   0x24
> > +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEF

Re: [PATCH 07/10] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display

2018-01-09 Thread Daniel Vetter 
On Thu, Jan 04, 2018 at 06:05:56PM -0800, Hyun Kwon wrote:
> Xilinx ZynqMP has a hardened display pipeline. The pipeline can
> be logically partitioned into 2 parts: display and DisplayPort.
> This driver handles the display part of the pipeline that handles
> buffer management and blending.
> 
> Signed-off-by: Hyun Kwon 
> ---
>  drivers/gpu/drm/xlnx/zynqmp_disp.c | 2935 
> 
>  drivers/gpu/drm/xlnx/zynqmp_disp.h |   28 +
>  2 files changed, 2963 insertions(+)
>  create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c
>  create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h
> 
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c 
> b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> new file mode 100644
> index 000..68f829c
> --- /dev/null
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -0,0 +1,2935 @@
> +/*
> + * ZynqMP Display Controller Driver
> + *
> + *  Copyright (C) 2017 - 2018 Xilinx, Inc.
> + *
> + *  Author: Hyun Woo Kwon 
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "xlnx_crtc.h"
> +#include "xlnx_fb.h"
> +#include "zynqmp_disp.h"
> +#include "zynqmp_dp.h"
> +#include "zynqmp_dpsub.h"
> +
> +/*
> + * Overview
> + * 
> + *
> + * The display part of ZynqMP DP subsystem. Internally, the device
> + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio.
> + * The driver creates the DRM crtc and plane objectes and maps the DRM
> + * interface into those 3 blocks. In high level, the driver is layered
> + * in the following way:
> + *
> + * zynqmp_disp_crtc & zynqmp_disp_plane
> + * |->zynqmp_disp
> + *   |->zynqmp_disp_aud
> + *   |->zynqmp_disp_blend
> + *   |->zynqmp_disp_av_buf
> + *
> + * The driver APIs are used externally by
> + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver
> + * - zynqmp_dp: ZynqMP DP driver
> + * - xlnx_crtc: Xilinx DRM specific crtc functions
> + */
> +
> +/* Blender registers */
> +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0
> +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4
> +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8
> +#define ZYNQMP_DISP_V_BLEND_BG_MAX   0xfff
> +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc
> +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK0x1fe
> +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT   0x14
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB   0x0
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444  0x1
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422  0x2
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4
> +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4)
> +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL0x18
> +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US  BIT(0)
> +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGBBIT(1)
> +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8)
> +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF9
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c
> +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF00x44
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF10x48
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF20x4c
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF30x50
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF40x54
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF50x58
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF60x5c
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF70x60
> +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF80x64
> +#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET   3
> +#define ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET   0x68
> +#define ZYNQMP_DISP_V_BLEND_CR_IN1CSC_OFFSET 0x6c
> +#define ZYNQMP_DISP_V_BLEND_CB_IN1CSC_OFFSET 0x70
> +#define ZYNQMP_DISP_V_BLEND_LUMA_OUTCSC_OFFSET   0x74
> +#define ZYNQMP_DISP_V_BLEND_CR_OUTCSC_OFFSET 0x78
> +#define ZYNQMP_DISP_V_BLEND_CB_OUTCSC_OFFSET 0x7c
> +#define

[PATCH 07/10] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display

2018-01-04 Thread Hyun Kwon 
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display and DisplayPort.
This driver handles the display part of the pipeline that handles
buffer management and blending.

Signed-off-by: Hyun Kwon 
---
 drivers/gpu/drm/xlnx/zynqmp_disp.c | 2935 
 drivers/gpu/drm/xlnx/zynqmp_disp.h |   28 +
 2 files changed, 2963 insertions(+)
 create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c
 create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h

diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c 
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
new file mode 100644
index 000..68f829c
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -0,0 +1,2935 @@
+/*
+ * ZynqMP Display Controller Driver
+ *
+ *  Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ *  Author: Hyun Woo Kwon 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "xlnx_crtc.h"
+#include "xlnx_fb.h"
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+/*
+ * Overview
+ * 
+ *
+ * The display part of ZynqMP DP subsystem. Internally, the device
+ * is partitioned into 3 blocks: AV buffer manager, Blender, Audio.
+ * The driver creates the DRM crtc and plane objectes and maps the DRM
+ * interface into those 3 blocks. In high level, the driver is layered
+ * in the following way:
+ *
+ * zynqmp_disp_crtc & zynqmp_disp_plane
+ * |->zynqmp_disp
+ * |->zynqmp_disp_aud
+ * |->zynqmp_disp_blend
+ * |->zynqmp_disp_av_buf
+ *
+ * The driver APIs are used externally by
+ * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver
+ * - zynqmp_dp: ZynqMP DP driver
+ * - xlnx_crtc: Xilinx DRM specific crtc functions
+ */
+
+/* Blender registers */
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_0   0x0
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_1   0x4
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_2   0x8
+#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA   0xc
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK  0x1fe
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX   0xff
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY   0x3
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC   0x4
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE   BIT(4)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL  0x18
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB  BIT(1)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS   BIT(8)
+#define ZYNQMP_DISP_V_BLEND_NUM_COEFF  9
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0   0x20
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1   0x24
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2   0x28
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3   0x2c
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4   0x30
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5   0x34
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6   0x38
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7   0x3c
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8   0x40
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0  0x44
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1  0x48
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2  0x4c
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3  0x50
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4  0x54
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5  0x58
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF6  0x5c
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF7  0x60
+#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF8  0x64
+#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 3
+#define ZYNQMP_DISP_V_BLEND_LUMA_IN1CSC_OFFSET 0x68
+#define ZYNQMP_DISP_V_BLEND_CR_IN1CSC_OFFSET   0x6c
+#define ZYNQMP_DISP_V_BLEND_CB_IN1CSC_OFFSET   0x70
+#define ZYNQMP_DISP_V_BLEND_LUMA_OUTCSC_OFFSET 0x74
+#define ZYNQMP_DISP_V_BLEND_CR_OUTCSC_OFFSET   0x78
+#define ZYNQMP_DISP_V_BLEND_CB_OUTCSC_OFFSET   0x7c
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF0  0x80
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF1  0x84
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF2  0x88
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF3  0x8c
+#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF4