[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
2012? 9? 13? Joonyoung Shim?? ??:
> On 09/13/2012 11:53 AM, Inki Dae wrote:
>
> -Original Message-
> From: Joonyoung Shim [mailto:jy0922.shim at samsung.com]
> Sent: Thursday, September 13, 2012 10:44 AM
> To: Rahul Sharma
> Cc: dri-devel at lists.freedesktop.org; sw0312.kim at samsung.com;
> inki.dae at samsung.com; kyungmin.park at samsung.com; prashanth.g at
> samsung.com;
> joshi at samsung.com; s.shirish at samsung.com; fahad.k at samsung.com;
> l.krishna at samsung.com; r.sh.open at gmail.com
> Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
> driver
>
> Hi, Rahul.
>
> On 09/12/2012 09:08 PM, Rahul Sharma wrote:
>
> Added support for exynos5 to drm mixer driver. Exynos5 works
> with dt enabled while in exynos4 mixer device information can
> be passed either way (dt or plf data). This situation is taken
> cared.
>
> Signed-off-by: Rahul Sharma
> Signed-off-by: Shirish S
> Signed-off-by: Fahad Kunnathadi
> ---
>drivers/gpu/drm/exynos/exynos_mixer.c | 153
>
> ++---
>
>drivers/gpu/drm/exynos/regs-mixer.h |2 +
>2 files changed, 142 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>
> b/drivers/gpu/drm/exynos/exynos_mixer.c
>
> index 8a43ee1..7d04a40 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -71,6 +71,7 @@ struct mixer_resources {
> struct clk *sclk_mixer;
> struct clk *sclk_hdmi;
> struct clk *sclk_dac;
> + boolis_soc_exynos5;
>};
>
>struct mixer_context {
> @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
>
> mixer_context *ctx, bool enable)
>
> mixer_reg_writemask(res, MXR_STATUS, enable ?
> MXR_STATUS_SYNC_ENABLE : 0,
MXR_STATUS_SYNC_ENABLE);
>
> - vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> + if (!res->is_soc_exynos5)
> + vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> VP_SHADOW_UPDATE_ENABLE : 0);
>}
>
> @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
>
> *ctx)
>
> val = MXR_GRP_CFG_ALPHA_VAL(0);
> mixer_reg_write(res, MXR_VIDEO_CFG, val);
>
> - /* configuration of Video Processor Registers */
> - vp_win_reset(ctx);
> - vp_default_filter(res);
> + if (!res->is_soc_exynos5) {
> + /* configuration of Video Processor Registers */
> + vp_win_reset(ctx);
> + vp_default_filter(res);
> + }
>
> /* disable all layers */
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
>
> + /* enable vsync interrupt after mixer reset*/
> + mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
> + MXR_INT_EN_VSYNC);
> +
> mixer_vsync_set_update(ctx, true);
> spin_unlock_irqrestore(>reg_slock, flags);
>}
> @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
> pm_runtime_get_sync(ctx->dev);
>
> clk_enable(res->mixer);
> - clk_enable(res->vp);
> + if (!res->is_soc_exynos5)
> + clk_enable(res->vp);
> clk_enable(res->sclk_mixer);
>
> mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
> @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
>
> *ctx)
>
> ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
>
> clk_disable(res->mixer
>
> Let's think to disassociate hdmi and mixer. I have plan to unify to one
> many things of exynos hdmi. Above problem occurs because exynos5 doesn't
> have video processor ip. Even if we use a field such is_soc_exynos5, the
> is_soc_exynos5 is unsuitable naming if other exynos SoC also doesn't
> have video processor ip.
>
one more thing, exynos5 uses GScaler instead of Video processor. the
GScaler can be also used as post processor but exynos5 spec has no any
descriptions to this. so we should check that first and next let's update
things related to hdmi.
___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
On 09/13/2012 11:53 AM, Inki Dae wrote:
>
>> -Original Message-
>> From: Joonyoung Shim [mailto:jy0922.shim at samsung.com]
>> Sent: Thursday, September 13, 2012 10:44 AM
>> To: Rahul Sharma
>> Cc: dri-devel at lists.freedesktop.org; sw0312.kim at samsung.com;
>> inki.dae at samsung.com; kyungmin.park at samsung.com; prashanth.g at
>> samsung.com;
>> joshi at samsung.com; s.shirish at samsung.com; fahad.k at samsung.com;
>> l.krishna at samsung.com; r.sh.open at gmail.com
>> Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
>> driver
>>
>> Hi, Rahul.
>>
>> On 09/12/2012 09:08 PM, Rahul Sharma wrote:
>>> Added support for exynos5 to drm mixer driver. Exynos5 works
>>> with dt enabled while in exynos4 mixer device information can
>>> be passed either way (dt or plf data). This situation is taken
>>> cared.
>>>
>>> Signed-off-by: Rahul Sharma
>>> Signed-off-by: Shirish S
>>> Signed-off-by: Fahad Kunnathadi
>>> ---
>>>drivers/gpu/drm/exynos/exynos_mixer.c | 153
>> ++---
>>>drivers/gpu/drm/exynos/regs-mixer.h |2 +
>>>2 files changed, 142 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> index 8a43ee1..7d04a40 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> @@ -71,6 +71,7 @@ struct mixer_resources {
>>> struct clk *sclk_mixer;
>>> struct clk *sclk_hdmi;
>>> struct clk *sclk_dac;
>>> + boolis_soc_exynos5;
>>>};
>>>
>>>struct mixer_context {
>>> @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
>> mixer_context *ctx, bool enable)
>>> mixer_reg_writemask(res, MXR_STATUS, enable ?
>>> MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
>>>
>>> - vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
>>> + if (!res->is_soc_exynos5)
>>> + vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
>>> VP_SHADOW_UPDATE_ENABLE : 0);
>>>}
>>>
>>> @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
>> *ctx)
>>> val = MXR_GRP_CFG_ALPHA_VAL(0);
>>> mixer_reg_write(res, MXR_VIDEO_CFG, val);
>>>
>>> - /* configuration of Video Processor Registers */
>>> - vp_win_reset(ctx);
>>> - vp_default_filter(res);
>>> + if (!res->is_soc_exynos5) {
>>> + /* configuration of Video Processor Registers */
>>> + vp_win_reset(ctx);
>>> + vp_default_filter(res);
>>> + }
>>>
>>> /* disable all layers */
>>> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
>>> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
>>> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
>>>
>>> + /* enable vsync interrupt after mixer reset*/
>>> + mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
>>> + MXR_INT_EN_VSYNC);
>>> +
>>> mixer_vsync_set_update(ctx, true);
>>> spin_unlock_irqrestore(>reg_slock, flags);
>>>}
>>> @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
>>> pm_runtime_get_sync(ctx->dev);
>>>
>>> clk_enable(res->mixer);
>>> - clk_enable(res->vp);
>>> + if (!res->is_soc_exynos5)
>>> + clk_enable(res->vp);
>>> clk_enable(res->sclk_mixer);
>>>
>>> mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
>>> @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
> *ctx)
>>> ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
>>>
>>> clk_disable(res->mixer);
>>> - clk_disable(res->vp);
>>> + if (!res->is_soc_exynos5)
>>> + clk_disable(res->vp);
>>> clk_disable(res->sclk_mixer);
>>>
>>> pm_runtime_put_sync(ctx->dev);
>>> @@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
>>>static void mixer_win_commit(void *ctx, int win)
>>>{
>>> struct mixer_context *mixer_ctx = ctx;
>>> + struct mixer_resources *res = _ctx->mixer_res;
>>>
[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
> -Original Message-
> From: Joonyoung Shim [mailto:jy0922.shim at samsung.com]
> Sent: Thursday, September 13, 2012 10:44 AM
> To: Rahul Sharma
> Cc: dri-devel at lists.freedesktop.org; sw0312.kim at samsung.com;
> inki.dae at samsung.com; kyungmin.park at samsung.com; prashanth.g at
> samsung.com;
> joshi at samsung.com; s.shirish at samsung.com; fahad.k at samsung.com;
> l.krishna at samsung.com; r.sh.open at gmail.com
> Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
> driver
>
> Hi, Rahul.
>
> On 09/12/2012 09:08 PM, Rahul Sharma wrote:
> > Added support for exynos5 to drm mixer driver. Exynos5 works
> > with dt enabled while in exynos4 mixer device information can
> > be passed either way (dt or plf data). This situation is taken
> > cared.
> >
> > Signed-off-by: Rahul Sharma
> > Signed-off-by: Shirish S
> > Signed-off-by: Fahad Kunnathadi
> > ---
> > drivers/gpu/drm/exynos/exynos_mixer.c | 153
> ++---
> > drivers/gpu/drm/exynos/regs-mixer.h |2 +
> > 2 files changed, 142 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> > index 8a43ee1..7d04a40 100644
> > --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> > +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> > @@ -71,6 +71,7 @@ struct mixer_resources {
> > struct clk *sclk_mixer;
> > struct clk *sclk_hdmi;
> > struct clk *sclk_dac;
> > + boolis_soc_exynos5;
> > };
> >
> > struct mixer_context {
> > @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
> mixer_context *ctx, bool enable)
> > mixer_reg_writemask(res, MXR_STATUS, enable ?
> > MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
> >
> > - vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> > + if (!res->is_soc_exynos5)
> > + vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> > VP_SHADOW_UPDATE_ENABLE : 0);
> > }
> >
> > @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
> *ctx)
> > val = MXR_GRP_CFG_ALPHA_VAL(0);
> > mixer_reg_write(res, MXR_VIDEO_CFG, val);
> >
> > - /* configuration of Video Processor Registers */
> > - vp_win_reset(ctx);
> > - vp_default_filter(res);
> > + if (!res->is_soc_exynos5) {
> > + /* configuration of Video Processor Registers */
> > + vp_win_reset(ctx);
> > + vp_default_filter(res);
> > + }
> >
> > /* disable all layers */
> > mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
> > mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
> > mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
> >
> > + /* enable vsync interrupt after mixer reset*/
> > + mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
> > + MXR_INT_EN_VSYNC);
> > +
> > mixer_vsync_set_update(ctx, true);
> > spin_unlock_irqrestore(>reg_slock, flags);
> > }
> > @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
> > pm_runtime_get_sync(ctx->dev);
> >
> > clk_enable(res->mixer);
> > - clk_enable(res->vp);
> > + if (!res->is_soc_exynos5)
> > + clk_enable(res->vp);
> > clk_enable(res->sclk_mixer);
> >
> > mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
> > @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
*ctx)
> > ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
> >
> > clk_disable(res->mixer);
> > - clk_disable(res->vp);
> > + if (!res->is_soc_exynos5)
> > + clk_disable(res->vp);
> > clk_disable(res->sclk_mixer);
> >
> > pm_runtime_put_sync(ctx->dev);
> > @@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
> > static void mixer_win_commit(void *ctx, int win)
> > {
> > struct mixer_context *mixer_ctx = ctx;
> > + struct mixer_resources *res = _ctx->mixer_res;
> >
> > DRM_DEBUG_KMS("[%d] %s, win: %d\n", __LINE__, __func__, win);
> >
> > - if (win > 1)
> > - vp_video_buffer(mixer_ctx, win);
> > + if (!res->is_soc_exynos5) {
> > + if (win > 1)
> > + vp_video_buffer(mixer_ctx, win);
> > + else
> > + mi
[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
Hi, Rahul.
On 09/12/2012 09:08 PM, Rahul Sharma wrote:
> Added support for exynos5 to drm mixer driver. Exynos5 works
> with dt enabled while in exynos4 mixer device information can
> be passed either way (dt or plf data). This situation is taken
> cared.
>
> Signed-off-by: Rahul Sharma
> Signed-off-by: Shirish S
> Signed-off-by: Fahad Kunnathadi
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 153
> ++---
> drivers/gpu/drm/exynos/regs-mixer.h |2 +
> 2 files changed, 142 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 8a43ee1..7d04a40 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -71,6 +71,7 @@ struct mixer_resources {
> struct clk *sclk_mixer;
> struct clk *sclk_hdmi;
> struct clk *sclk_dac;
> + boolis_soc_exynos5;
> };
>
> struct mixer_context {
> @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct mixer_context
> *ctx, bool enable)
> mixer_reg_writemask(res, MXR_STATUS, enable ?
> MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
>
> - vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> + if (!res->is_soc_exynos5)
> + vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> VP_SHADOW_UPDATE_ENABLE : 0);
> }
>
> @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context *ctx)
> val = MXR_GRP_CFG_ALPHA_VAL(0);
> mixer_reg_write(res, MXR_VIDEO_CFG, val);
>
> - /* configuration of Video Processor Registers */
> - vp_win_reset(ctx);
> - vp_default_filter(res);
> + if (!res->is_soc_exynos5) {
> + /* configuration of Video Processor Registers */
> + vp_win_reset(ctx);
> + vp_default_filter(res);
> + }
>
> /* disable all layers */
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
>
> + /* enable vsync interrupt after mixer reset*/
> + mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
> + MXR_INT_EN_VSYNC);
> +
> mixer_vsync_set_update(ctx, true);
> spin_unlock_irqrestore(>reg_slock, flags);
> }
> @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
> pm_runtime_get_sync(ctx->dev);
>
> clk_enable(res->mixer);
> - clk_enable(res->vp);
> + if (!res->is_soc_exynos5)
> + clk_enable(res->vp);
> clk_enable(res->sclk_mixer);
>
> mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
> @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context *ctx)
> ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
>
> clk_disable(res->mixer);
> - clk_disable(res->vp);
> + if (!res->is_soc_exynos5)
> + clk_disable(res->vp);
> clk_disable(res->sclk_mixer);
>
> pm_runtime_put_sync(ctx->dev);
> @@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
> static void mixer_win_commit(void *ctx, int win)
> {
> struct mixer_context *mixer_ctx = ctx;
> + struct mixer_resources *res = _ctx->mixer_res;
>
> DRM_DEBUG_KMS("[%d] %s, win: %d\n", __LINE__, __func__, win);
>
> - if (win > 1)
> - vp_video_buffer(mixer_ctx, win);
> + if (!res->is_soc_exynos5) {
> + if (win > 1)
> + vp_video_buffer(mixer_ctx, win);
> + else
> + mixer_graph_buffer(mixer_ctx, win);
> + }
> else
> mixer_graph_buffer(mixer_ctx, win);
> }
> @@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
>
> /* handling VSYNC */
> if (val & MXR_INT_STATUS_VSYNC) {
> + /* layer update mandatory for exynos5 soc,and not present
> + * in exynos4 */
> + if (res->is_soc_exynos5)
> + mixer_reg_writemask(res, MXR_CFG, ~0,
> + MXR_CFG_LAYER_UPDATE);
> +
> /* interlace scan need to check shadow register */
> if (ctx->interlace) {
> base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
> @@ -919,8 +940,81 @@ out:
> return IRQ_HANDLED;
> }
>
> -static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context
> *ctx,
> - struct platform_device *pdev)
> +static int __devinit mixer_resources_init_exynos5(
> + struct exynos_drm_hdmi_context *ctx,
> + struct platform_device *pdev)
> +{
> + struct mixer_context *mixer_ctx = ctx->ctx;
> + struct device *dev = >dev;
> + struct mixer_resources *mixer_res = _ctx->mixer_res;
> + struct resource
[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
--- Original Message ---
Sender : In-Ki Dae S5/Senior Engineer/System S/W
Lab./Samsung Electronics
Date : Sep 13, 2012 10:07 (GMT+05:30)
Title : Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
2012? 9? 13? Joonyoung Shim?? ??:
> On 09/13/2012 11:53 AM, Inki Dae wrote:
>
> -Original Message-
> From: Joonyoung Shim [mailto:jy0922.shim at samsung.com]
> Sent: Thursday, September 13, 2012 10:44 AM
> To: Rahul Sharma
> Cc: dri-devel at lists.freedesktop.org; sw0312.kim at samsung.com;
> inki.dae at samsung.com; kyungmin.park at samsung.com; prashanth.g at
> samsung.com;
> joshi at samsung.com; s.shirish at samsung.com; fahad.k at samsung.com;
> l.krishna at samsung.com; r.sh.open at gmail.com
> Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
> driver
>
> Hi, Rahul.
>
> On 09/12/2012 09:08 PM, Rahul Sharma wrote:
>
> Added support for exynos5 to drm mixer driver. Exynos5 works
> with dt enabled while in exynos4 mixer device information can
> be passed either way (dt or plf data). This situation is taken
> cared.
>
> Signed-off-by: Rahul Sharma
> Signed-off-by: Shirish S
> Signed-off-by: Fahad Kunnathadi
> ---
>drivers/gpu/drm/exynos/exynos_mixer.c | 153
>
> ++---
>
>drivers/gpu/drm/exynos/regs-mixer.h |2 +
>2 files changed, 142 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>
> b/drivers/gpu/drm/exynos/exynos_mixer.c
>
> index 8a43ee1..7d04a40 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -71,6 +71,7 @@ struct mixer_resources {
> struct clk *sclk_mixer;
> struct clk *sclk_hdmi;
> struct clk *sclk_dac;
> + boolis_soc_exynos5;
>};
>
>struct mixer_context {
> @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
>
> mixer_context *ctx, bool enable)
>
> mixer_reg_writemask(res, MXR_STATUS, enable ?
> MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
>
> - vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> + if (!res->is_soc_exynos5)
> + vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> VP_SHADOW_UPDATE_ENABLE : 0);
>}
>
> @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
>
> *ctx)
>
> val = MXR_GRP_CFG_ALPHA_VAL(0);
> mixer_reg_write(res, MXR_VIDEO_CFG, val);
>
> - /* configuration of Video Processor Registers */
> - vp_win_reset(ctx);
> - vp_default_filter(res);
> + if (!res->is_soc_exynos5) {
> + /* configuration of Video Processor Registers */
> + vp_win_reset(ctx);
> + vp_default_filter(res);
> + }
>
> /* disable all layers */
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
> mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
>
> + /* enable vsync interrupt after mixer reset*/
> + mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
> + MXR_INT_EN_VSYNC);
> +
> mixer_vsync_set_update(ctx, true);
> spin_unlock_irqrestore(>reg_slock, flags);
>}
> @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
> pm_runtime_get_sync(ctx->dev);
>
> clk_enable(res->mixer);
> - clk_enable(res->vp);
> + if (!res->is_soc_exynos5)
> + clk_enable(res->vp);
> clk_enable(res->sclk_mixer);
>
> mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
> @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
>
> *ctx)
>
> ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
>
> clk_disable(res->mixer
>
> Let's think to disassociate hdmi and mixer. I have plan to unify to one
> many things of exynos hdmi. Above problem occurs because exynos5 doesn't
> have video processor ip. Even if we use a field such is_soc_exynos5, the
> is_soc_exynos5 is unsuitable naming if other exynos SoC also doesn't
> have video processor ip.
>
one more thing, exynos5 uses GScaler instead of Video processor. the GScaler
can be also used as post processor but exynos5 spec has no any descriptions to
this. so we should check that first and next let's update things related to
hdmi.
Thanks Joonyoung, Inki,
I agree with you. mixer_resources_init_exynnos4,5 has code repetition here but
Since Exy4
is non-DT and and E
Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
2012년 9월 13일 목요일에 Joonyoung Shimjy0922.s...@samsung.com님이 작성:
On 09/13/2012 11:53 AM, Inki Dae wrote:
-Original Message-
From: Joonyoung Shim [mailto:jy0922.s...@samsung.com]
Sent: Thursday, September 13, 2012 10:44 AM
To: Rahul Sharma
Cc: dri-devel@lists.freedesktop.org; sw0312@samsung.com;
inki@samsung.com; kyungmin.p...@samsung.com; prashant...@samsung.com;
jo...@samsung.com; s.shir...@samsung.com; faha...@samsung.com;
l.kris...@samsung.com; r.sh.o...@gmail.com
Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
driver
Hi, Rahul.
On 09/12/2012 09:08 PM, Rahul Sharma wrote:
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Fahad Kunnathadi faha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153
++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
mixer_context *ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0,
MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res-is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
*ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res-is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(res-reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx-dev);
clk_enable(res-mixer);
- clk_enable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_enable(res-vp);
clk_enable(res-sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx-int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
*ctx)
ctx-int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res-mixer
Let's think to disassociate hdmi and mixer. I have plan to unify to one
many things of exynos hdmi. Above problem occurs because exynos5 doesn't
have video processor ip. Even if we use a field such is_soc_exynos5, the
is_soc_exynos5 is unsuitable naming if other exynos SoC also doesn't
have video processor ip.
one more thing, exynos5 uses GScaler instead of Video processor. the
GScaler can be also used as post processor but exynos5 spec has no any
descriptions to this. so we should check that first and next let's update
things related to hdmi.
___
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[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma
Signed-off-by: Shirish S
Signed-off-by: Fahad Kunnathadi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153 ++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct mixer_context
*ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res->is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context *ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res->is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(>reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx->dev);
clk_enable(res->mixer);
- clk_enable(res->vp);
+ if (!res->is_soc_exynos5)
+ clk_enable(res->vp);
clk_enable(res->sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context *ctx)
ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res->mixer);
- clk_disable(res->vp);
+ if (!res->is_soc_exynos5)
+ clk_disable(res->vp);
clk_disable(res->sclk_mixer);
pm_runtime_put_sync(ctx->dev);
@@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
static void mixer_win_commit(void *ctx, int win)
{
struct mixer_context *mixer_ctx = ctx;
+ struct mixer_resources *res = _ctx->mixer_res;
DRM_DEBUG_KMS("[%d] %s, win: %d\n", __LINE__, __func__, win);
- if (win > 1)
- vp_video_buffer(mixer_ctx, win);
+ if (!res->is_soc_exynos5) {
+ if (win > 1)
+ vp_video_buffer(mixer_ctx, win);
+ else
+ mixer_graph_buffer(mixer_ctx, win);
+ }
else
mixer_graph_buffer(mixer_ctx, win);
}
@@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* handling VSYNC */
if (val & MXR_INT_STATUS_VSYNC) {
+ /* layer update mandatory for exynos5 soc,and not present
+ * in exynos4 */
+ if (res->is_soc_exynos5)
+ mixer_reg_writemask(res, MXR_CFG, ~0,
+ MXR_CFG_LAYER_UPDATE);
+
/* interlace scan need to check shadow register */
if (ctx->interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -919,8 +940,81 @@ out:
return IRQ_HANDLED;
}
-static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
-struct platform_device *pdev)
+static int __devinit mixer_resources_init_exynos5(
+ struct exynos_drm_hdmi_context *ctx,
+ struct platform_device *pdev)
+{
+ struct mixer_context *mixer_ctx = ctx->ctx;
+ struct device *dev = >dev;
+ struct mixer_resources *mixer_res = _ctx->mixer_res;
+ struct resource *res;
+ int ret;
+
+ DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
+
+ mixer_res->is_soc_exynos5 = true;
+ spin_lock_init(_res->reg_slock);
+
+ mixer_res->mixer = clk_get(dev,
[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Fahad Kunnathadi faha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153 ++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct mixer_context
*ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res-is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context *ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res-is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(res-reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx-dev);
clk_enable(res-mixer);
- clk_enable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_enable(res-vp);
clk_enable(res-sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx-int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context *ctx)
ctx-int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res-mixer);
- clk_disable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_disable(res-vp);
clk_disable(res-sclk_mixer);
pm_runtime_put_sync(ctx-dev);
@@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
static void mixer_win_commit(void *ctx, int win)
{
struct mixer_context *mixer_ctx = ctx;
+ struct mixer_resources *res = mixer_ctx-mixer_res;
DRM_DEBUG_KMS([%d] %s, win: %d\n, __LINE__, __func__, win);
- if (win 1)
- vp_video_buffer(mixer_ctx, win);
+ if (!res-is_soc_exynos5) {
+ if (win 1)
+ vp_video_buffer(mixer_ctx, win);
+ else
+ mixer_graph_buffer(mixer_ctx, win);
+ }
else
mixer_graph_buffer(mixer_ctx, win);
}
@@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* handling VSYNC */
if (val MXR_INT_STATUS_VSYNC) {
+ /* layer update mandatory for exynos5 soc,and not present
+ * in exynos4 */
+ if (res-is_soc_exynos5)
+ mixer_reg_writemask(res, MXR_CFG, ~0,
+ MXR_CFG_LAYER_UPDATE);
+
/* interlace scan need to check shadow register */
if (ctx-interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -919,8 +940,81 @@ out:
return IRQ_HANDLED;
}
-static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
-struct platform_device *pdev)
+static int __devinit mixer_resources_init_exynos5(
+ struct exynos_drm_hdmi_context *ctx,
+ struct platform_device *pdev)
+{
+ struct mixer_context *mixer_ctx = ctx-ctx;
+ struct device *dev = pdev-dev;
+ struct mixer_resources *mixer_res = mixer_ctx-mixer_res;
+ struct resource *res;
+ int ret;
+
+ DRM_DEBUG_KMS([%d] %s\n, __LINE__, __func__);
+
+ mixer_res-is_soc_exynos5 = true;
+
Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
Hi, Rahul.
On 09/12/2012 09:08 PM, Rahul Sharma wrote:
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Fahad Kunnathadi faha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153 ++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct mixer_context
*ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res-is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context *ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res-is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(res-reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx-dev);
clk_enable(res-mixer);
- clk_enable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_enable(res-vp);
clk_enable(res-sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx-int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context *ctx)
ctx-int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res-mixer);
- clk_disable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_disable(res-vp);
clk_disable(res-sclk_mixer);
pm_runtime_put_sync(ctx-dev);
@@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
static void mixer_win_commit(void *ctx, int win)
{
struct mixer_context *mixer_ctx = ctx;
+ struct mixer_resources *res = mixer_ctx-mixer_res;
DRM_DEBUG_KMS([%d] %s, win: %d\n, __LINE__, __func__, win);
- if (win 1)
- vp_video_buffer(mixer_ctx, win);
+ if (!res-is_soc_exynos5) {
+ if (win 1)
+ vp_video_buffer(mixer_ctx, win);
+ else
+ mixer_graph_buffer(mixer_ctx, win);
+ }
else
mixer_graph_buffer(mixer_ctx, win);
}
@@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* handling VSYNC */
if (val MXR_INT_STATUS_VSYNC) {
+ /* layer update mandatory for exynos5 soc,and not present
+ * in exynos4 */
+ if (res-is_soc_exynos5)
+ mixer_reg_writemask(res, MXR_CFG, ~0,
+ MXR_CFG_LAYER_UPDATE);
+
/* interlace scan need to check shadow register */
if (ctx-interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -919,8 +940,81 @@ out:
return IRQ_HANDLED;
}
-static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
-struct platform_device *pdev)
+static int __devinit mixer_resources_init_exynos5(
+ struct exynos_drm_hdmi_context *ctx,
+ struct platform_device *pdev)
+{
+ struct mixer_context *mixer_ctx = ctx-ctx;
+ struct device *dev = pdev-dev;
+ struct mixer_resources *mixer_res = mixer_ctx-mixer_res;
+ struct resource *res;
+ int ret;
+
+ DRM_DEBUG_KMS([%d] %s\n, __LINE__, __func__);
+
+
RE: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
-Original Message-
From: Joonyoung Shim [mailto:jy0922.s...@samsung.com]
Sent: Thursday, September 13, 2012 10:44 AM
To: Rahul Sharma
Cc: dri-devel@lists.freedesktop.org; sw0312@samsung.com;
inki@samsung.com; kyungmin.p...@samsung.com; prashant...@samsung.com;
jo...@samsung.com; s.shir...@samsung.com; faha...@samsung.com;
l.kris...@samsung.com; r.sh.o...@gmail.com
Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
driver
Hi, Rahul.
On 09/12/2012 09:08 PM, Rahul Sharma wrote:
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Fahad Kunnathadi faha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153
++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
mixer_context *ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res-is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
*ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res-is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(res-reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx-dev);
clk_enable(res-mixer);
- clk_enable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_enable(res-vp);
clk_enable(res-sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx-int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
*ctx)
ctx-int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res-mixer);
- clk_disable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_disable(res-vp);
clk_disable(res-sclk_mixer);
pm_runtime_put_sync(ctx-dev);
@@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
static void mixer_win_commit(void *ctx, int win)
{
struct mixer_context *mixer_ctx = ctx;
+ struct mixer_resources *res = mixer_ctx-mixer_res;
DRM_DEBUG_KMS([%d] %s, win: %d\n, __LINE__, __func__, win);
- if (win 1)
- vp_video_buffer(mixer_ctx, win);
+ if (!res-is_soc_exynos5) {
+ if (win 1)
+ vp_video_buffer(mixer_ctx, win);
+ else
+ mixer_graph_buffer(mixer_ctx, win);
+ }
else
mixer_graph_buffer(mixer_ctx, win);
}
@@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void
*arg)
/* handling VSYNC */
if (val MXR_INT_STATUS_VSYNC) {
+ /* layer update mandatory for exynos5 soc,and not present
+ * in exynos4 */
+ if (res-is_soc_exynos5)
+ mixer_reg_writemask(res, MXR_CFG, ~0,
+ MXR_CFG_LAYER_UPDATE);
+
/* interlace scan need to check shadow register */
if (ctx-interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -919,8 +940,81 @@ out:
return IRQ_HANDLED;
}
-static int __devinit mixer_resources_init(struct
exynos_drm_hdmi_context *ctx,
-struct platform_device *pdev
Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver
On 09/13/2012 11:53 AM, Inki Dae wrote:
-Original Message-
From: Joonyoung Shim [mailto:jy0922.s...@samsung.com]
Sent: Thursday, September 13, 2012 10:44 AM
To: Rahul Sharma
Cc: dri-devel@lists.freedesktop.org; sw0312@samsung.com;
inki@samsung.com; kyungmin.p...@samsung.com; prashant...@samsung.com;
jo...@samsung.com; s.shir...@samsung.com; faha...@samsung.com;
l.kris...@samsung.com; r.sh.o...@gmail.com
Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
driver
Hi, Rahul.
On 09/12/2012 09:08 PM, Rahul Sharma wrote:
Added support for exynos5 to drm mixer driver. Exynos5 works
with dt enabled while in exynos4 mixer device information can
be passed either way (dt or plf data). This situation is taken
cared.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Fahad Kunnathadi faha...@samsung.com
---
drivers/gpu/drm/exynos/exynos_mixer.c | 153
++---
drivers/gpu/drm/exynos/regs-mixer.h |2 +
2 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8a43ee1..7d04a40 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ struct mixer_resources {
struct clk *sclk_mixer;
struct clk *sclk_hdmi;
struct clk *sclk_dac;
+ boolis_soc_exynos5;
};
struct mixer_context {
@@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
mixer_context *ctx, bool enable)
mixer_reg_writemask(res, MXR_STATUS, enable ?
MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
- vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
+ if (!res-is_soc_exynos5)
+ vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
VP_SHADOW_UPDATE_ENABLE : 0);
}
@@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
*ctx)
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);
- /* configuration of Video Processor Registers */
- vp_win_reset(ctx);
- vp_default_filter(res);
+ if (!res-is_soc_exynos5) {
+ /* configuration of Video Processor Registers */
+ vp_win_reset(ctx);
+ vp_default_filter(res);
+ }
/* disable all layers */
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
+ /* enable vsync interrupt after mixer reset*/
+ mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
+ MXR_INT_EN_VSYNC);
+
mixer_vsync_set_update(ctx, true);
spin_unlock_irqrestore(res-reg_slock, flags);
}
@@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
pm_runtime_get_sync(ctx-dev);
clk_enable(res-mixer);
- clk_enable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_enable(res-vp);
clk_enable(res-sclk_mixer);
mixer_reg_write(res, MXR_INT_EN, ctx-int_en);
@@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
*ctx)
ctx-int_en = mixer_reg_read(res, MXR_INT_EN);
clk_disable(res-mixer);
- clk_disable(res-vp);
+ if (!res-is_soc_exynos5)
+ clk_disable(res-vp);
clk_disable(res-sclk_mixer);
pm_runtime_put_sync(ctx-dev);
@@ -797,11 +807,16 @@ static void mixer_win_mode_set(void *ctx,
static void mixer_win_commit(void *ctx, int win)
{
struct mixer_context *mixer_ctx = ctx;
+ struct mixer_resources *res = mixer_ctx-mixer_res;
DRM_DEBUG_KMS([%d] %s, win: %d\n, __LINE__, __func__, win);
- if (win 1)
- vp_video_buffer(mixer_ctx, win);
+ if (!res-is_soc_exynos5) {
+ if (win 1)
+ vp_video_buffer(mixer_ctx, win);
+ else
+ mixer_graph_buffer(mixer_ctx, win);
+ }
else
mixer_graph_buffer(mixer_ctx, win);
}
@@ -888,6 +903,12 @@ static irqreturn_t mixer_irq_handler(int irq, void
*arg)
/* handling VSYNC */
if (val MXR_INT_STATUS_VSYNC) {
+ /* layer update mandatory for exynos5 soc,and not present
+ * in exynos4 */
+ if (res-is_soc_exynos5)
+ mixer_reg_writemask(res, MXR_CFG, ~0,
+ MXR_CFG_LAYER_UPDATE);
+
/* interlace scan need to check shadow register */
if (ctx-interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -919,8 +940,81 @@ out:
return IRQ_HANDLED;
}
-static int __devinit mixer_resources_init(struct
