[PATCH 10/12] drm/nouveau/graph: add GK20A support
On Thu, Apr 3, 2014 at 12:03 AM, Alexandre Courbot wrote: > On Wed, Mar 26, 2014 at 1:24 PM, Ben Skeggs wrote: >> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot >> wrote: >>> Add a GR device for GK20A based on NVE4, with the correct classes >>> definitions (GK20A's 3D class is 0xa297). >>> >>> Most of the NVE4 code can be used on GK20A, so make relevant bits of >>> NVE4 available to other chips as well. >> This will need a bit of a rebase on top of the tree I mentioned >> earlier (also queued for drm-next now), where I've further split out >> and named the various chunks of state. > > Will do that. > >> >> Does GK104 match entirely correctly, or just happen to work? I could >> probably hunt down the GK20A netlist images and check that actually :) > > Do you mean, the init sequence? I haven't checked in detail (we are > certainly doing things differently in the non-DRM driver), but the > registers seem to match and the GPU is able to render after that. I > admit I have not looked much further for now. I meant the arrays of register data, there's generally been some differences for most major chipset bumps. Where can I find the netlist firmware packages that go with the android driver? I can pull all the required info out of there to check :) > > The only register that does not exist on GK20A is 0x260, but when > accessing it Nouveau will be able to continue unharmed after a memory > fault. I have it in my queue to fix that too, the register doesn't exist on a couple of the other chips we support too.
[PATCH 10/12] drm/nouveau/graph: add GK20A support
On Wed, Mar 26, 2014 at 1:24 PM, Ben Skeggs wrote: > On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot > wrote: >> Add a GR device for GK20A based on NVE4, with the correct classes >> definitions (GK20A's 3D class is 0xa297). >> >> Most of the NVE4 code can be used on GK20A, so make relevant bits of >> NVE4 available to other chips as well. > This will need a bit of a rebase on top of the tree I mentioned > earlier (also queued for drm-next now), where I've further split out > and named the various chunks of state. Will do that. > > Does GK104 match entirely correctly, or just happen to work? I could > probably hunt down the GK20A netlist images and check that actually :) Do you mean, the init sequence? I haven't checked in detail (we are certainly doing things differently in the non-DRM driver), but the registers seem to match and the GPU is able to render after that. I admit I have not looked much further for now. The only register that does not exist on GK20A is 0x260, but when accessing it Nouveau will be able to continue unharmed after a memory fault.
[PATCH 10/12] drm/nouveau/graph: add GK20A support
On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
wrote:
> Add a GR device for GK20A based on NVE4, with the correct classes
> definitions (GK20A's 3D class is 0xa297).
>
> Most of the NVE4 code can be used on GK20A, so make relevant bits of
> NVE4 available to other chips as well.
This will need a bit of a rebase on top of the tree I mentioned
earlier (also queued for drm-next now), where I've further split out
and named the various chunks of state.
Does GK104 match entirely correctly, or just happen to work? I could
probably hunt down the GK20A netlist images and check that actually :)
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/gpu/drm/nouveau/Makefile | 1 +
> .../gpu/drm/nouveau/core/engine/graph/ctxnve4.c| 4 +-
> drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | 9 +++
> drivers/gpu/drm/nouveau/core/engine/graph/nve4.c | 2 +-
> drivers/gpu/drm/nouveau/core/engine/graph/nvea.c | 75
> ++
> .../gpu/drm/nouveau/core/include/engine/graph.h| 1 +
> 6 files changed, 89 insertions(+), 3 deletions(-)
> create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
>
> diff --git a/drivers/gpu/drm/nouveau/Makefile
> b/drivers/gpu/drm/nouveau/Makefile
> index 708d2e33835f..032a4744f843 100644
> --- a/drivers/gpu/drm/nouveau/Makefile
> +++ b/drivers/gpu/drm/nouveau/Makefile
> @@ -270,6 +270,7 @@ nouveau-y += core/engine/graph/nvc8.o
> nouveau-y += core/engine/graph/nvd7.o
> nouveau-y += core/engine/graph/nvd9.o
> nouveau-y += core/engine/graph/nve4.o
> +nouveau-y += core/engine/graph/nvea.o
> nouveau-y += core/engine/graph/nvf0.o
> nouveau-y += core/engine/graph/nv108.o
> nouveau-y += core/engine/mpeg/nv31.o
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
> b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
> index e2de73ee5eee..3904073f860d 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
> @@ -804,7 +804,7 @@ nve4_grctx_init_unk[] = {
> {}
> };
>
> -static void
> +void
> nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx
> *info)
> {
> u32 magic[GPC_MAX][2];
> @@ -962,7 +962,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv,
> struct nvc0_grctx *info)
> nv_mask(priv, 0x41be10, 0x0080, 0x0080);
> }
>
> -static struct nvc0_graph_init *
> +struct nvc0_graph_init *
> nve4_grctx_init_hub[] = {
> nvc0_grctx_init_base,
> nve4_grctx_init_unk40xx,
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
> b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
> index b0ab6de270b2..904f09b540c5 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
> @@ -221,6 +221,8 @@ void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv
> *);
> void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
> void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
>
> +void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
> +
> extern struct nouveau_oclass *nvc0_grctx_oclass;
> extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
> extern struct nvc0_graph_init nvc0_grctx_init_base[];
> @@ -237,12 +239,17 @@ extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
> extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
> extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
> extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
> +extern struct nvc0_graph_init nve4_grctx_init_icmd[];
> +
> +extern struct nvc0_graph_init *nve4_grctx_init_hub[];
> +extern struct nvc0_graph_init *nve4_grctx_init_gpc[];
>
> extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
> extern struct nvc0_graph_init nvc0_grctx_init_902d[];
> extern struct nvc0_graph_init nvc0_grctx_init_9039[];
> extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
> extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
> +extern struct nvc0_graph_init nve4_grctx_init_a097[];
>
> void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
> void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
> @@ -277,6 +284,8 @@ extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[];
>
> extern struct nouveau_oclass *nv108_grctx_oclass;
>
> +extern struct nvc0_graph_init *nve4_graph_init_mmio[];
> +
> #define mmio_data(s,a,p) do {
> \
> info->buffer[info->buffer_nr] = round_up(info->addr, (a));
> \
> info->addr = info->buffer[info->buffer_nr++] + (s);
> \
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
> b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
> index 05ec09c88517..442857c5c120 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
> @@ -298,7 +298,7 @@ nve4_graph_init(struct
[PATCH 10/12] drm/nouveau/graph: add GK20A support
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
.../gpu/drm/nouveau/core/engine/graph/ctxnve4.c| 4 +-
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | 9 +++
drivers/gpu/drm/nouveau/core/engine/graph/nve4.c | 2 +-
drivers/gpu/drm/nouveau/core/engine/graph/nvea.c | 75 ++
.../gpu/drm/nouveau/core/include/engine/graph.h| 1 +
6 files changed, 89 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 708d2e33835f..032a4744f843 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -270,6 +270,7 @@ nouveau-y += core/engine/graph/nvc8.o
nouveau-y += core/engine/graph/nvd7.o
nouveau-y += core/engine/graph/nvd9.o
nouveau-y += core/engine/graph/nve4.o
+nouveau-y += core/engine/graph/nvea.o
nouveau-y += core/engine/graph/nvf0.o
nouveau-y += core/engine/graph/nv108.o
nouveau-y += core/engine/mpeg/nv31.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
index e2de73ee5eee..3904073f860d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -804,7 +804,7 @@ nve4_grctx_init_unk[] = {
{}
};
-static void
+void
nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
u32 magic[GPC_MAX][2];
@@ -962,7 +962,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv,
struct nvc0_grctx *info)
nv_mask(priv, 0x41be10, 0x0080, 0x0080);
}
-static struct nvc0_graph_init *
+struct nvc0_graph_init *
nve4_grctx_init_hub[] = {
nvc0_grctx_init_base,
nve4_grctx_init_unk40xx,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index b0ab6de270b2..904f09b540c5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -221,6 +221,8 @@ void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
+void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
+
extern struct nouveau_oclass *nvc0_grctx_oclass;
extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
extern struct nvc0_graph_init nvc0_grctx_init_base[];
@@ -237,12 +239,17 @@ extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
+extern struct nvc0_graph_init nve4_grctx_init_icmd[];
+
+extern struct nvc0_graph_init *nve4_grctx_init_hub[];
+extern struct nvc0_graph_init *nve4_grctx_init_gpc[];
extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
extern struct nvc0_graph_init nvc0_grctx_init_902d[];
extern struct nvc0_graph_init nvc0_grctx_init_9039[];
extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
+extern struct nvc0_graph_init nve4_grctx_init_a097[];
void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
@@ -277,6 +284,8 @@ extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[];
extern struct nouveau_oclass *nv108_grctx_oclass;
+extern struct nvc0_graph_init *nve4_graph_init_mmio[];
+
#define mmio_data(s,a,p) do {
\
info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \
info->addr = info->buffer[info->buffer_nr++] + (s);\
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
index 05ec09c88517..442857c5c120 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
@@ -298,7 +298,7 @@ nve4_graph_init(struct nouveau_object *object)
return nvc0_graph_init_ctxctl(priv);
}
-static struct nvc0_graph_init *
+struct nvc0_graph_init *
nve4_graph_init_mmio[] = {
nve4_graph_init_regs,
nvc0_graph_init_unk40xx,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
b/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
new file mode 100644
index ..d5e6a1adcacb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of
