Re: [PATCH 12/17] drm/msm/dpu: add support of new peripheral flush mechanism

2024-02-08 Thread Paloma Arellano 



On 1/27/2024 9:42 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:41, Paloma Arellano  wrote:


On 1/25/2024 1:49 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

From: Kuogee Hsieh 

Introduce a peripheral flushing mechanism to decouple peripheral
metadata flushing from timing engine related flush.

Signed-off-by: Kuogee Hsieh 
Signed-off-by: Paloma Arellano 
---
   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c|  3 +++
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 17 +
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 10 ++
   3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce9..e284bf448bdda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -437,6 +437,9 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
   if (ctl->ops.update_pending_flush_merge_3d &&
phys_enc->hw_pp->merge_3d)
   ctl->ops.update_pending_flush_merge_3d(ctl,
phys_enc->hw_pp->merge_3d->idx);
   +if (ctl->ops.update_pending_flush_periph &&
phys_enc->hw_intf->cap->type == INTF_DP)
+ctl->ops.update_pending_flush_periph(ctl,
phys_enc->hw_intf->idx);
+
   skip_flush:
   DPU_DEBUG_VIDENC(phys_enc,
   "update pending flush ctl %d intf %d\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index e76565c3e6a43..bf45afeb616d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -39,6 +39,7 @@
   #define   CTL_WB_FLUSH  0x108
   #define   CTL_INTF_FLUSH0x110
   #define   CTL_CDM_FLUSH0x114
+#define   CTL_PERIPH_FLUSH  0x128
   #define   CTL_INTF_MASTER   0x134
   #define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
   @@ -49,6 +50,7 @@
   #define  MERGE_3D_IDX   23
   #define  DSC_IDX22
   #define CDM_IDX 26
+#define  PERIPH_IDX 30
   #define  INTF_IDX   31
   #define WB_IDX  16
   #define  DSPP_IDX   29  /* From DPU hw rev 7.x.x */
@@ -151,6 +153,10 @@ static inline void
dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
   ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
   }
   +if (ctx->pending_flush_mask & BIT(PERIPH_IDX))
+DPU_REG_WRITE(>hw, CTL_PERIPH_FLUSH,
+  ctx->pending_periph_flush_mask);
+
   if (ctx->pending_flush_mask & BIT(DSC_IDX))
   DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
 ctx->pending_dsc_flush_mask);
@@ -311,6 +317,13 @@ static void
dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,
   ctx->pending_flush_mask |= BIT(INTF_IDX);
   }
   +static void dpu_hw_ctl_update_pending_flush_periph(struct
dpu_hw_ctl *ctx,
+enum dpu_intf intf)

I assume this is _v1.
Also the argument is misaligned.

Ack.


I noticed that the placement of the 'enum dpu_intf intf' argument aligns 
with the other dpu_hw_ctl_update_pending_flush_* functions argument 
position. Is this alright, or should I align the argument with the first 
parentheses?




+{
+ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
+ctx->pending_flush_mask |= BIT(PERIPH_IDX);
+}
+
   static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct
dpu_hw_ctl *ctx,
   enum dpu_merge_3d merge_3d)
   {
@@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops
*ops,
   ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
   ops->update_pending_flush_intf =
   dpu_hw_ctl_update_pending_flush_intf_v1;
+
+ops->update_pending_flush_periph =
+dpu_hw_ctl_update_pending_flush_periph;
+
   ops->update_pending_flush_merge_3d =
   dpu_hw_ctl_update_pending_flush_merge_3d_v1;
   ops->update_pending_flush_wb =
dpu_hw_ctl_update_pending_flush_wb_v1;

What about the pre-active platforms?

Pre-active does not need a peripheral flush.

Ack.


diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index ff85b5ee0acf8..5d86c560b6d3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops {
   void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
   enum dpu_intf blk);
   +/**
+ * OR in the given flushbits to the cached
pending_(periph_)flush_mask
+ * No effect on hardware
+ * @ctx   : ctl path ctx pointer
+ * @blk   : interface block index
+ */
+void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
+enum dpu_intf blk);
+
   /**
* OR in the given flushbits to the cached
pending_(merge_3d_)flush_mask
* No effect on hardware
@@ -264,6

Re: [PATCH 12/17] drm/msm/dpu: add support of new peripheral flush mechanism

2024-01-27 Thread Dmitry Baryshkov 
On Sun, 28 Jan 2024 at 07:41, Paloma Arellano  wrote:
>
>
> On 1/25/2024 1:49 PM, Dmitry Baryshkov wrote:
> > On 25/01/2024 21:38, Paloma Arellano wrote:
> >> From: Kuogee Hsieh 
> >>
> >> Introduce a peripheral flushing mechanism to decouple peripheral
> >> metadata flushing from timing engine related flush.
> >>
> >> Signed-off-by: Kuogee Hsieh 
> >> Signed-off-by: Paloma Arellano 
> >> ---
> >>   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c|  3 +++
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 17 +
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 10 ++
> >>   3 files changed, 30 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> index d0f56c5c4cce9..e284bf448bdda 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> @@ -437,6 +437,9 @@ static void dpu_encoder_phys_vid_enable(struct
> >> dpu_encoder_phys *phys_enc)
> >>   if (ctl->ops.update_pending_flush_merge_3d &&
> >> phys_enc->hw_pp->merge_3d)
> >>   ctl->ops.update_pending_flush_merge_3d(ctl,
> >> phys_enc->hw_pp->merge_3d->idx);
> >>   +if (ctl->ops.update_pending_flush_periph &&
> >> phys_enc->hw_intf->cap->type == INTF_DP)
> >> +ctl->ops.update_pending_flush_periph(ctl,
> >> phys_enc->hw_intf->idx);
> >> +
> >>   skip_flush:
> >>   DPU_DEBUG_VIDENC(phys_enc,
> >>   "update pending flush ctl %d intf %d\n",
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >> index e76565c3e6a43..bf45afeb616d3 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> >> @@ -39,6 +39,7 @@
> >>   #define   CTL_WB_FLUSH  0x108
> >>   #define   CTL_INTF_FLUSH0x110
> >>   #define   CTL_CDM_FLUSH0x114
> >> +#define   CTL_PERIPH_FLUSH  0x128
> >>   #define   CTL_INTF_MASTER   0x134
> >>   #define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
> >>   @@ -49,6 +50,7 @@
> >>   #define  MERGE_3D_IDX   23
> >>   #define  DSC_IDX22
> >>   #define CDM_IDX 26
> >> +#define  PERIPH_IDX 30
> >>   #define  INTF_IDX   31
> >>   #define WB_IDX  16
> >>   #define  DSPP_IDX   29  /* From DPU hw rev 7.x.x */
> >> @@ -151,6 +153,10 @@ static inline void
> >> dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> >>   ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
> >>   }
> >>   +if (ctx->pending_flush_mask & BIT(PERIPH_IDX))
> >> +DPU_REG_WRITE(>hw, CTL_PERIPH_FLUSH,
> >> +  ctx->pending_periph_flush_mask);
> >> +
> >>   if (ctx->pending_flush_mask & BIT(DSC_IDX))
> >>   DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
> >> ctx->pending_dsc_flush_mask);
> >> @@ -311,6 +317,13 @@ static void
> >> dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,
> >>   ctx->pending_flush_mask |= BIT(INTF_IDX);
> >>   }
> >>   +static void dpu_hw_ctl_update_pending_flush_periph(struct
> >> dpu_hw_ctl *ctx,
> >> +enum dpu_intf intf)
> >
> > I assume this is _v1.
> > Also the argument is misaligned.
> Ack.
> >
> >> +{
> >> +ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
> >> +ctx->pending_flush_mask |= BIT(PERIPH_IDX);
> >> +}
> >> +
> >>   static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct
> >> dpu_hw_ctl *ctx,
> >>   enum dpu_merge_3d merge_3d)
> >>   {
> >> @@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops
> >> *ops,
> >>   ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
> >>   ops->update_pending_flush_intf =
> >>   dpu_hw_ctl_update_pending_flush_intf_v1;
> >> +
> >> +ops->update_pending_flush_periph =
> >> +dpu_hw_ctl_update_pending_flush_periph;
> >> +
> >>   ops->update_pending_flush_merge_3d =
> >>   dpu_hw_ctl_update_pending_flush_merge_3d_v1;
> >>   ops->update_pending_flush_wb =
> >> dpu_hw_ctl_update_pending_flush_wb_v1;
> >
> > What about the pre-active platforms?
> Pre-active does not need a peripheral flush.

Ack.

> >
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> >> index ff85b5ee0acf8..5d86c560b6d3f 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> >> @@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops {
> >>   void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
> >>   enum dpu_intf blk);
> >>   +/**
> >> + * OR in the given flushbits to the cached
> >> pending_(periph_)flush_mask
> >> + * No effect on hardware
> >> + * @ctx   : ctl path ctx pointer
> >> + * @blk   : interface block index
> >> +

Re: [PATCH 12/17] drm/msm/dpu: add support of new peripheral flush mechanism

2024-01-27 Thread Paloma Arellano 



On 1/25/2024 1:49 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

From: Kuogee Hsieh 

Introduce a peripheral flushing mechanism to decouple peripheral
metadata flushing from timing engine related flush.

Signed-off-by: Kuogee Hsieh 
Signed-off-by: Paloma Arellano 
---
  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c    |  3 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 17 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 10 ++
  3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

index d0f56c5c4cce9..e284bf448bdda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -437,6 +437,9 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
  if (ctl->ops.update_pending_flush_merge_3d && 
phys_enc->hw_pp->merge_3d)
  ctl->ops.update_pending_flush_merge_3d(ctl, 
phys_enc->hw_pp->merge_3d->idx);
  +    if (ctl->ops.update_pending_flush_periph && 
phys_enc->hw_intf->cap->type == INTF_DP)
+    ctl->ops.update_pending_flush_periph(ctl, 
phys_enc->hw_intf->idx);

+
  skip_flush:
  DPU_DEBUG_VIDENC(phys_enc,
  "update pending flush ctl %d intf %d\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

index e76565c3e6a43..bf45afeb616d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -39,6 +39,7 @@
  #define   CTL_WB_FLUSH  0x108
  #define   CTL_INTF_FLUSH    0x110
  #define   CTL_CDM_FLUSH    0x114
+#define   CTL_PERIPH_FLUSH  0x128
  #define   CTL_INTF_MASTER   0x134
  #define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
  @@ -49,6 +50,7 @@
  #define  MERGE_3D_IDX   23
  #define  DSC_IDX    22
  #define CDM_IDX 26
+#define  PERIPH_IDX 30
  #define  INTF_IDX   31
  #define WB_IDX  16
  #define  DSPP_IDX   29  /* From DPU hw rev 7.x.x */
@@ -151,6 +153,10 @@ static inline void 
dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)

  ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
  }
  +    if (ctx->pending_flush_mask & BIT(PERIPH_IDX))
+    DPU_REG_WRITE(>hw, CTL_PERIPH_FLUSH,
+  ctx->pending_periph_flush_mask);
+
  if (ctx->pending_flush_mask & BIT(DSC_IDX))
  DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
    ctx->pending_dsc_flush_mask);
@@ -311,6 +317,13 @@ static void 
dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,

  ctx->pending_flush_mask |= BIT(INTF_IDX);
  }
  +static void dpu_hw_ctl_update_pending_flush_periph(struct 
dpu_hw_ctl *ctx,

+    enum dpu_intf intf)


I assume this is _v1.
Also the argument is misaligned.

Ack.



+{
+    ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
+    ctx->pending_flush_mask |= BIT(PERIPH_IDX);
+}
+
  static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct 
dpu_hw_ctl *ctx,

  enum dpu_merge_3d merge_3d)
  {
@@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops 
*ops,

  ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
  ops->update_pending_flush_intf =
  dpu_hw_ctl_update_pending_flush_intf_v1;
+
+    ops->update_pending_flush_periph =
+    dpu_hw_ctl_update_pending_flush_periph;
+
  ops->update_pending_flush_merge_3d =
  dpu_hw_ctl_update_pending_flush_merge_3d_v1;
  ops->update_pending_flush_wb = 
dpu_hw_ctl_update_pending_flush_wb_v1;


What about the pre-active platforms?

Pre-active does not need a peripheral flush.


diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

index ff85b5ee0acf8..5d86c560b6d3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops {
  void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
  enum dpu_intf blk);
  +    /**
+ * OR in the given flushbits to the cached 
pending_(periph_)flush_mask

+ * No effect on hardware
+ * @ctx   : ctl path ctx pointer
+ * @blk   : interface block index
+ */
+    void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
+    enum dpu_intf blk);
+
  /**
   * OR in the given flushbits to the cached 
pending_(merge_3d_)flush_mask

   * No effect on hardware
@@ -264,6 +273,7 @@ struct dpu_hw_ctl {
  u32 pending_flush_mask;
  u32 pending_intf_flush_mask;
  u32 pending_wb_flush_mask;
+    u32 pending_periph_flush_mask;
  u32 pending_merge_3d_flush_mask;
  u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
  u32 pending_dsc_flush_mask;

Re: [PATCH 12/17] drm/msm/dpu: add support of new peripheral flush mechanism

2024-01-25 Thread Dmitry Baryshkov 

On 25/01/2024 21:38, Paloma Arellano wrote:

From: Kuogee Hsieh 

Introduce a peripheral flushing mechanism to decouple peripheral
metadata flushing from timing engine related flush.

Signed-off-by: Kuogee Hsieh 
Signed-off-by: Paloma Arellano 
---
  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c|  3 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 17 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 10 ++
  3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce9..e284bf448bdda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -437,6 +437,9 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
ctl->ops.update_pending_flush_merge_3d(ctl, 
phys_enc->hw_pp->merge_3d->idx);
  
+	if (ctl->ops.update_pending_flush_periph && phys_enc->hw_intf->cap->type == INTF_DP)

+   ctl->ops.update_pending_flush_periph(ctl, 
phys_enc->hw_intf->idx);
+
  skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
"update pending flush ctl %d intf %d\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index e76565c3e6a43..bf45afeb616d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -39,6 +39,7 @@
  #define   CTL_WB_FLUSH  0x108
  #define   CTL_INTF_FLUSH0x110
  #define   CTL_CDM_FLUSH0x114
+#define   CTL_PERIPH_FLUSH  0x128
  #define   CTL_INTF_MASTER   0x134
  #define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
  
@@ -49,6 +50,7 @@

  #define  MERGE_3D_IDX   23
  #define  DSC_IDX22
  #define CDM_IDX 26
+#define  PERIPH_IDX 30
  #define  INTF_IDX   31
  #define WB_IDX  16
  #define  DSPP_IDX   29  /* From DPU hw rev 7.x.x */
@@ -151,6 +153,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct 
dpu_hw_ctl *ctx)
ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
}
  
+	if (ctx->pending_flush_mask & BIT(PERIPH_IDX))

+   DPU_REG_WRITE(>hw, CTL_PERIPH_FLUSH,
+ ctx->pending_periph_flush_mask);
+
if (ctx->pending_flush_mask & BIT(DSC_IDX))
DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
  ctx->pending_dsc_flush_mask);
@@ -311,6 +317,13 @@ static void dpu_hw_ctl_update_pending_flush_intf_v1(struct 
dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= BIT(INTF_IDX);
  }
  
+static void dpu_hw_ctl_update_pending_flush_periph(struct dpu_hw_ctl *ctx,

+   enum dpu_intf intf)


I assume this is _v1.
Also the argument is misaligned.


+{
+   ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
+   ctx->pending_flush_mask |= BIT(PERIPH_IDX);
+}
+
  static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl 
*ctx,
enum dpu_merge_3d merge_3d)
  {
@@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
ops->update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf_v1;
+
+   ops->update_pending_flush_periph =
+   dpu_hw_ctl_update_pending_flush_periph;
+
ops->update_pending_flush_merge_3d =
dpu_hw_ctl_update_pending_flush_merge_3d_v1;
ops->update_pending_flush_wb = 
dpu_hw_ctl_update_pending_flush_wb_v1;


What about the pre-active platforms?


diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index ff85b5ee0acf8..5d86c560b6d3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops {
void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
enum dpu_intf blk);
  
+	/**

+* OR in the given flushbits to the cached pending_(periph_)flush_mask
+* No effect on hardware
+* @ctx   : ctl path ctx pointer
+* @blk   : interface block index
+*/
+   void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
+   enum dpu_intf blk);
+
/**
 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
 * No effect on hardware
@@ -264,6 +273,7 @@ struct dpu_hw_ctl {
u32 pending_flush_mask;
u32 pending_intf_flush_mask;
u32 pending_wb_flush_mask;
+   u32 pending_periph_flush_mask;
u32 pending_merge_3d_flush_mask;
u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

[PATCH 12/17] drm/msm/dpu: add support of new peripheral flush mechanism

2024-01-25 Thread Paloma Arellano 
From: Kuogee Hsieh 

Introduce a peripheral flushing mechanism to decouple peripheral
metadata flushing from timing engine related flush.

Signed-off-by: Kuogee Hsieh 
Signed-off-by: Paloma Arellano 
---
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c|  3 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 17 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 10 ++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce9..e284bf448bdda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -437,6 +437,9 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
ctl->ops.update_pending_flush_merge_3d(ctl, 
phys_enc->hw_pp->merge_3d->idx);
 
+   if (ctl->ops.update_pending_flush_periph && 
phys_enc->hw_intf->cap->type == INTF_DP)
+   ctl->ops.update_pending_flush_periph(ctl, 
phys_enc->hw_intf->idx);
+
 skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
"update pending flush ctl %d intf %d\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index e76565c3e6a43..bf45afeb616d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -39,6 +39,7 @@
 #define   CTL_WB_FLUSH  0x108
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_CDM_FLUSH0x114
+#define   CTL_PERIPH_FLUSH  0x128
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
 
@@ -49,6 +50,7 @@
 #define  MERGE_3D_IDX   23
 #define  DSC_IDX22
 #define CDM_IDX 26
+#define  PERIPH_IDX 30
 #define  INTF_IDX   31
 #define WB_IDX  16
 #define  DSPP_IDX   29  /* From DPU hw rev 7.x.x */
@@ -151,6 +153,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct 
dpu_hw_ctl *ctx)
ctx->pending_dspp_flush_mask[dspp - DSPP_0]);
}
 
+   if (ctx->pending_flush_mask & BIT(PERIPH_IDX))
+   DPU_REG_WRITE(>hw, CTL_PERIPH_FLUSH,
+ ctx->pending_periph_flush_mask);
+
if (ctx->pending_flush_mask & BIT(DSC_IDX))
DPU_REG_WRITE(>hw, CTL_DSC_FLUSH,
  ctx->pending_dsc_flush_mask);
@@ -311,6 +317,13 @@ static void dpu_hw_ctl_update_pending_flush_intf_v1(struct 
dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= BIT(INTF_IDX);
 }
 
+static void dpu_hw_ctl_update_pending_flush_periph(struct dpu_hw_ctl *ctx,
+   enum dpu_intf intf)
+{
+   ctx->pending_periph_flush_mask |= BIT(intf - INTF_0);
+   ctx->pending_flush_mask |= BIT(PERIPH_IDX);
+}
+
 static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
enum dpu_merge_3d merge_3d)
 {
@@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
ops->update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf_v1;
+
+   ops->update_pending_flush_periph =
+   dpu_hw_ctl_update_pending_flush_periph;
+
ops->update_pending_flush_merge_3d =
dpu_hw_ctl_update_pending_flush_merge_3d_v1;
ops->update_pending_flush_wb = 
dpu_hw_ctl_update_pending_flush_wb_v1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index ff85b5ee0acf8..5d86c560b6d3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -122,6 +122,15 @@ struct dpu_hw_ctl_ops {
void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
enum dpu_intf blk);
 
+   /**
+* OR in the given flushbits to the cached pending_(periph_)flush_mask
+* No effect on hardware
+* @ctx   : ctl path ctx pointer
+* @blk   : interface block index
+*/
+   void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
+   enum dpu_intf blk);
+
/**
 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
 * No effect on hardware
@@ -264,6 +273,7 @@ struct dpu_hw_ctl {
u32 pending_flush_mask;
u32 pending_intf_flush_mask;
u32 pending_wb_flush_mask;
+   u32 pending_periph_flush_mask;
u32 pending_merge_3d_flush_mask;
u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
u32 pending_dsc_flush_mask;
-- 
2.39.2